diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2016-01-12 14:06:54 -0800 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2016-01-12 14:06:54 -0800 |
| commit | a57cc2c988482010061b9e68344fdf1969889763 (patch) | |
| tree | 5c050337492ce27c09b47421b123980b5a79f8d9 /platform/devices | |
initial commit, FreeRTOS_BSP_1.0.0_iMX7D
Diffstat (limited to 'platform/devices')
16 files changed, 99509 insertions, 0 deletions
diff --git a/platform/devices/MCIMX7D/include/MCIMX7D_M4.h b/platform/devices/MCIMX7D/include/MCIMX7D_M4.h new file mode 100644 index 0000000..87670aa --- /dev/null +++ b/platform/devices/MCIMX7D/include/MCIMX7D_M4.h @@ -0,0 +1,97022 @@ +/* +** ################################################################### +** Processors: MCIMX7D_M4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** GNU C Compiler - CodeSourcery Sourcery G++ +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: +** Version: rev. 1.0, 2015-04-23 +** Build: b150423 +** +** Abstract: +** CMSIS Peripheral Access Layer for iMX7D +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2015-04-23) +** Initial version by Wang Ge. +** +** ################################################################### +*/ + +/*! + * @file MCIMX7D_M4.h + * @version 1.0 + * @date 2015-04-23 + * @brief CMSIS Peripheral Access Layer for MCIMX7D_M4 + * + * CMSIS Peripheral Access Layer for MCIMX7D_M4 + */ + + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(MCIMX7D_M4_H_) /* Check if memory map has not been already included */ +#define MCIMX7D_M4_H_ +#define MCU_MCIMX7D_M4 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error MCIMX7D_M4 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include <stdint.h> + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 16 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + GPR_IRQn = 0, /**< Used to notify cores on exception condition while boot */ + DAP_IRQn = 1, /**< DAP Interrupt */ + SDMA_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */ + DBGMON_IRQn = 3, /**< DBGMON Sync Interrupt */ + SNVS_IRQn = 4, /**< WRAPPER ON-OFF button press shorter than 5 seconds (pulse event) */ + LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */ + SIM2_IRQn = 6, /**< SIM Interrupt */ + CSI_IRQn = 7, /**< CSI Interrupt */ + PXP1_IRQn = 8, /**< PXP Interrupt */ + Reserved_IRQn = 9, /**< Reserved */ + WDOG3_IRQn = 10, /**< Watchdog Timer reset */ + HS1_IRQn = 11, /**< SEMA4-HS M4 Interrupt Request */ + APBHDMA_IRQn = 12, /**< GPMI operation channel 0 description complete interrupt */ + EIM_IRQn = 13, /**< EIM Interrupt */ + BCH_IRQn = 14, /**< BCH operation complete interrupt */ + GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */ + UART6_IRQn = 16, /**< UART-6 ORed interrupt */ + FTM1_IRQn = 17, /**< Flex Timer1 Fault / Counter / Channel interrupt */ + FTM2_IRQn = 18, /**< Flex Timer2 Fault / Counter / Channel interrupt */ + SNVS_CONSOLIDATED_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ + SNVS_SECURITY_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ + CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted */ + USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ + USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ + USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */ + MIPI_CSI_IRQn = 25, /**< MIPI CSI interrupt */ + UART1_IRQn = 26, /**< UART-1 ORed interrupt */ + UART2_IRQn = 27, /**< UART-2 ORed interrupt */ + UART3_IRQn = 28, /**< UART-3 ORed interrupt */ + UART4_IRQn = 29, /**< UART-4 ORed interrupt */ + UART5_IRQn = 30, /**< UART-5 ORed interrupt */ + eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request line to the core. */ + eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request line to the core. */ + eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request line to the core. */ + eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request line to the core. */ + I2C1_IRQn = 35, /**< I2C-1 Interrupt */ + I2C2_IRQn = 36, /**< I2C-2 Interrupt */ + I2C3_IRQn = 37, /**< I2C-3 Interrupt */ + I2C4_IRQn = 38, /**< I2C-4 Interrupt */ + RDC_IRQn = 39, /**< RDC interrupt */ + USB_OH3_OTG2_1_IRQn = 40, /**< USB OH3 OTG2 */ + MIPI_DSI_IRQn = 41, /**< MIPI CSI Interrupt */ + USB_OH3_OTG2_2_IRQn = 42, /**< USB OH3 OTG2 */ + USB_OH2_OTG_IRQn = 43, /**< USB OH2 OTG */ + USB_OTG1_IRQn = 44, /**< USB OTG1 Interrupt */ + USB_OTG2_IRQn = 45, /**< USB OTG2 Interrupt */ + PXP2_IRQn = 46, /**< PXP interrupt */ + SCTR1_IRQn = 47, /**< ISO7816IP Interrupt */ + SCTR2_IRQn = 48, /**< ISO7816IP Interrupt */ + Analog_TempSensor_IRQn = 49, /**< TempSensor (Temperature low alarm). */ + SAI3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */ + Analog_brown_out_IRQn = 51, /**< Brown-out event on either analog regulators. */ + GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT15_0_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_INT31_16_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO2 signals 16 throughout 31 */ + GPIO3_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO3 signals 16 throughout 31 */ + GPIO4_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO5 signals 0 throughout 15 */ + GPIO5_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO5 signals 16 throughout 31 */ + GPIO6_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO6 signals 0 throughtout 15 */ + GPIO6_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO6 signals 16 throughtout 31 */ + GPIO7_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO7 signals 0 throughout 15 */ + GPIO7_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO7 signals 16 throughout 31 */ + WDOG1_IRQn = 78, /**< Watchdog Timer reset */ + WDOG2_IRQn = 79, /**< Watchdog Timer reset */ + KPP_IRQn = 80, /**< Keypad Interrupt */ + PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + CCM_INT1_IRQn = 85, /**< CCM, Interrupt Request 1 */ + CCM_INT2_IRQn = 86, /**< CCM, Interrupt Request 2 */ + GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ + MU_IRQn = 88, /**< Interrupt to A7 */ + SRC_IRQn = 89, /**< SRC interrupt request */ + SIM1_IRQn = 90, /**< Sim Interrupt */ + RTIC_IRQn = 91, /**< RTIC Interrupt */ + CPU_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[0]) */ + /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[1]) */ + CPU_CTI_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[0]) */ + /**< CTI trigger outputs (internal: nCTIIRQ[1]) */ + CCM_SRC_GPC_IRQn = 94, /**< SRC GPC Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */ + SAI2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ + MU_INT_M4_IRQn = 97, /**< Interrupt to M4 */ + ADC1_IRQn = 98, /**< ADC-1 Interrupt */ + ADC2_IRQn = 99, /**< ADC-2 Interrupt */ + ENET2_MAC0_TRANS1_IRQn = 100, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ + ENET2_MAC0_TRANS2_IRQn = 101, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ + ENET2_MAC0_IRQ_IRQn = 102, /**< MAC 0 IRQ */ + ENET2_1588_TIMER_IRQ_IRQn = 103, /**< MAC 0 1588 Timer Interrupt - synchronous */ + TPR_IRQn = 104, /**< IRQ TPR IRQ */ + CAAM_QUEUE_IRQn = 105, /**< WRAPPER CAAM interrupt queue for JQ */ + CAAM_ERROR_IRQn = 106, /**< WRAPPER CAAM interrupt queue for JQ */ + QSPI_IRQn = 107, /**< QSPI Interrupt */ + TZASC1_IRQn = 108, /**< TZASC (PL380) interrupt */ + WDOG4_IRQn = 109, /**< Watchdog Timer reset */ + FLEXCAN1_IRQn = 110, /**< FlexCAN1 Interrupt */ + FLEXCAN2_IRQn = 111, /**< FlexCAN2 Interrupt */ + PERFMON1_IRQn = 112, /**< General interrupt */ + PERFMON2_IRQn = 113, /**< General interrupt */ + CAAM_WRAPPER1_IRQn = 114, /**< CAAM interrupt queue for JQ */ + CAAM_WRAPPER2_IRQn = 115, /**< Recoverable error interrupt */ + HS0_IRQn = 116, /**< SEMA4-HS processor A7 Interrupt Request */ + EPDC_IRQn = 117, /**< EPDC Interrupt */ + ENET1_MAC0_TRANS1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET1_MAC0_TRANS2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET1_MAC0_IRQn = 120, /**< MAC 0 IRQ */ + ENET1_1588_TIMER_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */ + PCIE_CTRL1_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL2_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL3_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL4_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + UART7_IRQn = 126, /**< UART-7 ORed interrupt */ + PCIE_CTRL_REQUEST_IRQn = 127, /**< Channels [63:32] interrupts requests */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MCIMX7D_M4.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CH_A_CFG1; /**< Channel A configuration 1, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CH_A_CFG2; /**< Channel A configuration 2, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CH_B_CFG1; /**< , offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CH_B_CFG2; /**< Channel B Configuration 2, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH_C_CFG1; /**< Channel C Configuration 1, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CH_C_CFG2; /**< Channel C Configuration 2, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CH_D_CFG1; /**< Channel D Configuration 1, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH_D_CFG2; /**< Channel D Configuration 2, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CH_SW_CFG; /**< Channel Software Configuration, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __IO uint32_t TIMER_UNIT; /**< Timer Unit, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DMA_FIFO; /**< DMA FIFO, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t FIFO_STATUS; /**< FIFO Status, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t INT_SIG_EN; /**< , offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t INT_STATUS; /**< , offset: 0xE0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CHA_B_CNV_RSLT; /**< Channel A and B Conversion Result, offset: 0xF0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CHC_D_CNV_RSLT; /**< Channel C and D Conversion Result, offset: 0x100 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH_SW_CNV_RSLT; /**< Channel Software Conversion Result, offset: 0x110 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA_FIFO_DAT; /**< DMA FIFO Data, offset: 0x120 */ + uint8_t RESERVED_18[12]; + __IO uint32_t ADC_CFG; /**< ADC Configuration, offset: 0x130 */ +} ADC_Type, *ADC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + + +/* ADC - Register accessors */ +#define ADC_CH_A_CFG1_REG(base) ((base)->CH_A_CFG1) +#define ADC_CH_A_CFG2_REG(base) ((base)->CH_A_CFG2) +#define ADC_CH_B_CFG1_REG(base) ((base)->CH_B_CFG1) +#define ADC_CH_B_CFG2_REG(base) ((base)->CH_B_CFG2) +#define ADC_CH_C_CFG1_REG(base) ((base)->CH_C_CFG1) +#define ADC_CH_C_CFG2_REG(base) ((base)->CH_C_CFG2) +#define ADC_CH_D_CFG1_REG(base) ((base)->CH_D_CFG1) +#define ADC_CH_D_CFG2_REG(base) ((base)->CH_D_CFG2) +#define ADC_CH_SW_CFG_REG(base) ((base)->CH_SW_CFG) +#define ADC_TIMER_UNIT_REG(base) ((base)->TIMER_UNIT) +#define ADC_DMA_FIFO_REG(base) ((base)->DMA_FIFO) +#define ADC_FIFO_STATUS_REG(base) ((base)->FIFO_STATUS) +#define ADC_INT_SIG_EN_REG(base) ((base)->INT_SIG_EN) +#define ADC_INT_EN_REG(base) ((base)->INT_EN) +#define ADC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define ADC_CHA_B_CNV_RSLT_REG(base) ((base)->CHA_B_CNV_RSLT) +#define ADC_CHC_D_CNV_RSLT_REG(base) ((base)->CHC_D_CNV_RSLT) +#define ADC_CH_SW_CNV_RSLT_REG(base) ((base)->CH_SW_CNV_RSLT) +#define ADC_DMA_FIFO_DAT_REG(base) ((base)->DMA_FIFO_DAT) +#define ADC_ADC_CFG_REG(base) ((base)->ADC_CFG) + +/*! + * @} + */ /* end of group ADC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* CH_A_CFG1 Bit Fields */ +#define ADC_CH_A_CFG1_CHA_TIMER_MASK 0xFFFFFFu +#define ADC_CH_A_CFG1_CHA_TIMER_SHIFT 0 +#define ADC_CH_A_CFG1_CHA_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG1_CHA_TIMER_SHIFT))&ADC_CH_A_CFG1_CHA_TIMER_MASK) +#define ADC_CH_A_CFG1_CHA_SEL_MASK 0xF000000u +#define ADC_CH_A_CFG1_CHA_SEL_SHIFT 24 +#define ADC_CH_A_CFG1_CHA_SEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG1_CHA_SEL_SHIFT))&ADC_CH_A_CFG1_CHA_SEL_MASK) +#define ADC_CH_A_CFG1_CHA_AVG_EN_MASK 0x20000000u +#define ADC_CH_A_CFG1_CHA_AVG_EN_SHIFT 29 +#define ADC_CH_A_CFG1_CHA_SINGLE_MASK 0x40000000u +#define ADC_CH_A_CFG1_CHA_SINGLE_SHIFT 30 +#define ADC_CH_A_CFG1_CHA_EN_MASK 0x80000000u +#define ADC_CH_A_CFG1_CHA_EN_SHIFT 31 +/* CH_A_CFG2 Bit Fields */ +#define ADC_CH_A_CFG2_CHA_LOW_THRES_MASK 0xFFFu +#define ADC_CH_A_CFG2_CHA_LOW_THRES_SHIFT 0 +#define ADC_CH_A_CFG2_CHA_LOW_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_LOW_THRES_SHIFT))&ADC_CH_A_CFG2_CHA_LOW_THRES_MASK) +#define ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK 0x3000u +#define ADC_CH_A_CFG2_CHA_AVG_NUMBER_SHIFT 12 +#define ADC_CH_A_CFG2_CHA_AVG_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_AVG_NUMBER_SHIFT))&ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK) +#define ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK 0x8000u +#define ADC_CH_A_CFG2_CHA_AUTO_DIS_SHIFT 15 +#define ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK 0xFFF0000u +#define ADC_CH_A_CFG2_CHA_HIGH_THRES_SHIFT 16 +#define ADC_CH_A_CFG2_CHA_HIGH_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_HIGH_THRES_SHIFT))&ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK) +#define ADC_CH_A_CFG2_CHA_CMP_MODE_MASK 0xE0000000u +#define ADC_CH_A_CFG2_CHA_CMP_MODE_SHIFT 29 +#define ADC_CH_A_CFG2_CHA_CMP_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_A_CFG2_CHA_CMP_MODE_SHIFT))&ADC_CH_A_CFG2_CHA_CMP_MODE_MASK) +/* CH_B_CFG1 Bit Fields */ +#define ADC_CH_B_CFG1_CHB_TIMER_MASK 0xFFFFFFu +#define ADC_CH_B_CFG1_CHB_TIMER_SHIFT 0 +#define ADC_CH_B_CFG1_CHB_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG1_CHB_TIMER_SHIFT))&ADC_CH_B_CFG1_CHB_TIMER_MASK) +#define ADC_CH_B_CFG1_CHB_SEL_MASK 0xF000000u +#define ADC_CH_B_CFG1_CHB_SEL_SHIFT 24 +#define ADC_CH_B_CFG1_CHB_SEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG1_CHB_SEL_SHIFT))&ADC_CH_B_CFG1_CHB_SEL_MASK) +#define ADC_CH_B_CFG1_CHB_AVG_EN_MASK 0x20000000u +#define ADC_CH_B_CFG1_CHB_AVG_EN_SHIFT 29 +#define ADC_CH_B_CFG1_CHB_SINGLE_MASK 0x40000000u +#define ADC_CH_B_CFG1_CHB_SINGLE_SHIFT 30 +#define ADC_CH_B_CFG1_CHB_EN_MASK 0x80000000u +#define ADC_CH_B_CFG1_CHB_EN_SHIFT 31 +/* CH_B_CFG2 Bit Fields */ +#define ADC_CH_B_CFG2_CHB_LOW_THRES_MASK 0xFFFu +#define ADC_CH_B_CFG2_CHB_LOW_THRES_SHIFT 0 +#define ADC_CH_B_CFG2_CHB_LOW_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_LOW_THRES_SHIFT))&ADC_CH_B_CFG2_CHB_LOW_THRES_MASK) +#define ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK 0x3000u +#define ADC_CH_B_CFG2_CHB_AVG_NUMBER_SHIFT 12 +#define ADC_CH_B_CFG2_CHB_AVG_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_AVG_NUMBER_SHIFT))&ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK) +#define ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK 0x8000u +#define ADC_CH_B_CFG2_CHB_AUTO_DIS_SHIFT 15 +#define ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK 0xFFF0000u +#define ADC_CH_B_CFG2_CHB_HIGH_THRES_SHIFT 16 +#define ADC_CH_B_CFG2_CHB_HIGH_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_HIGH_THRES_SHIFT))&ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK) +#define ADC_CH_B_CFG2_CHB_CMP_MODE_MASK 0xE0000000u +#define ADC_CH_B_CFG2_CHB_CMP_MODE_SHIFT 29 +#define ADC_CH_B_CFG2_CHB_CMP_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_B_CFG2_CHB_CMP_MODE_SHIFT))&ADC_CH_B_CFG2_CHB_CMP_MODE_MASK) +/* CH_C_CFG1 Bit Fields */ +#define ADC_CH_C_CFG1_CHC_TIMER_MASK 0xFFFFFFu +#define ADC_CH_C_CFG1_CHC_TIMER_SHIFT 0 +#define ADC_CH_C_CFG1_CHC_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG1_CHC_TIMER_SHIFT))&ADC_CH_C_CFG1_CHC_TIMER_MASK) +#define ADC_CH_C_CFG1_CHC_SEL_MASK 0xF000000u +#define ADC_CH_C_CFG1_CHC_SEL_SHIFT 24 +#define ADC_CH_C_CFG1_CHC_SEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG1_CHC_SEL_SHIFT))&ADC_CH_C_CFG1_CHC_SEL_MASK) +#define ADC_CH_C_CFG1_CHC_AVG_EN_MASK 0x20000000u +#define ADC_CH_C_CFG1_CHC_AVG_EN_SHIFT 29 +#define ADC_CH_C_CFG1_CHC_SINGLE_MASK 0x40000000u +#define ADC_CH_C_CFG1_CHC_SINGLE_SHIFT 30 +#define ADC_CH_C_CFG1_CHC_EN_MASK 0x80000000u +#define ADC_CH_C_CFG1_CHC_EN_SHIFT 31 +/* CH_C_CFG2 Bit Fields */ +#define ADC_CH_C_CFG2_CHC_LOW_THRES_MASK 0xFFFu +#define ADC_CH_C_CFG2_CHC_LOW_THRES_SHIFT 0 +#define ADC_CH_C_CFG2_CHC_LOW_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_LOW_THRES_SHIFT))&ADC_CH_C_CFG2_CHC_LOW_THRES_MASK) +#define ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK 0x3000u +#define ADC_CH_C_CFG2_CHC_AVG_NUMBER_SHIFT 12 +#define ADC_CH_C_CFG2_CHC_AVG_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_AVG_NUMBER_SHIFT))&ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK) +#define ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK 0x8000u +#define ADC_CH_C_CFG2_CHC_AUTO_DIS_SHIFT 15 +#define ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK 0xFFF0000u +#define ADC_CH_C_CFG2_CHC_HIGH_THRES_SHIFT 16 +#define ADC_CH_C_CFG2_CHC_HIGH_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_HIGH_THRES_SHIFT))&ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK) +#define ADC_CH_C_CFG2_CHC_CMP_MODE_MASK 0xE0000000u +#define ADC_CH_C_CFG2_CHC_CMP_MODE_SHIFT 29 +#define ADC_CH_C_CFG2_CHC_CMP_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_C_CFG2_CHC_CMP_MODE_SHIFT))&ADC_CH_C_CFG2_CHC_CMP_MODE_MASK) +/* CH_D_CFG1 Bit Fields */ +#define ADC_CH_D_CFG1_CHD_TIMER_MASK 0xFFFFFFu +#define ADC_CH_D_CFG1_CHD_TIMER_SHIFT 0 +#define ADC_CH_D_CFG1_CHD_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG1_CHD_TIMER_SHIFT))&ADC_CH_D_CFG1_CHD_TIMER_MASK) +#define ADC_CH_D_CFG1_CHD_SEL_MASK 0xF000000u +#define ADC_CH_D_CFG1_CHD_SEL_SHIFT 24 +#define ADC_CH_D_CFG1_CHD_SEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG1_CHD_SEL_SHIFT))&ADC_CH_D_CFG1_CHD_SEL_MASK) +#define ADC_CH_D_CFG1_CHD_AVG_EN_MASK 0x20000000u +#define ADC_CH_D_CFG1_CHD_AVG_EN_SHIFT 29 +#define ADC_CH_D_CFG1_CHD_SINGLE_MASK 0x40000000u +#define ADC_CH_D_CFG1_CHD_SINGLE_SHIFT 30 +#define ADC_CH_D_CFG1_CHD_EN_MASK 0x80000000u +#define ADC_CH_D_CFG1_CHD_EN_SHIFT 31 +/* CH_D_CFG2 Bit Fields */ +#define ADC_CH_D_CFG2_CHD_LOW_THRES_MASK 0xFFFu +#define ADC_CH_D_CFG2_CHD_LOW_THRES_SHIFT 0 +#define ADC_CH_D_CFG2_CHD_LOW_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_LOW_THRES_SHIFT))&ADC_CH_D_CFG2_CHD_LOW_THRES_MASK) +#define ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK 0x3000u +#define ADC_CH_D_CFG2_CHD_AVG_NUMBER_SHIFT 12 +#define ADC_CH_D_CFG2_CHD_AVG_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_AVG_NUMBER_SHIFT))&ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK) +#define ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK 0x8000u +#define ADC_CH_D_CFG2_CHD_AUTO_DIS_SHIFT 15 +#define ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK 0xFFF0000u +#define ADC_CH_D_CFG2_CHD_HIGH_THRES_SHIFT 16 +#define ADC_CH_D_CFG2_CHD_HIGH_THRES(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_HIGH_THRES_SHIFT))&ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK) +#define ADC_CH_D_CFG2_CHD_CMP_MODE_MASK 0xE0000000u +#define ADC_CH_D_CFG2_CHD_CMP_MODE_SHIFT 29 +#define ADC_CH_D_CFG2_CHD_CMP_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_D_CFG2_CHD_CMP_MODE_SHIFT))&ADC_CH_D_CFG2_CHD_CMP_MODE_MASK) +/* CH_SW_CFG Bit Fields */ +#define ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK 0x600000u +#define ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_SHIFT 21 +#define ADC_CH_SW_CFG_CH_SW_AVG_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_SHIFT))&ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK) +#define ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK 0x800000u +#define ADC_CH_SW_CFG_CH_SW_AVG_EN_SHIFT 23 +#define ADC_CH_SW_CFG_CH_SW_SEL_MASK 0xF000000u +#define ADC_CH_SW_CFG_CH_SW_SEL_SHIFT 24 +#define ADC_CH_SW_CFG_CH_SW_SEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_SW_CFG_CH_SW_SEL_SHIFT))&ADC_CH_SW_CFG_CH_SW_SEL_MASK) +#define ADC_CH_SW_CFG_START_CONV_MASK 0x80000000u +#define ADC_CH_SW_CFG_START_CONV_SHIFT 31 +/* TIMER_UNIT Bit Fields */ +#define ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK 0x1Fu +#define ADC_TIMER_UNIT_CORE_TIMER_UNIT_SHIFT 0 +#define ADC_TIMER_UNIT_CORE_TIMER_UNIT(x) (((uint32_t)(((uint32_t)(x))<<ADC_TIMER_UNIT_CORE_TIMER_UNIT_SHIFT))&ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK) +#define ADC_TIMER_UNIT_PRE_DIV_MASK 0xE0000000u +#define ADC_TIMER_UNIT_PRE_DIV_SHIFT 29 +#define ADC_TIMER_UNIT_PRE_DIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_TIMER_UNIT_PRE_DIV_SHIFT))&ADC_TIMER_UNIT_PRE_DIV_MASK) +/* DMA_FIFO Bit Fields */ +#define ADC_DMA_FIFO_DMA_WM_LVL_MASK 0x1Fu +#define ADC_DMA_FIFO_DMA_WM_LVL_SHIFT 0 +#define ADC_DMA_FIFO_DMA_WM_LVL(x) (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DMA_WM_LVL_SHIFT))&ADC_DMA_FIFO_DMA_WM_LVL_MASK) +#define ADC_DMA_FIFO_DMA_CH_SEL_MASK 0x60u +#define ADC_DMA_FIFO_DMA_CH_SEL_SHIFT 5 +#define ADC_DMA_FIFO_DMA_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DMA_CH_SEL_SHIFT))&ADC_DMA_FIFO_DMA_CH_SEL_MASK) +#define ADC_DMA_FIFO_DMA_EN_MASK 0x80u +#define ADC_DMA_FIFO_DMA_EN_SHIFT 7 +#define ADC_DMA_FIFO_DMA_FIFO_EN_MASK 0x100u +#define ADC_DMA_FIFO_DMA_FIFO_EN_SHIFT 8 +#define ADC_DMA_FIFO_DMA_RST_MASK 0x200u +#define ADC_DMA_FIFO_DMA_RST_SHIFT 9 +/* FIFO_STATUS Bit Fields */ +#define ADC_FIFO_STATUS_FIFO_ENTRIES_MASK 0x3Fu +#define ADC_FIFO_STATUS_FIFO_ENTRIES_SHIFT 0 +#define ADC_FIFO_STATUS_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x))<<ADC_FIFO_STATUS_FIFO_ENTRIES_SHIFT))&ADC_FIFO_STATUS_FIFO_ENTRIES_MASK) +#define ADC_FIFO_STATUS_FIFO_EMPTY_MASK 0x100u +#define ADC_FIFO_STATUS_FIFO_EMPTY_SHIFT 8 +#define ADC_FIFO_STATUS_FIFO_FULL_MASK 0x200u +#define ADC_FIFO_STATUS_FIFO_FULL_SHIFT 9 +/* INT_SIG_EN Bit Fields */ +#define ADC_INT_SIG_EN_CHA_CMP_INT_SIG_EN_MASK 0x1u +#define ADC_INT_SIG_EN_CHA_CMP_INT_SIG_EN_SHIFT 0 +#define ADC_INT_SIG_EN_CHB_CMP_INT_SIG_EN_MASK 0x2u +#define ADC_INT_SIG_EN_CHB_CMP_INT_SIG_EN_SHIFT 1 +#define ADC_INT_SIG_EN_CHC_CMP_INT_SIG_EN_MASK 0x4u +#define ADC_INT_SIG_EN_CHC_CMP_INT_SIG_EN_SHIFT 2 +#define ADC_INT_SIG_EN_CHD_CMP_INT_SIG_EN_MASK 0x8u +#define ADC_INT_SIG_EN_CHD_CMP_INT_SIG_EN_SHIFT 3 +#define ADC_INT_SIG_EN_DMA_REACH_WM_INT_SIG_EN_MASK 0x20u +#define ADC_INT_SIG_EN_DMA_REACH_WM_INT_SIG_EN_SHIFT 5 +#define ADC_INT_SIG_EN_FIFO_UNDERRUN_INT_SIG_EN_MASK 0x40u +#define ADC_INT_SIG_EN_FIFO_UNDERRUN_INT_SIG_EN_SHIFT 6 +#define ADC_INT_SIG_EN_FIFO_OVRRUN_INT_SIG_EN_MASK 0x80u +#define ADC_INT_SIG_EN_FIFO_OVRRUN_INT_SIG_EN_SHIFT 7 +#define ADC_INT_SIG_EN_CHA_COV_INT_SIG_EN_MASK 0x100u +#define ADC_INT_SIG_EN_CHA_COV_INT_SIG_EN_SHIFT 8 +#define ADC_INT_SIG_EN_CHB_COV_INT_SIG_EN_MASK 0x200u +#define ADC_INT_SIG_EN_CHB_COV_INT_SIG_EN_SHIFT 9 +#define ADC_INT_SIG_EN_CHC_COV_INT_SIG_EN_MASK 0x400u +#define ADC_INT_SIG_EN_CHC_COV_INT_SIG_EN_SHIFT 10 +#define ADC_INT_SIG_EN_CHD_COV_INT_SIG_EN_MASK 0x800u +#define ADC_INT_SIG_EN_CHD_COV_INT_SIG_EN_SHIFT 11 +#define ADC_INT_SIG_EN_SW_CH_COV_INT_SIG_EN_MASK 0x1000u +#define ADC_INT_SIG_EN_SW_CH_COV_INT_SIG_EN_SHIFT 12 +#define ADC_INT_SIG_EN_CHA_COV_TO_INT_SIG_EN_MASK 0x10000u +#define ADC_INT_SIG_EN_CHA_COV_TO_INT_SIG_EN_SHIFT 16 +#define ADC_INT_SIG_EN_CHB_COV_TO_INT_SIG_EN_MASK 0x20000u +#define ADC_INT_SIG_EN_CHB_COV_TO_INT_SIG_EN_SHIFT 17 +#define ADC_INT_SIG_EN_CHC_COV_TO_INT_SIG_EN_MASK 0x40000u +#define ADC_INT_SIG_EN_CHC_COV_TO_INT_SIG_EN_SHIFT 18 +#define ADC_INT_SIG_EN_CHD_COV_TO_INT_SIG_EN_MASK 0x80000u +#define ADC_INT_SIG_EN_CHD_COV_TO_INT_SIG_EN_SHIFT 19 +#define ADC_INT_SIG_EN_SW_CH_COV_TO_INT_SIG_EN_MASK 0x100000u +#define ADC_INT_SIG_EN_SW_CH_COV_TO_INT_SIG_EN_SHIFT 20 +#define ADC_INT_SIG_EN_LAST_FIFO_DATA_READ_SIG_EN_MASK 0x200000u +#define ADC_INT_SIG_EN_LAST_FIFO_DATA_READ_SIG_EN_SHIFT 21 +/* INT_EN Bit Fields */ +#define ADC_INT_EN_CHA_CMP_INT_EN_MASK 0x1u +#define ADC_INT_EN_CHA_CMP_INT_EN_SHIFT 0 +#define ADC_INT_EN_CHB_CMP_INT_EN_MASK 0x2u +#define ADC_INT_EN_CHB_CMP_INT_EN_SHIFT 1 +#define ADC_INT_EN_CHC_CMP_INT_EN_MASK 0x4u +#define ADC_INT_EN_CHC_CMP_INT_EN_SHIFT 2 +#define ADC_INT_EN_CHD_CMP_INT_EN_MASK 0x8u +#define ADC_INT_EN_CHD_CMP_INT_EN_SHIFT 3 +#define ADC_INT_EN_DMA_REACH_WM_INT_EN_MASK 0x20u +#define ADC_INT_EN_DMA_REACH_WM_INT_EN_SHIFT 5 +#define ADC_INT_EN_FIFO_UNDERRUN_INT_EN_MASK 0x40u +#define ADC_INT_EN_FIFO_UNDERRUN_INT_EN_SHIFT 6 +#define ADC_INT_EN_FIFO_OVERRUN_INT_EN_MASK 0x80u +#define ADC_INT_EN_FIFO_OVERRUN_INT_EN_SHIFT 7 +#define ADC_INT_EN_CHA_COV_INT_EN_MASK 0x100u +#define ADC_INT_EN_CHA_COV_INT_EN_SHIFT 8 +#define ADC_INT_EN_CHB_COV_INT_EN_MASK 0x200u +#define ADC_INT_EN_CHB_COV_INT_EN_SHIFT 9 +#define ADC_INT_EN_CHC_COV_INT_EN_MASK 0x400u +#define ADC_INT_EN_CHC_COV_INT_EN_SHIFT 10 +#define ADC_INT_EN_CHD_COV_INT_EN_MASK 0x800u +#define ADC_INT_EN_CHD_COV_INT_EN_SHIFT 11 +#define ADC_INT_EN_SW_CH_COV_INT_EN_MASK 0x1000u +#define ADC_INT_EN_SW_CH_COV_INT_EN_SHIFT 12 +#define ADC_INT_EN_CHA_COV_TO_INT_EN_MASK 0x10000u +#define ADC_INT_EN_CHA_COV_TO_INT_EN_SHIFT 16 +#define ADC_INT_EN_CHB_COV_TO_INT_EN_MASK 0x20000u +#define ADC_INT_EN_CHB_COV_TO_INT_EN_SHIFT 17 +#define ADC_INT_EN_CHC_COV_TO_INT_EN_MASK 0x40000u +#define ADC_INT_EN_CHC_COV_TO_INT_EN_SHIFT 18 +#define ADC_INT_EN_CHD_COV_TO_INT_EN_MASK 0x80000u +#define ADC_INT_EN_CHD_COV_TO_INT_EN_SHIFT 19 +#define ADC_INT_EN_SW_CH_COV_TO_INT_EN_MASK 0x100000u +#define ADC_INT_EN_SW_CH_COV_TO_INT_EN_SHIFT 20 +#define ADC_INT_EN_LAST_FIFO_DATA_READ_EN_MASK 0x200000u +#define ADC_INT_EN_LAST_FIFO_DATA_READ_EN_SHIFT 21 +/* INT_STATUS Bit Fields */ +#define ADC_INT_STATUS_CHA_CMP_MASK 0x1u +#define ADC_INT_STATUS_CHA_CMP_SHIFT 0 +#define ADC_INT_STATUS_CHB_CMP_MASK 0x2u +#define ADC_INT_STATUS_CHB_CMP_SHIFT 1 +#define ADC_INT_STATUS_CHC_CMP_MASK 0x4u +#define ADC_INT_STATUS_CHC_CMP_SHIFT 2 +#define ADC_INT_STATUS_CHD_CMP_MASK 0x8u +#define ADC_INT_STATUS_CHD_CMP_SHIFT 3 +#define ADC_INT_STATUS_DMA_REACH_WM_MASK 0x20u +#define ADC_INT_STATUS_DMA_REACH_WM_SHIFT 5 +#define ADC_INT_STATUS_FIFO_UNDERRUN_MASK 0x40u +#define ADC_INT_STATUS_FIFO_UNDERRUN_SHIFT 6 +#define ADC_INT_STATUS_FIFO_OVERRUN_MASK 0x80u +#define ADC_INT_STATUS_FIFO_OVERRUN_SHIFT 7 +#define ADC_INT_STATUS_CHA_COV_MASK 0x100u +#define ADC_INT_STATUS_CHA_COV_SHIFT 8 +#define ADC_INT_STATUS_CHB_COV_MASK 0x200u +#define ADC_INT_STATUS_CHB_COV_SHIFT 9 +#define ADC_INT_STATUS_CHC_COV_MASK 0x400u +#define ADC_INT_STATUS_CHC_COV_SHIFT 10 +#define ADC_INT_STATUS_CHD_COV_MASK 0x800u +#define ADC_INT_STATUS_CHD_COV_SHIFT 11 +#define ADC_INT_STATUS_SW_CH_COV_MASK 0x1000u +#define ADC_INT_STATUS_SW_CH_COV_SHIFT 12 +#define ADC_INT_STATUS_CHA_COV_TO_MASK 0x10000u +#define ADC_INT_STATUS_CHA_COV_TO_SHIFT 16 +#define ADC_INT_STATUS_CHB_COV_TO_MASK 0x20000u +#define ADC_INT_STATUS_CHB_COV_TO_SHIFT 17 +#define ADC_INT_STATUS_CHC_COV_TO_MASK 0x40000u +#define ADC_INT_STATUS_CHC_COV_TO_SHIFT 18 +#define ADC_INT_STATUS_CHD_COV_TO_MASK 0x80000u +#define ADC_INT_STATUS_CHD_COV_TO_SHIFT 19 +#define ADC_INT_STATUS_SW_CH_COV_TO_MASK 0x100000u +#define ADC_INT_STATUS_SW_CH_COV_TO_SHIFT 20 +#define ADC_INT_STATUS_LAST_FIFO_DATA_READ_MASK 0x200000u +#define ADC_INT_STATUS_LAST_FIFO_DATA_READ_SHIFT 21 +/* CHA_B_CNV_RSLT Bit Fields */ +#define ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK 0xFFFu +#define ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_SHIFT 0 +#define ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_SHIFT))&ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK) +#define ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_MASK 0xFFF0000u +#define ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT 16 +#define ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT))&ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_MASK) +/* CHC_D_CNV_RSLT Bit Fields */ +#define ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK 0xFFFu +#define ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_SHIFT 0 +#define ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_SHIFT))&ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK) +#define ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_MASK 0xFFF0000u +#define ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT 16 +#define ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT))&ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_MASK) +/* CH_SW_CNV_RSLT Bit Fields */ +#define ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK 0xFFFu +#define ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_SHIFT 0 +#define ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT(x) (((uint32_t)(((uint32_t)(x))<<ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_SHIFT))&ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK) +/* DMA_FIFO_DAT Bit Fields */ +#define ADC_DMA_FIFO_DAT_DMA_FIFO_0_MASK 0xFFFu +#define ADC_DMA_FIFO_DAT_DMA_FIFO_0_SHIFT 0 +#define ADC_DMA_FIFO_DAT_DMA_FIFO_0(x) (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DMA_FIFO_0_SHIFT))&ADC_DMA_FIFO_DAT_DMA_FIFO_0_MASK) +#define ADC_DMA_FIFO_DAT_DAT2_FLAG_MASK 0xC000u +#define ADC_DMA_FIFO_DAT_DAT2_FLAG_SHIFT 14 +#define ADC_DMA_FIFO_DAT_DAT2_FLAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DAT2_FLAG_SHIFT))&ADC_DMA_FIFO_DAT_DAT2_FLAG_MASK) +#define ADC_DMA_FIFO_DAT_DMA_FIFO_1_MASK 0xFFF0000u +#define ADC_DMA_FIFO_DAT_DMA_FIFO_1_SHIFT 16 +#define ADC_DMA_FIFO_DAT_DMA_FIFO_1(x) (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DMA_FIFO_1_SHIFT))&ADC_DMA_FIFO_DAT_DMA_FIFO_1_MASK) +#define ADC_DMA_FIFO_DAT_DAT1_FLAG_MASK 0xC0000000u +#define ADC_DMA_FIFO_DAT_DAT1_FLAG_SHIFT 30 +#define ADC_DMA_FIFO_DAT_DAT1_FLAG(x) (((uint32_t)(((uint32_t)(x))<<ADC_DMA_FIFO_DAT_DAT1_FLAG_SHIFT))&ADC_DMA_FIFO_DAT_DAT1_FLAG_MASK) +/* ADC_CFG Bit Fields */ +#define ADC_ADC_CFG_ADC_EN_MASK 0x1u +#define ADC_ADC_CFG_ADC_EN_SHIFT 0 +#define ADC_ADC_CFG_ADC_PD_MASK 0x2u +#define ADC_ADC_CFG_ADC_PD_SHIFT 1 +#define ADC_ADC_CFG_ADC_PD_OK_MASK 0x80u +#define ADC_ADC_CFG_ADC_PD_OK_SHIFT 7 +#define ADC_ADC_CFG_ADC_CLK_DOWN_MASK 0x80000000u +#define ADC_ADC_CFG_ADC_CLK_DOWN_SHIFT 31 + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x30610000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +#define ADC1_BASE_PTR (ADC1) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x30620000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +#define ADC2_BASE_PTR (ADC2) +/** Array initializer of ADC peripheral base adresses */ +#define ADC_BASE_ADDRS { ADC1_BASE, ADC2_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC1, ADC2 } + +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + + +/* ADC - Register instance definitions */ +/* ADC1 */ +#define ADC1_CH_A_CFG1 ADC_CH_A_CFG1_REG(ADC1_BASE_PTR) +#define ADC1_CH_A_CFG2 ADC_CH_A_CFG2_REG(ADC1_BASE_PTR) +#define ADC1_CH_B_CFG1 ADC_CH_B_CFG1_REG(ADC1_BASE_PTR) +#define ADC1_CH_B_CFG2 ADC_CH_B_CFG2_REG(ADC1_BASE_PTR) +#define ADC1_CH_C_CFG1 ADC_CH_C_CFG1_REG(ADC1_BASE_PTR) +#define ADC1_CH_C_CFG2 ADC_CH_C_CFG2_REG(ADC1_BASE_PTR) +#define ADC1_CH_D_CFG1 ADC_CH_D_CFG1_REG(ADC1_BASE_PTR) +#define ADC1_CH_D_CFG2 ADC_CH_D_CFG2_REG(ADC1_BASE_PTR) +#define ADC1_CH_SW_CFG ADC_CH_SW_CFG_REG(ADC1_BASE_PTR) +#define ADC1_TIMER_UNIT ADC_TIMER_UNIT_REG(ADC1_BASE_PTR) +#define ADC1_DMA_FIFO ADC_DMA_FIFO_REG(ADC1_BASE_PTR) +#define ADC1_FIFO_STATUS ADC_FIFO_STATUS_REG(ADC1_BASE_PTR) +#define ADC1_INT_SIG_EN ADC_INT_SIG_EN_REG(ADC1_BASE_PTR) +#define ADC1_INT_EN ADC_INT_EN_REG(ADC1_BASE_PTR) +#define ADC1_INT_STATUS ADC_INT_STATUS_REG(ADC1_BASE_PTR) +#define ADC1_CHA_B_CNV_RSLT ADC_CHA_B_CNV_RSLT_REG(ADC1_BASE_PTR) +#define ADC1_CHC_D_CNV_RSLT ADC_CHC_D_CNV_RSLT_REG(ADC1_BASE_PTR) +#define ADC1_CH_SW_CNV_RSLT ADC_CH_SW_CNV_RSLT_REG(ADC1_BASE_PTR) +#define ADC1_DMA_FIFO_DAT ADC_DMA_FIFO_DAT_REG(ADC1_BASE_PTR) +#define ADC1_ADC_CFG ADC_ADC_CFG_REG(ADC1_BASE_PTR) +/* ADC2 */ +#define ADC2_CH_A_CFG1 ADC_CH_A_CFG1_REG(ADC2_BASE_PTR) +#define ADC2_CH_A_CFG2 ADC_CH_A_CFG2_REG(ADC2_BASE_PTR) +#define ADC2_CH_B_CFG1 ADC_CH_B_CFG1_REG(ADC2_BASE_PTR) +#define ADC2_CH_B_CFG2 ADC_CH_B_CFG2_REG(ADC2_BASE_PTR) +#define ADC2_CH_C_CFG1 ADC_CH_C_CFG1_REG(ADC2_BASE_PTR) +#define ADC2_CH_C_CFG2 ADC_CH_C_CFG2_REG(ADC2_BASE_PTR) +#define ADC2_CH_D_CFG1 ADC_CH_D_CFG1_REG(ADC2_BASE_PTR) +#define ADC2_CH_D_CFG2 ADC_CH_D_CFG2_REG(ADC2_BASE_PTR) +#define ADC2_CH_SW_CFG ADC_CH_SW_CFG_REG(ADC2_BASE_PTR) +#define ADC2_TIMER_UNIT ADC_TIMER_UNIT_REG(ADC2_BASE_PTR) +#define ADC2_DMA_FIFO ADC_DMA_FIFO_REG(ADC2_BASE_PTR) +#define ADC2_FIFO_STATUS ADC_FIFO_STATUS_REG(ADC2_BASE_PTR) +#define ADC2_INT_SIG_EN ADC_INT_SIG_EN_REG(ADC2_BASE_PTR) +#define ADC2_INT_EN ADC_INT_EN_REG(ADC2_BASE_PTR) +#define ADC2_INT_STATUS ADC_INT_STATUS_REG(ADC2_BASE_PTR) +#define ADC2_CHA_B_CNV_RSLT ADC_CHA_B_CNV_RSLT_REG(ADC2_BASE_PTR) +#define ADC2_CHC_D_CNV_RSLT ADC_CHC_D_CNV_RSLT_REG(ADC2_BASE_PTR) +#define ADC2_CH_SW_CNV_RSLT ADC_CH_SW_CNV_RSLT_REG(ADC2_BASE_PTR) +#define ADC2_DMA_FIFO_DAT ADC_DMA_FIFO_DAT_REG(ADC2_BASE_PTR) +#define ADC2_ADC_CFG ADC_ADC_CFG_REG(ADC2_BASE_PTR) + +/*! + * @} + */ /* end of group ADC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group ADC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- APBH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer + * @{ + */ + +/** APBH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ + __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ + __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ + __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ + __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ + __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ + __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ + __IO uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ + uint8_t RESERVED_2[156]; + struct { /* offset: 0x100, array step: 0x70 */ + __IO uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */ + uint8_t RESERVED_6[12]; + } CH_[16]; + __IO uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ +} APBH_Type, *APBH_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- APBH - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Accessor_Macros APBH - Register accessor macros + * @{ + */ + + +/* APBH - Register accessors */ +#define APBH_CTRL0_REG(base) ((base)->CTRL0) +#define APBH_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define APBH_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define APBH_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define APBH_CTRL1_REG(base) ((base)->CTRL1) +#define APBH_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define APBH_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define APBH_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define APBH_CTRL2_REG(base) ((base)->CTRL2) +#define APBH_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define APBH_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define APBH_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define APBH_CHANNEL_CTRL_REG(base) ((base)->CHANNEL_CTRL) +#define APBH_CHANNEL_CTRL_SET_REG(base) ((base)->CHANNEL_CTRL_SET) +#define APBH_CHANNEL_CTRL_CLR_REG(base) ((base)->CHANNEL_CTRL_CLR) +#define APBH_CHANNEL_CTRL_TOG_REG(base) ((base)->CHANNEL_CTRL_TOG) +#define APBH_DEVSEL_REG(base) ((base)->DEVSEL) +#define APBH_DMA_BURST_SIZE_REG(base) ((base)->DMA_BURST_SIZE) +#define APBH_DEBUG_REG(base) ((base)->DEBUG) +#define APBH_CH_CURCMDAR_REG(base,index) ((base)->CH_[index].CH_CURCMDAR) +#define APBH_CH_NXTCMDAR_REG(base,index) ((base)->CH_[index].CH_NXTCMDAR) +#define APBH_CH_CMD_REG(base,index) ((base)->CH_[index].CH_CMD) +#define APBH_CH_BAR_REG(base,index) ((base)->CH_[index].CH_BAR) +#define APBH_CH_SEMA_REG(base,index) ((base)->CH_[index].CH_SEMA) +#define APBH_CH_DEBUG1_REG(base,index) ((base)->CH_[index].CH_DEBUG1) +#define APBH_CH_DEBUG2_REG(base,index) ((base)->CH_[index].CH_DEBUG2) +#define APBH_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group APBH_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xFFFFu +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT 0 +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_RSVD0_MASK 0xFFF0000u +#define APBH_CTRL0_RSVD0_SHIFT 16 +#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_RSVD0_SHIFT))&APBH_CTRL0_RSVD0_MASK) +#define APBH_CTRL0_APB_BURST_EN_MASK 0x10000000u +#define APBH_CTRL0_APB_BURST_EN_SHIFT 28 +#define APBH_CTRL0_AHB_BURST8_EN_MASK 0x20000000u +#define APBH_CTRL0_AHB_BURST8_EN_SHIFT 29 +#define APBH_CTRL0_CLKGATE_MASK 0x40000000u +#define APBH_CTRL0_CLKGATE_SHIFT 30 +#define APBH_CTRL0_SFTRST_MASK 0x80000000u +#define APBH_CTRL0_SFTRST_SHIFT 31 +/* CTRL0_SET Bit Fields */ +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK 0xFFFFu +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT 0 +#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_SET_RSVD0_MASK 0xFFF0000u +#define APBH_CTRL0_SET_RSVD0_SHIFT 16 +#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_SET_RSVD0_SHIFT))&APBH_CTRL0_SET_RSVD0_MASK) +#define APBH_CTRL0_SET_APB_BURST_EN_MASK 0x10000000u +#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT 28 +#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK 0x20000000u +#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT 29 +#define APBH_CTRL0_SET_CLKGATE_MASK 0x40000000u +#define APBH_CTRL0_SET_CLKGATE_SHIFT 30 +#define APBH_CTRL0_SET_SFTRST_MASK 0x80000000u +#define APBH_CTRL0_SET_SFTRST_SHIFT 31 +/* CTRL0_CLR Bit Fields */ +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK 0xFFFFu +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT 0 +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_CLR_RSVD0_MASK 0xFFF0000u +#define APBH_CTRL0_CLR_RSVD0_SHIFT 16 +#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_CLR_RSVD0_SHIFT))&APBH_CTRL0_CLR_RSVD0_MASK) +#define APBH_CTRL0_CLR_APB_BURST_EN_MASK 0x10000000u +#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT 28 +#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK 0x20000000u +#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT 29 +#define APBH_CTRL0_CLR_CLKGATE_MASK 0x40000000u +#define APBH_CTRL0_CLR_CLKGATE_SHIFT 30 +#define APBH_CTRL0_CLR_SFTRST_MASK 0x80000000u +#define APBH_CTRL0_CLR_SFTRST_SHIFT 31 +/* CTRL0_TOG Bit Fields */ +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK 0xFFFFu +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT 0 +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT))&APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_TOG_RSVD0_MASK 0xFFF0000u +#define APBH_CTRL0_TOG_RSVD0_SHIFT 16 +#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<APBH_CTRL0_TOG_RSVD0_SHIFT))&APBH_CTRL0_TOG_RSVD0_MASK) +#define APBH_CTRL0_TOG_APB_BURST_EN_MASK 0x10000000u +#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT 28 +#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK 0x20000000u +#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT 29 +#define APBH_CTRL0_TOG_CLKGATE_MASK 0x40000000u +#define APBH_CTRL0_TOG_CLKGATE_SHIFT 30 +#define APBH_CTRL0_TOG_SFTRST_MASK 0x80000000u +#define APBH_CTRL0_TOG_SFTRST_SHIFT 31 +/* CTRL1 Bit Fields */ +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK 0x1u +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT 0 +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK 0x2u +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT 1 +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK 0x4u +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT 2 +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK 0x8u +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT 3 +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK 0x10u +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT 4 +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK 0x20u +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT 5 +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK 0x40u +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT 6 +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK 0x80u +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT 7 +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK 0x100u +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT 8 +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK 0x200u +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT 9 +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK 0x400u +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT 10 +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK 0x800u +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT 11 +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK 0x1000u +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT 12 +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK 0x2000u +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT 13 +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK 0x4000u +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT 14 +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK 0x8000u +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT 15 +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK 0x10000u +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT 16 +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK 0x20000u +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT 17 +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK 0x40000u +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT 18 +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK 0x80000u +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT 19 +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK 0x100000u +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT 20 +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK 0x200000u +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT 21 +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK 0x400000u +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT 22 +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK 0x800000u +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT 23 +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK 0x1000000u +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT 24 +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK 0x2000000u +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT 25 +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK 0x4000000u +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT 26 +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK 0x8000000u +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT 27 +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK 0x10000000u +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT 28 +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK 0x20000000u +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT 29 +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK 0x40000000u +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT 30 +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK 0x80000000u +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT 31 +/* CTRL1_SET Bit Fields */ +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK 0x1u +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT 0 +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK 0x2u +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT 1 +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK 0x4u +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT 2 +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK 0x8u +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT 3 +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK 0x10u +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT 4 +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK 0x20u +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT 5 +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK 0x40u +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT 6 +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK 0x80u +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT 7 +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK 0x100u +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT 8 +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK 0x200u +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT 9 +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK 0x400u +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT 10 +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK 0x800u +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT 11 +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK 0x1000u +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT 12 +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK 0x2000u +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT 13 +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK 0x4000u +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT 14 +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK 0x8000u +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT 15 +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK 0x10000u +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT 16 +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK 0x20000u +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT 17 +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK 0x40000u +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT 18 +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK 0x80000u +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT 19 +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK 0x100000u +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT 20 +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK 0x200000u +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT 21 +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK 0x400000u +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT 22 +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK 0x800000u +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT 23 +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK 0x1000000u +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT 24 +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK 0x2000000u +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT 25 +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK 0x4000000u +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT 26 +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK 0x8000000u +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT 27 +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK 0x10000000u +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT 28 +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK 0x20000000u +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT 29 +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK 0x40000000u +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT 30 +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK 0x80000000u +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT 31 +/* CTRL1_CLR Bit Fields */ +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK 0x1u +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT 0 +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK 0x2u +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT 1 +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK 0x4u +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT 2 +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK 0x8u +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT 3 +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK 0x10u +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT 4 +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK 0x20u +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT 5 +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK 0x40u +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT 6 +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK 0x80u +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT 7 +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK 0x100u +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT 8 +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK 0x200u +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT 9 +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK 0x400u +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT 10 +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK 0x800u +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT 11 +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK 0x1000u +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT 12 +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK 0x2000u +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT 13 +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK 0x4000u +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT 14 +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK 0x8000u +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT 15 +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK 0x10000u +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT 16 +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK 0x20000u +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT 17 +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK 0x40000u +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT 18 +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK 0x80000u +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT 19 +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK 0x100000u +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT 20 +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK 0x200000u +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT 21 +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK 0x400000u +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT 22 +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK 0x800000u +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT 23 +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK 0x1000000u +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT 24 +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK 0x2000000u +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT 25 +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK 0x4000000u +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT 26 +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK 0x8000000u +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT 27 +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK 0x10000000u +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT 28 +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK 0x20000000u +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT 29 +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK 0x40000000u +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT 30 +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK 0x80000000u +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT 31 +/* CTRL1_TOG Bit Fields */ +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK 0x1u +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT 0 +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK 0x2u +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT 1 +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK 0x4u +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT 2 +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK 0x8u +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT 3 +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK 0x10u +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT 4 +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK 0x20u +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT 5 +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK 0x40u +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT 6 +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK 0x80u +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT 7 +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK 0x100u +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT 8 +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK 0x200u +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT 9 +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK 0x400u +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT 10 +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK 0x800u +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT 11 +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK 0x1000u +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT 12 +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK 0x2000u +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT 13 +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK 0x4000u +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT 14 +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK 0x8000u +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT 15 +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK 0x10000u +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT 16 +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK 0x20000u +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT 17 +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK 0x40000u +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT 18 +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK 0x80000u +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT 19 +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK 0x100000u +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT 20 +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK 0x200000u +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT 21 +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK 0x400000u +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT 22 +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK 0x800000u +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT 23 +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK 0x1000000u +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT 24 +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK 0x2000000u +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT 25 +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK 0x4000000u +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT 26 +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK 0x8000000u +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT 27 +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK 0x10000000u +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT 28 +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK 0x20000000u +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT 29 +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK 0x40000000u +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT 30 +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK 0x80000000u +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT 31 +/* CTRL2 Bit Fields */ +#define APBH_CTRL2_CH0_ERROR_IRQ_MASK 0x1u +#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT 0 +#define APBH_CTRL2_CH1_ERROR_IRQ_MASK 0x2u +#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT 1 +#define APBH_CTRL2_CH2_ERROR_IRQ_MASK 0x4u +#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT 2 +#define APBH_CTRL2_CH3_ERROR_IRQ_MASK 0x8u +#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT 3 +#define APBH_CTRL2_CH4_ERROR_IRQ_MASK 0x10u +#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT 4 +#define APBH_CTRL2_CH5_ERROR_IRQ_MASK 0x20u +#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT 5 +#define APBH_CTRL2_CH6_ERROR_IRQ_MASK 0x40u +#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT 6 +#define APBH_CTRL2_CH7_ERROR_IRQ_MASK 0x80u +#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT 7 +#define APBH_CTRL2_CH8_ERROR_IRQ_MASK 0x100u +#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT 8 +#define APBH_CTRL2_CH9_ERROR_IRQ_MASK 0x200u +#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT 9 +#define APBH_CTRL2_CH10_ERROR_IRQ_MASK 0x400u +#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT 10 +#define APBH_CTRL2_CH11_ERROR_IRQ_MASK 0x800u +#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT 11 +#define APBH_CTRL2_CH12_ERROR_IRQ_MASK 0x1000u +#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT 12 +#define APBH_CTRL2_CH13_ERROR_IRQ_MASK 0x2000u +#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT 13 +#define APBH_CTRL2_CH14_ERROR_IRQ_MASK 0x4000u +#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT 14 +#define APBH_CTRL2_CH15_ERROR_IRQ_MASK 0x8000u +#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT 15 +#define APBH_CTRL2_CH0_ERROR_STATUS_MASK 0x10000u +#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT 16 +#define APBH_CTRL2_CH1_ERROR_STATUS_MASK 0x20000u +#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT 17 +#define APBH_CTRL2_CH2_ERROR_STATUS_MASK 0x40000u +#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT 18 +#define APBH_CTRL2_CH3_ERROR_STATUS_MASK 0x80000u +#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT 19 +#define APBH_CTRL2_CH4_ERROR_STATUS_MASK 0x100000u +#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT 20 +#define APBH_CTRL2_CH5_ERROR_STATUS_MASK 0x200000u +#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT 21 +#define APBH_CTRL2_CH6_ERROR_STATUS_MASK 0x400000u +#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT 22 +#define APBH_CTRL2_CH7_ERROR_STATUS_MASK 0x800000u +#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT 23 +#define APBH_CTRL2_CH8_ERROR_STATUS_MASK 0x1000000u +#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT 24 +#define APBH_CTRL2_CH9_ERROR_STATUS_MASK 0x2000000u +#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT 25 +#define APBH_CTRL2_CH10_ERROR_STATUS_MASK 0x4000000u +#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT 26 +#define APBH_CTRL2_CH11_ERROR_STATUS_MASK 0x8000000u +#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT 27 +#define APBH_CTRL2_CH12_ERROR_STATUS_MASK 0x10000000u +#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT 28 +#define APBH_CTRL2_CH13_ERROR_STATUS_MASK 0x20000000u +#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT 29 +#define APBH_CTRL2_CH14_ERROR_STATUS_MASK 0x40000000u +#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT 30 +#define APBH_CTRL2_CH15_ERROR_STATUS_MASK 0x80000000u +#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT 31 +/* CTRL2_SET Bit Fields */ +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK 0x1u +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT 0 +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK 0x2u +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT 1 +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK 0x4u +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT 2 +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK 0x8u +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT 3 +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK 0x10u +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT 4 +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK 0x20u +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT 5 +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK 0x40u +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT 6 +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK 0x80u +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT 7 +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK 0x100u +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT 8 +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK 0x200u +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT 9 +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK 0x400u +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT 10 +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK 0x800u +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT 11 +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK 0x1000u +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT 12 +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK 0x2000u +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT 13 +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK 0x4000u +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT 14 +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK 0x8000u +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT 15 +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK 0x10000u +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT 16 +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK 0x20000u +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT 17 +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK 0x40000u +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT 18 +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK 0x80000u +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT 19 +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK 0x100000u +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT 20 +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK 0x200000u +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT 21 +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK 0x400000u +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT 22 +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK 0x800000u +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT 23 +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK 0x1000000u +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT 24 +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK 0x2000000u +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT 25 +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK 0x4000000u +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT 26 +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK 0x8000000u +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT 27 +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK 0x10000000u +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT 28 +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK 0x20000000u +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT 29 +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK 0x40000000u +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT 30 +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK 0x80000000u +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT 31 +/* CTRL2_CLR Bit Fields */ +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK 0x1u +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT 0 +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK 0x2u +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT 1 +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK 0x4u +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT 2 +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK 0x8u +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT 3 +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK 0x10u +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT 4 +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK 0x20u +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT 5 +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK 0x40u +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT 6 +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK 0x80u +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT 7 +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK 0x100u +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT 8 +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK 0x200u +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT 9 +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK 0x400u +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT 10 +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK 0x800u +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT 11 +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK 0x1000u +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT 12 +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK 0x2000u +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT 13 +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK 0x4000u +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT 14 +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK 0x8000u +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT 15 +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK 0x10000u +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT 16 +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK 0x20000u +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT 17 +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK 0x40000u +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT 18 +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK 0x80000u +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT 19 +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK 0x100000u +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT 20 +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK 0x200000u +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT 21 +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK 0x400000u +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT 22 +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK 0x800000u +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT 23 +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK 0x1000000u +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT 24 +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK 0x2000000u +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT 25 +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK 0x4000000u +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT 26 +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK 0x8000000u +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT 27 +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK 0x10000000u +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT 28 +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK 0x20000000u +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT 29 +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK 0x40000000u +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT 30 +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK 0x80000000u +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT 31 +/* CTRL2_TOG Bit Fields */ +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK 0x1u +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT 0 +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK 0x2u +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT 1 +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK 0x4u +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT 2 +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK 0x8u +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT 3 +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK 0x10u +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT 4 +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK 0x20u +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT 5 +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK 0x40u +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT 6 +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK 0x80u +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT 7 +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK 0x100u +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT 8 +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK 0x200u +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT 9 +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK 0x400u +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT 10 +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK 0x800u +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT 11 +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK 0x1000u +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT 12 +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK 0x2000u +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT 13 +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK 0x4000u +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT 14 +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK 0x8000u +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT 15 +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK 0x10000u +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT 16 +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK 0x20000u +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT 17 +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK 0x40000u +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT 18 +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK 0x80000u +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT 19 +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK 0x100000u +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT 20 +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK 0x200000u +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT 21 +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK 0x400000u +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT 22 +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK 0x800000u +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT 23 +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK 0x1000000u +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT 24 +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK 0x2000000u +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT 25 +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK 0x4000000u +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT 26 +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK 0x8000000u +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT 27 +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK 0x10000000u +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT 28 +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK 0x20000000u +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT 29 +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK 0x40000000u +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT 30 +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK 0x80000000u +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT 31 +/* CHANNEL_CTRL Bit Fields */ +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xFFFFu +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT 0 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK 0xFFFF0000u +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT 16 +#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) +/* CHANNEL_CTRL_SET Bit Fields */ +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK 0xFFFFu +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT 0 +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK 0xFFFF0000u +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT 16 +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) +/* CHANNEL_CTRL_CLR Bit Fields */ +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK 0xFFFFu +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT 0 +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK 0xFFFF0000u +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT 16 +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) +/* CHANNEL_CTRL_TOG Bit Fields */ +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK 0xFFFFu +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT 0 +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK 0xFFFF0000u +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT 16 +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT))&APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) +/* DEVSEL Bit Fields */ +#define APBH_DEVSEL_CH0_MASK 0x3u +#define APBH_DEVSEL_CH0_SHIFT 0 +#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH0_SHIFT))&APBH_DEVSEL_CH0_MASK) +#define APBH_DEVSEL_CH1_MASK 0xCu +#define APBH_DEVSEL_CH1_SHIFT 2 +#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH1_SHIFT))&APBH_DEVSEL_CH1_MASK) +#define APBH_DEVSEL_CH2_MASK 0x30u +#define APBH_DEVSEL_CH2_SHIFT 4 +#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH2_SHIFT))&APBH_DEVSEL_CH2_MASK) +#define APBH_DEVSEL_CH3_MASK 0xC0u +#define APBH_DEVSEL_CH3_SHIFT 6 +#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH3_SHIFT))&APBH_DEVSEL_CH3_MASK) +#define APBH_DEVSEL_CH4_MASK 0x300u +#define APBH_DEVSEL_CH4_SHIFT 8 +#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH4_SHIFT))&APBH_DEVSEL_CH4_MASK) +#define APBH_DEVSEL_CH5_MASK 0xC00u +#define APBH_DEVSEL_CH5_SHIFT 10 +#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH5_SHIFT))&APBH_DEVSEL_CH5_MASK) +#define APBH_DEVSEL_CH6_MASK 0x3000u +#define APBH_DEVSEL_CH6_SHIFT 12 +#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH6_SHIFT))&APBH_DEVSEL_CH6_MASK) +#define APBH_DEVSEL_CH7_MASK 0xC000u +#define APBH_DEVSEL_CH7_SHIFT 14 +#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH7_SHIFT))&APBH_DEVSEL_CH7_MASK) +#define APBH_DEVSEL_CH8_MASK 0x30000u +#define APBH_DEVSEL_CH8_SHIFT 16 +#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH8_SHIFT))&APBH_DEVSEL_CH8_MASK) +#define APBH_DEVSEL_CH9_MASK 0xC0000u +#define APBH_DEVSEL_CH9_SHIFT 18 +#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH9_SHIFT))&APBH_DEVSEL_CH9_MASK) +#define APBH_DEVSEL_CH10_MASK 0x300000u +#define APBH_DEVSEL_CH10_SHIFT 20 +#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH10_SHIFT))&APBH_DEVSEL_CH10_MASK) +#define APBH_DEVSEL_CH11_MASK 0xC00000u +#define APBH_DEVSEL_CH11_SHIFT 22 +#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH11_SHIFT))&APBH_DEVSEL_CH11_MASK) +#define APBH_DEVSEL_CH12_MASK 0x3000000u +#define APBH_DEVSEL_CH12_SHIFT 24 +#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH12_SHIFT))&APBH_DEVSEL_CH12_MASK) +#define APBH_DEVSEL_CH13_MASK 0xC000000u +#define APBH_DEVSEL_CH13_SHIFT 26 +#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH13_SHIFT))&APBH_DEVSEL_CH13_MASK) +#define APBH_DEVSEL_CH14_MASK 0x30000000u +#define APBH_DEVSEL_CH14_SHIFT 28 +#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH14_SHIFT))&APBH_DEVSEL_CH14_MASK) +#define APBH_DEVSEL_CH15_MASK 0xC0000000u +#define APBH_DEVSEL_CH15_SHIFT 30 +#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x))<<APBH_DEVSEL_CH15_SHIFT))&APBH_DEVSEL_CH15_MASK) +/* DMA_BURST_SIZE Bit Fields */ +#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3u +#define APBH_DMA_BURST_SIZE_CH0_SHIFT 0 +#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH0_SHIFT))&APBH_DMA_BURST_SIZE_CH0_MASK) +#define APBH_DMA_BURST_SIZE_CH1_MASK 0xCu +#define APBH_DMA_BURST_SIZE_CH1_SHIFT 2 +#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH1_SHIFT))&APBH_DMA_BURST_SIZE_CH1_MASK) +#define APBH_DMA_BURST_SIZE_CH2_MASK 0x30u +#define APBH_DMA_BURST_SIZE_CH2_SHIFT 4 +#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH2_SHIFT))&APBH_DMA_BURST_SIZE_CH2_MASK) +#define APBH_DMA_BURST_SIZE_CH3_MASK 0xC0u +#define APBH_DMA_BURST_SIZE_CH3_SHIFT 6 +#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH3_SHIFT))&APBH_DMA_BURST_SIZE_CH3_MASK) +#define APBH_DMA_BURST_SIZE_CH4_MASK 0x300u +#define APBH_DMA_BURST_SIZE_CH4_SHIFT 8 +#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH4_SHIFT))&APBH_DMA_BURST_SIZE_CH4_MASK) +#define APBH_DMA_BURST_SIZE_CH5_MASK 0xC00u +#define APBH_DMA_BURST_SIZE_CH5_SHIFT 10 +#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH5_SHIFT))&APBH_DMA_BURST_SIZE_CH5_MASK) +#define APBH_DMA_BURST_SIZE_CH6_MASK 0x3000u +#define APBH_DMA_BURST_SIZE_CH6_SHIFT 12 +#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH6_SHIFT))&APBH_DMA_BURST_SIZE_CH6_MASK) +#define APBH_DMA_BURST_SIZE_CH7_MASK 0xC000u +#define APBH_DMA_BURST_SIZE_CH7_SHIFT 14 +#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH7_SHIFT))&APBH_DMA_BURST_SIZE_CH7_MASK) +#define APBH_DMA_BURST_SIZE_CH8_MASK 0x30000u +#define APBH_DMA_BURST_SIZE_CH8_SHIFT 16 +#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH8_SHIFT))&APBH_DMA_BURST_SIZE_CH8_MASK) +#define APBH_DMA_BURST_SIZE_CH9_MASK 0xC0000u +#define APBH_DMA_BURST_SIZE_CH9_SHIFT 18 +#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH9_SHIFT))&APBH_DMA_BURST_SIZE_CH9_MASK) +#define APBH_DMA_BURST_SIZE_CH10_MASK 0x300000u +#define APBH_DMA_BURST_SIZE_CH10_SHIFT 20 +#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH10_SHIFT))&APBH_DMA_BURST_SIZE_CH10_MASK) +#define APBH_DMA_BURST_SIZE_CH11_MASK 0xC00000u +#define APBH_DMA_BURST_SIZE_CH11_SHIFT 22 +#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH11_SHIFT))&APBH_DMA_BURST_SIZE_CH11_MASK) +#define APBH_DMA_BURST_SIZE_CH12_MASK 0x3000000u +#define APBH_DMA_BURST_SIZE_CH12_SHIFT 24 +#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH12_SHIFT))&APBH_DMA_BURST_SIZE_CH12_MASK) +#define APBH_DMA_BURST_SIZE_CH13_MASK 0xC000000u +#define APBH_DMA_BURST_SIZE_CH13_SHIFT 26 +#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH13_SHIFT))&APBH_DMA_BURST_SIZE_CH13_MASK) +#define APBH_DMA_BURST_SIZE_CH14_MASK 0x30000000u +#define APBH_DMA_BURST_SIZE_CH14_SHIFT 28 +#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH14_SHIFT))&APBH_DMA_BURST_SIZE_CH14_MASK) +#define APBH_DMA_BURST_SIZE_CH15_MASK 0xC0000000u +#define APBH_DMA_BURST_SIZE_CH15_SHIFT 30 +#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x))<<APBH_DMA_BURST_SIZE_CH15_SHIFT))&APBH_DMA_BURST_SIZE_CH15_MASK) +/* DEBUG Bit Fields */ +#define APBH_DEBUG_GPMI_ONE_FIFO_MASK 0x1u +#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT 0 +/* CH_CURCMDAR Bit Fields */ +#define APBH_CH_CURCMDAR_CMD_ADDR_MASK 0xFFFFFFFFu +#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT 0 +#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_CURCMDAR_CMD_ADDR_SHIFT))&APBH_CH_CURCMDAR_CMD_ADDR_MASK) +/* CH_NXTCMDAR Bit Fields */ +#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK 0xFFFFFFFFu +#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT 0 +#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT))&APBH_CH_NXTCMDAR_CMD_ADDR_MASK) +/* CH_CMD Bit Fields */ +#define APBH_CH_CMD_COMMAND_MASK 0x3u +#define APBH_CH_CMD_COMMAND_SHIFT 0 +#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_CMD_COMMAND_SHIFT))&APBH_CH_CMD_COMMAND_MASK) +#define APBH_CH_CMD_CHAIN_MASK 0x4u +#define APBH_CH_CMD_CHAIN_SHIFT 2 +#define APBH_CH_CMD_IRQONCMPLT_MASK 0x8u +#define APBH_CH_CMD_IRQONCMPLT_SHIFT 3 +#define APBH_CH_CMD_NANDLOCK_MASK 0x10u +#define APBH_CH_CMD_NANDLOCK_SHIFT 4 +#define APBH_CH_CMD_NANDWAIT4READY_MASK 0x20u +#define APBH_CH_CMD_NANDWAIT4READY_SHIFT 5 +#define APBH_CH_CMD_SEMAPHORE_MASK 0x40u +#define APBH_CH_CMD_SEMAPHORE_SHIFT 6 +#define APBH_CH_CMD_WAIT4ENDCMD_MASK 0x80u +#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT 7 +#define APBH_CH_CMD_HALTONTERMINATE_MASK 0x100u +#define APBH_CH_CMD_HALTONTERMINATE_SHIFT 8 +#define APBH_CH_CMD_CMDWORDS_MASK 0xF000u +#define APBH_CH_CMD_CMDWORDS_SHIFT 12 +#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_CMD_CMDWORDS_SHIFT))&APBH_CH_CMD_CMDWORDS_MASK) +#define APBH_CH_CMD_XFER_COUNT_MASK 0xFFFF0000u +#define APBH_CH_CMD_XFER_COUNT_SHIFT 16 +#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_CMD_XFER_COUNT_SHIFT))&APBH_CH_CMD_XFER_COUNT_MASK) +/* CH_BAR Bit Fields */ +#define APBH_CH_BAR_ADDRESS_MASK 0xFFFFFFFFu +#define APBH_CH_BAR_ADDRESS_SHIFT 0 +#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_BAR_ADDRESS_SHIFT))&APBH_CH_BAR_ADDRESS_MASK) +/* CH_SEMA Bit Fields */ +#define APBH_CH_SEMA_INCREMENT_SEMA_MASK 0xFFu +#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT 0 +#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_SEMA_INCREMENT_SEMA_SHIFT))&APBH_CH_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH_SEMA_PHORE_MASK 0xFF0000u +#define APBH_CH_SEMA_PHORE_SHIFT 16 +#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_SEMA_PHORE_SHIFT))&APBH_CH_SEMA_PHORE_MASK) +/* CH_DEBUG1 Bit Fields */ +#define APBH_CH_DEBUG1_STATEMACHINE_MASK 0x1Fu +#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT 0 +#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG1_STATEMACHINE_SHIFT))&APBH_CH_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH_DEBUG1_RSVD1_MASK 0xFFFE0u +#define APBH_CH_DEBUG1_RSVD1_SHIFT 5 +#define APBH_CH_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG1_RSVD1_SHIFT))&APBH_CH_DEBUG1_RSVD1_MASK) +#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK 0x100000u +#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT 20 +#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK 0x200000u +#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT 21 +#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK 0x400000u +#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT 22 +#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK 0x800000u +#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT 23 +#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK 0x1000000u +#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT 24 +#define APBH_CH_DEBUG1_LOCK_MASK 0x2000000u +#define APBH_CH_DEBUG1_LOCK_SHIFT 25 +#define APBH_CH_DEBUG1_READY_MASK 0x4000000u +#define APBH_CH_DEBUG1_READY_SHIFT 26 +#define APBH_CH_DEBUG1_SENSE_MASK 0x8000000u +#define APBH_CH_DEBUG1_SENSE_SHIFT 27 +#define APBH_CH_DEBUG1_END_MASK 0x10000000u +#define APBH_CH_DEBUG1_END_SHIFT 28 +#define APBH_CH_DEBUG1_KICK_MASK 0x20000000u +#define APBH_CH_DEBUG1_KICK_SHIFT 29 +#define APBH_CH_DEBUG1_BURST_MASK 0x40000000u +#define APBH_CH_DEBUG1_BURST_SHIFT 30 +#define APBH_CH_DEBUG1_REQ_MASK 0x80000000u +#define APBH_CH_DEBUG1_REQ_SHIFT 31 +/* CH_DEBUG2 Bit Fields */ +#define APBH_CH_DEBUG2_AHB_BYTES_MASK 0xFFFFu +#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT 0 +#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG2_AHB_BYTES_SHIFT))&APBH_CH_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH_DEBUG2_APB_BYTES_MASK 0xFFFF0000u +#define APBH_CH_DEBUG2_APB_BYTES_SHIFT 16 +#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x))<<APBH_CH_DEBUG2_APB_BYTES_SHIFT))&APBH_CH_DEBUG2_APB_BYTES_MASK) +/* VERSION Bit Fields */ +#define APBH_VERSION_STEP_MASK 0xFFFFu +#define APBH_VERSION_STEP_SHIFT 0 +#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<APBH_VERSION_STEP_SHIFT))&APBH_VERSION_STEP_MASK) +#define APBH_VERSION_MINOR_MASK 0xFF0000u +#define APBH_VERSION_MINOR_SHIFT 16 +#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<APBH_VERSION_MINOR_SHIFT))&APBH_VERSION_MINOR_MASK) +#define APBH_VERSION_MAJOR_MASK 0xFF000000u +#define APBH_VERSION_MAJOR_SHIFT 24 +#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<APBH_VERSION_MAJOR_SHIFT))&APBH_VERSION_MAJOR_MASK) + +/*! + * @} + */ /* end of group APBH_Register_Masks */ + + +/* APBH - Peripheral instance base addresses */ +/** Peripheral APBH base address */ +#define APBH_BASE (0x33000000u) +/** Peripheral APBH base pointer */ +#define APBH ((APBH_Type *)APBH_BASE) +#define APBH_BASE_PTR (APBH) +/** Array initializer of APBH peripheral base adresses */ +#define APBH_BASE_ADDRS { APBH_BASE } +/** Array initializer of APBH peripheral base pointers */ +#define APBH_BASE_PTRS { APBH } + +/* ---------------------------------------------------------------------------- + -- APBH - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Accessor_Macros APBH - Register accessor macros + * @{ + */ + + +/* APBH - Register instance definitions */ +/* APBH */ +#define APBH_CTRL0 APBH_CTRL0_REG(APBH_BASE_PTR) +#define APBH_CTRL0_SET APBH_CTRL0_SET_REG(APBH_BASE_PTR) +#define APBH_CTRL0_CLR APBH_CTRL0_CLR_REG(APBH_BASE_PTR) +#define APBH_CTRL0_TOG APBH_CTRL0_TOG_REG(APBH_BASE_PTR) +#define APBH_CTRL1 APBH_CTRL1_REG(APBH_BASE_PTR) +#define APBH_CTRL1_SET APBH_CTRL1_SET_REG(APBH_BASE_PTR) +#define APBH_CTRL1_CLR APBH_CTRL1_CLR_REG(APBH_BASE_PTR) +#define APBH_CTRL1_TOG APBH_CTRL1_TOG_REG(APBH_BASE_PTR) +#define APBH_CTRL2 APBH_CTRL2_REG(APBH_BASE_PTR) +#define APBH_CTRL2_SET APBH_CTRL2_SET_REG(APBH_BASE_PTR) +#define APBH_CTRL2_CLR APBH_CTRL2_CLR_REG(APBH_BASE_PTR) +#define APBH_CTRL2_TOG APBH_CTRL2_TOG_REG(APBH_BASE_PTR) +#define APBH_CHANNEL_CTRL APBH_CHANNEL_CTRL_REG(APBH_BASE_PTR) +#define APBH_CHANNEL_CTRL_SET APBH_CHANNEL_CTRL_SET_REG(APBH_BASE_PTR) +#define APBH_CHANNEL_CTRL_CLR APBH_CHANNEL_CTRL_CLR_REG(APBH_BASE_PTR) +#define APBH_CHANNEL_CTRL_TOG APBH_CHANNEL_CTRL_TOG_REG(APBH_BASE_PTR) +#define APBH_DEVSEL APBH_DEVSEL_REG(APBH_BASE_PTR) +#define APBH_DMA_BURST_SIZE APBH_DMA_BURST_SIZE_REG(APBH_BASE_PTR) +#define APBH_DEBUG APBH_DEBUG_REG(APBH_BASE_PTR) +#define APBH_CH0_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,0) +#define APBH_CH0_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,0) +#define APBH_CH0_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,0) +#define APBH_CH0_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,0) +#define APBH_CH0_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,0) +#define APBH_CH0_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,0) +#define APBH_CH0_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,0) +#define APBH_CH1_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,1) +#define APBH_CH1_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,1) +#define APBH_CH1_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,1) +#define APBH_CH1_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,1) +#define APBH_CH1_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,1) +#define APBH_CH1_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,1) +#define APBH_CH1_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,1) +#define APBH_CH2_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,2) +#define APBH_CH2_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,2) +#define APBH_CH2_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,2) +#define APBH_CH2_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,2) +#define APBH_CH2_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,2) +#define APBH_CH2_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,2) +#define APBH_CH2_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,2) +#define APBH_CH3_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,3) +#define APBH_CH3_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,3) +#define APBH_CH3_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,3) +#define APBH_CH3_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,3) +#define APBH_CH3_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,3) +#define APBH_CH3_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,3) +#define APBH_CH3_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,3) +#define APBH_CH4_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,4) +#define APBH_CH4_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,4) +#define APBH_CH4_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,4) +#define APBH_CH4_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,4) +#define APBH_CH4_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,4) +#define APBH_CH4_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,4) +#define APBH_CH4_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,4) +#define APBH_CH5_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,5) +#define APBH_CH5_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,5) +#define APBH_CH5_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,5) +#define APBH_CH5_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,5) +#define APBH_CH5_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,5) +#define APBH_CH5_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,5) +#define APBH_CH5_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,5) +#define APBH_CH6_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,6) +#define APBH_CH6_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,6) +#define APBH_CH6_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,6) +#define APBH_CH6_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,6) +#define APBH_CH6_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,6) +#define APBH_CH6_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,6) +#define APBH_CH6_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,6) +#define APBH_CH7_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,7) +#define APBH_CH7_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,7) +#define APBH_CH7_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,7) +#define APBH_CH7_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,7) +#define APBH_CH7_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,7) +#define APBH_CH7_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,7) +#define APBH_CH7_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,7) +#define APBH_CH8_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,8) +#define APBH_CH8_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,8) +#define APBH_CH8_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,8) +#define APBH_CH8_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,8) +#define APBH_CH8_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,8) +#define APBH_CH8_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,8) +#define APBH_CH8_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,8) +#define APBH_CH9_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,9) +#define APBH_CH9_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,9) +#define APBH_CH9_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,9) +#define APBH_CH9_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,9) +#define APBH_CH9_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,9) +#define APBH_CH9_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,9) +#define APBH_CH9_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,9) +#define APBH_CH10_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,10) +#define APBH_CH10_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,10) +#define APBH_CH10_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,10) +#define APBH_CH10_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,10) +#define APBH_CH10_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,10) +#define APBH_CH10_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,10) +#define APBH_CH10_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,10) +#define APBH_CH11_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,11) +#define APBH_CH11_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,11) +#define APBH_CH11_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,11) +#define APBH_CH11_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,11) +#define APBH_CH11_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,11) +#define APBH_CH11_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,11) +#define APBH_CH11_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,11) +#define APBH_CH12_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,12) +#define APBH_CH12_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,12) +#define APBH_CH12_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,12) +#define APBH_CH12_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,12) +#define APBH_CH12_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,12) +#define APBH_CH12_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,12) +#define APBH_CH12_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,12) +#define APBH_CH13_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,13) +#define APBH_CH13_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,13) +#define APBH_CH13_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,13) +#define APBH_CH13_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,13) +#define APBH_CH13_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,13) +#define APBH_CH13_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,13) +#define APBH_CH13_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,13) +#define APBH_CH14_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,14) +#define APBH_CH14_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,14) +#define APBH_CH14_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,14) +#define APBH_CH14_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,14) +#define APBH_CH14_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,14) +#define APBH_CH14_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,14) +#define APBH_CH14_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,14) +#define APBH_CH15_CURCMDAR APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,15) +#define APBH_CH15_NXTCMDAR APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,15) +#define APBH_CH15_CMD APBH_CH_CMD_REG(APBH_BASE_PTR,15) +#define APBH_CH15_BAR APBH_CH_BAR_REG(APBH_BASE_PTR,15) +#define APBH_CH15_SEMA APBH_CH_SEMA_REG(APBH_BASE_PTR,15) +#define APBH_CH15_DEBUG1 APBH_CH_DEBUG1_REG(APBH_BASE_PTR,15) +#define APBH_CH15_DEBUG2 APBH_CH_DEBUG2_REG(APBH_BASE_PTR,15) +#define APBH_VERSION APBH_VERSION_REG(APBH_BASE_PTR) + +/* APBH - Register array accessors */ +#define APBH_CH_CURCMDAR(index) APBH_CH_CURCMDAR_REG(APBH_BASE_PTR,index) +#define APBH_CH_NXTCMDAR(index) APBH_CH_NXTCMDAR_REG(APBH_BASE_PTR,index) +#define APBH_CH_CMD(index) APBH_CH_CMD_REG(APBH_BASE_PTR,index) +#define APBH_CH_BAR(index) APBH_CH_BAR_REG(APBH_BASE_PTR,index) +#define APBH_CH_SEMA(index) APBH_CH_SEMA_REG(APBH_BASE_PTR,index) +#define APBH_CH_DEBUG1(index) APBH_CH_DEBUG1_REG(APBH_BASE_PTR,index) +#define APBH_CH_DEBUG2(index) APBH_CH_DEBUG2_REG(APBH_BASE_PTR,index) + +/*! + * @} + */ /* end of group APBH_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group APBH_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- BCH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer + * @{ + */ + +/** BCH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ + __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ + __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ + __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ + __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ + __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ + __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ + __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ + __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ + __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ + __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ + __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ + __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ + __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ + __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ + __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ + __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ + __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ + __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ + __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ + __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ + uint8_t RESERVED_0[16]; + __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ + __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ + __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ + __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ + __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ + __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ + __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ + __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ + __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ + __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ + __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ + __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ + __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ + __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ + __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ + __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ + __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ + __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ + __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ + __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ + __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ + __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ + __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ + __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ + __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ + __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ + __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ + __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ + __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ + __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ + __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ + __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ + __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ + __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ + __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ + __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ + __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ + __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ + __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ + __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ + __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ + __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ + __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ + __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ + __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ + __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ + __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ + __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ + __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ + __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ + __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ + __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ + __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ + __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ + __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ + __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ + __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ + __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ + __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ + __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ + __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ + __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ + __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ + __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ + __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ + __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ + __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ + __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ +} BCH_Type, *BCH_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- BCH - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros + * @{ + */ + + +/* BCH - Register accessors */ +#define BCH_CTRL_REG(base) ((base)->CTRL) +#define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define BCH_STATUS0_REG(base) ((base)->STATUS0) +#define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) +#define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) +#define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) +#define BCH_MODE_REG(base) ((base)->MODE) +#define BCH_MODE_SET_REG(base) ((base)->MODE_SET) +#define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) +#define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) +#define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) +#define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) +#define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) +#define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) +#define BCH_DATAPTR_REG(base) ((base)->DATAPTR) +#define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) +#define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) +#define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) +#define BCH_METAPTR_REG(base) ((base)->METAPTR) +#define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) +#define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) +#define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) +#define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) +#define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) +#define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) +#define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) +#define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) +#define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) +#define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) +#define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) +#define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) +#define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) +#define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) +#define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) +#define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) +#define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) +#define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) +#define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) +#define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) +#define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) +#define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) +#define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) +#define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) +#define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) +#define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) +#define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) +#define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) +#define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) +#define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) +#define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) +#define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) +#define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) +#define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) +#define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) +#define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) +#define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) +#define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) +#define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) +#define BCH_DEBUG0_REG(base) ((base)->DEBUG0) +#define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) +#define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) +#define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) +#define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) +#define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) +#define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) +#define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) +#define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) +#define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) +#define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) +#define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) +#define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) +#define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) +#define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) +#define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) +#define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) +#define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) +#define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) +#define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) +#define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) +#define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) +#define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) +#define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) +#define BCH_VERSION_REG(base) ((base)->VERSION) +#define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) +#define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) +#define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) +#define BCH_DEBUG1_REG(base) ((base)->DEBUG1) +#define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) + +/*! + * @} + */ /* end of group BCH_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_RSVD0_MASK 0x2u +#define BCH_CTRL_RSVD0_SHIFT 1 +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_RSVD1_MASK 0xF0u +#define BCH_CTRL_RSVD1_SHIFT 4 +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD1_SHIFT))&BCH_CTRL_RSVD1_MASK) +#define BCH_CTRL_COMPLETE_IRQ_EN_MASK 0x100u +#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT 8 +#define BCH_CTRL_RSVD2_MASK 0x200u +#define BCH_CTRL_RSVD2_SHIFT 9 +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK 0x400u +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT 10 +#define BCH_CTRL_RSVD3_MASK 0xF800u +#define BCH_CTRL_RSVD3_SHIFT 11 +#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD3_SHIFT))&BCH_CTRL_RSVD3_MASK) +#define BCH_CTRL_M2M_ENABLE_MASK 0x10000u +#define BCH_CTRL_M2M_ENABLE_SHIFT 16 +#define BCH_CTRL_M2M_ENCODE_MASK 0x20000u +#define BCH_CTRL_M2M_ENCODE_SHIFT 17 +#define BCH_CTRL_M2M_LAYOUT_MASK 0xC0000u +#define BCH_CTRL_M2M_LAYOUT_SHIFT 18 +#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_M2M_LAYOUT_SHIFT))&BCH_CTRL_M2M_LAYOUT_MASK) +#define BCH_CTRL_RSVD4_MASK 0x300000u +#define BCH_CTRL_RSVD4_SHIFT 20 +#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD4_SHIFT))&BCH_CTRL_RSVD4_MASK) +#define BCH_CTRL_DEBUGSYNDROME_MASK 0x400000u +#define BCH_CTRL_DEBUGSYNDROME_SHIFT 22 +#define BCH_CTRL_RSVD5_MASK 0x3F800000u +#define BCH_CTRL_RSVD5_SHIFT 23 +#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_RSVD5_SHIFT))&BCH_CTRL_RSVD5_MASK) +#define BCH_CTRL_CLKGATE_MASK 0x40000000u +#define BCH_CTRL_CLKGATE_SHIFT 30 +#define BCH_CTRL_SFTRST_MASK 0x80000000u +#define BCH_CTRL_SFTRST_SHIFT 31 +/* CTRL_SET Bit Fields */ +#define BCH_CTRL_SET_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_SET_RSVD0_MASK 0x2u +#define BCH_CTRL_SET_RSVD0_SHIFT 1 +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_SET_RSVD1_MASK 0xF0u +#define BCH_CTRL_SET_RSVD1_SHIFT 4 +#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD1_SHIFT))&BCH_CTRL_SET_RSVD1_MASK) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK 0x100u +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT 8 +#define BCH_CTRL_SET_RSVD2_MASK 0x200u +#define BCH_CTRL_SET_RSVD2_SHIFT 9 +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK 0x400u +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT 10 +#define BCH_CTRL_SET_RSVD3_MASK 0xF800u +#define BCH_CTRL_SET_RSVD3_SHIFT 11 +#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD3_SHIFT))&BCH_CTRL_SET_RSVD3_MASK) +#define BCH_CTRL_SET_M2M_ENABLE_MASK 0x10000u +#define BCH_CTRL_SET_M2M_ENABLE_SHIFT 16 +#define BCH_CTRL_SET_M2M_ENCODE_MASK 0x20000u +#define BCH_CTRL_SET_M2M_ENCODE_SHIFT 17 +#define BCH_CTRL_SET_M2M_LAYOUT_MASK 0xC0000u +#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT 18 +#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_M2M_LAYOUT_SHIFT))&BCH_CTRL_SET_M2M_LAYOUT_MASK) +#define BCH_CTRL_SET_RSVD4_MASK 0x300000u +#define BCH_CTRL_SET_RSVD4_SHIFT 20 +#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD4_SHIFT))&BCH_CTRL_SET_RSVD4_MASK) +#define BCH_CTRL_SET_DEBUGSYNDROME_MASK 0x400000u +#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT 22 +#define BCH_CTRL_SET_RSVD5_MASK 0x3F800000u +#define BCH_CTRL_SET_RSVD5_SHIFT 23 +#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_SET_RSVD5_SHIFT))&BCH_CTRL_SET_RSVD5_MASK) +#define BCH_CTRL_SET_CLKGATE_MASK 0x40000000u +#define BCH_CTRL_SET_CLKGATE_SHIFT 30 +#define BCH_CTRL_SET_SFTRST_MASK 0x80000000u +#define BCH_CTRL_SET_SFTRST_SHIFT 31 +/* CTRL_CLR Bit Fields */ +#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_CLR_RSVD0_MASK 0x2u +#define BCH_CTRL_CLR_RSVD0_SHIFT 1 +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_CLR_RSVD1_MASK 0xF0u +#define BCH_CTRL_CLR_RSVD1_SHIFT 4 +#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD1_SHIFT))&BCH_CTRL_CLR_RSVD1_MASK) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK 0x100u +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT 8 +#define BCH_CTRL_CLR_RSVD2_MASK 0x200u +#define BCH_CTRL_CLR_RSVD2_SHIFT 9 +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK 0x400u +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT 10 +#define BCH_CTRL_CLR_RSVD3_MASK 0xF800u +#define BCH_CTRL_CLR_RSVD3_SHIFT 11 +#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD3_SHIFT))&BCH_CTRL_CLR_RSVD3_MASK) +#define BCH_CTRL_CLR_M2M_ENABLE_MASK 0x10000u +#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT 16 +#define BCH_CTRL_CLR_M2M_ENCODE_MASK 0x20000u +#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT 17 +#define BCH_CTRL_CLR_M2M_LAYOUT_MASK 0xC0000u +#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT 18 +#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_M2M_LAYOUT_SHIFT))&BCH_CTRL_CLR_M2M_LAYOUT_MASK) +#define BCH_CTRL_CLR_RSVD4_MASK 0x300000u +#define BCH_CTRL_CLR_RSVD4_SHIFT 20 +#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD4_SHIFT))&BCH_CTRL_CLR_RSVD4_MASK) +#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK 0x400000u +#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT 22 +#define BCH_CTRL_CLR_RSVD5_MASK 0x3F800000u +#define BCH_CTRL_CLR_RSVD5_SHIFT 23 +#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_CLR_RSVD5_SHIFT))&BCH_CTRL_CLR_RSVD5_MASK) +#define BCH_CTRL_CLR_CLKGATE_MASK 0x40000000u +#define BCH_CTRL_CLR_CLKGATE_SHIFT 30 +#define BCH_CTRL_CLR_SFTRST_MASK 0x80000000u +#define BCH_CTRL_CLR_SFTRST_SHIFT 31 +/* CTRL_TOG Bit Fields */ +#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_TOG_RSVD0_MASK 0x2u +#define BCH_CTRL_TOG_RSVD0_SHIFT 1 +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_TOG_RSVD1_MASK 0xF0u +#define BCH_CTRL_TOG_RSVD1_SHIFT 4 +#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD1_SHIFT))&BCH_CTRL_TOG_RSVD1_MASK) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK 0x100u +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT 8 +#define BCH_CTRL_TOG_RSVD2_MASK 0x200u +#define BCH_CTRL_TOG_RSVD2_SHIFT 9 +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK 0x400u +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT 10 +#define BCH_CTRL_TOG_RSVD3_MASK 0xF800u +#define BCH_CTRL_TOG_RSVD3_SHIFT 11 +#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD3_SHIFT))&BCH_CTRL_TOG_RSVD3_MASK) +#define BCH_CTRL_TOG_M2M_ENABLE_MASK 0x10000u +#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT 16 +#define BCH_CTRL_TOG_M2M_ENCODE_MASK 0x20000u +#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT 17 +#define BCH_CTRL_TOG_M2M_LAYOUT_MASK 0xC0000u +#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT 18 +#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_M2M_LAYOUT_SHIFT))&BCH_CTRL_TOG_M2M_LAYOUT_MASK) +#define BCH_CTRL_TOG_RSVD4_MASK 0x300000u +#define BCH_CTRL_TOG_RSVD4_SHIFT 20 +#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD4_SHIFT))&BCH_CTRL_TOG_RSVD4_MASK) +#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK 0x400000u +#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT 22 +#define BCH_CTRL_TOG_RSVD5_MASK 0x3F800000u +#define BCH_CTRL_TOG_RSVD5_SHIFT 23 +#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<BCH_CTRL_TOG_RSVD5_SHIFT))&BCH_CTRL_TOG_RSVD5_MASK) +#define BCH_CTRL_TOG_CLKGATE_MASK 0x40000000u +#define BCH_CTRL_TOG_CLKGATE_SHIFT 30 +#define BCH_CTRL_TOG_SFTRST_MASK 0x80000000u +#define BCH_CTRL_TOG_SFTRST_SHIFT 31 +/* STATUS0 Bit Fields */ +#define BCH_STATUS0_RSVD0_MASK 0x3u +#define BCH_STATUS0_RSVD0_SHIFT 0 +#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD0_SHIFT))&BCH_STATUS0_RSVD0_MASK) +#define BCH_STATUS0_UNCORRECTABLE_MASK 0x4u +#define BCH_STATUS0_UNCORRECTABLE_SHIFT 2 +#define BCH_STATUS0_CORRECTED_MASK 0x8u +#define BCH_STATUS0_CORRECTED_SHIFT 3 +#define BCH_STATUS0_ALLONES_MASK 0x10u +#define BCH_STATUS0_ALLONES_SHIFT 4 +#define BCH_STATUS0_RSVD1_MASK 0xE0u +#define BCH_STATUS0_RSVD1_SHIFT 5 +#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_RSVD1_SHIFT))&BCH_STATUS0_RSVD1_MASK) +#define BCH_STATUS0_STATUS_BLK0_MASK 0xFF00u +#define BCH_STATUS0_STATUS_BLK0_SHIFT 8 +#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_STATUS_BLK0_SHIFT))&BCH_STATUS0_STATUS_BLK0_MASK) +#define BCH_STATUS0_COMPLETED_CE_MASK 0xF0000u +#define BCH_STATUS0_COMPLETED_CE_SHIFT 16 +#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_COMPLETED_CE_SHIFT))&BCH_STATUS0_COMPLETED_CE_MASK) +#define BCH_STATUS0_HANDLE_MASK 0xFFF00000u +#define BCH_STATUS0_HANDLE_SHIFT 20 +#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_HANDLE_SHIFT))&BCH_STATUS0_HANDLE_MASK) +/* STATUS0_SET Bit Fields */ +#define BCH_STATUS0_SET_RSVD0_MASK 0x3u +#define BCH_STATUS0_SET_RSVD0_SHIFT 0 +#define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD0_SHIFT))&BCH_STATUS0_SET_RSVD0_MASK) +#define BCH_STATUS0_SET_UNCORRECTABLE_MASK 0x4u +#define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT 2 +#define BCH_STATUS0_SET_CORRECTED_MASK 0x8u +#define BCH_STATUS0_SET_CORRECTED_SHIFT 3 +#define BCH_STATUS0_SET_ALLONES_MASK 0x10u +#define BCH_STATUS0_SET_ALLONES_SHIFT 4 +#define BCH_STATUS0_SET_RSVD1_MASK 0xE0u +#define BCH_STATUS0_SET_RSVD1_SHIFT 5 +#define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_RSVD1_SHIFT))&BCH_STATUS0_SET_RSVD1_MASK) +#define BCH_STATUS0_SET_STATUS_BLK0_MASK 0xFF00u +#define BCH_STATUS0_SET_STATUS_BLK0_SHIFT 8 +#define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_STATUS_BLK0_SHIFT))&BCH_STATUS0_SET_STATUS_BLK0_MASK) +#define BCH_STATUS0_SET_COMPLETED_CE_MASK 0xF0000u +#define BCH_STATUS0_SET_COMPLETED_CE_SHIFT 16 +#define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_COMPLETED_CE_SHIFT))&BCH_STATUS0_SET_COMPLETED_CE_MASK) +#define BCH_STATUS0_SET_HANDLE_MASK 0xFFF00000u +#define BCH_STATUS0_SET_HANDLE_SHIFT 20 +#define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_SET_HANDLE_SHIFT))&BCH_STATUS0_SET_HANDLE_MASK) +/* STATUS0_CLR Bit Fields */ +#define BCH_STATUS0_CLR_RSVD0_MASK 0x3u +#define BCH_STATUS0_CLR_RSVD0_SHIFT 0 +#define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD0_SHIFT))&BCH_STATUS0_CLR_RSVD0_MASK) +#define BCH_STATUS0_CLR_UNCORRECTABLE_MASK 0x4u +#define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT 2 +#define BCH_STATUS0_CLR_CORRECTED_MASK 0x8u +#define BCH_STATUS0_CLR_CORRECTED_SHIFT 3 +#define BCH_STATUS0_CLR_ALLONES_MASK 0x10u +#define BCH_STATUS0_CLR_ALLONES_SHIFT 4 +#define BCH_STATUS0_CLR_RSVD1_MASK 0xE0u +#define BCH_STATUS0_CLR_RSVD1_SHIFT 5 +#define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_RSVD1_SHIFT))&BCH_STATUS0_CLR_RSVD1_MASK) +#define BCH_STATUS0_CLR_STATUS_BLK0_MASK 0xFF00u +#define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT 8 +#define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_STATUS_BLK0_SHIFT))&BCH_STATUS0_CLR_STATUS_BLK0_MASK) +#define BCH_STATUS0_CLR_COMPLETED_CE_MASK 0xF0000u +#define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT 16 +#define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_COMPLETED_CE_SHIFT))&BCH_STATUS0_CLR_COMPLETED_CE_MASK) +#define BCH_STATUS0_CLR_HANDLE_MASK 0xFFF00000u +#define BCH_STATUS0_CLR_HANDLE_SHIFT 20 +#define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_CLR_HANDLE_SHIFT))&BCH_STATUS0_CLR_HANDLE_MASK) +/* STATUS0_TOG Bit Fields */ +#define BCH_STATUS0_TOG_RSVD0_MASK 0x3u +#define BCH_STATUS0_TOG_RSVD0_SHIFT 0 +#define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD0_SHIFT))&BCH_STATUS0_TOG_RSVD0_MASK) +#define BCH_STATUS0_TOG_UNCORRECTABLE_MASK 0x4u +#define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT 2 +#define BCH_STATUS0_TOG_CORRECTED_MASK 0x8u +#define BCH_STATUS0_TOG_CORRECTED_SHIFT 3 +#define BCH_STATUS0_TOG_ALLONES_MASK 0x10u +#define BCH_STATUS0_TOG_ALLONES_SHIFT 4 +#define BCH_STATUS0_TOG_RSVD1_MASK 0xE0u +#define BCH_STATUS0_TOG_RSVD1_SHIFT 5 +#define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_RSVD1_SHIFT))&BCH_STATUS0_TOG_RSVD1_MASK) +#define BCH_STATUS0_TOG_STATUS_BLK0_MASK 0xFF00u +#define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT 8 +#define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_STATUS_BLK0_SHIFT))&BCH_STATUS0_TOG_STATUS_BLK0_MASK) +#define BCH_STATUS0_TOG_COMPLETED_CE_MASK 0xF0000u +#define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT 16 +#define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_COMPLETED_CE_SHIFT))&BCH_STATUS0_TOG_COMPLETED_CE_MASK) +#define BCH_STATUS0_TOG_HANDLE_MASK 0xFFF00000u +#define BCH_STATUS0_TOG_HANDLE_SHIFT 20 +#define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<BCH_STATUS0_TOG_HANDLE_SHIFT))&BCH_STATUS0_TOG_HANDLE_MASK) +/* MODE Bit Fields */ +#define BCH_MODE_ERASE_THRESHOLD_MASK 0xFFu +#define BCH_MODE_ERASE_THRESHOLD_SHIFT 0 +#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_ERASE_THRESHOLD_SHIFT))&BCH_MODE_ERASE_THRESHOLD_MASK) +#define BCH_MODE_RSVD_MASK 0xFFFFFF00u +#define BCH_MODE_RSVD_SHIFT 8 +#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_RSVD_SHIFT))&BCH_MODE_RSVD_MASK) +/* MODE_SET Bit Fields */ +#define BCH_MODE_SET_ERASE_THRESHOLD_MASK 0xFFu +#define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT 0 +#define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_ERASE_THRESHOLD_SHIFT))&BCH_MODE_SET_ERASE_THRESHOLD_MASK) +#define BCH_MODE_SET_RSVD_MASK 0xFFFFFF00u +#define BCH_MODE_SET_RSVD_SHIFT 8 +#define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_SET_RSVD_SHIFT))&BCH_MODE_SET_RSVD_MASK) +/* MODE_CLR Bit Fields */ +#define BCH_MODE_CLR_ERASE_THRESHOLD_MASK 0xFFu +#define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT 0 +#define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT))&BCH_MODE_CLR_ERASE_THRESHOLD_MASK) +#define BCH_MODE_CLR_RSVD_MASK 0xFFFFFF00u +#define BCH_MODE_CLR_RSVD_SHIFT 8 +#define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_CLR_RSVD_SHIFT))&BCH_MODE_CLR_RSVD_MASK) +/* MODE_TOG Bit Fields */ +#define BCH_MODE_TOG_ERASE_THRESHOLD_MASK 0xFFu +#define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT 0 +#define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT))&BCH_MODE_TOG_ERASE_THRESHOLD_MASK) +#define BCH_MODE_TOG_RSVD_MASK 0xFFFFFF00u +#define BCH_MODE_TOG_RSVD_SHIFT 8 +#define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_MODE_TOG_RSVD_SHIFT))&BCH_MODE_TOG_RSVD_MASK) +/* ENCODEPTR Bit Fields */ +#define BCH_ENCODEPTR_ADDR_MASK 0xFFFFFFFFu +#define BCH_ENCODEPTR_ADDR_SHIFT 0 +#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_ADDR_SHIFT))&BCH_ENCODEPTR_ADDR_MASK) +/* ENCODEPTR_SET Bit Fields */ +#define BCH_ENCODEPTR_SET_ADDR_MASK 0xFFFFFFFFu +#define BCH_ENCODEPTR_SET_ADDR_SHIFT 0 +#define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_SET_ADDR_SHIFT))&BCH_ENCODEPTR_SET_ADDR_MASK) +/* ENCODEPTR_CLR Bit Fields */ +#define BCH_ENCODEPTR_CLR_ADDR_MASK 0xFFFFFFFFu +#define BCH_ENCODEPTR_CLR_ADDR_SHIFT 0 +#define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_CLR_ADDR_SHIFT))&BCH_ENCODEPTR_CLR_ADDR_MASK) +/* ENCODEPTR_TOG Bit Fields */ +#define BCH_ENCODEPTR_TOG_ADDR_MASK 0xFFFFFFFFu +#define BCH_ENCODEPTR_TOG_ADDR_SHIFT 0 +#define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_ENCODEPTR_TOG_ADDR_SHIFT))&BCH_ENCODEPTR_TOG_ADDR_MASK) +/* DATAPTR Bit Fields */ +#define BCH_DATAPTR_ADDR_MASK 0xFFFFFFFFu +#define BCH_DATAPTR_ADDR_SHIFT 0 +#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_ADDR_SHIFT))&BCH_DATAPTR_ADDR_MASK) +/* DATAPTR_SET Bit Fields */ +#define BCH_DATAPTR_SET_ADDR_MASK 0xFFFFFFFFu +#define BCH_DATAPTR_SET_ADDR_SHIFT 0 +#define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_SET_ADDR_SHIFT))&BCH_DATAPTR_SET_ADDR_MASK) +/* DATAPTR_CLR Bit Fields */ +#define BCH_DATAPTR_CLR_ADDR_MASK 0xFFFFFFFFu +#define BCH_DATAPTR_CLR_ADDR_SHIFT 0 +#define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_CLR_ADDR_SHIFT))&BCH_DATAPTR_CLR_ADDR_MASK) +/* DATAPTR_TOG Bit Fields */ +#define BCH_DATAPTR_TOG_ADDR_MASK 0xFFFFFFFFu +#define BCH_DATAPTR_TOG_ADDR_SHIFT 0 +#define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_DATAPTR_TOG_ADDR_SHIFT))&BCH_DATAPTR_TOG_ADDR_MASK) +/* METAPTR Bit Fields */ +#define BCH_METAPTR_ADDR_MASK 0xFFFFFFFFu +#define BCH_METAPTR_ADDR_SHIFT 0 +#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_ADDR_SHIFT))&BCH_METAPTR_ADDR_MASK) +/* METAPTR_SET Bit Fields */ +#define BCH_METAPTR_SET_ADDR_MASK 0xFFFFFFFFu +#define BCH_METAPTR_SET_ADDR_SHIFT 0 +#define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_SET_ADDR_SHIFT))&BCH_METAPTR_SET_ADDR_MASK) +/* METAPTR_CLR Bit Fields */ +#define BCH_METAPTR_CLR_ADDR_MASK 0xFFFFFFFFu +#define BCH_METAPTR_CLR_ADDR_SHIFT 0 +#define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_CLR_ADDR_SHIFT))&BCH_METAPTR_CLR_ADDR_MASK) +/* METAPTR_TOG Bit Fields */ +#define BCH_METAPTR_TOG_ADDR_MASK 0xFFFFFFFFu +#define BCH_METAPTR_TOG_ADDR_SHIFT 0 +#define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<BCH_METAPTR_TOG_ADDR_SHIFT))&BCH_METAPTR_TOG_ADDR_MASK) +/* LAYOUTSELECT Bit Fields */ +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK 0x3u +#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT 0 +#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK 0xCu +#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT 2 +#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK 0x30u +#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT 4 +#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK 0xC0u +#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT 6 +#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK 0x300u +#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT 8 +#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK 0xC00u +#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT 10 +#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK 0x3000u +#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT 12 +#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK 0xC000u +#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT 14 +#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK 0x30000u +#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT 16 +#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK 0xC0000u +#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT 18 +#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK 0x300000u +#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT 20 +#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK 0xC00000u +#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT 22 +#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK 0x3000000u +#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT 24 +#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK 0xC000000u +#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT 26 +#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK 0x30000000u +#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT 28 +#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK 0xC0000000u +#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT 30 +#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CS15_SELECT_MASK) +/* LAYOUTSELECT_SET Bit Fields */ +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK 0x3u +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT 0 +#define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK 0xCu +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT 2 +#define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK 0x30u +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT 4 +#define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK 0xC0u +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT 6 +#define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK 0x300u +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT 8 +#define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK 0xC00u +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT 10 +#define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK 0x3000u +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT 12 +#define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK 0xC000u +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT 14 +#define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK 0x30000u +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT 16 +#define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK 0xC0000u +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT 18 +#define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK 0x300000u +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT 20 +#define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK 0xC00000u +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT 22 +#define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK 0x3000000u +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT 24 +#define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK 0xC000000u +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT 26 +#define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK 0x30000000u +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT 28 +#define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK 0xC0000000u +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT 30 +#define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) +/* LAYOUTSELECT_CLR Bit Fields */ +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK 0x3u +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT 0 +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK 0xCu +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT 2 +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK 0x30u +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT 4 +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK 0xC0u +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT 6 +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK 0x300u +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT 8 +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK 0xC00u +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT 10 +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK 0x3000u +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT 12 +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK 0xC000u +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT 14 +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK 0x30000u +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT 16 +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK 0xC0000u +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT 18 +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK 0x300000u +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT 20 +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK 0xC00000u +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT 22 +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK 0x3000000u +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT 24 +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK 0xC000000u +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT 26 +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK 0x30000000u +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT 28 +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK 0xC0000000u +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT 30 +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) +/* LAYOUTSELECT_TOG Bit Fields */ +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK 0x3u +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT 0 +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK 0xCu +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT 2 +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK 0x30u +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT 4 +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK 0xC0u +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT 6 +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK 0x300u +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT 8 +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK 0xC00u +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT 10 +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK 0x3000u +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT 12 +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK 0xC000u +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT 14 +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK 0x30000u +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT 16 +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK 0xC0000u +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT 18 +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK 0x300000u +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT 20 +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK 0xC00000u +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT 22 +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK 0x3000000u +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT 24 +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK 0xC000000u +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT 26 +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK 0x30000000u +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT 28 +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK 0xC0000000u +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT 30 +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT))&BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) +/* FLASH0LAYOUT0 Bit Fields */ +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT0_ECC0_MASK 0xF800u +#define BCH_FLASH0LAYOUT0_ECC0_SHIFT 11 +#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT 24 +#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_NBLOCKS_MASK) +/* FLASH0LAYOUT0_SET Bit Fields */ +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT0_SET_ECC0_MASK 0xF800u +#define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT 11 +#define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT 24 +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) +/* FLASH0LAYOUT0_CLR Bit Fields */ +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK 0xF800u +#define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT 11 +#define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT 24 +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) +/* FLASH0LAYOUT0_TOG Bit Fields */ +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK 0xF800u +#define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT 11 +#define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT 24 +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) +/* FLASH0LAYOUT1 Bit Fields */ +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT1_ECCN_MASK 0xF800u +#define BCH_FLASH0LAYOUT1_ECCN_SHIFT 11 +#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) +/* FLASH0LAYOUT1_SET Bit Fields */ +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT1_SET_ECCN_MASK 0xF800u +#define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT 11 +#define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) +/* FLASH0LAYOUT1_CLR Bit Fields */ +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK 0xF800u +#define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT 11 +#define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) +/* FLASH0LAYOUT1_TOG Bit Fields */ +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK 0xF800u +#define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT 11 +#define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) +/* FLASH1LAYOUT0 Bit Fields */ +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT0_ECC0_MASK 0xF800u +#define BCH_FLASH1LAYOUT0_ECC0_SHIFT 11 +#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT 24 +#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_NBLOCKS_MASK) +/* FLASH1LAYOUT0_SET Bit Fields */ +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT0_SET_ECC0_MASK 0xF800u +#define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT 11 +#define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT 24 +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) +/* FLASH1LAYOUT0_CLR Bit Fields */ +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK 0xF800u +#define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT 11 +#define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT 24 +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) +/* FLASH1LAYOUT0_TOG Bit Fields */ +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK 0xF800u +#define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT 11 +#define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT 24 +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) +/* FLASH1LAYOUT1 Bit Fields */ +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT1_ECCN_MASK 0xF800u +#define BCH_FLASH1LAYOUT1_ECCN_SHIFT 11 +#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) +/* FLASH1LAYOUT1_SET Bit Fields */ +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT1_SET_ECCN_MASK 0xF800u +#define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT 11 +#define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) +/* FLASH1LAYOUT1_CLR Bit Fields */ +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK 0xF800u +#define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT 11 +#define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) +/* FLASH1LAYOUT1_TOG Bit Fields */ +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK 0xF800u +#define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT 11 +#define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) +/* FLASH2LAYOUT0 Bit Fields */ +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT0_ECC0_MASK 0xF800u +#define BCH_FLASH2LAYOUT0_ECC0_SHIFT 11 +#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT 24 +#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_NBLOCKS_MASK) +/* FLASH2LAYOUT0_SET Bit Fields */ +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT0_SET_ECC0_MASK 0xF800u +#define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT 11 +#define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT 24 +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) +/* FLASH2LAYOUT0_CLR Bit Fields */ +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK 0xF800u +#define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT 11 +#define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT 24 +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) +/* FLASH2LAYOUT0_TOG Bit Fields */ +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK 0xF800u +#define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT 11 +#define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT 24 +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) +/* FLASH2LAYOUT1 Bit Fields */ +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT1_ECCN_MASK 0xF800u +#define BCH_FLASH2LAYOUT1_ECCN_SHIFT 11 +#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) +/* FLASH2LAYOUT1_SET Bit Fields */ +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT1_SET_ECCN_MASK 0xF800u +#define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT 11 +#define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) +/* FLASH2LAYOUT1_CLR Bit Fields */ +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK 0xF800u +#define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT 11 +#define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) +/* FLASH2LAYOUT1_TOG Bit Fields */ +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK 0xF800u +#define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT 11 +#define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) +/* FLASH3LAYOUT0 Bit Fields */ +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT0_ECC0_MASK 0xF800u +#define BCH_FLASH3LAYOUT0_ECC0_SHIFT 11 +#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT 24 +#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_NBLOCKS_MASK) +/* FLASH3LAYOUT0_SET Bit Fields */ +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT0_SET_ECC0_MASK 0xF800u +#define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT 11 +#define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT 24 +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) +/* FLASH3LAYOUT0_CLR Bit Fields */ +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK 0xF800u +#define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT 11 +#define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT 24 +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) +/* FLASH3LAYOUT0_TOG Bit Fields */ +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK 0xF800u +#define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT 11 +#define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT))&BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK 0xFF0000u +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT))&BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK 0xFF000000u +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT 24 +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT))&BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) +/* FLASH3LAYOUT1 Bit Fields */ +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT1_ECCN_MASK 0xF800u +#define BCH_FLASH3LAYOUT1_ECCN_SHIFT 11 +#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) +/* FLASH3LAYOUT1_SET Bit Fields */ +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT1_SET_ECCN_MASK 0xF800u +#define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT 11 +#define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) +/* FLASH3LAYOUT1_CLR Bit Fields */ +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK 0xF800u +#define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT 11 +#define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) +/* FLASH3LAYOUT1_TOG Bit Fields */ +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK 0x3FFu +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT 0 +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK 0x400u +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT 10 +#define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK 0xF800u +#define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT 11 +#define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT))&BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK 0xFFFF0000u +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT 16 +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x))<<BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT))&BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) +/* DEBUG0 Bit Fields */ +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3Fu +#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT 0 +#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_RSVD0_MASK 0xC0u +#define BCH_DEBUG0_RSVD0_SHIFT 6 +#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD0_SHIFT))&BCH_DEBUG0_RSVD0_MASK) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK 0x100u +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT 8 +#define BCH_DEBUG0_KES_DEBUG_STALL_MASK 0x200u +#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT 9 +#define BCH_DEBUG0_KES_DEBUG_STEP_MASK 0x400u +#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT 10 +#define BCH_DEBUG0_KES_STANDALONE_MASK 0x800u +#define BCH_DEBUG0_KES_STANDALONE_SHIFT 11 +#define BCH_DEBUG0_KES_DEBUG_KICK_MASK 0x1000u +#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT 12 +#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK 0x2000u +#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT 13 +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK 0x8000u +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT 15 +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_RSVD1_MASK 0xFE000000u +#define BCH_DEBUG0_RSVD1_SHIFT 25 +#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_RSVD1_SHIFT))&BCH_DEBUG0_RSVD1_MASK) +/* DEBUG0_SET Bit Fields */ +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK 0x3Fu +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT 0 +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_SET_RSVD0_MASK 0xC0u +#define BCH_DEBUG0_SET_RSVD0_SHIFT 6 +#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD0_SHIFT))&BCH_DEBUG0_SET_RSVD0_MASK) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK 0x100u +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT 8 +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK 0x200u +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT 9 +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK 0x400u +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT 10 +#define BCH_DEBUG0_SET_KES_STANDALONE_MASK 0x800u +#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT 11 +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK 0x1000u +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT 12 +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK 0x2000u +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT 13 +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK 0x8000u +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT 15 +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_SET_RSVD1_MASK 0xFE000000u +#define BCH_DEBUG0_SET_RSVD1_SHIFT 25 +#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_SET_RSVD1_SHIFT))&BCH_DEBUG0_SET_RSVD1_MASK) +/* DEBUG0_CLR Bit Fields */ +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK 0x3Fu +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT 0 +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_CLR_RSVD0_MASK 0xC0u +#define BCH_DEBUG0_CLR_RSVD0_SHIFT 6 +#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD0_SHIFT))&BCH_DEBUG0_CLR_RSVD0_MASK) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK 0x100u +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT 8 +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK 0x200u +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT 9 +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK 0x400u +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT 10 +#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK 0x800u +#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT 11 +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK 0x1000u +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT 12 +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK 0x2000u +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT 13 +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK 0x8000u +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT 15 +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_CLR_RSVD1_MASK 0xFE000000u +#define BCH_DEBUG0_CLR_RSVD1_SHIFT 25 +#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_CLR_RSVD1_SHIFT))&BCH_DEBUG0_CLR_RSVD1_MASK) +/* DEBUG0_TOG Bit Fields */ +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK 0x3Fu +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT 0 +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT))&BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_TOG_RSVD0_MASK 0xC0u +#define BCH_DEBUG0_TOG_RSVD0_SHIFT 6 +#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD0_SHIFT))&BCH_DEBUG0_TOG_RSVD0_MASK) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK 0x100u +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT 8 +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK 0x200u +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT 9 +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK 0x400u +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT 10 +#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK 0x800u +#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT 11 +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK 0x1000u +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT 12 +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK 0x2000u +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT 13 +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK 0x4000u +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT 14 +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK 0x8000u +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT 15 +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK 0x1FF0000u +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT 16 +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT))&BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_TOG_RSVD1_MASK 0xFE000000u +#define BCH_DEBUG0_TOG_RSVD1_SHIFT 25 +#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG0_TOG_RSVD1_SHIFT))&BCH_DEBUG0_TOG_RSVD1_MASK) +/* DBGKESREAD Bit Fields */ +#define BCH_DBGKESREAD_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGKESREAD_VALUES_SHIFT 0 +#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_VALUES_SHIFT))&BCH_DBGKESREAD_VALUES_MASK) +/* DBGKESREAD_SET Bit Fields */ +#define BCH_DBGKESREAD_SET_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGKESREAD_SET_VALUES_SHIFT 0 +#define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_SET_VALUES_SHIFT))&BCH_DBGKESREAD_SET_VALUES_MASK) +/* DBGKESREAD_CLR Bit Fields */ +#define BCH_DBGKESREAD_CLR_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGKESREAD_CLR_VALUES_SHIFT 0 +#define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_CLR_VALUES_SHIFT))&BCH_DBGKESREAD_CLR_VALUES_MASK) +/* DBGKESREAD_TOG Bit Fields */ +#define BCH_DBGKESREAD_TOG_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGKESREAD_TOG_VALUES_SHIFT 0 +#define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGKESREAD_TOG_VALUES_SHIFT))&BCH_DBGKESREAD_TOG_VALUES_MASK) +/* DBGCSFEREAD Bit Fields */ +#define BCH_DBGCSFEREAD_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGCSFEREAD_VALUES_SHIFT 0 +#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_VALUES_SHIFT))&BCH_DBGCSFEREAD_VALUES_MASK) +/* DBGCSFEREAD_SET Bit Fields */ +#define BCH_DBGCSFEREAD_SET_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGCSFEREAD_SET_VALUES_SHIFT 0 +#define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_SET_VALUES_SHIFT))&BCH_DBGCSFEREAD_SET_VALUES_MASK) +/* DBGCSFEREAD_CLR Bit Fields */ +#define BCH_DBGCSFEREAD_CLR_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT 0 +#define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_CLR_VALUES_SHIFT))&BCH_DBGCSFEREAD_CLR_VALUES_MASK) +/* DBGCSFEREAD_TOG Bit Fields */ +#define BCH_DBGCSFEREAD_TOG_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT 0 +#define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGCSFEREAD_TOG_VALUES_SHIFT))&BCH_DBGCSFEREAD_TOG_VALUES_MASK) +/* DBGSYNDGENREAD Bit Fields */ +#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGSYNDGENREAD_VALUES_SHIFT 0 +#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_VALUES_MASK) +/* DBGSYNDGENREAD_SET Bit Fields */ +#define BCH_DBGSYNDGENREAD_SET_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT 0 +#define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_SET_VALUES_MASK) +/* DBGSYNDGENREAD_CLR Bit Fields */ +#define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT 0 +#define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) +/* DBGSYNDGENREAD_TOG Bit Fields */ +#define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT 0 +#define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT))&BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) +/* DBGAHBMREAD Bit Fields */ +#define BCH_DBGAHBMREAD_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGAHBMREAD_VALUES_SHIFT 0 +#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_VALUES_SHIFT))&BCH_DBGAHBMREAD_VALUES_MASK) +/* DBGAHBMREAD_SET Bit Fields */ +#define BCH_DBGAHBMREAD_SET_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGAHBMREAD_SET_VALUES_SHIFT 0 +#define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_SET_VALUES_SHIFT))&BCH_DBGAHBMREAD_SET_VALUES_MASK) +/* DBGAHBMREAD_CLR Bit Fields */ +#define BCH_DBGAHBMREAD_CLR_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT 0 +#define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_CLR_VALUES_SHIFT))&BCH_DBGAHBMREAD_CLR_VALUES_MASK) +/* DBGAHBMREAD_TOG Bit Fields */ +#define BCH_DBGAHBMREAD_TOG_VALUES_MASK 0xFFFFFFFFu +#define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT 0 +#define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x))<<BCH_DBGAHBMREAD_TOG_VALUES_SHIFT))&BCH_DBGAHBMREAD_TOG_VALUES_MASK) +/* BLOCKNAME Bit Fields */ +#define BCH_BLOCKNAME_NAME_MASK 0xFFFFFFFFu +#define BCH_BLOCKNAME_NAME_SHIFT 0 +#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_NAME_SHIFT))&BCH_BLOCKNAME_NAME_MASK) +/* BLOCKNAME_SET Bit Fields */ +#define BCH_BLOCKNAME_SET_NAME_MASK 0xFFFFFFFFu +#define BCH_BLOCKNAME_SET_NAME_SHIFT 0 +#define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_SET_NAME_SHIFT))&BCH_BLOCKNAME_SET_NAME_MASK) +/* BLOCKNAME_CLR Bit Fields */ +#define BCH_BLOCKNAME_CLR_NAME_MASK 0xFFFFFFFFu +#define BCH_BLOCKNAME_CLR_NAME_SHIFT 0 +#define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_CLR_NAME_SHIFT))&BCH_BLOCKNAME_CLR_NAME_MASK) +/* BLOCKNAME_TOG Bit Fields */ +#define BCH_BLOCKNAME_TOG_NAME_MASK 0xFFFFFFFFu +#define BCH_BLOCKNAME_TOG_NAME_SHIFT 0 +#define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x))<<BCH_BLOCKNAME_TOG_NAME_SHIFT))&BCH_BLOCKNAME_TOG_NAME_MASK) +/* VERSION Bit Fields */ +#define BCH_VERSION_STEP_MASK 0xFFFFu +#define BCH_VERSION_STEP_SHIFT 0 +#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_STEP_SHIFT))&BCH_VERSION_STEP_MASK) +#define BCH_VERSION_MINOR_MASK 0xFF0000u +#define BCH_VERSION_MINOR_SHIFT 16 +#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MINOR_SHIFT))&BCH_VERSION_MINOR_MASK) +#define BCH_VERSION_MAJOR_MASK 0xFF000000u +#define BCH_VERSION_MAJOR_SHIFT 24 +#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_MAJOR_SHIFT))&BCH_VERSION_MAJOR_MASK) +/* VERSION_SET Bit Fields */ +#define BCH_VERSION_SET_STEP_MASK 0xFFFFu +#define BCH_VERSION_SET_STEP_SHIFT 0 +#define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_STEP_SHIFT))&BCH_VERSION_SET_STEP_MASK) +#define BCH_VERSION_SET_MINOR_MASK 0xFF0000u +#define BCH_VERSION_SET_MINOR_SHIFT 16 +#define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MINOR_SHIFT))&BCH_VERSION_SET_MINOR_MASK) +#define BCH_VERSION_SET_MAJOR_MASK 0xFF000000u +#define BCH_VERSION_SET_MAJOR_SHIFT 24 +#define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_SET_MAJOR_SHIFT))&BCH_VERSION_SET_MAJOR_MASK) +/* VERSION_CLR Bit Fields */ +#define BCH_VERSION_CLR_STEP_MASK 0xFFFFu +#define BCH_VERSION_CLR_STEP_SHIFT 0 +#define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_STEP_SHIFT))&BCH_VERSION_CLR_STEP_MASK) +#define BCH_VERSION_CLR_MINOR_MASK 0xFF0000u +#define BCH_VERSION_CLR_MINOR_SHIFT 16 +#define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MINOR_SHIFT))&BCH_VERSION_CLR_MINOR_MASK) +#define BCH_VERSION_CLR_MAJOR_MASK 0xFF000000u +#define BCH_VERSION_CLR_MAJOR_SHIFT 24 +#define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_CLR_MAJOR_SHIFT))&BCH_VERSION_CLR_MAJOR_MASK) +/* VERSION_TOG Bit Fields */ +#define BCH_VERSION_TOG_STEP_MASK 0xFFFFu +#define BCH_VERSION_TOG_STEP_SHIFT 0 +#define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_STEP_SHIFT))&BCH_VERSION_TOG_STEP_MASK) +#define BCH_VERSION_TOG_MINOR_MASK 0xFF0000u +#define BCH_VERSION_TOG_MINOR_SHIFT 16 +#define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MINOR_SHIFT))&BCH_VERSION_TOG_MINOR_MASK) +#define BCH_VERSION_TOG_MAJOR_MASK 0xFF000000u +#define BCH_VERSION_TOG_MAJOR_SHIFT 24 +#define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<BCH_VERSION_TOG_MAJOR_SHIFT))&BCH_VERSION_TOG_MAJOR_MASK) +/* DEBUG1 Bit Fields */ +#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK 0x1FFu +#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT 0 +#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_RSVD_MASK 0x7FFFFE00u +#define BCH_DEBUG1_RSVD_SHIFT 9 +#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_RSVD_SHIFT))&BCH_DEBUG1_RSVD_MASK) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK 0x80000000u +#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT 31 +/* DEBUG1_SET Bit Fields */ +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK 0x1FFu +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT 0 +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_SET_RSVD_MASK 0x7FFFFE00u +#define BCH_DEBUG1_SET_RSVD_SHIFT 9 +#define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_SET_RSVD_SHIFT))&BCH_DEBUG1_SET_RSVD_MASK) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK 0x80000000u +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT 31 +/* DEBUG1_CLR Bit Fields */ +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK 0x1FFu +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT 0 +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_CLR_RSVD_MASK 0x7FFFFE00u +#define BCH_DEBUG1_CLR_RSVD_SHIFT 9 +#define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_CLR_RSVD_SHIFT))&BCH_DEBUG1_CLR_RSVD_MASK) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK 0x80000000u +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT 31 +/* DEBUG1_TOG Bit Fields */ +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK 0x1FFu +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT 0 +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT))&BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_TOG_RSVD_MASK 0x7FFFFE00u +#define BCH_DEBUG1_TOG_RSVD_SHIFT 9 +#define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x))<<BCH_DEBUG1_TOG_RSVD_SHIFT))&BCH_DEBUG1_TOG_RSVD_MASK) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK 0x80000000u +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT 31 + +/*! + * @} + */ /* end of group BCH_Register_Masks */ + + +/* BCH - Peripheral instance base addresses */ +/** Peripheral BCH base address */ +#define BCH_BASE (0x33004000u) +/** Peripheral BCH base pointer */ +#define BCH ((BCH_Type *)BCH_BASE) +#define BCH_BASE_PTR (BCH) +/** Array initializer of BCH peripheral base adresses */ +#define BCH_BASE_ADDRS { BCH_BASE } +/** Array initializer of BCH peripheral base pointers */ +#define BCH_BASE_PTRS { BCH } + +/* ---------------------------------------------------------------------------- + -- BCH - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Accessor_Macros BCH - Register accessor macros + * @{ + */ + + +/* BCH - Register instance definitions */ +/* BCH */ +#define BCH_CTRL BCH_CTRL_REG(BCH_BASE_PTR) +#define BCH_CTRL_SET BCH_CTRL_SET_REG(BCH_BASE_PTR) +#define BCH_CTRL_CLR BCH_CTRL_CLR_REG(BCH_BASE_PTR) +#define BCH_CTRL_TOG BCH_CTRL_TOG_REG(BCH_BASE_PTR) +#define BCH_STATUS0 BCH_STATUS0_REG(BCH_BASE_PTR) +#define BCH_STATUS0_SET BCH_STATUS0_SET_REG(BCH_BASE_PTR) +#define BCH_STATUS0_CLR BCH_STATUS0_CLR_REG(BCH_BASE_PTR) +#define BCH_STATUS0_TOG BCH_STATUS0_TOG_REG(BCH_BASE_PTR) +#define BCH_MODE BCH_MODE_REG(BCH_BASE_PTR) +#define BCH_MODE_SET BCH_MODE_SET_REG(BCH_BASE_PTR) +#define BCH_MODE_CLR BCH_MODE_CLR_REG(BCH_BASE_PTR) +#define BCH_MODE_TOG BCH_MODE_TOG_REG(BCH_BASE_PTR) +#define BCH_ENCODEPTR BCH_ENCODEPTR_REG(BCH_BASE_PTR) +#define BCH_ENCODEPTR_SET BCH_ENCODEPTR_SET_REG(BCH_BASE_PTR) +#define BCH_ENCODEPTR_CLR BCH_ENCODEPTR_CLR_REG(BCH_BASE_PTR) +#define BCH_ENCODEPTR_TOG BCH_ENCODEPTR_TOG_REG(BCH_BASE_PTR) +#define BCH_DATAPTR BCH_DATAPTR_REG(BCH_BASE_PTR) +#define BCH_DATAPTR_SET BCH_DATAPTR_SET_REG(BCH_BASE_PTR) +#define BCH_DATAPTR_CLR BCH_DATAPTR_CLR_REG(BCH_BASE_PTR) +#define BCH_DATAPTR_TOG BCH_DATAPTR_TOG_REG(BCH_BASE_PTR) +#define BCH_METAPTR BCH_METAPTR_REG(BCH_BASE_PTR) +#define BCH_METAPTR_SET BCH_METAPTR_SET_REG(BCH_BASE_PTR) +#define BCH_METAPTR_CLR BCH_METAPTR_CLR_REG(BCH_BASE_PTR) +#define BCH_METAPTR_TOG BCH_METAPTR_TOG_REG(BCH_BASE_PTR) +#define BCH_LAYOUTSELECT BCH_LAYOUTSELECT_REG(BCH_BASE_PTR) +#define BCH_LAYOUTSELECT_SET BCH_LAYOUTSELECT_SET_REG(BCH_BASE_PTR) +#define BCH_LAYOUTSELECT_CLR BCH_LAYOUTSELECT_CLR_REG(BCH_BASE_PTR) +#define BCH_LAYOUTSELECT_TOG BCH_LAYOUTSELECT_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT0 BCH_FLASH0LAYOUT0_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT0_SET BCH_FLASH0LAYOUT0_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT0_CLR BCH_FLASH0LAYOUT0_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT0_TOG BCH_FLASH0LAYOUT0_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT1 BCH_FLASH0LAYOUT1_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT1_SET BCH_FLASH0LAYOUT1_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT1_CLR BCH_FLASH0LAYOUT1_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH0LAYOUT1_TOG BCH_FLASH0LAYOUT1_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT0 BCH_FLASH1LAYOUT0_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT0_SET BCH_FLASH1LAYOUT0_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT0_CLR BCH_FLASH1LAYOUT0_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT0_TOG BCH_FLASH1LAYOUT0_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT1 BCH_FLASH1LAYOUT1_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT1_SET BCH_FLASH1LAYOUT1_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT1_CLR BCH_FLASH1LAYOUT1_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH1LAYOUT1_TOG BCH_FLASH1LAYOUT1_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT0 BCH_FLASH2LAYOUT0_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT0_SET BCH_FLASH2LAYOUT0_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT0_CLR BCH_FLASH2LAYOUT0_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT0_TOG BCH_FLASH2LAYOUT0_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT1 BCH_FLASH2LAYOUT1_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT1_SET BCH_FLASH2LAYOUT1_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT1_CLR BCH_FLASH2LAYOUT1_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH2LAYOUT1_TOG BCH_FLASH2LAYOUT1_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT0 BCH_FLASH3LAYOUT0_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT0_SET BCH_FLASH3LAYOUT0_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT0_CLR BCH_FLASH3LAYOUT0_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT0_TOG BCH_FLASH3LAYOUT0_TOG_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT1 BCH_FLASH3LAYOUT1_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT1_SET BCH_FLASH3LAYOUT1_SET_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT1_CLR BCH_FLASH3LAYOUT1_CLR_REG(BCH_BASE_PTR) +#define BCH_FLASH3LAYOUT1_TOG BCH_FLASH3LAYOUT1_TOG_REG(BCH_BASE_PTR) +#define BCH_DEBUG0 BCH_DEBUG0_REG(BCH_BASE_PTR) +#define BCH_DEBUG0_SET BCH_DEBUG0_SET_REG(BCH_BASE_PTR) +#define BCH_DEBUG0_CLR BCH_DEBUG0_CLR_REG(BCH_BASE_PTR) +#define BCH_DEBUG0_TOG BCH_DEBUG0_TOG_REG(BCH_BASE_PTR) +#define BCH_DBGKESREAD BCH_DBGKESREAD_REG(BCH_BASE_PTR) +#define BCH_DBGKESREAD_SET BCH_DBGKESREAD_SET_REG(BCH_BASE_PTR) +#define BCH_DBGKESREAD_CLR BCH_DBGKESREAD_CLR_REG(BCH_BASE_PTR) +#define BCH_DBGKESREAD_TOG BCH_DBGKESREAD_TOG_REG(BCH_BASE_PTR) +#define BCH_DBGCSFEREAD BCH_DBGCSFEREAD_REG(BCH_BASE_PTR) +#define BCH_DBGCSFEREAD_SET BCH_DBGCSFEREAD_SET_REG(BCH_BASE_PTR) +#define BCH_DBGCSFEREAD_CLR BCH_DBGCSFEREAD_CLR_REG(BCH_BASE_PTR) +#define BCH_DBGCSFEREAD_TOG BCH_DBGCSFEREAD_TOG_REG(BCH_BASE_PTR) +#define BCH_DBGSYNDGENREAD BCH_DBGSYNDGENREAD_REG(BCH_BASE_PTR) +#define BCH_DBGSYNDGENREAD_SET BCH_DBGSYNDGENREAD_SET_REG(BCH_BASE_PTR) +#define BCH_DBGSYNDGENREAD_CLR BCH_DBGSYNDGENREAD_CLR_REG(BCH_BASE_PTR) +#define BCH_DBGSYNDGENREAD_TOG BCH_DBGSYNDGENREAD_TOG_REG(BCH_BASE_PTR) +#define BCH_DBGAHBMREAD BCH_DBGAHBMREAD_REG(BCH_BASE_PTR) +#define BCH_DBGAHBMREAD_SET BCH_DBGAHBMREAD_SET_REG(BCH_BASE_PTR) +#define BCH_DBGAHBMREAD_CLR BCH_DBGAHBMREAD_CLR_REG(BCH_BASE_PTR) +#define BCH_DBGAHBMREAD_TOG BCH_DBGAHBMREAD_TOG_REG(BCH_BASE_PTR) +#define BCH_BLOCKNAME BCH_BLOCKNAME_REG(BCH_BASE_PTR) +#define BCH_BLOCKNAME_SET BCH_BLOCKNAME_SET_REG(BCH_BASE_PTR) +#define BCH_BLOCKNAME_CLR BCH_BLOCKNAME_CLR_REG(BCH_BASE_PTR) +#define BCH_BLOCKNAME_TOG BCH_BLOCKNAME_TOG_REG(BCH_BASE_PTR) +#define BCH_VERSION BCH_VERSION_REG(BCH_BASE_PTR) +#define BCH_VERSION_SET BCH_VERSION_SET_REG(BCH_BASE_PTR) +#define BCH_VERSION_CLR BCH_VERSION_CLR_REG(BCH_BASE_PTR) +#define BCH_VERSION_TOG BCH_VERSION_TOG_REG(BCH_BASE_PTR) +#define BCH_DEBUG1 BCH_DEBUG1_REG(BCH_BASE_PTR) +#define BCH_DEBUG1_SET BCH_DEBUG1_SET_REG(BCH_BASE_PTR) +#define BCH_DEBUG1_CLR BCH_DEBUG1_CLR_REG(BCH_BASE_PTR) +#define BCH_DEBUG1_TOG BCH_DEBUG1_TOG_REG(BCH_BASE_PTR) + +/*! + * @} + */ /* end of group BCH_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group BCH_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[48]; + struct { /**< offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_3[1024]; + __IO uint32_t RXIMR[64]; /**< RX Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, Address: Base address + 9E0h offset */ +} CAN_Type, *CAN_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- FLEXCAN - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros + * @{ + */ + + +/* FLEXCAN - Register accessors */ +#define CAN_MCR_REG(base) ((base)->MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK2_REG(base) ((base)->IMASK2) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG2_REG(base) ((base)->IFLAG2) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_CS_COUNT 64 +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_ID_COUNT 64 +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD0_COUNT 64 +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_WORD1_COUNT 64 +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) +#define CAN_RXIMR_COUNT 64 +#define CAN_GFWR_REG(base) ((base)->GFWR) + +/*! + * @} + */ /* end of group CAN_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK 0x300u +#define CAN_MCR_IDAM_SHIFT 8 +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK 0x1000u +#define CAN_MCR_AEN_SHIFT 12 +#define CAN_MCR_LPRIO_EN_MASK 0x2000u +#define CAN_MCR_LPRIO_EN_SHIFT 13 +#define CAN_MCR_IRMQ_MASK 0x10000u +#define CAN_MCR_IRMQ_SHIFT 16 +#define CAN_MCR_SRX_DIS_MASK 0x20000u +#define CAN_MCR_SRX_DIS_SHIFT 17 +#define CAN_MCR_WAK_SRC_MASK 0x80000u +#define CAN_MCR_WAK_SRC_SHIFT 19 +#define CAN_MCR_LPM_ACK_MASK 0x100000u +#define CAN_MCR_LPM_ACK_SHIFT 20 +#define CAN_MCR_WRN_EN_MASK 0x200000u +#define CAN_MCR_WRN_EN_SHIFT 21 +#define CAN_MCR_SLF_WAK_MASK 0x400000u +#define CAN_MCR_SLF_WAK_SHIFT 22 +#define CAN_MCR_SUPV_MASK 0x800000u +#define CAN_MCR_SUPV_SHIFT 23 +#define CAN_MCR_FRZ_ACK_MASK 0x1000000u +#define CAN_MCR_FRZ_ACK_SHIFT 24 +#define CAN_MCR_SOFT_RST_MASK 0x2000000u +#define CAN_MCR_SOFT_RST_SHIFT 25 +#define CAN_MCR_WAK_MSK_MASK 0x4000000u +#define CAN_MCR_WAK_MSK_SHIFT 26 +#define CAN_MCR_NOT_RDY_MASK 0x8000000u +#define CAN_MCR_NOT_RDY_SHIFT 27 +#define CAN_MCR_HALT_MASK 0x10000000u +#define CAN_MCR_HALT_SHIFT 28 +#define CAN_MCR_RFEN_MASK 0x20000000u +#define CAN_MCR_RFEN_SHIFT 29 +#define CAN_MCR_FRZ_MASK 0x40000000u +#define CAN_MCR_FRZ_SHIFT 30 +#define CAN_MCR_MDIS_MASK 0x80000000u +#define CAN_MCR_MDIS_SHIFT 31 +/* CTRL1 Bit Fields */ +#define CAN_CTRL1_PROP_SEG_MASK 0x7u +#define CAN_CTRL1_PROP_SEG_SHIFT 0 +#define CAN_CTRL1_PROP_SEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROP_SEG_SHIFT))&CAN_CTRL1_PROP_SEG_MASK) +#define CAN_CTRL1_LOM_MASK 0x8u +#define CAN_CTRL1_LOM_SHIFT 3 +#define CAN_CTRL1_LBUF_MASK 0x10u +#define CAN_CTRL1_LBUF_SHIFT 4 +#define CAN_CTRL1_TSYN_MASK 0x20u +#define CAN_CTRL1_TSYN_SHIFT 5 +#define CAN_CTRL1_BOFF_REC_MASK 0x40u +#define CAN_CTRL1_BOFF_REC_SHIFT 6 +#define CAN_CTRL1_SMP_MASK 0x80u +#define CAN_CTRL1_SMP_SHIFT 7 +#define CAN_CTRL1_RWRN_MSK_MASK 0x400u +#define CAN_CTRL1_RWRN_MSK_SHIFT 10 +#define CAN_CTRL1_TWRN_MSK_MASK 0x800u +#define CAN_CTRL1_TWRN_MSK_SHIFT 11 +#define CAN_CTRL1_LPB_MASK 0x1000u +#define CAN_CTRL1_LPB_SHIFT 12 +#define CAN_CTRL1_ERR_MSK_MASK 0x4000u +#define CAN_CTRL1_ERR_MSK_SHIFT 14 +#define CAN_CTRL1_BOFF_MSK_MASK 0x8000u +#define CAN_CTRL1_BOFF_MSK_SHIFT 15 +#define CAN_CTRL1_PSEG2_MASK 0x70000u +#define CAN_CTRL1_PSEG2_SHIFT 16 +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK 0x380000u +#define CAN_CTRL1_PSEG1_SHIFT 19 +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK 0xC00000u +#define CAN_CTRL1_RJW_SHIFT 22 +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u +#define CAN_CTRL1_PRESDIV_SHIFT 24 +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK) +/* TIMER Bit Fields */ +#define CAN_TIMER_TIMER_MASK 0xFFFFu +#define CAN_TIMER_TIMER_SHIFT 0 +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK) +/* RXMGMASK Bit Fields */ +#define CAN_RXMGMASK_MG31_MG0_MASK 0xFFFFFFFFu +#define CAN_RXMGMASK_MG31_MG0_SHIFT 0 +#define CAN_RXMGMASK_MG31_MG0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG31_MG0_SHIFT))&CAN_RXMGMASK_MG31_MG0_MASK) +/* RX14MASK Bit Fields */ +#define CAN_RX14MASK_RX14M31_RX14M0_MASK 0xFFFFFFFFu +#define CAN_RX14MASK_RX14M31_RX14M0_SHIFT 0 +#define CAN_RX14MASK_RX14M31_RX14M0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M31_RX14M0_SHIFT))&CAN_RX14MASK_RX14M31_RX14M0_MASK) +/* RX15MASK Bit Fields */ +#define CAN_RX15MASK_RX15M31_RX15M0_MASK 0xFFFFFFFFu +#define CAN_RX15MASK_RX15M31_RX15M0_SHIFT 0 +#define CAN_RX15MASK_RX15M31_RX15M0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M31_RX15M0_SHIFT))&CAN_RX15MASK_RX15M31_RX15M0_MASK) +/* ECR Bit Fields */ +#define CAN_ECR_Tx_Err_Counter_MASK 0xFFu +#define CAN_ECR_Tx_Err_Counter_SHIFT 0 +#define CAN_ECR_Tx_Err_Counter(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Tx_Err_Counter_SHIFT))&CAN_ECR_Tx_Err_Counter_MASK) +#define CAN_ECR_Rx_Err_Counter_MASK 0xFF00u +#define CAN_ECR_Rx_Err_Counter_SHIFT 8 +#define CAN_ECR_Rx_Err_Counter(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_Rx_Err_Counter_SHIFT))&CAN_ECR_Rx_Err_Counter_MASK) +/* ESR1 Bit Fields */ +#define CAN_ESR1_WAK_INT_MASK 0x1u +#define CAN_ESR1_WAK_INT_SHIFT 0 +#define CAN_ESR1_ERR_INT_MASK 0x2u +#define CAN_ESR1_ERR_INT_SHIFT 1 +#define CAN_ESR1_BOFF_INT_MASK 0x4u +#define CAN_ESR1_BOFF_INT_SHIFT 2 +#define CAN_ESR1_RX_MASK 0x8u +#define CAN_ESR1_RX_SHIFT 3 +#define CAN_ESR1_FLT_CONF_MASK 0x30u +#define CAN_ESR1_FLT_CONF_SHIFT 4 +#define CAN_ESR1_FLT_CONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLT_CONF_SHIFT))&CAN_ESR1_FLT_CONF_MASK) +#define CAN_ESR1_TX_MASK 0x40u +#define CAN_ESR1_TX_SHIFT 6 +#define CAN_ESR1_IDLE_MASK 0x80u +#define CAN_ESR1_IDLE_SHIFT 7 +#define CAN_ESR1_RX_WRN_MASK 0x100u +#define CAN_ESR1_RX_WRN_SHIFT 8 +#define CAN_ESR1_TX_WRN_MASK 0x200u +#define CAN_ESR1_TX_WRN_SHIFT 9 +#define CAN_ESR1_STF_ERR_MASK 0x400u +#define CAN_ESR1_STF_ERR_SHIFT 10 +#define CAN_ESR1_FRM_ERR_MASK 0x800u +#define CAN_ESR1_FRM_ERR_SHIFT 11 +#define CAN_ESR1_CRC_ERR_MASK 0x1000u +#define CAN_ESR1_CRC_ERR_SHIFT 12 +#define CAN_ESR1_ACK_ERR_MASK 0x2000u +#define CAN_ESR1_ACK_ERR_SHIFT 13 +#define CAN_ESR1_BIT0_ERR_MASK 0x4000u +#define CAN_ESR1_BIT0_ERR_SHIFT 14 +#define CAN_ESR1_BIT1_ERR_MASK 0x8000u +#define CAN_ESR1_BIT1_ERR_SHIFT 15 +#define CAN_ESR1_RWRN_INT_MASK 0x10000u +#define CAN_ESR1_RWRN_INT_SHIFT 16 +#define CAN_ESR1_TWRN_INT_MASK 0x20000u +#define CAN_ESR1_TWRN_INT_SHIFT 17 +#define CAN_ESR1_SYNCH_MASK 0x40000u +#define CAN_ESR1_SYNCH_SHIFT 18 +/* IMASK2 Bit Fields */ +#define CAN_IMASK2_BUF63M_BUF32M_MASK 0xFFFFFFFFu +#define CAN_IMASK2_BUF63M_BUF32M_SHIFT 0 +#define CAN_IMASK2_BUF63M_BUF32M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUF63M_BUF32M_SHIFT))&CAN_IMASK2_BUF63M_BUF32M_MASK) +/* IMASK1 Bit Fields */ +#define CAN_IMASK1_BUF31M_BUF0M_MASK 0xFFFFFFFFu +#define CAN_IMASK1_BUF31M_BUF0M_SHIFT 0 +#define CAN_IMASK1_BUF31M_BUF0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31M_BUF0M_SHIFT))&CAN_IMASK1_BUF31M_BUF0M_MASK) +/* IFLAG2 Bit Fields */ +#define CAN_IFLAG2_BUF63I_BUF32I_MASK 0xFFFFFFFFu +#define CAN_IFLAG2_BUF63I_BUF32I_SHIFT 0 +#define CAN_IFLAG2_BUF63I_BUF32I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUF63I_BUF32I_SHIFT))&CAN_IFLAG2_BUF63I_BUF32I_MASK) +/* IFLAG1 Bit Fields */ +#define CAN_IFLAG1_BUF4I_BUF0I_MASK 0x1Fu +#define CAN_IFLAG1_BUF4I_BUF0I_SHIFT 0 +#define CAN_IFLAG1_BUF4I_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4I_BUF0I_SHIFT))&CAN_IFLAG1_BUF4I_BUF0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK 0x20u +#define CAN_IFLAG1_BUF5I_SHIFT 5 +#define CAN_IFLAG1_BUF6I_MASK 0x40u +#define CAN_IFLAG1_BUF6I_SHIFT 6 +#define CAN_IFLAG1_BUF7I_MASK 0x80u +#define CAN_IFLAG1_BUF7I_SHIFT 7 +#define CAN_IFLAG1_BUF31I_BUF8I_MASK 0xFFFFFF00u +#define CAN_IFLAG1_BUF31I_BUF8I_SHIFT 8 +#define CAN_IFLAG1_BUF31I_BUF8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31I_BUF8I_SHIFT))&CAN_IFLAG1_BUF31I_BUF8I_MASK) +/* CTRL2 Bit Fields */ +#define CAN_CTRL2_EACEN_MASK 0x10000u +#define CAN_CTRL2_EACEN_SHIFT 16 +#define CAN_CTRL2_RRS_MASK 0x20000u +#define CAN_CTRL2_RRS_SHIFT 17 +#define CAN_CTRL2_MRP_MASK 0x40000u +#define CAN_CTRL2_MRP_SHIFT 18 +#define CAN_CTRL2_TASD_MASK 0xF80000u +#define CAN_CTRL2_TASD_SHIFT 19 +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK 0xF000000u +#define CAN_CTRL2_RFFN_SHIFT 24 +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u +#define CAN_CTRL2_WRMFRZ_SHIFT 28 +/* ESR2 Bit Fields */ +#define CAN_ESR2_IMB_MASK 0x2000u +#define CAN_ESR2_IMB_SHIFT 13 +#define CAN_ESR2_VPS_MASK 0x4000u +#define CAN_ESR2_VPS_SHIFT 14 +#define CAN_ESR2_LPTM_MASK 0x7F0000u +#define CAN_ESR2_LPTM_SHIFT 16 +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK) +/* CRCR Bit Fields */ +#define CAN_CRCR_TXCRC_MASK 0x7FFFu +#define CAN_CRCR_TXCRC_SHIFT 0 +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK 0x7F0000u +#define CAN_CRCR_MBCRC_SHIFT 16 +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK) +/* RXFGMASK Bit Fields */ +#define CAN_RXFGMASK_FGM31_FGM0_MASK 0xFFFFFFFFu +#define CAN_RXFGMASK_FGM31_FGM0_SHIFT 0 +#define CAN_RXFGMASK_FGM31_FGM0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM31_FGM0_SHIFT))&CAN_RXFGMASK_FGM31_FGM0_MASK) +/* RXFIR Bit Fields */ +#define CAN_RXFIR_IDHIT_MASK 0x1FFu +#define CAN_RXFIR_IDHIT_SHIFT 0 +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK) +/* CS Bit Fields */ +#define CAN_CS_TIME_STAMP_MASK 0xFFFFu +#define CAN_CS_TIME_STAMP_SHIFT 0 +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK 0xF0000u +#define CAN_CS_DLC_SHIFT 16 +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK 0x100000u +#define CAN_CS_RTR_SHIFT 20 +#define CAN_CS_IDE_MASK 0x200000u +#define CAN_CS_IDE_SHIFT 21 +#define CAN_CS_SRR_MASK 0x400000u +#define CAN_CS_SRR_SHIFT 22 +#define CAN_CS_CODE_MASK 0xF000000u +#define CAN_CS_CODE_SHIFT 24 +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK) +/* ID Bit Fields */ +#define CAN_ID_EXT_MASK 0x3FFFFu +#define CAN_ID_EXT_SHIFT 0 +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK 0x1FFC0000u +#define CAN_ID_STD_SHIFT 18 +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK 0xE0000000u +#define CAN_ID_PRIO_SHIFT 29 +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK) +/* WORD0 Bit Fields */ +#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu +#define CAN_WORD0_DATA_BYTE_3_SHIFT 0 +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u +#define CAN_WORD0_DATA_BYTE_2_SHIFT 8 +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u +#define CAN_WORD0_DATA_BYTE_1_SHIFT 16 +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u +#define CAN_WORD0_DATA_BYTE_0_SHIFT 24 +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK) +/* WORD1 Bit Fields */ +#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu +#define CAN_WORD1_DATA_BYTE_7_SHIFT 0 +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u +#define CAN_WORD1_DATA_BYTE_6_SHIFT 8 +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u +#define CAN_WORD1_DATA_BYTE_5_SHIFT 16 +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u +#define CAN_WORD1_DATA_BYTE_4_SHIFT 24 +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK) +/* RXIMR Bit Fields */ +#define CAN_RXIMR0_RXIMR63_MI31_MI0_MASK 0xFFFFFFFFu +#define CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT 0 +#define CAN_RXIMR0_RXIMR63_MI31_MI0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR0_RXIMR63_MI31_MI0_SHIFT))&CAN_RXIMR0_RXIMR63_MI31_MI0_MASK) +/* GFWR Bit Fields */ +#define CAN_GFWR_GFWR_MASK 0xFFu +#define CAN_GFWR_GFWR_SHIFT 0 +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x))<<CAN_GFWR_GFWR_SHIFT))&CAN_GFWR_GFWR_MASK) + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x30A00000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +#define CAN1_BASE_PTR (CAN1) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x30A10000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +#define CAN2_BASE_PTR (CAN2) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN1, CAN2 } + +/* ---------------------------------------------------------------------------- + -- CAN - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros + * @{ + */ + + +/* FLEXCAN - Register instance definitions */ +/* CAN1 */ +#define CAN1_MCR CAN_MCR_REG(CAN1_BASE_PTR) +#define CAN1_CTRL1 CAN_CTRL1_REG(CAN1_BASE_PTR) +#define CAN1_TIMER CAN_TIMER_REG(CAN1_BASE_PTR) +#define CAN1_RXMGMASK CAN_RXMGMASK_REG(CAN1_BASE_PTR) +#define CAN1_RX14MASK CAN_RX14MASK_REG(CAN1_BASE_PTR) +#define CAN1_RX15MASK CAN_RX15MASK_REG(CAN1_BASE_PTR) +#define CAN1_ECR CAN_ECR_REG(CAN1_BASE_PTR) +#define CAN1_ESR1 CAN_ESR1_REG(CAN1_BASE_PTR) +#define CAN1_IMASK2 CAN_IMASK2_REG(CAN1_BASE_PTR) +#define CAN1_IMASK1 CAN_IMASK1_REG(CAN1_BASE_PTR) +#define CAN1_IFLAG2 CAN_IFLAG2_REG(CAN1_BASE_PTR) +#define CAN1_IFLAG1 CAN_IFLAG1_REG(CAN1_BASE_PTR) +#define CAN1_CTRL2 CAN_CTRL2_REG(CAN1_BASE_PTR) +#define CAN1_ESR2 CAN_ESR2_REG(CAN1_BASE_PTR) +#define CAN1_CRCR CAN_CRCR_REG(CAN1_BASE_PTR) +#define CAN1_RXFGMASK CAN_RXFGMASK_REG(CAN1_BASE_PTR) +#define CAN1_RXFIR CAN_RXFIR_REG(CAN1_BASE_PTR) +#define CAN1_CS(index) CAN_CS_REG(CAN1,index) +#define CAN1_ID(index) CAN_ID_REG(CAN1,index) +#define CAN1_WORD0(index) CAN_WORD0_REG(CAN1,index) +#define CAN1_WORD1(index) CAN_WORD1_REG(CAN1,index) +#define CAN1_RXIMR(index) CAN_RXIMR_REG(CAN1,index) +#define CAN1_GFWR CAN_GFWR_REG(CAN1_BASE_PTR) +/* CAN2 */ +#define CAN2_MCR CAN_MCR_REG(CAN2_BASE_PTR) +#define CAN2_CTRL1 CAN_CTRL1_REG(CAN2_BASE_PTR) +#define CAN2_TIMER CAN_TIMER_REG(CAN2_BASE_PTR) +#define CAN2_RXMGMASK CAN_RXMGMASK_REG(CAN2_BASE_PTR) +#define CAN2_RX14MASK CAN_RX14MASK_REG(CAN2_BASE_PTR) +#define CAN2_RX15MASK CAN_RX15MASK_REG(CAN2_BASE_PTR) +#define CAN2_ECR CAN_ECR_REG(CAN2_BASE_PTR) +#define CAN2_ESR1 CAN_ESR1_REG(CAN2_BASE_PTR) +#define CAN2_IMASK2 CAN_IMASK2_REG(CAN2_BASE_PTR) +#define CAN2_IMASK1 CAN_IMASK1_REG(CAN2_BASE_PTR) +#define CAN2_IFLAG2 CAN_IFLAG2_REG(CAN2_BASE_PTR) +#define CAN2_IFLAG1 CAN_IFLAG1_REG(CAN2_BASE_PTR) +#define CAN2_CTRL2 CAN_CTRL2_REG(CAN2_BASE_PTR) +#define CAN2_ESR2 CAN_ESR2_REG(CAN2_BASE_PTR) +#define CAN2_CRCR CAN_CRCR_REG(CAN2_BASE_PTR) +#define CAN2_RXFGMASK CAN_RXFGMASK_REG(CAN2_BASE_PTR) +#define CAN2_RXFIR CAN_RXFIR_REG(CAN2_BASE_PTR) +#define CAN2_RXFIR CAN_RXFIR_REG(CAN2_BASE_PTR) +#define CAN2_CS(index) CAN_CS_REG(CAN2,index) +#define CAN2_ID(index) CAN_ID_REG(CAN2,index) +#define CAN2_WORD0(index) CAN_WORD0_REG(CAN2,index) +#define CAN2_WORD1(index) CAN_WORD1_REG(CAN2,index) +#define CAN2_RXIMR(index) CAN_RXIMR_REG(CAN2,index) +#define CAN2_GFWR CAN_GFWR_REG(CAN2_BASE_PTR) + +/*! + * @} + */ /* end of group CAN_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group CAN_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */ + uint8_t RESERVED[2032]; + __IO uint32_t PLL_CTRL0; /**< CCM PLL Control Register, offset: 0x800 */ + __IO uint32_t PLL_CTRL0_SET; /**< CCM PLL Control Register, offset: 0x804 */ + __IO uint32_t PLL_CTRL0_CLR; /**< CCM PLL Control Register, offset: 0x808 */ + __IO uint32_t PLL_CTRL0_TOG; /**< CCM PLL Control Register, offset: 0x80C */ + __IO uint32_t PLL_CTRL1; /**< CCM PLL Control Register, offset: 0x810 */ + __IO uint32_t PLL_CTRL1_SET; /**< CCM PLL Control Register, offset: 0x814 */ + __IO uint32_t PLL_CTRL1_CLR; /**< CCM PLL Control Register, offset: 0x818 */ + __IO uint32_t PLL_CTRL1_TOG; /**< CCM PLL Control Register, offset: 0x81C */ + __IO uint32_t PLL_CTRL2; /**< CCM PLL Control Register, offset: 0x820 */ + __IO uint32_t PLL_CTRL2_SET; /**< CCM PLL Control Register, offset: 0x824 */ + __IO uint32_t PLL_CTRL2_CLR; /**< CCM PLL Control Register, offset: 0x828 */ + __IO uint32_t PLL_CTRL2_TOG; /**< CCM PLL Control Register, offset: 0x82C */ + __IO uint32_t PLL_CTRL3; /**< CCM PLL Control Register, offset: 0x830 */ + __IO uint32_t PLL_CTRL3_SET; /**< CCM PLL Control Register, offset: 0x834 */ + __IO uint32_t PLL_CTRL3_CLR; /**< CCM PLL Control Register, offset: 0x838 */ + __IO uint32_t PLL_CTRL3_TOG; /**< CCM PLL Control Register, offset: 0x83C */ + __IO uint32_t PLL_CTRL4; /**< CCM PLL Control Register, offset: 0x840 */ + __IO uint32_t PLL_CTRL4_SET; /**< CCM PLL Control Register, offset: 0x844 */ + __IO uint32_t PLL_CTRL4_CLR; /**< CCM PLL Control Register, offset: 0x848 */ + __IO uint32_t PLL_CTRL4_TOG; /**< CCM PLL Control Register, offset: 0x84C */ + __IO uint32_t PLL_CTRL5; /**< CCM PLL Control Register, offset: 0x850 */ + __IO uint32_t PLL_CTRL5_SET; /**< CCM PLL Control Register, offset: 0x854 */ + __IO uint32_t PLL_CTRL5_CLR; /**< CCM PLL Control Register, offset: 0x858 */ + __IO uint32_t PLL_CTRL5_TOG; /**< CCM PLL Control Register, offset: 0x85C */ + __IO uint32_t PLL_CTRL6; /**< CCM PLL Control Register, offset: 0x860 */ + __IO uint32_t PLL_CTRL6_SET; /**< CCM PLL Control Register, offset: 0x864 */ + __IO uint32_t PLL_CTRL6_CLR; /**< CCM PLL Control Register, offset: 0x868 */ + __IO uint32_t PLL_CTRL6_TOG; /**< CCM PLL Control Register, offset: 0x86C */ + __IO uint32_t PLL_CTRL7; /**< CCM PLL Control Register, offset: 0x870 */ + __IO uint32_t PLL_CTRL7_SET; /**< CCM PLL Control Register, offset: 0x874 */ + __IO uint32_t PLL_CTRL7_CLR; /**< CCM PLL Control Register, offset: 0x878 */ + __IO uint32_t PLL_CTRL7_TOG; /**< CCM PLL Control Register, offset: 0x87C */ + __IO uint32_t PLL_CTRL8; /**< CCM PLL Control Register, offset: 0x880 */ + __IO uint32_t PLL_CTRL8_SET; /**< CCM PLL Control Register, offset: 0x884 */ + __IO uint32_t PLL_CTRL8_CLR; /**< CCM PLL Control Register, offset: 0x888 */ + __IO uint32_t PLL_CTRL8_TOG; /**< CCM PLL Control Register, offset: 0x88C */ + __IO uint32_t PLL_CTRL9; /**< CCM PLL Control Register, offset: 0x890 */ + __IO uint32_t PLL_CTRL9_SET; /**< CCM PLL Control Register, offset: 0x894 */ + __IO uint32_t PLL_CTRL9_CLR; /**< CCM PLL Control Register, offset: 0x898 */ + __IO uint32_t PLL_CTRL9_TOG; /**< CCM PLL Control Register, offset: 0x89C */ + __IO uint32_t PLL_CTRL10; /**< CCM PLL Control Register, offset: 0x8A0 */ + __IO uint32_t PLL_CTRL10_SET; /**< CCM PLL Control Register, offset: 0x8A4 */ + __IO uint32_t PLL_CTRL10_CLR; /**< CCM PLL Control Register, offset: 0x8A8 */ + __IO uint32_t PLL_CTRL10_TOG; /**< CCM PLL Control Register, offset: 0x8AC */ + __IO uint32_t PLL_CTRL11; /**< CCM PLL Control Register, offset: 0x8B0 */ + __IO uint32_t PLL_CTRL11_SET; /**< CCM PLL Control Register, offset: 0x8B4 */ + __IO uint32_t PLL_CTRL11_CLR; /**< CCM PLL Control Register, offset: 0x8B8 */ + __IO uint32_t PLL_CTRL11_TOG; /**< CCM PLL Control Register, offset: 0x8BC */ + __IO uint32_t PLL_CTRL12; /**< CCM PLL Control Register, offset: 0x8C0 */ + __IO uint32_t PLL_CTRL12_SET; /**< CCM PLL Control Register, offset: 0x8C4 */ + __IO uint32_t PLL_CTRL12_CLR; /**< CCM PLL Control Register, offset: 0x8C8 */ + __IO uint32_t PLL_CTRL12_TOG; /**< CCM PLL Control Register, offset: 0x8CC */ + __IO uint32_t PLL_CTRL13; /**< CCM PLL Control Register, offset: 0x8D0 */ + __IO uint32_t PLL_CTRL13_SET; /**< CCM PLL Control Register, offset: 0x8D4 */ + __IO uint32_t PLL_CTRL13_CLR; /**< CCM PLL Control Register, offset: 0x8D8 */ + __IO uint32_t PLL_CTRL13_TOG; /**< CCM PLL Control Register, offset: 0x8DC */ + __IO uint32_t PLL_CTRL14; /**< CCM PLL Control Register, offset: 0x8E0 */ + __IO uint32_t PLL_CTRL14_SET; /**< CCM PLL Control Register, offset: 0x8E4 */ + __IO uint32_t PLL_CTRL14_CLR; /**< CCM PLL Control Register, offset: 0x8E8 */ + __IO uint32_t PLL_CTRL14_TOG; /**< CCM PLL Control Register, offset: 0x8EC */ + __IO uint32_t PLL_CTRL15; /**< CCM PLL Control Register, offset: 0x8F0 */ + __IO uint32_t PLL_CTRL15_SET; /**< CCM PLL Control Register, offset: 0x8F4 */ + __IO uint32_t PLL_CTRL15_CLR; /**< CCM PLL Control Register, offset: 0x8F8 */ + __IO uint32_t PLL_CTRL15_TOG; /**< CCM PLL Control Register, offset: 0x8FC */ + __IO uint32_t PLL_CTRL16; /**< CCM PLL Control Register, offset: 0x900 */ + __IO uint32_t PLL_CTRL16_SET; /**< CCM PLL Control Register, offset: 0x904 */ + __IO uint32_t PLL_CTRL16_CLR; /**< CCM PLL Control Register, offset: 0x908 */ + __IO uint32_t PLL_CTRL16_TOG; /**< CCM PLL Control Register, offset: 0x90C */ + __IO uint32_t PLL_CTRL17; /**< CCM PLL Control Register, offset: 0x910 */ + __IO uint32_t PLL_CTRL17_SET; /**< CCM PLL Control Register, offset: 0x914 */ + __IO uint32_t PLL_CTRL17_CLR; /**< CCM PLL Control Register, offset: 0x918 */ + __IO uint32_t PLL_CTRL17_TOG; /**< CCM PLL Control Register, offset: 0x91C */ + __IO uint32_t PLL_CTRL18; /**< CCM PLL Control Register, offset: 0x920 */ + __IO uint32_t PLL_CTRL18_SET; /**< CCM PLL Control Register, offset: 0x924 */ + __IO uint32_t PLL_CTRL18_CLR; /**< CCM PLL Control Register, offset: 0x928 */ + __IO uint32_t PLL_CTRL18_TOG; /**< CCM PLL Control Register, offset: 0x92C */ + __IO uint32_t PLL_CTRL19; /**< CCM PLL Control Register, offset: 0x930 */ + __IO uint32_t PLL_CTRL19_SET; /**< CCM PLL Control Register, offset: 0x934 */ + __IO uint32_t PLL_CTRL19_CLR; /**< CCM PLL Control Register, offset: 0x938 */ + __IO uint32_t PLL_CTRL19_TOG; /**< CCM PLL Control Register, offset: 0x93C */ + __IO uint32_t PLL_CTRL20; /**< CCM PLL Control Register, offset: 0x940 */ + __IO uint32_t PLL_CTRL20_SET; /**< CCM PLL Control Register, offset: 0x944 */ + __IO uint32_t PLL_CTRL20_CLR; /**< CCM PLL Control Register, offset: 0x948 */ + __IO uint32_t PLL_CTRL20_TOG; /**< CCM PLL Control Register, offset: 0x94C */ + __IO uint32_t PLL_CTRL21; /**< CCM PLL Control Register, offset: 0x950 */ + __IO uint32_t PLL_CTRL21_SET; /**< CCM PLL Control Register, offset: 0x954 */ + __IO uint32_t PLL_CTRL21_CLR; /**< CCM PLL Control Register, offset: 0x958 */ + __IO uint32_t PLL_CTRL21_TOG; /**< CCM PLL Control Register, offset: 0x95C */ + __IO uint32_t PLL_CTRL22; /**< CCM PLL Control Register, offset: 0x960 */ + __IO uint32_t PLL_CTRL22_SET; /**< CCM PLL Control Register, offset: 0x964 */ + __IO uint32_t PLL_CTRL22_CLR; /**< CCM PLL Control Register, offset: 0x968 */ + __IO uint32_t PLL_CTRL22_TOG; /**< CCM PLL Control Register, offset: 0x96C */ + __IO uint32_t PLL_CTRL23; /**< CCM PLL Control Register, offset: 0x970 */ + __IO uint32_t PLL_CTRL23_SET; /**< CCM PLL Control Register, offset: 0x974 */ + __IO uint32_t PLL_CTRL23_CLR; /**< CCM PLL Control Register, offset: 0x978 */ + __IO uint32_t PLL_CTRL23_TOG; /**< CCM PLL Control Register, offset: 0x97C */ + __IO uint32_t PLL_CTRL24; /**< CCM PLL Control Register, offset: 0x980 */ + __IO uint32_t PLL_CTRL24_SET; /**< CCM PLL Control Register, offset: 0x984 */ + __IO uint32_t PLL_CTRL24_CLR; /**< CCM PLL Control Register, offset: 0x988 */ + __IO uint32_t PLL_CTRL24_TOG; /**< CCM PLL Control Register, offset: 0x98C */ + __IO uint32_t PLL_CTRL25; /**< CCM PLL Control Register, offset: 0x990 */ + __IO uint32_t PLL_CTRL25_SET; /**< CCM PLL Control Register, offset: 0x994 */ + __IO uint32_t PLL_CTRL25_CLR; /**< CCM PLL Control Register, offset: 0x998 */ + __IO uint32_t PLL_CTRL25_TOG; /**< CCM PLL Control Register, offset: 0x99C */ + __IO uint32_t PLL_CTRL26; /**< CCM PLL Control Register, offset: 0x9A0 */ + __IO uint32_t PLL_CTRL26_SET; /**< CCM PLL Control Register, offset: 0x9A4 */ + __IO uint32_t PLL_CTRL26_CLR; /**< CCM PLL Control Register, offset: 0x9A8 */ + __IO uint32_t PLL_CTRL26_TOG; /**< CCM PLL Control Register, offset: 0x9AC */ + __IO uint32_t PLL_CTRL27; /**< CCM PLL Control Register, offset: 0x9B0 */ + __IO uint32_t PLL_CTRL27_SET; /**< CCM PLL Control Register, offset: 0x9B4 */ + __IO uint32_t PLL_CTRL27_CLR; /**< CCM PLL Control Register, offset: 0x9B8 */ + __IO uint32_t PLL_CTRL27_TOG; /**< CCM PLL Control Register, offset: 0x9BC */ + __IO uint32_t PLL_CTRL28; /**< CCM PLL Control Register, offset: 0x9C0 */ + __IO uint32_t PLL_CTRL28_SET; /**< CCM PLL Control Register, offset: 0x9C4 */ + __IO uint32_t PLL_CTRL28_CLR; /**< CCM PLL Control Register, offset: 0x9C8 */ + __IO uint32_t PLL_CTRL28_TOG; /**< CCM PLL Control Register, offset: 0x9CC */ + __IO uint32_t PLL_CTRL29; /**< CCM PLL Control Register, offset: 0x9D0 */ + __IO uint32_t PLL_CTRL29_SET; /**< CCM PLL Control Register, offset: 0x9D4 */ + __IO uint32_t PLL_CTRL29_CLR; /**< CCM PLL Control Register, offset: 0x9D8 */ + __IO uint32_t PLL_CTRL29_TOG; /**< CCM PLL Control Register, offset: 0x9DC */ + __IO uint32_t PLL_CTRL30; /**< CCM PLL Control Register, offset: 0x9E0 */ + __IO uint32_t PLL_CTRL30_SET; /**< CCM PLL Control Register, offset: 0x9E4 */ + __IO uint32_t PLL_CTRL30_CLR; /**< CCM PLL Control Register, offset: 0x9E8 */ + __IO uint32_t PLL_CTRL30_TOG; /**< CCM PLL Control Register, offset: 0x9EC */ + __IO uint32_t PLL_CTRL31; /**< CCM PLL Control Register, offset: 0x9F0 */ + __IO uint32_t PLL_CTRL31_SET; /**< CCM PLL Control Register, offset: 0x9F4 */ + __IO uint32_t PLL_CTRL31_CLR; /**< CCM PLL Control Register, offset: 0x9F8 */ + __IO uint32_t PLL_CTRL31_TOG; /**< CCM PLL Control Register, offset: 0x9FC */ + __IO uint32_t PLL_CTRL32; /**< CCM PLL Control Register, offset: 0xA00 */ + __IO uint32_t PLL_CTRL32_SET; /**< CCM PLL Control Register, offset: 0xA04 */ + __IO uint32_t PLL_CTRL32_CLR; /**< CCM PLL Control Register, offset: 0xA08 */ + __IO uint32_t PLL_CTRL32_TOG; /**< CCM PLL Control Register, offset: 0xA0C */ + uint8_t RESERVED_0[13808]; + __IO uint32_t CCGR0; /**< CCM Clock Gating Register, offset: 0x4000 */ + __IO uint32_t CCGR0_SET; /**< CCM Clock Gating Register, offset: 0x4004 */ + __IO uint32_t CCGR0_CLR; /**< CCM Clock Gating Register, offset: 0x4008 */ + __IO uint32_t CCGR0_TOG; /**< CCM Clock Gating Register, offset: 0x400C */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register, offset: 0x4010 */ + __IO uint32_t CCGR1_SET; /**< CCM Clock Gating Register, offset: 0x4014 */ + __IO uint32_t CCGR1_CLR; /**< CCM Clock Gating Register, offset: 0x4018 */ + __IO uint32_t CCGR1_TOG; /**< CCM Clock Gating Register, offset: 0x401C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register, offset: 0x4020 */ + __IO uint32_t CCGR2_SET; /**< CCM Clock Gating Register, offset: 0x4024 */ + __IO uint32_t CCGR2_CLR; /**< CCM Clock Gating Register, offset: 0x4028 */ + __IO uint32_t CCGR2_TOG; /**< CCM Clock Gating Register, offset: 0x402C */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register, offset: 0x4030 */ + __IO uint32_t CCGR3_SET; /**< CCM Clock Gating Register, offset: 0x4034 */ + __IO uint32_t CCGR3_CLR; /**< CCM Clock Gating Register, offset: 0x4038 */ + __IO uint32_t CCGR3_TOG; /**< CCM Clock Gating Register, offset: 0x403C */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register, offset: 0x4040 */ + __IO uint32_t CCGR4_SET; /**< CCM Clock Gating Register, offset: 0x4044 */ + __IO uint32_t CCGR4_CLR; /**< CCM Clock Gating Register, offset: 0x4048 */ + __IO uint32_t CCGR4_TOG; /**< CCM Clock Gating Register, offset: 0x404C */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register, offset: 0x4050 */ + __IO uint32_t CCGR5_SET; /**< CCM Clock Gating Register, offset: 0x4054 */ + __IO uint32_t CCGR5_CLR; /**< CCM Clock Gating Register, offset: 0x4058 */ + __IO uint32_t CCGR5_TOG; /**< CCM Clock Gating Register, offset: 0x405C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register, offset: 0x4060 */ + __IO uint32_t CCGR6_SET; /**< CCM Clock Gating Register, offset: 0x4064 */ + __IO uint32_t CCGR6_CLR; /**< CCM Clock Gating Register, offset: 0x4068 */ + __IO uint32_t CCGR6_TOG; /**< CCM Clock Gating Register, offset: 0x406C */ + __IO uint32_t CCGR7; /**< CCM Clock Gating Register, offset: 0x4070 */ + __IO uint32_t CCGR7_SET; /**< CCM Clock Gating Register, offset: 0x4074 */ + __IO uint32_t CCGR7_CLR; /**< CCM Clock Gating Register, offset: 0x4078 */ + __IO uint32_t CCGR7_TOG; /**< CCM Clock Gating Register, offset: 0x407C */ + __IO uint32_t CCGR8; /**< CCM Clock Gating Register, offset: 0x4080 */ + __IO uint32_t CCGR8_SET; /**< CCM Clock Gating Register, offset: 0x4084 */ + __IO uint32_t CCGR8_CLR; /**< CCM Clock Gating Register, offset: 0x4088 */ + __IO uint32_t CCGR8_TOG; /**< CCM Clock Gating Register, offset: 0x408C */ + __IO uint32_t CCGR9; /**< CCM Clock Gating Register, offset: 0x4090 */ + __IO uint32_t CCGR9_SET; /**< CCM Clock Gating Register, offset: 0x4094 */ + __IO uint32_t CCGR9_CLR; /**< CCM Clock Gating Register, offset: 0x4098 */ + __IO uint32_t CCGR9_TOG; /**< CCM Clock Gating Register, offset: 0x409C */ + __IO uint32_t CCGR10; /**< CCM Clock Gating Register, offset: 0x40A0 */ + __IO uint32_t CCGR10_SET; /**< CCM Clock Gating Register, offset: 0x40A4 */ + __IO uint32_t CCGR10_CLR; /**< CCM Clock Gating Register, offset: 0x40A8 */ + __IO uint32_t CCGR10_TOG; /**< CCM Clock Gating Register, offset: 0x40AC */ + __IO uint32_t CCGR11; /**< CCM Clock Gating Register, offset: 0x40B0 */ + __IO uint32_t CCGR11_SET; /**< CCM Clock Gating Register, offset: 0x40B4 */ + __IO uint32_t CCGR11_CLR; /**< CCM Clock Gating Register, offset: 0x40B8 */ + __IO uint32_t CCGR11_TOG; /**< CCM Clock Gating Register, offset: 0x40BC */ + __IO uint32_t CCGR12; /**< CCM Clock Gating Register, offset: 0x40C0 */ + __IO uint32_t CCGR12_SET; /**< CCM Clock Gating Register, offset: 0x40C4 */ + __IO uint32_t CCGR12_CLR; /**< CCM Clock Gating Register, offset: 0x40C8 */ + __IO uint32_t CCGR12_TOG; /**< CCM Clock Gating Register, offset: 0x40CC */ + __IO uint32_t CCGR13; /**< CCM Clock Gating Register, offset: 0x40D0 */ + __IO uint32_t CCGR13_SET; /**< CCM Clock Gating Register, offset: 0x40D4 */ + __IO uint32_t CCGR13_CLR; /**< CCM Clock Gating Register, offset: 0x40D8 */ + __IO uint32_t CCGR13_TOG; /**< CCM Clock Gating Register, offset: 0x40DC */ + __IO uint32_t CCGR14; /**< CCM Clock Gating Register, offset: 0x40E0 */ + __IO uint32_t CCGR14_SET; /**< CCM Clock Gating Register, offset: 0x40E4 */ + __IO uint32_t CCGR14_CLR; /**< CCM Clock Gating Register, offset: 0x40E8 */ + __IO uint32_t CCGR14_TOG; /**< CCM Clock Gating Register, offset: 0x40EC */ + __IO uint32_t CCGR15; /**< CCM Clock Gating Register, offset: 0x40F0 */ + __IO uint32_t CCGR15_SET; /**< CCM Clock Gating Register, offset: 0x40F4 */ + __IO uint32_t CCGR15_CLR; /**< CCM Clock Gating Register, offset: 0x40F8 */ + __IO uint32_t CCGR15_TOG; /**< CCM Clock Gating Register, offset: 0x40FC */ + __IO uint32_t CCGR16; /**< CCM Clock Gating Register, offset: 0x4100 */ + __IO uint32_t CCGR16_SET; /**< CCM Clock Gating Register, offset: 0x4104 */ + __IO uint32_t CCGR16_CLR; /**< CCM Clock Gating Register, offset: 0x4108 */ + __IO uint32_t CCGR16_TOG; /**< CCM Clock Gating Register, offset: 0x410C */ + __IO uint32_t CCGR17; /**< CCM Clock Gating Register, offset: 0x4110 */ + __IO uint32_t CCGR17_SET; /**< CCM Clock Gating Register, offset: 0x4114 */ + __IO uint32_t CCGR17_CLR; /**< CCM Clock Gating Register, offset: 0x4118 */ + __IO uint32_t CCGR17_TOG; /**< CCM Clock Gating Register, offset: 0x411C */ + __IO uint32_t CCGR18; /**< CCM Clock Gating Register, offset: 0x4120 */ + __IO uint32_t CCGR18_SET; /**< CCM Clock Gating Register, offset: 0x4124 */ + __IO uint32_t CCGR18_CLR; /**< CCM Clock Gating Register, offset: 0x4128 */ + __IO uint32_t CCGR18_TOG; /**< CCM Clock Gating Register, offset: 0x412C */ + __IO uint32_t CCGR19; /**< CCM Clock Gating Register, offset: 0x4130 */ + __IO uint32_t CCGR19_SET; /**< CCM Clock Gating Register, offset: 0x4134 */ + __IO uint32_t CCGR19_CLR; /**< CCM Clock Gating Register, offset: 0x4138 */ + __IO uint32_t CCGR19_TOG; /**< CCM Clock Gating Register, offset: 0x413C */ + __IO uint32_t CCGR20; /**< CCM Clock Gating Register, offset: 0x4140 */ + __IO uint32_t CCGR20_SET; /**< CCM Clock Gating Register, offset: 0x4144 */ + __IO uint32_t CCGR20_CLR; /**< CCM Clock Gating Register, offset: 0x4148 */ + __IO uint32_t CCGR20_TOG; /**< CCM Clock Gating Register, offset: 0x414C */ + __IO uint32_t CCGR21; /**< CCM Clock Gating Register, offset: 0x4150 */ + __IO uint32_t CCGR21_SET; /**< CCM Clock Gating Register, offset: 0x4154 */ + __IO uint32_t CCGR21_CLR; /**< CCM Clock Gating Register, offset: 0x4158 */ + __IO uint32_t CCGR21_TOG; /**< CCM Clock Gating Register, offset: 0x415C */ + __IO uint32_t CCGR22; /**< CCM Clock Gating Register, offset: 0x4160 */ + __IO uint32_t CCGR22_SET; /**< CCM Clock Gating Register, offset: 0x4164 */ + __IO uint32_t CCGR22_CLR; /**< CCM Clock Gating Register, offset: 0x4168 */ + __IO uint32_t CCGR22_TOG; /**< CCM Clock Gating Register, offset: 0x416C */ + __IO uint32_t CCGR23; /**< CCM Clock Gating Register, offset: 0x4170 */ + __IO uint32_t CCGR23_SET; /**< CCM Clock Gating Register, offset: 0x4174 */ + __IO uint32_t CCGR23_CLR; /**< CCM Clock Gating Register, offset: 0x4178 */ + __IO uint32_t CCGR23_TOG; /**< CCM Clock Gating Register, offset: 0x417C */ + __IO uint32_t CCGR24; /**< CCM Clock Gating Register, offset: 0x4180 */ + __IO uint32_t CCGR24_SET; /**< CCM Clock Gating Register, offset: 0x4184 */ + __IO uint32_t CCGR24_CLR; /**< CCM Clock Gating Register, offset: 0x4188 */ + __IO uint32_t CCGR24_TOG; /**< CCM Clock Gating Register, offset: 0x418C */ + __IO uint32_t CCGR25; /**< CCM Clock Gating Register, offset: 0x4190 */ + __IO uint32_t CCGR25_SET; /**< CCM Clock Gating Register, offset: 0x4194 */ + __IO uint32_t CCGR25_CLR; /**< CCM Clock Gating Register, offset: 0x4198 */ + __IO uint32_t CCGR25_TOG; /**< CCM Clock Gating Register, offset: 0x419C */ + __IO uint32_t CCGR26; /**< CCM Clock Gating Register, offset: 0x41A0 */ + __IO uint32_t CCGR26_SET; /**< CCM Clock Gating Register, offset: 0x41A4 */ + __IO uint32_t CCGR26_CLR; /**< CCM Clock Gating Register, offset: 0x41A8 */ + __IO uint32_t CCGR26_TOG; /**< CCM Clock Gating Register, offset: 0x41AC */ + __IO uint32_t CCGR27; /**< CCM Clock Gating Register, offset: 0x41B0 */ + __IO uint32_t CCGR27_SET; /**< CCM Clock Gating Register, offset: 0x41B4 */ + __IO uint32_t CCGR27_CLR; /**< CCM Clock Gating Register, offset: 0x41B8 */ + __IO uint32_t CCGR27_TOG; /**< CCM Clock Gating Register, offset: 0x41BC */ + __IO uint32_t CCGR28; /**< CCM Clock Gating Register, offset: 0x41C0 */ + __IO uint32_t CCGR28_SET; /**< CCM Clock Gating Register, offset: 0x41C4 */ + __IO uint32_t CCGR28_CLR; /**< CCM Clock Gating Register, offset: 0x41C8 */ + __IO uint32_t CCGR28_TOG; /**< CCM Clock Gating Register, offset: 0x41CC */ + __IO uint32_t CCGR29; /**< CCM Clock Gating Register, offset: 0x41D0 */ + __IO uint32_t CCGR29_SET; /**< CCM Clock Gating Register, offset: 0x41D4 */ + __IO uint32_t CCGR29_CLR; /**< CCM Clock Gating Register, offset: 0x41D8 */ + __IO uint32_t CCGR29_TOG; /**< CCM Clock Gating Register, offset: 0x41DC */ + __IO uint32_t CCGR30; /**< CCM Clock Gating Register, offset: 0x41E0 */ + __IO uint32_t CCGR30_SET; /**< CCM Clock Gating Register, offset: 0x41E4 */ + __IO uint32_t CCGR30_CLR; /**< CCM Clock Gating Register, offset: 0x41E8 */ + __IO uint32_t CCGR30_TOG; /**< CCM Clock Gating Register, offset: 0x41EC */ + __IO uint32_t CCGR31; /**< CCM Clock Gating Register, offset: 0x41F0 */ + __IO uint32_t CCGR31_SET; /**< CCM Clock Gating Register, offset: 0x41F4 */ + __IO uint32_t CCGR31_CLR; /**< CCM Clock Gating Register, offset: 0x41F8 */ + __IO uint32_t CCGR31_TOG; /**< CCM Clock Gating Register, offset: 0x41FC */ + __IO uint32_t CCGR32; /**< CCM Clock Gating Register, offset: 0x4200 */ + __IO uint32_t CCGR32_SET; /**< CCM Clock Gating Register, offset: 0x4204 */ + __IO uint32_t CCGR32_CLR; /**< CCM Clock Gating Register, offset: 0x4208 */ + __IO uint32_t CCGR32_TOG; /**< CCM Clock Gating Register, offset: 0x420C */ + __IO uint32_t CCGR33; /**< CCM Clock Gating Register, offset: 0x4210 */ + __IO uint32_t CCGR33_SET; /**< CCM Clock Gating Register, offset: 0x4214 */ + __IO uint32_t CCGR33_CLR; /**< CCM Clock Gating Register, offset: 0x4218 */ + __IO uint32_t CCGR33_TOG; /**< CCM Clock Gating Register, offset: 0x421C */ + __IO uint32_t CCGR34; /**< CCM Clock Gating Register, offset: 0x4220 */ + __IO uint32_t CCGR34_SET; /**< CCM Clock Gating Register, offset: 0x4224 */ + __IO uint32_t CCGR34_CLR; /**< CCM Clock Gating Register, offset: 0x4228 */ + __IO uint32_t CCGR34_TOG; /**< CCM Clock Gating Register, offset: 0x422C */ + __IO uint32_t CCGR35; /**< CCM Clock Gating Register, offset: 0x4230 */ + __IO uint32_t CCGR35_SET; /**< CCM Clock Gating Register, offset: 0x4234 */ + __IO uint32_t CCGR35_CLR; /**< CCM Clock Gating Register, offset: 0x4238 */ + __IO uint32_t CCGR35_TOG; /**< CCM Clock Gating Register, offset: 0x423C */ + __IO uint32_t CCGR36; /**< CCM Clock Gating Register, offset: 0x4240 */ + __IO uint32_t CCGR36_SET; /**< CCM Clock Gating Register, offset: 0x4244 */ + __IO uint32_t CCGR36_CLR; /**< CCM Clock Gating Register, offset: 0x4248 */ + __IO uint32_t CCGR36_TOG; /**< CCM Clock Gating Register, offset: 0x424C */ + __IO uint32_t CCGR37; /**< CCM Clock Gating Register, offset: 0x4250 */ + __IO uint32_t CCGR37_SET; /**< CCM Clock Gating Register, offset: 0x4254 */ + __IO uint32_t CCGR37_CLR; /**< CCM Clock Gating Register, offset: 0x4258 */ + __IO uint32_t CCGR37_TOG; /**< CCM Clock Gating Register, offset: 0x425C */ + __IO uint32_t CCGR38; /**< CCM Clock Gating Register, offset: 0x4260 */ + __IO uint32_t CCGR38_SET; /**< CCM Clock Gating Register, offset: 0x4264 */ + __IO uint32_t CCGR38_CLR; /**< CCM Clock Gating Register, offset: 0x4268 */ + __IO uint32_t CCGR38_TOG; /**< CCM Clock Gating Register, offset: 0x426C */ + __IO uint32_t CCGR39; /**< CCM Clock Gating Register, offset: 0x4270 */ + __IO uint32_t CCGR39_SET; /**< CCM Clock Gating Register, offset: 0x4274 */ + __IO uint32_t CCGR39_CLR; /**< CCM Clock Gating Register, offset: 0x4278 */ + __IO uint32_t CCGR39_TOG; /**< CCM Clock Gating Register, offset: 0x427C */ + __IO uint32_t CCGR40; /**< CCM Clock Gating Register, offset: 0x4280 */ + __IO uint32_t CCGR40_SET; /**< CCM Clock Gating Register, offset: 0x4284 */ + __IO uint32_t CCGR40_CLR; /**< CCM Clock Gating Register, offset: 0x4288 */ + __IO uint32_t CCGR40_TOG; /**< CCM Clock Gating Register, offset: 0x428C */ + __IO uint32_t CCGR41; /**< CCM Clock Gating Register, offset: 0x4290 */ + __IO uint32_t CCGR41_SET; /**< CCM Clock Gating Register, offset: 0x4294 */ + __IO uint32_t CCGR41_CLR; /**< CCM Clock Gating Register, offset: 0x4298 */ + __IO uint32_t CCGR41_TOG; /**< CCM Clock Gating Register, offset: 0x429C */ + __IO uint32_t CCGR42; /**< CCM Clock Gating Register, offset: 0x42A0 */ + __IO uint32_t CCGR42_SET; /**< CCM Clock Gating Register, offset: 0x42A4 */ + __IO uint32_t CCGR42_CLR; /**< CCM Clock Gating Register, offset: 0x42A8 */ + __IO uint32_t CCGR42_TOG; /**< CCM Clock Gating Register, offset: 0x42AC */ + __IO uint32_t CCGR43; /**< CCM Clock Gating Register, offset: 0x42B0 */ + __IO uint32_t CCGR43_SET; /**< CCM Clock Gating Register, offset: 0x42B4 */ + __IO uint32_t CCGR43_CLR; /**< CCM Clock Gating Register, offset: 0x42B8 */ + __IO uint32_t CCGR43_TOG; /**< CCM Clock Gating Register, offset: 0x42BC */ + __IO uint32_t CCGR44; /**< CCM Clock Gating Register, offset: 0x42C0 */ + __IO uint32_t CCGR44_SET; /**< CCM Clock Gating Register, offset: 0x42C4 */ + __IO uint32_t CCGR44_CLR; /**< CCM Clock Gating Register, offset: 0x42C8 */ + __IO uint32_t CCGR44_TOG; /**< CCM Clock Gating Register, offset: 0x42CC */ + __IO uint32_t CCGR45; /**< CCM Clock Gating Register, offset: 0x42D0 */ + __IO uint32_t CCGR45_SET; /**< CCM Clock Gating Register, offset: 0x42D4 */ + __IO uint32_t CCGR45_CLR; /**< CCM Clock Gating Register, offset: 0x42D8 */ + __IO uint32_t CCGR45_TOG; /**< CCM Clock Gating Register, offset: 0x42DC */ + __IO uint32_t CCGR46; /**< CCM Clock Gating Register, offset: 0x42E0 */ + __IO uint32_t CCGR46_SET; /**< CCM Clock Gating Register, offset: 0x42E4 */ + __IO uint32_t CCGR46_CLR; /**< CCM Clock Gating Register, offset: 0x42E8 */ + __IO uint32_t CCGR46_TOG; /**< CCM Clock Gating Register, offset: 0x42EC */ + __IO uint32_t CCGR47; /**< CCM Clock Gating Register, offset: 0x42F0 */ + __IO uint32_t CCGR47_SET; /**< CCM Clock Gating Register, offset: 0x42F4 */ + __IO uint32_t CCGR47_CLR; /**< CCM Clock Gating Register, offset: 0x42F8 */ + __IO uint32_t CCGR47_TOG; /**< CCM Clock Gating Register, offset: 0x42FC */ + __IO uint32_t CCGR48; /**< CCM Clock Gating Register, offset: 0x4300 */ + __IO uint32_t CCGR48_SET; /**< CCM Clock Gating Register, offset: 0x4304 */ + __IO uint32_t CCGR48_CLR; /**< CCM Clock Gating Register, offset: 0x4308 */ + __IO uint32_t CCGR48_TOG; /**< CCM Clock Gating Register, offset: 0x430C */ + __IO uint32_t CCGR49; /**< CCM Clock Gating Register, offset: 0x4310 */ + __IO uint32_t CCGR49_SET; /**< CCM Clock Gating Register, offset: 0x4314 */ + __IO uint32_t CCGR49_CLR; /**< CCM Clock Gating Register, offset: 0x4318 */ + __IO uint32_t CCGR49_TOG; /**< CCM Clock Gating Register, offset: 0x431C */ + __IO uint32_t CCGR50; /**< CCM Clock Gating Register, offset: 0x4320 */ + __IO uint32_t CCGR50_SET; /**< CCM Clock Gating Register, offset: 0x4324 */ + __IO uint32_t CCGR50_CLR; /**< CCM Clock Gating Register, offset: 0x4328 */ + __IO uint32_t CCGR50_TOG; /**< CCM Clock Gating Register, offset: 0x432C */ + __IO uint32_t CCGR51; /**< CCM Clock Gating Register, offset: 0x4330 */ + __IO uint32_t CCGR51_SET; /**< CCM Clock Gating Register, offset: 0x4334 */ + __IO uint32_t CCGR51_CLR; /**< CCM Clock Gating Register, offset: 0x4338 */ + __IO uint32_t CCGR51_TOG; /**< CCM Clock Gating Register, offset: 0x433C */ + __IO uint32_t CCGR52; /**< CCM Clock Gating Register, offset: 0x4340 */ + __IO uint32_t CCGR52_SET; /**< CCM Clock Gating Register, offset: 0x4344 */ + __IO uint32_t CCGR52_CLR; /**< CCM Clock Gating Register, offset: 0x4348 */ + __IO uint32_t CCGR52_TOG; /**< CCM Clock Gating Register, offset: 0x434C */ + __IO uint32_t CCGR53; /**< CCM Clock Gating Register, offset: 0x4350 */ + __IO uint32_t CCGR53_SET; /**< CCM Clock Gating Register, offset: 0x4354 */ + __IO uint32_t CCGR53_CLR; /**< CCM Clock Gating Register, offset: 0x4358 */ + __IO uint32_t CCGR53_TOG; /**< CCM Clock Gating Register, offset: 0x435C */ + __IO uint32_t CCGR54; /**< CCM Clock Gating Register, offset: 0x4360 */ + __IO uint32_t CCGR54_SET; /**< CCM Clock Gating Register, offset: 0x4364 */ + __IO uint32_t CCGR54_CLR; /**< CCM Clock Gating Register, offset: 0x4368 */ + __IO uint32_t CCGR54_TOG; /**< CCM Clock Gating Register, offset: 0x436C */ + __IO uint32_t CCGR55; /**< CCM Clock Gating Register, offset: 0x4370 */ + __IO uint32_t CCGR55_SET; /**< CCM Clock Gating Register, offset: 0x4374 */ + __IO uint32_t CCGR55_CLR; /**< CCM Clock Gating Register, offset: 0x4378 */ + __IO uint32_t CCGR55_TOG; /**< CCM Clock Gating Register, offset: 0x437C */ + __IO uint32_t CCGR56; /**< CCM Clock Gating Register, offset: 0x4380 */ + __IO uint32_t CCGR56_SET; /**< CCM Clock Gating Register, offset: 0x4384 */ + __IO uint32_t CCGR56_CLR; /**< CCM Clock Gating Register, offset: 0x4388 */ + __IO uint32_t CCGR56_TOG; /**< CCM Clock Gating Register, offset: 0x438C */ + __IO uint32_t CCGR57; /**< CCM Clock Gating Register, offset: 0x4390 */ + __IO uint32_t CCGR57_SET; /**< CCM Clock Gating Register, offset: 0x4394 */ + __IO uint32_t CCGR57_CLR; /**< CCM Clock Gating Register, offset: 0x4398 */ + __IO uint32_t CCGR57_TOG; /**< CCM Clock Gating Register, offset: 0x439C */ + __IO uint32_t CCGR58; /**< CCM Clock Gating Register, offset: 0x43A0 */ + __IO uint32_t CCGR58_SET; /**< CCM Clock Gating Register, offset: 0x43A4 */ + __IO uint32_t CCGR58_CLR; /**< CCM Clock Gating Register, offset: 0x43A8 */ + __IO uint32_t CCGR58_TOG; /**< CCM Clock Gating Register, offset: 0x43AC */ + __IO uint32_t CCGR59; /**< CCM Clock Gating Register, offset: 0x43B0 */ + __IO uint32_t CCGR59_SET; /**< CCM Clock Gating Register, offset: 0x43B4 */ + __IO uint32_t CCGR59_CLR; /**< CCM Clock Gating Register, offset: 0x43B8 */ + __IO uint32_t CCGR59_TOG; /**< CCM Clock Gating Register, offset: 0x43BC */ + __IO uint32_t CCGR60; /**< CCM Clock Gating Register, offset: 0x43C0 */ + __IO uint32_t CCGR60_SET; /**< CCM Clock Gating Register, offset: 0x43C4 */ + __IO uint32_t CCGR60_CLR; /**< CCM Clock Gating Register, offset: 0x43C8 */ + __IO uint32_t CCGR60_TOG; /**< CCM Clock Gating Register, offset: 0x43CC */ + __IO uint32_t CCGR61; /**< CCM Clock Gating Register, offset: 0x43D0 */ + __IO uint32_t CCGR61_SET; /**< CCM Clock Gating Register, offset: 0x43D4 */ + __IO uint32_t CCGR61_CLR; /**< CCM Clock Gating Register, offset: 0x43D8 */ + __IO uint32_t CCGR61_TOG; /**< CCM Clock Gating Register, offset: 0x43DC */ + __IO uint32_t CCGR62; /**< CCM Clock Gating Register, offset: 0x43E0 */ + __IO uint32_t CCGR62_SET; /**< CCM Clock Gating Register, offset: 0x43E4 */ + __IO uint32_t CCGR62_CLR; /**< CCM Clock Gating Register, offset: 0x43E8 */ + __IO uint32_t CCGR62_TOG; /**< CCM Clock Gating Register, offset: 0x43EC */ + __IO uint32_t CCGR63; /**< CCM Clock Gating Register, offset: 0x43F0 */ + __IO uint32_t CCGR63_SET; /**< CCM Clock Gating Register, offset: 0x43F4 */ + __IO uint32_t CCGR63_CLR; /**< CCM Clock Gating Register, offset: 0x43F8 */ + __IO uint32_t CCGR63_TOG; /**< CCM Clock Gating Register, offset: 0x43FC */ + __IO uint32_t CCGR64; /**< CCM Clock Gating Register, offset: 0x4400 */ + __IO uint32_t CCGR64_SET; /**< CCM Clock Gating Register, offset: 0x4404 */ + __IO uint32_t CCGR64_CLR; /**< CCM Clock Gating Register, offset: 0x4408 */ + __IO uint32_t CCGR64_TOG; /**< CCM Clock Gating Register, offset: 0x440C */ + __IO uint32_t CCGR65; /**< CCM Clock Gating Register, offset: 0x4410 */ + __IO uint32_t CCGR65_SET; /**< CCM Clock Gating Register, offset: 0x4414 */ + __IO uint32_t CCGR65_CLR; /**< CCM Clock Gating Register, offset: 0x4418 */ + __IO uint32_t CCGR65_TOG; /**< CCM Clock Gating Register, offset: 0x441C */ + __IO uint32_t CCGR66; /**< CCM Clock Gating Register, offset: 0x4420 */ + __IO uint32_t CCGR66_SET; /**< CCM Clock Gating Register, offset: 0x4424 */ + __IO uint32_t CCGR66_CLR; /**< CCM Clock Gating Register, offset: 0x4428 */ + __IO uint32_t CCGR66_TOG; /**< CCM Clock Gating Register, offset: 0x442C */ + __IO uint32_t CCGR67; /**< CCM Clock Gating Register, offset: 0x4430 */ + __IO uint32_t CCGR67_SET; /**< CCM Clock Gating Register, offset: 0x4434 */ + __IO uint32_t CCGR67_CLR; /**< CCM Clock Gating Register, offset: 0x4438 */ + __IO uint32_t CCGR67_TOG; /**< CCM Clock Gating Register, offset: 0x443C */ + __IO uint32_t CCGR68; /**< CCM Clock Gating Register, offset: 0x4440 */ + __IO uint32_t CCGR68_SET; /**< CCM Clock Gating Register, offset: 0x4444 */ + __IO uint32_t CCGR68_CLR; /**< CCM Clock Gating Register, offset: 0x4448 */ + __IO uint32_t CCGR68_TOG; /**< CCM Clock Gating Register, offset: 0x444C */ + __IO uint32_t CCGR69; /**< CCM Clock Gating Register, offset: 0x4450 */ + __IO uint32_t CCGR69_SET; /**< CCM Clock Gating Register, offset: 0x4454 */ + __IO uint32_t CCGR69_CLR; /**< CCM Clock Gating Register, offset: 0x4458 */ + __IO uint32_t CCGR69_TOG; /**< CCM Clock Gating Register, offset: 0x445C */ + __IO uint32_t CCGR70; /**< CCM Clock Gating Register, offset: 0x4460 */ + __IO uint32_t CCGR70_SET; /**< CCM Clock Gating Register, offset: 0x4464 */ + __IO uint32_t CCGR70_CLR; /**< CCM Clock Gating Register, offset: 0x4468 */ + __IO uint32_t CCGR70_TOG; /**< CCM Clock Gating Register, offset: 0x446C */ + __IO uint32_t CCGR71; /**< CCM Clock Gating Register, offset: 0x4470 */ + __IO uint32_t CCGR71_SET; /**< CCM Clock Gating Register, offset: 0x4474 */ + __IO uint32_t CCGR71_CLR; /**< CCM Clock Gating Register, offset: 0x4478 */ + __IO uint32_t CCGR71_TOG; /**< CCM Clock Gating Register, offset: 0x447C */ + __IO uint32_t CCGR72; /**< CCM Clock Gating Register, offset: 0x4480 */ + __IO uint32_t CCGR72_SET; /**< CCM Clock Gating Register, offset: 0x4484 */ + __IO uint32_t CCGR72_CLR; /**< CCM Clock Gating Register, offset: 0x4488 */ + __IO uint32_t CCGR72_TOG; /**< CCM Clock Gating Register, offset: 0x448C */ + __IO uint32_t CCGR73; /**< CCM Clock Gating Register, offset: 0x4490 */ + __IO uint32_t CCGR73_SET; /**< CCM Clock Gating Register, offset: 0x4494 */ + __IO uint32_t CCGR73_CLR; /**< CCM Clock Gating Register, offset: 0x4498 */ + __IO uint32_t CCGR73_TOG; /**< CCM Clock Gating Register, offset: 0x449C */ + __IO uint32_t CCGR74; /**< CCM Clock Gating Register, offset: 0x44A0 */ + __IO uint32_t CCGR74_SET; /**< CCM Clock Gating Register, offset: 0x44A4 */ + __IO uint32_t CCGR74_CLR; /**< CCM Clock Gating Register, offset: 0x44A8 */ + __IO uint32_t CCGR74_TOG; /**< CCM Clock Gating Register, offset: 0x44AC */ + __IO uint32_t CCGR75; /**< CCM Clock Gating Register, offset: 0x44B0 */ + __IO uint32_t CCGR75_SET; /**< CCM Clock Gating Register, offset: 0x44B4 */ + __IO uint32_t CCGR75_CLR; /**< CCM Clock Gating Register, offset: 0x44B8 */ + __IO uint32_t CCGR75_TOG; /**< CCM Clock Gating Register, offset: 0x44BC */ + __IO uint32_t CCGR76; /**< CCM Clock Gating Register, offset: 0x44C0 */ + __IO uint32_t CCGR76_SET; /**< CCM Clock Gating Register, offset: 0x44C4 */ + __IO uint32_t CCGR76_CLR; /**< CCM Clock Gating Register, offset: 0x44C8 */ + __IO uint32_t CCGR76_TOG; /**< CCM Clock Gating Register, offset: 0x44CC */ + __IO uint32_t CCGR77; /**< CCM Clock Gating Register, offset: 0x44D0 */ + __IO uint32_t CCGR77_SET; /**< CCM Clock Gating Register, offset: 0x44D4 */ + __IO uint32_t CCGR77_CLR; /**< CCM Clock Gating Register, offset: 0x44D8 */ + __IO uint32_t CCGR77_TOG; /**< CCM Clock Gating Register, offset: 0x44DC */ + __IO uint32_t CCGR78; /**< CCM Clock Gating Register, offset: 0x44E0 */ + __IO uint32_t CCGR78_SET; /**< CCM Clock Gating Register, offset: 0x44E4 */ + __IO uint32_t CCGR78_CLR; /**< CCM Clock Gating Register, offset: 0x44E8 */ + __IO uint32_t CCGR78_TOG; /**< CCM Clock Gating Register, offset: 0x44EC */ + __IO uint32_t CCGR79; /**< CCM Clock Gating Register, offset: 0x44F0 */ + __IO uint32_t CCGR79_SET; /**< CCM Clock Gating Register, offset: 0x44F4 */ + __IO uint32_t CCGR79_CLR; /**< CCM Clock Gating Register, offset: 0x44F8 */ + __IO uint32_t CCGR79_TOG; /**< CCM Clock Gating Register, offset: 0x44FC */ + __IO uint32_t CCGR80; /**< CCM Clock Gating Register, offset: 0x4500 */ + __IO uint32_t CCGR80_SET; /**< CCM Clock Gating Register, offset: 0x4504 */ + __IO uint32_t CCGR80_CLR; /**< CCM Clock Gating Register, offset: 0x4508 */ + __IO uint32_t CCGR80_TOG; /**< CCM Clock Gating Register, offset: 0x450C */ + __IO uint32_t CCGR81; /**< CCM Clock Gating Register, offset: 0x4510 */ + __IO uint32_t CCGR81_SET; /**< CCM Clock Gating Register, offset: 0x4514 */ + __IO uint32_t CCGR81_CLR; /**< CCM Clock Gating Register, offset: 0x4518 */ + __IO uint32_t CCGR81_TOG; /**< CCM Clock Gating Register, offset: 0x451C */ + __IO uint32_t CCGR82; /**< CCM Clock Gating Register, offset: 0x4520 */ + __IO uint32_t CCGR82_SET; /**< CCM Clock Gating Register, offset: 0x4524 */ + __IO uint32_t CCGR82_CLR; /**< CCM Clock Gating Register, offset: 0x4528 */ + __IO uint32_t CCGR82_TOG; /**< CCM Clock Gating Register, offset: 0x452C */ + __IO uint32_t CCGR83; /**< CCM Clock Gating Register, offset: 0x4530 */ + __IO uint32_t CCGR83_SET; /**< CCM Clock Gating Register, offset: 0x4534 */ + __IO uint32_t CCGR83_CLR; /**< CCM Clock Gating Register, offset: 0x4538 */ + __IO uint32_t CCGR83_TOG; /**< CCM Clock Gating Register, offset: 0x453C */ + __IO uint32_t CCGR84; /**< CCM Clock Gating Register, offset: 0x4540 */ + __IO uint32_t CCGR84_SET; /**< CCM Clock Gating Register, offset: 0x4544 */ + __IO uint32_t CCGR84_CLR; /**< CCM Clock Gating Register, offset: 0x4548 */ + __IO uint32_t CCGR84_TOG; /**< CCM Clock Gating Register, offset: 0x454C */ + __IO uint32_t CCGR85; /**< CCM Clock Gating Register, offset: 0x4550 */ + __IO uint32_t CCGR85_SET; /**< CCM Clock Gating Register, offset: 0x4554 */ + __IO uint32_t CCGR85_CLR; /**< CCM Clock Gating Register, offset: 0x4558 */ + __IO uint32_t CCGR85_TOG; /**< CCM Clock Gating Register, offset: 0x455C */ + __IO uint32_t CCGR86; /**< CCM Clock Gating Register, offset: 0x4560 */ + __IO uint32_t CCGR86_SET; /**< CCM Clock Gating Register, offset: 0x4564 */ + __IO uint32_t CCGR86_CLR; /**< CCM Clock Gating Register, offset: 0x4568 */ + __IO uint32_t CCGR86_TOG; /**< CCM Clock Gating Register, offset: 0x456C */ + __IO uint32_t CCGR87; /**< CCM Clock Gating Register, offset: 0x4570 */ + __IO uint32_t CCGR87_SET; /**< CCM Clock Gating Register, offset: 0x4574 */ + __IO uint32_t CCGR87_CLR; /**< CCM Clock Gating Register, offset: 0x4578 */ + __IO uint32_t CCGR87_TOG; /**< CCM Clock Gating Register, offset: 0x457C */ + __IO uint32_t CCGR88; /**< CCM Clock Gating Register, offset: 0x4580 */ + __IO uint32_t CCGR88_SET; /**< CCM Clock Gating Register, offset: 0x4584 */ + __IO uint32_t CCGR88_CLR; /**< CCM Clock Gating Register, offset: 0x4588 */ + __IO uint32_t CCGR88_TOG; /**< CCM Clock Gating Register, offset: 0x458C */ + __IO uint32_t CCGR89; /**< CCM Clock Gating Register, offset: 0x4590 */ + __IO uint32_t CCGR89_SET; /**< CCM Clock Gating Register, offset: 0x4594 */ + __IO uint32_t CCGR89_CLR; /**< CCM Clock Gating Register, offset: 0x4598 */ + __IO uint32_t CCGR89_TOG; /**< CCM Clock Gating Register, offset: 0x459C */ + __IO uint32_t CCGR90; /**< CCM Clock Gating Register, offset: 0x45A0 */ + __IO uint32_t CCGR90_SET; /**< CCM Clock Gating Register, offset: 0x45A4 */ + __IO uint32_t CCGR90_CLR; /**< CCM Clock Gating Register, offset: 0x45A8 */ + __IO uint32_t CCGR90_TOG; /**< CCM Clock Gating Register, offset: 0x45AC */ + __IO uint32_t CCGR91; /**< CCM Clock Gating Register, offset: 0x45B0 */ + __IO uint32_t CCGR91_SET; /**< CCM Clock Gating Register, offset: 0x45B4 */ + __IO uint32_t CCGR91_CLR; /**< CCM Clock Gating Register, offset: 0x45B8 */ + __IO uint32_t CCGR91_TOG; /**< CCM Clock Gating Register, offset: 0x45BC */ + __IO uint32_t CCGR92; /**< CCM Clock Gating Register, offset: 0x45C0 */ + __IO uint32_t CCGR92_SET; /**< CCM Clock Gating Register, offset: 0x45C4 */ + __IO uint32_t CCGR92_CLR; /**< CCM Clock Gating Register, offset: 0x45C8 */ + __IO uint32_t CCGR92_TOG; /**< CCM Clock Gating Register, offset: 0x45CC */ + __IO uint32_t CCGR93; /**< CCM Clock Gating Register, offset: 0x45D0 */ + __IO uint32_t CCGR93_SET; /**< CCM Clock Gating Register, offset: 0x45D4 */ + __IO uint32_t CCGR93_CLR; /**< CCM Clock Gating Register, offset: 0x45D8 */ + __IO uint32_t CCGR93_TOG; /**< CCM Clock Gating Register, offset: 0x45DC */ + __IO uint32_t CCGR94; /**< CCM Clock Gating Register, offset: 0x45E0 */ + __IO uint32_t CCGR94_SET; /**< CCM Clock Gating Register, offset: 0x45E4 */ + __IO uint32_t CCGR94_CLR; /**< CCM Clock Gating Register, offset: 0x45E8 */ + __IO uint32_t CCGR94_TOG; /**< CCM Clock Gating Register, offset: 0x45EC */ + __IO uint32_t CCGR95; /**< CCM Clock Gating Register, offset: 0x45F0 */ + __IO uint32_t CCGR95_SET; /**< CCM Clock Gating Register, offset: 0x45F4 */ + __IO uint32_t CCGR95_CLR; /**< CCM Clock Gating Register, offset: 0x45F8 */ + __IO uint32_t CCGR95_TOG; /**< CCM Clock Gating Register, offset: 0x45FC */ + __IO uint32_t CCGR96; /**< CCM Clock Gating Register, offset: 0x4600 */ + __IO uint32_t CCGR96_SET; /**< CCM Clock Gating Register, offset: 0x4604 */ + __IO uint32_t CCGR96_CLR; /**< CCM Clock Gating Register, offset: 0x4608 */ + __IO uint32_t CCGR96_TOG; /**< CCM Clock Gating Register, offset: 0x460C */ + __IO uint32_t CCGR97; /**< CCM Clock Gating Register, offset: 0x4610 */ + __IO uint32_t CCGR97_SET; /**< CCM Clock Gating Register, offset: 0x4614 */ + __IO uint32_t CCGR97_CLR; /**< CCM Clock Gating Register, offset: 0x4618 */ + __IO uint32_t CCGR97_TOG; /**< CCM Clock Gating Register, offset: 0x461C */ + __IO uint32_t CCGR98; /**< CCM Clock Gating Register, offset: 0x4620 */ + __IO uint32_t CCGR98_SET; /**< CCM Clock Gating Register, offset: 0x4624 */ + __IO uint32_t CCGR98_CLR; /**< CCM Clock Gating Register, offset: 0x4628 */ + __IO uint32_t CCGR98_TOG; /**< CCM Clock Gating Register, offset: 0x462C */ + __IO uint32_t CCGR99; /**< CCM Clock Gating Register, offset: 0x4630 */ + __IO uint32_t CCGR99_SET; /**< CCM Clock Gating Register, offset: 0x4634 */ + __IO uint32_t CCGR99_CLR; /**< CCM Clock Gating Register, offset: 0x4638 */ + __IO uint32_t CCGR99_TOG; /**< CCM Clock Gating Register, offset: 0x463C */ + __IO uint32_t CCGR100; /**< CCM Clock Gating Register, offset: 0x4640 */ + __IO uint32_t CCGR100_SET; /**< CCM Clock Gating Register, offset: 0x4644 */ + __IO uint32_t CCGR100_CLR; /**< CCM Clock Gating Register, offset: 0x4648 */ + __IO uint32_t CCGR100_TOG; /**< CCM Clock Gating Register, offset: 0x464C */ + __IO uint32_t CCGR101; /**< CCM Clock Gating Register, offset: 0x4650 */ + __IO uint32_t CCGR101_SET; /**< CCM Clock Gating Register, offset: 0x4654 */ + __IO uint32_t CCGR101_CLR; /**< CCM Clock Gating Register, offset: 0x4658 */ + __IO uint32_t CCGR101_TOG; /**< CCM Clock Gating Register, offset: 0x465C */ + __IO uint32_t CCGR102; /**< CCM Clock Gating Register, offset: 0x4660 */ + __IO uint32_t CCGR102_SET; /**< CCM Clock Gating Register, offset: 0x4664 */ + __IO uint32_t CCGR102_CLR; /**< CCM Clock Gating Register, offset: 0x4668 */ + __IO uint32_t CCGR102_TOG; /**< CCM Clock Gating Register, offset: 0x466C */ + __IO uint32_t CCGR103; /**< CCM Clock Gating Register, offset: 0x4670 */ + __IO uint32_t CCGR103_SET; /**< CCM Clock Gating Register, offset: 0x4674 */ + __IO uint32_t CCGR103_CLR; /**< CCM Clock Gating Register, offset: 0x4678 */ + __IO uint32_t CCGR103_TOG; /**< CCM Clock Gating Register, offset: 0x467C */ + __IO uint32_t CCGR104; /**< CCM Clock Gating Register, offset: 0x4680 */ + __IO uint32_t CCGR104_SET; /**< CCM Clock Gating Register, offset: 0x4684 */ + __IO uint32_t CCGR104_CLR; /**< CCM Clock Gating Register, offset: 0x4688 */ + __IO uint32_t CCGR104_TOG; /**< CCM Clock Gating Register, offset: 0x468C */ + __IO uint32_t CCGR105; /**< CCM Clock Gating Register, offset: 0x4690 */ + __IO uint32_t CCGR105_SET; /**< CCM Clock Gating Register, offset: 0x4694 */ + __IO uint32_t CCGR105_CLR; /**< CCM Clock Gating Register, offset: 0x4698 */ + __IO uint32_t CCGR105_TOG; /**< CCM Clock Gating Register, offset: 0x469C */ + __IO uint32_t CCGR106; /**< CCM Clock Gating Register, offset: 0x46A0 */ + __IO uint32_t CCGR106_SET; /**< CCM Clock Gating Register, offset: 0x46A4 */ + __IO uint32_t CCGR106_CLR; /**< CCM Clock Gating Register, offset: 0x46A8 */ + __IO uint32_t CCGR106_TOG; /**< CCM Clock Gating Register, offset: 0x46AC */ + __IO uint32_t CCGR107; /**< CCM Clock Gating Register, offset: 0x46B0 */ + __IO uint32_t CCGR107_SET; /**< CCM Clock Gating Register, offset: 0x46B4 */ + __IO uint32_t CCGR107_CLR; /**< CCM Clock Gating Register, offset: 0x46B8 */ + __IO uint32_t CCGR107_TOG; /**< CCM Clock Gating Register, offset: 0x46BC */ + __IO uint32_t CCGR108; /**< CCM Clock Gating Register, offset: 0x46C0 */ + __IO uint32_t CCGR108_SET; /**< CCM Clock Gating Register, offset: 0x46C4 */ + __IO uint32_t CCGR108_CLR; /**< CCM Clock Gating Register, offset: 0x46C8 */ + __IO uint32_t CCGR108_TOG; /**< CCM Clock Gating Register, offset: 0x46CC */ + __IO uint32_t CCGR109; /**< CCM Clock Gating Register, offset: 0x46D0 */ + __IO uint32_t CCGR109_SET; /**< CCM Clock Gating Register, offset: 0x46D4 */ + __IO uint32_t CCGR109_CLR; /**< CCM Clock Gating Register, offset: 0x46D8 */ + __IO uint32_t CCGR109_TOG; /**< CCM Clock Gating Register, offset: 0x46DC */ + __IO uint32_t CCGR110; /**< CCM Clock Gating Register, offset: 0x46E0 */ + __IO uint32_t CCGR110_SET; /**< CCM Clock Gating Register, offset: 0x46E4 */ + __IO uint32_t CCGR110_CLR; /**< CCM Clock Gating Register, offset: 0x46E8 */ + __IO uint32_t CCGR110_TOG; /**< CCM Clock Gating Register, offset: 0x46EC */ + __IO uint32_t CCGR111; /**< CCM Clock Gating Register, offset: 0x46F0 */ + __IO uint32_t CCGR111_SET; /**< CCM Clock Gating Register, offset: 0x46F4 */ + __IO uint32_t CCGR111_CLR; /**< CCM Clock Gating Register, offset: 0x46F8 */ + __IO uint32_t CCGR111_TOG; /**< CCM Clock Gating Register, offset: 0x46FC */ + __IO uint32_t CCGR112; /**< CCM Clock Gating Register, offset: 0x4700 */ + __IO uint32_t CCGR112_SET; /**< CCM Clock Gating Register, offset: 0x4704 */ + __IO uint32_t CCGR112_CLR; /**< CCM Clock Gating Register, offset: 0x4708 */ + __IO uint32_t CCGR112_TOG; /**< CCM Clock Gating Register, offset: 0x470C */ + __IO uint32_t CCGR113; /**< CCM Clock Gating Register, offset: 0x4710 */ + __IO uint32_t CCGR113_SET; /**< CCM Clock Gating Register, offset: 0x4714 */ + __IO uint32_t CCGR113_CLR; /**< CCM Clock Gating Register, offset: 0x4718 */ + __IO uint32_t CCGR113_TOG; /**< CCM Clock Gating Register, offset: 0x471C */ + __IO uint32_t CCGR114; /**< CCM Clock Gating Register, offset: 0x4720 */ + __IO uint32_t CCGR114_SET; /**< CCM Clock Gating Register, offset: 0x4724 */ + __IO uint32_t CCGR114_CLR; /**< CCM Clock Gating Register, offset: 0x4728 */ + __IO uint32_t CCGR114_TOG; /**< CCM Clock Gating Register, offset: 0x472C */ + __IO uint32_t CCGR115; /**< CCM Clock Gating Register, offset: 0x4730 */ + __IO uint32_t CCGR115_SET; /**< CCM Clock Gating Register, offset: 0x4734 */ + __IO uint32_t CCGR115_CLR; /**< CCM Clock Gating Register, offset: 0x4738 */ + __IO uint32_t CCGR115_TOG; /**< CCM Clock Gating Register, offset: 0x473C */ + __IO uint32_t CCGR116; /**< CCM Clock Gating Register, offset: 0x4740 */ + __IO uint32_t CCGR116_SET; /**< CCM Clock Gating Register, offset: 0x4744 */ + __IO uint32_t CCGR116_CLR; /**< CCM Clock Gating Register, offset: 0x4748 */ + __IO uint32_t CCGR116_TOG; /**< CCM Clock Gating Register, offset: 0x474C */ + __IO uint32_t CCGR117; /**< CCM Clock Gating Register, offset: 0x4750 */ + __IO uint32_t CCGR117_SET; /**< CCM Clock Gating Register, offset: 0x4754 */ + __IO uint32_t CCGR117_CLR; /**< CCM Clock Gating Register, offset: 0x4758 */ + __IO uint32_t CCGR117_TOG; /**< CCM Clock Gating Register, offset: 0x475C */ + __IO uint32_t CCGR118; /**< CCM Clock Gating Register, offset: 0x4760 */ + __IO uint32_t CCGR118_SET; /**< CCM Clock Gating Register, offset: 0x4764 */ + __IO uint32_t CCGR118_CLR; /**< CCM Clock Gating Register, offset: 0x4768 */ + __IO uint32_t CCGR118_TOG; /**< CCM Clock Gating Register, offset: 0x476C */ + __IO uint32_t CCGR119; /**< CCM Clock Gating Register, offset: 0x4770 */ + __IO uint32_t CCGR119_SET; /**< CCM Clock Gating Register, offset: 0x4774 */ + __IO uint32_t CCGR119_CLR; /**< CCM Clock Gating Register, offset: 0x4778 */ + __IO uint32_t CCGR119_TOG; /**< CCM Clock Gating Register, offset: 0x477C */ + __IO uint32_t CCGR120; /**< CCM Clock Gating Register, offset: 0x4780 */ + __IO uint32_t CCGR120_SET; /**< CCM Clock Gating Register, offset: 0x4784 */ + __IO uint32_t CCGR120_CLR; /**< CCM Clock Gating Register, offset: 0x4788 */ + __IO uint32_t CCGR120_TOG; /**< CCM Clock Gating Register, offset: 0x478C */ + __IO uint32_t CCGR121; /**< CCM Clock Gating Register, offset: 0x4790 */ + __IO uint32_t CCGR121_SET; /**< CCM Clock Gating Register, offset: 0x4794 */ + __IO uint32_t CCGR121_CLR; /**< CCM Clock Gating Register, offset: 0x4798 */ + __IO uint32_t CCGR121_TOG; /**< CCM Clock Gating Register, offset: 0x479C */ + __IO uint32_t CCGR122; /**< CCM Clock Gating Register, offset: 0x47A0 */ + __IO uint32_t CCGR122_SET; /**< CCM Clock Gating Register, offset: 0x47A4 */ + __IO uint32_t CCGR122_CLR; /**< CCM Clock Gating Register, offset: 0x47A8 */ + __IO uint32_t CCGR122_TOG; /**< CCM Clock Gating Register, offset: 0x47AC */ + __IO uint32_t CCGR123; /**< CCM Clock Gating Register, offset: 0x47B0 */ + __IO uint32_t CCGR123_SET; /**< CCM Clock Gating Register, offset: 0x47B4 */ + __IO uint32_t CCGR123_CLR; /**< CCM Clock Gating Register, offset: 0x47B8 */ + __IO uint32_t CCGR123_TOG; /**< CCM Clock Gating Register, offset: 0x47BC */ + __IO uint32_t CCGR124; /**< CCM Clock Gating Register, offset: 0x47C0 */ + __IO uint32_t CCGR124_SET; /**< CCM Clock Gating Register, offset: 0x47C4 */ + __IO uint32_t CCGR124_CLR; /**< CCM Clock Gating Register, offset: 0x47C8 */ + __IO uint32_t CCGR124_TOG; /**< CCM Clock Gating Register, offset: 0x47CC */ + __IO uint32_t CCGR125; /**< CCM Clock Gating Register, offset: 0x47D0 */ + __IO uint32_t CCGR125_SET; /**< CCM Clock Gating Register, offset: 0x47D4 */ + __IO uint32_t CCGR125_CLR; /**< CCM Clock Gating Register, offset: 0x47D8 */ + __IO uint32_t CCGR125_TOG; /**< CCM Clock Gating Register, offset: 0x47DC */ + __IO uint32_t CCGR126; /**< CCM Clock Gating Register, offset: 0x47E0 */ + __IO uint32_t CCGR126_SET; /**< CCM Clock Gating Register, offset: 0x47E4 */ + __IO uint32_t CCGR126_CLR; /**< CCM Clock Gating Register, offset: 0x47E8 */ + __IO uint32_t CCGR126_TOG; /**< CCM Clock Gating Register, offset: 0x47EC */ + __IO uint32_t CCGR127; /**< CCM Clock Gating Register, offset: 0x47F0 */ + __IO uint32_t CCGR127_SET; /**< CCM Clock Gating Register, offset: 0x47F4 */ + __IO uint32_t CCGR127_CLR; /**< CCM Clock Gating Register, offset: 0x47F8 */ + __IO uint32_t CCGR127_TOG; /**< CCM Clock Gating Register, offset: 0x47FC */ + __IO uint32_t CCGR128; /**< CCM Clock Gating Register, offset: 0x4800 */ + __IO uint32_t CCGR128_SET; /**< CCM Clock Gating Register, offset: 0x4804 */ + __IO uint32_t CCGR128_CLR; /**< CCM Clock Gating Register, offset: 0x4808 */ + __IO uint32_t CCGR128_TOG; /**< CCM Clock Gating Register, offset: 0x480C */ + __IO uint32_t CCGR129; /**< CCM Clock Gating Register, offset: 0x4810 */ + __IO uint32_t CCGR129_SET; /**< CCM Clock Gating Register, offset: 0x4814 */ + __IO uint32_t CCGR129_CLR; /**< CCM Clock Gating Register, offset: 0x4818 */ + __IO uint32_t CCGR129_TOG; /**< CCM Clock Gating Register, offset: 0x481C */ + __IO uint32_t CCGR130; /**< CCM Clock Gating Register, offset: 0x4820 */ + __IO uint32_t CCGR130_SET; /**< CCM Clock Gating Register, offset: 0x4824 */ + __IO uint32_t CCGR130_CLR; /**< CCM Clock Gating Register, offset: 0x4828 */ + __IO uint32_t CCGR130_TOG; /**< CCM Clock Gating Register, offset: 0x482C */ + __IO uint32_t CCGR131; /**< CCM Clock Gating Register, offset: 0x4830 */ + __IO uint32_t CCGR131_SET; /**< CCM Clock Gating Register, offset: 0x4834 */ + __IO uint32_t CCGR131_CLR; /**< CCM Clock Gating Register, offset: 0x4838 */ + __IO uint32_t CCGR131_TOG; /**< CCM Clock Gating Register, offset: 0x483C */ + __IO uint32_t CCGR132; /**< CCM Clock Gating Register, offset: 0x4840 */ + __IO uint32_t CCGR132_SET; /**< CCM Clock Gating Register, offset: 0x4844 */ + __IO uint32_t CCGR132_CLR; /**< CCM Clock Gating Register, offset: 0x4848 */ + __IO uint32_t CCGR132_TOG; /**< CCM Clock Gating Register, offset: 0x484C */ + __IO uint32_t CCGR133; /**< CCM Clock Gating Register, offset: 0x4850 */ + __IO uint32_t CCGR133_SET; /**< CCM Clock Gating Register, offset: 0x4854 */ + __IO uint32_t CCGR133_CLR; /**< CCM Clock Gating Register, offset: 0x4858 */ + __IO uint32_t CCGR133_TOG; /**< CCM Clock Gating Register, offset: 0x485C */ + __IO uint32_t CCGR134; /**< CCM Clock Gating Register, offset: 0x4860 */ + __IO uint32_t CCGR134_SET; /**< CCM Clock Gating Register, offset: 0x4864 */ + __IO uint32_t CCGR134_CLR; /**< CCM Clock Gating Register, offset: 0x4868 */ + __IO uint32_t CCGR134_TOG; /**< CCM Clock Gating Register, offset: 0x486C */ + __IO uint32_t CCGR135; /**< CCM Clock Gating Register, offset: 0x4870 */ + __IO uint32_t CCGR135_SET; /**< CCM Clock Gating Register, offset: 0x4874 */ + __IO uint32_t CCGR135_CLR; /**< CCM Clock Gating Register, offset: 0x4878 */ + __IO uint32_t CCGR135_TOG; /**< CCM Clock Gating Register, offset: 0x487C */ + __IO uint32_t CCGR136; /**< CCM Clock Gating Register, offset: 0x4880 */ + __IO uint32_t CCGR136_SET; /**< CCM Clock Gating Register, offset: 0x4884 */ + __IO uint32_t CCGR136_CLR; /**< CCM Clock Gating Register, offset: 0x4888 */ + __IO uint32_t CCGR136_TOG; /**< CCM Clock Gating Register, offset: 0x488C */ + __IO uint32_t CCGR137; /**< CCM Clock Gating Register, offset: 0x4890 */ + __IO uint32_t CCGR137_SET; /**< CCM Clock Gating Register, offset: 0x4894 */ + __IO uint32_t CCGR137_CLR; /**< CCM Clock Gating Register, offset: 0x4898 */ + __IO uint32_t CCGR137_TOG; /**< CCM Clock Gating Register, offset: 0x489C */ + __IO uint32_t CCGR138; /**< CCM Clock Gating Register, offset: 0x48A0 */ + __IO uint32_t CCGR138_SET; /**< CCM Clock Gating Register, offset: 0x48A4 */ + __IO uint32_t CCGR138_CLR; /**< CCM Clock Gating Register, offset: 0x48A8 */ + __IO uint32_t CCGR138_TOG; /**< CCM Clock Gating Register, offset: 0x48AC */ + __IO uint32_t CCGR139; /**< CCM Clock Gating Register, offset: 0x48B0 */ + __IO uint32_t CCGR139_SET; /**< CCM Clock Gating Register, offset: 0x48B4 */ + __IO uint32_t CCGR139_CLR; /**< CCM Clock Gating Register, offset: 0x48B8 */ + __IO uint32_t CCGR139_TOG; /**< CCM Clock Gating Register, offset: 0x48BC */ + __IO uint32_t CCGR140; /**< CCM Clock Gating Register, offset: 0x48C0 */ + __IO uint32_t CCGR140_SET; /**< CCM Clock Gating Register, offset: 0x48C4 */ + __IO uint32_t CCGR140_CLR; /**< CCM Clock Gating Register, offset: 0x48C8 */ + __IO uint32_t CCGR140_TOG; /**< CCM Clock Gating Register, offset: 0x48CC */ + __IO uint32_t CCGR141; /**< CCM Clock Gating Register, offset: 0x48D0 */ + __IO uint32_t CCGR141_SET; /**< CCM Clock Gating Register, offset: 0x48D4 */ + __IO uint32_t CCGR141_CLR; /**< CCM Clock Gating Register, offset: 0x48D8 */ + __IO uint32_t CCGR141_TOG; /**< CCM Clock Gating Register, offset: 0x48DC */ + __IO uint32_t CCGR142; /**< CCM Clock Gating Register, offset: 0x48E0 */ + __IO uint32_t CCGR142_SET; /**< CCM Clock Gating Register, offset: 0x48E4 */ + __IO uint32_t CCGR142_CLR; /**< CCM Clock Gating Register, offset: 0x48E8 */ + __IO uint32_t CCGR142_TOG; /**< CCM Clock Gating Register, offset: 0x48EC */ + __IO uint32_t CCGR143; /**< CCM Clock Gating Register, offset: 0x48F0 */ + __IO uint32_t CCGR143_SET; /**< CCM Clock Gating Register, offset: 0x48F4 */ + __IO uint32_t CCGR143_CLR; /**< CCM Clock Gating Register, offset: 0x48F8 */ + __IO uint32_t CCGR143_TOG; /**< CCM Clock Gating Register, offset: 0x48FC */ + __IO uint32_t CCGR144; /**< CCM Clock Gating Register, offset: 0x4900 */ + __IO uint32_t CCGR144_SET; /**< CCM Clock Gating Register, offset: 0x4904 */ + __IO uint32_t CCGR144_CLR; /**< CCM Clock Gating Register, offset: 0x4908 */ + __IO uint32_t CCGR144_TOG; /**< CCM Clock Gating Register, offset: 0x490C */ + __IO uint32_t CCGR145; /**< CCM Clock Gating Register, offset: 0x4910 */ + __IO uint32_t CCGR145_SET; /**< CCM Clock Gating Register, offset: 0x4914 */ + __IO uint32_t CCGR145_CLR; /**< CCM Clock Gating Register, offset: 0x4918 */ + __IO uint32_t CCGR145_TOG; /**< CCM Clock Gating Register, offset: 0x491C */ + __IO uint32_t CCGR146; /**< CCM Clock Gating Register, offset: 0x4920 */ + __IO uint32_t CCGR146_SET; /**< CCM Clock Gating Register, offset: 0x4924 */ + __IO uint32_t CCGR146_CLR; /**< CCM Clock Gating Register, offset: 0x4928 */ + __IO uint32_t CCGR146_TOG; /**< CCM Clock Gating Register, offset: 0x492C */ + __IO uint32_t CCGR147; /**< CCM Clock Gating Register, offset: 0x4930 */ + __IO uint32_t CCGR147_SET; /**< CCM Clock Gating Register, offset: 0x4934 */ + __IO uint32_t CCGR147_CLR; /**< CCM Clock Gating Register, offset: 0x4938 */ + __IO uint32_t CCGR147_TOG; /**< CCM Clock Gating Register, offset: 0x493C */ + __IO uint32_t CCGR148; /**< CCM Clock Gating Register, offset: 0x4940 */ + __IO uint32_t CCGR148_SET; /**< CCM Clock Gating Register, offset: 0x4944 */ + __IO uint32_t CCGR148_CLR; /**< CCM Clock Gating Register, offset: 0x4948 */ + __IO uint32_t CCGR148_TOG; /**< CCM Clock Gating Register, offset: 0x494C */ + __IO uint32_t CCGR149; /**< CCM Clock Gating Register, offset: 0x4950 */ + __IO uint32_t CCGR149_SET; /**< CCM Clock Gating Register, offset: 0x4954 */ + __IO uint32_t CCGR149_CLR; /**< CCM Clock Gating Register, offset: 0x4958 */ + __IO uint32_t CCGR149_TOG; /**< CCM Clock Gating Register, offset: 0x495C */ + __IO uint32_t CCGR150; /**< CCM Clock Gating Register, offset: 0x4960 */ + __IO uint32_t CCGR150_SET; /**< CCM Clock Gating Register, offset: 0x4964 */ + __IO uint32_t CCGR150_CLR; /**< CCM Clock Gating Register, offset: 0x4968 */ + __IO uint32_t CCGR150_TOG; /**< CCM Clock Gating Register, offset: 0x496C */ + __IO uint32_t CCGR151; /**< CCM Clock Gating Register, offset: 0x4970 */ + __IO uint32_t CCGR151_SET; /**< CCM Clock Gating Register, offset: 0x4974 */ + __IO uint32_t CCGR151_CLR; /**< CCM Clock Gating Register, offset: 0x4978 */ + __IO uint32_t CCGR151_TOG; /**< CCM Clock Gating Register, offset: 0x497C */ + __IO uint32_t CCGR152; /**< CCM Clock Gating Register, offset: 0x4980 */ + __IO uint32_t CCGR152_SET; /**< CCM Clock Gating Register, offset: 0x4984 */ + __IO uint32_t CCGR152_CLR; /**< CCM Clock Gating Register, offset: 0x4988 */ + __IO uint32_t CCGR152_TOG; /**< CCM Clock Gating Register, offset: 0x498C */ + __IO uint32_t CCGR153; /**< CCM Clock Gating Register, offset: 0x4990 */ + __IO uint32_t CCGR153_SET; /**< CCM Clock Gating Register, offset: 0x4994 */ + __IO uint32_t CCGR153_CLR; /**< CCM Clock Gating Register, offset: 0x4998 */ + __IO uint32_t CCGR153_TOG; /**< CCM Clock Gating Register, offset: 0x499C */ + __IO uint32_t CCGR154; /**< CCM Clock Gating Register, offset: 0x49A0 */ + __IO uint32_t CCGR154_SET; /**< CCM Clock Gating Register, offset: 0x49A4 */ + __IO uint32_t CCGR154_CLR; /**< CCM Clock Gating Register, offset: 0x49A8 */ + __IO uint32_t CCGR154_TOG; /**< CCM Clock Gating Register, offset: 0x49AC */ + __IO uint32_t CCGR155; /**< CCM Clock Gating Register, offset: 0x49B0 */ + __IO uint32_t CCGR155_SET; /**< CCM Clock Gating Register, offset: 0x49B4 */ + __IO uint32_t CCGR155_CLR; /**< CCM Clock Gating Register, offset: 0x49B8 */ + __IO uint32_t CCGR155_TOG; /**< CCM Clock Gating Register, offset: 0x49BC */ + __IO uint32_t CCGR156; /**< CCM Clock Gating Register, offset: 0x49C0 */ + __IO uint32_t CCGR156_SET; /**< CCM Clock Gating Register, offset: 0x49C4 */ + __IO uint32_t CCGR156_CLR; /**< CCM Clock Gating Register, offset: 0x49C8 */ + __IO uint32_t CCGR156_TOG; /**< CCM Clock Gating Register, offset: 0x49CC */ + __IO uint32_t CCGR157; /**< CCM Clock Gating Register, offset: 0x49D0 */ + __IO uint32_t CCGR157_SET; /**< CCM Clock Gating Register, offset: 0x49D4 */ + __IO uint32_t CCGR157_CLR; /**< CCM Clock Gating Register, offset: 0x49D8 */ + __IO uint32_t CCGR157_TOG; /**< CCM Clock Gating Register, offset: 0x49DC */ + __IO uint32_t CCGR158; /**< CCM Clock Gating Register, offset: 0x49E0 */ + __IO uint32_t CCGR158_SET; /**< CCM Clock Gating Register, offset: 0x49E4 */ + __IO uint32_t CCGR158_CLR; /**< CCM Clock Gating Register, offset: 0x49E8 */ + __IO uint32_t CCGR158_TOG; /**< CCM Clock Gating Register, offset: 0x49EC */ + __IO uint32_t CCGR159; /**< CCM Clock Gating Register, offset: 0x49F0 */ + __IO uint32_t CCGR159_SET; /**< CCM Clock Gating Register, offset: 0x49F4 */ + __IO uint32_t CCGR159_CLR; /**< CCM Clock Gating Register, offset: 0x49F8 */ + __IO uint32_t CCGR159_TOG; /**< CCM Clock Gating Register, offset: 0x49FC */ + __IO uint32_t CCGR160; /**< CCM Clock Gating Register, offset: 0x4A00 */ + __IO uint32_t CCGR160_SET; /**< CCM Clock Gating Register, offset: 0x4A04 */ + __IO uint32_t CCGR160_CLR; /**< CCM Clock Gating Register, offset: 0x4A08 */ + __IO uint32_t CCGR160_TOG; /**< CCM Clock Gating Register, offset: 0x4A0C */ + __IO uint32_t CCGR161; /**< CCM Clock Gating Register, offset: 0x4A10 */ + __IO uint32_t CCGR161_SET; /**< CCM Clock Gating Register, offset: 0x4A14 */ + __IO uint32_t CCGR161_CLR; /**< CCM Clock Gating Register, offset: 0x4A18 */ + __IO uint32_t CCGR161_TOG; /**< CCM Clock Gating Register, offset: 0x4A1C */ + __IO uint32_t CCGR162; /**< CCM Clock Gating Register, offset: 0x4A20 */ + __IO uint32_t CCGR162_SET; /**< CCM Clock Gating Register, offset: 0x4A24 */ + __IO uint32_t CCGR162_CLR; /**< CCM Clock Gating Register, offset: 0x4A28 */ + __IO uint32_t CCGR162_TOG; /**< CCM Clock Gating Register, offset: 0x4A2C */ + __IO uint32_t CCGR163; /**< CCM Clock Gating Register, offset: 0x4A30 */ + __IO uint32_t CCGR163_SET; /**< CCM Clock Gating Register, offset: 0x4A34 */ + __IO uint32_t CCGR163_CLR; /**< CCM Clock Gating Register, offset: 0x4A38 */ + __IO uint32_t CCGR163_TOG; /**< CCM Clock Gating Register, offset: 0x4A3C */ + __IO uint32_t CCGR164; /**< CCM Clock Gating Register, offset: 0x4A40 */ + __IO uint32_t CCGR164_SET; /**< CCM Clock Gating Register, offset: 0x4A44 */ + __IO uint32_t CCGR164_CLR; /**< CCM Clock Gating Register, offset: 0x4A48 */ + __IO uint32_t CCGR164_TOG; /**< CCM Clock Gating Register, offset: 0x4A4C */ + __IO uint32_t CCGR165; /**< CCM Clock Gating Register, offset: 0x4A50 */ + __IO uint32_t CCGR165_SET; /**< CCM Clock Gating Register, offset: 0x4A54 */ + __IO uint32_t CCGR165_CLR; /**< CCM Clock Gating Register, offset: 0x4A58 */ + __IO uint32_t CCGR165_TOG; /**< CCM Clock Gating Register, offset: 0x4A5C */ + __IO uint32_t CCGR166; /**< CCM Clock Gating Register, offset: 0x4A60 */ + __IO uint32_t CCGR166_SET; /**< CCM Clock Gating Register, offset: 0x4A64 */ + __IO uint32_t CCGR166_CLR; /**< CCM Clock Gating Register, offset: 0x4A68 */ + __IO uint32_t CCGR166_TOG; /**< CCM Clock Gating Register, offset: 0x4A6C */ + __IO uint32_t CCGR167; /**< CCM Clock Gating Register, offset: 0x4A70 */ + __IO uint32_t CCGR167_SET; /**< CCM Clock Gating Register, offset: 0x4A74 */ + __IO uint32_t CCGR167_CLR; /**< CCM Clock Gating Register, offset: 0x4A78 */ + __IO uint32_t CCGR167_TOG; /**< CCM Clock Gating Register, offset: 0x4A7C */ + __IO uint32_t CCGR168; /**< CCM Clock Gating Register, offset: 0x4A80 */ + __IO uint32_t CCGR168_SET; /**< CCM Clock Gating Register, offset: 0x4A84 */ + __IO uint32_t CCGR168_CLR; /**< CCM Clock Gating Register, offset: 0x4A88 */ + __IO uint32_t CCGR168_TOG; /**< CCM Clock Gating Register, offset: 0x4A8C */ + __IO uint32_t CCGR169; /**< CCM Clock Gating Register, offset: 0x4A90 */ + __IO uint32_t CCGR169_SET; /**< CCM Clock Gating Register, offset: 0x4A94 */ + __IO uint32_t CCGR169_CLR; /**< CCM Clock Gating Register, offset: 0x4A98 */ + __IO uint32_t CCGR169_TOG; /**< CCM Clock Gating Register, offset: 0x4A9C */ + __IO uint32_t CCGR170; /**< CCM Clock Gating Register, offset: 0x4AA0 */ + __IO uint32_t CCGR170_SET; /**< CCM Clock Gating Register, offset: 0x4AA4 */ + __IO uint32_t CCGR170_CLR; /**< CCM Clock Gating Register, offset: 0x4AA8 */ + __IO uint32_t CCGR170_TOG; /**< CCM Clock Gating Register, offset: 0x4AAC */ + __IO uint32_t CCGR171; /**< CCM Clock Gating Register, offset: 0x4AB0 */ + __IO uint32_t CCGR171_SET; /**< CCM Clock Gating Register, offset: 0x4AB4 */ + __IO uint32_t CCGR171_CLR; /**< CCM Clock Gating Register, offset: 0x4AB8 */ + __IO uint32_t CCGR171_TOG; /**< CCM Clock Gating Register, offset: 0x4ABC */ + __IO uint32_t CCGR172; /**< CCM Clock Gating Register, offset: 0x4AC0 */ + __IO uint32_t CCGR172_SET; /**< CCM Clock Gating Register, offset: 0x4AC4 */ + __IO uint32_t CCGR172_CLR; /**< CCM Clock Gating Register, offset: 0x4AC8 */ + __IO uint32_t CCGR172_TOG; /**< CCM Clock Gating Register, offset: 0x4ACC */ + __IO uint32_t CCGR173; /**< CCM Clock Gating Register, offset: 0x4AD0 */ + __IO uint32_t CCGR173_SET; /**< CCM Clock Gating Register, offset: 0x4AD4 */ + __IO uint32_t CCGR173_CLR; /**< CCM Clock Gating Register, offset: 0x4AD8 */ + __IO uint32_t CCGR173_TOG; /**< CCM Clock Gating Register, offset: 0x4ADC */ + __IO uint32_t CCGR174; /**< CCM Clock Gating Register, offset: 0x4AE0 */ + __IO uint32_t CCGR174_SET; /**< CCM Clock Gating Register, offset: 0x4AE4 */ + __IO uint32_t CCGR174_CLR; /**< CCM Clock Gating Register, offset: 0x4AE8 */ + __IO uint32_t CCGR174_TOG; /**< CCM Clock Gating Register, offset: 0x4AEC */ + __IO uint32_t CCGR175; /**< CCM Clock Gating Register, offset: 0x4AF0 */ + __IO uint32_t CCGR175_SET; /**< CCM Clock Gating Register, offset: 0x4AF4 */ + __IO uint32_t CCGR175_CLR; /**< CCM Clock Gating Register, offset: 0x4AF8 */ + __IO uint32_t CCGR175_TOG; /**< CCM Clock Gating Register, offset: 0x4AFC */ + __IO uint32_t CCGR176; /**< CCM Clock Gating Register, offset: 0x4B00 */ + __IO uint32_t CCGR176_SET; /**< CCM Clock Gating Register, offset: 0x4B04 */ + __IO uint32_t CCGR176_CLR; /**< CCM Clock Gating Register, offset: 0x4B08 */ + __IO uint32_t CCGR176_TOG; /**< CCM Clock Gating Register, offset: 0x4B0C */ + __IO uint32_t CCGR177; /**< CCM Clock Gating Register, offset: 0x4B10 */ + __IO uint32_t CCGR177_SET; /**< CCM Clock Gating Register, offset: 0x4B14 */ + __IO uint32_t CCGR177_CLR; /**< CCM Clock Gating Register, offset: 0x4B18 */ + __IO uint32_t CCGR177_TOG; /**< CCM Clock Gating Register, offset: 0x4B1C */ + __IO uint32_t CCGR178; /**< CCM Clock Gating Register, offset: 0x4B20 */ + __IO uint32_t CCGR178_SET; /**< CCM Clock Gating Register, offset: 0x4B24 */ + __IO uint32_t CCGR178_CLR; /**< CCM Clock Gating Register, offset: 0x4B28 */ + __IO uint32_t CCGR178_TOG; /**< CCM Clock Gating Register, offset: 0x4B2C */ + __IO uint32_t CCGR179; /**< CCM Clock Gating Register, offset: 0x4B30 */ + __IO uint32_t CCGR179_SET; /**< CCM Clock Gating Register, offset: 0x4B34 */ + __IO uint32_t CCGR179_CLR; /**< CCM Clock Gating Register, offset: 0x4B38 */ + __IO uint32_t CCGR179_TOG; /**< CCM Clock Gating Register, offset: 0x4B3C */ + __IO uint32_t CCGR180; /**< CCM Clock Gating Register, offset: 0x4B40 */ + __IO uint32_t CCGR180_SET; /**< CCM Clock Gating Register, offset: 0x4B44 */ + __IO uint32_t CCGR180_CLR; /**< CCM Clock Gating Register, offset: 0x4B48 */ + __IO uint32_t CCGR180_TOG; /**< CCM Clock Gating Register, offset: 0x4B4C */ + __IO uint32_t CCGR181; /**< CCM Clock Gating Register, offset: 0x4B50 */ + __IO uint32_t CCGR181_SET; /**< CCM Clock Gating Register, offset: 0x4B54 */ + __IO uint32_t CCGR181_CLR; /**< CCM Clock Gating Register, offset: 0x4B58 */ + __IO uint32_t CCGR181_TOG; /**< CCM Clock Gating Register, offset: 0x4B5C */ + __IO uint32_t CCGR182; /**< CCM Clock Gating Register, offset: 0x4B60 */ + __IO uint32_t CCGR182_SET; /**< CCM Clock Gating Register, offset: 0x4B64 */ + __IO uint32_t CCGR182_CLR; /**< CCM Clock Gating Register, offset: 0x4B68 */ + __IO uint32_t CCGR182_TOG; /**< CCM Clock Gating Register, offset: 0x4B6C */ + __IO uint32_t CCGR183; /**< CCM Clock Gating Register, offset: 0x4B70 */ + __IO uint32_t CCGR183_SET; /**< CCM Clock Gating Register, offset: 0x4B74 */ + __IO uint32_t CCGR183_CLR; /**< CCM Clock Gating Register, offset: 0x4B78 */ + __IO uint32_t CCGR183_TOG; /**< CCM Clock Gating Register, offset: 0x4B7C */ + __IO uint32_t CCGR184; /**< CCM Clock Gating Register, offset: 0x4B80 */ + __IO uint32_t CCGR184_SET; /**< CCM Clock Gating Register, offset: 0x4B84 */ + __IO uint32_t CCGR184_CLR; /**< CCM Clock Gating Register, offset: 0x4B88 */ + __IO uint32_t CCGR184_TOG; /**< CCM Clock Gating Register, offset: 0x4B8C */ + __IO uint32_t CCGR185; /**< CCM Clock Gating Register, offset: 0x4B90 */ + __IO uint32_t CCGR185_SET; /**< CCM Clock Gating Register, offset: 0x4B94 */ + __IO uint32_t CCGR185_CLR; /**< CCM Clock Gating Register, offset: 0x4B98 */ + __IO uint32_t CCGR185_TOG; /**< CCM Clock Gating Register, offset: 0x4B9C */ + __IO uint32_t CCGR186; /**< CCM Clock Gating Register, offset: 0x4BA0 */ + __IO uint32_t CCGR186_SET; /**< CCM Clock Gating Register, offset: 0x4BA4 */ + __IO uint32_t CCGR186_CLR; /**< CCM Clock Gating Register, offset: 0x4BA8 */ + __IO uint32_t CCGR186_TOG; /**< CCM Clock Gating Register, offset: 0x4BAC */ + __IO uint32_t CCGR187; /**< CCM Clock Gating Register, offset: 0x4BB0 */ + __IO uint32_t CCGR187_SET; /**< CCM Clock Gating Register, offset: 0x4BB4 */ + __IO uint32_t CCGR187_CLR; /**< CCM Clock Gating Register, offset: 0x4BB8 */ + __IO uint32_t CCGR187_TOG; /**< CCM Clock Gating Register, offset: 0x4BBC */ + __IO uint32_t CCGR188; /**< CCM Clock Gating Register, offset: 0x4BC0 */ + __IO uint32_t CCGR188_SET; /**< CCM Clock Gating Register, offset: 0x4BC4 */ + __IO uint32_t CCGR188_CLR; /**< CCM Clock Gating Register, offset: 0x4BC8 */ + __IO uint32_t CCGR188_TOG; /**< CCM Clock Gating Register, offset: 0x4BCC */ + __IO uint32_t CCGR189; /**< CCM Clock Gating Register, offset: 0x4BD0 */ + __IO uint32_t CCGR189_SET; /**< CCM Clock Gating Register, offset: 0x4BD4 */ + __IO uint32_t CCGR189_CLR; /**< CCM Clock Gating Register, offset: 0x4BD8 */ + __IO uint32_t CCGR189_TOG; /**< CCM Clock Gating Register, offset: 0x4BDC */ + __IO uint32_t CCGR190; /**< CCM Clock Gating Register, offset: 0x4BE0 */ + __IO uint32_t CCGR190_SET; /**< CCM Clock Gating Register, offset: 0x4BE4 */ + __IO uint32_t CCGR190_CLR; /**< CCM Clock Gating Register, offset: 0x4BE8 */ + __IO uint32_t CCGR190_TOG; /**< CCM Clock Gating Register, offset: 0x4BEC */ + uint8_t RESERVED_1[13328]; + __IO uint32_t TARGET_ROOT0; /**< Target Register, offset: 0x8000 */ + __IO uint32_t TARGET_ROOT0_SET; /**< Target Register, offset: 0x8004 */ + __IO uint32_t TARGET_ROOT0_CLR; /**< Target Register, offset: 0x8008 */ + __IO uint32_t TARGET_ROOT0_TOG; /**< Target Register, offset: 0x800C */ + uint8_t RESERVED_2[16]; + __IO uint32_t POST0; /**< Post Divider Register, offset: 0x8020 */ + __IO uint32_t POST_ROOT0_SET; /**< Post Divider Register, offset: 0x8024 */ + __IO uint32_t POST_ROOT0_CLR; /**< Post Divider Register, offset: 0x8028 */ + __IO uint32_t POST_ROOT0_TOG; /**< Post Divider Register, offset: 0x802C */ + __IO uint32_t PRE0; /**< Pre Divider Register, offset: 0x8030 */ + __IO uint32_t PRE_ROOT0_SET; /**< Pre Divider Register, offset: 0x8034 */ + __IO uint32_t PRE_ROOT0_CLR; /**< Pre Divider Register, offset: 0x8038 */ + __IO uint32_t PRE_ROOT0_TOG; /**< Pre Divider Register, offset: 0x803C */ + uint8_t RESERVED_3[48]; + __IO uint32_t ACCESS_CTRL0; /**< Access Control Register, offset: 0x8070 */ + __IO uint32_t ACCESS_CTRL0_ROOT_SET; /**< Access Control Register, offset: 0x8074 */ + __IO uint32_t ACCESS_CTRL0_ROOT_CLR; /**< Access Control Register, offset: 0x8078 */ + __IO uint32_t ACCESS_CTRL0_ROOT_TOG; /**< Access Control Register, offset: 0x807C */ + __IO uint32_t TARGET_ROOT1; /**< Target Register, offset: 0x8080 */ + __IO uint32_t TARGET_ROOT1_SET; /**< Target Register, offset: 0x8084 */ + __IO uint32_t TARGET_ROOT1_CLR; /**< Target Register, offset: 0x8088 */ + __IO uint32_t TARGET_ROOT1_TOG; /**< Target Register, offset: 0x808C */ + uint8_t RESERVED_4[16]; + __IO uint32_t POST1; /**< Post Divider Register, offset: 0x80A0 */ + __IO uint32_t POST_ROOT1_SET; /**< Post Divider Register, offset: 0x80A4 */ + __IO uint32_t POST_ROOT1_CLR; /**< Post Divider Register, offset: 0x80A8 */ + __IO uint32_t POST_ROOT1_TOG; /**< Post Divider Register, offset: 0x80AC */ + __IO uint32_t PRE1; /**< Pre Divider Register, offset: 0x80B0 */ + __IO uint32_t PRE_ROOT1_SET; /**< Pre Divider Register, offset: 0x80B4 */ + __IO uint32_t PRE_ROOT1_CLR; /**< Pre Divider Register, offset: 0x80B8 */ + __IO uint32_t PRE_ROOT1_TOG; /**< Pre Divider Register, offset: 0x80BC */ + uint8_t RESERVED_5[48]; + __IO uint32_t ACCESS_CTRL1; /**< Access Control Register, offset: 0x80F0 */ + __IO uint32_t ACCESS_CTRL1_ROOT_SET; /**< Access Control Register, offset: 0x80F4 */ + __IO uint32_t ACCESS_CTRL1_ROOT_CLR; /**< Access Control Register, offset: 0x80F8 */ + __IO uint32_t ACCESS_CTRL1_ROOT_TOG; /**< Access Control Register, offset: 0x80FC */ + __IO uint32_t TARGET_ROOT2; /**< Target Register, offset: 0x8100 */ + __IO uint32_t TARGET_ROOT2_SET; /**< Target Register, offset: 0x8104 */ + __IO uint32_t TARGET_ROOT2_CLR; /**< Target Register, offset: 0x8108 */ + __IO uint32_t TARGET_ROOT2_TOG; /**< Target Register, offset: 0x810C */ + uint8_t RESERVED_6[16]; + __IO uint32_t POST2; /**< Post Divider Register, offset: 0x8120 */ + __IO uint32_t POST_ROOT2_SET; /**< Post Divider Register, offset: 0x8124 */ + __IO uint32_t POST_ROOT2_CLR; /**< Post Divider Register, offset: 0x8128 */ + __IO uint32_t POST_ROOT2_TOG; /**< Post Divider Register, offset: 0x812C */ + __IO uint32_t PRE2; /**< Pre Divider Register, offset: 0x8130 */ + __IO uint32_t PRE_ROOT2_SET; /**< Pre Divider Register, offset: 0x8134 */ + __IO uint32_t PRE_ROOT2_CLR; /**< Pre Divider Register, offset: 0x8138 */ + __IO uint32_t PRE_ROOT2_TOG; /**< Pre Divider Register, offset: 0x813C */ + uint8_t RESERVED_7[48]; + __IO uint32_t ACCESS_CTRL2; /**< Access Control Register, offset: 0x8170 */ + __IO uint32_t ACCESS_CTRL2_ROOT_SET; /**< Access Control Register, offset: 0x8174 */ + __IO uint32_t ACCESS_CTRL2_ROOT_CLR; /**< Access Control Register, offset: 0x8178 */ + __IO uint32_t ACCESS_CTRL2_ROOT_TOG; /**< Access Control Register, offset: 0x817C */ + __IO uint32_t TARGET_ROOT3; /**< Target Register, offset: 0x8180 */ + __IO uint32_t TARGET_ROOT3_SET; /**< Target Register, offset: 0x8184 */ + __IO uint32_t TARGET_ROOT3_CLR; /**< Target Register, offset: 0x8188 */ + __IO uint32_t TARGET_ROOT3_TOG; /**< Target Register, offset: 0x818C */ + uint8_t RESERVED_8[16]; + __IO uint32_t POST3; /**< Post Divider Register, offset: 0x81A0 */ + __IO uint32_t POST_ROOT3_SET; /**< Post Divider Register, offset: 0x81A4 */ + __IO uint32_t POST_ROOT3_CLR; /**< Post Divider Register, offset: 0x81A8 */ + __IO uint32_t POST_ROOT3_TOG; /**< Post Divider Register, offset: 0x81AC */ + __IO uint32_t PRE3; /**< Pre Divider Register, offset: 0x81B0 */ + __IO uint32_t PRE_ROOT3_SET; /**< Pre Divider Register, offset: 0x81B4 */ + __IO uint32_t PRE_ROOT3_CLR; /**< Pre Divider Register, offset: 0x81B8 */ + __IO uint32_t PRE_ROOT3_TOG; /**< Pre Divider Register, offset: 0x81BC */ + uint8_t RESERVED_9[48]; + __IO uint32_t ACCESS_CTRL3; /**< Access Control Register, offset: 0x81F0 */ + __IO uint32_t ACCESS_CTRL3_ROOT_SET; /**< Access Control Register, offset: 0x81F4 */ + __IO uint32_t ACCESS_CTRL3_ROOT_CLR; /**< Access Control Register, offset: 0x81F8 */ + __IO uint32_t ACCESS_CTRL3_ROOT_TOG; /**< Access Control Register, offset: 0x81FC */ + __IO uint32_t TARGET_ROOT4; /**< Target Register, offset: 0x8200 */ + __IO uint32_t TARGET_ROOT4_SET; /**< Target Register, offset: 0x8204 */ + __IO uint32_t TARGET_ROOT4_CLR; /**< Target Register, offset: 0x8208 */ + __IO uint32_t TARGET_ROOT4_TOG; /**< Target Register, offset: 0x820C */ + uint8_t RESERVED_10[16]; + __IO uint32_t POST4; /**< Post Divider Register, offset: 0x8220 */ + __IO uint32_t POST_ROOT4_SET; /**< Post Divider Register, offset: 0x8224 */ + __IO uint32_t POST_ROOT4_CLR; /**< Post Divider Register, offset: 0x8228 */ + __IO uint32_t POST_ROOT4_TOG; /**< Post Divider Register, offset: 0x822C */ + __IO uint32_t PRE4; /**< Pre Divider Register, offset: 0x8230 */ + __IO uint32_t PRE_ROOT4_SET; /**< Pre Divider Register, offset: 0x8234 */ + __IO uint32_t PRE_ROOT4_CLR; /**< Pre Divider Register, offset: 0x8238 */ + __IO uint32_t PRE_ROOT4_TOG; /**< Pre Divider Register, offset: 0x823C */ + uint8_t RESERVED_11[48]; + __IO uint32_t ACCESS_CTRL4; /**< Access Control Register, offset: 0x8270 */ + __IO uint32_t ACCESS_CTRL4_ROOT_SET; /**< Access Control Register, offset: 0x8274 */ + __IO uint32_t ACCESS_CTRL4_ROOT_CLR; /**< Access Control Register, offset: 0x8278 */ + __IO uint32_t ACCESS_CTRL4_ROOT_TOG; /**< Access Control Register, offset: 0x827C */ + __IO uint32_t TARGET_ROOT5; /**< Target Register, offset: 0x8280 */ + __IO uint32_t TARGET_ROOT5_SET; /**< Target Register, offset: 0x8284 */ + __IO uint32_t TARGET_ROOT5_CLR; /**< Target Register, offset: 0x8288 */ + __IO uint32_t TARGET_ROOT5_TOG; /**< Target Register, offset: 0x828C */ + uint8_t RESERVED_12[16]; + __IO uint32_t POST5; /**< Post Divider Register, offset: 0x82A0 */ + __IO uint32_t POST_ROOT5_SET; /**< Post Divider Register, offset: 0x82A4 */ + __IO uint32_t POST_ROOT5_CLR; /**< Post Divider Register, offset: 0x82A8 */ + __IO uint32_t POST_ROOT5_TOG; /**< Post Divider Register, offset: 0x82AC */ + __IO uint32_t PRE5; /**< Pre Divider Register, offset: 0x82B0 */ + __IO uint32_t PRE_ROOT5_SET; /**< Pre Divider Register, offset: 0x82B4 */ + __IO uint32_t PRE_ROOT5_CLR; /**< Pre Divider Register, offset: 0x82B8 */ + __IO uint32_t PRE_ROOT5_TOG; /**< Pre Divider Register, offset: 0x82BC */ + uint8_t RESERVED_13[48]; + __IO uint32_t ACCESS_CTRL5; /**< Access Control Register, offset: 0x82F0 */ + __IO uint32_t ACCESS_CTRL5_ROOT_SET; /**< Access Control Register, offset: 0x82F4 */ + __IO uint32_t ACCESS_CTRL5_ROOT_CLR; /**< Access Control Register, offset: 0x82F8 */ + __IO uint32_t ACCESS_CTRL5_ROOT_TOG; /**< Access Control Register, offset: 0x82FC */ + __IO uint32_t TARGET_ROOT6; /**< Target Register, offset: 0x8300 */ + __IO uint32_t TARGET_ROOT6_SET; /**< Target Register, offset: 0x8304 */ + __IO uint32_t TARGET_ROOT6_CLR; /**< Target Register, offset: 0x8308 */ + __IO uint32_t TARGET_ROOT6_TOG; /**< Target Register, offset: 0x830C */ + uint8_t RESERVED_14[16]; + __IO uint32_t POST6; /**< Post Divider Register, offset: 0x8320 */ + __IO uint32_t POST_ROOT6_SET; /**< Post Divider Register, offset: 0x8324 */ + __IO uint32_t POST_ROOT6_CLR; /**< Post Divider Register, offset: 0x8328 */ + __IO uint32_t POST_ROOT6_TOG; /**< Post Divider Register, offset: 0x832C */ + __IO uint32_t PRE6; /**< Pre Divider Register, offset: 0x8330 */ + __IO uint32_t PRE_ROOT6_SET; /**< Pre Divider Register, offset: 0x8334 */ + __IO uint32_t PRE_ROOT6_CLR; /**< Pre Divider Register, offset: 0x8338 */ + __IO uint32_t PRE_ROOT6_TOG; /**< Pre Divider Register, offset: 0x833C */ + uint8_t RESERVED_15[48]; + __IO uint32_t ACCESS_CTRL6; /**< Access Control Register, offset: 0x8370 */ + __IO uint32_t ACCESS_CTRL6_ROOT_SET; /**< Access Control Register, offset: 0x8374 */ + __IO uint32_t ACCESS_CTRL6_ROOT_CLR; /**< Access Control Register, offset: 0x8378 */ + __IO uint32_t ACCESS_CTRL6_ROOT_TOG; /**< Access Control Register, offset: 0x837C */ + __IO uint32_t TARGET_ROOT7; /**< Target Register, offset: 0x8380 */ + __IO uint32_t TARGET_ROOT7_SET; /**< Target Register, offset: 0x8384 */ + __IO uint32_t TARGET_ROOT7_CLR; /**< Target Register, offset: 0x8388 */ + __IO uint32_t TARGET_ROOT7_TOG; /**< Target Register, offset: 0x838C */ + uint8_t RESERVED_16[16]; + __IO uint32_t POST7; /**< Post Divider Register, offset: 0x83A0 */ + __IO uint32_t POST_ROOT7_SET; /**< Post Divider Register, offset: 0x83A4 */ + __IO uint32_t POST_ROOT7_CLR; /**< Post Divider Register, offset: 0x83A8 */ + __IO uint32_t POST_ROOT7_TOG; /**< Post Divider Register, offset: 0x83AC */ + __IO uint32_t PRE7; /**< Pre Divider Register, offset: 0x83B0 */ + __IO uint32_t PRE_ROOT7_SET; /**< Pre Divider Register, offset: 0x83B4 */ + __IO uint32_t PRE_ROOT7_CLR; /**< Pre Divider Register, offset: 0x83B8 */ + __IO uint32_t PRE_ROOT7_TOG; /**< Pre Divider Register, offset: 0x83BC */ + uint8_t RESERVED_17[48]; + __IO uint32_t ACCESS_CTRL7; /**< Access Control Register, offset: 0x83F0 */ + __IO uint32_t ACCESS_CTRL7_ROOT_SET; /**< Access Control Register, offset: 0x83F4 */ + __IO uint32_t ACCESS_CTRL7_ROOT_CLR; /**< Access Control Register, offset: 0x83F8 */ + __IO uint32_t ACCESS_CTRL7_ROOT_TOG; /**< Access Control Register, offset: 0x83FC */ + __IO uint32_t TARGET_ROOT8; /**< Target Register, offset: 0x8400 */ + __IO uint32_t TARGET_ROOT8_SET; /**< Target Register, offset: 0x8404 */ + __IO uint32_t TARGET_ROOT8_CLR; /**< Target Register, offset: 0x8408 */ + __IO uint32_t TARGET_ROOT8_TOG; /**< Target Register, offset: 0x840C */ + uint8_t RESERVED_18[16]; + __IO uint32_t POST8; /**< Post Divider Register, offset: 0x8420 */ + __IO uint32_t POST_ROOT8_SET; /**< Post Divider Register, offset: 0x8424 */ + __IO uint32_t POST_ROOT8_CLR; /**< Post Divider Register, offset: 0x8428 */ + __IO uint32_t POST_ROOT8_TOG; /**< Post Divider Register, offset: 0x842C */ + __IO uint32_t PRE8; /**< Pre Divider Register, offset: 0x8430 */ + __IO uint32_t PRE_ROOT8_SET; /**< Pre Divider Register, offset: 0x8434 */ + __IO uint32_t PRE_ROOT8_CLR; /**< Pre Divider Register, offset: 0x8438 */ + __IO uint32_t PRE_ROOT8_TOG; /**< Pre Divider Register, offset: 0x843C */ + uint8_t RESERVED_19[48]; + __IO uint32_t ACCESS_CTRL8; /**< Access Control Register, offset: 0x8470 */ + __IO uint32_t ACCESS_CTRL8_ROOT_SET; /**< Access Control Register, offset: 0x8474 */ + __IO uint32_t ACCESS_CTRL8_ROOT_CLR; /**< Access Control Register, offset: 0x8478 */ + __IO uint32_t ACCESS_CTRL8_ROOT_TOG; /**< Access Control Register, offset: 0x847C */ + __IO uint32_t TARGET_ROOT9; /**< Target Register, offset: 0x8480 */ + __IO uint32_t TARGET_ROOT9_SET; /**< Target Register, offset: 0x8484 */ + __IO uint32_t TARGET_ROOT9_CLR; /**< Target Register, offset: 0x8488 */ + __IO uint32_t TARGET_ROOT9_TOG; /**< Target Register, offset: 0x848C */ + uint8_t RESERVED_20[16]; + __IO uint32_t POST9; /**< Post Divider Register, offset: 0x84A0 */ + __IO uint32_t POST_ROOT9_SET; /**< Post Divider Register, offset: 0x84A4 */ + __IO uint32_t POST_ROOT9_CLR; /**< Post Divider Register, offset: 0x84A8 */ + __IO uint32_t POST_ROOT9_TOG; /**< Post Divider Register, offset: 0x84AC */ + __IO uint32_t PRE9; /**< Pre Divider Register, offset: 0x84B0 */ + __IO uint32_t PRE_ROOT9_SET; /**< Pre Divider Register, offset: 0x84B4 */ + __IO uint32_t PRE_ROOT9_CLR; /**< Pre Divider Register, offset: 0x84B8 */ + __IO uint32_t PRE_ROOT9_TOG; /**< Pre Divider Register, offset: 0x84BC */ + uint8_t RESERVED_21[48]; + __IO uint32_t ACCESS_CTRL9; /**< Access Control Register, offset: 0x84F0 */ + __IO uint32_t ACCESS_CTRL9_ROOT_SET; /**< Access Control Register, offset: 0x84F4 */ + __IO uint32_t ACCESS_CTRL9_ROOT_CLR; /**< Access Control Register, offset: 0x84F8 */ + __IO uint32_t ACCESS_CTRL9_ROOT_TOG; /**< Access Control Register, offset: 0x84FC */ + __IO uint32_t TARGET_ROOT10; /**< Target Register, offset: 0x8500 */ + __IO uint32_t TARGET_ROOT10_SET; /**< Target Register, offset: 0x8504 */ + __IO uint32_t TARGET_ROOT10_CLR; /**< Target Register, offset: 0x8508 */ + __IO uint32_t TARGET_ROOT10_TOG; /**< Target Register, offset: 0x850C */ + uint8_t RESERVED_22[16]; + __IO uint32_t POST10; /**< Post Divider Register, offset: 0x8520 */ + __IO uint32_t POST_ROOT10_SET; /**< Post Divider Register, offset: 0x8524 */ + __IO uint32_t POST_ROOT10_CLR; /**< Post Divider Register, offset: 0x8528 */ + __IO uint32_t POST_ROOT10_TOG; /**< Post Divider Register, offset: 0x852C */ + __IO uint32_t PRE10; /**< Pre Divider Register, offset: 0x8530 */ + __IO uint32_t PRE_ROOT10_SET; /**< Pre Divider Register, offset: 0x8534 */ + __IO uint32_t PRE_ROOT10_CLR; /**< Pre Divider Register, offset: 0x8538 */ + __IO uint32_t PRE_ROOT10_TOG; /**< Pre Divider Register, offset: 0x853C */ + uint8_t RESERVED_23[48]; + __IO uint32_t ACCESS_CTRL10; /**< Access Control Register, offset: 0x8570 */ + __IO uint32_t ACCESS_CTRL10_ROOT_SET; /**< Access Control Register, offset: 0x8574 */ + __IO uint32_t ACCESS_CTRL10_ROOT_CLR; /**< Access Control Register, offset: 0x8578 */ + __IO uint32_t ACCESS_CTRL10_ROOT_TOG; /**< Access Control Register, offset: 0x857C */ + __IO uint32_t TARGET_ROOT11; /**< Target Register, offset: 0x8580 */ + __IO uint32_t TARGET_ROOT11_SET; /**< Target Register, offset: 0x8584 */ + __IO uint32_t TARGET_ROOT11_CLR; /**< Target Register, offset: 0x8588 */ + __IO uint32_t TARGET_ROOT11_TOG; /**< Target Register, offset: 0x858C */ + uint8_t RESERVED_24[16]; + __IO uint32_t POST11; /**< Post Divider Register, offset: 0x85A0 */ + __IO uint32_t POST_ROOT11_SET; /**< Post Divider Register, offset: 0x85A4 */ + __IO uint32_t POST_ROOT11_CLR; /**< Post Divider Register, offset: 0x85A8 */ + __IO uint32_t POST_ROOT11_TOG; /**< Post Divider Register, offset: 0x85AC */ + __IO uint32_t PRE11; /**< Pre Divider Register, offset: 0x85B0 */ + __IO uint32_t PRE_ROOT11_SET; /**< Pre Divider Register, offset: 0x85B4 */ + __IO uint32_t PRE_ROOT11_CLR; /**< Pre Divider Register, offset: 0x85B8 */ + __IO uint32_t PRE_ROOT11_TOG; /**< Pre Divider Register, offset: 0x85BC */ + uint8_t RESERVED_25[48]; + __IO uint32_t ACCESS_CTRL11; /**< Access Control Register, offset: 0x85F0 */ + __IO uint32_t ACCESS_CTRL11_ROOT_SET; /**< Access Control Register, offset: 0x85F4 */ + __IO uint32_t ACCESS_CTRL11_ROOT_CLR; /**< Access Control Register, offset: 0x85F8 */ + __IO uint32_t ACCESS_CTRL11_ROOT_TOG; /**< Access Control Register, offset: 0x85FC */ + __IO uint32_t TARGET_ROOT12; /**< Target Register, offset: 0x8600 */ + __IO uint32_t TARGET_ROOT12_SET; /**< Target Register, offset: 0x8604 */ + __IO uint32_t TARGET_ROOT12_CLR; /**< Target Register, offset: 0x8608 */ + __IO uint32_t TARGET_ROOT12_TOG; /**< Target Register, offset: 0x860C */ + uint8_t RESERVED_26[16]; + __IO uint32_t POST12; /**< Post Divider Register, offset: 0x8620 */ + __IO uint32_t POST_ROOT12_SET; /**< Post Divider Register, offset: 0x8624 */ + __IO uint32_t POST_ROOT12_CLR; /**< Post Divider Register, offset: 0x8628 */ + __IO uint32_t POST_ROOT12_TOG; /**< Post Divider Register, offset: 0x862C */ + __IO uint32_t PRE12; /**< Pre Divider Register, offset: 0x8630 */ + __IO uint32_t PRE_ROOT12_SET; /**< Pre Divider Register, offset: 0x8634 */ + __IO uint32_t PRE_ROOT12_CLR; /**< Pre Divider Register, offset: 0x8638 */ + __IO uint32_t PRE_ROOT12_TOG; /**< Pre Divider Register, offset: 0x863C */ + uint8_t RESERVED_27[48]; + __IO uint32_t ACCESS_CTRL12; /**< Access Control Register, offset: 0x8670 */ + __IO uint32_t ACCESS_CTRL12_ROOT_SET; /**< Access Control Register, offset: 0x8674 */ + __IO uint32_t ACCESS_CTRL12_ROOT_CLR; /**< Access Control Register, offset: 0x8678 */ + __IO uint32_t ACCESS_CTRL12_ROOT_TOG; /**< Access Control Register, offset: 0x867C */ + __IO uint32_t TARGET_ROOT13; /**< Target Register, offset: 0x8680 */ + __IO uint32_t TARGET_ROOT13_SET; /**< Target Register, offset: 0x8684 */ + __IO uint32_t TARGET_ROOT13_CLR; /**< Target Register, offset: 0x8688 */ + __IO uint32_t TARGET_ROOT13_TOG; /**< Target Register, offset: 0x868C */ + uint8_t RESERVED_28[16]; + __IO uint32_t POST13; /**< Post Divider Register, offset: 0x86A0 */ + __IO uint32_t POST_ROOT13_SET; /**< Post Divider Register, offset: 0x86A4 */ + __IO uint32_t POST_ROOT13_CLR; /**< Post Divider Register, offset: 0x86A8 */ + __IO uint32_t POST_ROOT13_TOG; /**< Post Divider Register, offset: 0x86AC */ + __IO uint32_t PRE13; /**< Pre Divider Register, offset: 0x86B0 */ + __IO uint32_t PRE_ROOT13_SET; /**< Pre Divider Register, offset: 0x86B4 */ + __IO uint32_t PRE_ROOT13_CLR; /**< Pre Divider Register, offset: 0x86B8 */ + __IO uint32_t PRE_ROOT13_TOG; /**< Pre Divider Register, offset: 0x86BC */ + uint8_t RESERVED_29[48]; + __IO uint32_t ACCESS_CTRL13; /**< Access Control Register, offset: 0x86F0 */ + __IO uint32_t ACCESS_CTRL13_ROOT_SET; /**< Access Control Register, offset: 0x86F4 */ + __IO uint32_t ACCESS_CTRL13_ROOT_CLR; /**< Access Control Register, offset: 0x86F8 */ + __IO uint32_t ACCESS_CTRL13_ROOT_TOG; /**< Access Control Register, offset: 0x86FC */ + __IO uint32_t TARGET_ROOT14; /**< Target Register, offset: 0x8700 */ + __IO uint32_t TARGET_ROOT14_SET; /**< Target Register, offset: 0x8704 */ + __IO uint32_t TARGET_ROOT14_CLR; /**< Target Register, offset: 0x8708 */ + __IO uint32_t TARGET_ROOT14_TOG; /**< Target Register, offset: 0x870C */ + uint8_t RESERVED_30[16]; + __IO uint32_t POST14; /**< Post Divider Register, offset: 0x8720 */ + __IO uint32_t POST_ROOT14_SET; /**< Post Divider Register, offset: 0x8724 */ + __IO uint32_t POST_ROOT14_CLR; /**< Post Divider Register, offset: 0x8728 */ + __IO uint32_t POST_ROOT14_TOG; /**< Post Divider Register, offset: 0x872C */ + __IO uint32_t PRE14; /**< Pre Divider Register, offset: 0x8730 */ + __IO uint32_t PRE_ROOT14_SET; /**< Pre Divider Register, offset: 0x8734 */ + __IO uint32_t PRE_ROOT14_CLR; /**< Pre Divider Register, offset: 0x8738 */ + __IO uint32_t PRE_ROOT14_TOG; /**< Pre Divider Register, offset: 0x873C */ + uint8_t RESERVED_31[48]; + __IO uint32_t ACCESS_CTRL14; /**< Access Control Register, offset: 0x8770 */ + __IO uint32_t ACCESS_CTRL14_ROOT_SET; /**< Access Control Register, offset: 0x8774 */ + __IO uint32_t ACCESS_CTRL14_ROOT_CLR; /**< Access Control Register, offset: 0x8778 */ + __IO uint32_t ACCESS_CTRL14_ROOT_TOG; /**< Access Control Register, offset: 0x877C */ + __IO uint32_t TARGET_ROOT15; /**< Target Register, offset: 0x8780 */ + __IO uint32_t TARGET_ROOT15_SET; /**< Target Register, offset: 0x8784 */ + __IO uint32_t TARGET_ROOT15_CLR; /**< Target Register, offset: 0x8788 */ + __IO uint32_t TARGET_ROOT15_TOG; /**< Target Register, offset: 0x878C */ + uint8_t RESERVED_32[16]; + __IO uint32_t POST15; /**< Post Divider Register, offset: 0x87A0 */ + __IO uint32_t POST_ROOT15_SET; /**< Post Divider Register, offset: 0x87A4 */ + __IO uint32_t POST_ROOT15_CLR; /**< Post Divider Register, offset: 0x87A8 */ + __IO uint32_t POST_ROOT15_TOG; /**< Post Divider Register, offset: 0x87AC */ + __IO uint32_t PRE15; /**< Pre Divider Register, offset: 0x87B0 */ + __IO uint32_t PRE_ROOT15_SET; /**< Pre Divider Register, offset: 0x87B4 */ + __IO uint32_t PRE_ROOT15_CLR; /**< Pre Divider Register, offset: 0x87B8 */ + __IO uint32_t PRE_ROOT15_TOG; /**< Pre Divider Register, offset: 0x87BC */ + uint8_t RESERVED_33[48]; + __IO uint32_t ACCESS_CTRL15; /**< Access Control Register, offset: 0x87F0 */ + __IO uint32_t ACCESS_CTRL15_ROOT_SET; /**< Access Control Register, offset: 0x87F4 */ + __IO uint32_t ACCESS_CTRL15_ROOT_CLR; /**< Access Control Register, offset: 0x87F8 */ + __IO uint32_t ACCESS_CTRL15_ROOT_TOG; /**< Access Control Register, offset: 0x87FC */ + __IO uint32_t TARGET_ROOT16; /**< Target Register, offset: 0x8800 */ + __IO uint32_t TARGET_ROOT16_SET; /**< Target Register, offset: 0x8804 */ + __IO uint32_t TARGET_ROOT16_CLR; /**< Target Register, offset: 0x8808 */ + __IO uint32_t TARGET_ROOT16_TOG; /**< Target Register, offset: 0x880C */ + uint8_t RESERVED_34[16]; + __IO uint32_t POST16; /**< Post Divider Register, offset: 0x8820 */ + __IO uint32_t POST_ROOT16_SET; /**< Post Divider Register, offset: 0x8824 */ + __IO uint32_t POST_ROOT16_CLR; /**< Post Divider Register, offset: 0x8828 */ + __IO uint32_t POST_ROOT16_TOG; /**< Post Divider Register, offset: 0x882C */ + __IO uint32_t PRE16; /**< Pre Divider Register, offset: 0x8830 */ + __IO uint32_t PRE_ROOT16_SET; /**< Pre Divider Register, offset: 0x8834 */ + __IO uint32_t PRE_ROOT16_CLR; /**< Pre Divider Register, offset: 0x8838 */ + __IO uint32_t PRE_ROOT16_TOG; /**< Pre Divider Register, offset: 0x883C */ + uint8_t RESERVED_35[48]; + __IO uint32_t ACCESS_CTRL16; /**< Access Control Register, offset: 0x8870 */ + __IO uint32_t ACCESS_CTRL16_ROOT_SET; /**< Access Control Register, offset: 0x8874 */ + __IO uint32_t ACCESS_CTRL16_ROOT_CLR; /**< Access Control Register, offset: 0x8878 */ + __IO uint32_t ACCESS_CTRL16_ROOT_TOG; /**< Access Control Register, offset: 0x887C */ + __IO uint32_t TARGET_ROOT17; /**< Target Register, offset: 0x8880 */ + __IO uint32_t TARGET_ROOT17_SET; /**< Target Register, offset: 0x8884 */ + __IO uint32_t TARGET_ROOT17_CLR; /**< Target Register, offset: 0x8888 */ + __IO uint32_t TARGET_ROOT17_TOG; /**< Target Register, offset: 0x888C */ + uint8_t RESERVED_36[16]; + __IO uint32_t POST17; /**< Post Divider Register, offset: 0x88A0 */ + __IO uint32_t POST_ROOT17_SET; /**< Post Divider Register, offset: 0x88A4 */ + __IO uint32_t POST_ROOT17_CLR; /**< Post Divider Register, offset: 0x88A8 */ + __IO uint32_t POST_ROOT17_TOG; /**< Post Divider Register, offset: 0x88AC */ + __IO uint32_t PRE17; /**< Pre Divider Register, offset: 0x88B0 */ + __IO uint32_t PRE_ROOT17_SET; /**< Pre Divider Register, offset: 0x88B4 */ + __IO uint32_t PRE_ROOT17_CLR; /**< Pre Divider Register, offset: 0x88B8 */ + __IO uint32_t PRE_ROOT17_TOG; /**< Pre Divider Register, offset: 0x88BC */ + uint8_t RESERVED_37[48]; + __IO uint32_t ACCESS_CTRL17; /**< Access Control Register, offset: 0x88F0 */ + __IO uint32_t ACCESS_CTRL17_ROOT_SET; /**< Access Control Register, offset: 0x88F4 */ + __IO uint32_t ACCESS_CTRL17_ROOT_CLR; /**< Access Control Register, offset: 0x88F8 */ + __IO uint32_t ACCESS_CTRL17_ROOT_TOG; /**< Access Control Register, offset: 0x88FC */ + __IO uint32_t TARGET_ROOT18; /**< Target Register, offset: 0x8900 */ + __IO uint32_t TARGET_ROOT18_SET; /**< Target Register, offset: 0x8904 */ + __IO uint32_t TARGET_ROOT18_CLR; /**< Target Register, offset: 0x8908 */ + __IO uint32_t TARGET_ROOT18_TOG; /**< Target Register, offset: 0x890C */ + uint8_t RESERVED_38[16]; + __IO uint32_t POST18; /**< Post Divider Register, offset: 0x8920 */ + __IO uint32_t POST_ROOT18_SET; /**< Post Divider Register, offset: 0x8924 */ + __IO uint32_t POST_ROOT18_CLR; /**< Post Divider Register, offset: 0x8928 */ + __IO uint32_t POST_ROOT18_TOG; /**< Post Divider Register, offset: 0x892C */ + __IO uint32_t PRE18; /**< Pre Divider Register, offset: 0x8930 */ + __IO uint32_t PRE_ROOT18_SET; /**< Pre Divider Register, offset: 0x8934 */ + __IO uint32_t PRE_ROOT18_CLR; /**< Pre Divider Register, offset: 0x8938 */ + __IO uint32_t PRE_ROOT18_TOG; /**< Pre Divider Register, offset: 0x893C */ + uint8_t RESERVED_39[48]; + __IO uint32_t ACCESS_CTRL18; /**< Access Control Register, offset: 0x8970 */ + __IO uint32_t ACCESS_CTRL18_ROOT_SET; /**< Access Control Register, offset: 0x8974 */ + __IO uint32_t ACCESS_CTRL18_ROOT_CLR; /**< Access Control Register, offset: 0x8978 */ + __IO uint32_t ACCESS_CTRL18_ROOT_TOG; /**< Access Control Register, offset: 0x897C */ + __IO uint32_t TARGET_ROOT19; /**< Target Register, offset: 0x8980 */ + __IO uint32_t TARGET_ROOT19_SET; /**< Target Register, offset: 0x8984 */ + __IO uint32_t TARGET_ROOT19_CLR; /**< Target Register, offset: 0x8988 */ + __IO uint32_t TARGET_ROOT19_TOG; /**< Target Register, offset: 0x898C */ + uint8_t RESERVED_40[16]; + __IO uint32_t POST19; /**< Post Divider Register, offset: 0x89A0 */ + __IO uint32_t POST_ROOT19_SET; /**< Post Divider Register, offset: 0x89A4 */ + __IO uint32_t POST_ROOT19_CLR; /**< Post Divider Register, offset: 0x89A8 */ + __IO uint32_t POST_ROOT19_TOG; /**< Post Divider Register, offset: 0x89AC */ + __IO uint32_t PRE19; /**< Pre Divider Register, offset: 0x89B0 */ + __IO uint32_t PRE_ROOT19_SET; /**< Pre Divider Register, offset: 0x89B4 */ + __IO uint32_t PRE_ROOT19_CLR; /**< Pre Divider Register, offset: 0x89B8 */ + __IO uint32_t PRE_ROOT19_TOG; /**< Pre Divider Register, offset: 0x89BC */ + uint8_t RESERVED_41[48]; + __IO uint32_t ACCESS_CTRL19; /**< Access Control Register, offset: 0x89F0 */ + __IO uint32_t ACCESS_CTRL19_ROOT_SET; /**< Access Control Register, offset: 0x89F4 */ + __IO uint32_t ACCESS_CTRL19_ROOT_CLR; /**< Access Control Register, offset: 0x89F8 */ + __IO uint32_t ACCESS_CTRL19_ROOT_TOG; /**< Access Control Register, offset: 0x89FC */ + __IO uint32_t TARGET_ROOT20; /**< Target Register, offset: 0x8A00 */ + __IO uint32_t TARGET_ROOT20_SET; /**< Target Register, offset: 0x8A04 */ + __IO uint32_t TARGET_ROOT20_CLR; /**< Target Register, offset: 0x8A08 */ + __IO uint32_t TARGET_ROOT20_TOG; /**< Target Register, offset: 0x8A0C */ + uint8_t RESERVED_42[16]; + __IO uint32_t POST20; /**< Post Divider Register, offset: 0x8A20 */ + __IO uint32_t POST_ROOT20_SET; /**< Post Divider Register, offset: 0x8A24 */ + __IO uint32_t POST_ROOT20_CLR; /**< Post Divider Register, offset: 0x8A28 */ + __IO uint32_t POST_ROOT20_TOG; /**< Post Divider Register, offset: 0x8A2C */ + __IO uint32_t PRE20; /**< Pre Divider Register, offset: 0x8A30 */ + __IO uint32_t PRE_ROOT20_SET; /**< Pre Divider Register, offset: 0x8A34 */ + __IO uint32_t PRE_ROOT20_CLR; /**< Pre Divider Register, offset: 0x8A38 */ + __IO uint32_t PRE_ROOT20_TOG; /**< Pre Divider Register, offset: 0x8A3C */ + uint8_t RESERVED_43[48]; + __IO uint32_t ACCESS_CTRL20; /**< Access Control Register, offset: 0x8A70 */ + __IO uint32_t ACCESS_CTRL20_ROOT_SET; /**< Access Control Register, offset: 0x8A74 */ + __IO uint32_t ACCESS_CTRL20_ROOT_CLR; /**< Access Control Register, offset: 0x8A78 */ + __IO uint32_t ACCESS_CTRL20_ROOT_TOG; /**< Access Control Register, offset: 0x8A7C */ + __IO uint32_t TARGET_ROOT21; /**< Target Register, offset: 0x8A80 */ + __IO uint32_t TARGET_ROOT21_SET; /**< Target Register, offset: 0x8A84 */ + __IO uint32_t TARGET_ROOT21_CLR; /**< Target Register, offset: 0x8A88 */ + __IO uint32_t TARGET_ROOT21_TOG; /**< Target Register, offset: 0x8A8C */ + uint8_t RESERVED_44[16]; + __IO uint32_t POST21; /**< Post Divider Register, offset: 0x8AA0 */ + __IO uint32_t POST_ROOT21_SET; /**< Post Divider Register, offset: 0x8AA4 */ + __IO uint32_t POST_ROOT21_CLR; /**< Post Divider Register, offset: 0x8AA8 */ + __IO uint32_t POST_ROOT21_TOG; /**< Post Divider Register, offset: 0x8AAC */ + __IO uint32_t PRE21; /**< Pre Divider Register, offset: 0x8AB0 */ + __IO uint32_t PRE_ROOT21_SET; /**< Pre Divider Register, offset: 0x8AB4 */ + __IO uint32_t PRE_ROOT21_CLR; /**< Pre Divider Register, offset: 0x8AB8 */ + __IO uint32_t PRE_ROOT21_TOG; /**< Pre Divider Register, offset: 0x8ABC */ + uint8_t RESERVED_45[48]; + __IO uint32_t ACCESS_CTRL21; /**< Access Control Register, offset: 0x8AF0 */ + __IO uint32_t ACCESS_CTRL21_ROOT_SET; /**< Access Control Register, offset: 0x8AF4 */ + __IO uint32_t ACCESS_CTRL21_ROOT_CLR; /**< Access Control Register, offset: 0x8AF8 */ + __IO uint32_t ACCESS_CTRL21_ROOT_TOG; /**< Access Control Register, offset: 0x8AFC */ + __IO uint32_t TARGET_ROOT22; /**< Target Register, offset: 0x8B00 */ + __IO uint32_t TARGET_ROOT22_SET; /**< Target Register, offset: 0x8B04 */ + __IO uint32_t TARGET_ROOT22_CLR; /**< Target Register, offset: 0x8B08 */ + __IO uint32_t TARGET_ROOT22_TOG; /**< Target Register, offset: 0x8B0C */ + uint8_t RESERVED_46[16]; + __IO uint32_t POST22; /**< Post Divider Register, offset: 0x8B20 */ + __IO uint32_t POST_ROOT22_SET; /**< Post Divider Register, offset: 0x8B24 */ + __IO uint32_t POST_ROOT22_CLR; /**< Post Divider Register, offset: 0x8B28 */ + __IO uint32_t POST_ROOT22_TOG; /**< Post Divider Register, offset: 0x8B2C */ + __IO uint32_t PRE22; /**< Pre Divider Register, offset: 0x8B30 */ + __IO uint32_t PRE_ROOT22_SET; /**< Pre Divider Register, offset: 0x8B34 */ + __IO uint32_t PRE_ROOT22_CLR; /**< Pre Divider Register, offset: 0x8B38 */ + __IO uint32_t PRE_ROOT22_TOG; /**< Pre Divider Register, offset: 0x8B3C */ + uint8_t RESERVED_47[48]; + __IO uint32_t ACCESS_CTRL22; /**< Access Control Register, offset: 0x8B70 */ + __IO uint32_t ACCESS_CTRL22_ROOT_SET; /**< Access Control Register, offset: 0x8B74 */ + __IO uint32_t ACCESS_CTRL22_ROOT_CLR; /**< Access Control Register, offset: 0x8B78 */ + __IO uint32_t ACCESS_CTRL22_ROOT_TOG; /**< Access Control Register, offset: 0x8B7C */ + __IO uint32_t TARGET_ROOT23; /**< Target Register, offset: 0x8B80 */ + __IO uint32_t TARGET_ROOT23_SET; /**< Target Register, offset: 0x8B84 */ + __IO uint32_t TARGET_ROOT23_CLR; /**< Target Register, offset: 0x8B88 */ + __IO uint32_t TARGET_ROOT23_TOG; /**< Target Register, offset: 0x8B8C */ + uint8_t RESERVED_48[16]; + __IO uint32_t POST23; /**< Post Divider Register, offset: 0x8BA0 */ + __IO uint32_t POST_ROOT23_SET; /**< Post Divider Register, offset: 0x8BA4 */ + __IO uint32_t POST_ROOT23_CLR; /**< Post Divider Register, offset: 0x8BA8 */ + __IO uint32_t POST_ROOT23_TOG; /**< Post Divider Register, offset: 0x8BAC */ + __IO uint32_t PRE23; /**< Pre Divider Register, offset: 0x8BB0 */ + __IO uint32_t PRE_ROOT23_SET; /**< Pre Divider Register, offset: 0x8BB4 */ + __IO uint32_t PRE_ROOT23_CLR; /**< Pre Divider Register, offset: 0x8BB8 */ + __IO uint32_t PRE_ROOT23_TOG; /**< Pre Divider Register, offset: 0x8BBC */ + uint8_t RESERVED_49[48]; + __IO uint32_t ACCESS_CTRL23; /**< Access Control Register, offset: 0x8BF0 */ + __IO uint32_t ACCESS_CTRL23_ROOT_SET; /**< Access Control Register, offset: 0x8BF4 */ + __IO uint32_t ACCESS_CTRL23_ROOT_CLR; /**< Access Control Register, offset: 0x8BF8 */ + __IO uint32_t ACCESS_CTRL23_ROOT_TOG; /**< Access Control Register, offset: 0x8BFC */ + __IO uint32_t TARGET_ROOT24; /**< Target Register, offset: 0x8C00 */ + __IO uint32_t TARGET_ROOT24_SET; /**< Target Register, offset: 0x8C04 */ + __IO uint32_t TARGET_ROOT24_CLR; /**< Target Register, offset: 0x8C08 */ + __IO uint32_t TARGET_ROOT24_TOG; /**< Target Register, offset: 0x8C0C */ + uint8_t RESERVED_50[16]; + __IO uint32_t POST24; /**< Post Divider Register, offset: 0x8C20 */ + __IO uint32_t POST_ROOT24_SET; /**< Post Divider Register, offset: 0x8C24 */ + __IO uint32_t POST_ROOT24_CLR; /**< Post Divider Register, offset: 0x8C28 */ + __IO uint32_t POST_ROOT24_TOG; /**< Post Divider Register, offset: 0x8C2C */ + __IO uint32_t PRE24; /**< Pre Divider Register, offset: 0x8C30 */ + __IO uint32_t PRE_ROOT24_SET; /**< Pre Divider Register, offset: 0x8C34 */ + __IO uint32_t PRE_ROOT24_CLR; /**< Pre Divider Register, offset: 0x8C38 */ + __IO uint32_t PRE_ROOT24_TOG; /**< Pre Divider Register, offset: 0x8C3C */ + uint8_t RESERVED_51[48]; + __IO uint32_t ACCESS_CTRL24; /**< Access Control Register, offset: 0x8C70 */ + __IO uint32_t ACCESS_CTRL24_ROOT_SET; /**< Access Control Register, offset: 0x8C74 */ + __IO uint32_t ACCESS_CTRL24_ROOT_CLR; /**< Access Control Register, offset: 0x8C78 */ + __IO uint32_t ACCESS_CTRL24_ROOT_TOG; /**< Access Control Register, offset: 0x8C7C */ + __IO uint32_t TARGET_ROOT25; /**< Target Register, offset: 0x8C80 */ + __IO uint32_t TARGET_ROOT25_SET; /**< Target Register, offset: 0x8C84 */ + __IO uint32_t TARGET_ROOT25_CLR; /**< Target Register, offset: 0x8C88 */ + __IO uint32_t TARGET_ROOT25_TOG; /**< Target Register, offset: 0x8C8C */ + uint8_t RESERVED_52[16]; + __IO uint32_t POST25; /**< Post Divider Register, offset: 0x8CA0 */ + __IO uint32_t POST_ROOT25_SET; /**< Post Divider Register, offset: 0x8CA4 */ + __IO uint32_t POST_ROOT25_CLR; /**< Post Divider Register, offset: 0x8CA8 */ + __IO uint32_t POST_ROOT25_TOG; /**< Post Divider Register, offset: 0x8CAC */ + __IO uint32_t PRE25; /**< Pre Divider Register, offset: 0x8CB0 */ + __IO uint32_t PRE_ROOT25_SET; /**< Pre Divider Register, offset: 0x8CB4 */ + __IO uint32_t PRE_ROOT25_CLR; /**< Pre Divider Register, offset: 0x8CB8 */ + __IO uint32_t PRE_ROOT25_TOG; /**< Pre Divider Register, offset: 0x8CBC */ + uint8_t RESERVED_53[48]; + __IO uint32_t ACCESS_CTRL25; /**< Access Control Register, offset: 0x8CF0 */ + __IO uint32_t ACCESS_CTRL25_ROOT_SET; /**< Access Control Register, offset: 0x8CF4 */ + __IO uint32_t ACCESS_CTRL25_ROOT_CLR; /**< Access Control Register, offset: 0x8CF8 */ + __IO uint32_t ACCESS_CTRL25_ROOT_TOG; /**< Access Control Register, offset: 0x8CFC */ + __IO uint32_t TARGET_ROOT26; /**< Target Register, offset: 0x8D00 */ + __IO uint32_t TARGET_ROOT26_SET; /**< Target Register, offset: 0x8D04 */ + __IO uint32_t TARGET_ROOT26_CLR; /**< Target Register, offset: 0x8D08 */ + __IO uint32_t TARGET_ROOT26_TOG; /**< Target Register, offset: 0x8D0C */ + uint8_t RESERVED_54[16]; + __IO uint32_t POST26; /**< Post Divider Register, offset: 0x8D20 */ + __IO uint32_t POST_ROOT26_SET; /**< Post Divider Register, offset: 0x8D24 */ + __IO uint32_t POST_ROOT26_CLR; /**< Post Divider Register, offset: 0x8D28 */ + __IO uint32_t POST_ROOT26_TOG; /**< Post Divider Register, offset: 0x8D2C */ + __IO uint32_t PRE26; /**< Pre Divider Register, offset: 0x8D30 */ + __IO uint32_t PRE_ROOT26_SET; /**< Pre Divider Register, offset: 0x8D34 */ + __IO uint32_t PRE_ROOT26_CLR; /**< Pre Divider Register, offset: 0x8D38 */ + __IO uint32_t PRE_ROOT26_TOG; /**< Pre Divider Register, offset: 0x8D3C */ + uint8_t RESERVED_55[48]; + __IO uint32_t ACCESS_CTRL26; /**< Access Control Register, offset: 0x8D70 */ + __IO uint32_t ACCESS_CTRL26_ROOT_SET; /**< Access Control Register, offset: 0x8D74 */ + __IO uint32_t ACCESS_CTRL26_ROOT_CLR; /**< Access Control Register, offset: 0x8D78 */ + __IO uint32_t ACCESS_CTRL26_ROOT_TOG; /**< Access Control Register, offset: 0x8D7C */ + __IO uint32_t TARGET_ROOT27; /**< Target Register, offset: 0x8D80 */ + __IO uint32_t TARGET_ROOT27_SET; /**< Target Register, offset: 0x8D84 */ + __IO uint32_t TARGET_ROOT27_CLR; /**< Target Register, offset: 0x8D88 */ + __IO uint32_t TARGET_ROOT27_TOG; /**< Target Register, offset: 0x8D8C */ + uint8_t RESERVED_56[16]; + __IO uint32_t POST27; /**< Post Divider Register, offset: 0x8DA0 */ + __IO uint32_t POST_ROOT27_SET; /**< Post Divider Register, offset: 0x8DA4 */ + __IO uint32_t POST_ROOT27_CLR; /**< Post Divider Register, offset: 0x8DA8 */ + __IO uint32_t POST_ROOT27_TOG; /**< Post Divider Register, offset: 0x8DAC */ + __IO uint32_t PRE27; /**< Pre Divider Register, offset: 0x8DB0 */ + __IO uint32_t PRE_ROOT27_SET; /**< Pre Divider Register, offset: 0x8DB4 */ + __IO uint32_t PRE_ROOT27_CLR; /**< Pre Divider Register, offset: 0x8DB8 */ + __IO uint32_t PRE_ROOT27_TOG; /**< Pre Divider Register, offset: 0x8DBC */ + uint8_t RESERVED_57[48]; + __IO uint32_t ACCESS_CTRL27; /**< Access Control Register, offset: 0x8DF0 */ + __IO uint32_t ACCESS_CTRL27_ROOT_SET; /**< Access Control Register, offset: 0x8DF4 */ + __IO uint32_t ACCESS_CTRL27_ROOT_CLR; /**< Access Control Register, offset: 0x8DF8 */ + __IO uint32_t ACCESS_CTRL27_ROOT_TOG; /**< Access Control Register, offset: 0x8DFC */ + __IO uint32_t TARGET_ROOT28; /**< Target Register, offset: 0x8E00 */ + __IO uint32_t TARGET_ROOT28_SET; /**< Target Register, offset: 0x8E04 */ + __IO uint32_t TARGET_ROOT28_CLR; /**< Target Register, offset: 0x8E08 */ + __IO uint32_t TARGET_ROOT28_TOG; /**< Target Register, offset: 0x8E0C */ + uint8_t RESERVED_58[16]; + __IO uint32_t POST28; /**< Post Divider Register, offset: 0x8E20 */ + __IO uint32_t POST_ROOT28_SET; /**< Post Divider Register, offset: 0x8E24 */ + __IO uint32_t POST_ROOT28_CLR; /**< Post Divider Register, offset: 0x8E28 */ + __IO uint32_t POST_ROOT28_TOG; /**< Post Divider Register, offset: 0x8E2C */ + __IO uint32_t PRE28; /**< Pre Divider Register, offset: 0x8E30 */ + __IO uint32_t PRE_ROOT28_SET; /**< Pre Divider Register, offset: 0x8E34 */ + __IO uint32_t PRE_ROOT28_CLR; /**< Pre Divider Register, offset: 0x8E38 */ + __IO uint32_t PRE_ROOT28_TOG; /**< Pre Divider Register, offset: 0x8E3C */ + uint8_t RESERVED_59[48]; + __IO uint32_t ACCESS_CTRL28; /**< Access Control Register, offset: 0x8E70 */ + __IO uint32_t ACCESS_CTRL28_ROOT_SET; /**< Access Control Register, offset: 0x8E74 */ + __IO uint32_t ACCESS_CTRL28_ROOT_CLR; /**< Access Control Register, offset: 0x8E78 */ + __IO uint32_t ACCESS_CTRL28_ROOT_TOG; /**< Access Control Register, offset: 0x8E7C */ + __IO uint32_t TARGET_ROOT29; /**< Target Register, offset: 0x8E80 */ + __IO uint32_t TARGET_ROOT29_SET; /**< Target Register, offset: 0x8E84 */ + __IO uint32_t TARGET_ROOT29_CLR; /**< Target Register, offset: 0x8E88 */ + __IO uint32_t TARGET_ROOT29_TOG; /**< Target Register, offset: 0x8E8C */ + uint8_t RESERVED_60[16]; + __IO uint32_t POST29; /**< Post Divider Register, offset: 0x8EA0 */ + __IO uint32_t POST_ROOT29_SET; /**< Post Divider Register, offset: 0x8EA4 */ + __IO uint32_t POST_ROOT29_CLR; /**< Post Divider Register, offset: 0x8EA8 */ + __IO uint32_t POST_ROOT29_TOG; /**< Post Divider Register, offset: 0x8EAC */ + __IO uint32_t PRE29; /**< Pre Divider Register, offset: 0x8EB0 */ + __IO uint32_t PRE_ROOT29_SET; /**< Pre Divider Register, offset: 0x8EB4 */ + __IO uint32_t PRE_ROOT29_CLR; /**< Pre Divider Register, offset: 0x8EB8 */ + __IO uint32_t PRE_ROOT29_TOG; /**< Pre Divider Register, offset: 0x8EBC */ + uint8_t RESERVED_61[48]; + __IO uint32_t ACCESS_CTRL29; /**< Access Control Register, offset: 0x8EF0 */ + __IO uint32_t ACCESS_CTRL29_ROOT_SET; /**< Access Control Register, offset: 0x8EF4 */ + __IO uint32_t ACCESS_CTRL29_ROOT_CLR; /**< Access Control Register, offset: 0x8EF8 */ + __IO uint32_t ACCESS_CTRL29_ROOT_TOG; /**< Access Control Register, offset: 0x8EFC */ + __IO uint32_t TARGET_ROOT30; /**< Target Register, offset: 0x8F00 */ + __IO uint32_t TARGET_ROOT30_SET; /**< Target Register, offset: 0x8F04 */ + __IO uint32_t TARGET_ROOT30_CLR; /**< Target Register, offset: 0x8F08 */ + __IO uint32_t TARGET_ROOT30_TOG; /**< Target Register, offset: 0x8F0C */ + uint8_t RESERVED_62[16]; + __IO uint32_t POST30; /**< Post Divider Register, offset: 0x8F20 */ + __IO uint32_t POST_ROOT30_SET; /**< Post Divider Register, offset: 0x8F24 */ + __IO uint32_t POST_ROOT30_CLR; /**< Post Divider Register, offset: 0x8F28 */ + __IO uint32_t POST_ROOT30_TOG; /**< Post Divider Register, offset: 0x8F2C */ + __IO uint32_t PRE30; /**< Pre Divider Register, offset: 0x8F30 */ + __IO uint32_t PRE_ROOT30_SET; /**< Pre Divider Register, offset: 0x8F34 */ + __IO uint32_t PRE_ROOT30_CLR; /**< Pre Divider Register, offset: 0x8F38 */ + __IO uint32_t PRE_ROOT30_TOG; /**< Pre Divider Register, offset: 0x8F3C */ + uint8_t RESERVED_63[48]; + __IO uint32_t ACCESS_CTRL30; /**< Access Control Register, offset: 0x8F70 */ + __IO uint32_t ACCESS_CTRL30_ROOT_SET; /**< Access Control Register, offset: 0x8F74 */ + __IO uint32_t ACCESS_CTRL30_ROOT_CLR; /**< Access Control Register, offset: 0x8F78 */ + __IO uint32_t ACCESS_CTRL30_ROOT_TOG; /**< Access Control Register, offset: 0x8F7C */ + __IO uint32_t TARGET_ROOT31; /**< Target Register, offset: 0x8F80 */ + __IO uint32_t TARGET_ROOT31_SET; /**< Target Register, offset: 0x8F84 */ + __IO uint32_t TARGET_ROOT31_CLR; /**< Target Register, offset: 0x8F88 */ + __IO uint32_t TARGET_ROOT31_TOG; /**< Target Register, offset: 0x8F8C */ + uint8_t RESERVED_64[16]; + __IO uint32_t POST31; /**< Post Divider Register, offset: 0x8FA0 */ + __IO uint32_t POST_ROOT31_SET; /**< Post Divider Register, offset: 0x8FA4 */ + __IO uint32_t POST_ROOT31_CLR; /**< Post Divider Register, offset: 0x8FA8 */ + __IO uint32_t POST_ROOT31_TOG; /**< Post Divider Register, offset: 0x8FAC */ + __IO uint32_t PRE31; /**< Pre Divider Register, offset: 0x8FB0 */ + __IO uint32_t PRE_ROOT31_SET; /**< Pre Divider Register, offset: 0x8FB4 */ + __IO uint32_t PRE_ROOT31_CLR; /**< Pre Divider Register, offset: 0x8FB8 */ + __IO uint32_t PRE_ROOT31_TOG; /**< Pre Divider Register, offset: 0x8FBC */ + uint8_t RESERVED_65[48]; + __IO uint32_t ACCESS_CTRL31; /**< Access Control Register, offset: 0x8FF0 */ + __IO uint32_t ACCESS_CTRL31_ROOT_SET; /**< Access Control Register, offset: 0x8FF4 */ + __IO uint32_t ACCESS_CTRL31_ROOT_CLR; /**< Access Control Register, offset: 0x8FF8 */ + __IO uint32_t ACCESS_CTRL31_ROOT_TOG; /**< Access Control Register, offset: 0x8FFC */ + __IO uint32_t TARGET_ROOT32; /**< Target Register, offset: 0x9000 */ + __IO uint32_t TARGET_ROOT32_SET; /**< Target Register, offset: 0x9004 */ + __IO uint32_t TARGET_ROOT32_CLR; /**< Target Register, offset: 0x9008 */ + __IO uint32_t TARGET_ROOT32_TOG; /**< Target Register, offset: 0x900C */ + uint8_t RESERVED_66[16]; + __IO uint32_t POST32; /**< Post Divider Register, offset: 0x9020 */ + __IO uint32_t POST_ROOT32_SET; /**< Post Divider Register, offset: 0x9024 */ + __IO uint32_t POST_ROOT32_CLR; /**< Post Divider Register, offset: 0x9028 */ + __IO uint32_t POST_ROOT32_TOG; /**< Post Divider Register, offset: 0x902C */ + __IO uint32_t PRE32; /**< Pre Divider Register, offset: 0x9030 */ + __IO uint32_t PRE_ROOT32_SET; /**< Pre Divider Register, offset: 0x9034 */ + __IO uint32_t PRE_ROOT32_CLR; /**< Pre Divider Register, offset: 0x9038 */ + __IO uint32_t PRE_ROOT32_TOG; /**< Pre Divider Register, offset: 0x903C */ + uint8_t RESERVED_67[48]; + __IO uint32_t ACCESS_CTRL32; /**< Access Control Register, offset: 0x9070 */ + __IO uint32_t ACCESS_CTRL32_ROOT_SET; /**< Access Control Register, offset: 0x9074 */ + __IO uint32_t ACCESS_CTRL32_ROOT_CLR; /**< Access Control Register, offset: 0x9078 */ + __IO uint32_t ACCESS_CTRL32_ROOT_TOG; /**< Access Control Register, offset: 0x907C */ + __IO uint32_t TARGET_ROOT33; /**< Target Register, offset: 0x9080 */ + __IO uint32_t TARGET_ROOT33_SET; /**< Target Register, offset: 0x9084 */ + __IO uint32_t TARGET_ROOT33_CLR; /**< Target Register, offset: 0x9088 */ + __IO uint32_t TARGET_ROOT33_TOG; /**< Target Register, offset: 0x908C */ + uint8_t RESERVED_68[16]; + __IO uint32_t POST33; /**< Post Divider Register, offset: 0x90A0 */ + __IO uint32_t POST_ROOT33_SET; /**< Post Divider Register, offset: 0x90A4 */ + __IO uint32_t POST_ROOT33_CLR; /**< Post Divider Register, offset: 0x90A8 */ + __IO uint32_t POST_ROOT33_TOG; /**< Post Divider Register, offset: 0x90AC */ + __IO uint32_t PRE33; /**< Pre Divider Register, offset: 0x90B0 */ + __IO uint32_t PRE_ROOT33_SET; /**< Pre Divider Register, offset: 0x90B4 */ + __IO uint32_t PRE_ROOT33_CLR; /**< Pre Divider Register, offset: 0x90B8 */ + __IO uint32_t PRE_ROOT33_TOG; /**< Pre Divider Register, offset: 0x90BC */ + uint8_t RESERVED_69[48]; + __IO uint32_t ACCESS_CTRL33; /**< Access Control Register, offset: 0x90F0 */ + __IO uint32_t ACCESS_CTRL33_ROOT_SET; /**< Access Control Register, offset: 0x90F4 */ + __IO uint32_t ACCESS_CTRL33_ROOT_CLR; /**< Access Control Register, offset: 0x90F8 */ + __IO uint32_t ACCESS_CTRL33_ROOT_TOG; /**< Access Control Register, offset: 0x90FC */ + __IO uint32_t TARGET_ROOT34; /**< Target Register, offset: 0x9100 */ + __IO uint32_t TARGET_ROOT34_SET; /**< Target Register, offset: 0x9104 */ + __IO uint32_t TARGET_ROOT34_CLR; /**< Target Register, offset: 0x9108 */ + __IO uint32_t TARGET_ROOT34_TOG; /**< Target Register, offset: 0x910C */ + uint8_t RESERVED_70[16]; + __IO uint32_t POST34; /**< Post Divider Register, offset: 0x9120 */ + __IO uint32_t POST_ROOT34_SET; /**< Post Divider Register, offset: 0x9124 */ + __IO uint32_t POST_ROOT34_CLR; /**< Post Divider Register, offset: 0x9128 */ + __IO uint32_t POST_ROOT34_TOG; /**< Post Divider Register, offset: 0x912C */ + __IO uint32_t PRE34; /**< Pre Divider Register, offset: 0x9130 */ + __IO uint32_t PRE_ROOT34_SET; /**< Pre Divider Register, offset: 0x9134 */ + __IO uint32_t PRE_ROOT34_CLR; /**< Pre Divider Register, offset: 0x9138 */ + __IO uint32_t PRE_ROOT34_TOG; /**< Pre Divider Register, offset: 0x913C */ + uint8_t RESERVED_71[48]; + __IO uint32_t ACCESS_CTRL34; /**< Access Control Register, offset: 0x9170 */ + __IO uint32_t ACCESS_CTRL34_ROOT_SET; /**< Access Control Register, offset: 0x9174 */ + __IO uint32_t ACCESS_CTRL34_ROOT_CLR; /**< Access Control Register, offset: 0x9178 */ + __IO uint32_t ACCESS_CTRL34_ROOT_TOG; /**< Access Control Register, offset: 0x917C */ + __IO uint32_t TARGET_ROOT35; /**< Target Register, offset: 0x9180 */ + __IO uint32_t TARGET_ROOT35_SET; /**< Target Register, offset: 0x9184 */ + __IO uint32_t TARGET_ROOT35_CLR; /**< Target Register, offset: 0x9188 */ + __IO uint32_t TARGET_ROOT35_TOG; /**< Target Register, offset: 0x918C */ + uint8_t RESERVED_72[16]; + __IO uint32_t POST35; /**< Post Divider Register, offset: 0x91A0 */ + __IO uint32_t POST_ROOT35_SET; /**< Post Divider Register, offset: 0x91A4 */ + __IO uint32_t POST_ROOT35_CLR; /**< Post Divider Register, offset: 0x91A8 */ + __IO uint32_t POST_ROOT35_TOG; /**< Post Divider Register, offset: 0x91AC */ + __IO uint32_t PRE35; /**< Pre Divider Register, offset: 0x91B0 */ + __IO uint32_t PRE_ROOT35_SET; /**< Pre Divider Register, offset: 0x91B4 */ + __IO uint32_t PRE_ROOT35_CLR; /**< Pre Divider Register, offset: 0x91B8 */ + __IO uint32_t PRE_ROOT35_TOG; /**< Pre Divider Register, offset: 0x91BC */ + uint8_t RESERVED_73[48]; + __IO uint32_t ACCESS_CTRL35; /**< Access Control Register, offset: 0x91F0 */ + __IO uint32_t ACCESS_CTRL35_ROOT_SET; /**< Access Control Register, offset: 0x91F4 */ + __IO uint32_t ACCESS_CTRL35_ROOT_CLR; /**< Access Control Register, offset: 0x91F8 */ + __IO uint32_t ACCESS_CTRL35_ROOT_TOG; /**< Access Control Register, offset: 0x91FC */ + __IO uint32_t TARGET_ROOT36; /**< Target Register, offset: 0x9200 */ + __IO uint32_t TARGET_ROOT36_SET; /**< Target Register, offset: 0x9204 */ + __IO uint32_t TARGET_ROOT36_CLR; /**< Target Register, offset: 0x9208 */ + __IO uint32_t TARGET_ROOT36_TOG; /**< Target Register, offset: 0x920C */ + uint8_t RESERVED_74[16]; + __IO uint32_t POST36; /**< Post Divider Register, offset: 0x9220 */ + __IO uint32_t POST_ROOT36_SET; /**< Post Divider Register, offset: 0x9224 */ + __IO uint32_t POST_ROOT36_CLR; /**< Post Divider Register, offset: 0x9228 */ + __IO uint32_t POST_ROOT36_TOG; /**< Post Divider Register, offset: 0x922C */ + __IO uint32_t PRE36; /**< Pre Divider Register, offset: 0x9230 */ + __IO uint32_t PRE_ROOT36_SET; /**< Pre Divider Register, offset: 0x9234 */ + __IO uint32_t PRE_ROOT36_CLR; /**< Pre Divider Register, offset: 0x9238 */ + __IO uint32_t PRE_ROOT36_TOG; /**< Pre Divider Register, offset: 0x923C */ + uint8_t RESERVED_75[48]; + __IO uint32_t ACCESS_CTRL36; /**< Access Control Register, offset: 0x9270 */ + __IO uint32_t ACCESS_CTRL36_ROOT_SET; /**< Access Control Register, offset: 0x9274 */ + __IO uint32_t ACCESS_CTRL36_ROOT_CLR; /**< Access Control Register, offset: 0x9278 */ + __IO uint32_t ACCESS_CTRL36_ROOT_TOG; /**< Access Control Register, offset: 0x927C */ + __IO uint32_t TARGET_ROOT37; /**< Target Register, offset: 0x9280 */ + __IO uint32_t TARGET_ROOT37_SET; /**< Target Register, offset: 0x9284 */ + __IO uint32_t TARGET_ROOT37_CLR; /**< Target Register, offset: 0x9288 */ + __IO uint32_t TARGET_ROOT37_TOG; /**< Target Register, offset: 0x928C */ + uint8_t RESERVED_76[16]; + __IO uint32_t POST37; /**< Post Divider Register, offset: 0x92A0 */ + __IO uint32_t POST_ROOT37_SET; /**< Post Divider Register, offset: 0x92A4 */ + __IO uint32_t POST_ROOT37_CLR; /**< Post Divider Register, offset: 0x92A8 */ + __IO uint32_t POST_ROOT37_TOG; /**< Post Divider Register, offset: 0x92AC */ + __IO uint32_t PRE37; /**< Pre Divider Register, offset: 0x92B0 */ + __IO uint32_t PRE_ROOT37_SET; /**< Pre Divider Register, offset: 0x92B4 */ + __IO uint32_t PRE_ROOT37_CLR; /**< Pre Divider Register, offset: 0x92B8 */ + __IO uint32_t PRE_ROOT37_TOG; /**< Pre Divider Register, offset: 0x92BC */ + uint8_t RESERVED_77[48]; + __IO uint32_t ACCESS_CTRL37; /**< Access Control Register, offset: 0x92F0 */ + __IO uint32_t ACCESS_CTRL37_ROOT_SET; /**< Access Control Register, offset: 0x92F4 */ + __IO uint32_t ACCESS_CTRL37_ROOT_CLR; /**< Access Control Register, offset: 0x92F8 */ + __IO uint32_t ACCESS_CTRL37_ROOT_TOG; /**< Access Control Register, offset: 0x92FC */ + __IO uint32_t TARGET_ROOT38; /**< Target Register, offset: 0x9300 */ + __IO uint32_t TARGET_ROOT38_SET; /**< Target Register, offset: 0x9304 */ + __IO uint32_t TARGET_ROOT38_CLR; /**< Target Register, offset: 0x9308 */ + __IO uint32_t TARGET_ROOT38_TOG; /**< Target Register, offset: 0x930C */ + uint8_t RESERVED_78[16]; + __IO uint32_t POST38; /**< Post Divider Register, offset: 0x9320 */ + __IO uint32_t POST_ROOT38_SET; /**< Post Divider Register, offset: 0x9324 */ + __IO uint32_t POST_ROOT38_CLR; /**< Post Divider Register, offset: 0x9328 */ + __IO uint32_t POST_ROOT38_TOG; /**< Post Divider Register, offset: 0x932C */ + __IO uint32_t PRE38; /**< Pre Divider Register, offset: 0x9330 */ + __IO uint32_t PRE_ROOT38_SET; /**< Pre Divider Register, offset: 0x9334 */ + __IO uint32_t PRE_ROOT38_CLR; /**< Pre Divider Register, offset: 0x9338 */ + __IO uint32_t PRE_ROOT38_TOG; /**< Pre Divider Register, offset: 0x933C */ + uint8_t RESERVED_79[48]; + __IO uint32_t ACCESS_CTRL38; /**< Access Control Register, offset: 0x9370 */ + __IO uint32_t ACCESS_CTRL38_ROOT_SET; /**< Access Control Register, offset: 0x9374 */ + __IO uint32_t ACCESS_CTRL38_ROOT_CLR; /**< Access Control Register, offset: 0x9378 */ + __IO uint32_t ACCESS_CTRL38_ROOT_TOG; /**< Access Control Register, offset: 0x937C */ + __IO uint32_t TARGET_ROOT39; /**< Target Register, offset: 0x9380 */ + __IO uint32_t TARGET_ROOT39_SET; /**< Target Register, offset: 0x9384 */ + __IO uint32_t TARGET_ROOT39_CLR; /**< Target Register, offset: 0x9388 */ + __IO uint32_t TARGET_ROOT39_TOG; /**< Target Register, offset: 0x938C */ + uint8_t RESERVED_80[16]; + __IO uint32_t POST39; /**< Post Divider Register, offset: 0x93A0 */ + __IO uint32_t POST_ROOT39_SET; /**< Post Divider Register, offset: 0x93A4 */ + __IO uint32_t POST_ROOT39_CLR; /**< Post Divider Register, offset: 0x93A8 */ + __IO uint32_t POST_ROOT39_TOG; /**< Post Divider Register, offset: 0x93AC */ + __IO uint32_t PRE39; /**< Pre Divider Register, offset: 0x93B0 */ + __IO uint32_t PRE_ROOT39_SET; /**< Pre Divider Register, offset: 0x93B4 */ + __IO uint32_t PRE_ROOT39_CLR; /**< Pre Divider Register, offset: 0x93B8 */ + __IO uint32_t PRE_ROOT39_TOG; /**< Pre Divider Register, offset: 0x93BC */ + uint8_t RESERVED_81[48]; + __IO uint32_t ACCESS_CTRL39; /**< Access Control Register, offset: 0x93F0 */ + __IO uint32_t ACCESS_CTRL39_ROOT_SET; /**< Access Control Register, offset: 0x93F4 */ + __IO uint32_t ACCESS_CTRL39_ROOT_CLR; /**< Access Control Register, offset: 0x93F8 */ + __IO uint32_t ACCESS_CTRL39_ROOT_TOG; /**< Access Control Register, offset: 0x93FC */ + __IO uint32_t TARGET_ROOT40; /**< Target Register, offset: 0x9400 */ + __IO uint32_t TARGET_ROOT40_SET; /**< Target Register, offset: 0x9404 */ + __IO uint32_t TARGET_ROOT40_CLR; /**< Target Register, offset: 0x9408 */ + __IO uint32_t TARGET_ROOT40_TOG; /**< Target Register, offset: 0x940C */ + uint8_t RESERVED_82[16]; + __IO uint32_t POST40; /**< Post Divider Register, offset: 0x9420 */ + __IO uint32_t POST_ROOT40_SET; /**< Post Divider Register, offset: 0x9424 */ + __IO uint32_t POST_ROOT40_CLR; /**< Post Divider Register, offset: 0x9428 */ + __IO uint32_t POST_ROOT40_TOG; /**< Post Divider Register, offset: 0x942C */ + __IO uint32_t PRE40; /**< Pre Divider Register, offset: 0x9430 */ + __IO uint32_t PRE_ROOT40_SET; /**< Pre Divider Register, offset: 0x9434 */ + __IO uint32_t PRE_ROOT40_CLR; /**< Pre Divider Register, offset: 0x9438 */ + __IO uint32_t PRE_ROOT40_TOG; /**< Pre Divider Register, offset: 0x943C */ + uint8_t RESERVED_83[48]; + __IO uint32_t ACCESS_CTRL40; /**< Access Control Register, offset: 0x9470 */ + __IO uint32_t ACCESS_CTRL40_ROOT_SET; /**< Access Control Register, offset: 0x9474 */ + __IO uint32_t ACCESS_CTRL40_ROOT_CLR; /**< Access Control Register, offset: 0x9478 */ + __IO uint32_t ACCESS_CTRL40_ROOT_TOG; /**< Access Control Register, offset: 0x947C */ + __IO uint32_t TARGET_ROOT41; /**< Target Register, offset: 0x9480 */ + __IO uint32_t TARGET_ROOT41_SET; /**< Target Register, offset: 0x9484 */ + __IO uint32_t TARGET_ROOT41_CLR; /**< Target Register, offset: 0x9488 */ + __IO uint32_t TARGET_ROOT41_TOG; /**< Target Register, offset: 0x948C */ + uint8_t RESERVED_84[16]; + __IO uint32_t POST41; /**< Post Divider Register, offset: 0x94A0 */ + __IO uint32_t POST_ROOT41_SET; /**< Post Divider Register, offset: 0x94A4 */ + __IO uint32_t POST_ROOT41_CLR; /**< Post Divider Register, offset: 0x94A8 */ + __IO uint32_t POST_ROOT41_TOG; /**< Post Divider Register, offset: 0x94AC */ + __IO uint32_t PRE41; /**< Pre Divider Register, offset: 0x94B0 */ + __IO uint32_t PRE_ROOT41_SET; /**< Pre Divider Register, offset: 0x94B4 */ + __IO uint32_t PRE_ROOT41_CLR; /**< Pre Divider Register, offset: 0x94B8 */ + __IO uint32_t PRE_ROOT41_TOG; /**< Pre Divider Register, offset: 0x94BC */ + uint8_t RESERVED_85[48]; + __IO uint32_t ACCESS_CTRL41; /**< Access Control Register, offset: 0x94F0 */ + __IO uint32_t ACCESS_CTRL41_ROOT_SET; /**< Access Control Register, offset: 0x94F4 */ + __IO uint32_t ACCESS_CTRL41_ROOT_CLR; /**< Access Control Register, offset: 0x94F8 */ + __IO uint32_t ACCESS_CTRL41_ROOT_TOG; /**< Access Control Register, offset: 0x94FC */ + __IO uint32_t TARGET_ROOT42; /**< Target Register, offset: 0x9500 */ + __IO uint32_t TARGET_ROOT42_SET; /**< Target Register, offset: 0x9504 */ + __IO uint32_t TARGET_ROOT42_CLR; /**< Target Register, offset: 0x9508 */ + __IO uint32_t TARGET_ROOT42_TOG; /**< Target Register, offset: 0x950C */ + uint8_t RESERVED_86[16]; + __IO uint32_t POST42; /**< Post Divider Register, offset: 0x9520 */ + __IO uint32_t POST_ROOT42_SET; /**< Post Divider Register, offset: 0x9524 */ + __IO uint32_t POST_ROOT42_CLR; /**< Post Divider Register, offset: 0x9528 */ + __IO uint32_t POST_ROOT42_TOG; /**< Post Divider Register, offset: 0x952C */ + __IO uint32_t PRE42; /**< Pre Divider Register, offset: 0x9530 */ + __IO uint32_t PRE_ROOT42_SET; /**< Pre Divider Register, offset: 0x9534 */ + __IO uint32_t PRE_ROOT42_CLR; /**< Pre Divider Register, offset: 0x9538 */ + __IO uint32_t PRE_ROOT42_TOG; /**< Pre Divider Register, offset: 0x953C */ + uint8_t RESERVED_87[48]; + __IO uint32_t ACCESS_CTRL42; /**< Access Control Register, offset: 0x9570 */ + __IO uint32_t ACCESS_CTRL42_ROOT_SET; /**< Access Control Register, offset: 0x9574 */ + __IO uint32_t ACCESS_CTRL42_ROOT_CLR; /**< Access Control Register, offset: 0x9578 */ + __IO uint32_t ACCESS_CTRL42_ROOT_TOG; /**< Access Control Register, offset: 0x957C */ + __IO uint32_t TARGET_ROOT43; /**< Target Register, offset: 0x9580 */ + __IO uint32_t TARGET_ROOT43_SET; /**< Target Register, offset: 0x9584 */ + __IO uint32_t TARGET_ROOT43_CLR; /**< Target Register, offset: 0x9588 */ + __IO uint32_t TARGET_ROOT43_TOG; /**< Target Register, offset: 0x958C */ + uint8_t RESERVED_88[16]; + __IO uint32_t POST43; /**< Post Divider Register, offset: 0x95A0 */ + __IO uint32_t POST_ROOT43_SET; /**< Post Divider Register, offset: 0x95A4 */ + __IO uint32_t POST_ROOT43_CLR; /**< Post Divider Register, offset: 0x95A8 */ + __IO uint32_t POST_ROOT43_TOG; /**< Post Divider Register, offset: 0x95AC */ + __IO uint32_t PRE43; /**< Pre Divider Register, offset: 0x95B0 */ + __IO uint32_t PRE_ROOT43_SET; /**< Pre Divider Register, offset: 0x95B4 */ + __IO uint32_t PRE_ROOT43_CLR; /**< Pre Divider Register, offset: 0x95B8 */ + __IO uint32_t PRE_ROOT43_TOG; /**< Pre Divider Register, offset: 0x95BC */ + uint8_t RESERVED_89[48]; + __IO uint32_t ACCESS_CTRL43; /**< Access Control Register, offset: 0x95F0 */ + __IO uint32_t ACCESS_CTRL43_ROOT_SET; /**< Access Control Register, offset: 0x95F4 */ + __IO uint32_t ACCESS_CTRL43_ROOT_CLR; /**< Access Control Register, offset: 0x95F8 */ + __IO uint32_t ACCESS_CTRL43_ROOT_TOG; /**< Access Control Register, offset: 0x95FC */ + __IO uint32_t TARGET_ROOT44; /**< Target Register, offset: 0x9600 */ + __IO uint32_t TARGET_ROOT44_SET; /**< Target Register, offset: 0x9604 */ + __IO uint32_t TARGET_ROOT44_CLR; /**< Target Register, offset: 0x9608 */ + __IO uint32_t TARGET_ROOT44_TOG; /**< Target Register, offset: 0x960C */ + uint8_t RESERVED_90[16]; + __IO uint32_t POST44; /**< Post Divider Register, offset: 0x9620 */ + __IO uint32_t POST_ROOT44_SET; /**< Post Divider Register, offset: 0x9624 */ + __IO uint32_t POST_ROOT44_CLR; /**< Post Divider Register, offset: 0x9628 */ + __IO uint32_t POST_ROOT44_TOG; /**< Post Divider Register, offset: 0x962C */ + __IO uint32_t PRE44; /**< Pre Divider Register, offset: 0x9630 */ + __IO uint32_t PRE_ROOT44_SET; /**< Pre Divider Register, offset: 0x9634 */ + __IO uint32_t PRE_ROOT44_CLR; /**< Pre Divider Register, offset: 0x9638 */ + __IO uint32_t PRE_ROOT44_TOG; /**< Pre Divider Register, offset: 0x963C */ + uint8_t RESERVED_91[48]; + __IO uint32_t ACCESS_CTRL44; /**< Access Control Register, offset: 0x9670 */ + __IO uint32_t ACCESS_CTRL44_ROOT_SET; /**< Access Control Register, offset: 0x9674 */ + __IO uint32_t ACCESS_CTRL44_ROOT_CLR; /**< Access Control Register, offset: 0x9678 */ + __IO uint32_t ACCESS_CTRL44_ROOT_TOG; /**< Access Control Register, offset: 0x967C */ + __IO uint32_t TARGET_ROOT45; /**< Target Register, offset: 0x9680 */ + __IO uint32_t TARGET_ROOT45_SET; /**< Target Register, offset: 0x9684 */ + __IO uint32_t TARGET_ROOT45_CLR; /**< Target Register, offset: 0x9688 */ + __IO uint32_t TARGET_ROOT45_TOG; /**< Target Register, offset: 0x968C */ + uint8_t RESERVED_92[16]; + __IO uint32_t POST45; /**< Post Divider Register, offset: 0x96A0 */ + __IO uint32_t POST_ROOT45_SET; /**< Post Divider Register, offset: 0x96A4 */ + __IO uint32_t POST_ROOT45_CLR; /**< Post Divider Register, offset: 0x96A8 */ + __IO uint32_t POST_ROOT45_TOG; /**< Post Divider Register, offset: 0x96AC */ + __IO uint32_t PRE45; /**< Pre Divider Register, offset: 0x96B0 */ + __IO uint32_t PRE_ROOT45_SET; /**< Pre Divider Register, offset: 0x96B4 */ + __IO uint32_t PRE_ROOT45_CLR; /**< Pre Divider Register, offset: 0x96B8 */ + __IO uint32_t PRE_ROOT45_TOG; /**< Pre Divider Register, offset: 0x96BC */ + uint8_t RESERVED_93[48]; + __IO uint32_t ACCESS_CTRL45; /**< Access Control Register, offset: 0x96F0 */ + __IO uint32_t ACCESS_CTRL45_ROOT_SET; /**< Access Control Register, offset: 0x96F4 */ + __IO uint32_t ACCESS_CTRL45_ROOT_CLR; /**< Access Control Register, offset: 0x96F8 */ + __IO uint32_t ACCESS_CTRL45_ROOT_TOG; /**< Access Control Register, offset: 0x96FC */ + __IO uint32_t TARGET_ROOT46; /**< Target Register, offset: 0x9700 */ + __IO uint32_t TARGET_ROOT46_SET; /**< Target Register, offset: 0x9704 */ + __IO uint32_t TARGET_ROOT46_CLR; /**< Target Register, offset: 0x9708 */ + __IO uint32_t TARGET_ROOT46_TOG; /**< Target Register, offset: 0x970C */ + uint8_t RESERVED_94[16]; + __IO uint32_t POST46; /**< Post Divider Register, offset: 0x9720 */ + __IO uint32_t POST_ROOT46_SET; /**< Post Divider Register, offset: 0x9724 */ + __IO uint32_t POST_ROOT46_CLR; /**< Post Divider Register, offset: 0x9728 */ + __IO uint32_t POST_ROOT46_TOG; /**< Post Divider Register, offset: 0x972C */ + __IO uint32_t PRE46; /**< Pre Divider Register, offset: 0x9730 */ + __IO uint32_t PRE_ROOT46_SET; /**< Pre Divider Register, offset: 0x9734 */ + __IO uint32_t PRE_ROOT46_CLR; /**< Pre Divider Register, offset: 0x9738 */ + __IO uint32_t PRE_ROOT46_TOG; /**< Pre Divider Register, offset: 0x973C */ + uint8_t RESERVED_95[48]; + __IO uint32_t ACCESS_CTRL46; /**< Access Control Register, offset: 0x9770 */ + __IO uint32_t ACCESS_CTRL46_ROOT_SET; /**< Access Control Register, offset: 0x9774 */ + __IO uint32_t ACCESS_CTRL46_ROOT_CLR; /**< Access Control Register, offset: 0x9778 */ + __IO uint32_t ACCESS_CTRL46_ROOT_TOG; /**< Access Control Register, offset: 0x977C */ + __IO uint32_t TARGET_ROOT47; /**< Target Register, offset: 0x9780 */ + __IO uint32_t TARGET_ROOT47_SET; /**< Target Register, offset: 0x9784 */ + __IO uint32_t TARGET_ROOT47_CLR; /**< Target Register, offset: 0x9788 */ + __IO uint32_t TARGET_ROOT47_TOG; /**< Target Register, offset: 0x978C */ + uint8_t RESERVED_96[16]; + __IO uint32_t POST47; /**< Post Divider Register, offset: 0x97A0 */ + __IO uint32_t POST_ROOT47_SET; /**< Post Divider Register, offset: 0x97A4 */ + __IO uint32_t POST_ROOT47_CLR; /**< Post Divider Register, offset: 0x97A8 */ + __IO uint32_t POST_ROOT47_TOG; /**< Post Divider Register, offset: 0x97AC */ + __IO uint32_t PRE47; /**< Pre Divider Register, offset: 0x97B0 */ + __IO uint32_t PRE_ROOT47_SET; /**< Pre Divider Register, offset: 0x97B4 */ + __IO uint32_t PRE_ROOT47_CLR; /**< Pre Divider Register, offset: 0x97B8 */ + __IO uint32_t PRE_ROOT47_TOG; /**< Pre Divider Register, offset: 0x97BC */ + uint8_t RESERVED_97[48]; + __IO uint32_t ACCESS_CTRL47; /**< Access Control Register, offset: 0x97F0 */ + __IO uint32_t ACCESS_CTRL47_ROOT_SET; /**< Access Control Register, offset: 0x97F4 */ + __IO uint32_t ACCESS_CTRL47_ROOT_CLR; /**< Access Control Register, offset: 0x97F8 */ + __IO uint32_t ACCESS_CTRL47_ROOT_TOG; /**< Access Control Register, offset: 0x97FC */ + __IO uint32_t TARGET_ROOT48; /**< Target Register, offset: 0x9800 */ + __IO uint32_t TARGET_ROOT48_SET; /**< Target Register, offset: 0x9804 */ + __IO uint32_t TARGET_ROOT48_CLR; /**< Target Register, offset: 0x9808 */ + __IO uint32_t TARGET_ROOT48_TOG; /**< Target Register, offset: 0x980C */ + uint8_t RESERVED_98[16]; + __IO uint32_t POST48; /**< Post Divider Register, offset: 0x9820 */ + __IO uint32_t POST_ROOT48_SET; /**< Post Divider Register, offset: 0x9824 */ + __IO uint32_t POST_ROOT48_CLR; /**< Post Divider Register, offset: 0x9828 */ + __IO uint32_t POST_ROOT48_TOG; /**< Post Divider Register, offset: 0x982C */ + __IO uint32_t PRE48; /**< Pre Divider Register, offset: 0x9830 */ + __IO uint32_t PRE_ROOT48_SET; /**< Pre Divider Register, offset: 0x9834 */ + __IO uint32_t PRE_ROOT48_CLR; /**< Pre Divider Register, offset: 0x9838 */ + __IO uint32_t PRE_ROOT48_TOG; /**< Pre Divider Register, offset: 0x983C */ + uint8_t RESERVED_99[48]; + __IO uint32_t ACCESS_CTRL48; /**< Access Control Register, offset: 0x9870 */ + __IO uint32_t ACCESS_CTRL48_ROOT_SET; /**< Access Control Register, offset: 0x9874 */ + __IO uint32_t ACCESS_CTRL48_ROOT_CLR; /**< Access Control Register, offset: 0x9878 */ + __IO uint32_t ACCESS_CTRL48_ROOT_TOG; /**< Access Control Register, offset: 0x987C */ + __IO uint32_t TARGET_ROOT49; /**< Target Register, offset: 0x9880 */ + __IO uint32_t TARGET_ROOT49_SET; /**< Target Register, offset: 0x9884 */ + __IO uint32_t TARGET_ROOT49_CLR; /**< Target Register, offset: 0x9888 */ + __IO uint32_t TARGET_ROOT49_TOG; /**< Target Register, offset: 0x988C */ + uint8_t RESERVED_100[16]; + __IO uint32_t POST49; /**< Post Divider Register, offset: 0x98A0 */ + __IO uint32_t POST_ROOT49_SET; /**< Post Divider Register, offset: 0x98A4 */ + __IO uint32_t POST_ROOT49_CLR; /**< Post Divider Register, offset: 0x98A8 */ + __IO uint32_t POST_ROOT49_TOG; /**< Post Divider Register, offset: 0x98AC */ + __IO uint32_t PRE49; /**< Pre Divider Register, offset: 0x98B0 */ + __IO uint32_t PRE_ROOT49_SET; /**< Pre Divider Register, offset: 0x98B4 */ + __IO uint32_t PRE_ROOT49_CLR; /**< Pre Divider Register, offset: 0x98B8 */ + __IO uint32_t PRE_ROOT49_TOG; /**< Pre Divider Register, offset: 0x98BC */ + uint8_t RESERVED_101[48]; + __IO uint32_t ACCESS_CTRL49; /**< Access Control Register, offset: 0x98F0 */ + __IO uint32_t ACCESS_CTRL49_ROOT_SET; /**< Access Control Register, offset: 0x98F4 */ + __IO uint32_t ACCESS_CTRL49_ROOT_CLR; /**< Access Control Register, offset: 0x98F8 */ + __IO uint32_t ACCESS_CTRL49_ROOT_TOG; /**< Access Control Register, offset: 0x98FC */ + __IO uint32_t TARGET_ROOT50; /**< Target Register, offset: 0x9900 */ + __IO uint32_t TARGET_ROOT50_SET; /**< Target Register, offset: 0x9904 */ + __IO uint32_t TARGET_ROOT50_CLR; /**< Target Register, offset: 0x9908 */ + __IO uint32_t TARGET_ROOT50_TOG; /**< Target Register, offset: 0x990C */ + uint8_t RESERVED_102[16]; + __IO uint32_t POST50; /**< Post Divider Register, offset: 0x9920 */ + __IO uint32_t POST_ROOT50_SET; /**< Post Divider Register, offset: 0x9924 */ + __IO uint32_t POST_ROOT50_CLR; /**< Post Divider Register, offset: 0x9928 */ + __IO uint32_t POST_ROOT50_TOG; /**< Post Divider Register, offset: 0x992C */ + __IO uint32_t PRE50; /**< Pre Divider Register, offset: 0x9930 */ + __IO uint32_t PRE_ROOT50_SET; /**< Pre Divider Register, offset: 0x9934 */ + __IO uint32_t PRE_ROOT50_CLR; /**< Pre Divider Register, offset: 0x9938 */ + __IO uint32_t PRE_ROOT50_TOG; /**< Pre Divider Register, offset: 0x993C */ + uint8_t RESERVED_103[48]; + __IO uint32_t ACCESS_CTRL50; /**< Access Control Register, offset: 0x9970 */ + __IO uint32_t ACCESS_CTRL50_ROOT_SET; /**< Access Control Register, offset: 0x9974 */ + __IO uint32_t ACCESS_CTRL50_ROOT_CLR; /**< Access Control Register, offset: 0x9978 */ + __IO uint32_t ACCESS_CTRL50_ROOT_TOG; /**< Access Control Register, offset: 0x997C */ + __IO uint32_t TARGET_ROOT51; /**< Target Register, offset: 0x9980 */ + __IO uint32_t TARGET_ROOT51_SET; /**< Target Register, offset: 0x9984 */ + __IO uint32_t TARGET_ROOT51_CLR; /**< Target Register, offset: 0x9988 */ + __IO uint32_t TARGET_ROOT51_TOG; /**< Target Register, offset: 0x998C */ + uint8_t RESERVED_104[16]; + __IO uint32_t POST51; /**< Post Divider Register, offset: 0x99A0 */ + __IO uint32_t POST_ROOT51_SET; /**< Post Divider Register, offset: 0x99A4 */ + __IO uint32_t POST_ROOT51_CLR; /**< Post Divider Register, offset: 0x99A8 */ + __IO uint32_t POST_ROOT51_TOG; /**< Post Divider Register, offset: 0x99AC */ + __IO uint32_t PRE51; /**< Pre Divider Register, offset: 0x99B0 */ + __IO uint32_t PRE_ROOT51_SET; /**< Pre Divider Register, offset: 0x99B4 */ + __IO uint32_t PRE_ROOT51_CLR; /**< Pre Divider Register, offset: 0x99B8 */ + __IO uint32_t PRE_ROOT51_TOG; /**< Pre Divider Register, offset: 0x99BC */ + uint8_t RESERVED_105[48]; + __IO uint32_t ACCESS_CTRL51; /**< Access Control Register, offset: 0x99F0 */ + __IO uint32_t ACCESS_CTRL51_ROOT_SET; /**< Access Control Register, offset: 0x99F4 */ + __IO uint32_t ACCESS_CTRL51_ROOT_CLR; /**< Access Control Register, offset: 0x99F8 */ + __IO uint32_t ACCESS_CTRL51_ROOT_TOG; /**< Access Control Register, offset: 0x99FC */ + __IO uint32_t TARGET_ROOT52; /**< Target Register, offset: 0x9A00 */ + __IO uint32_t TARGET_ROOT52_SET; /**< Target Register, offset: 0x9A04 */ + __IO uint32_t TARGET_ROOT52_CLR; /**< Target Register, offset: 0x9A08 */ + __IO uint32_t TARGET_ROOT52_TOG; /**< Target Register, offset: 0x9A0C */ + uint8_t RESERVED_106[16]; + __IO uint32_t POST52; /**< Post Divider Register, offset: 0x9A20 */ + __IO uint32_t POST_ROOT52_SET; /**< Post Divider Register, offset: 0x9A24 */ + __IO uint32_t POST_ROOT52_CLR; /**< Post Divider Register, offset: 0x9A28 */ + __IO uint32_t POST_ROOT52_TOG; /**< Post Divider Register, offset: 0x9A2C */ + __IO uint32_t PRE52; /**< Pre Divider Register, offset: 0x9A30 */ + __IO uint32_t PRE_ROOT52_SET; /**< Pre Divider Register, offset: 0x9A34 */ + __IO uint32_t PRE_ROOT52_CLR; /**< Pre Divider Register, offset: 0x9A38 */ + __IO uint32_t PRE_ROOT52_TOG; /**< Pre Divider Register, offset: 0x9A3C */ + uint8_t RESERVED_107[48]; + __IO uint32_t ACCESS_CTRL52; /**< Access Control Register, offset: 0x9A70 */ + __IO uint32_t ACCESS_CTRL52_ROOT_SET; /**< Access Control Register, offset: 0x9A74 */ + __IO uint32_t ACCESS_CTRL52_ROOT_CLR; /**< Access Control Register, offset: 0x9A78 */ + __IO uint32_t ACCESS_CTRL52_ROOT_TOG; /**< Access Control Register, offset: 0x9A7C */ + __IO uint32_t TARGET_ROOT53; /**< Target Register, offset: 0x9A80 */ + __IO uint32_t TARGET_ROOT53_SET; /**< Target Register, offset: 0x9A84 */ + __IO uint32_t TARGET_ROOT53_CLR; /**< Target Register, offset: 0x9A88 */ + __IO uint32_t TARGET_ROOT53_TOG; /**< Target Register, offset: 0x9A8C */ + uint8_t RESERVED_108[16]; + __IO uint32_t POST53; /**< Post Divider Register, offset: 0x9AA0 */ + __IO uint32_t POST_ROOT53_SET; /**< Post Divider Register, offset: 0x9AA4 */ + __IO uint32_t POST_ROOT53_CLR; /**< Post Divider Register, offset: 0x9AA8 */ + __IO uint32_t POST_ROOT53_TOG; /**< Post Divider Register, offset: 0x9AAC */ + __IO uint32_t PRE53; /**< Pre Divider Register, offset: 0x9AB0 */ + __IO uint32_t PRE_ROOT53_SET; /**< Pre Divider Register, offset: 0x9AB4 */ + __IO uint32_t PRE_ROOT53_CLR; /**< Pre Divider Register, offset: 0x9AB8 */ + __IO uint32_t PRE_ROOT53_TOG; /**< Pre Divider Register, offset: 0x9ABC */ + uint8_t RESERVED_109[48]; + __IO uint32_t ACCESS_CTRL53; /**< Access Control Register, offset: 0x9AF0 */ + __IO uint32_t ACCESS_CTRL53_ROOT_SET; /**< Access Control Register, offset: 0x9AF4 */ + __IO uint32_t ACCESS_CTRL53_ROOT_CLR; /**< Access Control Register, offset: 0x9AF8 */ + __IO uint32_t ACCESS_CTRL53_ROOT_TOG; /**< Access Control Register, offset: 0x9AFC */ + __IO uint32_t TARGET_ROOT54; /**< Target Register, offset: 0x9B00 */ + __IO uint32_t TARGET_ROOT54_SET; /**< Target Register, offset: 0x9B04 */ + __IO uint32_t TARGET_ROOT54_CLR; /**< Target Register, offset: 0x9B08 */ + __IO uint32_t TARGET_ROOT54_TOG; /**< Target Register, offset: 0x9B0C */ + uint8_t RESERVED_110[16]; + __IO uint32_t POST54; /**< Post Divider Register, offset: 0x9B20 */ + __IO uint32_t POST_ROOT54_SET; /**< Post Divider Register, offset: 0x9B24 */ + __IO uint32_t POST_ROOT54_CLR; /**< Post Divider Register, offset: 0x9B28 */ + __IO uint32_t POST_ROOT54_TOG; /**< Post Divider Register, offset: 0x9B2C */ + __IO uint32_t PRE54; /**< Pre Divider Register, offset: 0x9B30 */ + __IO uint32_t PRE_ROOT54_SET; /**< Pre Divider Register, offset: 0x9B34 */ + __IO uint32_t PRE_ROOT54_CLR; /**< Pre Divider Register, offset: 0x9B38 */ + __IO uint32_t PRE_ROOT54_TOG; /**< Pre Divider Register, offset: 0x9B3C */ + uint8_t RESERVED_111[48]; + __IO uint32_t ACCESS_CTRL54; /**< Access Control Register, offset: 0x9B70 */ + __IO uint32_t ACCESS_CTRL54_ROOT_SET; /**< Access Control Register, offset: 0x9B74 */ + __IO uint32_t ACCESS_CTRL54_ROOT_CLR; /**< Access Control Register, offset: 0x9B78 */ + __IO uint32_t ACCESS_CTRL54_ROOT_TOG; /**< Access Control Register, offset: 0x9B7C */ + __IO uint32_t TARGET_ROOT55; /**< Target Register, offset: 0x9B80 */ + __IO uint32_t TARGET_ROOT55_SET; /**< Target Register, offset: 0x9B84 */ + __IO uint32_t TARGET_ROOT55_CLR; /**< Target Register, offset: 0x9B88 */ + __IO uint32_t TARGET_ROOT55_TOG; /**< Target Register, offset: 0x9B8C */ + uint8_t RESERVED_112[16]; + __IO uint32_t POST55; /**< Post Divider Register, offset: 0x9BA0 */ + __IO uint32_t POST_ROOT55_SET; /**< Post Divider Register, offset: 0x9BA4 */ + __IO uint32_t POST_ROOT55_CLR; /**< Post Divider Register, offset: 0x9BA8 */ + __IO uint32_t POST_ROOT55_TOG; /**< Post Divider Register, offset: 0x9BAC */ + __IO uint32_t PRE55; /**< Pre Divider Register, offset: 0x9BB0 */ + __IO uint32_t PRE_ROOT55_SET; /**< Pre Divider Register, offset: 0x9BB4 */ + __IO uint32_t PRE_ROOT55_CLR; /**< Pre Divider Register, offset: 0x9BB8 */ + __IO uint32_t PRE_ROOT55_TOG; /**< Pre Divider Register, offset: 0x9BBC */ + uint8_t RESERVED_113[48]; + __IO uint32_t ACCESS_CTRL55; /**< Access Control Register, offset: 0x9BF0 */ + __IO uint32_t ACCESS_CTRL55_ROOT_SET; /**< Access Control Register, offset: 0x9BF4 */ + __IO uint32_t ACCESS_CTRL55_ROOT_CLR; /**< Access Control Register, offset: 0x9BF8 */ + __IO uint32_t ACCESS_CTRL55_ROOT_TOG; /**< Access Control Register, offset: 0x9BFC */ + __IO uint32_t TARGET_ROOT56; /**< Target Register, offset: 0x9C00 */ + __IO uint32_t TARGET_ROOT56_SET; /**< Target Register, offset: 0x9C04 */ + __IO uint32_t TARGET_ROOT56_CLR; /**< Target Register, offset: 0x9C08 */ + __IO uint32_t TARGET_ROOT56_TOG; /**< Target Register, offset: 0x9C0C */ + uint8_t RESERVED_114[16]; + __IO uint32_t POST56; /**< Post Divider Register, offset: 0x9C20 */ + __IO uint32_t POST_ROOT56_SET; /**< Post Divider Register, offset: 0x9C24 */ + __IO uint32_t POST_ROOT56_CLR; /**< Post Divider Register, offset: 0x9C28 */ + __IO uint32_t POST_ROOT56_TOG; /**< Post Divider Register, offset: 0x9C2C */ + __IO uint32_t PRE56; /**< Pre Divider Register, offset: 0x9C30 */ + __IO uint32_t PRE_ROOT56_SET; /**< Pre Divider Register, offset: 0x9C34 */ + __IO uint32_t PRE_ROOT56_CLR; /**< Pre Divider Register, offset: 0x9C38 */ + __IO uint32_t PRE_ROOT56_TOG; /**< Pre Divider Register, offset: 0x9C3C */ + uint8_t RESERVED_115[48]; + __IO uint32_t ACCESS_CTRL56; /**< Access Control Register, offset: 0x9C70 */ + __IO uint32_t ACCESS_CTRL56_ROOT_SET; /**< Access Control Register, offset: 0x9C74 */ + __IO uint32_t ACCESS_CTRL56_ROOT_CLR; /**< Access Control Register, offset: 0x9C78 */ + __IO uint32_t ACCESS_CTRL56_ROOT_TOG; /**< Access Control Register, offset: 0x9C7C */ + __IO uint32_t TARGET_ROOT57; /**< Target Register, offset: 0x9C80 */ + __IO uint32_t TARGET_ROOT57_SET; /**< Target Register, offset: 0x9C84 */ + __IO uint32_t TARGET_ROOT57_CLR; /**< Target Register, offset: 0x9C88 */ + __IO uint32_t TARGET_ROOT57_TOG; /**< Target Register, offset: 0x9C8C */ + uint8_t RESERVED_116[16]; + __IO uint32_t POST57; /**< Post Divider Register, offset: 0x9CA0 */ + __IO uint32_t POST_ROOT57_SET; /**< Post Divider Register, offset: 0x9CA4 */ + __IO uint32_t POST_ROOT57_CLR; /**< Post Divider Register, offset: 0x9CA8 */ + __IO uint32_t POST_ROOT57_TOG; /**< Post Divider Register, offset: 0x9CAC */ + __IO uint32_t PRE57; /**< Pre Divider Register, offset: 0x9CB0 */ + __IO uint32_t PRE_ROOT57_SET; /**< Pre Divider Register, offset: 0x9CB4 */ + __IO uint32_t PRE_ROOT57_CLR; /**< Pre Divider Register, offset: 0x9CB8 */ + __IO uint32_t PRE_ROOT57_TOG; /**< Pre Divider Register, offset: 0x9CBC */ + uint8_t RESERVED_117[48]; + __IO uint32_t ACCESS_CTRL57; /**< Access Control Register, offset: 0x9CF0 */ + __IO uint32_t ACCESS_CTRL57_ROOT_SET; /**< Access Control Register, offset: 0x9CF4 */ + __IO uint32_t ACCESS_CTRL57_ROOT_CLR; /**< Access Control Register, offset: 0x9CF8 */ + __IO uint32_t ACCESS_CTRL57_ROOT_TOG; /**< Access Control Register, offset: 0x9CFC */ + __IO uint32_t TARGET_ROOT58; /**< Target Register, offset: 0x9D00 */ + __IO uint32_t TARGET_ROOT58_SET; /**< Target Register, offset: 0x9D04 */ + __IO uint32_t TARGET_ROOT58_CLR; /**< Target Register, offset: 0x9D08 */ + __IO uint32_t TARGET_ROOT58_TOG; /**< Target Register, offset: 0x9D0C */ + uint8_t RESERVED_118[16]; + __IO uint32_t POST58; /**< Post Divider Register, offset: 0x9D20 */ + __IO uint32_t POST_ROOT58_SET; /**< Post Divider Register, offset: 0x9D24 */ + __IO uint32_t POST_ROOT58_CLR; /**< Post Divider Register, offset: 0x9D28 */ + __IO uint32_t POST_ROOT58_TOG; /**< Post Divider Register, offset: 0x9D2C */ + __IO uint32_t PRE58; /**< Pre Divider Register, offset: 0x9D30 */ + __IO uint32_t PRE_ROOT58_SET; /**< Pre Divider Register, offset: 0x9D34 */ + __IO uint32_t PRE_ROOT58_CLR; /**< Pre Divider Register, offset: 0x9D38 */ + __IO uint32_t PRE_ROOT58_TOG; /**< Pre Divider Register, offset: 0x9D3C */ + uint8_t RESERVED_119[48]; + __IO uint32_t ACCESS_CTRL58; /**< Access Control Register, offset: 0x9D70 */ + __IO uint32_t ACCESS_CTRL58_ROOT_SET; /**< Access Control Register, offset: 0x9D74 */ + __IO uint32_t ACCESS_CTRL58_ROOT_CLR; /**< Access Control Register, offset: 0x9D78 */ + __IO uint32_t ACCESS_CTRL58_ROOT_TOG; /**< Access Control Register, offset: 0x9D7C */ + __IO uint32_t TARGET_ROOT59; /**< Target Register, offset: 0x9D80 */ + __IO uint32_t TARGET_ROOT59_SET; /**< Target Register, offset: 0x9D84 */ + __IO uint32_t TARGET_ROOT59_CLR; /**< Target Register, offset: 0x9D88 */ + __IO uint32_t TARGET_ROOT59_TOG; /**< Target Register, offset: 0x9D8C */ + uint8_t RESERVED_120[16]; + __IO uint32_t POST59; /**< Post Divider Register, offset: 0x9DA0 */ + __IO uint32_t POST_ROOT59_SET; /**< Post Divider Register, offset: 0x9DA4 */ + __IO uint32_t POST_ROOT59_CLR; /**< Post Divider Register, offset: 0x9DA8 */ + __IO uint32_t POST_ROOT59_TOG; /**< Post Divider Register, offset: 0x9DAC */ + __IO uint32_t PRE59; /**< Pre Divider Register, offset: 0x9DB0 */ + __IO uint32_t PRE_ROOT59_SET; /**< Pre Divider Register, offset: 0x9DB4 */ + __IO uint32_t PRE_ROOT59_CLR; /**< Pre Divider Register, offset: 0x9DB8 */ + __IO uint32_t PRE_ROOT59_TOG; /**< Pre Divider Register, offset: 0x9DBC */ + uint8_t RESERVED_121[48]; + __IO uint32_t ACCESS_CTRL59; /**< Access Control Register, offset: 0x9DF0 */ + __IO uint32_t ACCESS_CTRL59_ROOT_SET; /**< Access Control Register, offset: 0x9DF4 */ + __IO uint32_t ACCESS_CTRL59_ROOT_CLR; /**< Access Control Register, offset: 0x9DF8 */ + __IO uint32_t ACCESS_CTRL59_ROOT_TOG; /**< Access Control Register, offset: 0x9DFC */ + __IO uint32_t TARGET_ROOT60; /**< Target Register, offset: 0x9E00 */ + __IO uint32_t TARGET_ROOT60_SET; /**< Target Register, offset: 0x9E04 */ + __IO uint32_t TARGET_ROOT60_CLR; /**< Target Register, offset: 0x9E08 */ + __IO uint32_t TARGET_ROOT60_TOG; /**< Target Register, offset: 0x9E0C */ + uint8_t RESERVED_122[16]; + __IO uint32_t POST60; /**< Post Divider Register, offset: 0x9E20 */ + __IO uint32_t POST_ROOT60_SET; /**< Post Divider Register, offset: 0x9E24 */ + __IO uint32_t POST_ROOT60_CLR; /**< Post Divider Register, offset: 0x9E28 */ + __IO uint32_t POST_ROOT60_TOG; /**< Post Divider Register, offset: 0x9E2C */ + __IO uint32_t PRE60; /**< Pre Divider Register, offset: 0x9E30 */ + __IO uint32_t PRE_ROOT60_SET; /**< Pre Divider Register, offset: 0x9E34 */ + __IO uint32_t PRE_ROOT60_CLR; /**< Pre Divider Register, offset: 0x9E38 */ + __IO uint32_t PRE_ROOT60_TOG; /**< Pre Divider Register, offset: 0x9E3C */ + uint8_t RESERVED_123[48]; + __IO uint32_t ACCESS_CTRL60; /**< Access Control Register, offset: 0x9E70 */ + __IO uint32_t ACCESS_CTRL60_ROOT_SET; /**< Access Control Register, offset: 0x9E74 */ + __IO uint32_t ACCESS_CTRL60_ROOT_CLR; /**< Access Control Register, offset: 0x9E78 */ + __IO uint32_t ACCESS_CTRL60_ROOT_TOG; /**< Access Control Register, offset: 0x9E7C */ + __IO uint32_t TARGET_ROOT61; /**< Target Register, offset: 0x9E80 */ + __IO uint32_t TARGET_ROOT61_SET; /**< Target Register, offset: 0x9E84 */ + __IO uint32_t TARGET_ROOT61_CLR; /**< Target Register, offset: 0x9E88 */ + __IO uint32_t TARGET_ROOT61_TOG; /**< Target Register, offset: 0x9E8C */ + uint8_t RESERVED_124[16]; + __IO uint32_t POST61; /**< Post Divider Register, offset: 0x9EA0 */ + __IO uint32_t POST_ROOT61_SET; /**< Post Divider Register, offset: 0x9EA4 */ + __IO uint32_t POST_ROOT61_CLR; /**< Post Divider Register, offset: 0x9EA8 */ + __IO uint32_t POST_ROOT61_TOG; /**< Post Divider Register, offset: 0x9EAC */ + __IO uint32_t PRE61; /**< Pre Divider Register, offset: 0x9EB0 */ + __IO uint32_t PRE_ROOT61_SET; /**< Pre Divider Register, offset: 0x9EB4 */ + __IO uint32_t PRE_ROOT61_CLR; /**< Pre Divider Register, offset: 0x9EB8 */ + __IO uint32_t PRE_ROOT61_TOG; /**< Pre Divider Register, offset: 0x9EBC */ + uint8_t RESERVED_125[48]; + __IO uint32_t ACCESS_CTRL61; /**< Access Control Register, offset: 0x9EF0 */ + __IO uint32_t ACCESS_CTRL61_ROOT_SET; /**< Access Control Register, offset: 0x9EF4 */ + __IO uint32_t ACCESS_CTRL61_ROOT_CLR; /**< Access Control Register, offset: 0x9EF8 */ + __IO uint32_t ACCESS_CTRL61_ROOT_TOG; /**< Access Control Register, offset: 0x9EFC */ + __IO uint32_t TARGET_ROOT62; /**< Target Register, offset: 0x9F00 */ + __IO uint32_t TARGET_ROOT62_SET; /**< Target Register, offset: 0x9F04 */ + __IO uint32_t TARGET_ROOT62_CLR; /**< Target Register, offset: 0x9F08 */ + __IO uint32_t TARGET_ROOT62_TOG; /**< Target Register, offset: 0x9F0C */ + uint8_t RESERVED_126[16]; + __IO uint32_t POST62; /**< Post Divider Register, offset: 0x9F20 */ + __IO uint32_t POST_ROOT62_SET; /**< Post Divider Register, offset: 0x9F24 */ + __IO uint32_t POST_ROOT62_CLR; /**< Post Divider Register, offset: 0x9F28 */ + __IO uint32_t POST_ROOT62_TOG; /**< Post Divider Register, offset: 0x9F2C */ + __IO uint32_t PRE62; /**< Pre Divider Register, offset: 0x9F30 */ + __IO uint32_t PRE_ROOT62_SET; /**< Pre Divider Register, offset: 0x9F34 */ + __IO uint32_t PRE_ROOT62_CLR; /**< Pre Divider Register, offset: 0x9F38 */ + __IO uint32_t PRE_ROOT62_TOG; /**< Pre Divider Register, offset: 0x9F3C */ + uint8_t RESERVED_127[48]; + __IO uint32_t ACCESS_CTRL62; /**< Access Control Register, offset: 0x9F70 */ + __IO uint32_t ACCESS_CTRL62_ROOT_SET; /**< Access Control Register, offset: 0x9F74 */ + __IO uint32_t ACCESS_CTRL62_ROOT_CLR; /**< Access Control Register, offset: 0x9F78 */ + __IO uint32_t ACCESS_CTRL62_ROOT_TOG; /**< Access Control Register, offset: 0x9F7C */ + __IO uint32_t TARGET_ROOT63; /**< Target Register, offset: 0x9F80 */ + __IO uint32_t TARGET_ROOT63_SET; /**< Target Register, offset: 0x9F84 */ + __IO uint32_t TARGET_ROOT63_CLR; /**< Target Register, offset: 0x9F88 */ + __IO uint32_t TARGET_ROOT63_TOG; /**< Target Register, offset: 0x9F8C */ + uint8_t RESERVED_128[16]; + __IO uint32_t POST63; /**< Post Divider Register, offset: 0x9FA0 */ + __IO uint32_t POST_ROOT63_SET; /**< Post Divider Register, offset: 0x9FA4 */ + __IO uint32_t POST_ROOT63_CLR; /**< Post Divider Register, offset: 0x9FA8 */ + __IO uint32_t POST_ROOT63_TOG; /**< Post Divider Register, offset: 0x9FAC */ + __IO uint32_t PRE63; /**< Pre Divider Register, offset: 0x9FB0 */ + __IO uint32_t PRE_ROOT63_SET; /**< Pre Divider Register, offset: 0x9FB4 */ + __IO uint32_t PRE_ROOT63_CLR; /**< Pre Divider Register, offset: 0x9FB8 */ + __IO uint32_t PRE_ROOT63_TOG; /**< Pre Divider Register, offset: 0x9FBC */ + uint8_t RESERVED_129[48]; + __IO uint32_t ACCESS_CTRL63; /**< Access Control Register, offset: 0x9FF0 */ + __IO uint32_t ACCESS_CTRL63_ROOT_SET; /**< Access Control Register, offset: 0x9FF4 */ + __IO uint32_t ACCESS_CTRL63_ROOT_CLR; /**< Access Control Register, offset: 0x9FF8 */ + __IO uint32_t ACCESS_CTRL63_ROOT_TOG; /**< Access Control Register, offset: 0x9FFC */ + __IO uint32_t TARGET_ROOT64; /**< Target Register, offset: 0xA000 */ + __IO uint32_t TARGET_ROOT64_SET; /**< Target Register, offset: 0xA004 */ + __IO uint32_t TARGET_ROOT64_CLR; /**< Target Register, offset: 0xA008 */ + __IO uint32_t TARGET_ROOT64_TOG; /**< Target Register, offset: 0xA00C */ + uint8_t RESERVED_130[16]; + __IO uint32_t POST64; /**< Post Divider Register, offset: 0xA020 */ + __IO uint32_t POST_ROOT64_SET; /**< Post Divider Register, offset: 0xA024 */ + __IO uint32_t POST_ROOT64_CLR; /**< Post Divider Register, offset: 0xA028 */ + __IO uint32_t POST_ROOT64_TOG; /**< Post Divider Register, offset: 0xA02C */ + __IO uint32_t PRE64; /**< Pre Divider Register, offset: 0xA030 */ + __IO uint32_t PRE_ROOT64_SET; /**< Pre Divider Register, offset: 0xA034 */ + __IO uint32_t PRE_ROOT64_CLR; /**< Pre Divider Register, offset: 0xA038 */ + __IO uint32_t PRE_ROOT64_TOG; /**< Pre Divider Register, offset: 0xA03C */ + uint8_t RESERVED_131[48]; + __IO uint32_t ACCESS_CTRL64; /**< Access Control Register, offset: 0xA070 */ + __IO uint32_t ACCESS_CTRL64_ROOT_SET; /**< Access Control Register, offset: 0xA074 */ + __IO uint32_t ACCESS_CTRL64_ROOT_CLR; /**< Access Control Register, offset: 0xA078 */ + __IO uint32_t ACCESS_CTRL64_ROOT_TOG; /**< Access Control Register, offset: 0xA07C */ + __IO uint32_t TARGET_ROOT65; /**< Target Register, offset: 0xA080 */ + __IO uint32_t TARGET_ROOT65_SET; /**< Target Register, offset: 0xA084 */ + __IO uint32_t TARGET_ROOT65_CLR; /**< Target Register, offset: 0xA088 */ + __IO uint32_t TARGET_ROOT65_TOG; /**< Target Register, offset: 0xA08C */ + uint8_t RESERVED_132[16]; + __IO uint32_t POST65; /**< Post Divider Register, offset: 0xA0A0 */ + __IO uint32_t POST_ROOT65_SET; /**< Post Divider Register, offset: 0xA0A4 */ + __IO uint32_t POST_ROOT65_CLR; /**< Post Divider Register, offset: 0xA0A8 */ + __IO uint32_t POST_ROOT65_TOG; /**< Post Divider Register, offset: 0xA0AC */ + __IO uint32_t PRE65; /**< Pre Divider Register, offset: 0xA0B0 */ + __IO uint32_t PRE_ROOT65_SET; /**< Pre Divider Register, offset: 0xA0B4 */ + __IO uint32_t PRE_ROOT65_CLR; /**< Pre Divider Register, offset: 0xA0B8 */ + __IO uint32_t PRE_ROOT65_TOG; /**< Pre Divider Register, offset: 0xA0BC */ + uint8_t RESERVED_133[48]; + __IO uint32_t ACCESS_CTRL65; /**< Access Control Register, offset: 0xA0F0 */ + __IO uint32_t ACCESS_CTRL65_ROOT_SET; /**< Access Control Register, offset: 0xA0F4 */ + __IO uint32_t ACCESS_CTRL65_ROOT_CLR; /**< Access Control Register, offset: 0xA0F8 */ + __IO uint32_t ACCESS_CTRL65_ROOT_TOG; /**< Access Control Register, offset: 0xA0FC */ + __IO uint32_t TARGET_ROOT66; /**< Target Register, offset: 0xA100 */ + __IO uint32_t TARGET_ROOT66_SET; /**< Target Register, offset: 0xA104 */ + __IO uint32_t TARGET_ROOT66_CLR; /**< Target Register, offset: 0xA108 */ + __IO uint32_t TARGET_ROOT66_TOG; /**< Target Register, offset: 0xA10C */ + uint8_t RESERVED_134[16]; + __IO uint32_t POST66; /**< Post Divider Register, offset: 0xA120 */ + __IO uint32_t POST_ROOT66_SET; /**< Post Divider Register, offset: 0xA124 */ + __IO uint32_t POST_ROOT66_CLR; /**< Post Divider Register, offset: 0xA128 */ + __IO uint32_t POST_ROOT66_TOG; /**< Post Divider Register, offset: 0xA12C */ + __IO uint32_t PRE66; /**< Pre Divider Register, offset: 0xA130 */ + __IO uint32_t PRE_ROOT66_SET; /**< Pre Divider Register, offset: 0xA134 */ + __IO uint32_t PRE_ROOT66_CLR; /**< Pre Divider Register, offset: 0xA138 */ + __IO uint32_t PRE_ROOT66_TOG; /**< Pre Divider Register, offset: 0xA13C */ + uint8_t RESERVED_135[48]; + __IO uint32_t ACCESS_CTRL66; /**< Access Control Register, offset: 0xA170 */ + __IO uint32_t ACCESS_CTRL66_ROOT_SET; /**< Access Control Register, offset: 0xA174 */ + __IO uint32_t ACCESS_CTRL66_ROOT_CLR; /**< Access Control Register, offset: 0xA178 */ + __IO uint32_t ACCESS_CTRL66_ROOT_TOG; /**< Access Control Register, offset: 0xA17C */ + __IO uint32_t TARGET_ROOT67; /**< Target Register, offset: 0xA180 */ + __IO uint32_t TARGET_ROOT67_SET; /**< Target Register, offset: 0xA184 */ + __IO uint32_t TARGET_ROOT67_CLR; /**< Target Register, offset: 0xA188 */ + __IO uint32_t TARGET_ROOT67_TOG; /**< Target Register, offset: 0xA18C */ + uint8_t RESERVED_136[16]; + __IO uint32_t POST67; /**< Post Divider Register, offset: 0xA1A0 */ + __IO uint32_t POST_ROOT67_SET; /**< Post Divider Register, offset: 0xA1A4 */ + __IO uint32_t POST_ROOT67_CLR; /**< Post Divider Register, offset: 0xA1A8 */ + __IO uint32_t POST_ROOT67_TOG; /**< Post Divider Register, offset: 0xA1AC */ + __IO uint32_t PRE67; /**< Pre Divider Register, offset: 0xA1B0 */ + __IO uint32_t PRE_ROOT67_SET; /**< Pre Divider Register, offset: 0xA1B4 */ + __IO uint32_t PRE_ROOT67_CLR; /**< Pre Divider Register, offset: 0xA1B8 */ + __IO uint32_t PRE_ROOT67_TOG; /**< Pre Divider Register, offset: 0xA1BC */ + uint8_t RESERVED_137[48]; + __IO uint32_t ACCESS_CTRL67; /**< Access Control Register, offset: 0xA1F0 */ + __IO uint32_t ACCESS_CTRL67_ROOT_SET; /**< Access Control Register, offset: 0xA1F4 */ + __IO uint32_t ACCESS_CTRL67_ROOT_CLR; /**< Access Control Register, offset: 0xA1F8 */ + __IO uint32_t ACCESS_CTRL67_ROOT_TOG; /**< Access Control Register, offset: 0xA1FC */ + __IO uint32_t TARGET_ROOT68; /**< Target Register, offset: 0xA200 */ + __IO uint32_t TARGET_ROOT68_SET; /**< Target Register, offset: 0xA204 */ + __IO uint32_t TARGET_ROOT68_CLR; /**< Target Register, offset: 0xA208 */ + __IO uint32_t TARGET_ROOT68_TOG; /**< Target Register, offset: 0xA20C */ + uint8_t RESERVED_138[16]; + __IO uint32_t POST68; /**< Post Divider Register, offset: 0xA220 */ + __IO uint32_t POST_ROOT68_SET; /**< Post Divider Register, offset: 0xA224 */ + __IO uint32_t POST_ROOT68_CLR; /**< Post Divider Register, offset: 0xA228 */ + __IO uint32_t POST_ROOT68_TOG; /**< Post Divider Register, offset: 0xA22C */ + __IO uint32_t PRE68; /**< Pre Divider Register, offset: 0xA230 */ + __IO uint32_t PRE_ROOT68_SET; /**< Pre Divider Register, offset: 0xA234 */ + __IO uint32_t PRE_ROOT68_CLR; /**< Pre Divider Register, offset: 0xA238 */ + __IO uint32_t PRE_ROOT68_TOG; /**< Pre Divider Register, offset: 0xA23C */ + uint8_t RESERVED_139[48]; + __IO uint32_t ACCESS_CTRL68; /**< Access Control Register, offset: 0xA270 */ + __IO uint32_t ACCESS_CTRL68_ROOT_SET; /**< Access Control Register, offset: 0xA274 */ + __IO uint32_t ACCESS_CTRL68_ROOT_CLR; /**< Access Control Register, offset: 0xA278 */ + __IO uint32_t ACCESS_CTRL68_ROOT_TOG; /**< Access Control Register, offset: 0xA27C */ + __IO uint32_t TARGET_ROOT69; /**< Target Register, offset: 0xA280 */ + __IO uint32_t TARGET_ROOT69_SET; /**< Target Register, offset: 0xA284 */ + __IO uint32_t TARGET_ROOT69_CLR; /**< Target Register, offset: 0xA288 */ + __IO uint32_t TARGET_ROOT69_TOG; /**< Target Register, offset: 0xA28C */ + uint8_t RESERVED_140[16]; + __IO uint32_t POST69; /**< Post Divider Register, offset: 0xA2A0 */ + __IO uint32_t POST_ROOT69_SET; /**< Post Divider Register, offset: 0xA2A4 */ + __IO uint32_t POST_ROOT69_CLR; /**< Post Divider Register, offset: 0xA2A8 */ + __IO uint32_t POST_ROOT69_TOG; /**< Post Divider Register, offset: 0xA2AC */ + __IO uint32_t PRE69; /**< Pre Divider Register, offset: 0xA2B0 */ + __IO uint32_t PRE_ROOT69_SET; /**< Pre Divider Register, offset: 0xA2B4 */ + __IO uint32_t PRE_ROOT69_CLR; /**< Pre Divider Register, offset: 0xA2B8 */ + __IO uint32_t PRE_ROOT69_TOG; /**< Pre Divider Register, offset: 0xA2BC */ + uint8_t RESERVED_141[48]; + __IO uint32_t ACCESS_CTRL69; /**< Access Control Register, offset: 0xA2F0 */ + __IO uint32_t ACCESS_CTRL69_ROOT_SET; /**< Access Control Register, offset: 0xA2F4 */ + __IO uint32_t ACCESS_CTRL69_ROOT_CLR; /**< Access Control Register, offset: 0xA2F8 */ + __IO uint32_t ACCESS_CTRL69_ROOT_TOG; /**< Access Control Register, offset: 0xA2FC */ + __IO uint32_t TARGET_ROOT70; /**< Target Register, offset: 0xA300 */ + __IO uint32_t TARGET_ROOT70_SET; /**< Target Register, offset: 0xA304 */ + __IO uint32_t TARGET_ROOT70_CLR; /**< Target Register, offset: 0xA308 */ + __IO uint32_t TARGET_ROOT70_TOG; /**< Target Register, offset: 0xA30C */ + uint8_t RESERVED_142[16]; + __IO uint32_t POST70; /**< Post Divider Register, offset: 0xA320 */ + __IO uint32_t POST_ROOT70_SET; /**< Post Divider Register, offset: 0xA324 */ + __IO uint32_t POST_ROOT70_CLR; /**< Post Divider Register, offset: 0xA328 */ + __IO uint32_t POST_ROOT70_TOG; /**< Post Divider Register, offset: 0xA32C */ + __IO uint32_t PRE70; /**< Pre Divider Register, offset: 0xA330 */ + __IO uint32_t PRE_ROOT70_SET; /**< Pre Divider Register, offset: 0xA334 */ + __IO uint32_t PRE_ROOT70_CLR; /**< Pre Divider Register, offset: 0xA338 */ + __IO uint32_t PRE_ROOT70_TOG; /**< Pre Divider Register, offset: 0xA33C */ + uint8_t RESERVED_143[48]; + __IO uint32_t ACCESS_CTRL70; /**< Access Control Register, offset: 0xA370 */ + __IO uint32_t ACCESS_CTRL70_ROOT_SET; /**< Access Control Register, offset: 0xA374 */ + __IO uint32_t ACCESS_CTRL70_ROOT_CLR; /**< Access Control Register, offset: 0xA378 */ + __IO uint32_t ACCESS_CTRL70_ROOT_TOG; /**< Access Control Register, offset: 0xA37C */ + __IO uint32_t TARGET_ROOT71; /**< Target Register, offset: 0xA380 */ + __IO uint32_t TARGET_ROOT71_SET; /**< Target Register, offset: 0xA384 */ + __IO uint32_t TARGET_ROOT71_CLR; /**< Target Register, offset: 0xA388 */ + __IO uint32_t TARGET_ROOT71_TOG; /**< Target Register, offset: 0xA38C */ + uint8_t RESERVED_144[16]; + __IO uint32_t POST71; /**< Post Divider Register, offset: 0xA3A0 */ + __IO uint32_t POST_ROOT71_SET; /**< Post Divider Register, offset: 0xA3A4 */ + __IO uint32_t POST_ROOT71_CLR; /**< Post Divider Register, offset: 0xA3A8 */ + __IO uint32_t POST_ROOT71_TOG; /**< Post Divider Register, offset: 0xA3AC */ + __IO uint32_t PRE71; /**< Pre Divider Register, offset: 0xA3B0 */ + __IO uint32_t PRE_ROOT71_SET; /**< Pre Divider Register, offset: 0xA3B4 */ + __IO uint32_t PRE_ROOT71_CLR; /**< Pre Divider Register, offset: 0xA3B8 */ + __IO uint32_t PRE_ROOT71_TOG; /**< Pre Divider Register, offset: 0xA3BC */ + uint8_t RESERVED_145[48]; + __IO uint32_t ACCESS_CTRL71; /**< Access Control Register, offset: 0xA3F0 */ + __IO uint32_t ACCESS_CTRL71_ROOT_SET; /**< Access Control Register, offset: 0xA3F4 */ + __IO uint32_t ACCESS_CTRL71_ROOT_CLR; /**< Access Control Register, offset: 0xA3F8 */ + __IO uint32_t ACCESS_CTRL71_ROOT_TOG; /**< Access Control Register, offset: 0xA3FC */ + __IO uint32_t TARGET_ROOT72; /**< Target Register, offset: 0xA400 */ + __IO uint32_t TARGET_ROOT72_SET; /**< Target Register, offset: 0xA404 */ + __IO uint32_t TARGET_ROOT72_CLR; /**< Target Register, offset: 0xA408 */ + __IO uint32_t TARGET_ROOT72_TOG; /**< Target Register, offset: 0xA40C */ + uint8_t RESERVED_146[16]; + __IO uint32_t POST72; /**< Post Divider Register, offset: 0xA420 */ + __IO uint32_t POST_ROOT72_SET; /**< Post Divider Register, offset: 0xA424 */ + __IO uint32_t POST_ROOT72_CLR; /**< Post Divider Register, offset: 0xA428 */ + __IO uint32_t POST_ROOT72_TOG; /**< Post Divider Register, offset: 0xA42C */ + __IO uint32_t PRE72; /**< Pre Divider Register, offset: 0xA430 */ + __IO uint32_t PRE_ROOT72_SET; /**< Pre Divider Register, offset: 0xA434 */ + __IO uint32_t PRE_ROOT72_CLR; /**< Pre Divider Register, offset: 0xA438 */ + __IO uint32_t PRE_ROOT72_TOG; /**< Pre Divider Register, offset: 0xA43C */ + uint8_t RESERVED_147[48]; + __IO uint32_t ACCESS_CTRL72; /**< Access Control Register, offset: 0xA470 */ + __IO uint32_t ACCESS_CTRL72_ROOT_SET; /**< Access Control Register, offset: 0xA474 */ + __IO uint32_t ACCESS_CTRL72_ROOT_CLR; /**< Access Control Register, offset: 0xA478 */ + __IO uint32_t ACCESS_CTRL72_ROOT_TOG; /**< Access Control Register, offset: 0xA47C */ + __IO uint32_t TARGET_ROOT73; /**< Target Register, offset: 0xA480 */ + __IO uint32_t TARGET_ROOT73_SET; /**< Target Register, offset: 0xA484 */ + __IO uint32_t TARGET_ROOT73_CLR; /**< Target Register, offset: 0xA488 */ + __IO uint32_t TARGET_ROOT73_TOG; /**< Target Register, offset: 0xA48C */ + uint8_t RESERVED_148[16]; + __IO uint32_t POST73; /**< Post Divider Register, offset: 0xA4A0 */ + __IO uint32_t POST_ROOT73_SET; /**< Post Divider Register, offset: 0xA4A4 */ + __IO uint32_t POST_ROOT73_CLR; /**< Post Divider Register, offset: 0xA4A8 */ + __IO uint32_t POST_ROOT73_TOG; /**< Post Divider Register, offset: 0xA4AC */ + __IO uint32_t PRE73; /**< Pre Divider Register, offset: 0xA4B0 */ + __IO uint32_t PRE_ROOT73_SET; /**< Pre Divider Register, offset: 0xA4B4 */ + __IO uint32_t PRE_ROOT73_CLR; /**< Pre Divider Register, offset: 0xA4B8 */ + __IO uint32_t PRE_ROOT73_TOG; /**< Pre Divider Register, offset: 0xA4BC */ + uint8_t RESERVED_149[48]; + __IO uint32_t ACCESS_CTRL73; /**< Access Control Register, offset: 0xA4F0 */ + __IO uint32_t ACCESS_CTRL73_ROOT_SET; /**< Access Control Register, offset: 0xA4F4 */ + __IO uint32_t ACCESS_CTRL73_ROOT_CLR; /**< Access Control Register, offset: 0xA4F8 */ + __IO uint32_t ACCESS_CTRL73_ROOT_TOG; /**< Access Control Register, offset: 0xA4FC */ + __IO uint32_t TARGET_ROOT74; /**< Target Register, offset: 0xA500 */ + __IO uint32_t TARGET_ROOT74_SET; /**< Target Register, offset: 0xA504 */ + __IO uint32_t TARGET_ROOT74_CLR; /**< Target Register, offset: 0xA508 */ + __IO uint32_t TARGET_ROOT74_TOG; /**< Target Register, offset: 0xA50C */ + uint8_t RESERVED_150[16]; + __IO uint32_t POST74; /**< Post Divider Register, offset: 0xA520 */ + __IO uint32_t POST_ROOT74_SET; /**< Post Divider Register, offset: 0xA524 */ + __IO uint32_t POST_ROOT74_CLR; /**< Post Divider Register, offset: 0xA528 */ + __IO uint32_t POST_ROOT74_TOG; /**< Post Divider Register, offset: 0xA52C */ + __IO uint32_t PRE74; /**< Pre Divider Register, offset: 0xA530 */ + __IO uint32_t PRE_ROOT74_SET; /**< Pre Divider Register, offset: 0xA534 */ + __IO uint32_t PRE_ROOT74_CLR; /**< Pre Divider Register, offset: 0xA538 */ + __IO uint32_t PRE_ROOT74_TOG; /**< Pre Divider Register, offset: 0xA53C */ + uint8_t RESERVED_151[48]; + __IO uint32_t ACCESS_CTRL74; /**< Access Control Register, offset: 0xA570 */ + __IO uint32_t ACCESS_CTRL74_ROOT_SET; /**< Access Control Register, offset: 0xA574 */ + __IO uint32_t ACCESS_CTRL74_ROOT_CLR; /**< Access Control Register, offset: 0xA578 */ + __IO uint32_t ACCESS_CTRL74_ROOT_TOG; /**< Access Control Register, offset: 0xA57C */ + __IO uint32_t TARGET_ROOT75; /**< Target Register, offset: 0xA580 */ + __IO uint32_t TARGET_ROOT75_SET; /**< Target Register, offset: 0xA584 */ + __IO uint32_t TARGET_ROOT75_CLR; /**< Target Register, offset: 0xA588 */ + __IO uint32_t TARGET_ROOT75_TOG; /**< Target Register, offset: 0xA58C */ + uint8_t RESERVED_152[16]; + __IO uint32_t POST75; /**< Post Divider Register, offset: 0xA5A0 */ + __IO uint32_t POST_ROOT75_SET; /**< Post Divider Register, offset: 0xA5A4 */ + __IO uint32_t POST_ROOT75_CLR; /**< Post Divider Register, offset: 0xA5A8 */ + __IO uint32_t POST_ROOT75_TOG; /**< Post Divider Register, offset: 0xA5AC */ + __IO uint32_t PRE75; /**< Pre Divider Register, offset: 0xA5B0 */ + __IO uint32_t PRE_ROOT75_SET; /**< Pre Divider Register, offset: 0xA5B4 */ + __IO uint32_t PRE_ROOT75_CLR; /**< Pre Divider Register, offset: 0xA5B8 */ + __IO uint32_t PRE_ROOT75_TOG; /**< Pre Divider Register, offset: 0xA5BC */ + uint8_t RESERVED_153[48]; + __IO uint32_t ACCESS_CTRL75; /**< Access Control Register, offset: 0xA5F0 */ + __IO uint32_t ACCESS_CTRL75_ROOT_SET; /**< Access Control Register, offset: 0xA5F4 */ + __IO uint32_t ACCESS_CTRL75_ROOT_CLR; /**< Access Control Register, offset: 0xA5F8 */ + __IO uint32_t ACCESS_CTRL75_ROOT_TOG; /**< Access Control Register, offset: 0xA5FC */ + __IO uint32_t TARGET_ROOT76; /**< Target Register, offset: 0xA600 */ + __IO uint32_t TARGET_ROOT76_SET; /**< Target Register, offset: 0xA604 */ + __IO uint32_t TARGET_ROOT76_CLR; /**< Target Register, offset: 0xA608 */ + __IO uint32_t TARGET_ROOT76_TOG; /**< Target Register, offset: 0xA60C */ + uint8_t RESERVED_154[16]; + __IO uint32_t POST76; /**< Post Divider Register, offset: 0xA620 */ + __IO uint32_t POST_ROOT76_SET; /**< Post Divider Register, offset: 0xA624 */ + __IO uint32_t POST_ROOT76_CLR; /**< Post Divider Register, offset: 0xA628 */ + __IO uint32_t POST_ROOT76_TOG; /**< Post Divider Register, offset: 0xA62C */ + __IO uint32_t PRE76; /**< Pre Divider Register, offset: 0xA630 */ + __IO uint32_t PRE_ROOT76_SET; /**< Pre Divider Register, offset: 0xA634 */ + __IO uint32_t PRE_ROOT76_CLR; /**< Pre Divider Register, offset: 0xA638 */ + __IO uint32_t PRE_ROOT76_TOG; /**< Pre Divider Register, offset: 0xA63C */ + uint8_t RESERVED_155[48]; + __IO uint32_t ACCESS_CTRL76; /**< Access Control Register, offset: 0xA670 */ + __IO uint32_t ACCESS_CTRL76_ROOT_SET; /**< Access Control Register, offset: 0xA674 */ + __IO uint32_t ACCESS_CTRL76_ROOT_CLR; /**< Access Control Register, offset: 0xA678 */ + __IO uint32_t ACCESS_CTRL76_ROOT_TOG; /**< Access Control Register, offset: 0xA67C */ + __IO uint32_t TARGET_ROOT77; /**< Target Register, offset: 0xA680 */ + __IO uint32_t TARGET_ROOT77_SET; /**< Target Register, offset: 0xA684 */ + __IO uint32_t TARGET_ROOT77_CLR; /**< Target Register, offset: 0xA688 */ + __IO uint32_t TARGET_ROOT77_TOG; /**< Target Register, offset: 0xA68C */ + uint8_t RESERVED_156[16]; + __IO uint32_t POST77; /**< Post Divider Register, offset: 0xA6A0 */ + __IO uint32_t POST_ROOT77_SET; /**< Post Divider Register, offset: 0xA6A4 */ + __IO uint32_t POST_ROOT77_CLR; /**< Post Divider Register, offset: 0xA6A8 */ + __IO uint32_t POST_ROOT77_TOG; /**< Post Divider Register, offset: 0xA6AC */ + __IO uint32_t PRE77; /**< Pre Divider Register, offset: 0xA6B0 */ + __IO uint32_t PRE_ROOT77_SET; /**< Pre Divider Register, offset: 0xA6B4 */ + __IO uint32_t PRE_ROOT77_CLR; /**< Pre Divider Register, offset: 0xA6B8 */ + __IO uint32_t PRE_ROOT77_TOG; /**< Pre Divider Register, offset: 0xA6BC */ + uint8_t RESERVED_157[48]; + __IO uint32_t ACCESS_CTRL77; /**< Access Control Register, offset: 0xA6F0 */ + __IO uint32_t ACCESS_CTRL77_ROOT_SET; /**< Access Control Register, offset: 0xA6F4 */ + __IO uint32_t ACCESS_CTRL77_ROOT_CLR; /**< Access Control Register, offset: 0xA6F8 */ + __IO uint32_t ACCESS_CTRL77_ROOT_TOG; /**< Access Control Register, offset: 0xA6FC */ + __IO uint32_t TARGET_ROOT78; /**< Target Register, offset: 0xA700 */ + __IO uint32_t TARGET_ROOT78_SET; /**< Target Register, offset: 0xA704 */ + __IO uint32_t TARGET_ROOT78_CLR; /**< Target Register, offset: 0xA708 */ + __IO uint32_t TARGET_ROOT78_TOG; /**< Target Register, offset: 0xA70C */ + uint8_t RESERVED_158[16]; + __IO uint32_t POST78; /**< Post Divider Register, offset: 0xA720 */ + __IO uint32_t POST_ROOT78_SET; /**< Post Divider Register, offset: 0xA724 */ + __IO uint32_t POST_ROOT78_CLR; /**< Post Divider Register, offset: 0xA728 */ + __IO uint32_t POST_ROOT78_TOG; /**< Post Divider Register, offset: 0xA72C */ + __IO uint32_t PRE78; /**< Pre Divider Register, offset: 0xA730 */ + __IO uint32_t PRE_ROOT78_SET; /**< Pre Divider Register, offset: 0xA734 */ + __IO uint32_t PRE_ROOT78_CLR; /**< Pre Divider Register, offset: 0xA738 */ + __IO uint32_t PRE_ROOT78_TOG; /**< Pre Divider Register, offset: 0xA73C */ + uint8_t RESERVED_159[48]; + __IO uint32_t ACCESS_CTRL78; /**< Access Control Register, offset: 0xA770 */ + __IO uint32_t ACCESS_CTRL78_ROOT_SET; /**< Access Control Register, offset: 0xA774 */ + __IO uint32_t ACCESS_CTRL78_ROOT_CLR; /**< Access Control Register, offset: 0xA778 */ + __IO uint32_t ACCESS_CTRL78_ROOT_TOG; /**< Access Control Register, offset: 0xA77C */ + __IO uint32_t TARGET_ROOT79; /**< Target Register, offset: 0xA780 */ + __IO uint32_t TARGET_ROOT79_SET; /**< Target Register, offset: 0xA784 */ + __IO uint32_t TARGET_ROOT79_CLR; /**< Target Register, offset: 0xA788 */ + __IO uint32_t TARGET_ROOT79_TOG; /**< Target Register, offset: 0xA78C */ + uint8_t RESERVED_160[16]; + __IO uint32_t POST79; /**< Post Divider Register, offset: 0xA7A0 */ + __IO uint32_t POST_ROOT79_SET; /**< Post Divider Register, offset: 0xA7A4 */ + __IO uint32_t POST_ROOT79_CLR; /**< Post Divider Register, offset: 0xA7A8 */ + __IO uint32_t POST_ROOT79_TOG; /**< Post Divider Register, offset: 0xA7AC */ + __IO uint32_t PRE79; /**< Pre Divider Register, offset: 0xA7B0 */ + __IO uint32_t PRE_ROOT79_SET; /**< Pre Divider Register, offset: 0xA7B4 */ + __IO uint32_t PRE_ROOT79_CLR; /**< Pre Divider Register, offset: 0xA7B8 */ + __IO uint32_t PRE_ROOT79_TOG; /**< Pre Divider Register, offset: 0xA7BC */ + uint8_t RESERVED_161[48]; + __IO uint32_t ACCESS_CTRL79; /**< Access Control Register, offset: 0xA7F0 */ + __IO uint32_t ACCESS_CTRL79_ROOT_SET; /**< Access Control Register, offset: 0xA7F4 */ + __IO uint32_t ACCESS_CTRL79_ROOT_CLR; /**< Access Control Register, offset: 0xA7F8 */ + __IO uint32_t ACCESS_CTRL79_ROOT_TOG; /**< Access Control Register, offset: 0xA7FC */ + __IO uint32_t TARGET_ROOT80; /**< Target Register, offset: 0xA800 */ + __IO uint32_t TARGET_ROOT80_SET; /**< Target Register, offset: 0xA804 */ + __IO uint32_t TARGET_ROOT80_CLR; /**< Target Register, offset: 0xA808 */ + __IO uint32_t TARGET_ROOT80_TOG; /**< Target Register, offset: 0xA80C */ + uint8_t RESERVED_162[16]; + __IO uint32_t POST80; /**< Post Divider Register, offset: 0xA820 */ + __IO uint32_t POST_ROOT80_SET; /**< Post Divider Register, offset: 0xA824 */ + __IO uint32_t POST_ROOT80_CLR; /**< Post Divider Register, offset: 0xA828 */ + __IO uint32_t POST_ROOT80_TOG; /**< Post Divider Register, offset: 0xA82C */ + __IO uint32_t PRE80; /**< Pre Divider Register, offset: 0xA830 */ + __IO uint32_t PRE_ROOT80_SET; /**< Pre Divider Register, offset: 0xA834 */ + __IO uint32_t PRE_ROOT80_CLR; /**< Pre Divider Register, offset: 0xA838 */ + __IO uint32_t PRE_ROOT80_TOG; /**< Pre Divider Register, offset: 0xA83C */ + uint8_t RESERVED_163[48]; + __IO uint32_t ACCESS_CTRL80; /**< Access Control Register, offset: 0xA870 */ + __IO uint32_t ACCESS_CTRL80_ROOT_SET; /**< Access Control Register, offset: 0xA874 */ + __IO uint32_t ACCESS_CTRL80_ROOT_CLR; /**< Access Control Register, offset: 0xA878 */ + __IO uint32_t ACCESS_CTRL80_ROOT_TOG; /**< Access Control Register, offset: 0xA87C */ + __IO uint32_t TARGET_ROOT81; /**< Target Register, offset: 0xA880 */ + __IO uint32_t TARGET_ROOT81_SET; /**< Target Register, offset: 0xA884 */ + __IO uint32_t TARGET_ROOT81_CLR; /**< Target Register, offset: 0xA888 */ + __IO uint32_t TARGET_ROOT81_TOG; /**< Target Register, offset: 0xA88C */ + uint8_t RESERVED_164[16]; + __IO uint32_t POST81; /**< Post Divider Register, offset: 0xA8A0 */ + __IO uint32_t POST_ROOT81_SET; /**< Post Divider Register, offset: 0xA8A4 */ + __IO uint32_t POST_ROOT81_CLR; /**< Post Divider Register, offset: 0xA8A8 */ + __IO uint32_t POST_ROOT81_TOG; /**< Post Divider Register, offset: 0xA8AC */ + __IO uint32_t PRE81; /**< Pre Divider Register, offset: 0xA8B0 */ + __IO uint32_t PRE_ROOT81_SET; /**< Pre Divider Register, offset: 0xA8B4 */ + __IO uint32_t PRE_ROOT81_CLR; /**< Pre Divider Register, offset: 0xA8B8 */ + __IO uint32_t PRE_ROOT81_TOG; /**< Pre Divider Register, offset: 0xA8BC */ + uint8_t RESERVED_165[48]; + __IO uint32_t ACCESS_CTRL81; /**< Access Control Register, offset: 0xA8F0 */ + __IO uint32_t ACCESS_CTRL81_ROOT_SET; /**< Access Control Register, offset: 0xA8F4 */ + __IO uint32_t ACCESS_CTRL81_ROOT_CLR; /**< Access Control Register, offset: 0xA8F8 */ + __IO uint32_t ACCESS_CTRL81_ROOT_TOG; /**< Access Control Register, offset: 0xA8FC */ + __IO uint32_t TARGET_ROOT82; /**< Target Register, offset: 0xA900 */ + __IO uint32_t TARGET_ROOT82_SET; /**< Target Register, offset: 0xA904 */ + __IO uint32_t TARGET_ROOT82_CLR; /**< Target Register, offset: 0xA908 */ + __IO uint32_t TARGET_ROOT82_TOG; /**< Target Register, offset: 0xA90C */ + uint8_t RESERVED_166[16]; + __IO uint32_t POST82; /**< Post Divider Register, offset: 0xA920 */ + __IO uint32_t POST_ROOT82_SET; /**< Post Divider Register, offset: 0xA924 */ + __IO uint32_t POST_ROOT82_CLR; /**< Post Divider Register, offset: 0xA928 */ + __IO uint32_t POST_ROOT82_TOG; /**< Post Divider Register, offset: 0xA92C */ + __IO uint32_t PRE82; /**< Pre Divider Register, offset: 0xA930 */ + __IO uint32_t PRE_ROOT82_SET; /**< Pre Divider Register, offset: 0xA934 */ + __IO uint32_t PRE_ROOT82_CLR; /**< Pre Divider Register, offset: 0xA938 */ + __IO uint32_t PRE_ROOT82_TOG; /**< Pre Divider Register, offset: 0xA93C */ + uint8_t RESERVED_167[48]; + __IO uint32_t ACCESS_CTRL82; /**< Access Control Register, offset: 0xA970 */ + __IO uint32_t ACCESS_CTRL82_ROOT_SET; /**< Access Control Register, offset: 0xA974 */ + __IO uint32_t ACCESS_CTRL82_ROOT_CLR; /**< Access Control Register, offset: 0xA978 */ + __IO uint32_t ACCESS_CTRL82_ROOT_TOG; /**< Access Control Register, offset: 0xA97C */ + __IO uint32_t TARGET_ROOT83; /**< Target Register, offset: 0xA980 */ + __IO uint32_t TARGET_ROOT83_SET; /**< Target Register, offset: 0xA984 */ + __IO uint32_t TARGET_ROOT83_CLR; /**< Target Register, offset: 0xA988 */ + __IO uint32_t TARGET_ROOT83_TOG; /**< Target Register, offset: 0xA98C */ + uint8_t RESERVED_168[16]; + __IO uint32_t POST83; /**< Post Divider Register, offset: 0xA9A0 */ + __IO uint32_t POST_ROOT83_SET; /**< Post Divider Register, offset: 0xA9A4 */ + __IO uint32_t POST_ROOT83_CLR; /**< Post Divider Register, offset: 0xA9A8 */ + __IO uint32_t POST_ROOT83_TOG; /**< Post Divider Register, offset: 0xA9AC */ + __IO uint32_t PRE83; /**< Pre Divider Register, offset: 0xA9B0 */ + __IO uint32_t PRE_ROOT83_SET; /**< Pre Divider Register, offset: 0xA9B4 */ + __IO uint32_t PRE_ROOT83_CLR; /**< Pre Divider Register, offset: 0xA9B8 */ + __IO uint32_t PRE_ROOT83_TOG; /**< Pre Divider Register, offset: 0xA9BC */ + uint8_t RESERVED_169[48]; + __IO uint32_t ACCESS_CTRL83; /**< Access Control Register, offset: 0xA9F0 */ + __IO uint32_t ACCESS_CTRL83_ROOT_SET; /**< Access Control Register, offset: 0xA9F4 */ + __IO uint32_t ACCESS_CTRL83_ROOT_CLR; /**< Access Control Register, offset: 0xA9F8 */ + __IO uint32_t ACCESS_CTRL83_ROOT_TOG; /**< Access Control Register, offset: 0xA9FC */ + __IO uint32_t TARGET_ROOT84; /**< Target Register, offset: 0xAA00 */ + __IO uint32_t TARGET_ROOT84_SET; /**< Target Register, offset: 0xAA04 */ + __IO uint32_t TARGET_ROOT84_CLR; /**< Target Register, offset: 0xAA08 */ + __IO uint32_t TARGET_ROOT84_TOG; /**< Target Register, offset: 0xAA0C */ + uint8_t RESERVED_170[16]; + __IO uint32_t POST84; /**< Post Divider Register, offset: 0xAA20 */ + __IO uint32_t POST_ROOT84_SET; /**< Post Divider Register, offset: 0xAA24 */ + __IO uint32_t POST_ROOT84_CLR; /**< Post Divider Register, offset: 0xAA28 */ + __IO uint32_t POST_ROOT84_TOG; /**< Post Divider Register, offset: 0xAA2C */ + __IO uint32_t PRE84; /**< Pre Divider Register, offset: 0xAA30 */ + __IO uint32_t PRE_ROOT84_SET; /**< Pre Divider Register, offset: 0xAA34 */ + __IO uint32_t PRE_ROOT84_CLR; /**< Pre Divider Register, offset: 0xAA38 */ + __IO uint32_t PRE_ROOT84_TOG; /**< Pre Divider Register, offset: 0xAA3C */ + uint8_t RESERVED_171[48]; + __IO uint32_t ACCESS_CTRL84; /**< Access Control Register, offset: 0xAA70 */ + __IO uint32_t ACCESS_CTRL84_ROOT_SET; /**< Access Control Register, offset: 0xAA74 */ + __IO uint32_t ACCESS_CTRL84_ROOT_CLR; /**< Access Control Register, offset: 0xAA78 */ + __IO uint32_t ACCESS_CTRL84_ROOT_TOG; /**< Access Control Register, offset: 0xAA7C */ + __IO uint32_t TARGET_ROOT85; /**< Target Register, offset: 0xAA80 */ + __IO uint32_t TARGET_ROOT85_SET; /**< Target Register, offset: 0xAA84 */ + __IO uint32_t TARGET_ROOT85_CLR; /**< Target Register, offset: 0xAA88 */ + __IO uint32_t TARGET_ROOT85_TOG; /**< Target Register, offset: 0xAA8C */ + uint8_t RESERVED_172[16]; + __IO uint32_t POST85; /**< Post Divider Register, offset: 0xAAA0 */ + __IO uint32_t POST_ROOT85_SET; /**< Post Divider Register, offset: 0xAAA4 */ + __IO uint32_t POST_ROOT85_CLR; /**< Post Divider Register, offset: 0xAAA8 */ + __IO uint32_t POST_ROOT85_TOG; /**< Post Divider Register, offset: 0xAAAC */ + __IO uint32_t PRE85; /**< Pre Divider Register, offset: 0xAAB0 */ + __IO uint32_t PRE_ROOT85_SET; /**< Pre Divider Register, offset: 0xAAB4 */ + __IO uint32_t PRE_ROOT85_CLR; /**< Pre Divider Register, offset: 0xAAB8 */ + __IO uint32_t PRE_ROOT85_TOG; /**< Pre Divider Register, offset: 0xAABC */ + uint8_t RESERVED_173[48]; + __IO uint32_t ACCESS_CTRL85; /**< Access Control Register, offset: 0xAAF0 */ + __IO uint32_t ACCESS_CTRL85_ROOT_SET; /**< Access Control Register, offset: 0xAAF4 */ + __IO uint32_t ACCESS_CTRL85_ROOT_CLR; /**< Access Control Register, offset: 0xAAF8 */ + __IO uint32_t ACCESS_CTRL85_ROOT_TOG; /**< Access Control Register, offset: 0xAAFC */ + __IO uint32_t TARGET_ROOT86; /**< Target Register, offset: 0xAB00 */ + __IO uint32_t TARGET_ROOT86_SET; /**< Target Register, offset: 0xAB04 */ + __IO uint32_t TARGET_ROOT86_CLR; /**< Target Register, offset: 0xAB08 */ + __IO uint32_t TARGET_ROOT86_TOG; /**< Target Register, offset: 0xAB0C */ + uint8_t RESERVED_174[16]; + __IO uint32_t POST86; /**< Post Divider Register, offset: 0xAB20 */ + __IO uint32_t POST_ROOT86_SET; /**< Post Divider Register, offset: 0xAB24 */ + __IO uint32_t POST_ROOT86_CLR; /**< Post Divider Register, offset: 0xAB28 */ + __IO uint32_t POST_ROOT86_TOG; /**< Post Divider Register, offset: 0xAB2C */ + __IO uint32_t PRE86; /**< Pre Divider Register, offset: 0xAB30 */ + __IO uint32_t PRE_ROOT86_SET; /**< Pre Divider Register, offset: 0xAB34 */ + __IO uint32_t PRE_ROOT86_CLR; /**< Pre Divider Register, offset: 0xAB38 */ + __IO uint32_t PRE_ROOT86_TOG; /**< Pre Divider Register, offset: 0xAB3C */ + uint8_t RESERVED_175[48]; + __IO uint32_t ACCESS_CTRL86; /**< Access Control Register, offset: 0xAB70 */ + __IO uint32_t ACCESS_CTRL86_ROOT_SET; /**< Access Control Register, offset: 0xAB74 */ + __IO uint32_t ACCESS_CTRL86_ROOT_CLR; /**< Access Control Register, offset: 0xAB78 */ + __IO uint32_t ACCESS_CTRL86_ROOT_TOG; /**< Access Control Register, offset: 0xAB7C */ + __IO uint32_t TARGET_ROOT87; /**< Target Register, offset: 0xAB80 */ + __IO uint32_t TARGET_ROOT87_SET; /**< Target Register, offset: 0xAB84 */ + __IO uint32_t TARGET_ROOT87_CLR; /**< Target Register, offset: 0xAB88 */ + __IO uint32_t TARGET_ROOT87_TOG; /**< Target Register, offset: 0xAB8C */ + uint8_t RESERVED_176[16]; + __IO uint32_t POST87; /**< Post Divider Register, offset: 0xABA0 */ + __IO uint32_t POST_ROOT87_SET; /**< Post Divider Register, offset: 0xABA4 */ + __IO uint32_t POST_ROOT87_CLR; /**< Post Divider Register, offset: 0xABA8 */ + __IO uint32_t POST_ROOT87_TOG; /**< Post Divider Register, offset: 0xABAC */ + __IO uint32_t PRE87; /**< Pre Divider Register, offset: 0xABB0 */ + __IO uint32_t PRE_ROOT87_SET; /**< Pre Divider Register, offset: 0xABB4 */ + __IO uint32_t PRE_ROOT87_CLR; /**< Pre Divider Register, offset: 0xABB8 */ + __IO uint32_t PRE_ROOT87_TOG; /**< Pre Divider Register, offset: 0xABBC */ + uint8_t RESERVED_177[48]; + __IO uint32_t ACCESS_CTRL87; /**< Access Control Register, offset: 0xABF0 */ + __IO uint32_t ACCESS_CTRL87_ROOT_SET; /**< Access Control Register, offset: 0xABF4 */ + __IO uint32_t ACCESS_CTRL87_ROOT_CLR; /**< Access Control Register, offset: 0xABF8 */ + __IO uint32_t ACCESS_CTRL87_ROOT_TOG; /**< Access Control Register, offset: 0xABFC */ + __IO uint32_t TARGET_ROOT88; /**< Target Register, offset: 0xAC00 */ + __IO uint32_t TARGET_ROOT88_SET; /**< Target Register, offset: 0xAC04 */ + __IO uint32_t TARGET_ROOT88_CLR; /**< Target Register, offset: 0xAC08 */ + __IO uint32_t TARGET_ROOT88_TOG; /**< Target Register, offset: 0xAC0C */ + uint8_t RESERVED_178[16]; + __IO uint32_t POST88; /**< Post Divider Register, offset: 0xAC20 */ + __IO uint32_t POST_ROOT88_SET; /**< Post Divider Register, offset: 0xAC24 */ + __IO uint32_t POST_ROOT88_CLR; /**< Post Divider Register, offset: 0xAC28 */ + __IO uint32_t POST_ROOT88_TOG; /**< Post Divider Register, offset: 0xAC2C */ + __IO uint32_t PRE88; /**< Pre Divider Register, offset: 0xAC30 */ + __IO uint32_t PRE_ROOT88_SET; /**< Pre Divider Register, offset: 0xAC34 */ + __IO uint32_t PRE_ROOT88_CLR; /**< Pre Divider Register, offset: 0xAC38 */ + __IO uint32_t PRE_ROOT88_TOG; /**< Pre Divider Register, offset: 0xAC3C */ + uint8_t RESERVED_179[48]; + __IO uint32_t ACCESS_CTRL88; /**< Access Control Register, offset: 0xAC70 */ + __IO uint32_t ACCESS_CTRL88_ROOT_SET; /**< Access Control Register, offset: 0xAC74 */ + __IO uint32_t ACCESS_CTRL88_ROOT_CLR; /**< Access Control Register, offset: 0xAC78 */ + __IO uint32_t ACCESS_CTRL88_ROOT_TOG; /**< Access Control Register, offset: 0xAC7C */ + __IO uint32_t TARGET_ROOT89; /**< Target Register, offset: 0xAC80 */ + __IO uint32_t TARGET_ROOT89_SET; /**< Target Register, offset: 0xAC84 */ + __IO uint32_t TARGET_ROOT89_CLR; /**< Target Register, offset: 0xAC88 */ + __IO uint32_t TARGET_ROOT89_TOG; /**< Target Register, offset: 0xAC8C */ + uint8_t RESERVED_180[16]; + __IO uint32_t POST89; /**< Post Divider Register, offset: 0xACA0 */ + __IO uint32_t POST_ROOT89_SET; /**< Post Divider Register, offset: 0xACA4 */ + __IO uint32_t POST_ROOT89_CLR; /**< Post Divider Register, offset: 0xACA8 */ + __IO uint32_t POST_ROOT89_TOG; /**< Post Divider Register, offset: 0xACAC */ + __IO uint32_t PRE89; /**< Pre Divider Register, offset: 0xACB0 */ + __IO uint32_t PRE_ROOT89_SET; /**< Pre Divider Register, offset: 0xACB4 */ + __IO uint32_t PRE_ROOT89_CLR; /**< Pre Divider Register, offset: 0xACB8 */ + __IO uint32_t PRE_ROOT89_TOG; /**< Pre Divider Register, offset: 0xACBC */ + uint8_t RESERVED_181[48]; + __IO uint32_t ACCESS_CTRL89; /**< Access Control Register, offset: 0xACF0 */ + __IO uint32_t ACCESS_CTRL89_ROOT_SET; /**< Access Control Register, offset: 0xACF4 */ + __IO uint32_t ACCESS_CTRL89_ROOT_CLR; /**< Access Control Register, offset: 0xACF8 */ + __IO uint32_t ACCESS_CTRL89_ROOT_TOG; /**< Access Control Register, offset: 0xACFC */ + __IO uint32_t TARGET_ROOT90; /**< Target Register, offset: 0xAD00 */ + __IO uint32_t TARGET_ROOT90_SET; /**< Target Register, offset: 0xAD04 */ + __IO uint32_t TARGET_ROOT90_CLR; /**< Target Register, offset: 0xAD08 */ + __IO uint32_t TARGET_ROOT90_TOG; /**< Target Register, offset: 0xAD0C */ + uint8_t RESERVED_182[16]; + __IO uint32_t POST90; /**< Post Divider Register, offset: 0xAD20 */ + __IO uint32_t POST_ROOT90_SET; /**< Post Divider Register, offset: 0xAD24 */ + __IO uint32_t POST_ROOT90_CLR; /**< Post Divider Register, offset: 0xAD28 */ + __IO uint32_t POST_ROOT90_TOG; /**< Post Divider Register, offset: 0xAD2C */ + __IO uint32_t PRE90; /**< Pre Divider Register, offset: 0xAD30 */ + __IO uint32_t PRE_ROOT90_SET; /**< Pre Divider Register, offset: 0xAD34 */ + __IO uint32_t PRE_ROOT90_CLR; /**< Pre Divider Register, offset: 0xAD38 */ + __IO uint32_t PRE_ROOT90_TOG; /**< Pre Divider Register, offset: 0xAD3C */ + uint8_t RESERVED_183[48]; + __IO uint32_t ACCESS_CTRL90; /**< Access Control Register, offset: 0xAD70 */ + __IO uint32_t ACCESS_CTRL90_ROOT_SET; /**< Access Control Register, offset: 0xAD74 */ + __IO uint32_t ACCESS_CTRL90_ROOT_CLR; /**< Access Control Register, offset: 0xAD78 */ + __IO uint32_t ACCESS_CTRL90_ROOT_TOG; /**< Access Control Register, offset: 0xAD7C */ + __IO uint32_t TARGET_ROOT91; /**< Target Register, offset: 0xAD80 */ + __IO uint32_t TARGET_ROOT91_SET; /**< Target Register, offset: 0xAD84 */ + __IO uint32_t TARGET_ROOT91_CLR; /**< Target Register, offset: 0xAD88 */ + __IO uint32_t TARGET_ROOT91_TOG; /**< Target Register, offset: 0xAD8C */ + uint8_t RESERVED_184[16]; + __IO uint32_t POST91; /**< Post Divider Register, offset: 0xADA0 */ + __IO uint32_t POST_ROOT91_SET; /**< Post Divider Register, offset: 0xADA4 */ + __IO uint32_t POST_ROOT91_CLR; /**< Post Divider Register, offset: 0xADA8 */ + __IO uint32_t POST_ROOT91_TOG; /**< Post Divider Register, offset: 0xADAC */ + __IO uint32_t PRE91; /**< Pre Divider Register, offset: 0xADB0 */ + __IO uint32_t PRE_ROOT91_SET; /**< Pre Divider Register, offset: 0xADB4 */ + __IO uint32_t PRE_ROOT91_CLR; /**< Pre Divider Register, offset: 0xADB8 */ + __IO uint32_t PRE_ROOT91_TOG; /**< Pre Divider Register, offset: 0xADBC */ + uint8_t RESERVED_185[48]; + __IO uint32_t ACCESS_CTRL91; /**< Access Control Register, offset: 0xADF0 */ + __IO uint32_t ACCESS_CTRL91_ROOT_SET; /**< Access Control Register, offset: 0xADF4 */ + __IO uint32_t ACCESS_CTRL91_ROOT_CLR; /**< Access Control Register, offset: 0xADF8 */ + __IO uint32_t ACCESS_CTRL91_ROOT_TOG; /**< Access Control Register, offset: 0xADFC */ + __IO uint32_t TARGET_ROOT92; /**< Target Register, offset: 0xAE00 */ + __IO uint32_t TARGET_ROOT92_SET; /**< Target Register, offset: 0xAE04 */ + __IO uint32_t TARGET_ROOT92_CLR; /**< Target Register, offset: 0xAE08 */ + __IO uint32_t TARGET_ROOT92_TOG; /**< Target Register, offset: 0xAE0C */ + uint8_t RESERVED_186[16]; + __IO uint32_t POST92; /**< Post Divider Register, offset: 0xAE20 */ + __IO uint32_t POST_ROOT92_SET; /**< Post Divider Register, offset: 0xAE24 */ + __IO uint32_t POST_ROOT92_CLR; /**< Post Divider Register, offset: 0xAE28 */ + __IO uint32_t POST_ROOT92_TOG; /**< Post Divider Register, offset: 0xAE2C */ + __IO uint32_t PRE92; /**< Pre Divider Register, offset: 0xAE30 */ + __IO uint32_t PRE_ROOT92_SET; /**< Pre Divider Register, offset: 0xAE34 */ + __IO uint32_t PRE_ROOT92_CLR; /**< Pre Divider Register, offset: 0xAE38 */ + __IO uint32_t PRE_ROOT92_TOG; /**< Pre Divider Register, offset: 0xAE3C */ + uint8_t RESERVED_187[48]; + __IO uint32_t ACCESS_CTRL92; /**< Access Control Register, offset: 0xAE70 */ + __IO uint32_t ACCESS_CTRL92_ROOT_SET; /**< Access Control Register, offset: 0xAE74 */ + __IO uint32_t ACCESS_CTRL92_ROOT_CLR; /**< Access Control Register, offset: 0xAE78 */ + __IO uint32_t ACCESS_CTRL92_ROOT_TOG; /**< Access Control Register, offset: 0xAE7C */ + __IO uint32_t TARGET_ROOT93; /**< Target Register, offset: 0xAE80 */ + __IO uint32_t TARGET_ROOT93_SET; /**< Target Register, offset: 0xAE84 */ + __IO uint32_t TARGET_ROOT93_CLR; /**< Target Register, offset: 0xAE88 */ + __IO uint32_t TARGET_ROOT93_TOG; /**< Target Register, offset: 0xAE8C */ + uint8_t RESERVED_188[16]; + __IO uint32_t POST93; /**< Post Divider Register, offset: 0xAEA0 */ + __IO uint32_t POST_ROOT93_SET; /**< Post Divider Register, offset: 0xAEA4 */ + __IO uint32_t POST_ROOT93_CLR; /**< Post Divider Register, offset: 0xAEA8 */ + __IO uint32_t POST_ROOT93_TOG; /**< Post Divider Register, offset: 0xAEAC */ + __IO uint32_t PRE93; /**< Pre Divider Register, offset: 0xAEB0 */ + __IO uint32_t PRE_ROOT93_SET; /**< Pre Divider Register, offset: 0xAEB4 */ + __IO uint32_t PRE_ROOT93_CLR; /**< Pre Divider Register, offset: 0xAEB8 */ + __IO uint32_t PRE_ROOT93_TOG; /**< Pre Divider Register, offset: 0xAEBC */ + uint8_t RESERVED_189[48]; + __IO uint32_t ACCESS_CTRL93; /**< Access Control Register, offset: 0xAEF0 */ + __IO uint32_t ACCESS_CTRL93_ROOT_SET; /**< Access Control Register, offset: 0xAEF4 */ + __IO uint32_t ACCESS_CTRL93_ROOT_CLR; /**< Access Control Register, offset: 0xAEF8 */ + __IO uint32_t ACCESS_CTRL93_ROOT_TOG; /**< Access Control Register, offset: 0xAEFC */ + __IO uint32_t TARGET_ROOT94; /**< Target Register, offset: 0xAF00 */ + __IO uint32_t TARGET_ROOT94_SET; /**< Target Register, offset: 0xAF04 */ + __IO uint32_t TARGET_ROOT94_CLR; /**< Target Register, offset: 0xAF08 */ + __IO uint32_t TARGET_ROOT94_TOG; /**< Target Register, offset: 0xAF0C */ + uint8_t RESERVED_190[16]; + __IO uint32_t POST94; /**< Post Divider Register, offset: 0xAF20 */ + __IO uint32_t POST_ROOT94_SET; /**< Post Divider Register, offset: 0xAF24 */ + __IO uint32_t POST_ROOT94_CLR; /**< Post Divider Register, offset: 0xAF28 */ + __IO uint32_t POST_ROOT94_TOG; /**< Post Divider Register, offset: 0xAF2C */ + __IO uint32_t PRE94; /**< Pre Divider Register, offset: 0xAF30 */ + __IO uint32_t PRE_ROOT94_SET; /**< Pre Divider Register, offset: 0xAF34 */ + __IO uint32_t PRE_ROOT94_CLR; /**< Pre Divider Register, offset: 0xAF38 */ + __IO uint32_t PRE_ROOT94_TOG; /**< Pre Divider Register, offset: 0xAF3C */ + uint8_t RESERVED_191[48]; + __IO uint32_t ACCESS_CTRL94; /**< Access Control Register, offset: 0xAF70 */ + __IO uint32_t ACCESS_CTRL94_ROOT_SET; /**< Access Control Register, offset: 0xAF74 */ + __IO uint32_t ACCESS_CTRL94_ROOT_CLR; /**< Access Control Register, offset: 0xAF78 */ + __IO uint32_t ACCESS_CTRL94_ROOT_TOG; /**< Access Control Register, offset: 0xAF7C */ + __IO uint32_t TARGET_ROOT95; /**< Target Register, offset: 0xAF80 */ + __IO uint32_t TARGET_ROOT95_SET; /**< Target Register, offset: 0xAF84 */ + __IO uint32_t TARGET_ROOT95_CLR; /**< Target Register, offset: 0xAF88 */ + __IO uint32_t TARGET_ROOT95_TOG; /**< Target Register, offset: 0xAF8C */ + uint8_t RESERVED_192[16]; + __IO uint32_t POST95; /**< Post Divider Register, offset: 0xAFA0 */ + __IO uint32_t POST_ROOT95_SET; /**< Post Divider Register, offset: 0xAFA4 */ + __IO uint32_t POST_ROOT95_CLR; /**< Post Divider Register, offset: 0xAFA8 */ + __IO uint32_t POST_ROOT95_TOG; /**< Post Divider Register, offset: 0xAFAC */ + __IO uint32_t PRE95; /**< Pre Divider Register, offset: 0xAFB0 */ + __IO uint32_t PRE_ROOT95_SET; /**< Pre Divider Register, offset: 0xAFB4 */ + __IO uint32_t PRE_ROOT95_CLR; /**< Pre Divider Register, offset: 0xAFB8 */ + __IO uint32_t PRE_ROOT95_TOG; /**< Pre Divider Register, offset: 0xAFBC */ + uint8_t RESERVED_193[48]; + __IO uint32_t ACCESS_CTRL95; /**< Access Control Register, offset: 0xAFF0 */ + __IO uint32_t ACCESS_CTRL95_ROOT_SET; /**< Access Control Register, offset: 0xAFF4 */ + __IO uint32_t ACCESS_CTRL95_ROOT_CLR; /**< Access Control Register, offset: 0xAFF8 */ + __IO uint32_t ACCESS_CTRL95_ROOT_TOG; /**< Access Control Register, offset: 0xAFFC */ + __IO uint32_t TARGET_ROOT96; /**< Target Register, offset: 0xB000 */ + __IO uint32_t TARGET_ROOT96_SET; /**< Target Register, offset: 0xB004 */ + __IO uint32_t TARGET_ROOT96_CLR; /**< Target Register, offset: 0xB008 */ + __IO uint32_t TARGET_ROOT96_TOG; /**< Target Register, offset: 0xB00C */ + uint8_t RESERVED_194[16]; + __IO uint32_t POST96; /**< Post Divider Register, offset: 0xB020 */ + __IO uint32_t POST_ROOT96_SET; /**< Post Divider Register, offset: 0xB024 */ + __IO uint32_t POST_ROOT96_CLR; /**< Post Divider Register, offset: 0xB028 */ + __IO uint32_t POST_ROOT96_TOG; /**< Post Divider Register, offset: 0xB02C */ + __IO uint32_t PRE96; /**< Pre Divider Register, offset: 0xB030 */ + __IO uint32_t PRE_ROOT96_SET; /**< Pre Divider Register, offset: 0xB034 */ + __IO uint32_t PRE_ROOT96_CLR; /**< Pre Divider Register, offset: 0xB038 */ + __IO uint32_t PRE_ROOT96_TOG; /**< Pre Divider Register, offset: 0xB03C */ + uint8_t RESERVED_195[48]; + __IO uint32_t ACCESS_CTRL96; /**< Access Control Register, offset: 0xB070 */ + __IO uint32_t ACCESS_CTRL96_ROOT_SET; /**< Access Control Register, offset: 0xB074 */ + __IO uint32_t ACCESS_CTRL96_ROOT_CLR; /**< Access Control Register, offset: 0xB078 */ + __IO uint32_t ACCESS_CTRL96_ROOT_TOG; /**< Access Control Register, offset: 0xB07C */ + __IO uint32_t TARGET_ROOT97; /**< Target Register, offset: 0xB080 */ + __IO uint32_t TARGET_ROOT97_SET; /**< Target Register, offset: 0xB084 */ + __IO uint32_t TARGET_ROOT97_CLR; /**< Target Register, offset: 0xB088 */ + __IO uint32_t TARGET_ROOT97_TOG; /**< Target Register, offset: 0xB08C */ + uint8_t RESERVED_196[16]; + __IO uint32_t POST97; /**< Post Divider Register, offset: 0xB0A0 */ + __IO uint32_t POST_ROOT97_SET; /**< Post Divider Register, offset: 0xB0A4 */ + __IO uint32_t POST_ROOT97_CLR; /**< Post Divider Register, offset: 0xB0A8 */ + __IO uint32_t POST_ROOT97_TOG; /**< Post Divider Register, offset: 0xB0AC */ + __IO uint32_t PRE97; /**< Pre Divider Register, offset: 0xB0B0 */ + __IO uint32_t PRE_ROOT97_SET; /**< Pre Divider Register, offset: 0xB0B4 */ + __IO uint32_t PRE_ROOT97_CLR; /**< Pre Divider Register, offset: 0xB0B8 */ + __IO uint32_t PRE_ROOT97_TOG; /**< Pre Divider Register, offset: 0xB0BC */ + uint8_t RESERVED_197[48]; + __IO uint32_t ACCESS_CTRL97; /**< Access Control Register, offset: 0xB0F0 */ + __IO uint32_t ACCESS_CTRL97_ROOT_SET; /**< Access Control Register, offset: 0xB0F4 */ + __IO uint32_t ACCESS_CTRL97_ROOT_CLR; /**< Access Control Register, offset: 0xB0F8 */ + __IO uint32_t ACCESS_CTRL97_ROOT_TOG; /**< Access Control Register, offset: 0xB0FC */ + __IO uint32_t TARGET_ROOT98; /**< Target Register, offset: 0xB100 */ + __IO uint32_t TARGET_ROOT98_SET; /**< Target Register, offset: 0xB104 */ + __IO uint32_t TARGET_ROOT98_CLR; /**< Target Register, offset: 0xB108 */ + __IO uint32_t TARGET_ROOT98_TOG; /**< Target Register, offset: 0xB10C */ + uint8_t RESERVED_198[16]; + __IO uint32_t POST98; /**< Post Divider Register, offset: 0xB120 */ + __IO uint32_t POST_ROOT98_SET; /**< Post Divider Register, offset: 0xB124 */ + __IO uint32_t POST_ROOT98_CLR; /**< Post Divider Register, offset: 0xB128 */ + __IO uint32_t POST_ROOT98_TOG; /**< Post Divider Register, offset: 0xB12C */ + __IO uint32_t PRE98; /**< Pre Divider Register, offset: 0xB130 */ + __IO uint32_t PRE_ROOT98_SET; /**< Pre Divider Register, offset: 0xB134 */ + __IO uint32_t PRE_ROOT98_CLR; /**< Pre Divider Register, offset: 0xB138 */ + __IO uint32_t PRE_ROOT98_TOG; /**< Pre Divider Register, offset: 0xB13C */ + uint8_t RESERVED_199[48]; + __IO uint32_t ACCESS_CTRL98; /**< Access Control Register, offset: 0xB170 */ + __IO uint32_t ACCESS_CTRL98_ROOT_SET; /**< Access Control Register, offset: 0xB174 */ + __IO uint32_t ACCESS_CTRL98_ROOT_CLR; /**< Access Control Register, offset: 0xB178 */ + __IO uint32_t ACCESS_CTRL98_ROOT_TOG; /**< Access Control Register, offset: 0xB17C */ + __IO uint32_t TARGET_ROOT99; /**< Target Register, offset: 0xB180 */ + __IO uint32_t TARGET_ROOT99_SET; /**< Target Register, offset: 0xB184 */ + __IO uint32_t TARGET_ROOT99_CLR; /**< Target Register, offset: 0xB188 */ + __IO uint32_t TARGET_ROOT99_TOG; /**< Target Register, offset: 0xB18C */ + uint8_t RESERVED_200[16]; + __IO uint32_t POST99; /**< Post Divider Register, offset: 0xB1A0 */ + __IO uint32_t POST_ROOT99_SET; /**< Post Divider Register, offset: 0xB1A4 */ + __IO uint32_t POST_ROOT99_CLR; /**< Post Divider Register, offset: 0xB1A8 */ + __IO uint32_t POST_ROOT99_TOG; /**< Post Divider Register, offset: 0xB1AC */ + __IO uint32_t PRE99; /**< Pre Divider Register, offset: 0xB1B0 */ + __IO uint32_t PRE_ROOT99_SET; /**< Pre Divider Register, offset: 0xB1B4 */ + __IO uint32_t PRE_ROOT99_CLR; /**< Pre Divider Register, offset: 0xB1B8 */ + __IO uint32_t PRE_ROOT99_TOG; /**< Pre Divider Register, offset: 0xB1BC */ + uint8_t RESERVED_201[48]; + __IO uint32_t ACCESS_CTRL99; /**< Access Control Register, offset: 0xB1F0 */ + __IO uint32_t ACCESS_CTRL99_ROOT_SET; /**< Access Control Register, offset: 0xB1F4 */ + __IO uint32_t ACCESS_CTRL99_ROOT_CLR; /**< Access Control Register, offset: 0xB1F8 */ + __IO uint32_t ACCESS_CTRL99_ROOT_TOG; /**< Access Control Register, offset: 0xB1FC */ + __IO uint32_t TARGET_ROOT100; /**< Target Register, offset: 0xB200 */ + __IO uint32_t TARGET_ROOT100_SET; /**< Target Register, offset: 0xB204 */ + __IO uint32_t TARGET_ROOT100_CLR; /**< Target Register, offset: 0xB208 */ + __IO uint32_t TARGET_ROOT100_TOG; /**< Target Register, offset: 0xB20C */ + uint8_t RESERVED_202[16]; + __IO uint32_t POST100; /**< Post Divider Register, offset: 0xB220 */ + __IO uint32_t POST_ROOT100_SET; /**< Post Divider Register, offset: 0xB224 */ + __IO uint32_t POST_ROOT100_CLR; /**< Post Divider Register, offset: 0xB228 */ + __IO uint32_t POST_ROOT100_TOG; /**< Post Divider Register, offset: 0xB22C */ + __IO uint32_t PRE100; /**< Pre Divider Register, offset: 0xB230 */ + __IO uint32_t PRE_ROOT100_SET; /**< Pre Divider Register, offset: 0xB234 */ + __IO uint32_t PRE_ROOT100_CLR; /**< Pre Divider Register, offset: 0xB238 */ + __IO uint32_t PRE_ROOT100_TOG; /**< Pre Divider Register, offset: 0xB23C */ + uint8_t RESERVED_203[48]; + __IO uint32_t ACCESS_CTRL100; /**< Access Control Register, offset: 0xB270 */ + __IO uint32_t ACCESS_CTRL100_ROOT_SET; /**< Access Control Register, offset: 0xB274 */ + __IO uint32_t ACCESS_CTRL100_ROOT_CLR; /**< Access Control Register, offset: 0xB278 */ + __IO uint32_t ACCESS_CTRL100_ROOT_TOG; /**< Access Control Register, offset: 0xB27C */ + __IO uint32_t TARGET_ROOT101; /**< Target Register, offset: 0xB280 */ + __IO uint32_t TARGET_ROOT101_SET; /**< Target Register, offset: 0xB284 */ + __IO uint32_t TARGET_ROOT101_CLR; /**< Target Register, offset: 0xB288 */ + __IO uint32_t TARGET_ROOT101_TOG; /**< Target Register, offset: 0xB28C */ + uint8_t RESERVED_204[16]; + __IO uint32_t POST101; /**< Post Divider Register, offset: 0xB2A0 */ + __IO uint32_t POST_ROOT101_SET; /**< Post Divider Register, offset: 0xB2A4 */ + __IO uint32_t POST_ROOT101_CLR; /**< Post Divider Register, offset: 0xB2A8 */ + __IO uint32_t POST_ROOT101_TOG; /**< Post Divider Register, offset: 0xB2AC */ + __IO uint32_t PRE101; /**< Pre Divider Register, offset: 0xB2B0 */ + __IO uint32_t PRE_ROOT101_SET; /**< Pre Divider Register, offset: 0xB2B4 */ + __IO uint32_t PRE_ROOT101_CLR; /**< Pre Divider Register, offset: 0xB2B8 */ + __IO uint32_t PRE_ROOT101_TOG; /**< Pre Divider Register, offset: 0xB2BC */ + uint8_t RESERVED_205[48]; + __IO uint32_t ACCESS_CTRL101; /**< Access Control Register, offset: 0xB2F0 */ + __IO uint32_t ACCESS_CTRL101_ROOT_SET; /**< Access Control Register, offset: 0xB2F4 */ + __IO uint32_t ACCESS_CTRL101_ROOT_CLR; /**< Access Control Register, offset: 0xB2F8 */ + __IO uint32_t ACCESS_CTRL101_ROOT_TOG; /**< Access Control Register, offset: 0xB2FC */ + __IO uint32_t TARGET_ROOT102; /**< Target Register, offset: 0xB300 */ + __IO uint32_t TARGET_ROOT102_SET; /**< Target Register, offset: 0xB304 */ + __IO uint32_t TARGET_ROOT102_CLR; /**< Target Register, offset: 0xB308 */ + __IO uint32_t TARGET_ROOT102_TOG; /**< Target Register, offset: 0xB30C */ + uint8_t RESERVED_206[16]; + __IO uint32_t POST102; /**< Post Divider Register, offset: 0xB320 */ + __IO uint32_t POST_ROOT102_SET; /**< Post Divider Register, offset: 0xB324 */ + __IO uint32_t POST_ROOT102_CLR; /**< Post Divider Register, offset: 0xB328 */ + __IO uint32_t POST_ROOT102_TOG; /**< Post Divider Register, offset: 0xB32C */ + __IO uint32_t PRE102; /**< Pre Divider Register, offset: 0xB330 */ + __IO uint32_t PRE_ROOT102_SET; /**< Pre Divider Register, offset: 0xB334 */ + __IO uint32_t PRE_ROOT102_CLR; /**< Pre Divider Register, offset: 0xB338 */ + __IO uint32_t PRE_ROOT102_TOG; /**< Pre Divider Register, offset: 0xB33C */ + uint8_t RESERVED_207[48]; + __IO uint32_t ACCESS_CTRL102; /**< Access Control Register, offset: 0xB370 */ + __IO uint32_t ACCESS_CTRL102_ROOT_SET; /**< Access Control Register, offset: 0xB374 */ + __IO uint32_t ACCESS_CTRL102_ROOT_CLR; /**< Access Control Register, offset: 0xB378 */ + __IO uint32_t ACCESS_CTRL102_ROOT_TOG; /**< Access Control Register, offset: 0xB37C */ + __IO uint32_t TARGET_ROOT103; /**< Target Register, offset: 0xB380 */ + __IO uint32_t TARGET_ROOT103_SET; /**< Target Register, offset: 0xB384 */ + __IO uint32_t TARGET_ROOT103_CLR; /**< Target Register, offset: 0xB388 */ + __IO uint32_t TARGET_ROOT103_TOG; /**< Target Register, offset: 0xB38C */ + uint8_t RESERVED_208[16]; + __IO uint32_t POST103; /**< Post Divider Register, offset: 0xB3A0 */ + __IO uint32_t POST_ROOT103_SET; /**< Post Divider Register, offset: 0xB3A4 */ + __IO uint32_t POST_ROOT103_CLR; /**< Post Divider Register, offset: 0xB3A8 */ + __IO uint32_t POST_ROOT103_TOG; /**< Post Divider Register, offset: 0xB3AC */ + __IO uint32_t PRE103; /**< Pre Divider Register, offset: 0xB3B0 */ + __IO uint32_t PRE_ROOT103_SET; /**< Pre Divider Register, offset: 0xB3B4 */ + __IO uint32_t PRE_ROOT103_CLR; /**< Pre Divider Register, offset: 0xB3B8 */ + __IO uint32_t PRE_ROOT103_TOG; /**< Pre Divider Register, offset: 0xB3BC */ + uint8_t RESERVED_209[48]; + __IO uint32_t ACCESS_CTRL103; /**< Access Control Register, offset: 0xB3F0 */ + __IO uint32_t ACCESS_CTRL103_ROOT_SET; /**< Access Control Register, offset: 0xB3F4 */ + __IO uint32_t ACCESS_CTRL103_ROOT_CLR; /**< Access Control Register, offset: 0xB3F8 */ + __IO uint32_t ACCESS_CTRL103_ROOT_TOG; /**< Access Control Register, offset: 0xB3FC */ + __IO uint32_t TARGET_ROOT104; /**< Target Register, offset: 0xB400 */ + __IO uint32_t TARGET_ROOT104_SET; /**< Target Register, offset: 0xB404 */ + __IO uint32_t TARGET_ROOT104_CLR; /**< Target Register, offset: 0xB408 */ + __IO uint32_t TARGET_ROOT104_TOG; /**< Target Register, offset: 0xB40C */ + uint8_t RESERVED_210[16]; + __IO uint32_t POST104; /**< Post Divider Register, offset: 0xB420 */ + __IO uint32_t POST_ROOT104_SET; /**< Post Divider Register, offset: 0xB424 */ + __IO uint32_t POST_ROOT104_CLR; /**< Post Divider Register, offset: 0xB428 */ + __IO uint32_t POST_ROOT104_TOG; /**< Post Divider Register, offset: 0xB42C */ + __IO uint32_t PRE104; /**< Pre Divider Register, offset: 0xB430 */ + __IO uint32_t PRE_ROOT104_SET; /**< Pre Divider Register, offset: 0xB434 */ + __IO uint32_t PRE_ROOT104_CLR; /**< Pre Divider Register, offset: 0xB438 */ + __IO uint32_t PRE_ROOT104_TOG; /**< Pre Divider Register, offset: 0xB43C */ + uint8_t RESERVED_211[48]; + __IO uint32_t ACCESS_CTRL104; /**< Access Control Register, offset: 0xB470 */ + __IO uint32_t ACCESS_CTRL104_ROOT_SET; /**< Access Control Register, offset: 0xB474 */ + __IO uint32_t ACCESS_CTRL104_ROOT_CLR; /**< Access Control Register, offset: 0xB478 */ + __IO uint32_t ACCESS_CTRL104_ROOT_TOG; /**< Access Control Register, offset: 0xB47C */ + __IO uint32_t TARGET_ROOT105; /**< Target Register, offset: 0xB480 */ + __IO uint32_t TARGET_ROOT105_SET; /**< Target Register, offset: 0xB484 */ + __IO uint32_t TARGET_ROOT105_CLR; /**< Target Register, offset: 0xB488 */ + __IO uint32_t TARGET_ROOT105_TOG; /**< Target Register, offset: 0xB48C */ + uint8_t RESERVED_212[16]; + __IO uint32_t POST105; /**< Post Divider Register, offset: 0xB4A0 */ + __IO uint32_t POST_ROOT105_SET; /**< Post Divider Register, offset: 0xB4A4 */ + __IO uint32_t POST_ROOT105_CLR; /**< Post Divider Register, offset: 0xB4A8 */ + __IO uint32_t POST_ROOT105_TOG; /**< Post Divider Register, offset: 0xB4AC */ + __IO uint32_t PRE105; /**< Pre Divider Register, offset: 0xB4B0 */ + __IO uint32_t PRE_ROOT105_SET; /**< Pre Divider Register, offset: 0xB4B4 */ + __IO uint32_t PRE_ROOT105_CLR; /**< Pre Divider Register, offset: 0xB4B8 */ + __IO uint32_t PRE_ROOT105_TOG; /**< Pre Divider Register, offset: 0xB4BC */ + uint8_t RESERVED_213[48]; + __IO uint32_t ACCESS_CTRL105; /**< Access Control Register, offset: 0xB4F0 */ + __IO uint32_t ACCESS_CTRL105_ROOT_SET; /**< Access Control Register, offset: 0xB4F4 */ + __IO uint32_t ACCESS_CTRL105_ROOT_CLR; /**< Access Control Register, offset: 0xB4F8 */ + __IO uint32_t ACCESS_CTRL105_ROOT_TOG; /**< Access Control Register, offset: 0xB4FC */ + __IO uint32_t TARGET_ROOT106; /**< Target Register, offset: 0xB500 */ + __IO uint32_t TARGET_ROOT106_SET; /**< Target Register, offset: 0xB504 */ + __IO uint32_t TARGET_ROOT106_CLR; /**< Target Register, offset: 0xB508 */ + __IO uint32_t TARGET_ROOT106_TOG; /**< Target Register, offset: 0xB50C */ + uint8_t RESERVED_214[16]; + __IO uint32_t POST106; /**< Post Divider Register, offset: 0xB520 */ + __IO uint32_t POST_ROOT106_SET; /**< Post Divider Register, offset: 0xB524 */ + __IO uint32_t POST_ROOT106_CLR; /**< Post Divider Register, offset: 0xB528 */ + __IO uint32_t POST_ROOT106_TOG; /**< Post Divider Register, offset: 0xB52C */ + __IO uint32_t PRE106; /**< Pre Divider Register, offset: 0xB530 */ + __IO uint32_t PRE_ROOT106_SET; /**< Pre Divider Register, offset: 0xB534 */ + __IO uint32_t PRE_ROOT106_CLR; /**< Pre Divider Register, offset: 0xB538 */ + __IO uint32_t PRE_ROOT106_TOG; /**< Pre Divider Register, offset: 0xB53C */ + uint8_t RESERVED_215[48]; + __IO uint32_t ACCESS_CTRL106; /**< Access Control Register, offset: 0xB570 */ + __IO uint32_t ACCESS_CTRL106_ROOT_SET; /**< Access Control Register, offset: 0xB574 */ + __IO uint32_t ACCESS_CTRL106_ROOT_CLR; /**< Access Control Register, offset: 0xB578 */ + __IO uint32_t ACCESS_CTRL106_ROOT_TOG; /**< Access Control Register, offset: 0xB57C */ + __IO uint32_t TARGET_ROOT107; /**< Target Register, offset: 0xB580 */ + __IO uint32_t TARGET_ROOT107_SET; /**< Target Register, offset: 0xB584 */ + __IO uint32_t TARGET_ROOT107_CLR; /**< Target Register, offset: 0xB588 */ + __IO uint32_t TARGET_ROOT107_TOG; /**< Target Register, offset: 0xB58C */ + uint8_t RESERVED_216[16]; + __IO uint32_t POST107; /**< Post Divider Register, offset: 0xB5A0 */ + __IO uint32_t POST_ROOT107_SET; /**< Post Divider Register, offset: 0xB5A4 */ + __IO uint32_t POST_ROOT107_CLR; /**< Post Divider Register, offset: 0xB5A8 */ + __IO uint32_t POST_ROOT107_TOG; /**< Post Divider Register, offset: 0xB5AC */ + __IO uint32_t PRE107; /**< Pre Divider Register, offset: 0xB5B0 */ + __IO uint32_t PRE_ROOT107_SET; /**< Pre Divider Register, offset: 0xB5B4 */ + __IO uint32_t PRE_ROOT107_CLR; /**< Pre Divider Register, offset: 0xB5B8 */ + __IO uint32_t PRE_ROOT107_TOG; /**< Pre Divider Register, offset: 0xB5BC */ + uint8_t RESERVED_217[48]; + __IO uint32_t ACCESS_CTRL107; /**< Access Control Register, offset: 0xB5F0 */ + __IO uint32_t ACCESS_CTRL107_ROOT_SET; /**< Access Control Register, offset: 0xB5F4 */ + __IO uint32_t ACCESS_CTRL107_ROOT_CLR; /**< Access Control Register, offset: 0xB5F8 */ + __IO uint32_t ACCESS_CTRL107_ROOT_TOG; /**< Access Control Register, offset: 0xB5FC */ + __IO uint32_t TARGET_ROOT108; /**< Target Register, offset: 0xB600 */ + __IO uint32_t TARGET_ROOT108_SET; /**< Target Register, offset: 0xB604 */ + __IO uint32_t TARGET_ROOT108_CLR; /**< Target Register, offset: 0xB608 */ + __IO uint32_t TARGET_ROOT108_TOG; /**< Target Register, offset: 0xB60C */ + uint8_t RESERVED_218[16]; + __IO uint32_t POST108; /**< Post Divider Register, offset: 0xB620 */ + __IO uint32_t POST_ROOT108_SET; /**< Post Divider Register, offset: 0xB624 */ + __IO uint32_t POST_ROOT108_CLR; /**< Post Divider Register, offset: 0xB628 */ + __IO uint32_t POST_ROOT108_TOG; /**< Post Divider Register, offset: 0xB62C */ + __IO uint32_t PRE108; /**< Pre Divider Register, offset: 0xB630 */ + __IO uint32_t PRE_ROOT108_SET; /**< Pre Divider Register, offset: 0xB634 */ + __IO uint32_t PRE_ROOT108_CLR; /**< Pre Divider Register, offset: 0xB638 */ + __IO uint32_t PRE_ROOT108_TOG; /**< Pre Divider Register, offset: 0xB63C */ + uint8_t RESERVED_219[48]; + __IO uint32_t ACCESS_CTRL108; /**< Access Control Register, offset: 0xB670 */ + __IO uint32_t ACCESS_CTRL108_ROOT_SET; /**< Access Control Register, offset: 0xB674 */ + __IO uint32_t ACCESS_CTRL108_ROOT_CLR; /**< Access Control Register, offset: 0xB678 */ + __IO uint32_t ACCESS_CTRL108_ROOT_TOG; /**< Access Control Register, offset: 0xB67C */ + __IO uint32_t TARGET_ROOT109; /**< Target Register, offset: 0xB680 */ + __IO uint32_t TARGET_ROOT109_SET; /**< Target Register, offset: 0xB684 */ + __IO uint32_t TARGET_ROOT109_CLR; /**< Target Register, offset: 0xB688 */ + __IO uint32_t TARGET_ROOT109_TOG; /**< Target Register, offset: 0xB68C */ + uint8_t RESERVED_220[16]; + __IO uint32_t POST109; /**< Post Divider Register, offset: 0xB6A0 */ + __IO uint32_t POST_ROOT109_SET; /**< Post Divider Register, offset: 0xB6A4 */ + __IO uint32_t POST_ROOT109_CLR; /**< Post Divider Register, offset: 0xB6A8 */ + __IO uint32_t POST_ROOT109_TOG; /**< Post Divider Register, offset: 0xB6AC */ + __IO uint32_t PRE109; /**< Pre Divider Register, offset: 0xB6B0 */ + __IO uint32_t PRE_ROOT109_SET; /**< Pre Divider Register, offset: 0xB6B4 */ + __IO uint32_t PRE_ROOT109_CLR; /**< Pre Divider Register, offset: 0xB6B8 */ + __IO uint32_t PRE_ROOT109_TOG; /**< Pre Divider Register, offset: 0xB6BC */ + uint8_t RESERVED_221[48]; + __IO uint32_t ACCESS_CTRL109; /**< Access Control Register, offset: 0xB6F0 */ + __IO uint32_t ACCESS_CTRL109_ROOT_SET; /**< Access Control Register, offset: 0xB6F4 */ + __IO uint32_t ACCESS_CTRL109_ROOT_CLR; /**< Access Control Register, offset: 0xB6F8 */ + __IO uint32_t ACCESS_CTRL109_ROOT_TOG; /**< Access Control Register, offset: 0xB6FC */ + __IO uint32_t TARGET_ROOT110; /**< Target Register, offset: 0xB700 */ + __IO uint32_t TARGET_ROOT110_SET; /**< Target Register, offset: 0xB704 */ + __IO uint32_t TARGET_ROOT110_CLR; /**< Target Register, offset: 0xB708 */ + __IO uint32_t TARGET_ROOT110_TOG; /**< Target Register, offset: 0xB70C */ + uint8_t RESERVED_222[16]; + __IO uint32_t POST110; /**< Post Divider Register, offset: 0xB720 */ + __IO uint32_t POST_ROOT110_SET; /**< Post Divider Register, offset: 0xB724 */ + __IO uint32_t POST_ROOT110_CLR; /**< Post Divider Register, offset: 0xB728 */ + __IO uint32_t POST_ROOT110_TOG; /**< Post Divider Register, offset: 0xB72C */ + __IO uint32_t PRE110; /**< Pre Divider Register, offset: 0xB730 */ + __IO uint32_t PRE_ROOT110_SET; /**< Pre Divider Register, offset: 0xB734 */ + __IO uint32_t PRE_ROOT110_CLR; /**< Pre Divider Register, offset: 0xB738 */ + __IO uint32_t PRE_ROOT110_TOG; /**< Pre Divider Register, offset: 0xB73C */ + uint8_t RESERVED_223[48]; + __IO uint32_t ACCESS_CTRL110; /**< Access Control Register, offset: 0xB770 */ + __IO uint32_t ACCESS_CTRL110_ROOT_SET; /**< Access Control Register, offset: 0xB774 */ + __IO uint32_t ACCESS_CTRL110_ROOT_CLR; /**< Access Control Register, offset: 0xB778 */ + __IO uint32_t ACCESS_CTRL110_ROOT_TOG; /**< Access Control Register, offset: 0xB77C */ + __IO uint32_t TARGET_ROOT111; /**< Target Register, offset: 0xB780 */ + __IO uint32_t TARGET_ROOT111_SET; /**< Target Register, offset: 0xB784 */ + __IO uint32_t TARGET_ROOT111_CLR; /**< Target Register, offset: 0xB788 */ + __IO uint32_t TARGET_ROOT111_TOG; /**< Target Register, offset: 0xB78C */ + uint8_t RESERVED_224[16]; + __IO uint32_t POST111; /**< Post Divider Register, offset: 0xB7A0 */ + __IO uint32_t POST_ROOT111_SET; /**< Post Divider Register, offset: 0xB7A4 */ + __IO uint32_t POST_ROOT111_CLR; /**< Post Divider Register, offset: 0xB7A8 */ + __IO uint32_t POST_ROOT111_TOG; /**< Post Divider Register, offset: 0xB7AC */ + __IO uint32_t PRE111; /**< Pre Divider Register, offset: 0xB7B0 */ + __IO uint32_t PRE_ROOT111_SET; /**< Pre Divider Register, offset: 0xB7B4 */ + __IO uint32_t PRE_ROOT111_CLR; /**< Pre Divider Register, offset: 0xB7B8 */ + __IO uint32_t PRE_ROOT111_TOG; /**< Pre Divider Register, offset: 0xB7BC */ + uint8_t RESERVED_225[48]; + __IO uint32_t ACCESS_CTRL111; /**< Access Control Register, offset: 0xB7F0 */ + __IO uint32_t ACCESS_CTRL111_ROOT_SET; /**< Access Control Register, offset: 0xB7F4 */ + __IO uint32_t ACCESS_CTRL111_ROOT_CLR; /**< Access Control Register, offset: 0xB7F8 */ + __IO uint32_t ACCESS_CTRL111_ROOT_TOG; /**< Access Control Register, offset: 0xB7FC */ + __IO uint32_t TARGET_ROOT112; /**< Target Register, offset: 0xB800 */ + __IO uint32_t TARGET_ROOT112_SET; /**< Target Register, offset: 0xB804 */ + __IO uint32_t TARGET_ROOT112_CLR; /**< Target Register, offset: 0xB808 */ + __IO uint32_t TARGET_ROOT112_TOG; /**< Target Register, offset: 0xB80C */ + uint8_t RESERVED_226[16]; + __IO uint32_t POST112; /**< Post Divider Register, offset: 0xB820 */ + __IO uint32_t POST_ROOT112_SET; /**< Post Divider Register, offset: 0xB824 */ + __IO uint32_t POST_ROOT112_CLR; /**< Post Divider Register, offset: 0xB828 */ + __IO uint32_t POST_ROOT112_TOG; /**< Post Divider Register, offset: 0xB82C */ + __IO uint32_t PRE112; /**< Pre Divider Register, offset: 0xB830 */ + __IO uint32_t PRE_ROOT112_SET; /**< Pre Divider Register, offset: 0xB834 */ + __IO uint32_t PRE_ROOT112_CLR; /**< Pre Divider Register, offset: 0xB838 */ + __IO uint32_t PRE_ROOT112_TOG; /**< Pre Divider Register, offset: 0xB83C */ + uint8_t RESERVED_227[48]; + __IO uint32_t ACCESS_CTRL112; /**< Access Control Register, offset: 0xB870 */ + __IO uint32_t ACCESS_CTRL112_ROOT_SET; /**< Access Control Register, offset: 0xB874 */ + __IO uint32_t ACCESS_CTRL112_ROOT_CLR; /**< Access Control Register, offset: 0xB878 */ + __IO uint32_t ACCESS_CTRL112_ROOT_TOG; /**< Access Control Register, offset: 0xB87C */ + __IO uint32_t TARGET_ROOT113; /**< Target Register, offset: 0xB880 */ + __IO uint32_t TARGET_ROOT113_SET; /**< Target Register, offset: 0xB884 */ + __IO uint32_t TARGET_ROOT113_CLR; /**< Target Register, offset: 0xB888 */ + __IO uint32_t TARGET_ROOT113_TOG; /**< Target Register, offset: 0xB88C */ + uint8_t RESERVED_228[16]; + __IO uint32_t POST113; /**< Post Divider Register, offset: 0xB8A0 */ + __IO uint32_t POST_ROOT113_SET; /**< Post Divider Register, offset: 0xB8A4 */ + __IO uint32_t POST_ROOT113_CLR; /**< Post Divider Register, offset: 0xB8A8 */ + __IO uint32_t POST_ROOT113_TOG; /**< Post Divider Register, offset: 0xB8AC */ + __IO uint32_t PRE113; /**< Pre Divider Register, offset: 0xB8B0 */ + __IO uint32_t PRE_ROOT113_SET; /**< Pre Divider Register, offset: 0xB8B4 */ + __IO uint32_t PRE_ROOT113_CLR; /**< Pre Divider Register, offset: 0xB8B8 */ + __IO uint32_t PRE_ROOT113_TOG; /**< Pre Divider Register, offset: 0xB8BC */ + uint8_t RESERVED_229[48]; + __IO uint32_t ACCESS_CTRL113; /**< Access Control Register, offset: 0xB8F0 */ + __IO uint32_t ACCESS_CTRL113_ROOT_SET; /**< Access Control Register, offset: 0xB8F4 */ + __IO uint32_t ACCESS_CTRL113_ROOT_CLR; /**< Access Control Register, offset: 0xB8F8 */ + __IO uint32_t ACCESS_CTRL113_ROOT_TOG; /**< Access Control Register, offset: 0xB8FC */ + __IO uint32_t TARGET_ROOT114; /**< Target Register, offset: 0xB900 */ + __IO uint32_t TARGET_ROOT114_SET; /**< Target Register, offset: 0xB904 */ + __IO uint32_t TARGET_ROOT114_CLR; /**< Target Register, offset: 0xB908 */ + __IO uint32_t TARGET_ROOT114_TOG; /**< Target Register, offset: 0xB90C */ + uint8_t RESERVED_230[16]; + __IO uint32_t POST114; /**< Post Divider Register, offset: 0xB920 */ + __IO uint32_t POST_ROOT114_SET; /**< Post Divider Register, offset: 0xB924 */ + __IO uint32_t POST_ROOT114_CLR; /**< Post Divider Register, offset: 0xB928 */ + __IO uint32_t POST_ROOT114_TOG; /**< Post Divider Register, offset: 0xB92C */ + __IO uint32_t PRE114; /**< Pre Divider Register, offset: 0xB930 */ + __IO uint32_t PRE_ROOT114_SET; /**< Pre Divider Register, offset: 0xB934 */ + __IO uint32_t PRE_ROOT114_CLR; /**< Pre Divider Register, offset: 0xB938 */ + __IO uint32_t PRE_ROOT114_TOG; /**< Pre Divider Register, offset: 0xB93C */ + uint8_t RESERVED_231[48]; + __IO uint32_t ACCESS_CTRL114; /**< Access Control Register, offset: 0xB970 */ + __IO uint32_t ACCESS_CTRL114_ROOT_SET; /**< Access Control Register, offset: 0xB974 */ + __IO uint32_t ACCESS_CTRL114_ROOT_CLR; /**< Access Control Register, offset: 0xB978 */ + __IO uint32_t ACCESS_CTRL114_ROOT_TOG; /**< Access Control Register, offset: 0xB97C */ + __IO uint32_t TARGET_ROOT115; /**< Target Register, offset: 0xB980 */ + __IO uint32_t TARGET_ROOT115_SET; /**< Target Register, offset: 0xB984 */ + __IO uint32_t TARGET_ROOT115_CLR; /**< Target Register, offset: 0xB988 */ + __IO uint32_t TARGET_ROOT115_TOG; /**< Target Register, offset: 0xB98C */ + uint8_t RESERVED_232[16]; + __IO uint32_t POST115; /**< Post Divider Register, offset: 0xB9A0 */ + __IO uint32_t POST_ROOT115_SET; /**< Post Divider Register, offset: 0xB9A4 */ + __IO uint32_t POST_ROOT115_CLR; /**< Post Divider Register, offset: 0xB9A8 */ + __IO uint32_t POST_ROOT115_TOG; /**< Post Divider Register, offset: 0xB9AC */ + __IO uint32_t PRE115; /**< Pre Divider Register, offset: 0xB9B0 */ + __IO uint32_t PRE_ROOT115_SET; /**< Pre Divider Register, offset: 0xB9B4 */ + __IO uint32_t PRE_ROOT115_CLR; /**< Pre Divider Register, offset: 0xB9B8 */ + __IO uint32_t PRE_ROOT115_TOG; /**< Pre Divider Register, offset: 0xB9BC */ + uint8_t RESERVED_233[48]; + __IO uint32_t ACCESS_CTRL115; /**< Access Control Register, offset: 0xB9F0 */ + __IO uint32_t ACCESS_CTRL115_ROOT_SET; /**< Access Control Register, offset: 0xB9F4 */ + __IO uint32_t ACCESS_CTRL115_ROOT_CLR; /**< Access Control Register, offset: 0xB9F8 */ + __IO uint32_t ACCESS_CTRL115_ROOT_TOG; /**< Access Control Register, offset: 0xB9FC */ + __IO uint32_t TARGET_ROOT116; /**< Target Register, offset: 0xBA00 */ + __IO uint32_t TARGET_ROOT116_SET; /**< Target Register, offset: 0xBA04 */ + __IO uint32_t TARGET_ROOT116_CLR; /**< Target Register, offset: 0xBA08 */ + __IO uint32_t TARGET_ROOT116_TOG; /**< Target Register, offset: 0xBA0C */ + uint8_t RESERVED_234[16]; + __IO uint32_t POST116; /**< Post Divider Register, offset: 0xBA20 */ + __IO uint32_t POST_ROOT116_SET; /**< Post Divider Register, offset: 0xBA24 */ + __IO uint32_t POST_ROOT116_CLR; /**< Post Divider Register, offset: 0xBA28 */ + __IO uint32_t POST_ROOT116_TOG; /**< Post Divider Register, offset: 0xBA2C */ + __IO uint32_t PRE116; /**< Pre Divider Register, offset: 0xBA30 */ + __IO uint32_t PRE_ROOT116_SET; /**< Pre Divider Register, offset: 0xBA34 */ + __IO uint32_t PRE_ROOT116_CLR; /**< Pre Divider Register, offset: 0xBA38 */ + __IO uint32_t PRE_ROOT116_TOG; /**< Pre Divider Register, offset: 0xBA3C */ + uint8_t RESERVED_235[48]; + __IO uint32_t ACCESS_CTRL116; /**< Access Control Register, offset: 0xBA70 */ + __IO uint32_t ACCESS_CTRL116_ROOT_SET; /**< Access Control Register, offset: 0xBA74 */ + __IO uint32_t ACCESS_CTRL116_ROOT_CLR; /**< Access Control Register, offset: 0xBA78 */ + __IO uint32_t ACCESS_CTRL116_ROOT_TOG; /**< Access Control Register, offset: 0xBA7C */ + __IO uint32_t TARGET_ROOT117; /**< Target Register, offset: 0xBA80 */ + __IO uint32_t TARGET_ROOT117_SET; /**< Target Register, offset: 0xBA84 */ + __IO uint32_t TARGET_ROOT117_CLR; /**< Target Register, offset: 0xBA88 */ + __IO uint32_t TARGET_ROOT117_TOG; /**< Target Register, offset: 0xBA8C */ + uint8_t RESERVED_236[16]; + __IO uint32_t POST117; /**< Post Divider Register, offset: 0xBAA0 */ + __IO uint32_t POST_ROOT117_SET; /**< Post Divider Register, offset: 0xBAA4 */ + __IO uint32_t POST_ROOT117_CLR; /**< Post Divider Register, offset: 0xBAA8 */ + __IO uint32_t POST_ROOT117_TOG; /**< Post Divider Register, offset: 0xBAAC */ + __IO uint32_t PRE117; /**< Pre Divider Register, offset: 0xBAB0 */ + __IO uint32_t PRE_ROOT117_SET; /**< Pre Divider Register, offset: 0xBAB4 */ + __IO uint32_t PRE_ROOT117_CLR; /**< Pre Divider Register, offset: 0xBAB8 */ + __IO uint32_t PRE_ROOT117_TOG; /**< Pre Divider Register, offset: 0xBABC */ + uint8_t RESERVED_237[48]; + __IO uint32_t ACCESS_CTRL117; /**< Access Control Register, offset: 0xBAF0 */ + __IO uint32_t ACCESS_CTRL117_ROOT_SET; /**< Access Control Register, offset: 0xBAF4 */ + __IO uint32_t ACCESS_CTRL117_ROOT_CLR; /**< Access Control Register, offset: 0xBAF8 */ + __IO uint32_t ACCESS_CTRL117_ROOT_TOG; /**< Access Control Register, offset: 0xBAFC */ + __IO uint32_t TARGET_ROOT118; /**< Target Register, offset: 0xBB00 */ + __IO uint32_t TARGET_ROOT118_SET; /**< Target Register, offset: 0xBB04 */ + __IO uint32_t TARGET_ROOT118_CLR; /**< Target Register, offset: 0xBB08 */ + __IO uint32_t TARGET_ROOT118_TOG; /**< Target Register, offset: 0xBB0C */ + uint8_t RESERVED_238[16]; + __IO uint32_t POST118; /**< Post Divider Register, offset: 0xBB20 */ + __IO uint32_t POST_ROOT118_SET; /**< Post Divider Register, offset: 0xBB24 */ + __IO uint32_t POST_ROOT118_CLR; /**< Post Divider Register, offset: 0xBB28 */ + __IO uint32_t POST_ROOT118_TOG; /**< Post Divider Register, offset: 0xBB2C */ + __IO uint32_t PRE118; /**< Pre Divider Register, offset: 0xBB30 */ + __IO uint32_t PRE_ROOT118_SET; /**< Pre Divider Register, offset: 0xBB34 */ + __IO uint32_t PRE_ROOT118_CLR; /**< Pre Divider Register, offset: 0xBB38 */ + __IO uint32_t PRE_ROOT118_TOG; /**< Pre Divider Register, offset: 0xBB3C */ + uint8_t RESERVED_239[48]; + __IO uint32_t ACCESS_CTRL118; /**< Access Control Register, offset: 0xBB70 */ + __IO uint32_t ACCESS_CTRL118_ROOT_SET; /**< Access Control Register, offset: 0xBB74 */ + __IO uint32_t ACCESS_CTRL118_ROOT_CLR; /**< Access Control Register, offset: 0xBB78 */ + __IO uint32_t ACCESS_CTRL118_ROOT_TOG; /**< Access Control Register, offset: 0xBB7C */ + __IO uint32_t TARGET_ROOT119; /**< Target Register, offset: 0xBB80 */ + __IO uint32_t TARGET_ROOT119_SET; /**< Target Register, offset: 0xBB84 */ + __IO uint32_t TARGET_ROOT119_CLR; /**< Target Register, offset: 0xBB88 */ + __IO uint32_t TARGET_ROOT119_TOG; /**< Target Register, offset: 0xBB8C */ + uint8_t RESERVED_240[16]; + __IO uint32_t POST119; /**< Post Divider Register, offset: 0xBBA0 */ + __IO uint32_t POST_ROOT119_SET; /**< Post Divider Register, offset: 0xBBA4 */ + __IO uint32_t POST_ROOT119_CLR; /**< Post Divider Register, offset: 0xBBA8 */ + __IO uint32_t POST_ROOT119_TOG; /**< Post Divider Register, offset: 0xBBAC */ + __IO uint32_t PRE119; /**< Pre Divider Register, offset: 0xBBB0 */ + __IO uint32_t PRE_ROOT119_SET; /**< Pre Divider Register, offset: 0xBBB4 */ + __IO uint32_t PRE_ROOT119_CLR; /**< Pre Divider Register, offset: 0xBBB8 */ + __IO uint32_t PRE_ROOT119_TOG; /**< Pre Divider Register, offset: 0xBBBC */ + uint8_t RESERVED_241[48]; + __IO uint32_t ACCESS_CTRL119; /**< Access Control Register, offset: 0xBBF0 */ + __IO uint32_t ACCESS_CTRL119_ROOT_SET; /**< Access Control Register, offset: 0xBBF4 */ + __IO uint32_t ACCESS_CTRL119_ROOT_CLR; /**< Access Control Register, offset: 0xBBF8 */ + __IO uint32_t ACCESS_CTRL119_ROOT_TOG; /**< Access Control Register, offset: 0xBBFC */ + __IO uint32_t TARGET_ROOT120; /**< Target Register, offset: 0xBC00 */ + __IO uint32_t TARGET_ROOT120_SET; /**< Target Register, offset: 0xBC04 */ + __IO uint32_t TARGET_ROOT120_CLR; /**< Target Register, offset: 0xBC08 */ + __IO uint32_t TARGET_ROOT120_TOG; /**< Target Register, offset: 0xBC0C */ + uint8_t RESERVED_242[16]; + __IO uint32_t POST120; /**< Post Divider Register, offset: 0xBC20 */ + __IO uint32_t POST_ROOT120_SET; /**< Post Divider Register, offset: 0xBC24 */ + __IO uint32_t POST_ROOT120_CLR; /**< Post Divider Register, offset: 0xBC28 */ + __IO uint32_t POST_ROOT120_TOG; /**< Post Divider Register, offset: 0xBC2C */ + __IO uint32_t PRE120; /**< Pre Divider Register, offset: 0xBC30 */ + __IO uint32_t PRE_ROOT120_SET; /**< Pre Divider Register, offset: 0xBC34 */ + __IO uint32_t PRE_ROOT120_CLR; /**< Pre Divider Register, offset: 0xBC38 */ + __IO uint32_t PRE_ROOT120_TOG; /**< Pre Divider Register, offset: 0xBC3C */ + uint8_t RESERVED_243[48]; + __IO uint32_t ACCESS_CTRL120; /**< Access Control Register, offset: 0xBC70 */ + __IO uint32_t ACCESS_CTRL120_ROOT_SET; /**< Access Control Register, offset: 0xBC74 */ + __IO uint32_t ACCESS_CTRL120_ROOT_CLR; /**< Access Control Register, offset: 0xBC78 */ + __IO uint32_t ACCESS_CTRL120_ROOT_TOG; /**< Access Control Register, offset: 0xBC7C */ +} CCM_Type, *CCM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- CCM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros + * @{ + */ + + +/* CCM - Register accessors */ +#define CCM_GPR0_REG(base) ((base)->GPR0) +#define CCM_GPR0_SET_REG(base) ((base)->GPR0_SET) +#define CCM_GPR0_CLR_REG(base) ((base)->GPR0_CLR) +#define CCM_GPR0_TOG_REG(base) ((base)->GPR0_TOG) +#define CCM_PLL_CTRL0_REG(base) ((base)->PLL_CTRL0) +#define CCM_PLL_CTRL0_SET_REG(base) ((base)->PLL_CTRL0_SET) +#define CCM_PLL_CTRL0_CLR_REG(base) ((base)->PLL_CTRL0_CLR) +#define CCM_PLL_CTRL0_TOG_REG(base) ((base)->PLL_CTRL0_TOG) +#define CCM_PLL_CTRL1_REG(base) ((base)->PLL_CTRL1) +#define CCM_PLL_CTRL1_SET_REG(base) ((base)->PLL_CTRL1_SET) +#define CCM_PLL_CTRL1_CLR_REG(base) ((base)->PLL_CTRL1_CLR) +#define CCM_PLL_CTRL1_TOG_REG(base) ((base)->PLL_CTRL1_TOG) +#define CCM_PLL_CTRL2_REG(base) ((base)->PLL_CTRL2) +#define CCM_PLL_CTRL2_SET_REG(base) ((base)->PLL_CTRL2_SET) +#define CCM_PLL_CTRL2_CLR_REG(base) ((base)->PLL_CTRL2_CLR) +#define CCM_PLL_CTRL2_TOG_REG(base) ((base)->PLL_CTRL2_TOG) +#define CCM_PLL_CTRL3_REG(base) ((base)->PLL_CTRL3) +#define CCM_PLL_CTRL3_SET_REG(base) ((base)->PLL_CTRL3_SET) +#define CCM_PLL_CTRL3_CLR_REG(base) ((base)->PLL_CTRL3_CLR) +#define CCM_PLL_CTRL3_TOG_REG(base) ((base)->PLL_CTRL3_TOG) +#define CCM_PLL_CTRL4_REG(base) ((base)->PLL_CTRL4) +#define CCM_PLL_CTRL4_SET_REG(base) ((base)->PLL_CTRL4_SET) +#define CCM_PLL_CTRL4_CLR_REG(base) ((base)->PLL_CTRL4_CLR) +#define CCM_PLL_CTRL4_TOG_REG(base) ((base)->PLL_CTRL4_TOG) +#define CCM_PLL_CTRL5_REG(base) ((base)->PLL_CTRL5) +#define CCM_PLL_CTRL5_SET_REG(base) ((base)->PLL_CTRL5_SET) +#define CCM_PLL_CTRL5_CLR_REG(base) ((base)->PLL_CTRL5_CLR) +#define CCM_PLL_CTRL5_TOG_REG(base) ((base)->PLL_CTRL5_TOG) +#define CCM_PLL_CTRL6_REG(base) ((base)->PLL_CTRL6) +#define CCM_PLL_CTRL6_SET_REG(base) ((base)->PLL_CTRL6_SET) +#define CCM_PLL_CTRL6_CLR_REG(base) ((base)->PLL_CTRL6_CLR) +#define CCM_PLL_CTRL6_TOG_REG(base) ((base)->PLL_CTRL6_TOG) +#define CCM_PLL_CTRL7_REG(base) ((base)->PLL_CTRL7) +#define CCM_PLL_CTRL7_SET_REG(base) ((base)->PLL_CTRL7_SET) +#define CCM_PLL_CTRL7_CLR_REG(base) ((base)->PLL_CTRL7_CLR) +#define CCM_PLL_CTRL7_TOG_REG(base) ((base)->PLL_CTRL7_TOG) +#define CCM_PLL_CTRL8_REG(base) ((base)->PLL_CTRL8) +#define CCM_PLL_CTRL8_SET_REG(base) ((base)->PLL_CTRL8_SET) +#define CCM_PLL_CTRL8_CLR_REG(base) ((base)->PLL_CTRL8_CLR) +#define CCM_PLL_CTRL8_TOG_REG(base) ((base)->PLL_CTRL8_TOG) +#define CCM_PLL_CTRL9_REG(base) ((base)->PLL_CTRL9) +#define CCM_PLL_CTRL9_SET_REG(base) ((base)->PLL_CTRL9_SET) +#define CCM_PLL_CTRL9_CLR_REG(base) ((base)->PLL_CTRL9_CLR) +#define CCM_PLL_CTRL9_TOG_REG(base) ((base)->PLL_CTRL9_TOG) +#define CCM_PLL_CTRL10_REG(base) ((base)->PLL_CTRL10) +#define CCM_PLL_CTRL10_SET_REG(base) ((base)->PLL_CTRL10_SET) +#define CCM_PLL_CTRL10_CLR_REG(base) ((base)->PLL_CTRL10_CLR) +#define CCM_PLL_CTRL10_TOG_REG(base) ((base)->PLL_CTRL10_TOG) +#define CCM_PLL_CTRL11_REG(base) ((base)->PLL_CTRL11) +#define CCM_PLL_CTRL11_SET_REG(base) ((base)->PLL_CTRL11_SET) +#define CCM_PLL_CTRL11_CLR_REG(base) ((base)->PLL_CTRL11_CLR) +#define CCM_PLL_CTRL11_TOG_REG(base) ((base)->PLL_CTRL11_TOG) +#define CCM_PLL_CTRL12_REG(base) ((base)->PLL_CTRL12) +#define CCM_PLL_CTRL12_SET_REG(base) ((base)->PLL_CTRL12_SET) +#define CCM_PLL_CTRL12_CLR_REG(base) ((base)->PLL_CTRL12_CLR) +#define CCM_PLL_CTRL12_TOG_REG(base) ((base)->PLL_CTRL12_TOG) +#define CCM_PLL_CTRL13_REG(base) ((base)->PLL_CTRL13) +#define CCM_PLL_CTRL13_SET_REG(base) ((base)->PLL_CTRL13_SET) +#define CCM_PLL_CTRL13_CLR_REG(base) ((base)->PLL_CTRL13_CLR) +#define CCM_PLL_CTRL13_TOG_REG(base) ((base)->PLL_CTRL13_TOG) +#define CCM_PLL_CTRL14_REG(base) ((base)->PLL_CTRL14) +#define CCM_PLL_CTRL14_SET_REG(base) ((base)->PLL_CTRL14_SET) +#define CCM_PLL_CTRL14_CLR_REG(base) ((base)->PLL_CTRL14_CLR) +#define CCM_PLL_CTRL14_TOG_REG(base) ((base)->PLL_CTRL14_TOG) +#define CCM_PLL_CTRL15_REG(base) ((base)->PLL_CTRL15) +#define CCM_PLL_CTRL15_SET_REG(base) ((base)->PLL_CTRL15_SET) +#define CCM_PLL_CTRL15_CLR_REG(base) ((base)->PLL_CTRL15_CLR) +#define CCM_PLL_CTRL15_TOG_REG(base) ((base)->PLL_CTRL15_TOG) +#define CCM_PLL_CTRL16_REG(base) ((base)->PLL_CTRL16) +#define CCM_PLL_CTRL16_SET_REG(base) ((base)->PLL_CTRL16_SET) +#define CCM_PLL_CTRL16_CLR_REG(base) ((base)->PLL_CTRL16_CLR) +#define CCM_PLL_CTRL16_TOG_REG(base) ((base)->PLL_CTRL16_TOG) +#define CCM_PLL_CTRL17_REG(base) ((base)->PLL_CTRL17) +#define CCM_PLL_CTRL17_SET_REG(base) ((base)->PLL_CTRL17_SET) +#define CCM_PLL_CTRL17_CLR_REG(base) ((base)->PLL_CTRL17_CLR) +#define CCM_PLL_CTRL17_TOG_REG(base) ((base)->PLL_CTRL17_TOG) +#define CCM_PLL_CTRL18_REG(base) ((base)->PLL_CTRL18) +#define CCM_PLL_CTRL18_SET_REG(base) ((base)->PLL_CTRL18_SET) +#define CCM_PLL_CTRL18_CLR_REG(base) ((base)->PLL_CTRL18_CLR) +#define CCM_PLL_CTRL18_TOG_REG(base) ((base)->PLL_CTRL18_TOG) +#define CCM_PLL_CTRL19_REG(base) ((base)->PLL_CTRL19) +#define CCM_PLL_CTRL19_SET_REG(base) ((base)->PLL_CTRL19_SET) +#define CCM_PLL_CTRL19_CLR_REG(base) ((base)->PLL_CTRL19_CLR) +#define CCM_PLL_CTRL19_TOG_REG(base) ((base)->PLL_CTRL19_TOG) +#define CCM_PLL_CTRL20_REG(base) ((base)->PLL_CTRL20) +#define CCM_PLL_CTRL20_SET_REG(base) ((base)->PLL_CTRL20_SET) +#define CCM_PLL_CTRL20_CLR_REG(base) ((base)->PLL_CTRL20_CLR) +#define CCM_PLL_CTRL20_TOG_REG(base) ((base)->PLL_CTRL20_TOG) +#define CCM_PLL_CTRL21_REG(base) ((base)->PLL_CTRL21) +#define CCM_PLL_CTRL21_SET_REG(base) ((base)->PLL_CTRL21_SET) +#define CCM_PLL_CTRL21_CLR_REG(base) ((base)->PLL_CTRL21_CLR) +#define CCM_PLL_CTRL21_TOG_REG(base) ((base)->PLL_CTRL21_TOG) +#define CCM_PLL_CTRL22_REG(base) ((base)->PLL_CTRL22) +#define CCM_PLL_CTRL22_SET_REG(base) ((base)->PLL_CTRL22_SET) +#define CCM_PLL_CTRL22_CLR_REG(base) ((base)->PLL_CTRL22_CLR) +#define CCM_PLL_CTRL22_TOG_REG(base) ((base)->PLL_CTRL22_TOG) +#define CCM_PLL_CTRL23_REG(base) ((base)->PLL_CTRL23) +#define CCM_PLL_CTRL23_SET_REG(base) ((base)->PLL_CTRL23_SET) +#define CCM_PLL_CTRL23_CLR_REG(base) ((base)->PLL_CTRL23_CLR) +#define CCM_PLL_CTRL23_TOG_REG(base) ((base)->PLL_CTRL23_TOG) +#define CCM_PLL_CTRL24_REG(base) ((base)->PLL_CTRL24) +#define CCM_PLL_CTRL24_SET_REG(base) ((base)->PLL_CTRL24_SET) +#define CCM_PLL_CTRL24_CLR_REG(base) ((base)->PLL_CTRL24_CLR) +#define CCM_PLL_CTRL24_TOG_REG(base) ((base)->PLL_CTRL24_TOG) +#define CCM_PLL_CTRL25_REG(base) ((base)->PLL_CTRL25) +#define CCM_PLL_CTRL25_SET_REG(base) ((base)->PLL_CTRL25_SET) +#define CCM_PLL_CTRL25_CLR_REG(base) ((base)->PLL_CTRL25_CLR) +#define CCM_PLL_CTRL25_TOG_REG(base) ((base)->PLL_CTRL25_TOG) +#define CCM_PLL_CTRL26_REG(base) ((base)->PLL_CTRL26) +#define CCM_PLL_CTRL26_SET_REG(base) ((base)->PLL_CTRL26_SET) +#define CCM_PLL_CTRL26_CLR_REG(base) ((base)->PLL_CTRL26_CLR) +#define CCM_PLL_CTRL26_TOG_REG(base) ((base)->PLL_CTRL26_TOG) +#define CCM_PLL_CTRL27_REG(base) ((base)->PLL_CTRL27) +#define CCM_PLL_CTRL27_SET_REG(base) ((base)->PLL_CTRL27_SET) +#define CCM_PLL_CTRL27_CLR_REG(base) ((base)->PLL_CTRL27_CLR) +#define CCM_PLL_CTRL27_TOG_REG(base) ((base)->PLL_CTRL27_TOG) +#define CCM_PLL_CTRL28_REG(base) ((base)->PLL_CTRL28) +#define CCM_PLL_CTRL28_SET_REG(base) ((base)->PLL_CTRL28_SET) +#define CCM_PLL_CTRL28_CLR_REG(base) ((base)->PLL_CTRL28_CLR) +#define CCM_PLL_CTRL28_TOG_REG(base) ((base)->PLL_CTRL28_TOG) +#define CCM_PLL_CTRL29_REG(base) ((base)->PLL_CTRL29) +#define CCM_PLL_CTRL29_SET_REG(base) ((base)->PLL_CTRL29_SET) +#define CCM_PLL_CTRL29_CLR_REG(base) ((base)->PLL_CTRL29_CLR) +#define CCM_PLL_CTRL29_TOG_REG(base) ((base)->PLL_CTRL29_TOG) +#define CCM_PLL_CTRL30_REG(base) ((base)->PLL_CTRL30) +#define CCM_PLL_CTRL30_SET_REG(base) ((base)->PLL_CTRL30_SET) +#define CCM_PLL_CTRL30_CLR_REG(base) ((base)->PLL_CTRL30_CLR) +#define CCM_PLL_CTRL30_TOG_REG(base) ((base)->PLL_CTRL30_TOG) +#define CCM_PLL_CTRL31_REG(base) ((base)->PLL_CTRL31) +#define CCM_PLL_CTRL31_SET_REG(base) ((base)->PLL_CTRL31_SET) +#define CCM_PLL_CTRL31_CLR_REG(base) ((base)->PLL_CTRL31_CLR) +#define CCM_PLL_CTRL31_TOG_REG(base) ((base)->PLL_CTRL31_TOG) +#define CCM_PLL_CTRL32_REG(base) ((base)->PLL_CTRL32) +#define CCM_PLL_CTRL32_SET_REG(base) ((base)->PLL_CTRL32_SET) +#define CCM_PLL_CTRL32_CLR_REG(base) ((base)->PLL_CTRL32_CLR) +#define CCM_PLL_CTRL32_TOG_REG(base) ((base)->PLL_CTRL32_TOG) +#define CCM_CCGR0_REG(base) ((base)->CCGR0) +#define CCM_CCGR0_SET_REG(base) ((base)->CCGR0_SET) +#define CCM_CCGR0_CLR_REG(base) ((base)->CCGR0_CLR) +#define CCM_CCGR0_TOG_REG(base) ((base)->CCGR0_TOG) +#define CCM_CCGR1_REG(base) ((base)->CCGR1) +#define CCM_CCGR1_SET_REG(base) ((base)->CCGR1_SET) +#define CCM_CCGR1_CLR_REG(base) ((base)->CCGR1_CLR) +#define CCM_CCGR1_TOG_REG(base) ((base)->CCGR1_TOG) +#define CCM_CCGR2_REG(base) ((base)->CCGR2) +#define CCM_CCGR2_SET_REG(base) ((base)->CCGR2_SET) +#define CCM_CCGR2_CLR_REG(base) ((base)->CCGR2_CLR) +#define CCM_CCGR2_TOG_REG(base) ((base)->CCGR2_TOG) +#define CCM_CCGR3_REG(base) ((base)->CCGR3) +#define CCM_CCGR3_SET_REG(base) ((base)->CCGR3_SET) +#define CCM_CCGR3_CLR_REG(base) ((base)->CCGR3_CLR) +#define CCM_CCGR3_TOG_REG(base) ((base)->CCGR3_TOG) +#define CCM_CCGR4_REG(base) ((base)->CCGR4) +#define CCM_CCGR4_SET_REG(base) ((base)->CCGR4_SET) +#define CCM_CCGR4_CLR_REG(base) ((base)->CCGR4_CLR) +#define CCM_CCGR4_TOG_REG(base) ((base)->CCGR4_TOG) +#define CCM_CCGR5_REG(base) ((base)->CCGR5) +#define CCM_CCGR5_SET_REG(base) ((base)->CCGR5_SET) +#define CCM_CCGR5_CLR_REG(base) ((base)->CCGR5_CLR) +#define CCM_CCGR5_TOG_REG(base) ((base)->CCGR5_TOG) +#define CCM_CCGR6_REG(base) ((base)->CCGR6) +#define CCM_CCGR6_SET_REG(base) ((base)->CCGR6_SET) +#define CCM_CCGR6_CLR_REG(base) ((base)->CCGR6_CLR) +#define CCM_CCGR6_TOG_REG(base) ((base)->CCGR6_TOG) +#define CCM_CCGR7_REG(base) ((base)->CCGR7) +#define CCM_CCGR7_SET_REG(base) ((base)->CCGR7_SET) +#define CCM_CCGR7_CLR_REG(base) ((base)->CCGR7_CLR) +#define CCM_CCGR7_TOG_REG(base) ((base)->CCGR7_TOG) +#define CCM_CCGR8_REG(base) ((base)->CCGR8) +#define CCM_CCGR8_SET_REG(base) ((base)->CCGR8_SET) +#define CCM_CCGR8_CLR_REG(base) ((base)->CCGR8_CLR) +#define CCM_CCGR8_TOG_REG(base) ((base)->CCGR8_TOG) +#define CCM_CCGR9_REG(base) ((base)->CCGR9) +#define CCM_CCGR9_SET_REG(base) ((base)->CCGR9_SET) +#define CCM_CCGR9_CLR_REG(base) ((base)->CCGR9_CLR) +#define CCM_CCGR9_TOG_REG(base) ((base)->CCGR9_TOG) +#define CCM_CCGR10_REG(base) ((base)->CCGR10) +#define CCM_CCGR10_SET_REG(base) ((base)->CCGR10_SET) +#define CCM_CCGR10_CLR_REG(base) ((base)->CCGR10_CLR) +#define CCM_CCGR10_TOG_REG(base) ((base)->CCGR10_TOG) +#define CCM_CCGR11_REG(base) ((base)->CCGR11) +#define CCM_CCGR11_SET_REG(base) ((base)->CCGR11_SET) +#define CCM_CCGR11_CLR_REG(base) ((base)->CCGR11_CLR) +#define CCM_CCGR11_TOG_REG(base) ((base)->CCGR11_TOG) +#define CCM_CCGR12_REG(base) ((base)->CCGR12) +#define CCM_CCGR12_SET_REG(base) ((base)->CCGR12_SET) +#define CCM_CCGR12_CLR_REG(base) ((base)->CCGR12_CLR) +#define CCM_CCGR12_TOG_REG(base) ((base)->CCGR12_TOG) +#define CCM_CCGR13_REG(base) ((base)->CCGR13) +#define CCM_CCGR13_SET_REG(base) ((base)->CCGR13_SET) +#define CCM_CCGR13_CLR_REG(base) ((base)->CCGR13_CLR) +#define CCM_CCGR13_TOG_REG(base) ((base)->CCGR13_TOG) +#define CCM_CCGR14_REG(base) ((base)->CCGR14) +#define CCM_CCGR14_SET_REG(base) ((base)->CCGR14_SET) +#define CCM_CCGR14_CLR_REG(base) ((base)->CCGR14_CLR) +#define CCM_CCGR14_TOG_REG(base) ((base)->CCGR14_TOG) +#define CCM_CCGR15_REG(base) ((base)->CCGR15) +#define CCM_CCGR15_SET_REG(base) ((base)->CCGR15_SET) +#define CCM_CCGR15_CLR_REG(base) ((base)->CCGR15_CLR) +#define CCM_CCGR15_TOG_REG(base) ((base)->CCGR15_TOG) +#define CCM_CCGR16_REG(base) ((base)->CCGR16) +#define CCM_CCGR16_SET_REG(base) ((base)->CCGR16_SET) +#define CCM_CCGR16_CLR_REG(base) ((base)->CCGR16_CLR) +#define CCM_CCGR16_TOG_REG(base) ((base)->CCGR16_TOG) +#define CCM_CCGR17_REG(base) ((base)->CCGR17) +#define CCM_CCGR17_SET_REG(base) ((base)->CCGR17_SET) +#define CCM_CCGR17_CLR_REG(base) ((base)->CCGR17_CLR) +#define CCM_CCGR17_TOG_REG(base) ((base)->CCGR17_TOG) +#define CCM_CCGR18_REG(base) ((base)->CCGR18) +#define CCM_CCGR18_SET_REG(base) ((base)->CCGR18_SET) +#define CCM_CCGR18_CLR_REG(base) ((base)->CCGR18_CLR) +#define CCM_CCGR18_TOG_REG(base) ((base)->CCGR18_TOG) +#define CCM_CCGR19_REG(base) ((base)->CCGR19) +#define CCM_CCGR19_SET_REG(base) ((base)->CCGR19_SET) +#define CCM_CCGR19_CLR_REG(base) ((base)->CCGR19_CLR) +#define CCM_CCGR19_TOG_REG(base) ((base)->CCGR19_TOG) +#define CCM_CCGR20_REG(base) ((base)->CCGR20) +#define CCM_CCGR20_SET_REG(base) ((base)->CCGR20_SET) +#define CCM_CCGR20_CLR_REG(base) ((base)->CCGR20_CLR) +#define CCM_CCGR20_TOG_REG(base) ((base)->CCGR20_TOG) +#define CCM_CCGR21_REG(base) ((base)->CCGR21) +#define CCM_CCGR21_SET_REG(base) ((base)->CCGR21_SET) +#define CCM_CCGR21_CLR_REG(base) ((base)->CCGR21_CLR) +#define CCM_CCGR21_TOG_REG(base) ((base)->CCGR21_TOG) +#define CCM_CCGR22_REG(base) ((base)->CCGR22) +#define CCM_CCGR22_SET_REG(base) ((base)->CCGR22_SET) +#define CCM_CCGR22_CLR_REG(base) ((base)->CCGR22_CLR) +#define CCM_CCGR22_TOG_REG(base) ((base)->CCGR22_TOG) +#define CCM_CCGR23_REG(base) ((base)->CCGR23) +#define CCM_CCGR23_SET_REG(base) ((base)->CCGR23_SET) +#define CCM_CCGR23_CLR_REG(base) ((base)->CCGR23_CLR) +#define CCM_CCGR23_TOG_REG(base) ((base)->CCGR23_TOG) +#define CCM_CCGR24_REG(base) ((base)->CCGR24) +#define CCM_CCGR24_SET_REG(base) ((base)->CCGR24_SET) +#define CCM_CCGR24_CLR_REG(base) ((base)->CCGR24_CLR) +#define CCM_CCGR24_TOG_REG(base) ((base)->CCGR24_TOG) +#define CCM_CCGR25_REG(base) ((base)->CCGR25) +#define CCM_CCGR25_SET_REG(base) ((base)->CCGR25_SET) +#define CCM_CCGR25_CLR_REG(base) ((base)->CCGR25_CLR) +#define CCM_CCGR25_TOG_REG(base) ((base)->CCGR25_TOG) +#define CCM_CCGR26_REG(base) ((base)->CCGR26) +#define CCM_CCGR26_SET_REG(base) ((base)->CCGR26_SET) +#define CCM_CCGR26_CLR_REG(base) ((base)->CCGR26_CLR) +#define CCM_CCGR26_TOG_REG(base) ((base)->CCGR26_TOG) +#define CCM_CCGR27_REG(base) ((base)->CCGR27) +#define CCM_CCGR27_SET_REG(base) ((base)->CCGR27_SET) +#define CCM_CCGR27_CLR_REG(base) ((base)->CCGR27_CLR) +#define CCM_CCGR27_TOG_REG(base) ((base)->CCGR27_TOG) +#define CCM_CCGR28_REG(base) ((base)->CCGR28) +#define CCM_CCGR28_SET_REG(base) ((base)->CCGR28_SET) +#define CCM_CCGR28_CLR_REG(base) ((base)->CCGR28_CLR) +#define CCM_CCGR28_TOG_REG(base) ((base)->CCGR28_TOG) +#define CCM_CCGR29_REG(base) ((base)->CCGR29) +#define CCM_CCGR29_SET_REG(base) ((base)->CCGR29_SET) +#define CCM_CCGR29_CLR_REG(base) ((base)->CCGR29_CLR) +#define CCM_CCGR29_TOG_REG(base) ((base)->CCGR29_TOG) +#define CCM_CCGR30_REG(base) ((base)->CCGR30) +#define CCM_CCGR30_SET_REG(base) ((base)->CCGR30_SET) +#define CCM_CCGR30_CLR_REG(base) ((base)->CCGR30_CLR) +#define CCM_CCGR30_TOG_REG(base) ((base)->CCGR30_TOG) +#define CCM_CCGR31_REG(base) ((base)->CCGR31) +#define CCM_CCGR31_SET_REG(base) ((base)->CCGR31_SET) +#define CCM_CCGR31_CLR_REG(base) ((base)->CCGR31_CLR) +#define CCM_CCGR31_TOG_REG(base) ((base)->CCGR31_TOG) +#define CCM_CCGR32_REG(base) ((base)->CCGR32) +#define CCM_CCGR32_SET_REG(base) ((base)->CCGR32_SET) +#define CCM_CCGR32_CLR_REG(base) ((base)->CCGR32_CLR) +#define CCM_CCGR32_TOG_REG(base) ((base)->CCGR32_TOG) +#define CCM_CCGR33_REG(base) ((base)->CCGR33) +#define CCM_CCGR33_SET_REG(base) ((base)->CCGR33_SET) +#define CCM_CCGR33_CLR_REG(base) ((base)->CCGR33_CLR) +#define CCM_CCGR33_TOG_REG(base) ((base)->CCGR33_TOG) +#define CCM_CCGR34_REG(base) ((base)->CCGR34) +#define CCM_CCGR34_SET_REG(base) ((base)->CCGR34_SET) +#define CCM_CCGR34_CLR_REG(base) ((base)->CCGR34_CLR) +#define CCM_CCGR34_TOG_REG(base) ((base)->CCGR34_TOG) +#define CCM_CCGR35_REG(base) ((base)->CCGR35) +#define CCM_CCGR35_SET_REG(base) ((base)->CCGR35_SET) +#define CCM_CCGR35_CLR_REG(base) ((base)->CCGR35_CLR) +#define CCM_CCGR35_TOG_REG(base) ((base)->CCGR35_TOG) +#define CCM_CCGR36_REG(base) ((base)->CCGR36) +#define CCM_CCGR36_SET_REG(base) ((base)->CCGR36_SET) +#define CCM_CCGR36_CLR_REG(base) ((base)->CCGR36_CLR) +#define CCM_CCGR36_TOG_REG(base) ((base)->CCGR36_TOG) +#define CCM_CCGR37_REG(base) ((base)->CCGR37) +#define CCM_CCGR37_SET_REG(base) ((base)->CCGR37_SET) +#define CCM_CCGR37_CLR_REG(base) ((base)->CCGR37_CLR) +#define CCM_CCGR37_TOG_REG(base) ((base)->CCGR37_TOG) +#define CCM_CCGR38_REG(base) ((base)->CCGR38) +#define CCM_CCGR38_SET_REG(base) ((base)->CCGR38_SET) +#define CCM_CCGR38_CLR_REG(base) ((base)->CCGR38_CLR) +#define CCM_CCGR38_TOG_REG(base) ((base)->CCGR38_TOG) +#define CCM_CCGR39_REG(base) ((base)->CCGR39) +#define CCM_CCGR39_SET_REG(base) ((base)->CCGR39_SET) +#define CCM_CCGR39_CLR_REG(base) ((base)->CCGR39_CLR) +#define CCM_CCGR39_TOG_REG(base) ((base)->CCGR39_TOG) +#define CCM_CCGR40_REG(base) ((base)->CCGR40) +#define CCM_CCGR40_SET_REG(base) ((base)->CCGR40_SET) +#define CCM_CCGR40_CLR_REG(base) ((base)->CCGR40_CLR) +#define CCM_CCGR40_TOG_REG(base) ((base)->CCGR40_TOG) +#define CCM_CCGR41_REG(base) ((base)->CCGR41) +#define CCM_CCGR41_SET_REG(base) ((base)->CCGR41_SET) +#define CCM_CCGR41_CLR_REG(base) ((base)->CCGR41_CLR) +#define CCM_CCGR41_TOG_REG(base) ((base)->CCGR41_TOG) +#define CCM_CCGR42_REG(base) ((base)->CCGR42) +#define CCM_CCGR42_SET_REG(base) ((base)->CCGR42_SET) +#define CCM_CCGR42_CLR_REG(base) ((base)->CCGR42_CLR) +#define CCM_CCGR42_TOG_REG(base) ((base)->CCGR42_TOG) +#define CCM_CCGR43_REG(base) ((base)->CCGR43) +#define CCM_CCGR43_SET_REG(base) ((base)->CCGR43_SET) +#define CCM_CCGR43_CLR_REG(base) ((base)->CCGR43_CLR) +#define CCM_CCGR43_TOG_REG(base) ((base)->CCGR43_TOG) +#define CCM_CCGR44_REG(base) ((base)->CCGR44) +#define CCM_CCGR44_SET_REG(base) ((base)->CCGR44_SET) +#define CCM_CCGR44_CLR_REG(base) ((base)->CCGR44_CLR) +#define CCM_CCGR44_TOG_REG(base) ((base)->CCGR44_TOG) +#define CCM_CCGR45_REG(base) ((base)->CCGR45) +#define CCM_CCGR45_SET_REG(base) ((base)->CCGR45_SET) +#define CCM_CCGR45_CLR_REG(base) ((base)->CCGR45_CLR) +#define CCM_CCGR45_TOG_REG(base) ((base)->CCGR45_TOG) +#define CCM_CCGR46_REG(base) ((base)->CCGR46) +#define CCM_CCGR46_SET_REG(base) ((base)->CCGR46_SET) +#define CCM_CCGR46_CLR_REG(base) ((base)->CCGR46_CLR) +#define CCM_CCGR46_TOG_REG(base) ((base)->CCGR46_TOG) +#define CCM_CCGR47_REG(base) ((base)->CCGR47) +#define CCM_CCGR47_SET_REG(base) ((base)->CCGR47_SET) +#define CCM_CCGR47_CLR_REG(base) ((base)->CCGR47_CLR) +#define CCM_CCGR47_TOG_REG(base) ((base)->CCGR47_TOG) +#define CCM_CCGR48_REG(base) ((base)->CCGR48) +#define CCM_CCGR48_SET_REG(base) ((base)->CCGR48_SET) +#define CCM_CCGR48_CLR_REG(base) ((base)->CCGR48_CLR) +#define CCM_CCGR48_TOG_REG(base) ((base)->CCGR48_TOG) +#define CCM_CCGR49_REG(base) ((base)->CCGR49) +#define CCM_CCGR49_SET_REG(base) ((base)->CCGR49_SET) +#define CCM_CCGR49_CLR_REG(base) ((base)->CCGR49_CLR) +#define CCM_CCGR49_TOG_REG(base) ((base)->CCGR49_TOG) +#define CCM_CCGR50_REG(base) ((base)->CCGR50) +#define CCM_CCGR50_SET_REG(base) ((base)->CCGR50_SET) +#define CCM_CCGR50_CLR_REG(base) ((base)->CCGR50_CLR) +#define CCM_CCGR50_TOG_REG(base) ((base)->CCGR50_TOG) +#define CCM_CCGR51_REG(base) ((base)->CCGR51) +#define CCM_CCGR51_SET_REG(base) ((base)->CCGR51_SET) +#define CCM_CCGR51_CLR_REG(base) ((base)->CCGR51_CLR) +#define CCM_CCGR51_TOG_REG(base) ((base)->CCGR51_TOG) +#define CCM_CCGR52_REG(base) ((base)->CCGR52) +#define CCM_CCGR52_SET_REG(base) ((base)->CCGR52_SET) +#define CCM_CCGR52_CLR_REG(base) ((base)->CCGR52_CLR) +#define CCM_CCGR52_TOG_REG(base) ((base)->CCGR52_TOG) +#define CCM_CCGR53_REG(base) ((base)->CCGR53) +#define CCM_CCGR53_SET_REG(base) ((base)->CCGR53_SET) +#define CCM_CCGR53_CLR_REG(base) ((base)->CCGR53_CLR) +#define CCM_CCGR53_TOG_REG(base) ((base)->CCGR53_TOG) +#define CCM_CCGR54_REG(base) ((base)->CCGR54) +#define CCM_CCGR54_SET_REG(base) ((base)->CCGR54_SET) +#define CCM_CCGR54_CLR_REG(base) ((base)->CCGR54_CLR) +#define CCM_CCGR54_TOG_REG(base) ((base)->CCGR54_TOG) +#define CCM_CCGR55_REG(base) ((base)->CCGR55) +#define CCM_CCGR55_SET_REG(base) ((base)->CCGR55_SET) +#define CCM_CCGR55_CLR_REG(base) ((base)->CCGR55_CLR) +#define CCM_CCGR55_TOG_REG(base) ((base)->CCGR55_TOG) +#define CCM_CCGR56_REG(base) ((base)->CCGR56) +#define CCM_CCGR56_SET_REG(base) ((base)->CCGR56_SET) +#define CCM_CCGR56_CLR_REG(base) ((base)->CCGR56_CLR) +#define CCM_CCGR56_TOG_REG(base) ((base)->CCGR56_TOG) +#define CCM_CCGR57_REG(base) ((base)->CCGR57) +#define CCM_CCGR57_SET_REG(base) ((base)->CCGR57_SET) +#define CCM_CCGR57_CLR_REG(base) ((base)->CCGR57_CLR) +#define CCM_CCGR57_TOG_REG(base) ((base)->CCGR57_TOG) +#define CCM_CCGR58_REG(base) ((base)->CCGR58) +#define CCM_CCGR58_SET_REG(base) ((base)->CCGR58_SET) +#define CCM_CCGR58_CLR_REG(base) ((base)->CCGR58_CLR) +#define CCM_CCGR58_TOG_REG(base) ((base)->CCGR58_TOG) +#define CCM_CCGR59_REG(base) ((base)->CCGR59) +#define CCM_CCGR59_SET_REG(base) ((base)->CCGR59_SET) +#define CCM_CCGR59_CLR_REG(base) ((base)->CCGR59_CLR) +#define CCM_CCGR59_TOG_REG(base) ((base)->CCGR59_TOG) +#define CCM_CCGR60_REG(base) ((base)->CCGR60) +#define CCM_CCGR60_SET_REG(base) ((base)->CCGR60_SET) +#define CCM_CCGR60_CLR_REG(base) ((base)->CCGR60_CLR) +#define CCM_CCGR60_TOG_REG(base) ((base)->CCGR60_TOG) +#define CCM_CCGR61_REG(base) ((base)->CCGR61) +#define CCM_CCGR61_SET_REG(base) ((base)->CCGR61_SET) +#define CCM_CCGR61_CLR_REG(base) ((base)->CCGR61_CLR) +#define CCM_CCGR61_TOG_REG(base) ((base)->CCGR61_TOG) +#define CCM_CCGR62_REG(base) ((base)->CCGR62) +#define CCM_CCGR62_SET_REG(base) ((base)->CCGR62_SET) +#define CCM_CCGR62_CLR_REG(base) ((base)->CCGR62_CLR) +#define CCM_CCGR62_TOG_REG(base) ((base)->CCGR62_TOG) +#define CCM_CCGR63_REG(base) ((base)->CCGR63) +#define CCM_CCGR63_SET_REG(base) ((base)->CCGR63_SET) +#define CCM_CCGR63_CLR_REG(base) ((base)->CCGR63_CLR) +#define CCM_CCGR63_TOG_REG(base) ((base)->CCGR63_TOG) +#define CCM_CCGR64_REG(base) ((base)->CCGR64) +#define CCM_CCGR64_SET_REG(base) ((base)->CCGR64_SET) +#define CCM_CCGR64_CLR_REG(base) ((base)->CCGR64_CLR) +#define CCM_CCGR64_TOG_REG(base) ((base)->CCGR64_TOG) +#define CCM_CCGR65_REG(base) ((base)->CCGR65) +#define CCM_CCGR65_SET_REG(base) ((base)->CCGR65_SET) +#define CCM_CCGR65_CLR_REG(base) ((base)->CCGR65_CLR) +#define CCM_CCGR65_TOG_REG(base) ((base)->CCGR65_TOG) +#define CCM_CCGR66_REG(base) ((base)->CCGR66) +#define CCM_CCGR66_SET_REG(base) ((base)->CCGR66_SET) +#define CCM_CCGR66_CLR_REG(base) ((base)->CCGR66_CLR) +#define CCM_CCGR66_TOG_REG(base) ((base)->CCGR66_TOG) +#define CCM_CCGR67_REG(base) ((base)->CCGR67) +#define CCM_CCGR67_SET_REG(base) ((base)->CCGR67_SET) +#define CCM_CCGR67_CLR_REG(base) ((base)->CCGR67_CLR) +#define CCM_CCGR67_TOG_REG(base) ((base)->CCGR67_TOG) +#define CCM_CCGR68_REG(base) ((base)->CCGR68) +#define CCM_CCGR68_SET_REG(base) ((base)->CCGR68_SET) +#define CCM_CCGR68_CLR_REG(base) ((base)->CCGR68_CLR) +#define CCM_CCGR68_TOG_REG(base) ((base)->CCGR68_TOG) +#define CCM_CCGR69_REG(base) ((base)->CCGR69) +#define CCM_CCGR69_SET_REG(base) ((base)->CCGR69_SET) +#define CCM_CCGR69_CLR_REG(base) ((base)->CCGR69_CLR) +#define CCM_CCGR69_TOG_REG(base) ((base)->CCGR69_TOG) +#define CCM_CCGR70_REG(base) ((base)->CCGR70) +#define CCM_CCGR70_SET_REG(base) ((base)->CCGR70_SET) +#define CCM_CCGR70_CLR_REG(base) ((base)->CCGR70_CLR) +#define CCM_CCGR70_TOG_REG(base) ((base)->CCGR70_TOG) +#define CCM_CCGR71_REG(base) ((base)->CCGR71) +#define CCM_CCGR71_SET_REG(base) ((base)->CCGR71_SET) +#define CCM_CCGR71_CLR_REG(base) ((base)->CCGR71_CLR) +#define CCM_CCGR71_TOG_REG(base) ((base)->CCGR71_TOG) +#define CCM_CCGR72_REG(base) ((base)->CCGR72) +#define CCM_CCGR72_SET_REG(base) ((base)->CCGR72_SET) +#define CCM_CCGR72_CLR_REG(base) ((base)->CCGR72_CLR) +#define CCM_CCGR72_TOG_REG(base) ((base)->CCGR72_TOG) +#define CCM_CCGR73_REG(base) ((base)->CCGR73) +#define CCM_CCGR73_SET_REG(base) ((base)->CCGR73_SET) +#define CCM_CCGR73_CLR_REG(base) ((base)->CCGR73_CLR) +#define CCM_CCGR73_TOG_REG(base) ((base)->CCGR73_TOG) +#define CCM_CCGR74_REG(base) ((base)->CCGR74) +#define CCM_CCGR74_SET_REG(base) ((base)->CCGR74_SET) +#define CCM_CCGR74_CLR_REG(base) ((base)->CCGR74_CLR) +#define CCM_CCGR74_TOG_REG(base) ((base)->CCGR74_TOG) +#define CCM_CCGR75_REG(base) ((base)->CCGR75) +#define CCM_CCGR75_SET_REG(base) ((base)->CCGR75_SET) +#define CCM_CCGR75_CLR_REG(base) ((base)->CCGR75_CLR) +#define CCM_CCGR75_TOG_REG(base) ((base)->CCGR75_TOG) +#define CCM_CCGR76_REG(base) ((base)->CCGR76) +#define CCM_CCGR76_SET_REG(base) ((base)->CCGR76_SET) +#define CCM_CCGR76_CLR_REG(base) ((base)->CCGR76_CLR) +#define CCM_CCGR76_TOG_REG(base) ((base)->CCGR76_TOG) +#define CCM_CCGR77_REG(base) ((base)->CCGR77) +#define CCM_CCGR77_SET_REG(base) ((base)->CCGR77_SET) +#define CCM_CCGR77_CLR_REG(base) ((base)->CCGR77_CLR) +#define CCM_CCGR77_TOG_REG(base) ((base)->CCGR77_TOG) +#define CCM_CCGR78_REG(base) ((base)->CCGR78) +#define CCM_CCGR78_SET_REG(base) ((base)->CCGR78_SET) +#define CCM_CCGR78_CLR_REG(base) ((base)->CCGR78_CLR) +#define CCM_CCGR78_TOG_REG(base) ((base)->CCGR78_TOG) +#define CCM_CCGR79_REG(base) ((base)->CCGR79) +#define CCM_CCGR79_SET_REG(base) ((base)->CCGR79_SET) +#define CCM_CCGR79_CLR_REG(base) ((base)->CCGR79_CLR) +#define CCM_CCGR79_TOG_REG(base) ((base)->CCGR79_TOG) +#define CCM_CCGR80_REG(base) ((base)->CCGR80) +#define CCM_CCGR80_SET_REG(base) ((base)->CCGR80_SET) +#define CCM_CCGR80_CLR_REG(base) ((base)->CCGR80_CLR) +#define CCM_CCGR80_TOG_REG(base) ((base)->CCGR80_TOG) +#define CCM_CCGR81_REG(base) ((base)->CCGR81) +#define CCM_CCGR81_SET_REG(base) ((base)->CCGR81_SET) +#define CCM_CCGR81_CLR_REG(base) ((base)->CCGR81_CLR) +#define CCM_CCGR81_TOG_REG(base) ((base)->CCGR81_TOG) +#define CCM_CCGR82_REG(base) ((base)->CCGR82) +#define CCM_CCGR82_SET_REG(base) ((base)->CCGR82_SET) +#define CCM_CCGR82_CLR_REG(base) ((base)->CCGR82_CLR) +#define CCM_CCGR82_TOG_REG(base) ((base)->CCGR82_TOG) +#define CCM_CCGR83_REG(base) ((base)->CCGR83) +#define CCM_CCGR83_SET_REG(base) ((base)->CCGR83_SET) +#define CCM_CCGR83_CLR_REG(base) ((base)->CCGR83_CLR) +#define CCM_CCGR83_TOG_REG(base) ((base)->CCGR83_TOG) +#define CCM_CCGR84_REG(base) ((base)->CCGR84) +#define CCM_CCGR84_SET_REG(base) ((base)->CCGR84_SET) +#define CCM_CCGR84_CLR_REG(base) ((base)->CCGR84_CLR) +#define CCM_CCGR84_TOG_REG(base) ((base)->CCGR84_TOG) +#define CCM_CCGR85_REG(base) ((base)->CCGR85) +#define CCM_CCGR85_SET_REG(base) ((base)->CCGR85_SET) +#define CCM_CCGR85_CLR_REG(base) ((base)->CCGR85_CLR) +#define CCM_CCGR85_TOG_REG(base) ((base)->CCGR85_TOG) +#define CCM_CCGR86_REG(base) ((base)->CCGR86) +#define CCM_CCGR86_SET_REG(base) ((base)->CCGR86_SET) +#define CCM_CCGR86_CLR_REG(base) ((base)->CCGR86_CLR) +#define CCM_CCGR86_TOG_REG(base) ((base)->CCGR86_TOG) +#define CCM_CCGR87_REG(base) ((base)->CCGR87) +#define CCM_CCGR87_SET_REG(base) ((base)->CCGR87_SET) +#define CCM_CCGR87_CLR_REG(base) ((base)->CCGR87_CLR) +#define CCM_CCGR87_TOG_REG(base) ((base)->CCGR87_TOG) +#define CCM_CCGR88_REG(base) ((base)->CCGR88) +#define CCM_CCGR88_SET_REG(base) ((base)->CCGR88_SET) +#define CCM_CCGR88_CLR_REG(base) ((base)->CCGR88_CLR) +#define CCM_CCGR88_TOG_REG(base) ((base)->CCGR88_TOG) +#define CCM_CCGR89_REG(base) ((base)->CCGR89) +#define CCM_CCGR89_SET_REG(base) ((base)->CCGR89_SET) +#define CCM_CCGR89_CLR_REG(base) ((base)->CCGR89_CLR) +#define CCM_CCGR89_TOG_REG(base) ((base)->CCGR89_TOG) +#define CCM_CCGR90_REG(base) ((base)->CCGR90) +#define CCM_CCGR90_SET_REG(base) ((base)->CCGR90_SET) +#define CCM_CCGR90_CLR_REG(base) ((base)->CCGR90_CLR) +#define CCM_CCGR90_TOG_REG(base) ((base)->CCGR90_TOG) +#define CCM_CCGR91_REG(base) ((base)->CCGR91) +#define CCM_CCGR91_SET_REG(base) ((base)->CCGR91_SET) +#define CCM_CCGR91_CLR_REG(base) ((base)->CCGR91_CLR) +#define CCM_CCGR91_TOG_REG(base) ((base)->CCGR91_TOG) +#define CCM_CCGR92_REG(base) ((base)->CCGR92) +#define CCM_CCGR92_SET_REG(base) ((base)->CCGR92_SET) +#define CCM_CCGR92_CLR_REG(base) ((base)->CCGR92_CLR) +#define CCM_CCGR92_TOG_REG(base) ((base)->CCGR92_TOG) +#define CCM_CCGR93_REG(base) ((base)->CCGR93) +#define CCM_CCGR93_SET_REG(base) ((base)->CCGR93_SET) +#define CCM_CCGR93_CLR_REG(base) ((base)->CCGR93_CLR) +#define CCM_CCGR93_TOG_REG(base) ((base)->CCGR93_TOG) +#define CCM_CCGR94_REG(base) ((base)->CCGR94) +#define CCM_CCGR94_SET_REG(base) ((base)->CCGR94_SET) +#define CCM_CCGR94_CLR_REG(base) ((base)->CCGR94_CLR) +#define CCM_CCGR94_TOG_REG(base) ((base)->CCGR94_TOG) +#define CCM_CCGR95_REG(base) ((base)->CCGR95) +#define CCM_CCGR95_SET_REG(base) ((base)->CCGR95_SET) +#define CCM_CCGR95_CLR_REG(base) ((base)->CCGR95_CLR) +#define CCM_CCGR95_TOG_REG(base) ((base)->CCGR95_TOG) +#define CCM_CCGR96_REG(base) ((base)->CCGR96) +#define CCM_CCGR96_SET_REG(base) ((base)->CCGR96_SET) +#define CCM_CCGR96_CLR_REG(base) ((base)->CCGR96_CLR) +#define CCM_CCGR96_TOG_REG(base) ((base)->CCGR96_TOG) +#define CCM_CCGR97_REG(base) ((base)->CCGR97) +#define CCM_CCGR97_SET_REG(base) ((base)->CCGR97_SET) +#define CCM_CCGR97_CLR_REG(base) ((base)->CCGR97_CLR) +#define CCM_CCGR97_TOG_REG(base) ((base)->CCGR97_TOG) +#define CCM_CCGR98_REG(base) ((base)->CCGR98) +#define CCM_CCGR98_SET_REG(base) ((base)->CCGR98_SET) +#define CCM_CCGR98_CLR_REG(base) ((base)->CCGR98_CLR) +#define CCM_CCGR98_TOG_REG(base) ((base)->CCGR98_TOG) +#define CCM_CCGR99_REG(base) ((base)->CCGR99) +#define CCM_CCGR99_SET_REG(base) ((base)->CCGR99_SET) +#define CCM_CCGR99_CLR_REG(base) ((base)->CCGR99_CLR) +#define CCM_CCGR99_TOG_REG(base) ((base)->CCGR99_TOG) +#define CCM_CCGR100_REG(base) ((base)->CCGR100) +#define CCM_CCGR100_SET_REG(base) ((base)->CCGR100_SET) +#define CCM_CCGR100_CLR_REG(base) ((base)->CCGR100_CLR) +#define CCM_CCGR100_TOG_REG(base) ((base)->CCGR100_TOG) +#define CCM_CCGR101_REG(base) ((base)->CCGR101) +#define CCM_CCGR101_SET_REG(base) ((base)->CCGR101_SET) +#define CCM_CCGR101_CLR_REG(base) ((base)->CCGR101_CLR) +#define CCM_CCGR101_TOG_REG(base) ((base)->CCGR101_TOG) +#define CCM_CCGR102_REG(base) ((base)->CCGR102) +#define CCM_CCGR102_SET_REG(base) ((base)->CCGR102_SET) +#define CCM_CCGR102_CLR_REG(base) ((base)->CCGR102_CLR) +#define CCM_CCGR102_TOG_REG(base) ((base)->CCGR102_TOG) +#define CCM_CCGR103_REG(base) ((base)->CCGR103) +#define CCM_CCGR103_SET_REG(base) ((base)->CCGR103_SET) +#define CCM_CCGR103_CLR_REG(base) ((base)->CCGR103_CLR) +#define CCM_CCGR103_TOG_REG(base) ((base)->CCGR103_TOG) +#define CCM_CCGR104_REG(base) ((base)->CCGR104) +#define CCM_CCGR104_SET_REG(base) ((base)->CCGR104_SET) +#define CCM_CCGR104_CLR_REG(base) ((base)->CCGR104_CLR) +#define CCM_CCGR104_TOG_REG(base) ((base)->CCGR104_TOG) +#define CCM_CCGR105_REG(base) ((base)->CCGR105) +#define CCM_CCGR105_SET_REG(base) ((base)->CCGR105_SET) +#define CCM_CCGR105_CLR_REG(base) ((base)->CCGR105_CLR) +#define CCM_CCGR105_TOG_REG(base) ((base)->CCGR105_TOG) +#define CCM_CCGR106_REG(base) ((base)->CCGR106) +#define CCM_CCGR106_SET_REG(base) ((base)->CCGR106_SET) +#define CCM_CCGR106_CLR_REG(base) ((base)->CCGR106_CLR) +#define CCM_CCGR106_TOG_REG(base) ((base)->CCGR106_TOG) +#define CCM_CCGR107_REG(base) ((base)->CCGR107) +#define CCM_CCGR107_SET_REG(base) ((base)->CCGR107_SET) +#define CCM_CCGR107_CLR_REG(base) ((base)->CCGR107_CLR) +#define CCM_CCGR107_TOG_REG(base) ((base)->CCGR107_TOG) +#define CCM_CCGR108_REG(base) ((base)->CCGR108) +#define CCM_CCGR108_SET_REG(base) ((base)->CCGR108_SET) +#define CCM_CCGR108_CLR_REG(base) ((base)->CCGR108_CLR) +#define CCM_CCGR108_TOG_REG(base) ((base)->CCGR108_TOG) +#define CCM_CCGR109_REG(base) ((base)->CCGR109) +#define CCM_CCGR109_SET_REG(base) ((base)->CCGR109_SET) +#define CCM_CCGR109_CLR_REG(base) ((base)->CCGR109_CLR) +#define CCM_CCGR109_TOG_REG(base) ((base)->CCGR109_TOG) +#define CCM_CCGR110_REG(base) ((base)->CCGR110) +#define CCM_CCGR110_SET_REG(base) ((base)->CCGR110_SET) +#define CCM_CCGR110_CLR_REG(base) ((base)->CCGR110_CLR) +#define CCM_CCGR110_TOG_REG(base) ((base)->CCGR110_TOG) +#define CCM_CCGR111_REG(base) ((base)->CCGR111) +#define CCM_CCGR111_SET_REG(base) ((base)->CCGR111_SET) +#define CCM_CCGR111_CLR_REG(base) ((base)->CCGR111_CLR) +#define CCM_CCGR111_TOG_REG(base) ((base)->CCGR111_TOG) +#define CCM_CCGR112_REG(base) ((base)->CCGR112) +#define CCM_CCGR112_SET_REG(base) ((base)->CCGR112_SET) +#define CCM_CCGR112_CLR_REG(base) ((base)->CCGR112_CLR) +#define CCM_CCGR112_TOG_REG(base) ((base)->CCGR112_TOG) +#define CCM_CCGR113_REG(base) ((base)->CCGR113) +#define CCM_CCGR113_SET_REG(base) ((base)->CCGR113_SET) +#define CCM_CCGR113_CLR_REG(base) ((base)->CCGR113_CLR) +#define CCM_CCGR113_TOG_REG(base) ((base)->CCGR113_TOG) +#define CCM_CCGR114_REG(base) ((base)->CCGR114) +#define CCM_CCGR114_SET_REG(base) ((base)->CCGR114_SET) +#define CCM_CCGR114_CLR_REG(base) ((base)->CCGR114_CLR) +#define CCM_CCGR114_TOG_REG(base) ((base)->CCGR114_TOG) +#define CCM_CCGR115_REG(base) ((base)->CCGR115) +#define CCM_CCGR115_SET_REG(base) ((base)->CCGR115_SET) +#define CCM_CCGR115_CLR_REG(base) ((base)->CCGR115_CLR) +#define CCM_CCGR115_TOG_REG(base) ((base)->CCGR115_TOG) +#define CCM_CCGR116_REG(base) ((base)->CCGR116) +#define CCM_CCGR116_SET_REG(base) ((base)->CCGR116_SET) +#define CCM_CCGR116_CLR_REG(base) ((base)->CCGR116_CLR) +#define CCM_CCGR116_TOG_REG(base) ((base)->CCGR116_TOG) +#define CCM_CCGR117_REG(base) ((base)->CCGR117) +#define CCM_CCGR117_SET_REG(base) ((base)->CCGR117_SET) +#define CCM_CCGR117_CLR_REG(base) ((base)->CCGR117_CLR) +#define CCM_CCGR117_TOG_REG(base) ((base)->CCGR117_TOG) +#define CCM_CCGR118_REG(base) ((base)->CCGR118) +#define CCM_CCGR118_SET_REG(base) ((base)->CCGR118_SET) +#define CCM_CCGR118_CLR_REG(base) ((base)->CCGR118_CLR) +#define CCM_CCGR118_TOG_REG(base) ((base)->CCGR118_TOG) +#define CCM_CCGR119_REG(base) ((base)->CCGR119) +#define CCM_CCGR119_SET_REG(base) ((base)->CCGR119_SET) +#define CCM_CCGR119_CLR_REG(base) ((base)->CCGR119_CLR) +#define CCM_CCGR119_TOG_REG(base) ((base)->CCGR119_TOG) +#define CCM_CCGR120_REG(base) ((base)->CCGR120) +#define CCM_CCGR120_SET_REG(base) ((base)->CCGR120_SET) +#define CCM_CCGR120_CLR_REG(base) ((base)->CCGR120_CLR) +#define CCM_CCGR120_TOG_REG(base) ((base)->CCGR120_TOG) +#define CCM_CCGR121_REG(base) ((base)->CCGR121) +#define CCM_CCGR121_SET_REG(base) ((base)->CCGR121_SET) +#define CCM_CCGR121_CLR_REG(base) ((base)->CCGR121_CLR) +#define CCM_CCGR121_TOG_REG(base) ((base)->CCGR121_TOG) +#define CCM_CCGR122_REG(base) ((base)->CCGR122) +#define CCM_CCGR122_SET_REG(base) ((base)->CCGR122_SET) +#define CCM_CCGR122_CLR_REG(base) ((base)->CCGR122_CLR) +#define CCM_CCGR122_TOG_REG(base) ((base)->CCGR122_TOG) +#define CCM_CCGR123_REG(base) ((base)->CCGR123) +#define CCM_CCGR123_SET_REG(base) ((base)->CCGR123_SET) +#define CCM_CCGR123_CLR_REG(base) ((base)->CCGR123_CLR) +#define CCM_CCGR123_TOG_REG(base) ((base)->CCGR123_TOG) +#define CCM_CCGR124_REG(base) ((base)->CCGR124) +#define CCM_CCGR124_SET_REG(base) ((base)->CCGR124_SET) +#define CCM_CCGR124_CLR_REG(base) ((base)->CCGR124_CLR) +#define CCM_CCGR124_TOG_REG(base) ((base)->CCGR124_TOG) +#define CCM_CCGR125_REG(base) ((base)->CCGR125) +#define CCM_CCGR125_SET_REG(base) ((base)->CCGR125_SET) +#define CCM_CCGR125_CLR_REG(base) ((base)->CCGR125_CLR) +#define CCM_CCGR125_TOG_REG(base) ((base)->CCGR125_TOG) +#define CCM_CCGR126_REG(base) ((base)->CCGR126) +#define CCM_CCGR126_SET_REG(base) ((base)->CCGR126_SET) +#define CCM_CCGR126_CLR_REG(base) ((base)->CCGR126_CLR) +#define CCM_CCGR126_TOG_REG(base) ((base)->CCGR126_TOG) +#define CCM_CCGR127_REG(base) ((base)->CCGR127) +#define CCM_CCGR127_SET_REG(base) ((base)->CCGR127_SET) +#define CCM_CCGR127_CLR_REG(base) ((base)->CCGR127_CLR) +#define CCM_CCGR127_TOG_REG(base) ((base)->CCGR127_TOG) +#define CCM_CCGR128_REG(base) ((base)->CCGR128) +#define CCM_CCGR128_SET_REG(base) ((base)->CCGR128_SET) +#define CCM_CCGR128_CLR_REG(base) ((base)->CCGR128_CLR) +#define CCM_CCGR128_TOG_REG(base) ((base)->CCGR128_TOG) +#define CCM_CCGR129_REG(base) ((base)->CCGR129) +#define CCM_CCGR129_SET_REG(base) ((base)->CCGR129_SET) +#define CCM_CCGR129_CLR_REG(base) ((base)->CCGR129_CLR) +#define CCM_CCGR129_TOG_REG(base) ((base)->CCGR129_TOG) +#define CCM_CCGR130_REG(base) ((base)->CCGR130) +#define CCM_CCGR130_SET_REG(base) ((base)->CCGR130_SET) +#define CCM_CCGR130_CLR_REG(base) ((base)->CCGR130_CLR) +#define CCM_CCGR130_TOG_REG(base) ((base)->CCGR130_TOG) +#define CCM_CCGR131_REG(base) ((base)->CCGR131) +#define CCM_CCGR131_SET_REG(base) ((base)->CCGR131_SET) +#define CCM_CCGR131_CLR_REG(base) ((base)->CCGR131_CLR) +#define CCM_CCGR131_TOG_REG(base) ((base)->CCGR131_TOG) +#define CCM_CCGR132_REG(base) ((base)->CCGR132) +#define CCM_CCGR132_SET_REG(base) ((base)->CCGR132_SET) +#define CCM_CCGR132_CLR_REG(base) ((base)->CCGR132_CLR) +#define CCM_CCGR132_TOG_REG(base) ((base)->CCGR132_TOG) +#define CCM_CCGR133_REG(base) ((base)->CCGR133) +#define CCM_CCGR133_SET_REG(base) ((base)->CCGR133_SET) +#define CCM_CCGR133_CLR_REG(base) ((base)->CCGR133_CLR) +#define CCM_CCGR133_TOG_REG(base) ((base)->CCGR133_TOG) +#define CCM_CCGR134_REG(base) ((base)->CCGR134) +#define CCM_CCGR134_SET_REG(base) ((base)->CCGR134_SET) +#define CCM_CCGR134_CLR_REG(base) ((base)->CCGR134_CLR) +#define CCM_CCGR134_TOG_REG(base) ((base)->CCGR134_TOG) +#define CCM_CCGR135_REG(base) ((base)->CCGR135) +#define CCM_CCGR135_SET_REG(base) ((base)->CCGR135_SET) +#define CCM_CCGR135_CLR_REG(base) ((base)->CCGR135_CLR) +#define CCM_CCGR135_TOG_REG(base) ((base)->CCGR135_TOG) +#define CCM_CCGR136_REG(base) ((base)->CCGR136) +#define CCM_CCGR136_SET_REG(base) ((base)->CCGR136_SET) +#define CCM_CCGR136_CLR_REG(base) ((base)->CCGR136_CLR) +#define CCM_CCGR136_TOG_REG(base) ((base)->CCGR136_TOG) +#define CCM_CCGR137_REG(base) ((base)->CCGR137) +#define CCM_CCGR137_SET_REG(base) ((base)->CCGR137_SET) +#define CCM_CCGR137_CLR_REG(base) ((base)->CCGR137_CLR) +#define CCM_CCGR137_TOG_REG(base) ((base)->CCGR137_TOG) +#define CCM_CCGR138_REG(base) ((base)->CCGR138) +#define CCM_CCGR138_SET_REG(base) ((base)->CCGR138_SET) +#define CCM_CCGR138_CLR_REG(base) ((base)->CCGR138_CLR) +#define CCM_CCGR138_TOG_REG(base) ((base)->CCGR138_TOG) +#define CCM_CCGR139_REG(base) ((base)->CCGR139) +#define CCM_CCGR139_SET_REG(base) ((base)->CCGR139_SET) +#define CCM_CCGR139_CLR_REG(base) ((base)->CCGR139_CLR) +#define CCM_CCGR139_TOG_REG(base) ((base)->CCGR139_TOG) +#define CCM_CCGR140_REG(base) ((base)->CCGR140) +#define CCM_CCGR140_SET_REG(base) ((base)->CCGR140_SET) +#define CCM_CCGR140_CLR_REG(base) ((base)->CCGR140_CLR) +#define CCM_CCGR140_TOG_REG(base) ((base)->CCGR140_TOG) +#define CCM_CCGR141_REG(base) ((base)->CCGR141) +#define CCM_CCGR141_SET_REG(base) ((base)->CCGR141_SET) +#define CCM_CCGR141_CLR_REG(base) ((base)->CCGR141_CLR) +#define CCM_CCGR141_TOG_REG(base) ((base)->CCGR141_TOG) +#define CCM_CCGR142_REG(base) ((base)->CCGR142) +#define CCM_CCGR142_SET_REG(base) ((base)->CCGR142_SET) +#define CCM_CCGR142_CLR_REG(base) ((base)->CCGR142_CLR) +#define CCM_CCGR142_TOG_REG(base) ((base)->CCGR142_TOG) +#define CCM_CCGR143_REG(base) ((base)->CCGR143) +#define CCM_CCGR143_SET_REG(base) ((base)->CCGR143_SET) +#define CCM_CCGR143_CLR_REG(base) ((base)->CCGR143_CLR) +#define CCM_CCGR143_TOG_REG(base) ((base)->CCGR143_TOG) +#define CCM_CCGR144_REG(base) ((base)->CCGR144) +#define CCM_CCGR144_SET_REG(base) ((base)->CCGR144_SET) +#define CCM_CCGR144_CLR_REG(base) ((base)->CCGR144_CLR) +#define CCM_CCGR144_TOG_REG(base) ((base)->CCGR144_TOG) +#define CCM_CCGR145_REG(base) ((base)->CCGR145) +#define CCM_CCGR145_SET_REG(base) ((base)->CCGR145_SET) +#define CCM_CCGR145_CLR_REG(base) ((base)->CCGR145_CLR) +#define CCM_CCGR145_TOG_REG(base) ((base)->CCGR145_TOG) +#define CCM_CCGR146_REG(base) ((base)->CCGR146) +#define CCM_CCGR146_SET_REG(base) ((base)->CCGR146_SET) +#define CCM_CCGR146_CLR_REG(base) ((base)->CCGR146_CLR) +#define CCM_CCGR146_TOG_REG(base) ((base)->CCGR146_TOG) +#define CCM_CCGR147_REG(base) ((base)->CCGR147) +#define CCM_CCGR147_SET_REG(base) ((base)->CCGR147_SET) +#define CCM_CCGR147_CLR_REG(base) ((base)->CCGR147_CLR) +#define CCM_CCGR147_TOG_REG(base) ((base)->CCGR147_TOG) +#define CCM_CCGR148_REG(base) ((base)->CCGR148) +#define CCM_CCGR148_SET_REG(base) ((base)->CCGR148_SET) +#define CCM_CCGR148_CLR_REG(base) ((base)->CCGR148_CLR) +#define CCM_CCGR148_TOG_REG(base) ((base)->CCGR148_TOG) +#define CCM_CCGR149_REG(base) ((base)->CCGR149) +#define CCM_CCGR149_SET_REG(base) ((base)->CCGR149_SET) +#define CCM_CCGR149_CLR_REG(base) ((base)->CCGR149_CLR) +#define CCM_CCGR149_TOG_REG(base) ((base)->CCGR149_TOG) +#define CCM_CCGR150_REG(base) ((base)->CCGR150) +#define CCM_CCGR150_SET_REG(base) ((base)->CCGR150_SET) +#define CCM_CCGR150_CLR_REG(base) ((base)->CCGR150_CLR) +#define CCM_CCGR150_TOG_REG(base) ((base)->CCGR150_TOG) +#define CCM_CCGR151_REG(base) ((base)->CCGR151) +#define CCM_CCGR151_SET_REG(base) ((base)->CCGR151_SET) +#define CCM_CCGR151_CLR_REG(base) ((base)->CCGR151_CLR) +#define CCM_CCGR151_TOG_REG(base) ((base)->CCGR151_TOG) +#define CCM_CCGR152_REG(base) ((base)->CCGR152) +#define CCM_CCGR152_SET_REG(base) ((base)->CCGR152_SET) +#define CCM_CCGR152_CLR_REG(base) ((base)->CCGR152_CLR) +#define CCM_CCGR152_TOG_REG(base) ((base)->CCGR152_TOG) +#define CCM_CCGR153_REG(base) ((base)->CCGR153) +#define CCM_CCGR153_SET_REG(base) ((base)->CCGR153_SET) +#define CCM_CCGR153_CLR_REG(base) ((base)->CCGR153_CLR) +#define CCM_CCGR153_TOG_REG(base) ((base)->CCGR153_TOG) +#define CCM_CCGR154_REG(base) ((base)->CCGR154) +#define CCM_CCGR154_SET_REG(base) ((base)->CCGR154_SET) +#define CCM_CCGR154_CLR_REG(base) ((base)->CCGR154_CLR) +#define CCM_CCGR154_TOG_REG(base) ((base)->CCGR154_TOG) +#define CCM_CCGR155_REG(base) ((base)->CCGR155) +#define CCM_CCGR155_SET_REG(base) ((base)->CCGR155_SET) +#define CCM_CCGR155_CLR_REG(base) ((base)->CCGR155_CLR) +#define CCM_CCGR155_TOG_REG(base) ((base)->CCGR155_TOG) +#define CCM_CCGR156_REG(base) ((base)->CCGR156) +#define CCM_CCGR156_SET_REG(base) ((base)->CCGR156_SET) +#define CCM_CCGR156_CLR_REG(base) ((base)->CCGR156_CLR) +#define CCM_CCGR156_TOG_REG(base) ((base)->CCGR156_TOG) +#define CCM_CCGR157_REG(base) ((base)->CCGR157) +#define CCM_CCGR157_SET_REG(base) ((base)->CCGR157_SET) +#define CCM_CCGR157_CLR_REG(base) ((base)->CCGR157_CLR) +#define CCM_CCGR157_TOG_REG(base) ((base)->CCGR157_TOG) +#define CCM_CCGR158_REG(base) ((base)->CCGR158) +#define CCM_CCGR158_SET_REG(base) ((base)->CCGR158_SET) +#define CCM_CCGR158_CLR_REG(base) ((base)->CCGR158_CLR) +#define CCM_CCGR158_TOG_REG(base) ((base)->CCGR158_TOG) +#define CCM_CCGR159_REG(base) ((base)->CCGR159) +#define CCM_CCGR159_SET_REG(base) ((base)->CCGR159_SET) +#define CCM_CCGR159_CLR_REG(base) ((base)->CCGR159_CLR) +#define CCM_CCGR159_TOG_REG(base) ((base)->CCGR159_TOG) +#define CCM_CCGR160_REG(base) ((base)->CCGR160) +#define CCM_CCGR160_SET_REG(base) ((base)->CCGR160_SET) +#define CCM_CCGR160_CLR_REG(base) ((base)->CCGR160_CLR) +#define CCM_CCGR160_TOG_REG(base) ((base)->CCGR160_TOG) +#define CCM_CCGR161_REG(base) ((base)->CCGR161) +#define CCM_CCGR161_SET_REG(base) ((base)->CCGR161_SET) +#define CCM_CCGR161_CLR_REG(base) ((base)->CCGR161_CLR) +#define CCM_CCGR161_TOG_REG(base) ((base)->CCGR161_TOG) +#define CCM_CCGR162_REG(base) ((base)->CCGR162) +#define CCM_CCGR162_SET_REG(base) ((base)->CCGR162_SET) +#define CCM_CCGR162_CLR_REG(base) ((base)->CCGR162_CLR) +#define CCM_CCGR162_TOG_REG(base) ((base)->CCGR162_TOG) +#define CCM_CCGR163_REG(base) ((base)->CCGR163) +#define CCM_CCGR163_SET_REG(base) ((base)->CCGR163_SET) +#define CCM_CCGR163_CLR_REG(base) ((base)->CCGR163_CLR) +#define CCM_CCGR163_TOG_REG(base) ((base)->CCGR163_TOG) +#define CCM_CCGR164_REG(base) ((base)->CCGR164) +#define CCM_CCGR164_SET_REG(base) ((base)->CCGR164_SET) +#define CCM_CCGR164_CLR_REG(base) ((base)->CCGR164_CLR) +#define CCM_CCGR164_TOG_REG(base) ((base)->CCGR164_TOG) +#define CCM_CCGR165_REG(base) ((base)->CCGR165) +#define CCM_CCGR165_SET_REG(base) ((base)->CCGR165_SET) +#define CCM_CCGR165_CLR_REG(base) ((base)->CCGR165_CLR) +#define CCM_CCGR165_TOG_REG(base) ((base)->CCGR165_TOG) +#define CCM_CCGR166_REG(base) ((base)->CCGR166) +#define CCM_CCGR166_SET_REG(base) ((base)->CCGR166_SET) +#define CCM_CCGR166_CLR_REG(base) ((base)->CCGR166_CLR) +#define CCM_CCGR166_TOG_REG(base) ((base)->CCGR166_TOG) +#define CCM_CCGR167_REG(base) ((base)->CCGR167) +#define CCM_CCGR167_SET_REG(base) ((base)->CCGR167_SET) +#define CCM_CCGR167_CLR_REG(base) ((base)->CCGR167_CLR) +#define CCM_CCGR167_TOG_REG(base) ((base)->CCGR167_TOG) +#define CCM_CCGR168_REG(base) ((base)->CCGR168) +#define CCM_CCGR168_SET_REG(base) ((base)->CCGR168_SET) +#define CCM_CCGR168_CLR_REG(base) ((base)->CCGR168_CLR) +#define CCM_CCGR168_TOG_REG(base) ((base)->CCGR168_TOG) +#define CCM_CCGR169_REG(base) ((base)->CCGR169) +#define CCM_CCGR169_SET_REG(base) ((base)->CCGR169_SET) +#define CCM_CCGR169_CLR_REG(base) ((base)->CCGR169_CLR) +#define CCM_CCGR169_TOG_REG(base) ((base)->CCGR169_TOG) +#define CCM_CCGR170_REG(base) ((base)->CCGR170) +#define CCM_CCGR170_SET_REG(base) ((base)->CCGR170_SET) +#define CCM_CCGR170_CLR_REG(base) ((base)->CCGR170_CLR) +#define CCM_CCGR170_TOG_REG(base) ((base)->CCGR170_TOG) +#define CCM_CCGR171_REG(base) ((base)->CCGR171) +#define CCM_CCGR171_SET_REG(base) ((base)->CCGR171_SET) +#define CCM_CCGR171_CLR_REG(base) ((base)->CCGR171_CLR) +#define CCM_CCGR171_TOG_REG(base) ((base)->CCGR171_TOG) +#define CCM_CCGR172_REG(base) ((base)->CCGR172) +#define CCM_CCGR172_SET_REG(base) ((base)->CCGR172_SET) +#define CCM_CCGR172_CLR_REG(base) ((base)->CCGR172_CLR) +#define CCM_CCGR172_TOG_REG(base) ((base)->CCGR172_TOG) +#define CCM_CCGR173_REG(base) ((base)->CCGR173) +#define CCM_CCGR173_SET_REG(base) ((base)->CCGR173_SET) +#define CCM_CCGR173_CLR_REG(base) ((base)->CCGR173_CLR) +#define CCM_CCGR173_TOG_REG(base) ((base)->CCGR173_TOG) +#define CCM_CCGR174_REG(base) ((base)->CCGR174) +#define CCM_CCGR174_SET_REG(base) ((base)->CCGR174_SET) +#define CCM_CCGR174_CLR_REG(base) ((base)->CCGR174_CLR) +#define CCM_CCGR174_TOG_REG(base) ((base)->CCGR174_TOG) +#define CCM_CCGR175_REG(base) ((base)->CCGR175) +#define CCM_CCGR175_SET_REG(base) ((base)->CCGR175_SET) +#define CCM_CCGR175_CLR_REG(base) ((base)->CCGR175_CLR) +#define CCM_CCGR175_TOG_REG(base) ((base)->CCGR175_TOG) +#define CCM_CCGR176_REG(base) ((base)->CCGR176) +#define CCM_CCGR176_SET_REG(base) ((base)->CCGR176_SET) +#define CCM_CCGR176_CLR_REG(base) ((base)->CCGR176_CLR) +#define CCM_CCGR176_TOG_REG(base) ((base)->CCGR176_TOG) +#define CCM_CCGR177_REG(base) ((base)->CCGR177) +#define CCM_CCGR177_SET_REG(base) ((base)->CCGR177_SET) +#define CCM_CCGR177_CLR_REG(base) ((base)->CCGR177_CLR) +#define CCM_CCGR177_TOG_REG(base) ((base)->CCGR177_TOG) +#define CCM_CCGR178_REG(base) ((base)->CCGR178) +#define CCM_CCGR178_SET_REG(base) ((base)->CCGR178_SET) +#define CCM_CCGR178_CLR_REG(base) ((base)->CCGR178_CLR) +#define CCM_CCGR178_TOG_REG(base) ((base)->CCGR178_TOG) +#define CCM_CCGR179_REG(base) ((base)->CCGR179) +#define CCM_CCGR179_SET_REG(base) ((base)->CCGR179_SET) +#define CCM_CCGR179_CLR_REG(base) ((base)->CCGR179_CLR) +#define CCM_CCGR179_TOG_REG(base) ((base)->CCGR179_TOG) +#define CCM_CCGR180_REG(base) ((base)->CCGR180) +#define CCM_CCGR180_SET_REG(base) ((base)->CCGR180_SET) +#define CCM_CCGR180_CLR_REG(base) ((base)->CCGR180_CLR) +#define CCM_CCGR180_TOG_REG(base) ((base)->CCGR180_TOG) +#define CCM_CCGR181_REG(base) ((base)->CCGR181) +#define CCM_CCGR181_SET_REG(base) ((base)->CCGR181_SET) +#define CCM_CCGR181_CLR_REG(base) ((base)->CCGR181_CLR) +#define CCM_CCGR181_TOG_REG(base) ((base)->CCGR181_TOG) +#define CCM_CCGR182_REG(base) ((base)->CCGR182) +#define CCM_CCGR182_SET_REG(base) ((base)->CCGR182_SET) +#define CCM_CCGR182_CLR_REG(base) ((base)->CCGR182_CLR) +#define CCM_CCGR182_TOG_REG(base) ((base)->CCGR182_TOG) +#define CCM_CCGR183_REG(base) ((base)->CCGR183) +#define CCM_CCGR183_SET_REG(base) ((base)->CCGR183_SET) +#define CCM_CCGR183_CLR_REG(base) ((base)->CCGR183_CLR) +#define CCM_CCGR183_TOG_REG(base) ((base)->CCGR183_TOG) +#define CCM_CCGR184_REG(base) ((base)->CCGR184) +#define CCM_CCGR184_SET_REG(base) ((base)->CCGR184_SET) +#define CCM_CCGR184_CLR_REG(base) ((base)->CCGR184_CLR) +#define CCM_CCGR184_TOG_REG(base) ((base)->CCGR184_TOG) +#define CCM_CCGR185_REG(base) ((base)->CCGR185) +#define CCM_CCGR185_SET_REG(base) ((base)->CCGR185_SET) +#define CCM_CCGR185_CLR_REG(base) ((base)->CCGR185_CLR) +#define CCM_CCGR185_TOG_REG(base) ((base)->CCGR185_TOG) +#define CCM_CCGR186_REG(base) ((base)->CCGR186) +#define CCM_CCGR186_SET_REG(base) ((base)->CCGR186_SET) +#define CCM_CCGR186_CLR_REG(base) ((base)->CCGR186_CLR) +#define CCM_CCGR186_TOG_REG(base) ((base)->CCGR186_TOG) +#define CCM_CCGR187_REG(base) ((base)->CCGR187) +#define CCM_CCGR187_SET_REG(base) ((base)->CCGR187_SET) +#define CCM_CCGR187_CLR_REG(base) ((base)->CCGR187_CLR) +#define CCM_CCGR187_TOG_REG(base) ((base)->CCGR187_TOG) +#define CCM_CCGR188_REG(base) ((base)->CCGR188) +#define CCM_CCGR188_SET_REG(base) ((base)->CCGR188_SET) +#define CCM_CCGR188_CLR_REG(base) ((base)->CCGR188_CLR) +#define CCM_CCGR188_TOG_REG(base) ((base)->CCGR188_TOG) +#define CCM_CCGR189_REG(base) ((base)->CCGR189) +#define CCM_CCGR189_SET_REG(base) ((base)->CCGR189_SET) +#define CCM_CCGR189_CLR_REG(base) ((base)->CCGR189_CLR) +#define CCM_CCGR189_TOG_REG(base) ((base)->CCGR189_TOG) +#define CCM_CCGR190_REG(base) ((base)->CCGR190) +#define CCM_CCGR190_SET_REG(base) ((base)->CCGR190_SET) +#define CCM_CCGR190_CLR_REG(base) ((base)->CCGR190_CLR) +#define CCM_CCGR190_TOG_REG(base) ((base)->CCGR190_TOG) +#define CCM_TARGET_ROOT0_REG(base) ((base)->TARGET_ROOT0) +#define CCM_TARGET_ROOT0_SET_REG(base) ((base)->TARGET_ROOT0_SET) +#define CCM_TARGET_ROOT0_CLR_REG(base) ((base)->TARGET_ROOT0_CLR) +#define CCM_TARGET_ROOT0_TOG_REG(base) ((base)->TARGET_ROOT0_TOG) +#define CCM_POST0_REG(base) ((base)->POST0) +#define CCM_POST_ROOT0_SET_REG(base) ((base)->POST_ROOT0_SET) +#define CCM_POST_ROOT0_CLR_REG(base) ((base)->POST_ROOT0_CLR) +#define CCM_POST_ROOT0_TOG_REG(base) ((base)->POST_ROOT0_TOG) +#define CCM_PRE0_REG(base) ((base)->PRE0) +#define CCM_PRE_ROOT0_SET_REG(base) ((base)->PRE_ROOT0_SET) +#define CCM_PRE_ROOT0_CLR_REG(base) ((base)->PRE_ROOT0_CLR) +#define CCM_PRE_ROOT0_TOG_REG(base) ((base)->PRE_ROOT0_TOG) +#define CCM_ACCESS_CTRL0_REG(base) ((base)->ACCESS_CTRL0) +#define CCM_ACCESS_CTRL0_ROOT_SET_REG(base) ((base)->ACCESS_CTRL0_ROOT_SET) +#define CCM_ACCESS_CTRL0_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL0_ROOT_CLR) +#define CCM_ACCESS_CTRL0_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL0_ROOT_TOG) +#define CCM_TARGET_ROOT1_REG(base) ((base)->TARGET_ROOT1) +#define CCM_TARGET_ROOT1_SET_REG(base) ((base)->TARGET_ROOT1_SET) +#define CCM_TARGET_ROOT1_CLR_REG(base) ((base)->TARGET_ROOT1_CLR) +#define CCM_TARGET_ROOT1_TOG_REG(base) ((base)->TARGET_ROOT1_TOG) +#define CCM_POST1_REG(base) ((base)->POST1) +#define CCM_POST_ROOT1_SET_REG(base) ((base)->POST_ROOT1_SET) +#define CCM_POST_ROOT1_CLR_REG(base) ((base)->POST_ROOT1_CLR) +#define CCM_POST_ROOT1_TOG_REG(base) ((base)->POST_ROOT1_TOG) +#define CCM_PRE1_REG(base) ((base)->PRE1) +#define CCM_PRE_ROOT1_SET_REG(base) ((base)->PRE_ROOT1_SET) +#define CCM_PRE_ROOT1_CLR_REG(base) ((base)->PRE_ROOT1_CLR) +#define CCM_PRE_ROOT1_TOG_REG(base) ((base)->PRE_ROOT1_TOG) +#define CCM_ACCESS_CTRL1_REG(base) ((base)->ACCESS_CTRL1) +#define CCM_ACCESS_CTRL1_ROOT_SET_REG(base) ((base)->ACCESS_CTRL1_ROOT_SET) +#define CCM_ACCESS_CTRL1_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL1_ROOT_CLR) +#define CCM_ACCESS_CTRL1_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL1_ROOT_TOG) +#define CCM_TARGET_ROOT2_REG(base) ((base)->TARGET_ROOT2) +#define CCM_TARGET_ROOT2_SET_REG(base) ((base)->TARGET_ROOT2_SET) +#define CCM_TARGET_ROOT2_CLR_REG(base) ((base)->TARGET_ROOT2_CLR) +#define CCM_TARGET_ROOT2_TOG_REG(base) ((base)->TARGET_ROOT2_TOG) +#define CCM_POST2_REG(base) ((base)->POST2) +#define CCM_POST_ROOT2_SET_REG(base) ((base)->POST_ROOT2_SET) +#define CCM_POST_ROOT2_CLR_REG(base) ((base)->POST_ROOT2_CLR) +#define CCM_POST_ROOT2_TOG_REG(base) ((base)->POST_ROOT2_TOG) +#define CCM_PRE2_REG(base) ((base)->PRE2) +#define CCM_PRE_ROOT2_SET_REG(base) ((base)->PRE_ROOT2_SET) +#define CCM_PRE_ROOT2_CLR_REG(base) ((base)->PRE_ROOT2_CLR) +#define CCM_PRE_ROOT2_TOG_REG(base) ((base)->PRE_ROOT2_TOG) +#define CCM_ACCESS_CTRL2_REG(base) ((base)->ACCESS_CTRL2) +#define CCM_ACCESS_CTRL2_ROOT_SET_REG(base) ((base)->ACCESS_CTRL2_ROOT_SET) +#define CCM_ACCESS_CTRL2_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL2_ROOT_CLR) +#define CCM_ACCESS_CTRL2_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL2_ROOT_TOG) +#define CCM_TARGET_ROOT3_REG(base) ((base)->TARGET_ROOT3) +#define CCM_TARGET_ROOT3_SET_REG(base) ((base)->TARGET_ROOT3_SET) +#define CCM_TARGET_ROOT3_CLR_REG(base) ((base)->TARGET_ROOT3_CLR) +#define CCM_TARGET_ROOT3_TOG_REG(base) ((base)->TARGET_ROOT3_TOG) +#define CCM_POST3_REG(base) ((base)->POST3) +#define CCM_POST_ROOT3_SET_REG(base) ((base)->POST_ROOT3_SET) +#define CCM_POST_ROOT3_CLR_REG(base) ((base)->POST_ROOT3_CLR) +#define CCM_POST_ROOT3_TOG_REG(base) ((base)->POST_ROOT3_TOG) +#define CCM_PRE3_REG(base) ((base)->PRE3) +#define CCM_PRE_ROOT3_SET_REG(base) ((base)->PRE_ROOT3_SET) +#define CCM_PRE_ROOT3_CLR_REG(base) ((base)->PRE_ROOT3_CLR) +#define CCM_PRE_ROOT3_TOG_REG(base) ((base)->PRE_ROOT3_TOG) +#define CCM_ACCESS_CTRL3_REG(base) ((base)->ACCESS_CTRL3) +#define CCM_ACCESS_CTRL3_ROOT_SET_REG(base) ((base)->ACCESS_CTRL3_ROOT_SET) +#define CCM_ACCESS_CTRL3_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL3_ROOT_CLR) +#define CCM_ACCESS_CTRL3_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL3_ROOT_TOG) +#define CCM_TARGET_ROOT4_REG(base) ((base)->TARGET_ROOT4) +#define CCM_TARGET_ROOT4_SET_REG(base) ((base)->TARGET_ROOT4_SET) +#define CCM_TARGET_ROOT4_CLR_REG(base) ((base)->TARGET_ROOT4_CLR) +#define CCM_TARGET_ROOT4_TOG_REG(base) ((base)->TARGET_ROOT4_TOG) +#define CCM_POST4_REG(base) ((base)->POST4) +#define CCM_POST_ROOT4_SET_REG(base) ((base)->POST_ROOT4_SET) +#define CCM_POST_ROOT4_CLR_REG(base) ((base)->POST_ROOT4_CLR) +#define CCM_POST_ROOT4_TOG_REG(base) ((base)->POST_ROOT4_TOG) +#define CCM_PRE4_REG(base) ((base)->PRE4) +#define CCM_PRE_ROOT4_SET_REG(base) ((base)->PRE_ROOT4_SET) +#define CCM_PRE_ROOT4_CLR_REG(base) ((base)->PRE_ROOT4_CLR) +#define CCM_PRE_ROOT4_TOG_REG(base) ((base)->PRE_ROOT4_TOG) +#define CCM_ACCESS_CTRL4_REG(base) ((base)->ACCESS_CTRL4) +#define CCM_ACCESS_CTRL4_ROOT_SET_REG(base) ((base)->ACCESS_CTRL4_ROOT_SET) +#define CCM_ACCESS_CTRL4_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL4_ROOT_CLR) +#define CCM_ACCESS_CTRL4_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL4_ROOT_TOG) +#define CCM_TARGET_ROOT5_REG(base) ((base)->TARGET_ROOT5) +#define CCM_TARGET_ROOT5_SET_REG(base) ((base)->TARGET_ROOT5_SET) +#define CCM_TARGET_ROOT5_CLR_REG(base) ((base)->TARGET_ROOT5_CLR) +#define CCM_TARGET_ROOT5_TOG_REG(base) ((base)->TARGET_ROOT5_TOG) +#define CCM_POST5_REG(base) ((base)->POST5) +#define CCM_POST_ROOT5_SET_REG(base) ((base)->POST_ROOT5_SET) +#define CCM_POST_ROOT5_CLR_REG(base) ((base)->POST_ROOT5_CLR) +#define CCM_POST_ROOT5_TOG_REG(base) ((base)->POST_ROOT5_TOG) +#define CCM_PRE5_REG(base) ((base)->PRE5) +#define CCM_PRE_ROOT5_SET_REG(base) ((base)->PRE_ROOT5_SET) +#define CCM_PRE_ROOT5_CLR_REG(base) ((base)->PRE_ROOT5_CLR) +#define CCM_PRE_ROOT5_TOG_REG(base) ((base)->PRE_ROOT5_TOG) +#define CCM_ACCESS_CTRL5_REG(base) ((base)->ACCESS_CTRL5) +#define CCM_ACCESS_CTRL5_ROOT_SET_REG(base) ((base)->ACCESS_CTRL5_ROOT_SET) +#define CCM_ACCESS_CTRL5_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL5_ROOT_CLR) +#define CCM_ACCESS_CTRL5_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL5_ROOT_TOG) +#define CCM_TARGET_ROOT6_REG(base) ((base)->TARGET_ROOT6) +#define CCM_TARGET_ROOT6_SET_REG(base) ((base)->TARGET_ROOT6_SET) +#define CCM_TARGET_ROOT6_CLR_REG(base) ((base)->TARGET_ROOT6_CLR) +#define CCM_TARGET_ROOT6_TOG_REG(base) ((base)->TARGET_ROOT6_TOG) +#define CCM_POST6_REG(base) ((base)->POST6) +#define CCM_POST_ROOT6_SET_REG(base) ((base)->POST_ROOT6_SET) +#define CCM_POST_ROOT6_CLR_REG(base) ((base)->POST_ROOT6_CLR) +#define CCM_POST_ROOT6_TOG_REG(base) ((base)->POST_ROOT6_TOG) +#define CCM_PRE6_REG(base) ((base)->PRE6) +#define CCM_PRE_ROOT6_SET_REG(base) ((base)->PRE_ROOT6_SET) +#define CCM_PRE_ROOT6_CLR_REG(base) ((base)->PRE_ROOT6_CLR) +#define CCM_PRE_ROOT6_TOG_REG(base) ((base)->PRE_ROOT6_TOG) +#define CCM_ACCESS_CTRL6_REG(base) ((base)->ACCESS_CTRL6) +#define CCM_ACCESS_CTRL6_ROOT_SET_REG(base) ((base)->ACCESS_CTRL6_ROOT_SET) +#define CCM_ACCESS_CTRL6_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL6_ROOT_CLR) +#define CCM_ACCESS_CTRL6_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL6_ROOT_TOG) +#define CCM_TARGET_ROOT7_REG(base) ((base)->TARGET_ROOT7) +#define CCM_TARGET_ROOT7_SET_REG(base) ((base)->TARGET_ROOT7_SET) +#define CCM_TARGET_ROOT7_CLR_REG(base) ((base)->TARGET_ROOT7_CLR) +#define CCM_TARGET_ROOT7_TOG_REG(base) ((base)->TARGET_ROOT7_TOG) +#define CCM_POST7_REG(base) ((base)->POST7) +#define CCM_POST_ROOT7_SET_REG(base) ((base)->POST_ROOT7_SET) +#define CCM_POST_ROOT7_CLR_REG(base) ((base)->POST_ROOT7_CLR) +#define CCM_POST_ROOT7_TOG_REG(base) ((base)->POST_ROOT7_TOG) +#define CCM_PRE7_REG(base) ((base)->PRE7) +#define CCM_PRE_ROOT7_SET_REG(base) ((base)->PRE_ROOT7_SET) +#define CCM_PRE_ROOT7_CLR_REG(base) ((base)->PRE_ROOT7_CLR) +#define CCM_PRE_ROOT7_TOG_REG(base) ((base)->PRE_ROOT7_TOG) +#define CCM_ACCESS_CTRL7_REG(base) ((base)->ACCESS_CTRL7) +#define CCM_ACCESS_CTRL7_ROOT_SET_REG(base) ((base)->ACCESS_CTRL7_ROOT_SET) +#define CCM_ACCESS_CTRL7_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL7_ROOT_CLR) +#define CCM_ACCESS_CTRL7_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL7_ROOT_TOG) +#define CCM_TARGET_ROOT8_REG(base) ((base)->TARGET_ROOT8) +#define CCM_TARGET_ROOT8_SET_REG(base) ((base)->TARGET_ROOT8_SET) +#define CCM_TARGET_ROOT8_CLR_REG(base) ((base)->TARGET_ROOT8_CLR) +#define CCM_TARGET_ROOT8_TOG_REG(base) ((base)->TARGET_ROOT8_TOG) +#define CCM_POST8_REG(base) ((base)->POST8) +#define CCM_POST_ROOT8_SET_REG(base) ((base)->POST_ROOT8_SET) +#define CCM_POST_ROOT8_CLR_REG(base) ((base)->POST_ROOT8_CLR) +#define CCM_POST_ROOT8_TOG_REG(base) ((base)->POST_ROOT8_TOG) +#define CCM_PRE8_REG(base) ((base)->PRE8) +#define CCM_PRE_ROOT8_SET_REG(base) ((base)->PRE_ROOT8_SET) +#define CCM_PRE_ROOT8_CLR_REG(base) ((base)->PRE_ROOT8_CLR) +#define CCM_PRE_ROOT8_TOG_REG(base) ((base)->PRE_ROOT8_TOG) +#define CCM_ACCESS_CTRL8_REG(base) ((base)->ACCESS_CTRL8) +#define CCM_ACCESS_CTRL8_ROOT_SET_REG(base) ((base)->ACCESS_CTRL8_ROOT_SET) +#define CCM_ACCESS_CTRL8_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL8_ROOT_CLR) +#define CCM_ACCESS_CTRL8_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL8_ROOT_TOG) +#define CCM_TARGET_ROOT9_REG(base) ((base)->TARGET_ROOT9) +#define CCM_TARGET_ROOT9_SET_REG(base) ((base)->TARGET_ROOT9_SET) +#define CCM_TARGET_ROOT9_CLR_REG(base) ((base)->TARGET_ROOT9_CLR) +#define CCM_TARGET_ROOT9_TOG_REG(base) ((base)->TARGET_ROOT9_TOG) +#define CCM_POST9_REG(base) ((base)->POST9) +#define CCM_POST_ROOT9_SET_REG(base) ((base)->POST_ROOT9_SET) +#define CCM_POST_ROOT9_CLR_REG(base) ((base)->POST_ROOT9_CLR) +#define CCM_POST_ROOT9_TOG_REG(base) ((base)->POST_ROOT9_TOG) +#define CCM_PRE9_REG(base) ((base)->PRE9) +#define CCM_PRE_ROOT9_SET_REG(base) ((base)->PRE_ROOT9_SET) +#define CCM_PRE_ROOT9_CLR_REG(base) ((base)->PRE_ROOT9_CLR) +#define CCM_PRE_ROOT9_TOG_REG(base) ((base)->PRE_ROOT9_TOG) +#define CCM_ACCESS_CTRL9_REG(base) ((base)->ACCESS_CTRL9) +#define CCM_ACCESS_CTRL9_ROOT_SET_REG(base) ((base)->ACCESS_CTRL9_ROOT_SET) +#define CCM_ACCESS_CTRL9_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL9_ROOT_CLR) +#define CCM_ACCESS_CTRL9_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL9_ROOT_TOG) +#define CCM_TARGET_ROOT10_REG(base) ((base)->TARGET_ROOT10) +#define CCM_TARGET_ROOT10_SET_REG(base) ((base)->TARGET_ROOT10_SET) +#define CCM_TARGET_ROOT10_CLR_REG(base) ((base)->TARGET_ROOT10_CLR) +#define CCM_TARGET_ROOT10_TOG_REG(base) ((base)->TARGET_ROOT10_TOG) +#define CCM_POST10_REG(base) ((base)->POST10) +#define CCM_POST_ROOT10_SET_REG(base) ((base)->POST_ROOT10_SET) +#define CCM_POST_ROOT10_CLR_REG(base) ((base)->POST_ROOT10_CLR) +#define CCM_POST_ROOT10_TOG_REG(base) ((base)->POST_ROOT10_TOG) +#define CCM_PRE10_REG(base) ((base)->PRE10) +#define CCM_PRE_ROOT10_SET_REG(base) ((base)->PRE_ROOT10_SET) +#define CCM_PRE_ROOT10_CLR_REG(base) ((base)->PRE_ROOT10_CLR) +#define CCM_PRE_ROOT10_TOG_REG(base) ((base)->PRE_ROOT10_TOG) +#define CCM_ACCESS_CTRL10_REG(base) ((base)->ACCESS_CTRL10) +#define CCM_ACCESS_CTRL10_ROOT_SET_REG(base) ((base)->ACCESS_CTRL10_ROOT_SET) +#define CCM_ACCESS_CTRL10_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL10_ROOT_CLR) +#define CCM_ACCESS_CTRL10_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL10_ROOT_TOG) +#define CCM_TARGET_ROOT11_REG(base) ((base)->TARGET_ROOT11) +#define CCM_TARGET_ROOT11_SET_REG(base) ((base)->TARGET_ROOT11_SET) +#define CCM_TARGET_ROOT11_CLR_REG(base) ((base)->TARGET_ROOT11_CLR) +#define CCM_TARGET_ROOT11_TOG_REG(base) ((base)->TARGET_ROOT11_TOG) +#define CCM_POST11_REG(base) ((base)->POST11) +#define CCM_POST_ROOT11_SET_REG(base) ((base)->POST_ROOT11_SET) +#define CCM_POST_ROOT11_CLR_REG(base) ((base)->POST_ROOT11_CLR) +#define CCM_POST_ROOT11_TOG_REG(base) ((base)->POST_ROOT11_TOG) +#define CCM_PRE11_REG(base) ((base)->PRE11) +#define CCM_PRE_ROOT11_SET_REG(base) ((base)->PRE_ROOT11_SET) +#define CCM_PRE_ROOT11_CLR_REG(base) ((base)->PRE_ROOT11_CLR) +#define CCM_PRE_ROOT11_TOG_REG(base) ((base)->PRE_ROOT11_TOG) +#define CCM_ACCESS_CTRL11_REG(base) ((base)->ACCESS_CTRL11) +#define CCM_ACCESS_CTRL11_ROOT_SET_REG(base) ((base)->ACCESS_CTRL11_ROOT_SET) +#define CCM_ACCESS_CTRL11_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL11_ROOT_CLR) +#define CCM_ACCESS_CTRL11_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL11_ROOT_TOG) +#define CCM_TARGET_ROOT12_REG(base) ((base)->TARGET_ROOT12) +#define CCM_TARGET_ROOT12_SET_REG(base) ((base)->TARGET_ROOT12_SET) +#define CCM_TARGET_ROOT12_CLR_REG(base) ((base)->TARGET_ROOT12_CLR) +#define CCM_TARGET_ROOT12_TOG_REG(base) ((base)->TARGET_ROOT12_TOG) +#define CCM_POST12_REG(base) ((base)->POST12) +#define CCM_POST_ROOT12_SET_REG(base) ((base)->POST_ROOT12_SET) +#define CCM_POST_ROOT12_CLR_REG(base) ((base)->POST_ROOT12_CLR) +#define CCM_POST_ROOT12_TOG_REG(base) ((base)->POST_ROOT12_TOG) +#define CCM_PRE12_REG(base) ((base)->PRE12) +#define CCM_PRE_ROOT12_SET_REG(base) ((base)->PRE_ROOT12_SET) +#define CCM_PRE_ROOT12_CLR_REG(base) ((base)->PRE_ROOT12_CLR) +#define CCM_PRE_ROOT12_TOG_REG(base) ((base)->PRE_ROOT12_TOG) +#define CCM_ACCESS_CTRL12_REG(base) ((base)->ACCESS_CTRL12) +#define CCM_ACCESS_CTRL12_ROOT_SET_REG(base) ((base)->ACCESS_CTRL12_ROOT_SET) +#define CCM_ACCESS_CTRL12_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL12_ROOT_CLR) +#define CCM_ACCESS_CTRL12_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL12_ROOT_TOG) +#define CCM_TARGET_ROOT13_REG(base) ((base)->TARGET_ROOT13) +#define CCM_TARGET_ROOT13_SET_REG(base) ((base)->TARGET_ROOT13_SET) +#define CCM_TARGET_ROOT13_CLR_REG(base) ((base)->TARGET_ROOT13_CLR) +#define CCM_TARGET_ROOT13_TOG_REG(base) ((base)->TARGET_ROOT13_TOG) +#define CCM_POST13_REG(base) ((base)->POST13) +#define CCM_POST_ROOT13_SET_REG(base) ((base)->POST_ROOT13_SET) +#define CCM_POST_ROOT13_CLR_REG(base) ((base)->POST_ROOT13_CLR) +#define CCM_POST_ROOT13_TOG_REG(base) ((base)->POST_ROOT13_TOG) +#define CCM_PRE13_REG(base) ((base)->PRE13) +#define CCM_PRE_ROOT13_SET_REG(base) ((base)->PRE_ROOT13_SET) +#define CCM_PRE_ROOT13_CLR_REG(base) ((base)->PRE_ROOT13_CLR) +#define CCM_PRE_ROOT13_TOG_REG(base) ((base)->PRE_ROOT13_TOG) +#define CCM_ACCESS_CTRL13_REG(base) ((base)->ACCESS_CTRL13) +#define CCM_ACCESS_CTRL13_ROOT_SET_REG(base) ((base)->ACCESS_CTRL13_ROOT_SET) +#define CCM_ACCESS_CTRL13_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL13_ROOT_CLR) +#define CCM_ACCESS_CTRL13_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL13_ROOT_TOG) +#define CCM_TARGET_ROOT14_REG(base) ((base)->TARGET_ROOT14) +#define CCM_TARGET_ROOT14_SET_REG(base) ((base)->TARGET_ROOT14_SET) +#define CCM_TARGET_ROOT14_CLR_REG(base) ((base)->TARGET_ROOT14_CLR) +#define CCM_TARGET_ROOT14_TOG_REG(base) ((base)->TARGET_ROOT14_TOG) +#define CCM_POST14_REG(base) ((base)->POST14) +#define CCM_POST_ROOT14_SET_REG(base) ((base)->POST_ROOT14_SET) +#define CCM_POST_ROOT14_CLR_REG(base) ((base)->POST_ROOT14_CLR) +#define CCM_POST_ROOT14_TOG_REG(base) ((base)->POST_ROOT14_TOG) +#define CCM_PRE14_REG(base) ((base)->PRE14) +#define CCM_PRE_ROOT14_SET_REG(base) ((base)->PRE_ROOT14_SET) +#define CCM_PRE_ROOT14_CLR_REG(base) ((base)->PRE_ROOT14_CLR) +#define CCM_PRE_ROOT14_TOG_REG(base) ((base)->PRE_ROOT14_TOG) +#define CCM_ACCESS_CTRL14_REG(base) ((base)->ACCESS_CTRL14) +#define CCM_ACCESS_CTRL14_ROOT_SET_REG(base) ((base)->ACCESS_CTRL14_ROOT_SET) +#define CCM_ACCESS_CTRL14_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL14_ROOT_CLR) +#define CCM_ACCESS_CTRL14_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL14_ROOT_TOG) +#define CCM_TARGET_ROOT15_REG(base) ((base)->TARGET_ROOT15) +#define CCM_TARGET_ROOT15_SET_REG(base) ((base)->TARGET_ROOT15_SET) +#define CCM_TARGET_ROOT15_CLR_REG(base) ((base)->TARGET_ROOT15_CLR) +#define CCM_TARGET_ROOT15_TOG_REG(base) ((base)->TARGET_ROOT15_TOG) +#define CCM_POST15_REG(base) ((base)->POST15) +#define CCM_POST_ROOT15_SET_REG(base) ((base)->POST_ROOT15_SET) +#define CCM_POST_ROOT15_CLR_REG(base) ((base)->POST_ROOT15_CLR) +#define CCM_POST_ROOT15_TOG_REG(base) ((base)->POST_ROOT15_TOG) +#define CCM_PRE15_REG(base) ((base)->PRE15) +#define CCM_PRE_ROOT15_SET_REG(base) ((base)->PRE_ROOT15_SET) +#define CCM_PRE_ROOT15_CLR_REG(base) ((base)->PRE_ROOT15_CLR) +#define CCM_PRE_ROOT15_TOG_REG(base) ((base)->PRE_ROOT15_TOG) +#define CCM_ACCESS_CTRL15_REG(base) ((base)->ACCESS_CTRL15) +#define CCM_ACCESS_CTRL15_ROOT_SET_REG(base) ((base)->ACCESS_CTRL15_ROOT_SET) +#define CCM_ACCESS_CTRL15_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL15_ROOT_CLR) +#define CCM_ACCESS_CTRL15_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL15_ROOT_TOG) +#define CCM_TARGET_ROOT16_REG(base) ((base)->TARGET_ROOT16) +#define CCM_TARGET_ROOT16_SET_REG(base) ((base)->TARGET_ROOT16_SET) +#define CCM_TARGET_ROOT16_CLR_REG(base) ((base)->TARGET_ROOT16_CLR) +#define CCM_TARGET_ROOT16_TOG_REG(base) ((base)->TARGET_ROOT16_TOG) +#define CCM_POST16_REG(base) ((base)->POST16) +#define CCM_POST_ROOT16_SET_REG(base) ((base)->POST_ROOT16_SET) +#define CCM_POST_ROOT16_CLR_REG(base) ((base)->POST_ROOT16_CLR) +#define CCM_POST_ROOT16_TOG_REG(base) ((base)->POST_ROOT16_TOG) +#define CCM_PRE16_REG(base) ((base)->PRE16) +#define CCM_PRE_ROOT16_SET_REG(base) ((base)->PRE_ROOT16_SET) +#define CCM_PRE_ROOT16_CLR_REG(base) ((base)->PRE_ROOT16_CLR) +#define CCM_PRE_ROOT16_TOG_REG(base) ((base)->PRE_ROOT16_TOG) +#define CCM_ACCESS_CTRL16_REG(base) ((base)->ACCESS_CTRL16) +#define CCM_ACCESS_CTRL16_ROOT_SET_REG(base) ((base)->ACCESS_CTRL16_ROOT_SET) +#define CCM_ACCESS_CTRL16_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL16_ROOT_CLR) +#define CCM_ACCESS_CTRL16_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL16_ROOT_TOG) +#define CCM_TARGET_ROOT17_REG(base) ((base)->TARGET_ROOT17) +#define CCM_TARGET_ROOT17_SET_REG(base) ((base)->TARGET_ROOT17_SET) +#define CCM_TARGET_ROOT17_CLR_REG(base) ((base)->TARGET_ROOT17_CLR) +#define CCM_TARGET_ROOT17_TOG_REG(base) ((base)->TARGET_ROOT17_TOG) +#define CCM_POST17_REG(base) ((base)->POST17) +#define CCM_POST_ROOT17_SET_REG(base) ((base)->POST_ROOT17_SET) +#define CCM_POST_ROOT17_CLR_REG(base) ((base)->POST_ROOT17_CLR) +#define CCM_POST_ROOT17_TOG_REG(base) ((base)->POST_ROOT17_TOG) +#define CCM_PRE17_REG(base) ((base)->PRE17) +#define CCM_PRE_ROOT17_SET_REG(base) ((base)->PRE_ROOT17_SET) +#define CCM_PRE_ROOT17_CLR_REG(base) ((base)->PRE_ROOT17_CLR) +#define CCM_PRE_ROOT17_TOG_REG(base) ((base)->PRE_ROOT17_TOG) +#define CCM_ACCESS_CTRL17_REG(base) ((base)->ACCESS_CTRL17) +#define CCM_ACCESS_CTRL17_ROOT_SET_REG(base) ((base)->ACCESS_CTRL17_ROOT_SET) +#define CCM_ACCESS_CTRL17_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL17_ROOT_CLR) +#define CCM_ACCESS_CTRL17_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL17_ROOT_TOG) +#define CCM_TARGET_ROOT18_REG(base) ((base)->TARGET_ROOT18) +#define CCM_TARGET_ROOT18_SET_REG(base) ((base)->TARGET_ROOT18_SET) +#define CCM_TARGET_ROOT18_CLR_REG(base) ((base)->TARGET_ROOT18_CLR) +#define CCM_TARGET_ROOT18_TOG_REG(base) ((base)->TARGET_ROOT18_TOG) +#define CCM_POST18_REG(base) ((base)->POST18) +#define CCM_POST_ROOT18_SET_REG(base) ((base)->POST_ROOT18_SET) +#define CCM_POST_ROOT18_CLR_REG(base) ((base)->POST_ROOT18_CLR) +#define CCM_POST_ROOT18_TOG_REG(base) ((base)->POST_ROOT18_TOG) +#define CCM_PRE18_REG(base) ((base)->PRE18) +#define CCM_PRE_ROOT18_SET_REG(base) ((base)->PRE_ROOT18_SET) +#define CCM_PRE_ROOT18_CLR_REG(base) ((base)->PRE_ROOT18_CLR) +#define CCM_PRE_ROOT18_TOG_REG(base) ((base)->PRE_ROOT18_TOG) +#define CCM_ACCESS_CTRL18_REG(base) ((base)->ACCESS_CTRL18) +#define CCM_ACCESS_CTRL18_ROOT_SET_REG(base) ((base)->ACCESS_CTRL18_ROOT_SET) +#define CCM_ACCESS_CTRL18_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL18_ROOT_CLR) +#define CCM_ACCESS_CTRL18_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL18_ROOT_TOG) +#define CCM_TARGET_ROOT19_REG(base) ((base)->TARGET_ROOT19) +#define CCM_TARGET_ROOT19_SET_REG(base) ((base)->TARGET_ROOT19_SET) +#define CCM_TARGET_ROOT19_CLR_REG(base) ((base)->TARGET_ROOT19_CLR) +#define CCM_TARGET_ROOT19_TOG_REG(base) ((base)->TARGET_ROOT19_TOG) +#define CCM_POST19_REG(base) ((base)->POST19) +#define CCM_POST_ROOT19_SET_REG(base) ((base)->POST_ROOT19_SET) +#define CCM_POST_ROOT19_CLR_REG(base) ((base)->POST_ROOT19_CLR) +#define CCM_POST_ROOT19_TOG_REG(base) ((base)->POST_ROOT19_TOG) +#define CCM_PRE19_REG(base) ((base)->PRE19) +#define CCM_PRE_ROOT19_SET_REG(base) ((base)->PRE_ROOT19_SET) +#define CCM_PRE_ROOT19_CLR_REG(base) ((base)->PRE_ROOT19_CLR) +#define CCM_PRE_ROOT19_TOG_REG(base) ((base)->PRE_ROOT19_TOG) +#define CCM_ACCESS_CTRL19_REG(base) ((base)->ACCESS_CTRL19) +#define CCM_ACCESS_CTRL19_ROOT_SET_REG(base) ((base)->ACCESS_CTRL19_ROOT_SET) +#define CCM_ACCESS_CTRL19_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL19_ROOT_CLR) +#define CCM_ACCESS_CTRL19_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL19_ROOT_TOG) +#define CCM_TARGET_ROOT20_REG(base) ((base)->TARGET_ROOT20) +#define CCM_TARGET_ROOT20_SET_REG(base) ((base)->TARGET_ROOT20_SET) +#define CCM_TARGET_ROOT20_CLR_REG(base) ((base)->TARGET_ROOT20_CLR) +#define CCM_TARGET_ROOT20_TOG_REG(base) ((base)->TARGET_ROOT20_TOG) +#define CCM_POST20_REG(base) ((base)->POST20) +#define CCM_POST_ROOT20_SET_REG(base) ((base)->POST_ROOT20_SET) +#define CCM_POST_ROOT20_CLR_REG(base) ((base)->POST_ROOT20_CLR) +#define CCM_POST_ROOT20_TOG_REG(base) ((base)->POST_ROOT20_TOG) +#define CCM_PRE20_REG(base) ((base)->PRE20) +#define CCM_PRE_ROOT20_SET_REG(base) ((base)->PRE_ROOT20_SET) +#define CCM_PRE_ROOT20_CLR_REG(base) ((base)->PRE_ROOT20_CLR) +#define CCM_PRE_ROOT20_TOG_REG(base) ((base)->PRE_ROOT20_TOG) +#define CCM_ACCESS_CTRL20_REG(base) ((base)->ACCESS_CTRL20) +#define CCM_ACCESS_CTRL20_ROOT_SET_REG(base) ((base)->ACCESS_CTRL20_ROOT_SET) +#define CCM_ACCESS_CTRL20_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL20_ROOT_CLR) +#define CCM_ACCESS_CTRL20_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL20_ROOT_TOG) +#define CCM_TARGET_ROOT21_REG(base) ((base)->TARGET_ROOT21) +#define CCM_TARGET_ROOT21_SET_REG(base) ((base)->TARGET_ROOT21_SET) +#define CCM_TARGET_ROOT21_CLR_REG(base) ((base)->TARGET_ROOT21_CLR) +#define CCM_TARGET_ROOT21_TOG_REG(base) ((base)->TARGET_ROOT21_TOG) +#define CCM_POST21_REG(base) ((base)->POST21) +#define CCM_POST_ROOT21_SET_REG(base) ((base)->POST_ROOT21_SET) +#define CCM_POST_ROOT21_CLR_REG(base) ((base)->POST_ROOT21_CLR) +#define CCM_POST_ROOT21_TOG_REG(base) ((base)->POST_ROOT21_TOG) +#define CCM_PRE21_REG(base) ((base)->PRE21) +#define CCM_PRE_ROOT21_SET_REG(base) ((base)->PRE_ROOT21_SET) +#define CCM_PRE_ROOT21_CLR_REG(base) ((base)->PRE_ROOT21_CLR) +#define CCM_PRE_ROOT21_TOG_REG(base) ((base)->PRE_ROOT21_TOG) +#define CCM_ACCESS_CTRL21_REG(base) ((base)->ACCESS_CTRL21) +#define CCM_ACCESS_CTRL21_ROOT_SET_REG(base) ((base)->ACCESS_CTRL21_ROOT_SET) +#define CCM_ACCESS_CTRL21_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL21_ROOT_CLR) +#define CCM_ACCESS_CTRL21_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL21_ROOT_TOG) +#define CCM_TARGET_ROOT22_REG(base) ((base)->TARGET_ROOT22) +#define CCM_TARGET_ROOT22_SET_REG(base) ((base)->TARGET_ROOT22_SET) +#define CCM_TARGET_ROOT22_CLR_REG(base) ((base)->TARGET_ROOT22_CLR) +#define CCM_TARGET_ROOT22_TOG_REG(base) ((base)->TARGET_ROOT22_TOG) +#define CCM_POST22_REG(base) ((base)->POST22) +#define CCM_POST_ROOT22_SET_REG(base) ((base)->POST_ROOT22_SET) +#define CCM_POST_ROOT22_CLR_REG(base) ((base)->POST_ROOT22_CLR) +#define CCM_POST_ROOT22_TOG_REG(base) ((base)->POST_ROOT22_TOG) +#define CCM_PRE22_REG(base) ((base)->PRE22) +#define CCM_PRE_ROOT22_SET_REG(base) ((base)->PRE_ROOT22_SET) +#define CCM_PRE_ROOT22_CLR_REG(base) ((base)->PRE_ROOT22_CLR) +#define CCM_PRE_ROOT22_TOG_REG(base) ((base)->PRE_ROOT22_TOG) +#define CCM_ACCESS_CTRL22_REG(base) ((base)->ACCESS_CTRL22) +#define CCM_ACCESS_CTRL22_ROOT_SET_REG(base) ((base)->ACCESS_CTRL22_ROOT_SET) +#define CCM_ACCESS_CTRL22_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL22_ROOT_CLR) +#define CCM_ACCESS_CTRL22_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL22_ROOT_TOG) +#define CCM_TARGET_ROOT23_REG(base) ((base)->TARGET_ROOT23) +#define CCM_TARGET_ROOT23_SET_REG(base) ((base)->TARGET_ROOT23_SET) +#define CCM_TARGET_ROOT23_CLR_REG(base) ((base)->TARGET_ROOT23_CLR) +#define CCM_TARGET_ROOT23_TOG_REG(base) ((base)->TARGET_ROOT23_TOG) +#define CCM_POST23_REG(base) ((base)->POST23) +#define CCM_POST_ROOT23_SET_REG(base) ((base)->POST_ROOT23_SET) +#define CCM_POST_ROOT23_CLR_REG(base) ((base)->POST_ROOT23_CLR) +#define CCM_POST_ROOT23_TOG_REG(base) ((base)->POST_ROOT23_TOG) +#define CCM_PRE23_REG(base) ((base)->PRE23) +#define CCM_PRE_ROOT23_SET_REG(base) ((base)->PRE_ROOT23_SET) +#define CCM_PRE_ROOT23_CLR_REG(base) ((base)->PRE_ROOT23_CLR) +#define CCM_PRE_ROOT23_TOG_REG(base) ((base)->PRE_ROOT23_TOG) +#define CCM_ACCESS_CTRL23_REG(base) ((base)->ACCESS_CTRL23) +#define CCM_ACCESS_CTRL23_ROOT_SET_REG(base) ((base)->ACCESS_CTRL23_ROOT_SET) +#define CCM_ACCESS_CTRL23_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL23_ROOT_CLR) +#define CCM_ACCESS_CTRL23_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL23_ROOT_TOG) +#define CCM_TARGET_ROOT24_REG(base) ((base)->TARGET_ROOT24) +#define CCM_TARGET_ROOT24_SET_REG(base) ((base)->TARGET_ROOT24_SET) +#define CCM_TARGET_ROOT24_CLR_REG(base) ((base)->TARGET_ROOT24_CLR) +#define CCM_TARGET_ROOT24_TOG_REG(base) ((base)->TARGET_ROOT24_TOG) +#define CCM_POST24_REG(base) ((base)->POST24) +#define CCM_POST_ROOT24_SET_REG(base) ((base)->POST_ROOT24_SET) +#define CCM_POST_ROOT24_CLR_REG(base) ((base)->POST_ROOT24_CLR) +#define CCM_POST_ROOT24_TOG_REG(base) ((base)->POST_ROOT24_TOG) +#define CCM_PRE24_REG(base) ((base)->PRE24) +#define CCM_PRE_ROOT24_SET_REG(base) ((base)->PRE_ROOT24_SET) +#define CCM_PRE_ROOT24_CLR_REG(base) ((base)->PRE_ROOT24_CLR) +#define CCM_PRE_ROOT24_TOG_REG(base) ((base)->PRE_ROOT24_TOG) +#define CCM_ACCESS_CTRL24_REG(base) ((base)->ACCESS_CTRL24) +#define CCM_ACCESS_CTRL24_ROOT_SET_REG(base) ((base)->ACCESS_CTRL24_ROOT_SET) +#define CCM_ACCESS_CTRL24_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL24_ROOT_CLR) +#define CCM_ACCESS_CTRL24_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL24_ROOT_TOG) +#define CCM_TARGET_ROOT25_REG(base) ((base)->TARGET_ROOT25) +#define CCM_TARGET_ROOT25_SET_REG(base) ((base)->TARGET_ROOT25_SET) +#define CCM_TARGET_ROOT25_CLR_REG(base) ((base)->TARGET_ROOT25_CLR) +#define CCM_TARGET_ROOT25_TOG_REG(base) ((base)->TARGET_ROOT25_TOG) +#define CCM_POST25_REG(base) ((base)->POST25) +#define CCM_POST_ROOT25_SET_REG(base) ((base)->POST_ROOT25_SET) +#define CCM_POST_ROOT25_CLR_REG(base) ((base)->POST_ROOT25_CLR) +#define CCM_POST_ROOT25_TOG_REG(base) ((base)->POST_ROOT25_TOG) +#define CCM_PRE25_REG(base) ((base)->PRE25) +#define CCM_PRE_ROOT25_SET_REG(base) ((base)->PRE_ROOT25_SET) +#define CCM_PRE_ROOT25_CLR_REG(base) ((base)->PRE_ROOT25_CLR) +#define CCM_PRE_ROOT25_TOG_REG(base) ((base)->PRE_ROOT25_TOG) +#define CCM_ACCESS_CTRL25_REG(base) ((base)->ACCESS_CTRL25) +#define CCM_ACCESS_CTRL25_ROOT_SET_REG(base) ((base)->ACCESS_CTRL25_ROOT_SET) +#define CCM_ACCESS_CTRL25_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL25_ROOT_CLR) +#define CCM_ACCESS_CTRL25_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL25_ROOT_TOG) +#define CCM_TARGET_ROOT26_REG(base) ((base)->TARGET_ROOT26) +#define CCM_TARGET_ROOT26_SET_REG(base) ((base)->TARGET_ROOT26_SET) +#define CCM_TARGET_ROOT26_CLR_REG(base) ((base)->TARGET_ROOT26_CLR) +#define CCM_TARGET_ROOT26_TOG_REG(base) ((base)->TARGET_ROOT26_TOG) +#define CCM_POST26_REG(base) ((base)->POST26) +#define CCM_POST_ROOT26_SET_REG(base) ((base)->POST_ROOT26_SET) +#define CCM_POST_ROOT26_CLR_REG(base) ((base)->POST_ROOT26_CLR) +#define CCM_POST_ROOT26_TOG_REG(base) ((base)->POST_ROOT26_TOG) +#define CCM_PRE26_REG(base) ((base)->PRE26) +#define CCM_PRE_ROOT26_SET_REG(base) ((base)->PRE_ROOT26_SET) +#define CCM_PRE_ROOT26_CLR_REG(base) ((base)->PRE_ROOT26_CLR) +#define CCM_PRE_ROOT26_TOG_REG(base) ((base)->PRE_ROOT26_TOG) +#define CCM_ACCESS_CTRL26_REG(base) ((base)->ACCESS_CTRL26) +#define CCM_ACCESS_CTRL26_ROOT_SET_REG(base) ((base)->ACCESS_CTRL26_ROOT_SET) +#define CCM_ACCESS_CTRL26_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL26_ROOT_CLR) +#define CCM_ACCESS_CTRL26_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL26_ROOT_TOG) +#define CCM_TARGET_ROOT27_REG(base) ((base)->TARGET_ROOT27) +#define CCM_TARGET_ROOT27_SET_REG(base) ((base)->TARGET_ROOT27_SET) +#define CCM_TARGET_ROOT27_CLR_REG(base) ((base)->TARGET_ROOT27_CLR) +#define CCM_TARGET_ROOT27_TOG_REG(base) ((base)->TARGET_ROOT27_TOG) +#define CCM_POST27_REG(base) ((base)->POST27) +#define CCM_POST_ROOT27_SET_REG(base) ((base)->POST_ROOT27_SET) +#define CCM_POST_ROOT27_CLR_REG(base) ((base)->POST_ROOT27_CLR) +#define CCM_POST_ROOT27_TOG_REG(base) ((base)->POST_ROOT27_TOG) +#define CCM_PRE27_REG(base) ((base)->PRE27) +#define CCM_PRE_ROOT27_SET_REG(base) ((base)->PRE_ROOT27_SET) +#define CCM_PRE_ROOT27_CLR_REG(base) ((base)->PRE_ROOT27_CLR) +#define CCM_PRE_ROOT27_TOG_REG(base) ((base)->PRE_ROOT27_TOG) +#define CCM_ACCESS_CTRL27_REG(base) ((base)->ACCESS_CTRL27) +#define CCM_ACCESS_CTRL27_ROOT_SET_REG(base) ((base)->ACCESS_CTRL27_ROOT_SET) +#define CCM_ACCESS_CTRL27_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL27_ROOT_CLR) +#define CCM_ACCESS_CTRL27_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL27_ROOT_TOG) +#define CCM_TARGET_ROOT28_REG(base) ((base)->TARGET_ROOT28) +#define CCM_TARGET_ROOT28_SET_REG(base) ((base)->TARGET_ROOT28_SET) +#define CCM_TARGET_ROOT28_CLR_REG(base) ((base)->TARGET_ROOT28_CLR) +#define CCM_TARGET_ROOT28_TOG_REG(base) ((base)->TARGET_ROOT28_TOG) +#define CCM_POST28_REG(base) ((base)->POST28) +#define CCM_POST_ROOT28_SET_REG(base) ((base)->POST_ROOT28_SET) +#define CCM_POST_ROOT28_CLR_REG(base) ((base)->POST_ROOT28_CLR) +#define CCM_POST_ROOT28_TOG_REG(base) ((base)->POST_ROOT28_TOG) +#define CCM_PRE28_REG(base) ((base)->PRE28) +#define CCM_PRE_ROOT28_SET_REG(base) ((base)->PRE_ROOT28_SET) +#define CCM_PRE_ROOT28_CLR_REG(base) ((base)->PRE_ROOT28_CLR) +#define CCM_PRE_ROOT28_TOG_REG(base) ((base)->PRE_ROOT28_TOG) +#define CCM_ACCESS_CTRL28_REG(base) ((base)->ACCESS_CTRL28) +#define CCM_ACCESS_CTRL28_ROOT_SET_REG(base) ((base)->ACCESS_CTRL28_ROOT_SET) +#define CCM_ACCESS_CTRL28_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL28_ROOT_CLR) +#define CCM_ACCESS_CTRL28_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL28_ROOT_TOG) +#define CCM_TARGET_ROOT29_REG(base) ((base)->TARGET_ROOT29) +#define CCM_TARGET_ROOT29_SET_REG(base) ((base)->TARGET_ROOT29_SET) +#define CCM_TARGET_ROOT29_CLR_REG(base) ((base)->TARGET_ROOT29_CLR) +#define CCM_TARGET_ROOT29_TOG_REG(base) ((base)->TARGET_ROOT29_TOG) +#define CCM_POST29_REG(base) ((base)->POST29) +#define CCM_POST_ROOT29_SET_REG(base) ((base)->POST_ROOT29_SET) +#define CCM_POST_ROOT29_CLR_REG(base) ((base)->POST_ROOT29_CLR) +#define CCM_POST_ROOT29_TOG_REG(base) ((base)->POST_ROOT29_TOG) +#define CCM_PRE29_REG(base) ((base)->PRE29) +#define CCM_PRE_ROOT29_SET_REG(base) ((base)->PRE_ROOT29_SET) +#define CCM_PRE_ROOT29_CLR_REG(base) ((base)->PRE_ROOT29_CLR) +#define CCM_PRE_ROOT29_TOG_REG(base) ((base)->PRE_ROOT29_TOG) +#define CCM_ACCESS_CTRL29_REG(base) ((base)->ACCESS_CTRL29) +#define CCM_ACCESS_CTRL29_ROOT_SET_REG(base) ((base)->ACCESS_CTRL29_ROOT_SET) +#define CCM_ACCESS_CTRL29_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL29_ROOT_CLR) +#define CCM_ACCESS_CTRL29_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL29_ROOT_TOG) +#define CCM_TARGET_ROOT30_REG(base) ((base)->TARGET_ROOT30) +#define CCM_TARGET_ROOT30_SET_REG(base) ((base)->TARGET_ROOT30_SET) +#define CCM_TARGET_ROOT30_CLR_REG(base) ((base)->TARGET_ROOT30_CLR) +#define CCM_TARGET_ROOT30_TOG_REG(base) ((base)->TARGET_ROOT30_TOG) +#define CCM_POST30_REG(base) ((base)->POST30) +#define CCM_POST_ROOT30_SET_REG(base) ((base)->POST_ROOT30_SET) +#define CCM_POST_ROOT30_CLR_REG(base) ((base)->POST_ROOT30_CLR) +#define CCM_POST_ROOT30_TOG_REG(base) ((base)->POST_ROOT30_TOG) +#define CCM_PRE30_REG(base) ((base)->PRE30) +#define CCM_PRE_ROOT30_SET_REG(base) ((base)->PRE_ROOT30_SET) +#define CCM_PRE_ROOT30_CLR_REG(base) ((base)->PRE_ROOT30_CLR) +#define CCM_PRE_ROOT30_TOG_REG(base) ((base)->PRE_ROOT30_TOG) +#define CCM_ACCESS_CTRL30_REG(base) ((base)->ACCESS_CTRL30) +#define CCM_ACCESS_CTRL30_ROOT_SET_REG(base) ((base)->ACCESS_CTRL30_ROOT_SET) +#define CCM_ACCESS_CTRL30_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL30_ROOT_CLR) +#define CCM_ACCESS_CTRL30_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL30_ROOT_TOG) +#define CCM_TARGET_ROOT31_REG(base) ((base)->TARGET_ROOT31) +#define CCM_TARGET_ROOT31_SET_REG(base) ((base)->TARGET_ROOT31_SET) +#define CCM_TARGET_ROOT31_CLR_REG(base) ((base)->TARGET_ROOT31_CLR) +#define CCM_TARGET_ROOT31_TOG_REG(base) ((base)->TARGET_ROOT31_TOG) +#define CCM_POST31_REG(base) ((base)->POST31) +#define CCM_POST_ROOT31_SET_REG(base) ((base)->POST_ROOT31_SET) +#define CCM_POST_ROOT31_CLR_REG(base) ((base)->POST_ROOT31_CLR) +#define CCM_POST_ROOT31_TOG_REG(base) ((base)->POST_ROOT31_TOG) +#define CCM_PRE31_REG(base) ((base)->PRE31) +#define CCM_PRE_ROOT31_SET_REG(base) ((base)->PRE_ROOT31_SET) +#define CCM_PRE_ROOT31_CLR_REG(base) ((base)->PRE_ROOT31_CLR) +#define CCM_PRE_ROOT31_TOG_REG(base) ((base)->PRE_ROOT31_TOG) +#define CCM_ACCESS_CTRL31_REG(base) ((base)->ACCESS_CTRL31) +#define CCM_ACCESS_CTRL31_ROOT_SET_REG(base) ((base)->ACCESS_CTRL31_ROOT_SET) +#define CCM_ACCESS_CTRL31_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL31_ROOT_CLR) +#define CCM_ACCESS_CTRL31_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL31_ROOT_TOG) +#define CCM_TARGET_ROOT32_REG(base) ((base)->TARGET_ROOT32) +#define CCM_TARGET_ROOT32_SET_REG(base) ((base)->TARGET_ROOT32_SET) +#define CCM_TARGET_ROOT32_CLR_REG(base) ((base)->TARGET_ROOT32_CLR) +#define CCM_TARGET_ROOT32_TOG_REG(base) ((base)->TARGET_ROOT32_TOG) +#define CCM_POST32_REG(base) ((base)->POST32) +#define CCM_POST_ROOT32_SET_REG(base) ((base)->POST_ROOT32_SET) +#define CCM_POST_ROOT32_CLR_REG(base) ((base)->POST_ROOT32_CLR) +#define CCM_POST_ROOT32_TOG_REG(base) ((base)->POST_ROOT32_TOG) +#define CCM_PRE32_REG(base) ((base)->PRE32) +#define CCM_PRE_ROOT32_SET_REG(base) ((base)->PRE_ROOT32_SET) +#define CCM_PRE_ROOT32_CLR_REG(base) ((base)->PRE_ROOT32_CLR) +#define CCM_PRE_ROOT32_TOG_REG(base) ((base)->PRE_ROOT32_TOG) +#define CCM_ACCESS_CTRL32_REG(base) ((base)->ACCESS_CTRL32) +#define CCM_ACCESS_CTRL32_ROOT_SET_REG(base) ((base)->ACCESS_CTRL32_ROOT_SET) +#define CCM_ACCESS_CTRL32_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL32_ROOT_CLR) +#define CCM_ACCESS_CTRL32_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL32_ROOT_TOG) +#define CCM_TARGET_ROOT33_REG(base) ((base)->TARGET_ROOT33) +#define CCM_TARGET_ROOT33_SET_REG(base) ((base)->TARGET_ROOT33_SET) +#define CCM_TARGET_ROOT33_CLR_REG(base) ((base)->TARGET_ROOT33_CLR) +#define CCM_TARGET_ROOT33_TOG_REG(base) ((base)->TARGET_ROOT33_TOG) +#define CCM_POST33_REG(base) ((base)->POST33) +#define CCM_POST_ROOT33_SET_REG(base) ((base)->POST_ROOT33_SET) +#define CCM_POST_ROOT33_CLR_REG(base) ((base)->POST_ROOT33_CLR) +#define CCM_POST_ROOT33_TOG_REG(base) ((base)->POST_ROOT33_TOG) +#define CCM_PRE33_REG(base) ((base)->PRE33) +#define CCM_PRE_ROOT33_SET_REG(base) ((base)->PRE_ROOT33_SET) +#define CCM_PRE_ROOT33_CLR_REG(base) ((base)->PRE_ROOT33_CLR) +#define CCM_PRE_ROOT33_TOG_REG(base) ((base)->PRE_ROOT33_TOG) +#define CCM_ACCESS_CTRL33_REG(base) ((base)->ACCESS_CTRL33) +#define CCM_ACCESS_CTRL33_ROOT_SET_REG(base) ((base)->ACCESS_CTRL33_ROOT_SET) +#define CCM_ACCESS_CTRL33_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL33_ROOT_CLR) +#define CCM_ACCESS_CTRL33_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL33_ROOT_TOG) +#define CCM_TARGET_ROOT34_REG(base) ((base)->TARGET_ROOT34) +#define CCM_TARGET_ROOT34_SET_REG(base) ((base)->TARGET_ROOT34_SET) +#define CCM_TARGET_ROOT34_CLR_REG(base) ((base)->TARGET_ROOT34_CLR) +#define CCM_TARGET_ROOT34_TOG_REG(base) ((base)->TARGET_ROOT34_TOG) +#define CCM_POST34_REG(base) ((base)->POST34) +#define CCM_POST_ROOT34_SET_REG(base) ((base)->POST_ROOT34_SET) +#define CCM_POST_ROOT34_CLR_REG(base) ((base)->POST_ROOT34_CLR) +#define CCM_POST_ROOT34_TOG_REG(base) ((base)->POST_ROOT34_TOG) +#define CCM_PRE34_REG(base) ((base)->PRE34) +#define CCM_PRE_ROOT34_SET_REG(base) ((base)->PRE_ROOT34_SET) +#define CCM_PRE_ROOT34_CLR_REG(base) ((base)->PRE_ROOT34_CLR) +#define CCM_PRE_ROOT34_TOG_REG(base) ((base)->PRE_ROOT34_TOG) +#define CCM_ACCESS_CTRL34_REG(base) ((base)->ACCESS_CTRL34) +#define CCM_ACCESS_CTRL34_ROOT_SET_REG(base) ((base)->ACCESS_CTRL34_ROOT_SET) +#define CCM_ACCESS_CTRL34_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL34_ROOT_CLR) +#define CCM_ACCESS_CTRL34_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL34_ROOT_TOG) +#define CCM_TARGET_ROOT35_REG(base) ((base)->TARGET_ROOT35) +#define CCM_TARGET_ROOT35_SET_REG(base) ((base)->TARGET_ROOT35_SET) +#define CCM_TARGET_ROOT35_CLR_REG(base) ((base)->TARGET_ROOT35_CLR) +#define CCM_TARGET_ROOT35_TOG_REG(base) ((base)->TARGET_ROOT35_TOG) +#define CCM_POST35_REG(base) ((base)->POST35) +#define CCM_POST_ROOT35_SET_REG(base) ((base)->POST_ROOT35_SET) +#define CCM_POST_ROOT35_CLR_REG(base) ((base)->POST_ROOT35_CLR) +#define CCM_POST_ROOT35_TOG_REG(base) ((base)->POST_ROOT35_TOG) +#define CCM_PRE35_REG(base) ((base)->PRE35) +#define CCM_PRE_ROOT35_SET_REG(base) ((base)->PRE_ROOT35_SET) +#define CCM_PRE_ROOT35_CLR_REG(base) ((base)->PRE_ROOT35_CLR) +#define CCM_PRE_ROOT35_TOG_REG(base) ((base)->PRE_ROOT35_TOG) +#define CCM_ACCESS_CTRL35_REG(base) ((base)->ACCESS_CTRL35) +#define CCM_ACCESS_CTRL35_ROOT_SET_REG(base) ((base)->ACCESS_CTRL35_ROOT_SET) +#define CCM_ACCESS_CTRL35_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL35_ROOT_CLR) +#define CCM_ACCESS_CTRL35_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL35_ROOT_TOG) +#define CCM_TARGET_ROOT36_REG(base) ((base)->TARGET_ROOT36) +#define CCM_TARGET_ROOT36_SET_REG(base) ((base)->TARGET_ROOT36_SET) +#define CCM_TARGET_ROOT36_CLR_REG(base) ((base)->TARGET_ROOT36_CLR) +#define CCM_TARGET_ROOT36_TOG_REG(base) ((base)->TARGET_ROOT36_TOG) +#define CCM_POST36_REG(base) ((base)->POST36) +#define CCM_POST_ROOT36_SET_REG(base) ((base)->POST_ROOT36_SET) +#define CCM_POST_ROOT36_CLR_REG(base) ((base)->POST_ROOT36_CLR) +#define CCM_POST_ROOT36_TOG_REG(base) ((base)->POST_ROOT36_TOG) +#define CCM_PRE36_REG(base) ((base)->PRE36) +#define CCM_PRE_ROOT36_SET_REG(base) ((base)->PRE_ROOT36_SET) +#define CCM_PRE_ROOT36_CLR_REG(base) ((base)->PRE_ROOT36_CLR) +#define CCM_PRE_ROOT36_TOG_REG(base) ((base)->PRE_ROOT36_TOG) +#define CCM_ACCESS_CTRL36_REG(base) ((base)->ACCESS_CTRL36) +#define CCM_ACCESS_CTRL36_ROOT_SET_REG(base) ((base)->ACCESS_CTRL36_ROOT_SET) +#define CCM_ACCESS_CTRL36_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL36_ROOT_CLR) +#define CCM_ACCESS_CTRL36_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL36_ROOT_TOG) +#define CCM_TARGET_ROOT37_REG(base) ((base)->TARGET_ROOT37) +#define CCM_TARGET_ROOT37_SET_REG(base) ((base)->TARGET_ROOT37_SET) +#define CCM_TARGET_ROOT37_CLR_REG(base) ((base)->TARGET_ROOT37_CLR) +#define CCM_TARGET_ROOT37_TOG_REG(base) ((base)->TARGET_ROOT37_TOG) +#define CCM_POST37_REG(base) ((base)->POST37) +#define CCM_POST_ROOT37_SET_REG(base) ((base)->POST_ROOT37_SET) +#define CCM_POST_ROOT37_CLR_REG(base) ((base)->POST_ROOT37_CLR) +#define CCM_POST_ROOT37_TOG_REG(base) ((base)->POST_ROOT37_TOG) +#define CCM_PRE37_REG(base) ((base)->PRE37) +#define CCM_PRE_ROOT37_SET_REG(base) ((base)->PRE_ROOT37_SET) +#define CCM_PRE_ROOT37_CLR_REG(base) ((base)->PRE_ROOT37_CLR) +#define CCM_PRE_ROOT37_TOG_REG(base) ((base)->PRE_ROOT37_TOG) +#define CCM_ACCESS_CTRL37_REG(base) ((base)->ACCESS_CTRL37) +#define CCM_ACCESS_CTRL37_ROOT_SET_REG(base) ((base)->ACCESS_CTRL37_ROOT_SET) +#define CCM_ACCESS_CTRL37_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL37_ROOT_CLR) +#define CCM_ACCESS_CTRL37_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL37_ROOT_TOG) +#define CCM_TARGET_ROOT38_REG(base) ((base)->TARGET_ROOT38) +#define CCM_TARGET_ROOT38_SET_REG(base) ((base)->TARGET_ROOT38_SET) +#define CCM_TARGET_ROOT38_CLR_REG(base) ((base)->TARGET_ROOT38_CLR) +#define CCM_TARGET_ROOT38_TOG_REG(base) ((base)->TARGET_ROOT38_TOG) +#define CCM_POST38_REG(base) ((base)->POST38) +#define CCM_POST_ROOT38_SET_REG(base) ((base)->POST_ROOT38_SET) +#define CCM_POST_ROOT38_CLR_REG(base) ((base)->POST_ROOT38_CLR) +#define CCM_POST_ROOT38_TOG_REG(base) ((base)->POST_ROOT38_TOG) +#define CCM_PRE38_REG(base) ((base)->PRE38) +#define CCM_PRE_ROOT38_SET_REG(base) ((base)->PRE_ROOT38_SET) +#define CCM_PRE_ROOT38_CLR_REG(base) ((base)->PRE_ROOT38_CLR) +#define CCM_PRE_ROOT38_TOG_REG(base) ((base)->PRE_ROOT38_TOG) +#define CCM_ACCESS_CTRL38_REG(base) ((base)->ACCESS_CTRL38) +#define CCM_ACCESS_CTRL38_ROOT_SET_REG(base) ((base)->ACCESS_CTRL38_ROOT_SET) +#define CCM_ACCESS_CTRL38_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL38_ROOT_CLR) +#define CCM_ACCESS_CTRL38_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL38_ROOT_TOG) +#define CCM_TARGET_ROOT39_REG(base) ((base)->TARGET_ROOT39) +#define CCM_TARGET_ROOT39_SET_REG(base) ((base)->TARGET_ROOT39_SET) +#define CCM_TARGET_ROOT39_CLR_REG(base) ((base)->TARGET_ROOT39_CLR) +#define CCM_TARGET_ROOT39_TOG_REG(base) ((base)->TARGET_ROOT39_TOG) +#define CCM_POST39_REG(base) ((base)->POST39) +#define CCM_POST_ROOT39_SET_REG(base) ((base)->POST_ROOT39_SET) +#define CCM_POST_ROOT39_CLR_REG(base) ((base)->POST_ROOT39_CLR) +#define CCM_POST_ROOT39_TOG_REG(base) ((base)->POST_ROOT39_TOG) +#define CCM_PRE39_REG(base) ((base)->PRE39) +#define CCM_PRE_ROOT39_SET_REG(base) ((base)->PRE_ROOT39_SET) +#define CCM_PRE_ROOT39_CLR_REG(base) ((base)->PRE_ROOT39_CLR) +#define CCM_PRE_ROOT39_TOG_REG(base) ((base)->PRE_ROOT39_TOG) +#define CCM_ACCESS_CTRL39_REG(base) ((base)->ACCESS_CTRL39) +#define CCM_ACCESS_CTRL39_ROOT_SET_REG(base) ((base)->ACCESS_CTRL39_ROOT_SET) +#define CCM_ACCESS_CTRL39_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL39_ROOT_CLR) +#define CCM_ACCESS_CTRL39_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL39_ROOT_TOG) +#define CCM_TARGET_ROOT40_REG(base) ((base)->TARGET_ROOT40) +#define CCM_TARGET_ROOT40_SET_REG(base) ((base)->TARGET_ROOT40_SET) +#define CCM_TARGET_ROOT40_CLR_REG(base) ((base)->TARGET_ROOT40_CLR) +#define CCM_TARGET_ROOT40_TOG_REG(base) ((base)->TARGET_ROOT40_TOG) +#define CCM_POST40_REG(base) ((base)->POST40) +#define CCM_POST_ROOT40_SET_REG(base) ((base)->POST_ROOT40_SET) +#define CCM_POST_ROOT40_CLR_REG(base) ((base)->POST_ROOT40_CLR) +#define CCM_POST_ROOT40_TOG_REG(base) ((base)->POST_ROOT40_TOG) +#define CCM_PRE40_REG(base) ((base)->PRE40) +#define CCM_PRE_ROOT40_SET_REG(base) ((base)->PRE_ROOT40_SET) +#define CCM_PRE_ROOT40_CLR_REG(base) ((base)->PRE_ROOT40_CLR) +#define CCM_PRE_ROOT40_TOG_REG(base) ((base)->PRE_ROOT40_TOG) +#define CCM_ACCESS_CTRL40_REG(base) ((base)->ACCESS_CTRL40) +#define CCM_ACCESS_CTRL40_ROOT_SET_REG(base) ((base)->ACCESS_CTRL40_ROOT_SET) +#define CCM_ACCESS_CTRL40_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL40_ROOT_CLR) +#define CCM_ACCESS_CTRL40_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL40_ROOT_TOG) +#define CCM_TARGET_ROOT41_REG(base) ((base)->TARGET_ROOT41) +#define CCM_TARGET_ROOT41_SET_REG(base) ((base)->TARGET_ROOT41_SET) +#define CCM_TARGET_ROOT41_CLR_REG(base) ((base)->TARGET_ROOT41_CLR) +#define CCM_TARGET_ROOT41_TOG_REG(base) ((base)->TARGET_ROOT41_TOG) +#define CCM_POST41_REG(base) ((base)->POST41) +#define CCM_POST_ROOT41_SET_REG(base) ((base)->POST_ROOT41_SET) +#define CCM_POST_ROOT41_CLR_REG(base) ((base)->POST_ROOT41_CLR) +#define CCM_POST_ROOT41_TOG_REG(base) ((base)->POST_ROOT41_TOG) +#define CCM_PRE41_REG(base) ((base)->PRE41) +#define CCM_PRE_ROOT41_SET_REG(base) ((base)->PRE_ROOT41_SET) +#define CCM_PRE_ROOT41_CLR_REG(base) ((base)->PRE_ROOT41_CLR) +#define CCM_PRE_ROOT41_TOG_REG(base) ((base)->PRE_ROOT41_TOG) +#define CCM_ACCESS_CTRL41_REG(base) ((base)->ACCESS_CTRL41) +#define CCM_ACCESS_CTRL41_ROOT_SET_REG(base) ((base)->ACCESS_CTRL41_ROOT_SET) +#define CCM_ACCESS_CTRL41_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL41_ROOT_CLR) +#define CCM_ACCESS_CTRL41_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL41_ROOT_TOG) +#define CCM_TARGET_ROOT42_REG(base) ((base)->TARGET_ROOT42) +#define CCM_TARGET_ROOT42_SET_REG(base) ((base)->TARGET_ROOT42_SET) +#define CCM_TARGET_ROOT42_CLR_REG(base) ((base)->TARGET_ROOT42_CLR) +#define CCM_TARGET_ROOT42_TOG_REG(base) ((base)->TARGET_ROOT42_TOG) +#define CCM_POST42_REG(base) ((base)->POST42) +#define CCM_POST_ROOT42_SET_REG(base) ((base)->POST_ROOT42_SET) +#define CCM_POST_ROOT42_CLR_REG(base) ((base)->POST_ROOT42_CLR) +#define CCM_POST_ROOT42_TOG_REG(base) ((base)->POST_ROOT42_TOG) +#define CCM_PRE42_REG(base) ((base)->PRE42) +#define CCM_PRE_ROOT42_SET_REG(base) ((base)->PRE_ROOT42_SET) +#define CCM_PRE_ROOT42_CLR_REG(base) ((base)->PRE_ROOT42_CLR) +#define CCM_PRE_ROOT42_TOG_REG(base) ((base)->PRE_ROOT42_TOG) +#define CCM_ACCESS_CTRL42_REG(base) ((base)->ACCESS_CTRL42) +#define CCM_ACCESS_CTRL42_ROOT_SET_REG(base) ((base)->ACCESS_CTRL42_ROOT_SET) +#define CCM_ACCESS_CTRL42_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL42_ROOT_CLR) +#define CCM_ACCESS_CTRL42_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL42_ROOT_TOG) +#define CCM_TARGET_ROOT43_REG(base) ((base)->TARGET_ROOT43) +#define CCM_TARGET_ROOT43_SET_REG(base) ((base)->TARGET_ROOT43_SET) +#define CCM_TARGET_ROOT43_CLR_REG(base) ((base)->TARGET_ROOT43_CLR) +#define CCM_TARGET_ROOT43_TOG_REG(base) ((base)->TARGET_ROOT43_TOG) +#define CCM_POST43_REG(base) ((base)->POST43) +#define CCM_POST_ROOT43_SET_REG(base) ((base)->POST_ROOT43_SET) +#define CCM_POST_ROOT43_CLR_REG(base) ((base)->POST_ROOT43_CLR) +#define CCM_POST_ROOT43_TOG_REG(base) ((base)->POST_ROOT43_TOG) +#define CCM_PRE43_REG(base) ((base)->PRE43) +#define CCM_PRE_ROOT43_SET_REG(base) ((base)->PRE_ROOT43_SET) +#define CCM_PRE_ROOT43_CLR_REG(base) ((base)->PRE_ROOT43_CLR) +#define CCM_PRE_ROOT43_TOG_REG(base) ((base)->PRE_ROOT43_TOG) +#define CCM_ACCESS_CTRL43_REG(base) ((base)->ACCESS_CTRL43) +#define CCM_ACCESS_CTRL43_ROOT_SET_REG(base) ((base)->ACCESS_CTRL43_ROOT_SET) +#define CCM_ACCESS_CTRL43_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL43_ROOT_CLR) +#define CCM_ACCESS_CTRL43_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL43_ROOT_TOG) +#define CCM_TARGET_ROOT44_REG(base) ((base)->TARGET_ROOT44) +#define CCM_TARGET_ROOT44_SET_REG(base) ((base)->TARGET_ROOT44_SET) +#define CCM_TARGET_ROOT44_CLR_REG(base) ((base)->TARGET_ROOT44_CLR) +#define CCM_TARGET_ROOT44_TOG_REG(base) ((base)->TARGET_ROOT44_TOG) +#define CCM_POST44_REG(base) ((base)->POST44) +#define CCM_POST_ROOT44_SET_REG(base) ((base)->POST_ROOT44_SET) +#define CCM_POST_ROOT44_CLR_REG(base) ((base)->POST_ROOT44_CLR) +#define CCM_POST_ROOT44_TOG_REG(base) ((base)->POST_ROOT44_TOG) +#define CCM_PRE44_REG(base) ((base)->PRE44) +#define CCM_PRE_ROOT44_SET_REG(base) ((base)->PRE_ROOT44_SET) +#define CCM_PRE_ROOT44_CLR_REG(base) ((base)->PRE_ROOT44_CLR) +#define CCM_PRE_ROOT44_TOG_REG(base) ((base)->PRE_ROOT44_TOG) +#define CCM_ACCESS_CTRL44_REG(base) ((base)->ACCESS_CTRL44) +#define CCM_ACCESS_CTRL44_ROOT_SET_REG(base) ((base)->ACCESS_CTRL44_ROOT_SET) +#define CCM_ACCESS_CTRL44_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL44_ROOT_CLR) +#define CCM_ACCESS_CTRL44_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL44_ROOT_TOG) +#define CCM_TARGET_ROOT45_REG(base) ((base)->TARGET_ROOT45) +#define CCM_TARGET_ROOT45_SET_REG(base) ((base)->TARGET_ROOT45_SET) +#define CCM_TARGET_ROOT45_CLR_REG(base) ((base)->TARGET_ROOT45_CLR) +#define CCM_TARGET_ROOT45_TOG_REG(base) ((base)->TARGET_ROOT45_TOG) +#define CCM_POST45_REG(base) ((base)->POST45) +#define CCM_POST_ROOT45_SET_REG(base) ((base)->POST_ROOT45_SET) +#define CCM_POST_ROOT45_CLR_REG(base) ((base)->POST_ROOT45_CLR) +#define CCM_POST_ROOT45_TOG_REG(base) ((base)->POST_ROOT45_TOG) +#define CCM_PRE45_REG(base) ((base)->PRE45) +#define CCM_PRE_ROOT45_SET_REG(base) ((base)->PRE_ROOT45_SET) +#define CCM_PRE_ROOT45_CLR_REG(base) ((base)->PRE_ROOT45_CLR) +#define CCM_PRE_ROOT45_TOG_REG(base) ((base)->PRE_ROOT45_TOG) +#define CCM_ACCESS_CTRL45_REG(base) ((base)->ACCESS_CTRL45) +#define CCM_ACCESS_CTRL45_ROOT_SET_REG(base) ((base)->ACCESS_CTRL45_ROOT_SET) +#define CCM_ACCESS_CTRL45_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL45_ROOT_CLR) +#define CCM_ACCESS_CTRL45_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL45_ROOT_TOG) +#define CCM_TARGET_ROOT46_REG(base) ((base)->TARGET_ROOT46) +#define CCM_TARGET_ROOT46_SET_REG(base) ((base)->TARGET_ROOT46_SET) +#define CCM_TARGET_ROOT46_CLR_REG(base) ((base)->TARGET_ROOT46_CLR) +#define CCM_TARGET_ROOT46_TOG_REG(base) ((base)->TARGET_ROOT46_TOG) +#define CCM_POST46_REG(base) ((base)->POST46) +#define CCM_POST_ROOT46_SET_REG(base) ((base)->POST_ROOT46_SET) +#define CCM_POST_ROOT46_CLR_REG(base) ((base)->POST_ROOT46_CLR) +#define CCM_POST_ROOT46_TOG_REG(base) ((base)->POST_ROOT46_TOG) +#define CCM_PRE46_REG(base) ((base)->PRE46) +#define CCM_PRE_ROOT46_SET_REG(base) ((base)->PRE_ROOT46_SET) +#define CCM_PRE_ROOT46_CLR_REG(base) ((base)->PRE_ROOT46_CLR) +#define CCM_PRE_ROOT46_TOG_REG(base) ((base)->PRE_ROOT46_TOG) +#define CCM_ACCESS_CTRL46_REG(base) ((base)->ACCESS_CTRL46) +#define CCM_ACCESS_CTRL46_ROOT_SET_REG(base) ((base)->ACCESS_CTRL46_ROOT_SET) +#define CCM_ACCESS_CTRL46_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL46_ROOT_CLR) +#define CCM_ACCESS_CTRL46_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL46_ROOT_TOG) +#define CCM_TARGET_ROOT47_REG(base) ((base)->TARGET_ROOT47) +#define CCM_TARGET_ROOT47_SET_REG(base) ((base)->TARGET_ROOT47_SET) +#define CCM_TARGET_ROOT47_CLR_REG(base) ((base)->TARGET_ROOT47_CLR) +#define CCM_TARGET_ROOT47_TOG_REG(base) ((base)->TARGET_ROOT47_TOG) +#define CCM_POST47_REG(base) ((base)->POST47) +#define CCM_POST_ROOT47_SET_REG(base) ((base)->POST_ROOT47_SET) +#define CCM_POST_ROOT47_CLR_REG(base) ((base)->POST_ROOT47_CLR) +#define CCM_POST_ROOT47_TOG_REG(base) ((base)->POST_ROOT47_TOG) +#define CCM_PRE47_REG(base) ((base)->PRE47) +#define CCM_PRE_ROOT47_SET_REG(base) ((base)->PRE_ROOT47_SET) +#define CCM_PRE_ROOT47_CLR_REG(base) ((base)->PRE_ROOT47_CLR) +#define CCM_PRE_ROOT47_TOG_REG(base) ((base)->PRE_ROOT47_TOG) +#define CCM_ACCESS_CTRL47_REG(base) ((base)->ACCESS_CTRL47) +#define CCM_ACCESS_CTRL47_ROOT_SET_REG(base) ((base)->ACCESS_CTRL47_ROOT_SET) +#define CCM_ACCESS_CTRL47_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL47_ROOT_CLR) +#define CCM_ACCESS_CTRL47_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL47_ROOT_TOG) +#define CCM_TARGET_ROOT48_REG(base) ((base)->TARGET_ROOT48) +#define CCM_TARGET_ROOT48_SET_REG(base) ((base)->TARGET_ROOT48_SET) +#define CCM_TARGET_ROOT48_CLR_REG(base) ((base)->TARGET_ROOT48_CLR) +#define CCM_TARGET_ROOT48_TOG_REG(base) ((base)->TARGET_ROOT48_TOG) +#define CCM_POST48_REG(base) ((base)->POST48) +#define CCM_POST_ROOT48_SET_REG(base) ((base)->POST_ROOT48_SET) +#define CCM_POST_ROOT48_CLR_REG(base) ((base)->POST_ROOT48_CLR) +#define CCM_POST_ROOT48_TOG_REG(base) ((base)->POST_ROOT48_TOG) +#define CCM_PRE48_REG(base) ((base)->PRE48) +#define CCM_PRE_ROOT48_SET_REG(base) ((base)->PRE_ROOT48_SET) +#define CCM_PRE_ROOT48_CLR_REG(base) ((base)->PRE_ROOT48_CLR) +#define CCM_PRE_ROOT48_TOG_REG(base) ((base)->PRE_ROOT48_TOG) +#define CCM_ACCESS_CTRL48_REG(base) ((base)->ACCESS_CTRL48) +#define CCM_ACCESS_CTRL48_ROOT_SET_REG(base) ((base)->ACCESS_CTRL48_ROOT_SET) +#define CCM_ACCESS_CTRL48_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL48_ROOT_CLR) +#define CCM_ACCESS_CTRL48_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL48_ROOT_TOG) +#define CCM_TARGET_ROOT49_REG(base) ((base)->TARGET_ROOT49) +#define CCM_TARGET_ROOT49_SET_REG(base) ((base)->TARGET_ROOT49_SET) +#define CCM_TARGET_ROOT49_CLR_REG(base) ((base)->TARGET_ROOT49_CLR) +#define CCM_TARGET_ROOT49_TOG_REG(base) ((base)->TARGET_ROOT49_TOG) +#define CCM_POST49_REG(base) ((base)->POST49) +#define CCM_POST_ROOT49_SET_REG(base) ((base)->POST_ROOT49_SET) +#define CCM_POST_ROOT49_CLR_REG(base) ((base)->POST_ROOT49_CLR) +#define CCM_POST_ROOT49_TOG_REG(base) ((base)->POST_ROOT49_TOG) +#define CCM_PRE49_REG(base) ((base)->PRE49) +#define CCM_PRE_ROOT49_SET_REG(base) ((base)->PRE_ROOT49_SET) +#define CCM_PRE_ROOT49_CLR_REG(base) ((base)->PRE_ROOT49_CLR) +#define CCM_PRE_ROOT49_TOG_REG(base) ((base)->PRE_ROOT49_TOG) +#define CCM_ACCESS_CTRL49_REG(base) ((base)->ACCESS_CTRL49) +#define CCM_ACCESS_CTRL49_ROOT_SET_REG(base) ((base)->ACCESS_CTRL49_ROOT_SET) +#define CCM_ACCESS_CTRL49_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL49_ROOT_CLR) +#define CCM_ACCESS_CTRL49_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL49_ROOT_TOG) +#define CCM_TARGET_ROOT50_REG(base) ((base)->TARGET_ROOT50) +#define CCM_TARGET_ROOT50_SET_REG(base) ((base)->TARGET_ROOT50_SET) +#define CCM_TARGET_ROOT50_CLR_REG(base) ((base)->TARGET_ROOT50_CLR) +#define CCM_TARGET_ROOT50_TOG_REG(base) ((base)->TARGET_ROOT50_TOG) +#define CCM_POST50_REG(base) ((base)->POST50) +#define CCM_POST_ROOT50_SET_REG(base) ((base)->POST_ROOT50_SET) +#define CCM_POST_ROOT50_CLR_REG(base) ((base)->POST_ROOT50_CLR) +#define CCM_POST_ROOT50_TOG_REG(base) ((base)->POST_ROOT50_TOG) +#define CCM_PRE50_REG(base) ((base)->PRE50) +#define CCM_PRE_ROOT50_SET_REG(base) ((base)->PRE_ROOT50_SET) +#define CCM_PRE_ROOT50_CLR_REG(base) ((base)->PRE_ROOT50_CLR) +#define CCM_PRE_ROOT50_TOG_REG(base) ((base)->PRE_ROOT50_TOG) +#define CCM_ACCESS_CTRL50_REG(base) ((base)->ACCESS_CTRL50) +#define CCM_ACCESS_CTRL50_ROOT_SET_REG(base) ((base)->ACCESS_CTRL50_ROOT_SET) +#define CCM_ACCESS_CTRL50_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL50_ROOT_CLR) +#define CCM_ACCESS_CTRL50_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL50_ROOT_TOG) +#define CCM_TARGET_ROOT51_REG(base) ((base)->TARGET_ROOT51) +#define CCM_TARGET_ROOT51_SET_REG(base) ((base)->TARGET_ROOT51_SET) +#define CCM_TARGET_ROOT51_CLR_REG(base) ((base)->TARGET_ROOT51_CLR) +#define CCM_TARGET_ROOT51_TOG_REG(base) ((base)->TARGET_ROOT51_TOG) +#define CCM_POST51_REG(base) ((base)->POST51) +#define CCM_POST_ROOT51_SET_REG(base) ((base)->POST_ROOT51_SET) +#define CCM_POST_ROOT51_CLR_REG(base) ((base)->POST_ROOT51_CLR) +#define CCM_POST_ROOT51_TOG_REG(base) ((base)->POST_ROOT51_TOG) +#define CCM_PRE51_REG(base) ((base)->PRE51) +#define CCM_PRE_ROOT51_SET_REG(base) ((base)->PRE_ROOT51_SET) +#define CCM_PRE_ROOT51_CLR_REG(base) ((base)->PRE_ROOT51_CLR) +#define CCM_PRE_ROOT51_TOG_REG(base) ((base)->PRE_ROOT51_TOG) +#define CCM_ACCESS_CTRL51_REG(base) ((base)->ACCESS_CTRL51) +#define CCM_ACCESS_CTRL51_ROOT_SET_REG(base) ((base)->ACCESS_CTRL51_ROOT_SET) +#define CCM_ACCESS_CTRL51_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL51_ROOT_CLR) +#define CCM_ACCESS_CTRL51_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL51_ROOT_TOG) +#define CCM_TARGET_ROOT52_REG(base) ((base)->TARGET_ROOT52) +#define CCM_TARGET_ROOT52_SET_REG(base) ((base)->TARGET_ROOT52_SET) +#define CCM_TARGET_ROOT52_CLR_REG(base) ((base)->TARGET_ROOT52_CLR) +#define CCM_TARGET_ROOT52_TOG_REG(base) ((base)->TARGET_ROOT52_TOG) +#define CCM_POST52_REG(base) ((base)->POST52) +#define CCM_POST_ROOT52_SET_REG(base) ((base)->POST_ROOT52_SET) +#define CCM_POST_ROOT52_CLR_REG(base) ((base)->POST_ROOT52_CLR) +#define CCM_POST_ROOT52_TOG_REG(base) ((base)->POST_ROOT52_TOG) +#define CCM_PRE52_REG(base) ((base)->PRE52) +#define CCM_PRE_ROOT52_SET_REG(base) ((base)->PRE_ROOT52_SET) +#define CCM_PRE_ROOT52_CLR_REG(base) ((base)->PRE_ROOT52_CLR) +#define CCM_PRE_ROOT52_TOG_REG(base) ((base)->PRE_ROOT52_TOG) +#define CCM_ACCESS_CTRL52_REG(base) ((base)->ACCESS_CTRL52) +#define CCM_ACCESS_CTRL52_ROOT_SET_REG(base) ((base)->ACCESS_CTRL52_ROOT_SET) +#define CCM_ACCESS_CTRL52_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL52_ROOT_CLR) +#define CCM_ACCESS_CTRL52_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL52_ROOT_TOG) +#define CCM_TARGET_ROOT53_REG(base) ((base)->TARGET_ROOT53) +#define CCM_TARGET_ROOT53_SET_REG(base) ((base)->TARGET_ROOT53_SET) +#define CCM_TARGET_ROOT53_CLR_REG(base) ((base)->TARGET_ROOT53_CLR) +#define CCM_TARGET_ROOT53_TOG_REG(base) ((base)->TARGET_ROOT53_TOG) +#define CCM_POST53_REG(base) ((base)->POST53) +#define CCM_POST_ROOT53_SET_REG(base) ((base)->POST_ROOT53_SET) +#define CCM_POST_ROOT53_CLR_REG(base) ((base)->POST_ROOT53_CLR) +#define CCM_POST_ROOT53_TOG_REG(base) ((base)->POST_ROOT53_TOG) +#define CCM_PRE53_REG(base) ((base)->PRE53) +#define CCM_PRE_ROOT53_SET_REG(base) ((base)->PRE_ROOT53_SET) +#define CCM_PRE_ROOT53_CLR_REG(base) ((base)->PRE_ROOT53_CLR) +#define CCM_PRE_ROOT53_TOG_REG(base) ((base)->PRE_ROOT53_TOG) +#define CCM_ACCESS_CTRL53_REG(base) ((base)->ACCESS_CTRL53) +#define CCM_ACCESS_CTRL53_ROOT_SET_REG(base) ((base)->ACCESS_CTRL53_ROOT_SET) +#define CCM_ACCESS_CTRL53_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL53_ROOT_CLR) +#define CCM_ACCESS_CTRL53_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL53_ROOT_TOG) +#define CCM_TARGET_ROOT54_REG(base) ((base)->TARGET_ROOT54) +#define CCM_TARGET_ROOT54_SET_REG(base) ((base)->TARGET_ROOT54_SET) +#define CCM_TARGET_ROOT54_CLR_REG(base) ((base)->TARGET_ROOT54_CLR) +#define CCM_TARGET_ROOT54_TOG_REG(base) ((base)->TARGET_ROOT54_TOG) +#define CCM_POST54_REG(base) ((base)->POST54) +#define CCM_POST_ROOT54_SET_REG(base) ((base)->POST_ROOT54_SET) +#define CCM_POST_ROOT54_CLR_REG(base) ((base)->POST_ROOT54_CLR) +#define CCM_POST_ROOT54_TOG_REG(base) ((base)->POST_ROOT54_TOG) +#define CCM_PRE54_REG(base) ((base)->PRE54) +#define CCM_PRE_ROOT54_SET_REG(base) ((base)->PRE_ROOT54_SET) +#define CCM_PRE_ROOT54_CLR_REG(base) ((base)->PRE_ROOT54_CLR) +#define CCM_PRE_ROOT54_TOG_REG(base) ((base)->PRE_ROOT54_TOG) +#define CCM_ACCESS_CTRL54_REG(base) ((base)->ACCESS_CTRL54) +#define CCM_ACCESS_CTRL54_ROOT_SET_REG(base) ((base)->ACCESS_CTRL54_ROOT_SET) +#define CCM_ACCESS_CTRL54_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL54_ROOT_CLR) +#define CCM_ACCESS_CTRL54_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL54_ROOT_TOG) +#define CCM_TARGET_ROOT55_REG(base) ((base)->TARGET_ROOT55) +#define CCM_TARGET_ROOT55_SET_REG(base) ((base)->TARGET_ROOT55_SET) +#define CCM_TARGET_ROOT55_CLR_REG(base) ((base)->TARGET_ROOT55_CLR) +#define CCM_TARGET_ROOT55_TOG_REG(base) ((base)->TARGET_ROOT55_TOG) +#define CCM_POST55_REG(base) ((base)->POST55) +#define CCM_POST_ROOT55_SET_REG(base) ((base)->POST_ROOT55_SET) +#define CCM_POST_ROOT55_CLR_REG(base) ((base)->POST_ROOT55_CLR) +#define CCM_POST_ROOT55_TOG_REG(base) ((base)->POST_ROOT55_TOG) +#define CCM_PRE55_REG(base) ((base)->PRE55) +#define CCM_PRE_ROOT55_SET_REG(base) ((base)->PRE_ROOT55_SET) +#define CCM_PRE_ROOT55_CLR_REG(base) ((base)->PRE_ROOT55_CLR) +#define CCM_PRE_ROOT55_TOG_REG(base) ((base)->PRE_ROOT55_TOG) +#define CCM_ACCESS_CTRL55_REG(base) ((base)->ACCESS_CTRL55) +#define CCM_ACCESS_CTRL55_ROOT_SET_REG(base) ((base)->ACCESS_CTRL55_ROOT_SET) +#define CCM_ACCESS_CTRL55_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL55_ROOT_CLR) +#define CCM_ACCESS_CTRL55_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL55_ROOT_TOG) +#define CCM_TARGET_ROOT56_REG(base) ((base)->TARGET_ROOT56) +#define CCM_TARGET_ROOT56_SET_REG(base) ((base)->TARGET_ROOT56_SET) +#define CCM_TARGET_ROOT56_CLR_REG(base) ((base)->TARGET_ROOT56_CLR) +#define CCM_TARGET_ROOT56_TOG_REG(base) ((base)->TARGET_ROOT56_TOG) +#define CCM_POST56_REG(base) ((base)->POST56) +#define CCM_POST_ROOT56_SET_REG(base) ((base)->POST_ROOT56_SET) +#define CCM_POST_ROOT56_CLR_REG(base) ((base)->POST_ROOT56_CLR) +#define CCM_POST_ROOT56_TOG_REG(base) ((base)->POST_ROOT56_TOG) +#define CCM_PRE56_REG(base) ((base)->PRE56) +#define CCM_PRE_ROOT56_SET_REG(base) ((base)->PRE_ROOT56_SET) +#define CCM_PRE_ROOT56_CLR_REG(base) ((base)->PRE_ROOT56_CLR) +#define CCM_PRE_ROOT56_TOG_REG(base) ((base)->PRE_ROOT56_TOG) +#define CCM_ACCESS_CTRL56_REG(base) ((base)->ACCESS_CTRL56) +#define CCM_ACCESS_CTRL56_ROOT_SET_REG(base) ((base)->ACCESS_CTRL56_ROOT_SET) +#define CCM_ACCESS_CTRL56_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL56_ROOT_CLR) +#define CCM_ACCESS_CTRL56_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL56_ROOT_TOG) +#define CCM_TARGET_ROOT57_REG(base) ((base)->TARGET_ROOT57) +#define CCM_TARGET_ROOT57_SET_REG(base) ((base)->TARGET_ROOT57_SET) +#define CCM_TARGET_ROOT57_CLR_REG(base) ((base)->TARGET_ROOT57_CLR) +#define CCM_TARGET_ROOT57_TOG_REG(base) ((base)->TARGET_ROOT57_TOG) +#define CCM_POST57_REG(base) ((base)->POST57) +#define CCM_POST_ROOT57_SET_REG(base) ((base)->POST_ROOT57_SET) +#define CCM_POST_ROOT57_CLR_REG(base) ((base)->POST_ROOT57_CLR) +#define CCM_POST_ROOT57_TOG_REG(base) ((base)->POST_ROOT57_TOG) +#define CCM_PRE57_REG(base) ((base)->PRE57) +#define CCM_PRE_ROOT57_SET_REG(base) ((base)->PRE_ROOT57_SET) +#define CCM_PRE_ROOT57_CLR_REG(base) ((base)->PRE_ROOT57_CLR) +#define CCM_PRE_ROOT57_TOG_REG(base) ((base)->PRE_ROOT57_TOG) +#define CCM_ACCESS_CTRL57_REG(base) ((base)->ACCESS_CTRL57) +#define CCM_ACCESS_CTRL57_ROOT_SET_REG(base) ((base)->ACCESS_CTRL57_ROOT_SET) +#define CCM_ACCESS_CTRL57_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL57_ROOT_CLR) +#define CCM_ACCESS_CTRL57_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL57_ROOT_TOG) +#define CCM_TARGET_ROOT58_REG(base) ((base)->TARGET_ROOT58) +#define CCM_TARGET_ROOT58_SET_REG(base) ((base)->TARGET_ROOT58_SET) +#define CCM_TARGET_ROOT58_CLR_REG(base) ((base)->TARGET_ROOT58_CLR) +#define CCM_TARGET_ROOT58_TOG_REG(base) ((base)->TARGET_ROOT58_TOG) +#define CCM_POST58_REG(base) ((base)->POST58) +#define CCM_POST_ROOT58_SET_REG(base) ((base)->POST_ROOT58_SET) +#define CCM_POST_ROOT58_CLR_REG(base) ((base)->POST_ROOT58_CLR) +#define CCM_POST_ROOT58_TOG_REG(base) ((base)->POST_ROOT58_TOG) +#define CCM_PRE58_REG(base) ((base)->PRE58) +#define CCM_PRE_ROOT58_SET_REG(base) ((base)->PRE_ROOT58_SET) +#define CCM_PRE_ROOT58_CLR_REG(base) ((base)->PRE_ROOT58_CLR) +#define CCM_PRE_ROOT58_TOG_REG(base) ((base)->PRE_ROOT58_TOG) +#define CCM_ACCESS_CTRL58_REG(base) ((base)->ACCESS_CTRL58) +#define CCM_ACCESS_CTRL58_ROOT_SET_REG(base) ((base)->ACCESS_CTRL58_ROOT_SET) +#define CCM_ACCESS_CTRL58_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL58_ROOT_CLR) +#define CCM_ACCESS_CTRL58_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL58_ROOT_TOG) +#define CCM_TARGET_ROOT59_REG(base) ((base)->TARGET_ROOT59) +#define CCM_TARGET_ROOT59_SET_REG(base) ((base)->TARGET_ROOT59_SET) +#define CCM_TARGET_ROOT59_CLR_REG(base) ((base)->TARGET_ROOT59_CLR) +#define CCM_TARGET_ROOT59_TOG_REG(base) ((base)->TARGET_ROOT59_TOG) +#define CCM_POST59_REG(base) ((base)->POST59) +#define CCM_POST_ROOT59_SET_REG(base) ((base)->POST_ROOT59_SET) +#define CCM_POST_ROOT59_CLR_REG(base) ((base)->POST_ROOT59_CLR) +#define CCM_POST_ROOT59_TOG_REG(base) ((base)->POST_ROOT59_TOG) +#define CCM_PRE59_REG(base) ((base)->PRE59) +#define CCM_PRE_ROOT59_SET_REG(base) ((base)->PRE_ROOT59_SET) +#define CCM_PRE_ROOT59_CLR_REG(base) ((base)->PRE_ROOT59_CLR) +#define CCM_PRE_ROOT59_TOG_REG(base) ((base)->PRE_ROOT59_TOG) +#define CCM_ACCESS_CTRL59_REG(base) ((base)->ACCESS_CTRL59) +#define CCM_ACCESS_CTRL59_ROOT_SET_REG(base) ((base)->ACCESS_CTRL59_ROOT_SET) +#define CCM_ACCESS_CTRL59_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL59_ROOT_CLR) +#define CCM_ACCESS_CTRL59_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL59_ROOT_TOG) +#define CCM_TARGET_ROOT60_REG(base) ((base)->TARGET_ROOT60) +#define CCM_TARGET_ROOT60_SET_REG(base) ((base)->TARGET_ROOT60_SET) +#define CCM_TARGET_ROOT60_CLR_REG(base) ((base)->TARGET_ROOT60_CLR) +#define CCM_TARGET_ROOT60_TOG_REG(base) ((base)->TARGET_ROOT60_TOG) +#define CCM_POST60_REG(base) ((base)->POST60) +#define CCM_POST_ROOT60_SET_REG(base) ((base)->POST_ROOT60_SET) +#define CCM_POST_ROOT60_CLR_REG(base) ((base)->POST_ROOT60_CLR) +#define CCM_POST_ROOT60_TOG_REG(base) ((base)->POST_ROOT60_TOG) +#define CCM_PRE60_REG(base) ((base)->PRE60) +#define CCM_PRE_ROOT60_SET_REG(base) ((base)->PRE_ROOT60_SET) +#define CCM_PRE_ROOT60_CLR_REG(base) ((base)->PRE_ROOT60_CLR) +#define CCM_PRE_ROOT60_TOG_REG(base) ((base)->PRE_ROOT60_TOG) +#define CCM_ACCESS_CTRL60_REG(base) ((base)->ACCESS_CTRL60) +#define CCM_ACCESS_CTRL60_ROOT_SET_REG(base) ((base)->ACCESS_CTRL60_ROOT_SET) +#define CCM_ACCESS_CTRL60_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL60_ROOT_CLR) +#define CCM_ACCESS_CTRL60_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL60_ROOT_TOG) +#define CCM_TARGET_ROOT61_REG(base) ((base)->TARGET_ROOT61) +#define CCM_TARGET_ROOT61_SET_REG(base) ((base)->TARGET_ROOT61_SET) +#define CCM_TARGET_ROOT61_CLR_REG(base) ((base)->TARGET_ROOT61_CLR) +#define CCM_TARGET_ROOT61_TOG_REG(base) ((base)->TARGET_ROOT61_TOG) +#define CCM_POST61_REG(base) ((base)->POST61) +#define CCM_POST_ROOT61_SET_REG(base) ((base)->POST_ROOT61_SET) +#define CCM_POST_ROOT61_CLR_REG(base) ((base)->POST_ROOT61_CLR) +#define CCM_POST_ROOT61_TOG_REG(base) ((base)->POST_ROOT61_TOG) +#define CCM_PRE61_REG(base) ((base)->PRE61) +#define CCM_PRE_ROOT61_SET_REG(base) ((base)->PRE_ROOT61_SET) +#define CCM_PRE_ROOT61_CLR_REG(base) ((base)->PRE_ROOT61_CLR) +#define CCM_PRE_ROOT61_TOG_REG(base) ((base)->PRE_ROOT61_TOG) +#define CCM_ACCESS_CTRL61_REG(base) ((base)->ACCESS_CTRL61) +#define CCM_ACCESS_CTRL61_ROOT_SET_REG(base) ((base)->ACCESS_CTRL61_ROOT_SET) +#define CCM_ACCESS_CTRL61_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL61_ROOT_CLR) +#define CCM_ACCESS_CTRL61_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL61_ROOT_TOG) +#define CCM_TARGET_ROOT62_REG(base) ((base)->TARGET_ROOT62) +#define CCM_TARGET_ROOT62_SET_REG(base) ((base)->TARGET_ROOT62_SET) +#define CCM_TARGET_ROOT62_CLR_REG(base) ((base)->TARGET_ROOT62_CLR) +#define CCM_TARGET_ROOT62_TOG_REG(base) ((base)->TARGET_ROOT62_TOG) +#define CCM_POST62_REG(base) ((base)->POST62) +#define CCM_POST_ROOT62_SET_REG(base) ((base)->POST_ROOT62_SET) +#define CCM_POST_ROOT62_CLR_REG(base) ((base)->POST_ROOT62_CLR) +#define CCM_POST_ROOT62_TOG_REG(base) ((base)->POST_ROOT62_TOG) +#define CCM_PRE62_REG(base) ((base)->PRE62) +#define CCM_PRE_ROOT62_SET_REG(base) ((base)->PRE_ROOT62_SET) +#define CCM_PRE_ROOT62_CLR_REG(base) ((base)->PRE_ROOT62_CLR) +#define CCM_PRE_ROOT62_TOG_REG(base) ((base)->PRE_ROOT62_TOG) +#define CCM_ACCESS_CTRL62_REG(base) ((base)->ACCESS_CTRL62) +#define CCM_ACCESS_CTRL62_ROOT_SET_REG(base) ((base)->ACCESS_CTRL62_ROOT_SET) +#define CCM_ACCESS_CTRL62_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL62_ROOT_CLR) +#define CCM_ACCESS_CTRL62_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL62_ROOT_TOG) +#define CCM_TARGET_ROOT63_REG(base) ((base)->TARGET_ROOT63) +#define CCM_TARGET_ROOT63_SET_REG(base) ((base)->TARGET_ROOT63_SET) +#define CCM_TARGET_ROOT63_CLR_REG(base) ((base)->TARGET_ROOT63_CLR) +#define CCM_TARGET_ROOT63_TOG_REG(base) ((base)->TARGET_ROOT63_TOG) +#define CCM_POST63_REG(base) ((base)->POST63) +#define CCM_POST_ROOT63_SET_REG(base) ((base)->POST_ROOT63_SET) +#define CCM_POST_ROOT63_CLR_REG(base) ((base)->POST_ROOT63_CLR) +#define CCM_POST_ROOT63_TOG_REG(base) ((base)->POST_ROOT63_TOG) +#define CCM_PRE63_REG(base) ((base)->PRE63) +#define CCM_PRE_ROOT63_SET_REG(base) ((base)->PRE_ROOT63_SET) +#define CCM_PRE_ROOT63_CLR_REG(base) ((base)->PRE_ROOT63_CLR) +#define CCM_PRE_ROOT63_TOG_REG(base) ((base)->PRE_ROOT63_TOG) +#define CCM_ACCESS_CTRL63_REG(base) ((base)->ACCESS_CTRL63) +#define CCM_ACCESS_CTRL63_ROOT_SET_REG(base) ((base)->ACCESS_CTRL63_ROOT_SET) +#define CCM_ACCESS_CTRL63_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL63_ROOT_CLR) +#define CCM_ACCESS_CTRL63_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL63_ROOT_TOG) +#define CCM_TARGET_ROOT64_REG(base) ((base)->TARGET_ROOT64) +#define CCM_TARGET_ROOT64_SET_REG(base) ((base)->TARGET_ROOT64_SET) +#define CCM_TARGET_ROOT64_CLR_REG(base) ((base)->TARGET_ROOT64_CLR) +#define CCM_TARGET_ROOT64_TOG_REG(base) ((base)->TARGET_ROOT64_TOG) +#define CCM_POST64_REG(base) ((base)->POST64) +#define CCM_POST_ROOT64_SET_REG(base) ((base)->POST_ROOT64_SET) +#define CCM_POST_ROOT64_CLR_REG(base) ((base)->POST_ROOT64_CLR) +#define CCM_POST_ROOT64_TOG_REG(base) ((base)->POST_ROOT64_TOG) +#define CCM_PRE64_REG(base) ((base)->PRE64) +#define CCM_PRE_ROOT64_SET_REG(base) ((base)->PRE_ROOT64_SET) +#define CCM_PRE_ROOT64_CLR_REG(base) ((base)->PRE_ROOT64_CLR) +#define CCM_PRE_ROOT64_TOG_REG(base) ((base)->PRE_ROOT64_TOG) +#define CCM_ACCESS_CTRL64_REG(base) ((base)->ACCESS_CTRL64) +#define CCM_ACCESS_CTRL64_ROOT_SET_REG(base) ((base)->ACCESS_CTRL64_ROOT_SET) +#define CCM_ACCESS_CTRL64_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL64_ROOT_CLR) +#define CCM_ACCESS_CTRL64_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL64_ROOT_TOG) +#define CCM_TARGET_ROOT65_REG(base) ((base)->TARGET_ROOT65) +#define CCM_TARGET_ROOT65_SET_REG(base) ((base)->TARGET_ROOT65_SET) +#define CCM_TARGET_ROOT65_CLR_REG(base) ((base)->TARGET_ROOT65_CLR) +#define CCM_TARGET_ROOT65_TOG_REG(base) ((base)->TARGET_ROOT65_TOG) +#define CCM_POST65_REG(base) ((base)->POST65) +#define CCM_POST_ROOT65_SET_REG(base) ((base)->POST_ROOT65_SET) +#define CCM_POST_ROOT65_CLR_REG(base) ((base)->POST_ROOT65_CLR) +#define CCM_POST_ROOT65_TOG_REG(base) ((base)->POST_ROOT65_TOG) +#define CCM_PRE65_REG(base) ((base)->PRE65) +#define CCM_PRE_ROOT65_SET_REG(base) ((base)->PRE_ROOT65_SET) +#define CCM_PRE_ROOT65_CLR_REG(base) ((base)->PRE_ROOT65_CLR) +#define CCM_PRE_ROOT65_TOG_REG(base) ((base)->PRE_ROOT65_TOG) +#define CCM_ACCESS_CTRL65_REG(base) ((base)->ACCESS_CTRL65) +#define CCM_ACCESS_CTRL65_ROOT_SET_REG(base) ((base)->ACCESS_CTRL65_ROOT_SET) +#define CCM_ACCESS_CTRL65_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL65_ROOT_CLR) +#define CCM_ACCESS_CTRL65_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL65_ROOT_TOG) +#define CCM_TARGET_ROOT66_REG(base) ((base)->TARGET_ROOT66) +#define CCM_TARGET_ROOT66_SET_REG(base) ((base)->TARGET_ROOT66_SET) +#define CCM_TARGET_ROOT66_CLR_REG(base) ((base)->TARGET_ROOT66_CLR) +#define CCM_TARGET_ROOT66_TOG_REG(base) ((base)->TARGET_ROOT66_TOG) +#define CCM_POST66_REG(base) ((base)->POST66) +#define CCM_POST_ROOT66_SET_REG(base) ((base)->POST_ROOT66_SET) +#define CCM_POST_ROOT66_CLR_REG(base) ((base)->POST_ROOT66_CLR) +#define CCM_POST_ROOT66_TOG_REG(base) ((base)->POST_ROOT66_TOG) +#define CCM_PRE66_REG(base) ((base)->PRE66) +#define CCM_PRE_ROOT66_SET_REG(base) ((base)->PRE_ROOT66_SET) +#define CCM_PRE_ROOT66_CLR_REG(base) ((base)->PRE_ROOT66_CLR) +#define CCM_PRE_ROOT66_TOG_REG(base) ((base)->PRE_ROOT66_TOG) +#define CCM_ACCESS_CTRL66_REG(base) ((base)->ACCESS_CTRL66) +#define CCM_ACCESS_CTRL66_ROOT_SET_REG(base) ((base)->ACCESS_CTRL66_ROOT_SET) +#define CCM_ACCESS_CTRL66_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL66_ROOT_CLR) +#define CCM_ACCESS_CTRL66_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL66_ROOT_TOG) +#define CCM_TARGET_ROOT67_REG(base) ((base)->TARGET_ROOT67) +#define CCM_TARGET_ROOT67_SET_REG(base) ((base)->TARGET_ROOT67_SET) +#define CCM_TARGET_ROOT67_CLR_REG(base) ((base)->TARGET_ROOT67_CLR) +#define CCM_TARGET_ROOT67_TOG_REG(base) ((base)->TARGET_ROOT67_TOG) +#define CCM_POST67_REG(base) ((base)->POST67) +#define CCM_POST_ROOT67_SET_REG(base) ((base)->POST_ROOT67_SET) +#define CCM_POST_ROOT67_CLR_REG(base) ((base)->POST_ROOT67_CLR) +#define CCM_POST_ROOT67_TOG_REG(base) ((base)->POST_ROOT67_TOG) +#define CCM_PRE67_REG(base) ((base)->PRE67) +#define CCM_PRE_ROOT67_SET_REG(base) ((base)->PRE_ROOT67_SET) +#define CCM_PRE_ROOT67_CLR_REG(base) ((base)->PRE_ROOT67_CLR) +#define CCM_PRE_ROOT67_TOG_REG(base) ((base)->PRE_ROOT67_TOG) +#define CCM_ACCESS_CTRL67_REG(base) ((base)->ACCESS_CTRL67) +#define CCM_ACCESS_CTRL67_ROOT_SET_REG(base) ((base)->ACCESS_CTRL67_ROOT_SET) +#define CCM_ACCESS_CTRL67_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL67_ROOT_CLR) +#define CCM_ACCESS_CTRL67_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL67_ROOT_TOG) +#define CCM_TARGET_ROOT68_REG(base) ((base)->TARGET_ROOT68) +#define CCM_TARGET_ROOT68_SET_REG(base) ((base)->TARGET_ROOT68_SET) +#define CCM_TARGET_ROOT68_CLR_REG(base) ((base)->TARGET_ROOT68_CLR) +#define CCM_TARGET_ROOT68_TOG_REG(base) ((base)->TARGET_ROOT68_TOG) +#define CCM_POST68_REG(base) ((base)->POST68) +#define CCM_POST_ROOT68_SET_REG(base) ((base)->POST_ROOT68_SET) +#define CCM_POST_ROOT68_CLR_REG(base) ((base)->POST_ROOT68_CLR) +#define CCM_POST_ROOT68_TOG_REG(base) ((base)->POST_ROOT68_TOG) +#define CCM_PRE68_REG(base) ((base)->PRE68) +#define CCM_PRE_ROOT68_SET_REG(base) ((base)->PRE_ROOT68_SET) +#define CCM_PRE_ROOT68_CLR_REG(base) ((base)->PRE_ROOT68_CLR) +#define CCM_PRE_ROOT68_TOG_REG(base) ((base)->PRE_ROOT68_TOG) +#define CCM_ACCESS_CTRL68_REG(base) ((base)->ACCESS_CTRL68) +#define CCM_ACCESS_CTRL68_ROOT_SET_REG(base) ((base)->ACCESS_CTRL68_ROOT_SET) +#define CCM_ACCESS_CTRL68_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL68_ROOT_CLR) +#define CCM_ACCESS_CTRL68_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL68_ROOT_TOG) +#define CCM_TARGET_ROOT69_REG(base) ((base)->TARGET_ROOT69) +#define CCM_TARGET_ROOT69_SET_REG(base) ((base)->TARGET_ROOT69_SET) +#define CCM_TARGET_ROOT69_CLR_REG(base) ((base)->TARGET_ROOT69_CLR) +#define CCM_TARGET_ROOT69_TOG_REG(base) ((base)->TARGET_ROOT69_TOG) +#define CCM_POST69_REG(base) ((base)->POST69) +#define CCM_POST_ROOT69_SET_REG(base) ((base)->POST_ROOT69_SET) +#define CCM_POST_ROOT69_CLR_REG(base) ((base)->POST_ROOT69_CLR) +#define CCM_POST_ROOT69_TOG_REG(base) ((base)->POST_ROOT69_TOG) +#define CCM_PRE69_REG(base) ((base)->PRE69) +#define CCM_PRE_ROOT69_SET_REG(base) ((base)->PRE_ROOT69_SET) +#define CCM_PRE_ROOT69_CLR_REG(base) ((base)->PRE_ROOT69_CLR) +#define CCM_PRE_ROOT69_TOG_REG(base) ((base)->PRE_ROOT69_TOG) +#define CCM_ACCESS_CTRL69_REG(base) ((base)->ACCESS_CTRL69) +#define CCM_ACCESS_CTRL69_ROOT_SET_REG(base) ((base)->ACCESS_CTRL69_ROOT_SET) +#define CCM_ACCESS_CTRL69_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL69_ROOT_CLR) +#define CCM_ACCESS_CTRL69_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL69_ROOT_TOG) +#define CCM_TARGET_ROOT70_REG(base) ((base)->TARGET_ROOT70) +#define CCM_TARGET_ROOT70_SET_REG(base) ((base)->TARGET_ROOT70_SET) +#define CCM_TARGET_ROOT70_CLR_REG(base) ((base)->TARGET_ROOT70_CLR) +#define CCM_TARGET_ROOT70_TOG_REG(base) ((base)->TARGET_ROOT70_TOG) +#define CCM_POST70_REG(base) ((base)->POST70) +#define CCM_POST_ROOT70_SET_REG(base) ((base)->POST_ROOT70_SET) +#define CCM_POST_ROOT70_CLR_REG(base) ((base)->POST_ROOT70_CLR) +#define CCM_POST_ROOT70_TOG_REG(base) ((base)->POST_ROOT70_TOG) +#define CCM_PRE70_REG(base) ((base)->PRE70) +#define CCM_PRE_ROOT70_SET_REG(base) ((base)->PRE_ROOT70_SET) +#define CCM_PRE_ROOT70_CLR_REG(base) ((base)->PRE_ROOT70_CLR) +#define CCM_PRE_ROOT70_TOG_REG(base) ((base)->PRE_ROOT70_TOG) +#define CCM_ACCESS_CTRL70_REG(base) ((base)->ACCESS_CTRL70) +#define CCM_ACCESS_CTRL70_ROOT_SET_REG(base) ((base)->ACCESS_CTRL70_ROOT_SET) +#define CCM_ACCESS_CTRL70_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL70_ROOT_CLR) +#define CCM_ACCESS_CTRL70_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL70_ROOT_TOG) +#define CCM_TARGET_ROOT71_REG(base) ((base)->TARGET_ROOT71) +#define CCM_TARGET_ROOT71_SET_REG(base) ((base)->TARGET_ROOT71_SET) +#define CCM_TARGET_ROOT71_CLR_REG(base) ((base)->TARGET_ROOT71_CLR) +#define CCM_TARGET_ROOT71_TOG_REG(base) ((base)->TARGET_ROOT71_TOG) +#define CCM_POST71_REG(base) ((base)->POST71) +#define CCM_POST_ROOT71_SET_REG(base) ((base)->POST_ROOT71_SET) +#define CCM_POST_ROOT71_CLR_REG(base) ((base)->POST_ROOT71_CLR) +#define CCM_POST_ROOT71_TOG_REG(base) ((base)->POST_ROOT71_TOG) +#define CCM_PRE71_REG(base) ((base)->PRE71) +#define CCM_PRE_ROOT71_SET_REG(base) ((base)->PRE_ROOT71_SET) +#define CCM_PRE_ROOT71_CLR_REG(base) ((base)->PRE_ROOT71_CLR) +#define CCM_PRE_ROOT71_TOG_REG(base) ((base)->PRE_ROOT71_TOG) +#define CCM_ACCESS_CTRL71_REG(base) ((base)->ACCESS_CTRL71) +#define CCM_ACCESS_CTRL71_ROOT_SET_REG(base) ((base)->ACCESS_CTRL71_ROOT_SET) +#define CCM_ACCESS_CTRL71_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL71_ROOT_CLR) +#define CCM_ACCESS_CTRL71_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL71_ROOT_TOG) +#define CCM_TARGET_ROOT72_REG(base) ((base)->TARGET_ROOT72) +#define CCM_TARGET_ROOT72_SET_REG(base) ((base)->TARGET_ROOT72_SET) +#define CCM_TARGET_ROOT72_CLR_REG(base) ((base)->TARGET_ROOT72_CLR) +#define CCM_TARGET_ROOT72_TOG_REG(base) ((base)->TARGET_ROOT72_TOG) +#define CCM_POST72_REG(base) ((base)->POST72) +#define CCM_POST_ROOT72_SET_REG(base) ((base)->POST_ROOT72_SET) +#define CCM_POST_ROOT72_CLR_REG(base) ((base)->POST_ROOT72_CLR) +#define CCM_POST_ROOT72_TOG_REG(base) ((base)->POST_ROOT72_TOG) +#define CCM_PRE72_REG(base) ((base)->PRE72) +#define CCM_PRE_ROOT72_SET_REG(base) ((base)->PRE_ROOT72_SET) +#define CCM_PRE_ROOT72_CLR_REG(base) ((base)->PRE_ROOT72_CLR) +#define CCM_PRE_ROOT72_TOG_REG(base) ((base)->PRE_ROOT72_TOG) +#define CCM_ACCESS_CTRL72_REG(base) ((base)->ACCESS_CTRL72) +#define CCM_ACCESS_CTRL72_ROOT_SET_REG(base) ((base)->ACCESS_CTRL72_ROOT_SET) +#define CCM_ACCESS_CTRL72_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL72_ROOT_CLR) +#define CCM_ACCESS_CTRL72_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL72_ROOT_TOG) +#define CCM_TARGET_ROOT73_REG(base) ((base)->TARGET_ROOT73) +#define CCM_TARGET_ROOT73_SET_REG(base) ((base)->TARGET_ROOT73_SET) +#define CCM_TARGET_ROOT73_CLR_REG(base) ((base)->TARGET_ROOT73_CLR) +#define CCM_TARGET_ROOT73_TOG_REG(base) ((base)->TARGET_ROOT73_TOG) +#define CCM_POST73_REG(base) ((base)->POST73) +#define CCM_POST_ROOT73_SET_REG(base) ((base)->POST_ROOT73_SET) +#define CCM_POST_ROOT73_CLR_REG(base) ((base)->POST_ROOT73_CLR) +#define CCM_POST_ROOT73_TOG_REG(base) ((base)->POST_ROOT73_TOG) +#define CCM_PRE73_REG(base) ((base)->PRE73) +#define CCM_PRE_ROOT73_SET_REG(base) ((base)->PRE_ROOT73_SET) +#define CCM_PRE_ROOT73_CLR_REG(base) ((base)->PRE_ROOT73_CLR) +#define CCM_PRE_ROOT73_TOG_REG(base) ((base)->PRE_ROOT73_TOG) +#define CCM_ACCESS_CTRL73_REG(base) ((base)->ACCESS_CTRL73) +#define CCM_ACCESS_CTRL73_ROOT_SET_REG(base) ((base)->ACCESS_CTRL73_ROOT_SET) +#define CCM_ACCESS_CTRL73_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL73_ROOT_CLR) +#define CCM_ACCESS_CTRL73_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL73_ROOT_TOG) +#define CCM_TARGET_ROOT74_REG(base) ((base)->TARGET_ROOT74) +#define CCM_TARGET_ROOT74_SET_REG(base) ((base)->TARGET_ROOT74_SET) +#define CCM_TARGET_ROOT74_CLR_REG(base) ((base)->TARGET_ROOT74_CLR) +#define CCM_TARGET_ROOT74_TOG_REG(base) ((base)->TARGET_ROOT74_TOG) +#define CCM_POST74_REG(base) ((base)->POST74) +#define CCM_POST_ROOT74_SET_REG(base) ((base)->POST_ROOT74_SET) +#define CCM_POST_ROOT74_CLR_REG(base) ((base)->POST_ROOT74_CLR) +#define CCM_POST_ROOT74_TOG_REG(base) ((base)->POST_ROOT74_TOG) +#define CCM_PRE74_REG(base) ((base)->PRE74) +#define CCM_PRE_ROOT74_SET_REG(base) ((base)->PRE_ROOT74_SET) +#define CCM_PRE_ROOT74_CLR_REG(base) ((base)->PRE_ROOT74_CLR) +#define CCM_PRE_ROOT74_TOG_REG(base) ((base)->PRE_ROOT74_TOG) +#define CCM_ACCESS_CTRL74_REG(base) ((base)->ACCESS_CTRL74) +#define CCM_ACCESS_CTRL74_ROOT_SET_REG(base) ((base)->ACCESS_CTRL74_ROOT_SET) +#define CCM_ACCESS_CTRL74_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL74_ROOT_CLR) +#define CCM_ACCESS_CTRL74_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL74_ROOT_TOG) +#define CCM_TARGET_ROOT75_REG(base) ((base)->TARGET_ROOT75) +#define CCM_TARGET_ROOT75_SET_REG(base) ((base)->TARGET_ROOT75_SET) +#define CCM_TARGET_ROOT75_CLR_REG(base) ((base)->TARGET_ROOT75_CLR) +#define CCM_TARGET_ROOT75_TOG_REG(base) ((base)->TARGET_ROOT75_TOG) +#define CCM_POST75_REG(base) ((base)->POST75) +#define CCM_POST_ROOT75_SET_REG(base) ((base)->POST_ROOT75_SET) +#define CCM_POST_ROOT75_CLR_REG(base) ((base)->POST_ROOT75_CLR) +#define CCM_POST_ROOT75_TOG_REG(base) ((base)->POST_ROOT75_TOG) +#define CCM_PRE75_REG(base) ((base)->PRE75) +#define CCM_PRE_ROOT75_SET_REG(base) ((base)->PRE_ROOT75_SET) +#define CCM_PRE_ROOT75_CLR_REG(base) ((base)->PRE_ROOT75_CLR) +#define CCM_PRE_ROOT75_TOG_REG(base) ((base)->PRE_ROOT75_TOG) +#define CCM_ACCESS_CTRL75_REG(base) ((base)->ACCESS_CTRL75) +#define CCM_ACCESS_CTRL75_ROOT_SET_REG(base) ((base)->ACCESS_CTRL75_ROOT_SET) +#define CCM_ACCESS_CTRL75_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL75_ROOT_CLR) +#define CCM_ACCESS_CTRL75_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL75_ROOT_TOG) +#define CCM_TARGET_ROOT76_REG(base) ((base)->TARGET_ROOT76) +#define CCM_TARGET_ROOT76_SET_REG(base) ((base)->TARGET_ROOT76_SET) +#define CCM_TARGET_ROOT76_CLR_REG(base) ((base)->TARGET_ROOT76_CLR) +#define CCM_TARGET_ROOT76_TOG_REG(base) ((base)->TARGET_ROOT76_TOG) +#define CCM_POST76_REG(base) ((base)->POST76) +#define CCM_POST_ROOT76_SET_REG(base) ((base)->POST_ROOT76_SET) +#define CCM_POST_ROOT76_CLR_REG(base) ((base)->POST_ROOT76_CLR) +#define CCM_POST_ROOT76_TOG_REG(base) ((base)->POST_ROOT76_TOG) +#define CCM_PRE76_REG(base) ((base)->PRE76) +#define CCM_PRE_ROOT76_SET_REG(base) ((base)->PRE_ROOT76_SET) +#define CCM_PRE_ROOT76_CLR_REG(base) ((base)->PRE_ROOT76_CLR) +#define CCM_PRE_ROOT76_TOG_REG(base) ((base)->PRE_ROOT76_TOG) +#define CCM_ACCESS_CTRL76_REG(base) ((base)->ACCESS_CTRL76) +#define CCM_ACCESS_CTRL76_ROOT_SET_REG(base) ((base)->ACCESS_CTRL76_ROOT_SET) +#define CCM_ACCESS_CTRL76_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL76_ROOT_CLR) +#define CCM_ACCESS_CTRL76_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL76_ROOT_TOG) +#define CCM_TARGET_ROOT77_REG(base) ((base)->TARGET_ROOT77) +#define CCM_TARGET_ROOT77_SET_REG(base) ((base)->TARGET_ROOT77_SET) +#define CCM_TARGET_ROOT77_CLR_REG(base) ((base)->TARGET_ROOT77_CLR) +#define CCM_TARGET_ROOT77_TOG_REG(base) ((base)->TARGET_ROOT77_TOG) +#define CCM_POST77_REG(base) ((base)->POST77) +#define CCM_POST_ROOT77_SET_REG(base) ((base)->POST_ROOT77_SET) +#define CCM_POST_ROOT77_CLR_REG(base) ((base)->POST_ROOT77_CLR) +#define CCM_POST_ROOT77_TOG_REG(base) ((base)->POST_ROOT77_TOG) +#define CCM_PRE77_REG(base) ((base)->PRE77) +#define CCM_PRE_ROOT77_SET_REG(base) ((base)->PRE_ROOT77_SET) +#define CCM_PRE_ROOT77_CLR_REG(base) ((base)->PRE_ROOT77_CLR) +#define CCM_PRE_ROOT77_TOG_REG(base) ((base)->PRE_ROOT77_TOG) +#define CCM_ACCESS_CTRL77_REG(base) ((base)->ACCESS_CTRL77) +#define CCM_ACCESS_CTRL77_ROOT_SET_REG(base) ((base)->ACCESS_CTRL77_ROOT_SET) +#define CCM_ACCESS_CTRL77_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL77_ROOT_CLR) +#define CCM_ACCESS_CTRL77_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL77_ROOT_TOG) +#define CCM_TARGET_ROOT78_REG(base) ((base)->TARGET_ROOT78) +#define CCM_TARGET_ROOT78_SET_REG(base) ((base)->TARGET_ROOT78_SET) +#define CCM_TARGET_ROOT78_CLR_REG(base) ((base)->TARGET_ROOT78_CLR) +#define CCM_TARGET_ROOT78_TOG_REG(base) ((base)->TARGET_ROOT78_TOG) +#define CCM_POST78_REG(base) ((base)->POST78) +#define CCM_POST_ROOT78_SET_REG(base) ((base)->POST_ROOT78_SET) +#define CCM_POST_ROOT78_CLR_REG(base) ((base)->POST_ROOT78_CLR) +#define CCM_POST_ROOT78_TOG_REG(base) ((base)->POST_ROOT78_TOG) +#define CCM_PRE78_REG(base) ((base)->PRE78) +#define CCM_PRE_ROOT78_SET_REG(base) ((base)->PRE_ROOT78_SET) +#define CCM_PRE_ROOT78_CLR_REG(base) ((base)->PRE_ROOT78_CLR) +#define CCM_PRE_ROOT78_TOG_REG(base) ((base)->PRE_ROOT78_TOG) +#define CCM_ACCESS_CTRL78_REG(base) ((base)->ACCESS_CTRL78) +#define CCM_ACCESS_CTRL78_ROOT_SET_REG(base) ((base)->ACCESS_CTRL78_ROOT_SET) +#define CCM_ACCESS_CTRL78_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL78_ROOT_CLR) +#define CCM_ACCESS_CTRL78_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL78_ROOT_TOG) +#define CCM_TARGET_ROOT79_REG(base) ((base)->TARGET_ROOT79) +#define CCM_TARGET_ROOT79_SET_REG(base) ((base)->TARGET_ROOT79_SET) +#define CCM_TARGET_ROOT79_CLR_REG(base) ((base)->TARGET_ROOT79_CLR) +#define CCM_TARGET_ROOT79_TOG_REG(base) ((base)->TARGET_ROOT79_TOG) +#define CCM_POST79_REG(base) ((base)->POST79) +#define CCM_POST_ROOT79_SET_REG(base) ((base)->POST_ROOT79_SET) +#define CCM_POST_ROOT79_CLR_REG(base) ((base)->POST_ROOT79_CLR) +#define CCM_POST_ROOT79_TOG_REG(base) ((base)->POST_ROOT79_TOG) +#define CCM_PRE79_REG(base) ((base)->PRE79) +#define CCM_PRE_ROOT79_SET_REG(base) ((base)->PRE_ROOT79_SET) +#define CCM_PRE_ROOT79_CLR_REG(base) ((base)->PRE_ROOT79_CLR) +#define CCM_PRE_ROOT79_TOG_REG(base) ((base)->PRE_ROOT79_TOG) +#define CCM_ACCESS_CTRL79_REG(base) ((base)->ACCESS_CTRL79) +#define CCM_ACCESS_CTRL79_ROOT_SET_REG(base) ((base)->ACCESS_CTRL79_ROOT_SET) +#define CCM_ACCESS_CTRL79_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL79_ROOT_CLR) +#define CCM_ACCESS_CTRL79_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL79_ROOT_TOG) +#define CCM_TARGET_ROOT80_REG(base) ((base)->TARGET_ROOT80) +#define CCM_TARGET_ROOT80_SET_REG(base) ((base)->TARGET_ROOT80_SET) +#define CCM_TARGET_ROOT80_CLR_REG(base) ((base)->TARGET_ROOT80_CLR) +#define CCM_TARGET_ROOT80_TOG_REG(base) ((base)->TARGET_ROOT80_TOG) +#define CCM_POST80_REG(base) ((base)->POST80) +#define CCM_POST_ROOT80_SET_REG(base) ((base)->POST_ROOT80_SET) +#define CCM_POST_ROOT80_CLR_REG(base) ((base)->POST_ROOT80_CLR) +#define CCM_POST_ROOT80_TOG_REG(base) ((base)->POST_ROOT80_TOG) +#define CCM_PRE80_REG(base) ((base)->PRE80) +#define CCM_PRE_ROOT80_SET_REG(base) ((base)->PRE_ROOT80_SET) +#define CCM_PRE_ROOT80_CLR_REG(base) ((base)->PRE_ROOT80_CLR) +#define CCM_PRE_ROOT80_TOG_REG(base) ((base)->PRE_ROOT80_TOG) +#define CCM_ACCESS_CTRL80_REG(base) ((base)->ACCESS_CTRL80) +#define CCM_ACCESS_CTRL80_ROOT_SET_REG(base) ((base)->ACCESS_CTRL80_ROOT_SET) +#define CCM_ACCESS_CTRL80_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL80_ROOT_CLR) +#define CCM_ACCESS_CTRL80_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL80_ROOT_TOG) +#define CCM_TARGET_ROOT81_REG(base) ((base)->TARGET_ROOT81) +#define CCM_TARGET_ROOT81_SET_REG(base) ((base)->TARGET_ROOT81_SET) +#define CCM_TARGET_ROOT81_CLR_REG(base) ((base)->TARGET_ROOT81_CLR) +#define CCM_TARGET_ROOT81_TOG_REG(base) ((base)->TARGET_ROOT81_TOG) +#define CCM_POST81_REG(base) ((base)->POST81) +#define CCM_POST_ROOT81_SET_REG(base) ((base)->POST_ROOT81_SET) +#define CCM_POST_ROOT81_CLR_REG(base) ((base)->POST_ROOT81_CLR) +#define CCM_POST_ROOT81_TOG_REG(base) ((base)->POST_ROOT81_TOG) +#define CCM_PRE81_REG(base) ((base)->PRE81) +#define CCM_PRE_ROOT81_SET_REG(base) ((base)->PRE_ROOT81_SET) +#define CCM_PRE_ROOT81_CLR_REG(base) ((base)->PRE_ROOT81_CLR) +#define CCM_PRE_ROOT81_TOG_REG(base) ((base)->PRE_ROOT81_TOG) +#define CCM_ACCESS_CTRL81_REG(base) ((base)->ACCESS_CTRL81) +#define CCM_ACCESS_CTRL81_ROOT_SET_REG(base) ((base)->ACCESS_CTRL81_ROOT_SET) +#define CCM_ACCESS_CTRL81_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL81_ROOT_CLR) +#define CCM_ACCESS_CTRL81_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL81_ROOT_TOG) +#define CCM_TARGET_ROOT82_REG(base) ((base)->TARGET_ROOT82) +#define CCM_TARGET_ROOT82_SET_REG(base) ((base)->TARGET_ROOT82_SET) +#define CCM_TARGET_ROOT82_CLR_REG(base) ((base)->TARGET_ROOT82_CLR) +#define CCM_TARGET_ROOT82_TOG_REG(base) ((base)->TARGET_ROOT82_TOG) +#define CCM_POST82_REG(base) ((base)->POST82) +#define CCM_POST_ROOT82_SET_REG(base) ((base)->POST_ROOT82_SET) +#define CCM_POST_ROOT82_CLR_REG(base) ((base)->POST_ROOT82_CLR) +#define CCM_POST_ROOT82_TOG_REG(base) ((base)->POST_ROOT82_TOG) +#define CCM_PRE82_REG(base) ((base)->PRE82) +#define CCM_PRE_ROOT82_SET_REG(base) ((base)->PRE_ROOT82_SET) +#define CCM_PRE_ROOT82_CLR_REG(base) ((base)->PRE_ROOT82_CLR) +#define CCM_PRE_ROOT82_TOG_REG(base) ((base)->PRE_ROOT82_TOG) +#define CCM_ACCESS_CTRL82_REG(base) ((base)->ACCESS_CTRL82) +#define CCM_ACCESS_CTRL82_ROOT_SET_REG(base) ((base)->ACCESS_CTRL82_ROOT_SET) +#define CCM_ACCESS_CTRL82_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL82_ROOT_CLR) +#define CCM_ACCESS_CTRL82_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL82_ROOT_TOG) +#define CCM_TARGET_ROOT83_REG(base) ((base)->TARGET_ROOT83) +#define CCM_TARGET_ROOT83_SET_REG(base) ((base)->TARGET_ROOT83_SET) +#define CCM_TARGET_ROOT83_CLR_REG(base) ((base)->TARGET_ROOT83_CLR) +#define CCM_TARGET_ROOT83_TOG_REG(base) ((base)->TARGET_ROOT83_TOG) +#define CCM_POST83_REG(base) ((base)->POST83) +#define CCM_POST_ROOT83_SET_REG(base) ((base)->POST_ROOT83_SET) +#define CCM_POST_ROOT83_CLR_REG(base) ((base)->POST_ROOT83_CLR) +#define CCM_POST_ROOT83_TOG_REG(base) ((base)->POST_ROOT83_TOG) +#define CCM_PRE83_REG(base) ((base)->PRE83) +#define CCM_PRE_ROOT83_SET_REG(base) ((base)->PRE_ROOT83_SET) +#define CCM_PRE_ROOT83_CLR_REG(base) ((base)->PRE_ROOT83_CLR) +#define CCM_PRE_ROOT83_TOG_REG(base) ((base)->PRE_ROOT83_TOG) +#define CCM_ACCESS_CTRL83_REG(base) ((base)->ACCESS_CTRL83) +#define CCM_ACCESS_CTRL83_ROOT_SET_REG(base) ((base)->ACCESS_CTRL83_ROOT_SET) +#define CCM_ACCESS_CTRL83_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL83_ROOT_CLR) +#define CCM_ACCESS_CTRL83_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL83_ROOT_TOG) +#define CCM_TARGET_ROOT84_REG(base) ((base)->TARGET_ROOT84) +#define CCM_TARGET_ROOT84_SET_REG(base) ((base)->TARGET_ROOT84_SET) +#define CCM_TARGET_ROOT84_CLR_REG(base) ((base)->TARGET_ROOT84_CLR) +#define CCM_TARGET_ROOT84_TOG_REG(base) ((base)->TARGET_ROOT84_TOG) +#define CCM_POST84_REG(base) ((base)->POST84) +#define CCM_POST_ROOT84_SET_REG(base) ((base)->POST_ROOT84_SET) +#define CCM_POST_ROOT84_CLR_REG(base) ((base)->POST_ROOT84_CLR) +#define CCM_POST_ROOT84_TOG_REG(base) ((base)->POST_ROOT84_TOG) +#define CCM_PRE84_REG(base) ((base)->PRE84) +#define CCM_PRE_ROOT84_SET_REG(base) ((base)->PRE_ROOT84_SET) +#define CCM_PRE_ROOT84_CLR_REG(base) ((base)->PRE_ROOT84_CLR) +#define CCM_PRE_ROOT84_TOG_REG(base) ((base)->PRE_ROOT84_TOG) +#define CCM_ACCESS_CTRL84_REG(base) ((base)->ACCESS_CTRL84) +#define CCM_ACCESS_CTRL84_ROOT_SET_REG(base) ((base)->ACCESS_CTRL84_ROOT_SET) +#define CCM_ACCESS_CTRL84_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL84_ROOT_CLR) +#define CCM_ACCESS_CTRL84_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL84_ROOT_TOG) +#define CCM_TARGET_ROOT85_REG(base) ((base)->TARGET_ROOT85) +#define CCM_TARGET_ROOT85_SET_REG(base) ((base)->TARGET_ROOT85_SET) +#define CCM_TARGET_ROOT85_CLR_REG(base) ((base)->TARGET_ROOT85_CLR) +#define CCM_TARGET_ROOT85_TOG_REG(base) ((base)->TARGET_ROOT85_TOG) +#define CCM_POST85_REG(base) ((base)->POST85) +#define CCM_POST_ROOT85_SET_REG(base) ((base)->POST_ROOT85_SET) +#define CCM_POST_ROOT85_CLR_REG(base) ((base)->POST_ROOT85_CLR) +#define CCM_POST_ROOT85_TOG_REG(base) ((base)->POST_ROOT85_TOG) +#define CCM_PRE85_REG(base) ((base)->PRE85) +#define CCM_PRE_ROOT85_SET_REG(base) ((base)->PRE_ROOT85_SET) +#define CCM_PRE_ROOT85_CLR_REG(base) ((base)->PRE_ROOT85_CLR) +#define CCM_PRE_ROOT85_TOG_REG(base) ((base)->PRE_ROOT85_TOG) +#define CCM_ACCESS_CTRL85_REG(base) ((base)->ACCESS_CTRL85) +#define CCM_ACCESS_CTRL85_ROOT_SET_REG(base) ((base)->ACCESS_CTRL85_ROOT_SET) +#define CCM_ACCESS_CTRL85_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL85_ROOT_CLR) +#define CCM_ACCESS_CTRL85_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL85_ROOT_TOG) +#define CCM_TARGET_ROOT86_REG(base) ((base)->TARGET_ROOT86) +#define CCM_TARGET_ROOT86_SET_REG(base) ((base)->TARGET_ROOT86_SET) +#define CCM_TARGET_ROOT86_CLR_REG(base) ((base)->TARGET_ROOT86_CLR) +#define CCM_TARGET_ROOT86_TOG_REG(base) ((base)->TARGET_ROOT86_TOG) +#define CCM_POST86_REG(base) ((base)->POST86) +#define CCM_POST_ROOT86_SET_REG(base) ((base)->POST_ROOT86_SET) +#define CCM_POST_ROOT86_CLR_REG(base) ((base)->POST_ROOT86_CLR) +#define CCM_POST_ROOT86_TOG_REG(base) ((base)->POST_ROOT86_TOG) +#define CCM_PRE86_REG(base) ((base)->PRE86) +#define CCM_PRE_ROOT86_SET_REG(base) ((base)->PRE_ROOT86_SET) +#define CCM_PRE_ROOT86_CLR_REG(base) ((base)->PRE_ROOT86_CLR) +#define CCM_PRE_ROOT86_TOG_REG(base) ((base)->PRE_ROOT86_TOG) +#define CCM_ACCESS_CTRL86_REG(base) ((base)->ACCESS_CTRL86) +#define CCM_ACCESS_CTRL86_ROOT_SET_REG(base) ((base)->ACCESS_CTRL86_ROOT_SET) +#define CCM_ACCESS_CTRL86_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL86_ROOT_CLR) +#define CCM_ACCESS_CTRL86_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL86_ROOT_TOG) +#define CCM_TARGET_ROOT87_REG(base) ((base)->TARGET_ROOT87) +#define CCM_TARGET_ROOT87_SET_REG(base) ((base)->TARGET_ROOT87_SET) +#define CCM_TARGET_ROOT87_CLR_REG(base) ((base)->TARGET_ROOT87_CLR) +#define CCM_TARGET_ROOT87_TOG_REG(base) ((base)->TARGET_ROOT87_TOG) +#define CCM_POST87_REG(base) ((base)->POST87) +#define CCM_POST_ROOT87_SET_REG(base) ((base)->POST_ROOT87_SET) +#define CCM_POST_ROOT87_CLR_REG(base) ((base)->POST_ROOT87_CLR) +#define CCM_POST_ROOT87_TOG_REG(base) ((base)->POST_ROOT87_TOG) +#define CCM_PRE87_REG(base) ((base)->PRE87) +#define CCM_PRE_ROOT87_SET_REG(base) ((base)->PRE_ROOT87_SET) +#define CCM_PRE_ROOT87_CLR_REG(base) ((base)->PRE_ROOT87_CLR) +#define CCM_PRE_ROOT87_TOG_REG(base) ((base)->PRE_ROOT87_TOG) +#define CCM_ACCESS_CTRL87_REG(base) ((base)->ACCESS_CTRL87) +#define CCM_ACCESS_CTRL87_ROOT_SET_REG(base) ((base)->ACCESS_CTRL87_ROOT_SET) +#define CCM_ACCESS_CTRL87_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL87_ROOT_CLR) +#define CCM_ACCESS_CTRL87_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL87_ROOT_TOG) +#define CCM_TARGET_ROOT88_REG(base) ((base)->TARGET_ROOT88) +#define CCM_TARGET_ROOT88_SET_REG(base) ((base)->TARGET_ROOT88_SET) +#define CCM_TARGET_ROOT88_CLR_REG(base) ((base)->TARGET_ROOT88_CLR) +#define CCM_TARGET_ROOT88_TOG_REG(base) ((base)->TARGET_ROOT88_TOG) +#define CCM_POST88_REG(base) ((base)->POST88) +#define CCM_POST_ROOT88_SET_REG(base) ((base)->POST_ROOT88_SET) +#define CCM_POST_ROOT88_CLR_REG(base) ((base)->POST_ROOT88_CLR) +#define CCM_POST_ROOT88_TOG_REG(base) ((base)->POST_ROOT88_TOG) +#define CCM_PRE88_REG(base) ((base)->PRE88) +#define CCM_PRE_ROOT88_SET_REG(base) ((base)->PRE_ROOT88_SET) +#define CCM_PRE_ROOT88_CLR_REG(base) ((base)->PRE_ROOT88_CLR) +#define CCM_PRE_ROOT88_TOG_REG(base) ((base)->PRE_ROOT88_TOG) +#define CCM_ACCESS_CTRL88_REG(base) ((base)->ACCESS_CTRL88) +#define CCM_ACCESS_CTRL88_ROOT_SET_REG(base) ((base)->ACCESS_CTRL88_ROOT_SET) +#define CCM_ACCESS_CTRL88_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL88_ROOT_CLR) +#define CCM_ACCESS_CTRL88_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL88_ROOT_TOG) +#define CCM_TARGET_ROOT89_REG(base) ((base)->TARGET_ROOT89) +#define CCM_TARGET_ROOT89_SET_REG(base) ((base)->TARGET_ROOT89_SET) +#define CCM_TARGET_ROOT89_CLR_REG(base) ((base)->TARGET_ROOT89_CLR) +#define CCM_TARGET_ROOT89_TOG_REG(base) ((base)->TARGET_ROOT89_TOG) +#define CCM_POST89_REG(base) ((base)->POST89) +#define CCM_POST_ROOT89_SET_REG(base) ((base)->POST_ROOT89_SET) +#define CCM_POST_ROOT89_CLR_REG(base) ((base)->POST_ROOT89_CLR) +#define CCM_POST_ROOT89_TOG_REG(base) ((base)->POST_ROOT89_TOG) +#define CCM_PRE89_REG(base) ((base)->PRE89) +#define CCM_PRE_ROOT89_SET_REG(base) ((base)->PRE_ROOT89_SET) +#define CCM_PRE_ROOT89_CLR_REG(base) ((base)->PRE_ROOT89_CLR) +#define CCM_PRE_ROOT89_TOG_REG(base) ((base)->PRE_ROOT89_TOG) +#define CCM_ACCESS_CTRL89_REG(base) ((base)->ACCESS_CTRL89) +#define CCM_ACCESS_CTRL89_ROOT_SET_REG(base) ((base)->ACCESS_CTRL89_ROOT_SET) +#define CCM_ACCESS_CTRL89_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL89_ROOT_CLR) +#define CCM_ACCESS_CTRL89_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL89_ROOT_TOG) +#define CCM_TARGET_ROOT90_REG(base) ((base)->TARGET_ROOT90) +#define CCM_TARGET_ROOT90_SET_REG(base) ((base)->TARGET_ROOT90_SET) +#define CCM_TARGET_ROOT90_CLR_REG(base) ((base)->TARGET_ROOT90_CLR) +#define CCM_TARGET_ROOT90_TOG_REG(base) ((base)->TARGET_ROOT90_TOG) +#define CCM_POST90_REG(base) ((base)->POST90) +#define CCM_POST_ROOT90_SET_REG(base) ((base)->POST_ROOT90_SET) +#define CCM_POST_ROOT90_CLR_REG(base) ((base)->POST_ROOT90_CLR) +#define CCM_POST_ROOT90_TOG_REG(base) ((base)->POST_ROOT90_TOG) +#define CCM_PRE90_REG(base) ((base)->PRE90) +#define CCM_PRE_ROOT90_SET_REG(base) ((base)->PRE_ROOT90_SET) +#define CCM_PRE_ROOT90_CLR_REG(base) ((base)->PRE_ROOT90_CLR) +#define CCM_PRE_ROOT90_TOG_REG(base) ((base)->PRE_ROOT90_TOG) +#define CCM_ACCESS_CTRL90_REG(base) ((base)->ACCESS_CTRL90) +#define CCM_ACCESS_CTRL90_ROOT_SET_REG(base) ((base)->ACCESS_CTRL90_ROOT_SET) +#define CCM_ACCESS_CTRL90_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL90_ROOT_CLR) +#define CCM_ACCESS_CTRL90_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL90_ROOT_TOG) +#define CCM_TARGET_ROOT91_REG(base) ((base)->TARGET_ROOT91) +#define CCM_TARGET_ROOT91_SET_REG(base) ((base)->TARGET_ROOT91_SET) +#define CCM_TARGET_ROOT91_CLR_REG(base) ((base)->TARGET_ROOT91_CLR) +#define CCM_TARGET_ROOT91_TOG_REG(base) ((base)->TARGET_ROOT91_TOG) +#define CCM_POST91_REG(base) ((base)->POST91) +#define CCM_POST_ROOT91_SET_REG(base) ((base)->POST_ROOT91_SET) +#define CCM_POST_ROOT91_CLR_REG(base) ((base)->POST_ROOT91_CLR) +#define CCM_POST_ROOT91_TOG_REG(base) ((base)->POST_ROOT91_TOG) +#define CCM_PRE91_REG(base) ((base)->PRE91) +#define CCM_PRE_ROOT91_SET_REG(base) ((base)->PRE_ROOT91_SET) +#define CCM_PRE_ROOT91_CLR_REG(base) ((base)->PRE_ROOT91_CLR) +#define CCM_PRE_ROOT91_TOG_REG(base) ((base)->PRE_ROOT91_TOG) +#define CCM_ACCESS_CTRL91_REG(base) ((base)->ACCESS_CTRL91) +#define CCM_ACCESS_CTRL91_ROOT_SET_REG(base) ((base)->ACCESS_CTRL91_ROOT_SET) +#define CCM_ACCESS_CTRL91_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL91_ROOT_CLR) +#define CCM_ACCESS_CTRL91_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL91_ROOT_TOG) +#define CCM_TARGET_ROOT92_REG(base) ((base)->TARGET_ROOT92) +#define CCM_TARGET_ROOT92_SET_REG(base) ((base)->TARGET_ROOT92_SET) +#define CCM_TARGET_ROOT92_CLR_REG(base) ((base)->TARGET_ROOT92_CLR) +#define CCM_TARGET_ROOT92_TOG_REG(base) ((base)->TARGET_ROOT92_TOG) +#define CCM_POST92_REG(base) ((base)->POST92) +#define CCM_POST_ROOT92_SET_REG(base) ((base)->POST_ROOT92_SET) +#define CCM_POST_ROOT92_CLR_REG(base) ((base)->POST_ROOT92_CLR) +#define CCM_POST_ROOT92_TOG_REG(base) ((base)->POST_ROOT92_TOG) +#define CCM_PRE92_REG(base) ((base)->PRE92) +#define CCM_PRE_ROOT92_SET_REG(base) ((base)->PRE_ROOT92_SET) +#define CCM_PRE_ROOT92_CLR_REG(base) ((base)->PRE_ROOT92_CLR) +#define CCM_PRE_ROOT92_TOG_REG(base) ((base)->PRE_ROOT92_TOG) +#define CCM_ACCESS_CTRL92_REG(base) ((base)->ACCESS_CTRL92) +#define CCM_ACCESS_CTRL92_ROOT_SET_REG(base) ((base)->ACCESS_CTRL92_ROOT_SET) +#define CCM_ACCESS_CTRL92_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL92_ROOT_CLR) +#define CCM_ACCESS_CTRL92_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL92_ROOT_TOG) +#define CCM_TARGET_ROOT93_REG(base) ((base)->TARGET_ROOT93) +#define CCM_TARGET_ROOT93_SET_REG(base) ((base)->TARGET_ROOT93_SET) +#define CCM_TARGET_ROOT93_CLR_REG(base) ((base)->TARGET_ROOT93_CLR) +#define CCM_TARGET_ROOT93_TOG_REG(base) ((base)->TARGET_ROOT93_TOG) +#define CCM_POST93_REG(base) ((base)->POST93) +#define CCM_POST_ROOT93_SET_REG(base) ((base)->POST_ROOT93_SET) +#define CCM_POST_ROOT93_CLR_REG(base) ((base)->POST_ROOT93_CLR) +#define CCM_POST_ROOT93_TOG_REG(base) ((base)->POST_ROOT93_TOG) +#define CCM_PRE93_REG(base) ((base)->PRE93) +#define CCM_PRE_ROOT93_SET_REG(base) ((base)->PRE_ROOT93_SET) +#define CCM_PRE_ROOT93_CLR_REG(base) ((base)->PRE_ROOT93_CLR) +#define CCM_PRE_ROOT93_TOG_REG(base) ((base)->PRE_ROOT93_TOG) +#define CCM_ACCESS_CTRL93_REG(base) ((base)->ACCESS_CTRL93) +#define CCM_ACCESS_CTRL93_ROOT_SET_REG(base) ((base)->ACCESS_CTRL93_ROOT_SET) +#define CCM_ACCESS_CTRL93_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL93_ROOT_CLR) +#define CCM_ACCESS_CTRL93_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL93_ROOT_TOG) +#define CCM_TARGET_ROOT94_REG(base) ((base)->TARGET_ROOT94) +#define CCM_TARGET_ROOT94_SET_REG(base) ((base)->TARGET_ROOT94_SET) +#define CCM_TARGET_ROOT94_CLR_REG(base) ((base)->TARGET_ROOT94_CLR) +#define CCM_TARGET_ROOT94_TOG_REG(base) ((base)->TARGET_ROOT94_TOG) +#define CCM_POST94_REG(base) ((base)->POST94) +#define CCM_POST_ROOT94_SET_REG(base) ((base)->POST_ROOT94_SET) +#define CCM_POST_ROOT94_CLR_REG(base) ((base)->POST_ROOT94_CLR) +#define CCM_POST_ROOT94_TOG_REG(base) ((base)->POST_ROOT94_TOG) +#define CCM_PRE94_REG(base) ((base)->PRE94) +#define CCM_PRE_ROOT94_SET_REG(base) ((base)->PRE_ROOT94_SET) +#define CCM_PRE_ROOT94_CLR_REG(base) ((base)->PRE_ROOT94_CLR) +#define CCM_PRE_ROOT94_TOG_REG(base) ((base)->PRE_ROOT94_TOG) +#define CCM_ACCESS_CTRL94_REG(base) ((base)->ACCESS_CTRL94) +#define CCM_ACCESS_CTRL94_ROOT_SET_REG(base) ((base)->ACCESS_CTRL94_ROOT_SET) +#define CCM_ACCESS_CTRL94_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL94_ROOT_CLR) +#define CCM_ACCESS_CTRL94_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL94_ROOT_TOG) +#define CCM_TARGET_ROOT95_REG(base) ((base)->TARGET_ROOT95) +#define CCM_TARGET_ROOT95_SET_REG(base) ((base)->TARGET_ROOT95_SET) +#define CCM_TARGET_ROOT95_CLR_REG(base) ((base)->TARGET_ROOT95_CLR) +#define CCM_TARGET_ROOT95_TOG_REG(base) ((base)->TARGET_ROOT95_TOG) +#define CCM_POST95_REG(base) ((base)->POST95) +#define CCM_POST_ROOT95_SET_REG(base) ((base)->POST_ROOT95_SET) +#define CCM_POST_ROOT95_CLR_REG(base) ((base)->POST_ROOT95_CLR) +#define CCM_POST_ROOT95_TOG_REG(base) ((base)->POST_ROOT95_TOG) +#define CCM_PRE95_REG(base) ((base)->PRE95) +#define CCM_PRE_ROOT95_SET_REG(base) ((base)->PRE_ROOT95_SET) +#define CCM_PRE_ROOT95_CLR_REG(base) ((base)->PRE_ROOT95_CLR) +#define CCM_PRE_ROOT95_TOG_REG(base) ((base)->PRE_ROOT95_TOG) +#define CCM_ACCESS_CTRL95_REG(base) ((base)->ACCESS_CTRL95) +#define CCM_ACCESS_CTRL95_ROOT_SET_REG(base) ((base)->ACCESS_CTRL95_ROOT_SET) +#define CCM_ACCESS_CTRL95_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL95_ROOT_CLR) +#define CCM_ACCESS_CTRL95_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL95_ROOT_TOG) +#define CCM_TARGET_ROOT96_REG(base) ((base)->TARGET_ROOT96) +#define CCM_TARGET_ROOT96_SET_REG(base) ((base)->TARGET_ROOT96_SET) +#define CCM_TARGET_ROOT96_CLR_REG(base) ((base)->TARGET_ROOT96_CLR) +#define CCM_TARGET_ROOT96_TOG_REG(base) ((base)->TARGET_ROOT96_TOG) +#define CCM_POST96_REG(base) ((base)->POST96) +#define CCM_POST_ROOT96_SET_REG(base) ((base)->POST_ROOT96_SET) +#define CCM_POST_ROOT96_CLR_REG(base) ((base)->POST_ROOT96_CLR) +#define CCM_POST_ROOT96_TOG_REG(base) ((base)->POST_ROOT96_TOG) +#define CCM_PRE96_REG(base) ((base)->PRE96) +#define CCM_PRE_ROOT96_SET_REG(base) ((base)->PRE_ROOT96_SET) +#define CCM_PRE_ROOT96_CLR_REG(base) ((base)->PRE_ROOT96_CLR) +#define CCM_PRE_ROOT96_TOG_REG(base) ((base)->PRE_ROOT96_TOG) +#define CCM_ACCESS_CTRL96_REG(base) ((base)->ACCESS_CTRL96) +#define CCM_ACCESS_CTRL96_ROOT_SET_REG(base) ((base)->ACCESS_CTRL96_ROOT_SET) +#define CCM_ACCESS_CTRL96_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL96_ROOT_CLR) +#define CCM_ACCESS_CTRL96_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL96_ROOT_TOG) +#define CCM_TARGET_ROOT97_REG(base) ((base)->TARGET_ROOT97) +#define CCM_TARGET_ROOT97_SET_REG(base) ((base)->TARGET_ROOT97_SET) +#define CCM_TARGET_ROOT97_CLR_REG(base) ((base)->TARGET_ROOT97_CLR) +#define CCM_TARGET_ROOT97_TOG_REG(base) ((base)->TARGET_ROOT97_TOG) +#define CCM_POST97_REG(base) ((base)->POST97) +#define CCM_POST_ROOT97_SET_REG(base) ((base)->POST_ROOT97_SET) +#define CCM_POST_ROOT97_CLR_REG(base) ((base)->POST_ROOT97_CLR) +#define CCM_POST_ROOT97_TOG_REG(base) ((base)->POST_ROOT97_TOG) +#define CCM_PRE97_REG(base) ((base)->PRE97) +#define CCM_PRE_ROOT97_SET_REG(base) ((base)->PRE_ROOT97_SET) +#define CCM_PRE_ROOT97_CLR_REG(base) ((base)->PRE_ROOT97_CLR) +#define CCM_PRE_ROOT97_TOG_REG(base) ((base)->PRE_ROOT97_TOG) +#define CCM_ACCESS_CTRL97_REG(base) ((base)->ACCESS_CTRL97) +#define CCM_ACCESS_CTRL97_ROOT_SET_REG(base) ((base)->ACCESS_CTRL97_ROOT_SET) +#define CCM_ACCESS_CTRL97_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL97_ROOT_CLR) +#define CCM_ACCESS_CTRL97_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL97_ROOT_TOG) +#define CCM_TARGET_ROOT98_REG(base) ((base)->TARGET_ROOT98) +#define CCM_TARGET_ROOT98_SET_REG(base) ((base)->TARGET_ROOT98_SET) +#define CCM_TARGET_ROOT98_CLR_REG(base) ((base)->TARGET_ROOT98_CLR) +#define CCM_TARGET_ROOT98_TOG_REG(base) ((base)->TARGET_ROOT98_TOG) +#define CCM_POST98_REG(base) ((base)->POST98) +#define CCM_POST_ROOT98_SET_REG(base) ((base)->POST_ROOT98_SET) +#define CCM_POST_ROOT98_CLR_REG(base) ((base)->POST_ROOT98_CLR) +#define CCM_POST_ROOT98_TOG_REG(base) ((base)->POST_ROOT98_TOG) +#define CCM_PRE98_REG(base) ((base)->PRE98) +#define CCM_PRE_ROOT98_SET_REG(base) ((base)->PRE_ROOT98_SET) +#define CCM_PRE_ROOT98_CLR_REG(base) ((base)->PRE_ROOT98_CLR) +#define CCM_PRE_ROOT98_TOG_REG(base) ((base)->PRE_ROOT98_TOG) +#define CCM_ACCESS_CTRL98_REG(base) ((base)->ACCESS_CTRL98) +#define CCM_ACCESS_CTRL98_ROOT_SET_REG(base) ((base)->ACCESS_CTRL98_ROOT_SET) +#define CCM_ACCESS_CTRL98_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL98_ROOT_CLR) +#define CCM_ACCESS_CTRL98_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL98_ROOT_TOG) +#define CCM_TARGET_ROOT99_REG(base) ((base)->TARGET_ROOT99) +#define CCM_TARGET_ROOT99_SET_REG(base) ((base)->TARGET_ROOT99_SET) +#define CCM_TARGET_ROOT99_CLR_REG(base) ((base)->TARGET_ROOT99_CLR) +#define CCM_TARGET_ROOT99_TOG_REG(base) ((base)->TARGET_ROOT99_TOG) +#define CCM_POST99_REG(base) ((base)->POST99) +#define CCM_POST_ROOT99_SET_REG(base) ((base)->POST_ROOT99_SET) +#define CCM_POST_ROOT99_CLR_REG(base) ((base)->POST_ROOT99_CLR) +#define CCM_POST_ROOT99_TOG_REG(base) ((base)->POST_ROOT99_TOG) +#define CCM_PRE99_REG(base) ((base)->PRE99) +#define CCM_PRE_ROOT99_SET_REG(base) ((base)->PRE_ROOT99_SET) +#define CCM_PRE_ROOT99_CLR_REG(base) ((base)->PRE_ROOT99_CLR) +#define CCM_PRE_ROOT99_TOG_REG(base) ((base)->PRE_ROOT99_TOG) +#define CCM_ACCESS_CTRL99_REG(base) ((base)->ACCESS_CTRL99) +#define CCM_ACCESS_CTRL99_ROOT_SET_REG(base) ((base)->ACCESS_CTRL99_ROOT_SET) +#define CCM_ACCESS_CTRL99_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL99_ROOT_CLR) +#define CCM_ACCESS_CTRL99_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL99_ROOT_TOG) +#define CCM_TARGET_ROOT100_REG(base) ((base)->TARGET_ROOT100) +#define CCM_TARGET_ROOT100_SET_REG(base) ((base)->TARGET_ROOT100_SET) +#define CCM_TARGET_ROOT100_CLR_REG(base) ((base)->TARGET_ROOT100_CLR) +#define CCM_TARGET_ROOT100_TOG_REG(base) ((base)->TARGET_ROOT100_TOG) +#define CCM_POST100_REG(base) ((base)->POST100) +#define CCM_POST_ROOT100_SET_REG(base) ((base)->POST_ROOT100_SET) +#define CCM_POST_ROOT100_CLR_REG(base) ((base)->POST_ROOT100_CLR) +#define CCM_POST_ROOT100_TOG_REG(base) ((base)->POST_ROOT100_TOG) +#define CCM_PRE100_REG(base) ((base)->PRE100) +#define CCM_PRE_ROOT100_SET_REG(base) ((base)->PRE_ROOT100_SET) +#define CCM_PRE_ROOT100_CLR_REG(base) ((base)->PRE_ROOT100_CLR) +#define CCM_PRE_ROOT100_TOG_REG(base) ((base)->PRE_ROOT100_TOG) +#define CCM_ACCESS_CTRL100_REG(base) ((base)->ACCESS_CTRL100) +#define CCM_ACCESS_CTRL100_ROOT_SET_REG(base) ((base)->ACCESS_CTRL100_ROOT_SET) +#define CCM_ACCESS_CTRL100_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL100_ROOT_CLR) +#define CCM_ACCESS_CTRL100_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL100_ROOT_TOG) +#define CCM_TARGET_ROOT101_REG(base) ((base)->TARGET_ROOT101) +#define CCM_TARGET_ROOT101_SET_REG(base) ((base)->TARGET_ROOT101_SET) +#define CCM_TARGET_ROOT101_CLR_REG(base) ((base)->TARGET_ROOT101_CLR) +#define CCM_TARGET_ROOT101_TOG_REG(base) ((base)->TARGET_ROOT101_TOG) +#define CCM_POST101_REG(base) ((base)->POST101) +#define CCM_POST_ROOT101_SET_REG(base) ((base)->POST_ROOT101_SET) +#define CCM_POST_ROOT101_CLR_REG(base) ((base)->POST_ROOT101_CLR) +#define CCM_POST_ROOT101_TOG_REG(base) ((base)->POST_ROOT101_TOG) +#define CCM_PRE101_REG(base) ((base)->PRE101) +#define CCM_PRE_ROOT101_SET_REG(base) ((base)->PRE_ROOT101_SET) +#define CCM_PRE_ROOT101_CLR_REG(base) ((base)->PRE_ROOT101_CLR) +#define CCM_PRE_ROOT101_TOG_REG(base) ((base)->PRE_ROOT101_TOG) +#define CCM_ACCESS_CTRL101_REG(base) ((base)->ACCESS_CTRL101) +#define CCM_ACCESS_CTRL101_ROOT_SET_REG(base) ((base)->ACCESS_CTRL101_ROOT_SET) +#define CCM_ACCESS_CTRL101_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL101_ROOT_CLR) +#define CCM_ACCESS_CTRL101_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL101_ROOT_TOG) +#define CCM_TARGET_ROOT102_REG(base) ((base)->TARGET_ROOT102) +#define CCM_TARGET_ROOT102_SET_REG(base) ((base)->TARGET_ROOT102_SET) +#define CCM_TARGET_ROOT102_CLR_REG(base) ((base)->TARGET_ROOT102_CLR) +#define CCM_TARGET_ROOT102_TOG_REG(base) ((base)->TARGET_ROOT102_TOG) +#define CCM_POST102_REG(base) ((base)->POST102) +#define CCM_POST_ROOT102_SET_REG(base) ((base)->POST_ROOT102_SET) +#define CCM_POST_ROOT102_CLR_REG(base) ((base)->POST_ROOT102_CLR) +#define CCM_POST_ROOT102_TOG_REG(base) ((base)->POST_ROOT102_TOG) +#define CCM_PRE102_REG(base) ((base)->PRE102) +#define CCM_PRE_ROOT102_SET_REG(base) ((base)->PRE_ROOT102_SET) +#define CCM_PRE_ROOT102_CLR_REG(base) ((base)->PRE_ROOT102_CLR) +#define CCM_PRE_ROOT102_TOG_REG(base) ((base)->PRE_ROOT102_TOG) +#define CCM_ACCESS_CTRL102_REG(base) ((base)->ACCESS_CTRL102) +#define CCM_ACCESS_CTRL102_ROOT_SET_REG(base) ((base)->ACCESS_CTRL102_ROOT_SET) +#define CCM_ACCESS_CTRL102_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL102_ROOT_CLR) +#define CCM_ACCESS_CTRL102_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL102_ROOT_TOG) +#define CCM_TARGET_ROOT103_REG(base) ((base)->TARGET_ROOT103) +#define CCM_TARGET_ROOT103_SET_REG(base) ((base)->TARGET_ROOT103_SET) +#define CCM_TARGET_ROOT103_CLR_REG(base) ((base)->TARGET_ROOT103_CLR) +#define CCM_TARGET_ROOT103_TOG_REG(base) ((base)->TARGET_ROOT103_TOG) +#define CCM_POST103_REG(base) ((base)->POST103) +#define CCM_POST_ROOT103_SET_REG(base) ((base)->POST_ROOT103_SET) +#define CCM_POST_ROOT103_CLR_REG(base) ((base)->POST_ROOT103_CLR) +#define CCM_POST_ROOT103_TOG_REG(base) ((base)->POST_ROOT103_TOG) +#define CCM_PRE103_REG(base) ((base)->PRE103) +#define CCM_PRE_ROOT103_SET_REG(base) ((base)->PRE_ROOT103_SET) +#define CCM_PRE_ROOT103_CLR_REG(base) ((base)->PRE_ROOT103_CLR) +#define CCM_PRE_ROOT103_TOG_REG(base) ((base)->PRE_ROOT103_TOG) +#define CCM_ACCESS_CTRL103_REG(base) ((base)->ACCESS_CTRL103) +#define CCM_ACCESS_CTRL103_ROOT_SET_REG(base) ((base)->ACCESS_CTRL103_ROOT_SET) +#define CCM_ACCESS_CTRL103_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL103_ROOT_CLR) +#define CCM_ACCESS_CTRL103_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL103_ROOT_TOG) +#define CCM_TARGET_ROOT104_REG(base) ((base)->TARGET_ROOT104) +#define CCM_TARGET_ROOT104_SET_REG(base) ((base)->TARGET_ROOT104_SET) +#define CCM_TARGET_ROOT104_CLR_REG(base) ((base)->TARGET_ROOT104_CLR) +#define CCM_TARGET_ROOT104_TOG_REG(base) ((base)->TARGET_ROOT104_TOG) +#define CCM_POST104_REG(base) ((base)->POST104) +#define CCM_POST_ROOT104_SET_REG(base) ((base)->POST_ROOT104_SET) +#define CCM_POST_ROOT104_CLR_REG(base) ((base)->POST_ROOT104_CLR) +#define CCM_POST_ROOT104_TOG_REG(base) ((base)->POST_ROOT104_TOG) +#define CCM_PRE104_REG(base) ((base)->PRE104) +#define CCM_PRE_ROOT104_SET_REG(base) ((base)->PRE_ROOT104_SET) +#define CCM_PRE_ROOT104_CLR_REG(base) ((base)->PRE_ROOT104_CLR) +#define CCM_PRE_ROOT104_TOG_REG(base) ((base)->PRE_ROOT104_TOG) +#define CCM_ACCESS_CTRL104_REG(base) ((base)->ACCESS_CTRL104) +#define CCM_ACCESS_CTRL104_ROOT_SET_REG(base) ((base)->ACCESS_CTRL104_ROOT_SET) +#define CCM_ACCESS_CTRL104_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL104_ROOT_CLR) +#define CCM_ACCESS_CTRL104_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL104_ROOT_TOG) +#define CCM_TARGET_ROOT105_REG(base) ((base)->TARGET_ROOT105) +#define CCM_TARGET_ROOT105_SET_REG(base) ((base)->TARGET_ROOT105_SET) +#define CCM_TARGET_ROOT105_CLR_REG(base) ((base)->TARGET_ROOT105_CLR) +#define CCM_TARGET_ROOT105_TOG_REG(base) ((base)->TARGET_ROOT105_TOG) +#define CCM_POST105_REG(base) ((base)->POST105) +#define CCM_POST_ROOT105_SET_REG(base) ((base)->POST_ROOT105_SET) +#define CCM_POST_ROOT105_CLR_REG(base) ((base)->POST_ROOT105_CLR) +#define CCM_POST_ROOT105_TOG_REG(base) ((base)->POST_ROOT105_TOG) +#define CCM_PRE105_REG(base) ((base)->PRE105) +#define CCM_PRE_ROOT105_SET_REG(base) ((base)->PRE_ROOT105_SET) +#define CCM_PRE_ROOT105_CLR_REG(base) ((base)->PRE_ROOT105_CLR) +#define CCM_PRE_ROOT105_TOG_REG(base) ((base)->PRE_ROOT105_TOG) +#define CCM_ACCESS_CTRL105_REG(base) ((base)->ACCESS_CTRL105) +#define CCM_ACCESS_CTRL105_ROOT_SET_REG(base) ((base)->ACCESS_CTRL105_ROOT_SET) +#define CCM_ACCESS_CTRL105_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL105_ROOT_CLR) +#define CCM_ACCESS_CTRL105_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL105_ROOT_TOG) +#define CCM_TARGET_ROOT106_REG(base) ((base)->TARGET_ROOT106) +#define CCM_TARGET_ROOT106_SET_REG(base) ((base)->TARGET_ROOT106_SET) +#define CCM_TARGET_ROOT106_CLR_REG(base) ((base)->TARGET_ROOT106_CLR) +#define CCM_TARGET_ROOT106_TOG_REG(base) ((base)->TARGET_ROOT106_TOG) +#define CCM_POST106_REG(base) ((base)->POST106) +#define CCM_POST_ROOT106_SET_REG(base) ((base)->POST_ROOT106_SET) +#define CCM_POST_ROOT106_CLR_REG(base) ((base)->POST_ROOT106_CLR) +#define CCM_POST_ROOT106_TOG_REG(base) ((base)->POST_ROOT106_TOG) +#define CCM_PRE106_REG(base) ((base)->PRE106) +#define CCM_PRE_ROOT106_SET_REG(base) ((base)->PRE_ROOT106_SET) +#define CCM_PRE_ROOT106_CLR_REG(base) ((base)->PRE_ROOT106_CLR) +#define CCM_PRE_ROOT106_TOG_REG(base) ((base)->PRE_ROOT106_TOG) +#define CCM_ACCESS_CTRL106_REG(base) ((base)->ACCESS_CTRL106) +#define CCM_ACCESS_CTRL106_ROOT_SET_REG(base) ((base)->ACCESS_CTRL106_ROOT_SET) +#define CCM_ACCESS_CTRL106_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL106_ROOT_CLR) +#define CCM_ACCESS_CTRL106_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL106_ROOT_TOG) +#define CCM_TARGET_ROOT107_REG(base) ((base)->TARGET_ROOT107) +#define CCM_TARGET_ROOT107_SET_REG(base) ((base)->TARGET_ROOT107_SET) +#define CCM_TARGET_ROOT107_CLR_REG(base) ((base)->TARGET_ROOT107_CLR) +#define CCM_TARGET_ROOT107_TOG_REG(base) ((base)->TARGET_ROOT107_TOG) +#define CCM_POST107_REG(base) ((base)->POST107) +#define CCM_POST_ROOT107_SET_REG(base) ((base)->POST_ROOT107_SET) +#define CCM_POST_ROOT107_CLR_REG(base) ((base)->POST_ROOT107_CLR) +#define CCM_POST_ROOT107_TOG_REG(base) ((base)->POST_ROOT107_TOG) +#define CCM_PRE107_REG(base) ((base)->PRE107) +#define CCM_PRE_ROOT107_SET_REG(base) ((base)->PRE_ROOT107_SET) +#define CCM_PRE_ROOT107_CLR_REG(base) ((base)->PRE_ROOT107_CLR) +#define CCM_PRE_ROOT107_TOG_REG(base) ((base)->PRE_ROOT107_TOG) +#define CCM_ACCESS_CTRL107_REG(base) ((base)->ACCESS_CTRL107) +#define CCM_ACCESS_CTRL107_ROOT_SET_REG(base) ((base)->ACCESS_CTRL107_ROOT_SET) +#define CCM_ACCESS_CTRL107_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL107_ROOT_CLR) +#define CCM_ACCESS_CTRL107_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL107_ROOT_TOG) +#define CCM_TARGET_ROOT108_REG(base) ((base)->TARGET_ROOT108) +#define CCM_TARGET_ROOT108_SET_REG(base) ((base)->TARGET_ROOT108_SET) +#define CCM_TARGET_ROOT108_CLR_REG(base) ((base)->TARGET_ROOT108_CLR) +#define CCM_TARGET_ROOT108_TOG_REG(base) ((base)->TARGET_ROOT108_TOG) +#define CCM_POST108_REG(base) ((base)->POST108) +#define CCM_POST_ROOT108_SET_REG(base) ((base)->POST_ROOT108_SET) +#define CCM_POST_ROOT108_CLR_REG(base) ((base)->POST_ROOT108_CLR) +#define CCM_POST_ROOT108_TOG_REG(base) ((base)->POST_ROOT108_TOG) +#define CCM_PRE108_REG(base) ((base)->PRE108) +#define CCM_PRE_ROOT108_SET_REG(base) ((base)->PRE_ROOT108_SET) +#define CCM_PRE_ROOT108_CLR_REG(base) ((base)->PRE_ROOT108_CLR) +#define CCM_PRE_ROOT108_TOG_REG(base) ((base)->PRE_ROOT108_TOG) +#define CCM_ACCESS_CTRL108_REG(base) ((base)->ACCESS_CTRL108) +#define CCM_ACCESS_CTRL108_ROOT_SET_REG(base) ((base)->ACCESS_CTRL108_ROOT_SET) +#define CCM_ACCESS_CTRL108_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL108_ROOT_CLR) +#define CCM_ACCESS_CTRL108_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL108_ROOT_TOG) +#define CCM_TARGET_ROOT109_REG(base) ((base)->TARGET_ROOT109) +#define CCM_TARGET_ROOT109_SET_REG(base) ((base)->TARGET_ROOT109_SET) +#define CCM_TARGET_ROOT109_CLR_REG(base) ((base)->TARGET_ROOT109_CLR) +#define CCM_TARGET_ROOT109_TOG_REG(base) ((base)->TARGET_ROOT109_TOG) +#define CCM_POST109_REG(base) ((base)->POST109) +#define CCM_POST_ROOT109_SET_REG(base) ((base)->POST_ROOT109_SET) +#define CCM_POST_ROOT109_CLR_REG(base) ((base)->POST_ROOT109_CLR) +#define CCM_POST_ROOT109_TOG_REG(base) ((base)->POST_ROOT109_TOG) +#define CCM_PRE109_REG(base) ((base)->PRE109) +#define CCM_PRE_ROOT109_SET_REG(base) ((base)->PRE_ROOT109_SET) +#define CCM_PRE_ROOT109_CLR_REG(base) ((base)->PRE_ROOT109_CLR) +#define CCM_PRE_ROOT109_TOG_REG(base) ((base)->PRE_ROOT109_TOG) +#define CCM_ACCESS_CTRL109_REG(base) ((base)->ACCESS_CTRL109) +#define CCM_ACCESS_CTRL109_ROOT_SET_REG(base) ((base)->ACCESS_CTRL109_ROOT_SET) +#define CCM_ACCESS_CTRL109_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL109_ROOT_CLR) +#define CCM_ACCESS_CTRL109_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL109_ROOT_TOG) +#define CCM_TARGET_ROOT110_REG(base) ((base)->TARGET_ROOT110) +#define CCM_TARGET_ROOT110_SET_REG(base) ((base)->TARGET_ROOT110_SET) +#define CCM_TARGET_ROOT110_CLR_REG(base) ((base)->TARGET_ROOT110_CLR) +#define CCM_TARGET_ROOT110_TOG_REG(base) ((base)->TARGET_ROOT110_TOG) +#define CCM_POST110_REG(base) ((base)->POST110) +#define CCM_POST_ROOT110_SET_REG(base) ((base)->POST_ROOT110_SET) +#define CCM_POST_ROOT110_CLR_REG(base) ((base)->POST_ROOT110_CLR) +#define CCM_POST_ROOT110_TOG_REG(base) ((base)->POST_ROOT110_TOG) +#define CCM_PRE110_REG(base) ((base)->PRE110) +#define CCM_PRE_ROOT110_SET_REG(base) ((base)->PRE_ROOT110_SET) +#define CCM_PRE_ROOT110_CLR_REG(base) ((base)->PRE_ROOT110_CLR) +#define CCM_PRE_ROOT110_TOG_REG(base) ((base)->PRE_ROOT110_TOG) +#define CCM_ACCESS_CTRL110_REG(base) ((base)->ACCESS_CTRL110) +#define CCM_ACCESS_CTRL110_ROOT_SET_REG(base) ((base)->ACCESS_CTRL110_ROOT_SET) +#define CCM_ACCESS_CTRL110_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL110_ROOT_CLR) +#define CCM_ACCESS_CTRL110_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL110_ROOT_TOG) +#define CCM_TARGET_ROOT111_REG(base) ((base)->TARGET_ROOT111) +#define CCM_TARGET_ROOT111_SET_REG(base) ((base)->TARGET_ROOT111_SET) +#define CCM_TARGET_ROOT111_CLR_REG(base) ((base)->TARGET_ROOT111_CLR) +#define CCM_TARGET_ROOT111_TOG_REG(base) ((base)->TARGET_ROOT111_TOG) +#define CCM_POST111_REG(base) ((base)->POST111) +#define CCM_POST_ROOT111_SET_REG(base) ((base)->POST_ROOT111_SET) +#define CCM_POST_ROOT111_CLR_REG(base) ((base)->POST_ROOT111_CLR) +#define CCM_POST_ROOT111_TOG_REG(base) ((base)->POST_ROOT111_TOG) +#define CCM_PRE111_REG(base) ((base)->PRE111) +#define CCM_PRE_ROOT111_SET_REG(base) ((base)->PRE_ROOT111_SET) +#define CCM_PRE_ROOT111_CLR_REG(base) ((base)->PRE_ROOT111_CLR) +#define CCM_PRE_ROOT111_TOG_REG(base) ((base)->PRE_ROOT111_TOG) +#define CCM_ACCESS_CTRL111_REG(base) ((base)->ACCESS_CTRL111) +#define CCM_ACCESS_CTRL111_ROOT_SET_REG(base) ((base)->ACCESS_CTRL111_ROOT_SET) +#define CCM_ACCESS_CTRL111_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL111_ROOT_CLR) +#define CCM_ACCESS_CTRL111_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL111_ROOT_TOG) +#define CCM_TARGET_ROOT112_REG(base) ((base)->TARGET_ROOT112) +#define CCM_TARGET_ROOT112_SET_REG(base) ((base)->TARGET_ROOT112_SET) +#define CCM_TARGET_ROOT112_CLR_REG(base) ((base)->TARGET_ROOT112_CLR) +#define CCM_TARGET_ROOT112_TOG_REG(base) ((base)->TARGET_ROOT112_TOG) +#define CCM_POST112_REG(base) ((base)->POST112) +#define CCM_POST_ROOT112_SET_REG(base) ((base)->POST_ROOT112_SET) +#define CCM_POST_ROOT112_CLR_REG(base) ((base)->POST_ROOT112_CLR) +#define CCM_POST_ROOT112_TOG_REG(base) ((base)->POST_ROOT112_TOG) +#define CCM_PRE112_REG(base) ((base)->PRE112) +#define CCM_PRE_ROOT112_SET_REG(base) ((base)->PRE_ROOT112_SET) +#define CCM_PRE_ROOT112_CLR_REG(base) ((base)->PRE_ROOT112_CLR) +#define CCM_PRE_ROOT112_TOG_REG(base) ((base)->PRE_ROOT112_TOG) +#define CCM_ACCESS_CTRL112_REG(base) ((base)->ACCESS_CTRL112) +#define CCM_ACCESS_CTRL112_ROOT_SET_REG(base) ((base)->ACCESS_CTRL112_ROOT_SET) +#define CCM_ACCESS_CTRL112_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL112_ROOT_CLR) +#define CCM_ACCESS_CTRL112_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL112_ROOT_TOG) +#define CCM_TARGET_ROOT113_REG(base) ((base)->TARGET_ROOT113) +#define CCM_TARGET_ROOT113_SET_REG(base) ((base)->TARGET_ROOT113_SET) +#define CCM_TARGET_ROOT113_CLR_REG(base) ((base)->TARGET_ROOT113_CLR) +#define CCM_TARGET_ROOT113_TOG_REG(base) ((base)->TARGET_ROOT113_TOG) +#define CCM_POST113_REG(base) ((base)->POST113) +#define CCM_POST_ROOT113_SET_REG(base) ((base)->POST_ROOT113_SET) +#define CCM_POST_ROOT113_CLR_REG(base) ((base)->POST_ROOT113_CLR) +#define CCM_POST_ROOT113_TOG_REG(base) ((base)->POST_ROOT113_TOG) +#define CCM_PRE113_REG(base) ((base)->PRE113) +#define CCM_PRE_ROOT113_SET_REG(base) ((base)->PRE_ROOT113_SET) +#define CCM_PRE_ROOT113_CLR_REG(base) ((base)->PRE_ROOT113_CLR) +#define CCM_PRE_ROOT113_TOG_REG(base) ((base)->PRE_ROOT113_TOG) +#define CCM_ACCESS_CTRL113_REG(base) ((base)->ACCESS_CTRL113) +#define CCM_ACCESS_CTRL113_ROOT_SET_REG(base) ((base)->ACCESS_CTRL113_ROOT_SET) +#define CCM_ACCESS_CTRL113_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL113_ROOT_CLR) +#define CCM_ACCESS_CTRL113_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL113_ROOT_TOG) +#define CCM_TARGET_ROOT114_REG(base) ((base)->TARGET_ROOT114) +#define CCM_TARGET_ROOT114_SET_REG(base) ((base)->TARGET_ROOT114_SET) +#define CCM_TARGET_ROOT114_CLR_REG(base) ((base)->TARGET_ROOT114_CLR) +#define CCM_TARGET_ROOT114_TOG_REG(base) ((base)->TARGET_ROOT114_TOG) +#define CCM_POST114_REG(base) ((base)->POST114) +#define CCM_POST_ROOT114_SET_REG(base) ((base)->POST_ROOT114_SET) +#define CCM_POST_ROOT114_CLR_REG(base) ((base)->POST_ROOT114_CLR) +#define CCM_POST_ROOT114_TOG_REG(base) ((base)->POST_ROOT114_TOG) +#define CCM_PRE114_REG(base) ((base)->PRE114) +#define CCM_PRE_ROOT114_SET_REG(base) ((base)->PRE_ROOT114_SET) +#define CCM_PRE_ROOT114_CLR_REG(base) ((base)->PRE_ROOT114_CLR) +#define CCM_PRE_ROOT114_TOG_REG(base) ((base)->PRE_ROOT114_TOG) +#define CCM_ACCESS_CTRL114_REG(base) ((base)->ACCESS_CTRL114) +#define CCM_ACCESS_CTRL114_ROOT_SET_REG(base) ((base)->ACCESS_CTRL114_ROOT_SET) +#define CCM_ACCESS_CTRL114_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL114_ROOT_CLR) +#define CCM_ACCESS_CTRL114_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL114_ROOT_TOG) +#define CCM_TARGET_ROOT115_REG(base) ((base)->TARGET_ROOT115) +#define CCM_TARGET_ROOT115_SET_REG(base) ((base)->TARGET_ROOT115_SET) +#define CCM_TARGET_ROOT115_CLR_REG(base) ((base)->TARGET_ROOT115_CLR) +#define CCM_TARGET_ROOT115_TOG_REG(base) ((base)->TARGET_ROOT115_TOG) +#define CCM_POST115_REG(base) ((base)->POST115) +#define CCM_POST_ROOT115_SET_REG(base) ((base)->POST_ROOT115_SET) +#define CCM_POST_ROOT115_CLR_REG(base) ((base)->POST_ROOT115_CLR) +#define CCM_POST_ROOT115_TOG_REG(base) ((base)->POST_ROOT115_TOG) +#define CCM_PRE115_REG(base) ((base)->PRE115) +#define CCM_PRE_ROOT115_SET_REG(base) ((base)->PRE_ROOT115_SET) +#define CCM_PRE_ROOT115_CLR_REG(base) ((base)->PRE_ROOT115_CLR) +#define CCM_PRE_ROOT115_TOG_REG(base) ((base)->PRE_ROOT115_TOG) +#define CCM_ACCESS_CTRL115_REG(base) ((base)->ACCESS_CTRL115) +#define CCM_ACCESS_CTRL115_ROOT_SET_REG(base) ((base)->ACCESS_CTRL115_ROOT_SET) +#define CCM_ACCESS_CTRL115_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL115_ROOT_CLR) +#define CCM_ACCESS_CTRL115_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL115_ROOT_TOG) +#define CCM_TARGET_ROOT116_REG(base) ((base)->TARGET_ROOT116) +#define CCM_TARGET_ROOT116_SET_REG(base) ((base)->TARGET_ROOT116_SET) +#define CCM_TARGET_ROOT116_CLR_REG(base) ((base)->TARGET_ROOT116_CLR) +#define CCM_TARGET_ROOT116_TOG_REG(base) ((base)->TARGET_ROOT116_TOG) +#define CCM_POST116_REG(base) ((base)->POST116) +#define CCM_POST_ROOT116_SET_REG(base) ((base)->POST_ROOT116_SET) +#define CCM_POST_ROOT116_CLR_REG(base) ((base)->POST_ROOT116_CLR) +#define CCM_POST_ROOT116_TOG_REG(base) ((base)->POST_ROOT116_TOG) +#define CCM_PRE116_REG(base) ((base)->PRE116) +#define CCM_PRE_ROOT116_SET_REG(base) ((base)->PRE_ROOT116_SET) +#define CCM_PRE_ROOT116_CLR_REG(base) ((base)->PRE_ROOT116_CLR) +#define CCM_PRE_ROOT116_TOG_REG(base) ((base)->PRE_ROOT116_TOG) +#define CCM_ACCESS_CTRL116_REG(base) ((base)->ACCESS_CTRL116) +#define CCM_ACCESS_CTRL116_ROOT_SET_REG(base) ((base)->ACCESS_CTRL116_ROOT_SET) +#define CCM_ACCESS_CTRL116_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL116_ROOT_CLR) +#define CCM_ACCESS_CTRL116_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL116_ROOT_TOG) +#define CCM_TARGET_ROOT117_REG(base) ((base)->TARGET_ROOT117) +#define CCM_TARGET_ROOT117_SET_REG(base) ((base)->TARGET_ROOT117_SET) +#define CCM_TARGET_ROOT117_CLR_REG(base) ((base)->TARGET_ROOT117_CLR) +#define CCM_TARGET_ROOT117_TOG_REG(base) ((base)->TARGET_ROOT117_TOG) +#define CCM_POST117_REG(base) ((base)->POST117) +#define CCM_POST_ROOT117_SET_REG(base) ((base)->POST_ROOT117_SET) +#define CCM_POST_ROOT117_CLR_REG(base) ((base)->POST_ROOT117_CLR) +#define CCM_POST_ROOT117_TOG_REG(base) ((base)->POST_ROOT117_TOG) +#define CCM_PRE117_REG(base) ((base)->PRE117) +#define CCM_PRE_ROOT117_SET_REG(base) ((base)->PRE_ROOT117_SET) +#define CCM_PRE_ROOT117_CLR_REG(base) ((base)->PRE_ROOT117_CLR) +#define CCM_PRE_ROOT117_TOG_REG(base) ((base)->PRE_ROOT117_TOG) +#define CCM_ACCESS_CTRL117_REG(base) ((base)->ACCESS_CTRL117) +#define CCM_ACCESS_CTRL117_ROOT_SET_REG(base) ((base)->ACCESS_CTRL117_ROOT_SET) +#define CCM_ACCESS_CTRL117_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL117_ROOT_CLR) +#define CCM_ACCESS_CTRL117_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL117_ROOT_TOG) +#define CCM_TARGET_ROOT118_REG(base) ((base)->TARGET_ROOT118) +#define CCM_TARGET_ROOT118_SET_REG(base) ((base)->TARGET_ROOT118_SET) +#define CCM_TARGET_ROOT118_CLR_REG(base) ((base)->TARGET_ROOT118_CLR) +#define CCM_TARGET_ROOT118_TOG_REG(base) ((base)->TARGET_ROOT118_TOG) +#define CCM_POST118_REG(base) ((base)->POST118) +#define CCM_POST_ROOT118_SET_REG(base) ((base)->POST_ROOT118_SET) +#define CCM_POST_ROOT118_CLR_REG(base) ((base)->POST_ROOT118_CLR) +#define CCM_POST_ROOT118_TOG_REG(base) ((base)->POST_ROOT118_TOG) +#define CCM_PRE118_REG(base) ((base)->PRE118) +#define CCM_PRE_ROOT118_SET_REG(base) ((base)->PRE_ROOT118_SET) +#define CCM_PRE_ROOT118_CLR_REG(base) ((base)->PRE_ROOT118_CLR) +#define CCM_PRE_ROOT118_TOG_REG(base) ((base)->PRE_ROOT118_TOG) +#define CCM_ACCESS_CTRL118_REG(base) ((base)->ACCESS_CTRL118) +#define CCM_ACCESS_CTRL118_ROOT_SET_REG(base) ((base)->ACCESS_CTRL118_ROOT_SET) +#define CCM_ACCESS_CTRL118_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL118_ROOT_CLR) +#define CCM_ACCESS_CTRL118_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL118_ROOT_TOG) +#define CCM_TARGET_ROOT119_REG(base) ((base)->TARGET_ROOT119) +#define CCM_TARGET_ROOT119_SET_REG(base) ((base)->TARGET_ROOT119_SET) +#define CCM_TARGET_ROOT119_CLR_REG(base) ((base)->TARGET_ROOT119_CLR) +#define CCM_TARGET_ROOT119_TOG_REG(base) ((base)->TARGET_ROOT119_TOG) +#define CCM_POST119_REG(base) ((base)->POST119) +#define CCM_POST_ROOT119_SET_REG(base) ((base)->POST_ROOT119_SET) +#define CCM_POST_ROOT119_CLR_REG(base) ((base)->POST_ROOT119_CLR) +#define CCM_POST_ROOT119_TOG_REG(base) ((base)->POST_ROOT119_TOG) +#define CCM_PRE119_REG(base) ((base)->PRE119) +#define CCM_PRE_ROOT119_SET_REG(base) ((base)->PRE_ROOT119_SET) +#define CCM_PRE_ROOT119_CLR_REG(base) ((base)->PRE_ROOT119_CLR) +#define CCM_PRE_ROOT119_TOG_REG(base) ((base)->PRE_ROOT119_TOG) +#define CCM_ACCESS_CTRL119_REG(base) ((base)->ACCESS_CTRL119) +#define CCM_ACCESS_CTRL119_ROOT_SET_REG(base) ((base)->ACCESS_CTRL119_ROOT_SET) +#define CCM_ACCESS_CTRL119_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL119_ROOT_CLR) +#define CCM_ACCESS_CTRL119_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL119_ROOT_TOG) +#define CCM_TARGET_ROOT120_REG(base) ((base)->TARGET_ROOT120) +#define CCM_TARGET_ROOT120_SET_REG(base) ((base)->TARGET_ROOT120_SET) +#define CCM_TARGET_ROOT120_CLR_REG(base) ((base)->TARGET_ROOT120_CLR) +#define CCM_TARGET_ROOT120_TOG_REG(base) ((base)->TARGET_ROOT120_TOG) +#define CCM_POST120_REG(base) ((base)->POST120) +#define CCM_POST_ROOT120_SET_REG(base) ((base)->POST_ROOT120_SET) +#define CCM_POST_ROOT120_CLR_REG(base) ((base)->POST_ROOT120_CLR) +#define CCM_POST_ROOT120_TOG_REG(base) ((base)->POST_ROOT120_TOG) +#define CCM_PRE120_REG(base) ((base)->PRE120) +#define CCM_PRE_ROOT120_SET_REG(base) ((base)->PRE_ROOT120_SET) +#define CCM_PRE_ROOT120_CLR_REG(base) ((base)->PRE_ROOT120_CLR) +#define CCM_PRE_ROOT120_TOG_REG(base) ((base)->PRE_ROOT120_TOG) +#define CCM_ACCESS_CTRL120_REG(base) ((base)->ACCESS_CTRL120) +#define CCM_ACCESS_CTRL120_ROOT_SET_REG(base) ((base)->ACCESS_CTRL120_ROOT_SET) +#define CCM_ACCESS_CTRL120_ROOT_CLR_REG(base) ((base)->ACCESS_CTRL120_ROOT_CLR) +#define CCM_ACCESS_CTRL120_ROOT_TOG_REG(base) ((base)->ACCESS_CTRL120_ROOT_TOG) + +/*! + * @} + */ /* end of group CCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define CCM_GPR0_GP0_MASK 0xFFFFFFFFu +#define CCM_GPR0_GP0_SHIFT 0 +#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_GP0_SHIFT))&CCM_GPR0_GP0_MASK) +/* GPR0_SET Bit Fields */ +#define CCM_GPR0_SET_GP0_MASK 0xFFFFFFFFu +#define CCM_GPR0_SET_GP0_SHIFT 0 +#define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_SET_GP0_SHIFT))&CCM_GPR0_SET_GP0_MASK) +/* GPR0_CLR Bit Fields */ +#define CCM_GPR0_CLR_GP0_MASK 0xFFFFFFFFu +#define CCM_GPR0_CLR_GP0_SHIFT 0 +#define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_CLR_GP0_SHIFT))&CCM_GPR0_CLR_GP0_MASK) +/* GPR0_TOG Bit Fields */ +#define CCM_GPR0_TOG_GP0_MASK 0xFFFFFFFFu +#define CCM_GPR0_TOG_GP0_SHIFT 0 +#define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x))<<CCM_GPR0_TOG_GP0_SHIFT))&CCM_GPR0_TOG_GP0_MASK) +/* PLL_CTRL0 Bit Fields */ +#define CCM_PLL_CTRL0_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL0_CG_SHIFT 0 +#define CCM_PLL_CTRL0_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_CG_SHIFT))&CCM_PLL_CTRL0_CG_MASK) +/* PLL_CTRL0_SET Bit Fields */ +#define CCM_PLL_CTRL0_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL0_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL0_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_SET_CG_SHIFT))&CCM_PLL_CTRL0_SET_CG_MASK) +/* PLL_CTRL0_CLR Bit Fields */ +#define CCM_PLL_CTRL0_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL0_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL0_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_CLR_CG_SHIFT))&CCM_PLL_CTRL0_CLR_CG_MASK) +/* PLL_CTRL0_TOG Bit Fields */ +#define CCM_PLL_CTRL0_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL0_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL0_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL0_TOG_CG_SHIFT))&CCM_PLL_CTRL0_TOG_CG_MASK) +/* PLL_CTRL1 Bit Fields */ +#define CCM_PLL_CTRL1_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL1_CG_SHIFT 0 +#define CCM_PLL_CTRL1_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_CG_SHIFT))&CCM_PLL_CTRL1_CG_MASK) +/* PLL_CTRL1_SET Bit Fields */ +#define CCM_PLL_CTRL1_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL1_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL1_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_SET_CG_SHIFT))&CCM_PLL_CTRL1_SET_CG_MASK) +/* PLL_CTRL1_CLR Bit Fields */ +#define CCM_PLL_CTRL1_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL1_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL1_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_CLR_CG_SHIFT))&CCM_PLL_CTRL1_CLR_CG_MASK) +/* PLL_CTRL1_TOG Bit Fields */ +#define CCM_PLL_CTRL1_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL1_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL1_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL1_TOG_CG_SHIFT))&CCM_PLL_CTRL1_TOG_CG_MASK) +/* PLL_CTRL2 Bit Fields */ +#define CCM_PLL_CTRL2_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL2_CG_SHIFT 0 +#define CCM_PLL_CTRL2_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_CG_SHIFT))&CCM_PLL_CTRL2_CG_MASK) +/* PLL_CTRL2_SET Bit Fields */ +#define CCM_PLL_CTRL2_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL2_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL2_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_SET_CG_SHIFT))&CCM_PLL_CTRL2_SET_CG_MASK) +/* PLL_CTRL2_CLR Bit Fields */ +#define CCM_PLL_CTRL2_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL2_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL2_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_CLR_CG_SHIFT))&CCM_PLL_CTRL2_CLR_CG_MASK) +/* PLL_CTRL2_TOG Bit Fields */ +#define CCM_PLL_CTRL2_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL2_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL2_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL2_TOG_CG_SHIFT))&CCM_PLL_CTRL2_TOG_CG_MASK) +/* PLL_CTRL3 Bit Fields */ +#define CCM_PLL_CTRL3_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL3_CG_SHIFT 0 +#define CCM_PLL_CTRL3_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_CG_SHIFT))&CCM_PLL_CTRL3_CG_MASK) +/* PLL_CTRL3_SET Bit Fields */ +#define CCM_PLL_CTRL3_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL3_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL3_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_SET_CG_SHIFT))&CCM_PLL_CTRL3_SET_CG_MASK) +/* PLL_CTRL3_CLR Bit Fields */ +#define CCM_PLL_CTRL3_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL3_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL3_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_CLR_CG_SHIFT))&CCM_PLL_CTRL3_CLR_CG_MASK) +/* PLL_CTRL3_TOG Bit Fields */ +#define CCM_PLL_CTRL3_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL3_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL3_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL3_TOG_CG_SHIFT))&CCM_PLL_CTRL3_TOG_CG_MASK) +/* PLL_CTRL4 Bit Fields */ +#define CCM_PLL_CTRL4_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL4_CG_SHIFT 0 +#define CCM_PLL_CTRL4_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_CG_SHIFT))&CCM_PLL_CTRL4_CG_MASK) +/* PLL_CTRL4_SET Bit Fields */ +#define CCM_PLL_CTRL4_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL4_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL4_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_SET_CG_SHIFT))&CCM_PLL_CTRL4_SET_CG_MASK) +/* PLL_CTRL4_CLR Bit Fields */ +#define CCM_PLL_CTRL4_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL4_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL4_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_CLR_CG_SHIFT))&CCM_PLL_CTRL4_CLR_CG_MASK) +/* PLL_CTRL4_TOG Bit Fields */ +#define CCM_PLL_CTRL4_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL4_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL4_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL4_TOG_CG_SHIFT))&CCM_PLL_CTRL4_TOG_CG_MASK) +/* PLL_CTRL5 Bit Fields */ +#define CCM_PLL_CTRL5_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL5_CG_SHIFT 0 +#define CCM_PLL_CTRL5_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_CG_SHIFT))&CCM_PLL_CTRL5_CG_MASK) +/* PLL_CTRL5_SET Bit Fields */ +#define CCM_PLL_CTRL5_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL5_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL5_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_SET_CG_SHIFT))&CCM_PLL_CTRL5_SET_CG_MASK) +/* PLL_CTRL5_CLR Bit Fields */ +#define CCM_PLL_CTRL5_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL5_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL5_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_CLR_CG_SHIFT))&CCM_PLL_CTRL5_CLR_CG_MASK) +/* PLL_CTRL5_TOG Bit Fields */ +#define CCM_PLL_CTRL5_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL5_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL5_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL5_TOG_CG_SHIFT))&CCM_PLL_CTRL5_TOG_CG_MASK) +/* PLL_CTRL6 Bit Fields */ +#define CCM_PLL_CTRL6_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL6_CG_SHIFT 0 +#define CCM_PLL_CTRL6_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_CG_SHIFT))&CCM_PLL_CTRL6_CG_MASK) +/* PLL_CTRL6_SET Bit Fields */ +#define CCM_PLL_CTRL6_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL6_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL6_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_SET_CG_SHIFT))&CCM_PLL_CTRL6_SET_CG_MASK) +/* PLL_CTRL6_CLR Bit Fields */ +#define CCM_PLL_CTRL6_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL6_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL6_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_CLR_CG_SHIFT))&CCM_PLL_CTRL6_CLR_CG_MASK) +/* PLL_CTRL6_TOG Bit Fields */ +#define CCM_PLL_CTRL6_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL6_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL6_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL6_TOG_CG_SHIFT))&CCM_PLL_CTRL6_TOG_CG_MASK) +/* PLL_CTRL7 Bit Fields */ +#define CCM_PLL_CTRL7_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL7_CG_SHIFT 0 +#define CCM_PLL_CTRL7_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_CG_SHIFT))&CCM_PLL_CTRL7_CG_MASK) +/* PLL_CTRL7_SET Bit Fields */ +#define CCM_PLL_CTRL7_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL7_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL7_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_SET_CG_SHIFT))&CCM_PLL_CTRL7_SET_CG_MASK) +/* PLL_CTRL7_CLR Bit Fields */ +#define CCM_PLL_CTRL7_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL7_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL7_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_CLR_CG_SHIFT))&CCM_PLL_CTRL7_CLR_CG_MASK) +/* PLL_CTRL7_TOG Bit Fields */ +#define CCM_PLL_CTRL7_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL7_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL7_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL7_TOG_CG_SHIFT))&CCM_PLL_CTRL7_TOG_CG_MASK) +/* PLL_CTRL8 Bit Fields */ +#define CCM_PLL_CTRL8_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL8_CG_SHIFT 0 +#define CCM_PLL_CTRL8_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_CG_SHIFT))&CCM_PLL_CTRL8_CG_MASK) +/* PLL_CTRL8_SET Bit Fields */ +#define CCM_PLL_CTRL8_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL8_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL8_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_SET_CG_SHIFT))&CCM_PLL_CTRL8_SET_CG_MASK) +/* PLL_CTRL8_CLR Bit Fields */ +#define CCM_PLL_CTRL8_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL8_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL8_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_CLR_CG_SHIFT))&CCM_PLL_CTRL8_CLR_CG_MASK) +/* PLL_CTRL8_TOG Bit Fields */ +#define CCM_PLL_CTRL8_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL8_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL8_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL8_TOG_CG_SHIFT))&CCM_PLL_CTRL8_TOG_CG_MASK) +/* PLL_CTRL9 Bit Fields */ +#define CCM_PLL_CTRL9_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL9_CG_SHIFT 0 +#define CCM_PLL_CTRL9_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_CG_SHIFT))&CCM_PLL_CTRL9_CG_MASK) +/* PLL_CTRL9_SET Bit Fields */ +#define CCM_PLL_CTRL9_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL9_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL9_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_SET_CG_SHIFT))&CCM_PLL_CTRL9_SET_CG_MASK) +/* PLL_CTRL9_CLR Bit Fields */ +#define CCM_PLL_CTRL9_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL9_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL9_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_CLR_CG_SHIFT))&CCM_PLL_CTRL9_CLR_CG_MASK) +/* PLL_CTRL9_TOG Bit Fields */ +#define CCM_PLL_CTRL9_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL9_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL9_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL9_TOG_CG_SHIFT))&CCM_PLL_CTRL9_TOG_CG_MASK) +/* PLL_CTRL10 Bit Fields */ +#define CCM_PLL_CTRL10_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL10_CG_SHIFT 0 +#define CCM_PLL_CTRL10_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_CG_SHIFT))&CCM_PLL_CTRL10_CG_MASK) +/* PLL_CTRL10_SET Bit Fields */ +#define CCM_PLL_CTRL10_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL10_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL10_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_SET_CG_SHIFT))&CCM_PLL_CTRL10_SET_CG_MASK) +/* PLL_CTRL10_CLR Bit Fields */ +#define CCM_PLL_CTRL10_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL10_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL10_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_CLR_CG_SHIFT))&CCM_PLL_CTRL10_CLR_CG_MASK) +/* PLL_CTRL10_TOG Bit Fields */ +#define CCM_PLL_CTRL10_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL10_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL10_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL10_TOG_CG_SHIFT))&CCM_PLL_CTRL10_TOG_CG_MASK) +/* PLL_CTRL11 Bit Fields */ +#define CCM_PLL_CTRL11_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL11_CG_SHIFT 0 +#define CCM_PLL_CTRL11_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_CG_SHIFT))&CCM_PLL_CTRL11_CG_MASK) +/* PLL_CTRL11_SET Bit Fields */ +#define CCM_PLL_CTRL11_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL11_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL11_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_SET_CG_SHIFT))&CCM_PLL_CTRL11_SET_CG_MASK) +/* PLL_CTRL11_CLR Bit Fields */ +#define CCM_PLL_CTRL11_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL11_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL11_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_CLR_CG_SHIFT))&CCM_PLL_CTRL11_CLR_CG_MASK) +/* PLL_CTRL11_TOG Bit Fields */ +#define CCM_PLL_CTRL11_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL11_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL11_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL11_TOG_CG_SHIFT))&CCM_PLL_CTRL11_TOG_CG_MASK) +/* PLL_CTRL12 Bit Fields */ +#define CCM_PLL_CTRL12_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL12_CG_SHIFT 0 +#define CCM_PLL_CTRL12_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_CG_SHIFT))&CCM_PLL_CTRL12_CG_MASK) +/* PLL_CTRL12_SET Bit Fields */ +#define CCM_PLL_CTRL12_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL12_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL12_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_SET_CG_SHIFT))&CCM_PLL_CTRL12_SET_CG_MASK) +/* PLL_CTRL12_CLR Bit Fields */ +#define CCM_PLL_CTRL12_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL12_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL12_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_CLR_CG_SHIFT))&CCM_PLL_CTRL12_CLR_CG_MASK) +/* PLL_CTRL12_TOG Bit Fields */ +#define CCM_PLL_CTRL12_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL12_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL12_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL12_TOG_CG_SHIFT))&CCM_PLL_CTRL12_TOG_CG_MASK) +/* PLL_CTRL13 Bit Fields */ +#define CCM_PLL_CTRL13_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL13_CG_SHIFT 0 +#define CCM_PLL_CTRL13_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_CG_SHIFT))&CCM_PLL_CTRL13_CG_MASK) +/* PLL_CTRL13_SET Bit Fields */ +#define CCM_PLL_CTRL13_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL13_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL13_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_SET_CG_SHIFT))&CCM_PLL_CTRL13_SET_CG_MASK) +/* PLL_CTRL13_CLR Bit Fields */ +#define CCM_PLL_CTRL13_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL13_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL13_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_CLR_CG_SHIFT))&CCM_PLL_CTRL13_CLR_CG_MASK) +/* PLL_CTRL13_TOG Bit Fields */ +#define CCM_PLL_CTRL13_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL13_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL13_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL13_TOG_CG_SHIFT))&CCM_PLL_CTRL13_TOG_CG_MASK) +/* PLL_CTRL14 Bit Fields */ +#define CCM_PLL_CTRL14_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL14_CG_SHIFT 0 +#define CCM_PLL_CTRL14_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_CG_SHIFT))&CCM_PLL_CTRL14_CG_MASK) +/* PLL_CTRL14_SET Bit Fields */ +#define CCM_PLL_CTRL14_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL14_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL14_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_SET_CG_SHIFT))&CCM_PLL_CTRL14_SET_CG_MASK) +/* PLL_CTRL14_CLR Bit Fields */ +#define CCM_PLL_CTRL14_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL14_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL14_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_CLR_CG_SHIFT))&CCM_PLL_CTRL14_CLR_CG_MASK) +/* PLL_CTRL14_TOG Bit Fields */ +#define CCM_PLL_CTRL14_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL14_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL14_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL14_TOG_CG_SHIFT))&CCM_PLL_CTRL14_TOG_CG_MASK) +/* PLL_CTRL15 Bit Fields */ +#define CCM_PLL_CTRL15_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL15_CG_SHIFT 0 +#define CCM_PLL_CTRL15_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_CG_SHIFT))&CCM_PLL_CTRL15_CG_MASK) +/* PLL_CTRL15_SET Bit Fields */ +#define CCM_PLL_CTRL15_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL15_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL15_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_SET_CG_SHIFT))&CCM_PLL_CTRL15_SET_CG_MASK) +/* PLL_CTRL15_CLR Bit Fields */ +#define CCM_PLL_CTRL15_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL15_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL15_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_CLR_CG_SHIFT))&CCM_PLL_CTRL15_CLR_CG_MASK) +/* PLL_CTRL15_TOG Bit Fields */ +#define CCM_PLL_CTRL15_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL15_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL15_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL15_TOG_CG_SHIFT))&CCM_PLL_CTRL15_TOG_CG_MASK) +/* PLL_CTRL16 Bit Fields */ +#define CCM_PLL_CTRL16_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL16_CG_SHIFT 0 +#define CCM_PLL_CTRL16_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_CG_SHIFT))&CCM_PLL_CTRL16_CG_MASK) +/* PLL_CTRL16_SET Bit Fields */ +#define CCM_PLL_CTRL16_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL16_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL16_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_SET_CG_SHIFT))&CCM_PLL_CTRL16_SET_CG_MASK) +/* PLL_CTRL16_CLR Bit Fields */ +#define CCM_PLL_CTRL16_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL16_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL16_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_CLR_CG_SHIFT))&CCM_PLL_CTRL16_CLR_CG_MASK) +/* PLL_CTRL16_TOG Bit Fields */ +#define CCM_PLL_CTRL16_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL16_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL16_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL16_TOG_CG_SHIFT))&CCM_PLL_CTRL16_TOG_CG_MASK) +/* PLL_CTRL17 Bit Fields */ +#define CCM_PLL_CTRL17_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL17_CG_SHIFT 0 +#define CCM_PLL_CTRL17_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_CG_SHIFT))&CCM_PLL_CTRL17_CG_MASK) +/* PLL_CTRL17_SET Bit Fields */ +#define CCM_PLL_CTRL17_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL17_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL17_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_SET_CG_SHIFT))&CCM_PLL_CTRL17_SET_CG_MASK) +/* PLL_CTRL17_CLR Bit Fields */ +#define CCM_PLL_CTRL17_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL17_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL17_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_CLR_CG_SHIFT))&CCM_PLL_CTRL17_CLR_CG_MASK) +/* PLL_CTRL17_TOG Bit Fields */ +#define CCM_PLL_CTRL17_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL17_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL17_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL17_TOG_CG_SHIFT))&CCM_PLL_CTRL17_TOG_CG_MASK) +/* PLL_CTRL18 Bit Fields */ +#define CCM_PLL_CTRL18_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL18_CG_SHIFT 0 +#define CCM_PLL_CTRL18_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_CG_SHIFT))&CCM_PLL_CTRL18_CG_MASK) +/* PLL_CTRL18_SET Bit Fields */ +#define CCM_PLL_CTRL18_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL18_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL18_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_SET_CG_SHIFT))&CCM_PLL_CTRL18_SET_CG_MASK) +/* PLL_CTRL18_CLR Bit Fields */ +#define CCM_PLL_CTRL18_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL18_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL18_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_CLR_CG_SHIFT))&CCM_PLL_CTRL18_CLR_CG_MASK) +/* PLL_CTRL18_TOG Bit Fields */ +#define CCM_PLL_CTRL18_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL18_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL18_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL18_TOG_CG_SHIFT))&CCM_PLL_CTRL18_TOG_CG_MASK) +/* PLL_CTRL19 Bit Fields */ +#define CCM_PLL_CTRL19_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL19_CG_SHIFT 0 +#define CCM_PLL_CTRL19_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_CG_SHIFT))&CCM_PLL_CTRL19_CG_MASK) +/* PLL_CTRL19_SET Bit Fields */ +#define CCM_PLL_CTRL19_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL19_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL19_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_SET_CG_SHIFT))&CCM_PLL_CTRL19_SET_CG_MASK) +/* PLL_CTRL19_CLR Bit Fields */ +#define CCM_PLL_CTRL19_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL19_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL19_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_CLR_CG_SHIFT))&CCM_PLL_CTRL19_CLR_CG_MASK) +/* PLL_CTRL19_TOG Bit Fields */ +#define CCM_PLL_CTRL19_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL19_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL19_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL19_TOG_CG_SHIFT))&CCM_PLL_CTRL19_TOG_CG_MASK) +/* PLL_CTRL20 Bit Fields */ +#define CCM_PLL_CTRL20_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL20_CG_SHIFT 0 +#define CCM_PLL_CTRL20_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_CG_SHIFT))&CCM_PLL_CTRL20_CG_MASK) +/* PLL_CTRL20_SET Bit Fields */ +#define CCM_PLL_CTRL20_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL20_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL20_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_SET_CG_SHIFT))&CCM_PLL_CTRL20_SET_CG_MASK) +/* PLL_CTRL20_CLR Bit Fields */ +#define CCM_PLL_CTRL20_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL20_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL20_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_CLR_CG_SHIFT))&CCM_PLL_CTRL20_CLR_CG_MASK) +/* PLL_CTRL20_TOG Bit Fields */ +#define CCM_PLL_CTRL20_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL20_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL20_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL20_TOG_CG_SHIFT))&CCM_PLL_CTRL20_TOG_CG_MASK) +/* PLL_CTRL21 Bit Fields */ +#define CCM_PLL_CTRL21_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL21_CG_SHIFT 0 +#define CCM_PLL_CTRL21_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_CG_SHIFT))&CCM_PLL_CTRL21_CG_MASK) +/* PLL_CTRL21_SET Bit Fields */ +#define CCM_PLL_CTRL21_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL21_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL21_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_SET_CG_SHIFT))&CCM_PLL_CTRL21_SET_CG_MASK) +/* PLL_CTRL21_CLR Bit Fields */ +#define CCM_PLL_CTRL21_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL21_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL21_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_CLR_CG_SHIFT))&CCM_PLL_CTRL21_CLR_CG_MASK) +/* PLL_CTRL21_TOG Bit Fields */ +#define CCM_PLL_CTRL21_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL21_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL21_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL21_TOG_CG_SHIFT))&CCM_PLL_CTRL21_TOG_CG_MASK) +/* PLL_CTRL22 Bit Fields */ +#define CCM_PLL_CTRL22_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL22_CG_SHIFT 0 +#define CCM_PLL_CTRL22_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_CG_SHIFT))&CCM_PLL_CTRL22_CG_MASK) +/* PLL_CTRL22_SET Bit Fields */ +#define CCM_PLL_CTRL22_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL22_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL22_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_SET_CG_SHIFT))&CCM_PLL_CTRL22_SET_CG_MASK) +/* PLL_CTRL22_CLR Bit Fields */ +#define CCM_PLL_CTRL22_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL22_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL22_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_CLR_CG_SHIFT))&CCM_PLL_CTRL22_CLR_CG_MASK) +/* PLL_CTRL22_TOG Bit Fields */ +#define CCM_PLL_CTRL22_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL22_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL22_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL22_TOG_CG_SHIFT))&CCM_PLL_CTRL22_TOG_CG_MASK) +/* PLL_CTRL23 Bit Fields */ +#define CCM_PLL_CTRL23_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL23_CG_SHIFT 0 +#define CCM_PLL_CTRL23_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_CG_SHIFT))&CCM_PLL_CTRL23_CG_MASK) +/* PLL_CTRL23_SET Bit Fields */ +#define CCM_PLL_CTRL23_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL23_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL23_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_SET_CG_SHIFT))&CCM_PLL_CTRL23_SET_CG_MASK) +/* PLL_CTRL23_CLR Bit Fields */ +#define CCM_PLL_CTRL23_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL23_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL23_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_CLR_CG_SHIFT))&CCM_PLL_CTRL23_CLR_CG_MASK) +/* PLL_CTRL23_TOG Bit Fields */ +#define CCM_PLL_CTRL23_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL23_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL23_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL23_TOG_CG_SHIFT))&CCM_PLL_CTRL23_TOG_CG_MASK) +/* PLL_CTRL24 Bit Fields */ +#define CCM_PLL_CTRL24_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL24_CG_SHIFT 0 +#define CCM_PLL_CTRL24_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_CG_SHIFT))&CCM_PLL_CTRL24_CG_MASK) +/* PLL_CTRL24_SET Bit Fields */ +#define CCM_PLL_CTRL24_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL24_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL24_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_SET_CG_SHIFT))&CCM_PLL_CTRL24_SET_CG_MASK) +/* PLL_CTRL24_CLR Bit Fields */ +#define CCM_PLL_CTRL24_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL24_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL24_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_CLR_CG_SHIFT))&CCM_PLL_CTRL24_CLR_CG_MASK) +/* PLL_CTRL24_TOG Bit Fields */ +#define CCM_PLL_CTRL24_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL24_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL24_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL24_TOG_CG_SHIFT))&CCM_PLL_CTRL24_TOG_CG_MASK) +/* PLL_CTRL25 Bit Fields */ +#define CCM_PLL_CTRL25_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL25_CG_SHIFT 0 +#define CCM_PLL_CTRL25_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_CG_SHIFT))&CCM_PLL_CTRL25_CG_MASK) +/* PLL_CTRL25_SET Bit Fields */ +#define CCM_PLL_CTRL25_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL25_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL25_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_SET_CG_SHIFT))&CCM_PLL_CTRL25_SET_CG_MASK) +/* PLL_CTRL25_CLR Bit Fields */ +#define CCM_PLL_CTRL25_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL25_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL25_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_CLR_CG_SHIFT))&CCM_PLL_CTRL25_CLR_CG_MASK) +/* PLL_CTRL25_TOG Bit Fields */ +#define CCM_PLL_CTRL25_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL25_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL25_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL25_TOG_CG_SHIFT))&CCM_PLL_CTRL25_TOG_CG_MASK) +/* PLL_CTRL26 Bit Fields */ +#define CCM_PLL_CTRL26_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL26_CG_SHIFT 0 +#define CCM_PLL_CTRL26_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_CG_SHIFT))&CCM_PLL_CTRL26_CG_MASK) +/* PLL_CTRL26_SET Bit Fields */ +#define CCM_PLL_CTRL26_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL26_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL26_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_SET_CG_SHIFT))&CCM_PLL_CTRL26_SET_CG_MASK) +/* PLL_CTRL26_CLR Bit Fields */ +#define CCM_PLL_CTRL26_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL26_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL26_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_CLR_CG_SHIFT))&CCM_PLL_CTRL26_CLR_CG_MASK) +/* PLL_CTRL26_TOG Bit Fields */ +#define CCM_PLL_CTRL26_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL26_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL26_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL26_TOG_CG_SHIFT))&CCM_PLL_CTRL26_TOG_CG_MASK) +/* PLL_CTRL27 Bit Fields */ +#define CCM_PLL_CTRL27_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL27_CG_SHIFT 0 +#define CCM_PLL_CTRL27_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_CG_SHIFT))&CCM_PLL_CTRL27_CG_MASK) +/* PLL_CTRL27_SET Bit Fields */ +#define CCM_PLL_CTRL27_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL27_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL27_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_SET_CG_SHIFT))&CCM_PLL_CTRL27_SET_CG_MASK) +/* PLL_CTRL27_CLR Bit Fields */ +#define CCM_PLL_CTRL27_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL27_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL27_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_CLR_CG_SHIFT))&CCM_PLL_CTRL27_CLR_CG_MASK) +/* PLL_CTRL27_TOG Bit Fields */ +#define CCM_PLL_CTRL27_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL27_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL27_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL27_TOG_CG_SHIFT))&CCM_PLL_CTRL27_TOG_CG_MASK) +/* PLL_CTRL28 Bit Fields */ +#define CCM_PLL_CTRL28_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL28_CG_SHIFT 0 +#define CCM_PLL_CTRL28_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_CG_SHIFT))&CCM_PLL_CTRL28_CG_MASK) +/* PLL_CTRL28_SET Bit Fields */ +#define CCM_PLL_CTRL28_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL28_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL28_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_SET_CG_SHIFT))&CCM_PLL_CTRL28_SET_CG_MASK) +/* PLL_CTRL28_CLR Bit Fields */ +#define CCM_PLL_CTRL28_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL28_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL28_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_CLR_CG_SHIFT))&CCM_PLL_CTRL28_CLR_CG_MASK) +/* PLL_CTRL28_TOG Bit Fields */ +#define CCM_PLL_CTRL28_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL28_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL28_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL28_TOG_CG_SHIFT))&CCM_PLL_CTRL28_TOG_CG_MASK) +/* PLL_CTRL29 Bit Fields */ +#define CCM_PLL_CTRL29_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL29_CG_SHIFT 0 +#define CCM_PLL_CTRL29_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_CG_SHIFT))&CCM_PLL_CTRL29_CG_MASK) +/* PLL_CTRL29_SET Bit Fields */ +#define CCM_PLL_CTRL29_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL29_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL29_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_SET_CG_SHIFT))&CCM_PLL_CTRL29_SET_CG_MASK) +/* PLL_CTRL29_CLR Bit Fields */ +#define CCM_PLL_CTRL29_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL29_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL29_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_CLR_CG_SHIFT))&CCM_PLL_CTRL29_CLR_CG_MASK) +/* PLL_CTRL29_TOG Bit Fields */ +#define CCM_PLL_CTRL29_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL29_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL29_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL29_TOG_CG_SHIFT))&CCM_PLL_CTRL29_TOG_CG_MASK) +/* PLL_CTRL30 Bit Fields */ +#define CCM_PLL_CTRL30_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL30_CG_SHIFT 0 +#define CCM_PLL_CTRL30_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_CG_SHIFT))&CCM_PLL_CTRL30_CG_MASK) +/* PLL_CTRL30_SET Bit Fields */ +#define CCM_PLL_CTRL30_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL30_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL30_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_SET_CG_SHIFT))&CCM_PLL_CTRL30_SET_CG_MASK) +/* PLL_CTRL30_CLR Bit Fields */ +#define CCM_PLL_CTRL30_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL30_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL30_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_CLR_CG_SHIFT))&CCM_PLL_CTRL30_CLR_CG_MASK) +/* PLL_CTRL30_TOG Bit Fields */ +#define CCM_PLL_CTRL30_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL30_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL30_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL30_TOG_CG_SHIFT))&CCM_PLL_CTRL30_TOG_CG_MASK) +/* PLL_CTRL31 Bit Fields */ +#define CCM_PLL_CTRL31_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL31_CG_SHIFT 0 +#define CCM_PLL_CTRL31_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_CG_SHIFT))&CCM_PLL_CTRL31_CG_MASK) +/* PLL_CTRL31_SET Bit Fields */ +#define CCM_PLL_CTRL31_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL31_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL31_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_SET_CG_SHIFT))&CCM_PLL_CTRL31_SET_CG_MASK) +/* PLL_CTRL31_CLR Bit Fields */ +#define CCM_PLL_CTRL31_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL31_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL31_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_CLR_CG_SHIFT))&CCM_PLL_CTRL31_CLR_CG_MASK) +/* PLL_CTRL31_TOG Bit Fields */ +#define CCM_PLL_CTRL31_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL31_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL31_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL31_TOG_CG_SHIFT))&CCM_PLL_CTRL31_TOG_CG_MASK) +/* PLL_CTRL32 Bit Fields */ +#define CCM_PLL_CTRL32_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL32_CG_SHIFT 0 +#define CCM_PLL_CTRL32_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_CG_SHIFT))&CCM_PLL_CTRL32_CG_MASK) +/* PLL_CTRL32_SET Bit Fields */ +#define CCM_PLL_CTRL32_SET_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL32_SET_CG_SHIFT 0 +#define CCM_PLL_CTRL32_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_SET_CG_SHIFT))&CCM_PLL_CTRL32_SET_CG_MASK) +/* PLL_CTRL32_CLR Bit Fields */ +#define CCM_PLL_CTRL32_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL32_CLR_CG_SHIFT 0 +#define CCM_PLL_CTRL32_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_CLR_CG_SHIFT))&CCM_PLL_CTRL32_CLR_CG_MASK) +/* PLL_CTRL32_TOG Bit Fields */ +#define CCM_PLL_CTRL32_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_PLL_CTRL32_TOG_CG_SHIFT 0 +#define CCM_PLL_CTRL32_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_PLL_CTRL32_TOG_CG_SHIFT))&CCM_PLL_CTRL32_TOG_CG_MASK) +/* CCGR0 Bit Fields */ +#define CCM_CCGR0_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR0_CG_SHIFT 0 +#define CCM_CCGR0_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CG_SHIFT))&CCM_CCGR0_CG_MASK) +/* CCGR0_SET Bit Fields */ +#define CCM_CCGR0_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR0_SET_CG_SHIFT 0 +#define CCM_CCGR0_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_SET_CG_SHIFT))&CCM_CCGR0_SET_CG_MASK) +/* CCGR0_CLR Bit Fields */ +#define CCM_CCGR0_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR0_CLR_CG_SHIFT 0 +#define CCM_CCGR0_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_CLR_CG_SHIFT))&CCM_CCGR0_CLR_CG_MASK) +/* CCGR0_TOG Bit Fields */ +#define CCM_CCGR0_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR0_TOG_CG_SHIFT 0 +#define CCM_CCGR0_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR0_TOG_CG_SHIFT))&CCM_CCGR0_TOG_CG_MASK) +/* CCGR1 Bit Fields */ +#define CCM_CCGR1_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR1_CG_SHIFT 0 +#define CCM_CCGR1_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CG_SHIFT))&CCM_CCGR1_CG_MASK) +/* CCGR1_SET Bit Fields */ +#define CCM_CCGR1_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR1_SET_CG_SHIFT 0 +#define CCM_CCGR1_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_SET_CG_SHIFT))&CCM_CCGR1_SET_CG_MASK) +/* CCGR1_CLR Bit Fields */ +#define CCM_CCGR1_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR1_CLR_CG_SHIFT 0 +#define CCM_CCGR1_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_CLR_CG_SHIFT))&CCM_CCGR1_CLR_CG_MASK) +/* CCGR1_TOG Bit Fields */ +#define CCM_CCGR1_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR1_TOG_CG_SHIFT 0 +#define CCM_CCGR1_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR1_TOG_CG_SHIFT))&CCM_CCGR1_TOG_CG_MASK) +/* CCGR2 Bit Fields */ +#define CCM_CCGR2_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR2_CG_SHIFT 0 +#define CCM_CCGR2_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CG_SHIFT))&CCM_CCGR2_CG_MASK) +/* CCGR2_SET Bit Fields */ +#define CCM_CCGR2_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR2_SET_CG_SHIFT 0 +#define CCM_CCGR2_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_SET_CG_SHIFT))&CCM_CCGR2_SET_CG_MASK) +/* CCGR2_CLR Bit Fields */ +#define CCM_CCGR2_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR2_CLR_CG_SHIFT 0 +#define CCM_CCGR2_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_CLR_CG_SHIFT))&CCM_CCGR2_CLR_CG_MASK) +/* CCGR2_TOG Bit Fields */ +#define CCM_CCGR2_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR2_TOG_CG_SHIFT 0 +#define CCM_CCGR2_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR2_TOG_CG_SHIFT))&CCM_CCGR2_TOG_CG_MASK) +/* CCGR3 Bit Fields */ +#define CCM_CCGR3_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR3_CG_SHIFT 0 +#define CCM_CCGR3_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CG_SHIFT))&CCM_CCGR3_CG_MASK) +/* CCGR3_SET Bit Fields */ +#define CCM_CCGR3_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR3_SET_CG_SHIFT 0 +#define CCM_CCGR3_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_SET_CG_SHIFT))&CCM_CCGR3_SET_CG_MASK) +/* CCGR3_CLR Bit Fields */ +#define CCM_CCGR3_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR3_CLR_CG_SHIFT 0 +#define CCM_CCGR3_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_CLR_CG_SHIFT))&CCM_CCGR3_CLR_CG_MASK) +/* CCGR3_TOG Bit Fields */ +#define CCM_CCGR3_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR3_TOG_CG_SHIFT 0 +#define CCM_CCGR3_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR3_TOG_CG_SHIFT))&CCM_CCGR3_TOG_CG_MASK) +/* CCGR4 Bit Fields */ +#define CCM_CCGR4_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR4_CG_SHIFT 0 +#define CCM_CCGR4_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CG_SHIFT))&CCM_CCGR4_CG_MASK) +/* CCGR4_SET Bit Fields */ +#define CCM_CCGR4_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR4_SET_CG_SHIFT 0 +#define CCM_CCGR4_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_SET_CG_SHIFT))&CCM_CCGR4_SET_CG_MASK) +/* CCGR4_CLR Bit Fields */ +#define CCM_CCGR4_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR4_CLR_CG_SHIFT 0 +#define CCM_CCGR4_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_CLR_CG_SHIFT))&CCM_CCGR4_CLR_CG_MASK) +/* CCGR4_TOG Bit Fields */ +#define CCM_CCGR4_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR4_TOG_CG_SHIFT 0 +#define CCM_CCGR4_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR4_TOG_CG_SHIFT))&CCM_CCGR4_TOG_CG_MASK) +/* CCGR5 Bit Fields */ +#define CCM_CCGR5_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR5_CG_SHIFT 0 +#define CCM_CCGR5_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CG_SHIFT))&CCM_CCGR5_CG_MASK) +/* CCGR5_SET Bit Fields */ +#define CCM_CCGR5_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR5_SET_CG_SHIFT 0 +#define CCM_CCGR5_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_SET_CG_SHIFT))&CCM_CCGR5_SET_CG_MASK) +/* CCGR5_CLR Bit Fields */ +#define CCM_CCGR5_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR5_CLR_CG_SHIFT 0 +#define CCM_CCGR5_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_CLR_CG_SHIFT))&CCM_CCGR5_CLR_CG_MASK) +/* CCGR5_TOG Bit Fields */ +#define CCM_CCGR5_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR5_TOG_CG_SHIFT 0 +#define CCM_CCGR5_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR5_TOG_CG_SHIFT))&CCM_CCGR5_TOG_CG_MASK) +/* CCGR6 Bit Fields */ +#define CCM_CCGR6_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR6_CG_SHIFT 0 +#define CCM_CCGR6_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CG_SHIFT))&CCM_CCGR6_CG_MASK) +/* CCGR6_SET Bit Fields */ +#define CCM_CCGR6_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR6_SET_CG_SHIFT 0 +#define CCM_CCGR6_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_SET_CG_SHIFT))&CCM_CCGR6_SET_CG_MASK) +/* CCGR6_CLR Bit Fields */ +#define CCM_CCGR6_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR6_CLR_CG_SHIFT 0 +#define CCM_CCGR6_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_CLR_CG_SHIFT))&CCM_CCGR6_CLR_CG_MASK) +/* CCGR6_TOG Bit Fields */ +#define CCM_CCGR6_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR6_TOG_CG_SHIFT 0 +#define CCM_CCGR6_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR6_TOG_CG_SHIFT))&CCM_CCGR6_TOG_CG_MASK) +/* CCGR7 Bit Fields */ +#define CCM_CCGR7_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR7_CG_SHIFT 0 +#define CCM_CCGR7_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CG_SHIFT))&CCM_CCGR7_CG_MASK) +/* CCGR7_SET Bit Fields */ +#define CCM_CCGR7_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR7_SET_CG_SHIFT 0 +#define CCM_CCGR7_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_SET_CG_SHIFT))&CCM_CCGR7_SET_CG_MASK) +/* CCGR7_CLR Bit Fields */ +#define CCM_CCGR7_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR7_CLR_CG_SHIFT 0 +#define CCM_CCGR7_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_CLR_CG_SHIFT))&CCM_CCGR7_CLR_CG_MASK) +/* CCGR7_TOG Bit Fields */ +#define CCM_CCGR7_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR7_TOG_CG_SHIFT 0 +#define CCM_CCGR7_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR7_TOG_CG_SHIFT))&CCM_CCGR7_TOG_CG_MASK) +/* CCGR8 Bit Fields */ +#define CCM_CCGR8_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR8_CG_SHIFT 0 +#define CCM_CCGR8_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CG_SHIFT))&CCM_CCGR8_CG_MASK) +/* CCGR8_SET Bit Fields */ +#define CCM_CCGR8_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR8_SET_CG_SHIFT 0 +#define CCM_CCGR8_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_SET_CG_SHIFT))&CCM_CCGR8_SET_CG_MASK) +/* CCGR8_CLR Bit Fields */ +#define CCM_CCGR8_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR8_CLR_CG_SHIFT 0 +#define CCM_CCGR8_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_CLR_CG_SHIFT))&CCM_CCGR8_CLR_CG_MASK) +/* CCGR8_TOG Bit Fields */ +#define CCM_CCGR8_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR8_TOG_CG_SHIFT 0 +#define CCM_CCGR8_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR8_TOG_CG_SHIFT))&CCM_CCGR8_TOG_CG_MASK) +/* CCGR9 Bit Fields */ +#define CCM_CCGR9_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR9_CG_SHIFT 0 +#define CCM_CCGR9_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CG_SHIFT))&CCM_CCGR9_CG_MASK) +/* CCGR9_SET Bit Fields */ +#define CCM_CCGR9_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR9_SET_CG_SHIFT 0 +#define CCM_CCGR9_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_SET_CG_SHIFT))&CCM_CCGR9_SET_CG_MASK) +/* CCGR9_CLR Bit Fields */ +#define CCM_CCGR9_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR9_CLR_CG_SHIFT 0 +#define CCM_CCGR9_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_CLR_CG_SHIFT))&CCM_CCGR9_CLR_CG_MASK) +/* CCGR9_TOG Bit Fields */ +#define CCM_CCGR9_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR9_TOG_CG_SHIFT 0 +#define CCM_CCGR9_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR9_TOG_CG_SHIFT))&CCM_CCGR9_TOG_CG_MASK) +/* CCGR10 Bit Fields */ +#define CCM_CCGR10_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR10_CG_SHIFT 0 +#define CCM_CCGR10_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CG_SHIFT))&CCM_CCGR10_CG_MASK) +/* CCGR10_SET Bit Fields */ +#define CCM_CCGR10_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR10_SET_CG_SHIFT 0 +#define CCM_CCGR10_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_SET_CG_SHIFT))&CCM_CCGR10_SET_CG_MASK) +/* CCGR10_CLR Bit Fields */ +#define CCM_CCGR10_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR10_CLR_CG_SHIFT 0 +#define CCM_CCGR10_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_CLR_CG_SHIFT))&CCM_CCGR10_CLR_CG_MASK) +/* CCGR10_TOG Bit Fields */ +#define CCM_CCGR10_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR10_TOG_CG_SHIFT 0 +#define CCM_CCGR10_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR10_TOG_CG_SHIFT))&CCM_CCGR10_TOG_CG_MASK) +/* CCGR11 Bit Fields */ +#define CCM_CCGR11_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR11_CG_SHIFT 0 +#define CCM_CCGR11_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CG_SHIFT))&CCM_CCGR11_CG_MASK) +/* CCGR11_SET Bit Fields */ +#define CCM_CCGR11_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR11_SET_CG_SHIFT 0 +#define CCM_CCGR11_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_SET_CG_SHIFT))&CCM_CCGR11_SET_CG_MASK) +/* CCGR11_CLR Bit Fields */ +#define CCM_CCGR11_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR11_CLR_CG_SHIFT 0 +#define CCM_CCGR11_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_CLR_CG_SHIFT))&CCM_CCGR11_CLR_CG_MASK) +/* CCGR11_TOG Bit Fields */ +#define CCM_CCGR11_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR11_TOG_CG_SHIFT 0 +#define CCM_CCGR11_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR11_TOG_CG_SHIFT))&CCM_CCGR11_TOG_CG_MASK) +/* CCGR12 Bit Fields */ +#define CCM_CCGR12_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR12_CG_SHIFT 0 +#define CCM_CCGR12_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_CG_SHIFT))&CCM_CCGR12_CG_MASK) +/* CCGR12_SET Bit Fields */ +#define CCM_CCGR12_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR12_SET_CG_SHIFT 0 +#define CCM_CCGR12_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_SET_CG_SHIFT))&CCM_CCGR12_SET_CG_MASK) +/* CCGR12_CLR Bit Fields */ +#define CCM_CCGR12_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR12_CLR_CG_SHIFT 0 +#define CCM_CCGR12_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_CLR_CG_SHIFT))&CCM_CCGR12_CLR_CG_MASK) +/* CCGR12_TOG Bit Fields */ +#define CCM_CCGR12_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR12_TOG_CG_SHIFT 0 +#define CCM_CCGR12_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR12_TOG_CG_SHIFT))&CCM_CCGR12_TOG_CG_MASK) +/* CCGR13 Bit Fields */ +#define CCM_CCGR13_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR13_CG_SHIFT 0 +#define CCM_CCGR13_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_CG_SHIFT))&CCM_CCGR13_CG_MASK) +/* CCGR13_SET Bit Fields */ +#define CCM_CCGR13_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR13_SET_CG_SHIFT 0 +#define CCM_CCGR13_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_SET_CG_SHIFT))&CCM_CCGR13_SET_CG_MASK) +/* CCGR13_CLR Bit Fields */ +#define CCM_CCGR13_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR13_CLR_CG_SHIFT 0 +#define CCM_CCGR13_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_CLR_CG_SHIFT))&CCM_CCGR13_CLR_CG_MASK) +/* CCGR13_TOG Bit Fields */ +#define CCM_CCGR13_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR13_TOG_CG_SHIFT 0 +#define CCM_CCGR13_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR13_TOG_CG_SHIFT))&CCM_CCGR13_TOG_CG_MASK) +/* CCGR14 Bit Fields */ +#define CCM_CCGR14_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR14_CG_SHIFT 0 +#define CCM_CCGR14_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_CG_SHIFT))&CCM_CCGR14_CG_MASK) +/* CCGR14_SET Bit Fields */ +#define CCM_CCGR14_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR14_SET_CG_SHIFT 0 +#define CCM_CCGR14_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_SET_CG_SHIFT))&CCM_CCGR14_SET_CG_MASK) +/* CCGR14_CLR Bit Fields */ +#define CCM_CCGR14_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR14_CLR_CG_SHIFT 0 +#define CCM_CCGR14_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_CLR_CG_SHIFT))&CCM_CCGR14_CLR_CG_MASK) +/* CCGR14_TOG Bit Fields */ +#define CCM_CCGR14_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR14_TOG_CG_SHIFT 0 +#define CCM_CCGR14_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR14_TOG_CG_SHIFT))&CCM_CCGR14_TOG_CG_MASK) +/* CCGR15 Bit Fields */ +#define CCM_CCGR15_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR15_CG_SHIFT 0 +#define CCM_CCGR15_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_CG_SHIFT))&CCM_CCGR15_CG_MASK) +/* CCGR15_SET Bit Fields */ +#define CCM_CCGR15_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR15_SET_CG_SHIFT 0 +#define CCM_CCGR15_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_SET_CG_SHIFT))&CCM_CCGR15_SET_CG_MASK) +/* CCGR15_CLR Bit Fields */ +#define CCM_CCGR15_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR15_CLR_CG_SHIFT 0 +#define CCM_CCGR15_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_CLR_CG_SHIFT))&CCM_CCGR15_CLR_CG_MASK) +/* CCGR15_TOG Bit Fields */ +#define CCM_CCGR15_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR15_TOG_CG_SHIFT 0 +#define CCM_CCGR15_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR15_TOG_CG_SHIFT))&CCM_CCGR15_TOG_CG_MASK) +/* CCGR16 Bit Fields */ +#define CCM_CCGR16_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR16_CG_SHIFT 0 +#define CCM_CCGR16_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_CG_SHIFT))&CCM_CCGR16_CG_MASK) +/* CCGR16_SET Bit Fields */ +#define CCM_CCGR16_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR16_SET_CG_SHIFT 0 +#define CCM_CCGR16_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_SET_CG_SHIFT))&CCM_CCGR16_SET_CG_MASK) +/* CCGR16_CLR Bit Fields */ +#define CCM_CCGR16_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR16_CLR_CG_SHIFT 0 +#define CCM_CCGR16_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_CLR_CG_SHIFT))&CCM_CCGR16_CLR_CG_MASK) +/* CCGR16_TOG Bit Fields */ +#define CCM_CCGR16_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR16_TOG_CG_SHIFT 0 +#define CCM_CCGR16_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR16_TOG_CG_SHIFT))&CCM_CCGR16_TOG_CG_MASK) +/* CCGR17 Bit Fields */ +#define CCM_CCGR17_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR17_CG_SHIFT 0 +#define CCM_CCGR17_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_CG_SHIFT))&CCM_CCGR17_CG_MASK) +/* CCGR17_SET Bit Fields */ +#define CCM_CCGR17_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR17_SET_CG_SHIFT 0 +#define CCM_CCGR17_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_SET_CG_SHIFT))&CCM_CCGR17_SET_CG_MASK) +/* CCGR17_CLR Bit Fields */ +#define CCM_CCGR17_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR17_CLR_CG_SHIFT 0 +#define CCM_CCGR17_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_CLR_CG_SHIFT))&CCM_CCGR17_CLR_CG_MASK) +/* CCGR17_TOG Bit Fields */ +#define CCM_CCGR17_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR17_TOG_CG_SHIFT 0 +#define CCM_CCGR17_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR17_TOG_CG_SHIFT))&CCM_CCGR17_TOG_CG_MASK) +/* CCGR18 Bit Fields */ +#define CCM_CCGR18_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR18_CG_SHIFT 0 +#define CCM_CCGR18_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_CG_SHIFT))&CCM_CCGR18_CG_MASK) +/* CCGR18_SET Bit Fields */ +#define CCM_CCGR18_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR18_SET_CG_SHIFT 0 +#define CCM_CCGR18_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_SET_CG_SHIFT))&CCM_CCGR18_SET_CG_MASK) +/* CCGR18_CLR Bit Fields */ +#define CCM_CCGR18_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR18_CLR_CG_SHIFT 0 +#define CCM_CCGR18_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_CLR_CG_SHIFT))&CCM_CCGR18_CLR_CG_MASK) +/* CCGR18_TOG Bit Fields */ +#define CCM_CCGR18_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR18_TOG_CG_SHIFT 0 +#define CCM_CCGR18_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR18_TOG_CG_SHIFT))&CCM_CCGR18_TOG_CG_MASK) +/* CCGR19 Bit Fields */ +#define CCM_CCGR19_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR19_CG_SHIFT 0 +#define CCM_CCGR19_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_CG_SHIFT))&CCM_CCGR19_CG_MASK) +/* CCGR19_SET Bit Fields */ +#define CCM_CCGR19_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR19_SET_CG_SHIFT 0 +#define CCM_CCGR19_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_SET_CG_SHIFT))&CCM_CCGR19_SET_CG_MASK) +/* CCGR19_CLR Bit Fields */ +#define CCM_CCGR19_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR19_CLR_CG_SHIFT 0 +#define CCM_CCGR19_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_CLR_CG_SHIFT))&CCM_CCGR19_CLR_CG_MASK) +/* CCGR19_TOG Bit Fields */ +#define CCM_CCGR19_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR19_TOG_CG_SHIFT 0 +#define CCM_CCGR19_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR19_TOG_CG_SHIFT))&CCM_CCGR19_TOG_CG_MASK) +/* CCGR20 Bit Fields */ +#define CCM_CCGR20_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR20_CG_SHIFT 0 +#define CCM_CCGR20_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_CG_SHIFT))&CCM_CCGR20_CG_MASK) +/* CCGR20_SET Bit Fields */ +#define CCM_CCGR20_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR20_SET_CG_SHIFT 0 +#define CCM_CCGR20_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_SET_CG_SHIFT))&CCM_CCGR20_SET_CG_MASK) +/* CCGR20_CLR Bit Fields */ +#define CCM_CCGR20_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR20_CLR_CG_SHIFT 0 +#define CCM_CCGR20_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_CLR_CG_SHIFT))&CCM_CCGR20_CLR_CG_MASK) +/* CCGR20_TOG Bit Fields */ +#define CCM_CCGR20_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR20_TOG_CG_SHIFT 0 +#define CCM_CCGR20_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR20_TOG_CG_SHIFT))&CCM_CCGR20_TOG_CG_MASK) +/* CCGR21 Bit Fields */ +#define CCM_CCGR21_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR21_CG_SHIFT 0 +#define CCM_CCGR21_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_CG_SHIFT))&CCM_CCGR21_CG_MASK) +/* CCGR21_SET Bit Fields */ +#define CCM_CCGR21_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR21_SET_CG_SHIFT 0 +#define CCM_CCGR21_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_SET_CG_SHIFT))&CCM_CCGR21_SET_CG_MASK) +/* CCGR21_CLR Bit Fields */ +#define CCM_CCGR21_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR21_CLR_CG_SHIFT 0 +#define CCM_CCGR21_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_CLR_CG_SHIFT))&CCM_CCGR21_CLR_CG_MASK) +/* CCGR21_TOG Bit Fields */ +#define CCM_CCGR21_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR21_TOG_CG_SHIFT 0 +#define CCM_CCGR21_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR21_TOG_CG_SHIFT))&CCM_CCGR21_TOG_CG_MASK) +/* CCGR22 Bit Fields */ +#define CCM_CCGR22_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR22_CG_SHIFT 0 +#define CCM_CCGR22_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_CG_SHIFT))&CCM_CCGR22_CG_MASK) +/* CCGR22_SET Bit Fields */ +#define CCM_CCGR22_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR22_SET_CG_SHIFT 0 +#define CCM_CCGR22_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_SET_CG_SHIFT))&CCM_CCGR22_SET_CG_MASK) +/* CCGR22_CLR Bit Fields */ +#define CCM_CCGR22_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR22_CLR_CG_SHIFT 0 +#define CCM_CCGR22_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_CLR_CG_SHIFT))&CCM_CCGR22_CLR_CG_MASK) +/* CCGR22_TOG Bit Fields */ +#define CCM_CCGR22_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR22_TOG_CG_SHIFT 0 +#define CCM_CCGR22_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR22_TOG_CG_SHIFT))&CCM_CCGR22_TOG_CG_MASK) +/* CCGR23 Bit Fields */ +#define CCM_CCGR23_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR23_CG_SHIFT 0 +#define CCM_CCGR23_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_CG_SHIFT))&CCM_CCGR23_CG_MASK) +/* CCGR23_SET Bit Fields */ +#define CCM_CCGR23_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR23_SET_CG_SHIFT 0 +#define CCM_CCGR23_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_SET_CG_SHIFT))&CCM_CCGR23_SET_CG_MASK) +/* CCGR23_CLR Bit Fields */ +#define CCM_CCGR23_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR23_CLR_CG_SHIFT 0 +#define CCM_CCGR23_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_CLR_CG_SHIFT))&CCM_CCGR23_CLR_CG_MASK) +/* CCGR23_TOG Bit Fields */ +#define CCM_CCGR23_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR23_TOG_CG_SHIFT 0 +#define CCM_CCGR23_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR23_TOG_CG_SHIFT))&CCM_CCGR23_TOG_CG_MASK) +/* CCGR24 Bit Fields */ +#define CCM_CCGR24_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR24_CG_SHIFT 0 +#define CCM_CCGR24_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_CG_SHIFT))&CCM_CCGR24_CG_MASK) +/* CCGR24_SET Bit Fields */ +#define CCM_CCGR24_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR24_SET_CG_SHIFT 0 +#define CCM_CCGR24_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_SET_CG_SHIFT))&CCM_CCGR24_SET_CG_MASK) +/* CCGR24_CLR Bit Fields */ +#define CCM_CCGR24_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR24_CLR_CG_SHIFT 0 +#define CCM_CCGR24_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_CLR_CG_SHIFT))&CCM_CCGR24_CLR_CG_MASK) +/* CCGR24_TOG Bit Fields */ +#define CCM_CCGR24_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR24_TOG_CG_SHIFT 0 +#define CCM_CCGR24_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR24_TOG_CG_SHIFT))&CCM_CCGR24_TOG_CG_MASK) +/* CCGR25 Bit Fields */ +#define CCM_CCGR25_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR25_CG_SHIFT 0 +#define CCM_CCGR25_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_CG_SHIFT))&CCM_CCGR25_CG_MASK) +/* CCGR25_SET Bit Fields */ +#define CCM_CCGR25_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR25_SET_CG_SHIFT 0 +#define CCM_CCGR25_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_SET_CG_SHIFT))&CCM_CCGR25_SET_CG_MASK) +/* CCGR25_CLR Bit Fields */ +#define CCM_CCGR25_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR25_CLR_CG_SHIFT 0 +#define CCM_CCGR25_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_CLR_CG_SHIFT))&CCM_CCGR25_CLR_CG_MASK) +/* CCGR25_TOG Bit Fields */ +#define CCM_CCGR25_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR25_TOG_CG_SHIFT 0 +#define CCM_CCGR25_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR25_TOG_CG_SHIFT))&CCM_CCGR25_TOG_CG_MASK) +/* CCGR26 Bit Fields */ +#define CCM_CCGR26_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR26_CG_SHIFT 0 +#define CCM_CCGR26_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_CG_SHIFT))&CCM_CCGR26_CG_MASK) +/* CCGR26_SET Bit Fields */ +#define CCM_CCGR26_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR26_SET_CG_SHIFT 0 +#define CCM_CCGR26_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_SET_CG_SHIFT))&CCM_CCGR26_SET_CG_MASK) +/* CCGR26_CLR Bit Fields */ +#define CCM_CCGR26_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR26_CLR_CG_SHIFT 0 +#define CCM_CCGR26_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_CLR_CG_SHIFT))&CCM_CCGR26_CLR_CG_MASK) +/* CCGR26_TOG Bit Fields */ +#define CCM_CCGR26_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR26_TOG_CG_SHIFT 0 +#define CCM_CCGR26_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR26_TOG_CG_SHIFT))&CCM_CCGR26_TOG_CG_MASK) +/* CCGR27 Bit Fields */ +#define CCM_CCGR27_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR27_CG_SHIFT 0 +#define CCM_CCGR27_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_CG_SHIFT))&CCM_CCGR27_CG_MASK) +/* CCGR27_SET Bit Fields */ +#define CCM_CCGR27_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR27_SET_CG_SHIFT 0 +#define CCM_CCGR27_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_SET_CG_SHIFT))&CCM_CCGR27_SET_CG_MASK) +/* CCGR27_CLR Bit Fields */ +#define CCM_CCGR27_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR27_CLR_CG_SHIFT 0 +#define CCM_CCGR27_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_CLR_CG_SHIFT))&CCM_CCGR27_CLR_CG_MASK) +/* CCGR27_TOG Bit Fields */ +#define CCM_CCGR27_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR27_TOG_CG_SHIFT 0 +#define CCM_CCGR27_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR27_TOG_CG_SHIFT))&CCM_CCGR27_TOG_CG_MASK) +/* CCGR28 Bit Fields */ +#define CCM_CCGR28_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR28_CG_SHIFT 0 +#define CCM_CCGR28_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_CG_SHIFT))&CCM_CCGR28_CG_MASK) +/* CCGR28_SET Bit Fields */ +#define CCM_CCGR28_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR28_SET_CG_SHIFT 0 +#define CCM_CCGR28_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_SET_CG_SHIFT))&CCM_CCGR28_SET_CG_MASK) +/* CCGR28_CLR Bit Fields */ +#define CCM_CCGR28_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR28_CLR_CG_SHIFT 0 +#define CCM_CCGR28_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_CLR_CG_SHIFT))&CCM_CCGR28_CLR_CG_MASK) +/* CCGR28_TOG Bit Fields */ +#define CCM_CCGR28_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR28_TOG_CG_SHIFT 0 +#define CCM_CCGR28_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR28_TOG_CG_SHIFT))&CCM_CCGR28_TOG_CG_MASK) +/* CCGR29 Bit Fields */ +#define CCM_CCGR29_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR29_CG_SHIFT 0 +#define CCM_CCGR29_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_CG_SHIFT))&CCM_CCGR29_CG_MASK) +/* CCGR29_SET Bit Fields */ +#define CCM_CCGR29_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR29_SET_CG_SHIFT 0 +#define CCM_CCGR29_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_SET_CG_SHIFT))&CCM_CCGR29_SET_CG_MASK) +/* CCGR29_CLR Bit Fields */ +#define CCM_CCGR29_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR29_CLR_CG_SHIFT 0 +#define CCM_CCGR29_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_CLR_CG_SHIFT))&CCM_CCGR29_CLR_CG_MASK) +/* CCGR29_TOG Bit Fields */ +#define CCM_CCGR29_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR29_TOG_CG_SHIFT 0 +#define CCM_CCGR29_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR29_TOG_CG_SHIFT))&CCM_CCGR29_TOG_CG_MASK) +/* CCGR30 Bit Fields */ +#define CCM_CCGR30_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR30_CG_SHIFT 0 +#define CCM_CCGR30_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_CG_SHIFT))&CCM_CCGR30_CG_MASK) +/* CCGR30_SET Bit Fields */ +#define CCM_CCGR30_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR30_SET_CG_SHIFT 0 +#define CCM_CCGR30_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_SET_CG_SHIFT))&CCM_CCGR30_SET_CG_MASK) +/* CCGR30_CLR Bit Fields */ +#define CCM_CCGR30_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR30_CLR_CG_SHIFT 0 +#define CCM_CCGR30_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_CLR_CG_SHIFT))&CCM_CCGR30_CLR_CG_MASK) +/* CCGR30_TOG Bit Fields */ +#define CCM_CCGR30_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR30_TOG_CG_SHIFT 0 +#define CCM_CCGR30_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR30_TOG_CG_SHIFT))&CCM_CCGR30_TOG_CG_MASK) +/* CCGR31 Bit Fields */ +#define CCM_CCGR31_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR31_CG_SHIFT 0 +#define CCM_CCGR31_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_CG_SHIFT))&CCM_CCGR31_CG_MASK) +/* CCGR31_SET Bit Fields */ +#define CCM_CCGR31_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR31_SET_CG_SHIFT 0 +#define CCM_CCGR31_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_SET_CG_SHIFT))&CCM_CCGR31_SET_CG_MASK) +/* CCGR31_CLR Bit Fields */ +#define CCM_CCGR31_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR31_CLR_CG_SHIFT 0 +#define CCM_CCGR31_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_CLR_CG_SHIFT))&CCM_CCGR31_CLR_CG_MASK) +/* CCGR31_TOG Bit Fields */ +#define CCM_CCGR31_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR31_TOG_CG_SHIFT 0 +#define CCM_CCGR31_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR31_TOG_CG_SHIFT))&CCM_CCGR31_TOG_CG_MASK) +/* CCGR32 Bit Fields */ +#define CCM_CCGR32_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR32_CG_SHIFT 0 +#define CCM_CCGR32_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_CG_SHIFT))&CCM_CCGR32_CG_MASK) +/* CCGR32_SET Bit Fields */ +#define CCM_CCGR32_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR32_SET_CG_SHIFT 0 +#define CCM_CCGR32_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_SET_CG_SHIFT))&CCM_CCGR32_SET_CG_MASK) +/* CCGR32_CLR Bit Fields */ +#define CCM_CCGR32_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR32_CLR_CG_SHIFT 0 +#define CCM_CCGR32_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_CLR_CG_SHIFT))&CCM_CCGR32_CLR_CG_MASK) +/* CCGR32_TOG Bit Fields */ +#define CCM_CCGR32_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR32_TOG_CG_SHIFT 0 +#define CCM_CCGR32_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR32_TOG_CG_SHIFT))&CCM_CCGR32_TOG_CG_MASK) +/* CCGR33 Bit Fields */ +#define CCM_CCGR33_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR33_CG_SHIFT 0 +#define CCM_CCGR33_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_CG_SHIFT))&CCM_CCGR33_CG_MASK) +/* CCGR33_SET Bit Fields */ +#define CCM_CCGR33_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR33_SET_CG_SHIFT 0 +#define CCM_CCGR33_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_SET_CG_SHIFT))&CCM_CCGR33_SET_CG_MASK) +/* CCGR33_CLR Bit Fields */ +#define CCM_CCGR33_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR33_CLR_CG_SHIFT 0 +#define CCM_CCGR33_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_CLR_CG_SHIFT))&CCM_CCGR33_CLR_CG_MASK) +/* CCGR33_TOG Bit Fields */ +#define CCM_CCGR33_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR33_TOG_CG_SHIFT 0 +#define CCM_CCGR33_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR33_TOG_CG_SHIFT))&CCM_CCGR33_TOG_CG_MASK) +/* CCGR34 Bit Fields */ +#define CCM_CCGR34_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR34_CG_SHIFT 0 +#define CCM_CCGR34_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_CG_SHIFT))&CCM_CCGR34_CG_MASK) +/* CCGR34_SET Bit Fields */ +#define CCM_CCGR34_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR34_SET_CG_SHIFT 0 +#define CCM_CCGR34_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_SET_CG_SHIFT))&CCM_CCGR34_SET_CG_MASK) +/* CCGR34_CLR Bit Fields */ +#define CCM_CCGR34_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR34_CLR_CG_SHIFT 0 +#define CCM_CCGR34_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_CLR_CG_SHIFT))&CCM_CCGR34_CLR_CG_MASK) +/* CCGR34_TOG Bit Fields */ +#define CCM_CCGR34_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR34_TOG_CG_SHIFT 0 +#define CCM_CCGR34_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR34_TOG_CG_SHIFT))&CCM_CCGR34_TOG_CG_MASK) +/* CCGR35 Bit Fields */ +#define CCM_CCGR35_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR35_CG_SHIFT 0 +#define CCM_CCGR35_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_CG_SHIFT))&CCM_CCGR35_CG_MASK) +/* CCGR35_SET Bit Fields */ +#define CCM_CCGR35_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR35_SET_CG_SHIFT 0 +#define CCM_CCGR35_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_SET_CG_SHIFT))&CCM_CCGR35_SET_CG_MASK) +/* CCGR35_CLR Bit Fields */ +#define CCM_CCGR35_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR35_CLR_CG_SHIFT 0 +#define CCM_CCGR35_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_CLR_CG_SHIFT))&CCM_CCGR35_CLR_CG_MASK) +/* CCGR35_TOG Bit Fields */ +#define CCM_CCGR35_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR35_TOG_CG_SHIFT 0 +#define CCM_CCGR35_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR35_TOG_CG_SHIFT))&CCM_CCGR35_TOG_CG_MASK) +/* CCGR36 Bit Fields */ +#define CCM_CCGR36_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR36_CG_SHIFT 0 +#define CCM_CCGR36_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_CG_SHIFT))&CCM_CCGR36_CG_MASK) +/* CCGR36_SET Bit Fields */ +#define CCM_CCGR36_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR36_SET_CG_SHIFT 0 +#define CCM_CCGR36_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_SET_CG_SHIFT))&CCM_CCGR36_SET_CG_MASK) +/* CCGR36_CLR Bit Fields */ +#define CCM_CCGR36_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR36_CLR_CG_SHIFT 0 +#define CCM_CCGR36_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_CLR_CG_SHIFT))&CCM_CCGR36_CLR_CG_MASK) +/* CCGR36_TOG Bit Fields */ +#define CCM_CCGR36_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR36_TOG_CG_SHIFT 0 +#define CCM_CCGR36_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR36_TOG_CG_SHIFT))&CCM_CCGR36_TOG_CG_MASK) +/* CCGR37 Bit Fields */ +#define CCM_CCGR37_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR37_CG_SHIFT 0 +#define CCM_CCGR37_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_CG_SHIFT))&CCM_CCGR37_CG_MASK) +/* CCGR37_SET Bit Fields */ +#define CCM_CCGR37_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR37_SET_CG_SHIFT 0 +#define CCM_CCGR37_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_SET_CG_SHIFT))&CCM_CCGR37_SET_CG_MASK) +/* CCGR37_CLR Bit Fields */ +#define CCM_CCGR37_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR37_CLR_CG_SHIFT 0 +#define CCM_CCGR37_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_CLR_CG_SHIFT))&CCM_CCGR37_CLR_CG_MASK) +/* CCGR37_TOG Bit Fields */ +#define CCM_CCGR37_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR37_TOG_CG_SHIFT 0 +#define CCM_CCGR37_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR37_TOG_CG_SHIFT))&CCM_CCGR37_TOG_CG_MASK) +/* CCGR38 Bit Fields */ +#define CCM_CCGR38_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR38_CG_SHIFT 0 +#define CCM_CCGR38_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_CG_SHIFT))&CCM_CCGR38_CG_MASK) +/* CCGR38_SET Bit Fields */ +#define CCM_CCGR38_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR38_SET_CG_SHIFT 0 +#define CCM_CCGR38_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_SET_CG_SHIFT))&CCM_CCGR38_SET_CG_MASK) +/* CCGR38_CLR Bit Fields */ +#define CCM_CCGR38_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR38_CLR_CG_SHIFT 0 +#define CCM_CCGR38_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_CLR_CG_SHIFT))&CCM_CCGR38_CLR_CG_MASK) +/* CCGR38_TOG Bit Fields */ +#define CCM_CCGR38_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR38_TOG_CG_SHIFT 0 +#define CCM_CCGR38_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR38_TOG_CG_SHIFT))&CCM_CCGR38_TOG_CG_MASK) +/* CCGR39 Bit Fields */ +#define CCM_CCGR39_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR39_CG_SHIFT 0 +#define CCM_CCGR39_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_CG_SHIFT))&CCM_CCGR39_CG_MASK) +/* CCGR39_SET Bit Fields */ +#define CCM_CCGR39_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR39_SET_CG_SHIFT 0 +#define CCM_CCGR39_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_SET_CG_SHIFT))&CCM_CCGR39_SET_CG_MASK) +/* CCGR39_CLR Bit Fields */ +#define CCM_CCGR39_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR39_CLR_CG_SHIFT 0 +#define CCM_CCGR39_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_CLR_CG_SHIFT))&CCM_CCGR39_CLR_CG_MASK) +/* CCGR39_TOG Bit Fields */ +#define CCM_CCGR39_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR39_TOG_CG_SHIFT 0 +#define CCM_CCGR39_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR39_TOG_CG_SHIFT))&CCM_CCGR39_TOG_CG_MASK) +/* CCGR40 Bit Fields */ +#define CCM_CCGR40_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR40_CG_SHIFT 0 +#define CCM_CCGR40_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_CG_SHIFT))&CCM_CCGR40_CG_MASK) +/* CCGR40_SET Bit Fields */ +#define CCM_CCGR40_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR40_SET_CG_SHIFT 0 +#define CCM_CCGR40_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_SET_CG_SHIFT))&CCM_CCGR40_SET_CG_MASK) +/* CCGR40_CLR Bit Fields */ +#define CCM_CCGR40_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR40_CLR_CG_SHIFT 0 +#define CCM_CCGR40_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_CLR_CG_SHIFT))&CCM_CCGR40_CLR_CG_MASK) +/* CCGR40_TOG Bit Fields */ +#define CCM_CCGR40_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR40_TOG_CG_SHIFT 0 +#define CCM_CCGR40_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR40_TOG_CG_SHIFT))&CCM_CCGR40_TOG_CG_MASK) +/* CCGR41 Bit Fields */ +#define CCM_CCGR41_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR41_CG_SHIFT 0 +#define CCM_CCGR41_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_CG_SHIFT))&CCM_CCGR41_CG_MASK) +/* CCGR41_SET Bit Fields */ +#define CCM_CCGR41_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR41_SET_CG_SHIFT 0 +#define CCM_CCGR41_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_SET_CG_SHIFT))&CCM_CCGR41_SET_CG_MASK) +/* CCGR41_CLR Bit Fields */ +#define CCM_CCGR41_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR41_CLR_CG_SHIFT 0 +#define CCM_CCGR41_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_CLR_CG_SHIFT))&CCM_CCGR41_CLR_CG_MASK) +/* CCGR41_TOG Bit Fields */ +#define CCM_CCGR41_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR41_TOG_CG_SHIFT 0 +#define CCM_CCGR41_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR41_TOG_CG_SHIFT))&CCM_CCGR41_TOG_CG_MASK) +/* CCGR42 Bit Fields */ +#define CCM_CCGR42_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR42_CG_SHIFT 0 +#define CCM_CCGR42_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_CG_SHIFT))&CCM_CCGR42_CG_MASK) +/* CCGR42_SET Bit Fields */ +#define CCM_CCGR42_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR42_SET_CG_SHIFT 0 +#define CCM_CCGR42_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_SET_CG_SHIFT))&CCM_CCGR42_SET_CG_MASK) +/* CCGR42_CLR Bit Fields */ +#define CCM_CCGR42_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR42_CLR_CG_SHIFT 0 +#define CCM_CCGR42_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_CLR_CG_SHIFT))&CCM_CCGR42_CLR_CG_MASK) +/* CCGR42_TOG Bit Fields */ +#define CCM_CCGR42_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR42_TOG_CG_SHIFT 0 +#define CCM_CCGR42_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR42_TOG_CG_SHIFT))&CCM_CCGR42_TOG_CG_MASK) +/* CCGR43 Bit Fields */ +#define CCM_CCGR43_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR43_CG_SHIFT 0 +#define CCM_CCGR43_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_CG_SHIFT))&CCM_CCGR43_CG_MASK) +/* CCGR43_SET Bit Fields */ +#define CCM_CCGR43_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR43_SET_CG_SHIFT 0 +#define CCM_CCGR43_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_SET_CG_SHIFT))&CCM_CCGR43_SET_CG_MASK) +/* CCGR43_CLR Bit Fields */ +#define CCM_CCGR43_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR43_CLR_CG_SHIFT 0 +#define CCM_CCGR43_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_CLR_CG_SHIFT))&CCM_CCGR43_CLR_CG_MASK) +/* CCGR43_TOG Bit Fields */ +#define CCM_CCGR43_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR43_TOG_CG_SHIFT 0 +#define CCM_CCGR43_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR43_TOG_CG_SHIFT))&CCM_CCGR43_TOG_CG_MASK) +/* CCGR44 Bit Fields */ +#define CCM_CCGR44_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR44_CG_SHIFT 0 +#define CCM_CCGR44_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_CG_SHIFT))&CCM_CCGR44_CG_MASK) +/* CCGR44_SET Bit Fields */ +#define CCM_CCGR44_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR44_SET_CG_SHIFT 0 +#define CCM_CCGR44_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_SET_CG_SHIFT))&CCM_CCGR44_SET_CG_MASK) +/* CCGR44_CLR Bit Fields */ +#define CCM_CCGR44_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR44_CLR_CG_SHIFT 0 +#define CCM_CCGR44_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_CLR_CG_SHIFT))&CCM_CCGR44_CLR_CG_MASK) +/* CCGR44_TOG Bit Fields */ +#define CCM_CCGR44_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR44_TOG_CG_SHIFT 0 +#define CCM_CCGR44_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR44_TOG_CG_SHIFT))&CCM_CCGR44_TOG_CG_MASK) +/* CCGR45 Bit Fields */ +#define CCM_CCGR45_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR45_CG_SHIFT 0 +#define CCM_CCGR45_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_CG_SHIFT))&CCM_CCGR45_CG_MASK) +/* CCGR45_SET Bit Fields */ +#define CCM_CCGR45_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR45_SET_CG_SHIFT 0 +#define CCM_CCGR45_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_SET_CG_SHIFT))&CCM_CCGR45_SET_CG_MASK) +/* CCGR45_CLR Bit Fields */ +#define CCM_CCGR45_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR45_CLR_CG_SHIFT 0 +#define CCM_CCGR45_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_CLR_CG_SHIFT))&CCM_CCGR45_CLR_CG_MASK) +/* CCGR45_TOG Bit Fields */ +#define CCM_CCGR45_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR45_TOG_CG_SHIFT 0 +#define CCM_CCGR45_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR45_TOG_CG_SHIFT))&CCM_CCGR45_TOG_CG_MASK) +/* CCGR46 Bit Fields */ +#define CCM_CCGR46_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR46_CG_SHIFT 0 +#define CCM_CCGR46_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_CG_SHIFT))&CCM_CCGR46_CG_MASK) +/* CCGR46_SET Bit Fields */ +#define CCM_CCGR46_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR46_SET_CG_SHIFT 0 +#define CCM_CCGR46_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_SET_CG_SHIFT))&CCM_CCGR46_SET_CG_MASK) +/* CCGR46_CLR Bit Fields */ +#define CCM_CCGR46_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR46_CLR_CG_SHIFT 0 +#define CCM_CCGR46_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_CLR_CG_SHIFT))&CCM_CCGR46_CLR_CG_MASK) +/* CCGR46_TOG Bit Fields */ +#define CCM_CCGR46_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR46_TOG_CG_SHIFT 0 +#define CCM_CCGR46_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR46_TOG_CG_SHIFT))&CCM_CCGR46_TOG_CG_MASK) +/* CCGR47 Bit Fields */ +#define CCM_CCGR47_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR47_CG_SHIFT 0 +#define CCM_CCGR47_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_CG_SHIFT))&CCM_CCGR47_CG_MASK) +/* CCGR47_SET Bit Fields */ +#define CCM_CCGR47_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR47_SET_CG_SHIFT 0 +#define CCM_CCGR47_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_SET_CG_SHIFT))&CCM_CCGR47_SET_CG_MASK) +/* CCGR47_CLR Bit Fields */ +#define CCM_CCGR47_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR47_CLR_CG_SHIFT 0 +#define CCM_CCGR47_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_CLR_CG_SHIFT))&CCM_CCGR47_CLR_CG_MASK) +/* CCGR47_TOG Bit Fields */ +#define CCM_CCGR47_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR47_TOG_CG_SHIFT 0 +#define CCM_CCGR47_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR47_TOG_CG_SHIFT))&CCM_CCGR47_TOG_CG_MASK) +/* CCGR48 Bit Fields */ +#define CCM_CCGR48_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR48_CG_SHIFT 0 +#define CCM_CCGR48_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_CG_SHIFT))&CCM_CCGR48_CG_MASK) +/* CCGR48_SET Bit Fields */ +#define CCM_CCGR48_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR48_SET_CG_SHIFT 0 +#define CCM_CCGR48_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_SET_CG_SHIFT))&CCM_CCGR48_SET_CG_MASK) +/* CCGR48_CLR Bit Fields */ +#define CCM_CCGR48_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR48_CLR_CG_SHIFT 0 +#define CCM_CCGR48_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_CLR_CG_SHIFT))&CCM_CCGR48_CLR_CG_MASK) +/* CCGR48_TOG Bit Fields */ +#define CCM_CCGR48_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR48_TOG_CG_SHIFT 0 +#define CCM_CCGR48_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR48_TOG_CG_SHIFT))&CCM_CCGR48_TOG_CG_MASK) +/* CCGR49 Bit Fields */ +#define CCM_CCGR49_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR49_CG_SHIFT 0 +#define CCM_CCGR49_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_CG_SHIFT))&CCM_CCGR49_CG_MASK) +/* CCGR49_SET Bit Fields */ +#define CCM_CCGR49_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR49_SET_CG_SHIFT 0 +#define CCM_CCGR49_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_SET_CG_SHIFT))&CCM_CCGR49_SET_CG_MASK) +/* CCGR49_CLR Bit Fields */ +#define CCM_CCGR49_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR49_CLR_CG_SHIFT 0 +#define CCM_CCGR49_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_CLR_CG_SHIFT))&CCM_CCGR49_CLR_CG_MASK) +/* CCGR49_TOG Bit Fields */ +#define CCM_CCGR49_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR49_TOG_CG_SHIFT 0 +#define CCM_CCGR49_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR49_TOG_CG_SHIFT))&CCM_CCGR49_TOG_CG_MASK) +/* CCGR50 Bit Fields */ +#define CCM_CCGR50_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR50_CG_SHIFT 0 +#define CCM_CCGR50_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_CG_SHIFT))&CCM_CCGR50_CG_MASK) +/* CCGR50_SET Bit Fields */ +#define CCM_CCGR50_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR50_SET_CG_SHIFT 0 +#define CCM_CCGR50_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_SET_CG_SHIFT))&CCM_CCGR50_SET_CG_MASK) +/* CCGR50_CLR Bit Fields */ +#define CCM_CCGR50_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR50_CLR_CG_SHIFT 0 +#define CCM_CCGR50_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_CLR_CG_SHIFT))&CCM_CCGR50_CLR_CG_MASK) +/* CCGR50_TOG Bit Fields */ +#define CCM_CCGR50_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR50_TOG_CG_SHIFT 0 +#define CCM_CCGR50_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR50_TOG_CG_SHIFT))&CCM_CCGR50_TOG_CG_MASK) +/* CCGR51 Bit Fields */ +#define CCM_CCGR51_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR51_CG_SHIFT 0 +#define CCM_CCGR51_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_CG_SHIFT))&CCM_CCGR51_CG_MASK) +/* CCGR51_SET Bit Fields */ +#define CCM_CCGR51_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR51_SET_CG_SHIFT 0 +#define CCM_CCGR51_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_SET_CG_SHIFT))&CCM_CCGR51_SET_CG_MASK) +/* CCGR51_CLR Bit Fields */ +#define CCM_CCGR51_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR51_CLR_CG_SHIFT 0 +#define CCM_CCGR51_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_CLR_CG_SHIFT))&CCM_CCGR51_CLR_CG_MASK) +/* CCGR51_TOG Bit Fields */ +#define CCM_CCGR51_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR51_TOG_CG_SHIFT 0 +#define CCM_CCGR51_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR51_TOG_CG_SHIFT))&CCM_CCGR51_TOG_CG_MASK) +/* CCGR52 Bit Fields */ +#define CCM_CCGR52_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR52_CG_SHIFT 0 +#define CCM_CCGR52_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_CG_SHIFT))&CCM_CCGR52_CG_MASK) +/* CCGR52_SET Bit Fields */ +#define CCM_CCGR52_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR52_SET_CG_SHIFT 0 +#define CCM_CCGR52_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_SET_CG_SHIFT))&CCM_CCGR52_SET_CG_MASK) +/* CCGR52_CLR Bit Fields */ +#define CCM_CCGR52_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR52_CLR_CG_SHIFT 0 +#define CCM_CCGR52_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_CLR_CG_SHIFT))&CCM_CCGR52_CLR_CG_MASK) +/* CCGR52_TOG Bit Fields */ +#define CCM_CCGR52_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR52_TOG_CG_SHIFT 0 +#define CCM_CCGR52_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR52_TOG_CG_SHIFT))&CCM_CCGR52_TOG_CG_MASK) +/* CCGR53 Bit Fields */ +#define CCM_CCGR53_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR53_CG_SHIFT 0 +#define CCM_CCGR53_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_CG_SHIFT))&CCM_CCGR53_CG_MASK) +/* CCGR53_SET Bit Fields */ +#define CCM_CCGR53_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR53_SET_CG_SHIFT 0 +#define CCM_CCGR53_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_SET_CG_SHIFT))&CCM_CCGR53_SET_CG_MASK) +/* CCGR53_CLR Bit Fields */ +#define CCM_CCGR53_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR53_CLR_CG_SHIFT 0 +#define CCM_CCGR53_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_CLR_CG_SHIFT))&CCM_CCGR53_CLR_CG_MASK) +/* CCGR53_TOG Bit Fields */ +#define CCM_CCGR53_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR53_TOG_CG_SHIFT 0 +#define CCM_CCGR53_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR53_TOG_CG_SHIFT))&CCM_CCGR53_TOG_CG_MASK) +/* CCGR54 Bit Fields */ +#define CCM_CCGR54_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR54_CG_SHIFT 0 +#define CCM_CCGR54_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_CG_SHIFT))&CCM_CCGR54_CG_MASK) +/* CCGR54_SET Bit Fields */ +#define CCM_CCGR54_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR54_SET_CG_SHIFT 0 +#define CCM_CCGR54_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_SET_CG_SHIFT))&CCM_CCGR54_SET_CG_MASK) +/* CCGR54_CLR Bit Fields */ +#define CCM_CCGR54_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR54_CLR_CG_SHIFT 0 +#define CCM_CCGR54_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_CLR_CG_SHIFT))&CCM_CCGR54_CLR_CG_MASK) +/* CCGR54_TOG Bit Fields */ +#define CCM_CCGR54_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR54_TOG_CG_SHIFT 0 +#define CCM_CCGR54_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR54_TOG_CG_SHIFT))&CCM_CCGR54_TOG_CG_MASK) +/* CCGR55 Bit Fields */ +#define CCM_CCGR55_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR55_CG_SHIFT 0 +#define CCM_CCGR55_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_CG_SHIFT))&CCM_CCGR55_CG_MASK) +/* CCGR55_SET Bit Fields */ +#define CCM_CCGR55_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR55_SET_CG_SHIFT 0 +#define CCM_CCGR55_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_SET_CG_SHIFT))&CCM_CCGR55_SET_CG_MASK) +/* CCGR55_CLR Bit Fields */ +#define CCM_CCGR55_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR55_CLR_CG_SHIFT 0 +#define CCM_CCGR55_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_CLR_CG_SHIFT))&CCM_CCGR55_CLR_CG_MASK) +/* CCGR55_TOG Bit Fields */ +#define CCM_CCGR55_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR55_TOG_CG_SHIFT 0 +#define CCM_CCGR55_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR55_TOG_CG_SHIFT))&CCM_CCGR55_TOG_CG_MASK) +/* CCGR56 Bit Fields */ +#define CCM_CCGR56_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR56_CG_SHIFT 0 +#define CCM_CCGR56_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_CG_SHIFT))&CCM_CCGR56_CG_MASK) +/* CCGR56_SET Bit Fields */ +#define CCM_CCGR56_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR56_SET_CG_SHIFT 0 +#define CCM_CCGR56_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_SET_CG_SHIFT))&CCM_CCGR56_SET_CG_MASK) +/* CCGR56_CLR Bit Fields */ +#define CCM_CCGR56_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR56_CLR_CG_SHIFT 0 +#define CCM_CCGR56_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_CLR_CG_SHIFT))&CCM_CCGR56_CLR_CG_MASK) +/* CCGR56_TOG Bit Fields */ +#define CCM_CCGR56_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR56_TOG_CG_SHIFT 0 +#define CCM_CCGR56_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR56_TOG_CG_SHIFT))&CCM_CCGR56_TOG_CG_MASK) +/* CCGR57 Bit Fields */ +#define CCM_CCGR57_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR57_CG_SHIFT 0 +#define CCM_CCGR57_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_CG_SHIFT))&CCM_CCGR57_CG_MASK) +/* CCGR57_SET Bit Fields */ +#define CCM_CCGR57_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR57_SET_CG_SHIFT 0 +#define CCM_CCGR57_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_SET_CG_SHIFT))&CCM_CCGR57_SET_CG_MASK) +/* CCGR57_CLR Bit Fields */ +#define CCM_CCGR57_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR57_CLR_CG_SHIFT 0 +#define CCM_CCGR57_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_CLR_CG_SHIFT))&CCM_CCGR57_CLR_CG_MASK) +/* CCGR57_TOG Bit Fields */ +#define CCM_CCGR57_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR57_TOG_CG_SHIFT 0 +#define CCM_CCGR57_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR57_TOG_CG_SHIFT))&CCM_CCGR57_TOG_CG_MASK) +/* CCGR58 Bit Fields */ +#define CCM_CCGR58_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR58_CG_SHIFT 0 +#define CCM_CCGR58_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_CG_SHIFT))&CCM_CCGR58_CG_MASK) +/* CCGR58_SET Bit Fields */ +#define CCM_CCGR58_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR58_SET_CG_SHIFT 0 +#define CCM_CCGR58_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_SET_CG_SHIFT))&CCM_CCGR58_SET_CG_MASK) +/* CCGR58_CLR Bit Fields */ +#define CCM_CCGR58_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR58_CLR_CG_SHIFT 0 +#define CCM_CCGR58_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_CLR_CG_SHIFT))&CCM_CCGR58_CLR_CG_MASK) +/* CCGR58_TOG Bit Fields */ +#define CCM_CCGR58_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR58_TOG_CG_SHIFT 0 +#define CCM_CCGR58_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR58_TOG_CG_SHIFT))&CCM_CCGR58_TOG_CG_MASK) +/* CCGR59 Bit Fields */ +#define CCM_CCGR59_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR59_CG_SHIFT 0 +#define CCM_CCGR59_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_CG_SHIFT))&CCM_CCGR59_CG_MASK) +/* CCGR59_SET Bit Fields */ +#define CCM_CCGR59_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR59_SET_CG_SHIFT 0 +#define CCM_CCGR59_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_SET_CG_SHIFT))&CCM_CCGR59_SET_CG_MASK) +/* CCGR59_CLR Bit Fields */ +#define CCM_CCGR59_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR59_CLR_CG_SHIFT 0 +#define CCM_CCGR59_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_CLR_CG_SHIFT))&CCM_CCGR59_CLR_CG_MASK) +/* CCGR59_TOG Bit Fields */ +#define CCM_CCGR59_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR59_TOG_CG_SHIFT 0 +#define CCM_CCGR59_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR59_TOG_CG_SHIFT))&CCM_CCGR59_TOG_CG_MASK) +/* CCGR60 Bit Fields */ +#define CCM_CCGR60_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR60_CG_SHIFT 0 +#define CCM_CCGR60_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_CG_SHIFT))&CCM_CCGR60_CG_MASK) +/* CCGR60_SET Bit Fields */ +#define CCM_CCGR60_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR60_SET_CG_SHIFT 0 +#define CCM_CCGR60_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_SET_CG_SHIFT))&CCM_CCGR60_SET_CG_MASK) +/* CCGR60_CLR Bit Fields */ +#define CCM_CCGR60_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR60_CLR_CG_SHIFT 0 +#define CCM_CCGR60_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_CLR_CG_SHIFT))&CCM_CCGR60_CLR_CG_MASK) +/* CCGR60_TOG Bit Fields */ +#define CCM_CCGR60_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR60_TOG_CG_SHIFT 0 +#define CCM_CCGR60_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR60_TOG_CG_SHIFT))&CCM_CCGR60_TOG_CG_MASK) +/* CCGR61 Bit Fields */ +#define CCM_CCGR61_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR61_CG_SHIFT 0 +#define CCM_CCGR61_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_CG_SHIFT))&CCM_CCGR61_CG_MASK) +/* CCGR61_SET Bit Fields */ +#define CCM_CCGR61_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR61_SET_CG_SHIFT 0 +#define CCM_CCGR61_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_SET_CG_SHIFT))&CCM_CCGR61_SET_CG_MASK) +/* CCGR61_CLR Bit Fields */ +#define CCM_CCGR61_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR61_CLR_CG_SHIFT 0 +#define CCM_CCGR61_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_CLR_CG_SHIFT))&CCM_CCGR61_CLR_CG_MASK) +/* CCGR61_TOG Bit Fields */ +#define CCM_CCGR61_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR61_TOG_CG_SHIFT 0 +#define CCM_CCGR61_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR61_TOG_CG_SHIFT))&CCM_CCGR61_TOG_CG_MASK) +/* CCGR62 Bit Fields */ +#define CCM_CCGR62_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR62_CG_SHIFT 0 +#define CCM_CCGR62_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_CG_SHIFT))&CCM_CCGR62_CG_MASK) +/* CCGR62_SET Bit Fields */ +#define CCM_CCGR62_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR62_SET_CG_SHIFT 0 +#define CCM_CCGR62_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_SET_CG_SHIFT))&CCM_CCGR62_SET_CG_MASK) +/* CCGR62_CLR Bit Fields */ +#define CCM_CCGR62_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR62_CLR_CG_SHIFT 0 +#define CCM_CCGR62_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_CLR_CG_SHIFT))&CCM_CCGR62_CLR_CG_MASK) +/* CCGR62_TOG Bit Fields */ +#define CCM_CCGR62_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR62_TOG_CG_SHIFT 0 +#define CCM_CCGR62_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR62_TOG_CG_SHIFT))&CCM_CCGR62_TOG_CG_MASK) +/* CCGR63 Bit Fields */ +#define CCM_CCGR63_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR63_CG_SHIFT 0 +#define CCM_CCGR63_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_CG_SHIFT))&CCM_CCGR63_CG_MASK) +/* CCGR63_SET Bit Fields */ +#define CCM_CCGR63_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR63_SET_CG_SHIFT 0 +#define CCM_CCGR63_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_SET_CG_SHIFT))&CCM_CCGR63_SET_CG_MASK) +/* CCGR63_CLR Bit Fields */ +#define CCM_CCGR63_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR63_CLR_CG_SHIFT 0 +#define CCM_CCGR63_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_CLR_CG_SHIFT))&CCM_CCGR63_CLR_CG_MASK) +/* CCGR63_TOG Bit Fields */ +#define CCM_CCGR63_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR63_TOG_CG_SHIFT 0 +#define CCM_CCGR63_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR63_TOG_CG_SHIFT))&CCM_CCGR63_TOG_CG_MASK) +/* CCGR64 Bit Fields */ +#define CCM_CCGR64_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR64_CG_SHIFT 0 +#define CCM_CCGR64_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_CG_SHIFT))&CCM_CCGR64_CG_MASK) +/* CCGR64_SET Bit Fields */ +#define CCM_CCGR64_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR64_SET_CG_SHIFT 0 +#define CCM_CCGR64_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_SET_CG_SHIFT))&CCM_CCGR64_SET_CG_MASK) +/* CCGR64_CLR Bit Fields */ +#define CCM_CCGR64_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR64_CLR_CG_SHIFT 0 +#define CCM_CCGR64_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_CLR_CG_SHIFT))&CCM_CCGR64_CLR_CG_MASK) +/* CCGR64_TOG Bit Fields */ +#define CCM_CCGR64_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR64_TOG_CG_SHIFT 0 +#define CCM_CCGR64_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR64_TOG_CG_SHIFT))&CCM_CCGR64_TOG_CG_MASK) +/* CCGR65 Bit Fields */ +#define CCM_CCGR65_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR65_CG_SHIFT 0 +#define CCM_CCGR65_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_CG_SHIFT))&CCM_CCGR65_CG_MASK) +/* CCGR65_SET Bit Fields */ +#define CCM_CCGR65_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR65_SET_CG_SHIFT 0 +#define CCM_CCGR65_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_SET_CG_SHIFT))&CCM_CCGR65_SET_CG_MASK) +/* CCGR65_CLR Bit Fields */ +#define CCM_CCGR65_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR65_CLR_CG_SHIFT 0 +#define CCM_CCGR65_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_CLR_CG_SHIFT))&CCM_CCGR65_CLR_CG_MASK) +/* CCGR65_TOG Bit Fields */ +#define CCM_CCGR65_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR65_TOG_CG_SHIFT 0 +#define CCM_CCGR65_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR65_TOG_CG_SHIFT))&CCM_CCGR65_TOG_CG_MASK) +/* CCGR66 Bit Fields */ +#define CCM_CCGR66_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR66_CG_SHIFT 0 +#define CCM_CCGR66_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_CG_SHIFT))&CCM_CCGR66_CG_MASK) +/* CCGR66_SET Bit Fields */ +#define CCM_CCGR66_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR66_SET_CG_SHIFT 0 +#define CCM_CCGR66_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_SET_CG_SHIFT))&CCM_CCGR66_SET_CG_MASK) +/* CCGR66_CLR Bit Fields */ +#define CCM_CCGR66_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR66_CLR_CG_SHIFT 0 +#define CCM_CCGR66_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_CLR_CG_SHIFT))&CCM_CCGR66_CLR_CG_MASK) +/* CCGR66_TOG Bit Fields */ +#define CCM_CCGR66_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR66_TOG_CG_SHIFT 0 +#define CCM_CCGR66_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR66_TOG_CG_SHIFT))&CCM_CCGR66_TOG_CG_MASK) +/* CCGR67 Bit Fields */ +#define CCM_CCGR67_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR67_CG_SHIFT 0 +#define CCM_CCGR67_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_CG_SHIFT))&CCM_CCGR67_CG_MASK) +/* CCGR67_SET Bit Fields */ +#define CCM_CCGR67_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR67_SET_CG_SHIFT 0 +#define CCM_CCGR67_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_SET_CG_SHIFT))&CCM_CCGR67_SET_CG_MASK) +/* CCGR67_CLR Bit Fields */ +#define CCM_CCGR67_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR67_CLR_CG_SHIFT 0 +#define CCM_CCGR67_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_CLR_CG_SHIFT))&CCM_CCGR67_CLR_CG_MASK) +/* CCGR67_TOG Bit Fields */ +#define CCM_CCGR67_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR67_TOG_CG_SHIFT 0 +#define CCM_CCGR67_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR67_TOG_CG_SHIFT))&CCM_CCGR67_TOG_CG_MASK) +/* CCGR68 Bit Fields */ +#define CCM_CCGR68_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR68_CG_SHIFT 0 +#define CCM_CCGR68_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_CG_SHIFT))&CCM_CCGR68_CG_MASK) +/* CCGR68_SET Bit Fields */ +#define CCM_CCGR68_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR68_SET_CG_SHIFT 0 +#define CCM_CCGR68_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_SET_CG_SHIFT))&CCM_CCGR68_SET_CG_MASK) +/* CCGR68_CLR Bit Fields */ +#define CCM_CCGR68_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR68_CLR_CG_SHIFT 0 +#define CCM_CCGR68_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_CLR_CG_SHIFT))&CCM_CCGR68_CLR_CG_MASK) +/* CCGR68_TOG Bit Fields */ +#define CCM_CCGR68_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR68_TOG_CG_SHIFT 0 +#define CCM_CCGR68_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR68_TOG_CG_SHIFT))&CCM_CCGR68_TOG_CG_MASK) +/* CCGR69 Bit Fields */ +#define CCM_CCGR69_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR69_CG_SHIFT 0 +#define CCM_CCGR69_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_CG_SHIFT))&CCM_CCGR69_CG_MASK) +/* CCGR69_SET Bit Fields */ +#define CCM_CCGR69_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR69_SET_CG_SHIFT 0 +#define CCM_CCGR69_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_SET_CG_SHIFT))&CCM_CCGR69_SET_CG_MASK) +/* CCGR69_CLR Bit Fields */ +#define CCM_CCGR69_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR69_CLR_CG_SHIFT 0 +#define CCM_CCGR69_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_CLR_CG_SHIFT))&CCM_CCGR69_CLR_CG_MASK) +/* CCGR69_TOG Bit Fields */ +#define CCM_CCGR69_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR69_TOG_CG_SHIFT 0 +#define CCM_CCGR69_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR69_TOG_CG_SHIFT))&CCM_CCGR69_TOG_CG_MASK) +/* CCGR70 Bit Fields */ +#define CCM_CCGR70_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR70_CG_SHIFT 0 +#define CCM_CCGR70_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_CG_SHIFT))&CCM_CCGR70_CG_MASK) +/* CCGR70_SET Bit Fields */ +#define CCM_CCGR70_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR70_SET_CG_SHIFT 0 +#define CCM_CCGR70_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_SET_CG_SHIFT))&CCM_CCGR70_SET_CG_MASK) +/* CCGR70_CLR Bit Fields */ +#define CCM_CCGR70_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR70_CLR_CG_SHIFT 0 +#define CCM_CCGR70_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_CLR_CG_SHIFT))&CCM_CCGR70_CLR_CG_MASK) +/* CCGR70_TOG Bit Fields */ +#define CCM_CCGR70_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR70_TOG_CG_SHIFT 0 +#define CCM_CCGR70_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR70_TOG_CG_SHIFT))&CCM_CCGR70_TOG_CG_MASK) +/* CCGR71 Bit Fields */ +#define CCM_CCGR71_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR71_CG_SHIFT 0 +#define CCM_CCGR71_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_CG_SHIFT))&CCM_CCGR71_CG_MASK) +/* CCGR71_SET Bit Fields */ +#define CCM_CCGR71_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR71_SET_CG_SHIFT 0 +#define CCM_CCGR71_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_SET_CG_SHIFT))&CCM_CCGR71_SET_CG_MASK) +/* CCGR71_CLR Bit Fields */ +#define CCM_CCGR71_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR71_CLR_CG_SHIFT 0 +#define CCM_CCGR71_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_CLR_CG_SHIFT))&CCM_CCGR71_CLR_CG_MASK) +/* CCGR71_TOG Bit Fields */ +#define CCM_CCGR71_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR71_TOG_CG_SHIFT 0 +#define CCM_CCGR71_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR71_TOG_CG_SHIFT))&CCM_CCGR71_TOG_CG_MASK) +/* CCGR72 Bit Fields */ +#define CCM_CCGR72_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR72_CG_SHIFT 0 +#define CCM_CCGR72_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_CG_SHIFT))&CCM_CCGR72_CG_MASK) +/* CCGR72_SET Bit Fields */ +#define CCM_CCGR72_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR72_SET_CG_SHIFT 0 +#define CCM_CCGR72_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_SET_CG_SHIFT))&CCM_CCGR72_SET_CG_MASK) +/* CCGR72_CLR Bit Fields */ +#define CCM_CCGR72_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR72_CLR_CG_SHIFT 0 +#define CCM_CCGR72_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_CLR_CG_SHIFT))&CCM_CCGR72_CLR_CG_MASK) +/* CCGR72_TOG Bit Fields */ +#define CCM_CCGR72_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR72_TOG_CG_SHIFT 0 +#define CCM_CCGR72_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR72_TOG_CG_SHIFT))&CCM_CCGR72_TOG_CG_MASK) +/* CCGR73 Bit Fields */ +#define CCM_CCGR73_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR73_CG_SHIFT 0 +#define CCM_CCGR73_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_CG_SHIFT))&CCM_CCGR73_CG_MASK) +/* CCGR73_SET Bit Fields */ +#define CCM_CCGR73_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR73_SET_CG_SHIFT 0 +#define CCM_CCGR73_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_SET_CG_SHIFT))&CCM_CCGR73_SET_CG_MASK) +/* CCGR73_CLR Bit Fields */ +#define CCM_CCGR73_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR73_CLR_CG_SHIFT 0 +#define CCM_CCGR73_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_CLR_CG_SHIFT))&CCM_CCGR73_CLR_CG_MASK) +/* CCGR73_TOG Bit Fields */ +#define CCM_CCGR73_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR73_TOG_CG_SHIFT 0 +#define CCM_CCGR73_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR73_TOG_CG_SHIFT))&CCM_CCGR73_TOG_CG_MASK) +/* CCGR74 Bit Fields */ +#define CCM_CCGR74_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR74_CG_SHIFT 0 +#define CCM_CCGR74_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_CG_SHIFT))&CCM_CCGR74_CG_MASK) +/* CCGR74_SET Bit Fields */ +#define CCM_CCGR74_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR74_SET_CG_SHIFT 0 +#define CCM_CCGR74_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_SET_CG_SHIFT))&CCM_CCGR74_SET_CG_MASK) +/* CCGR74_CLR Bit Fields */ +#define CCM_CCGR74_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR74_CLR_CG_SHIFT 0 +#define CCM_CCGR74_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_CLR_CG_SHIFT))&CCM_CCGR74_CLR_CG_MASK) +/* CCGR74_TOG Bit Fields */ +#define CCM_CCGR74_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR74_TOG_CG_SHIFT 0 +#define CCM_CCGR74_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR74_TOG_CG_SHIFT))&CCM_CCGR74_TOG_CG_MASK) +/* CCGR75 Bit Fields */ +#define CCM_CCGR75_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR75_CG_SHIFT 0 +#define CCM_CCGR75_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_CG_SHIFT))&CCM_CCGR75_CG_MASK) +/* CCGR75_SET Bit Fields */ +#define CCM_CCGR75_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR75_SET_CG_SHIFT 0 +#define CCM_CCGR75_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_SET_CG_SHIFT))&CCM_CCGR75_SET_CG_MASK) +/* CCGR75_CLR Bit Fields */ +#define CCM_CCGR75_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR75_CLR_CG_SHIFT 0 +#define CCM_CCGR75_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_CLR_CG_SHIFT))&CCM_CCGR75_CLR_CG_MASK) +/* CCGR75_TOG Bit Fields */ +#define CCM_CCGR75_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR75_TOG_CG_SHIFT 0 +#define CCM_CCGR75_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR75_TOG_CG_SHIFT))&CCM_CCGR75_TOG_CG_MASK) +/* CCGR76 Bit Fields */ +#define CCM_CCGR76_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR76_CG_SHIFT 0 +#define CCM_CCGR76_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_CG_SHIFT))&CCM_CCGR76_CG_MASK) +/* CCGR76_SET Bit Fields */ +#define CCM_CCGR76_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR76_SET_CG_SHIFT 0 +#define CCM_CCGR76_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_SET_CG_SHIFT))&CCM_CCGR76_SET_CG_MASK) +/* CCGR76_CLR Bit Fields */ +#define CCM_CCGR76_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR76_CLR_CG_SHIFT 0 +#define CCM_CCGR76_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_CLR_CG_SHIFT))&CCM_CCGR76_CLR_CG_MASK) +/* CCGR76_TOG Bit Fields */ +#define CCM_CCGR76_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR76_TOG_CG_SHIFT 0 +#define CCM_CCGR76_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR76_TOG_CG_SHIFT))&CCM_CCGR76_TOG_CG_MASK) +/* CCGR77 Bit Fields */ +#define CCM_CCGR77_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR77_CG_SHIFT 0 +#define CCM_CCGR77_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_CG_SHIFT))&CCM_CCGR77_CG_MASK) +/* CCGR77_SET Bit Fields */ +#define CCM_CCGR77_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR77_SET_CG_SHIFT 0 +#define CCM_CCGR77_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_SET_CG_SHIFT))&CCM_CCGR77_SET_CG_MASK) +/* CCGR77_CLR Bit Fields */ +#define CCM_CCGR77_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR77_CLR_CG_SHIFT 0 +#define CCM_CCGR77_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_CLR_CG_SHIFT))&CCM_CCGR77_CLR_CG_MASK) +/* CCGR77_TOG Bit Fields */ +#define CCM_CCGR77_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR77_TOG_CG_SHIFT 0 +#define CCM_CCGR77_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR77_TOG_CG_SHIFT))&CCM_CCGR77_TOG_CG_MASK) +/* CCGR78 Bit Fields */ +#define CCM_CCGR78_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR78_CG_SHIFT 0 +#define CCM_CCGR78_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_CG_SHIFT))&CCM_CCGR78_CG_MASK) +/* CCGR78_SET Bit Fields */ +#define CCM_CCGR78_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR78_SET_CG_SHIFT 0 +#define CCM_CCGR78_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_SET_CG_SHIFT))&CCM_CCGR78_SET_CG_MASK) +/* CCGR78_CLR Bit Fields */ +#define CCM_CCGR78_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR78_CLR_CG_SHIFT 0 +#define CCM_CCGR78_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_CLR_CG_SHIFT))&CCM_CCGR78_CLR_CG_MASK) +/* CCGR78_TOG Bit Fields */ +#define CCM_CCGR78_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR78_TOG_CG_SHIFT 0 +#define CCM_CCGR78_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR78_TOG_CG_SHIFT))&CCM_CCGR78_TOG_CG_MASK) +/* CCGR79 Bit Fields */ +#define CCM_CCGR79_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR79_CG_SHIFT 0 +#define CCM_CCGR79_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_CG_SHIFT))&CCM_CCGR79_CG_MASK) +/* CCGR79_SET Bit Fields */ +#define CCM_CCGR79_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR79_SET_CG_SHIFT 0 +#define CCM_CCGR79_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_SET_CG_SHIFT))&CCM_CCGR79_SET_CG_MASK) +/* CCGR79_CLR Bit Fields */ +#define CCM_CCGR79_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR79_CLR_CG_SHIFT 0 +#define CCM_CCGR79_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_CLR_CG_SHIFT))&CCM_CCGR79_CLR_CG_MASK) +/* CCGR79_TOG Bit Fields */ +#define CCM_CCGR79_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR79_TOG_CG_SHIFT 0 +#define CCM_CCGR79_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR79_TOG_CG_SHIFT))&CCM_CCGR79_TOG_CG_MASK) +/* CCGR80 Bit Fields */ +#define CCM_CCGR80_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR80_CG_SHIFT 0 +#define CCM_CCGR80_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_CG_SHIFT))&CCM_CCGR80_CG_MASK) +/* CCGR80_SET Bit Fields */ +#define CCM_CCGR80_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR80_SET_CG_SHIFT 0 +#define CCM_CCGR80_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_SET_CG_SHIFT))&CCM_CCGR80_SET_CG_MASK) +/* CCGR80_CLR Bit Fields */ +#define CCM_CCGR80_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR80_CLR_CG_SHIFT 0 +#define CCM_CCGR80_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_CLR_CG_SHIFT))&CCM_CCGR80_CLR_CG_MASK) +/* CCGR80_TOG Bit Fields */ +#define CCM_CCGR80_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR80_TOG_CG_SHIFT 0 +#define CCM_CCGR80_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR80_TOG_CG_SHIFT))&CCM_CCGR80_TOG_CG_MASK) +/* CCGR81 Bit Fields */ +#define CCM_CCGR81_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR81_CG_SHIFT 0 +#define CCM_CCGR81_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_CG_SHIFT))&CCM_CCGR81_CG_MASK) +/* CCGR81_SET Bit Fields */ +#define CCM_CCGR81_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR81_SET_CG_SHIFT 0 +#define CCM_CCGR81_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_SET_CG_SHIFT))&CCM_CCGR81_SET_CG_MASK) +/* CCGR81_CLR Bit Fields */ +#define CCM_CCGR81_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR81_CLR_CG_SHIFT 0 +#define CCM_CCGR81_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_CLR_CG_SHIFT))&CCM_CCGR81_CLR_CG_MASK) +/* CCGR81_TOG Bit Fields */ +#define CCM_CCGR81_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR81_TOG_CG_SHIFT 0 +#define CCM_CCGR81_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR81_TOG_CG_SHIFT))&CCM_CCGR81_TOG_CG_MASK) +/* CCGR82 Bit Fields */ +#define CCM_CCGR82_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR82_CG_SHIFT 0 +#define CCM_CCGR82_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_CG_SHIFT))&CCM_CCGR82_CG_MASK) +/* CCGR82_SET Bit Fields */ +#define CCM_CCGR82_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR82_SET_CG_SHIFT 0 +#define CCM_CCGR82_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_SET_CG_SHIFT))&CCM_CCGR82_SET_CG_MASK) +/* CCGR82_CLR Bit Fields */ +#define CCM_CCGR82_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR82_CLR_CG_SHIFT 0 +#define CCM_CCGR82_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_CLR_CG_SHIFT))&CCM_CCGR82_CLR_CG_MASK) +/* CCGR82_TOG Bit Fields */ +#define CCM_CCGR82_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR82_TOG_CG_SHIFT 0 +#define CCM_CCGR82_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR82_TOG_CG_SHIFT))&CCM_CCGR82_TOG_CG_MASK) +/* CCGR83 Bit Fields */ +#define CCM_CCGR83_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR83_CG_SHIFT 0 +#define CCM_CCGR83_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_CG_SHIFT))&CCM_CCGR83_CG_MASK) +/* CCGR83_SET Bit Fields */ +#define CCM_CCGR83_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR83_SET_CG_SHIFT 0 +#define CCM_CCGR83_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_SET_CG_SHIFT))&CCM_CCGR83_SET_CG_MASK) +/* CCGR83_CLR Bit Fields */ +#define CCM_CCGR83_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR83_CLR_CG_SHIFT 0 +#define CCM_CCGR83_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_CLR_CG_SHIFT))&CCM_CCGR83_CLR_CG_MASK) +/* CCGR83_TOG Bit Fields */ +#define CCM_CCGR83_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR83_TOG_CG_SHIFT 0 +#define CCM_CCGR83_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR83_TOG_CG_SHIFT))&CCM_CCGR83_TOG_CG_MASK) +/* CCGR84 Bit Fields */ +#define CCM_CCGR84_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR84_CG_SHIFT 0 +#define CCM_CCGR84_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_CG_SHIFT))&CCM_CCGR84_CG_MASK) +/* CCGR84_SET Bit Fields */ +#define CCM_CCGR84_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR84_SET_CG_SHIFT 0 +#define CCM_CCGR84_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_SET_CG_SHIFT))&CCM_CCGR84_SET_CG_MASK) +/* CCGR84_CLR Bit Fields */ +#define CCM_CCGR84_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR84_CLR_CG_SHIFT 0 +#define CCM_CCGR84_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_CLR_CG_SHIFT))&CCM_CCGR84_CLR_CG_MASK) +/* CCGR84_TOG Bit Fields */ +#define CCM_CCGR84_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR84_TOG_CG_SHIFT 0 +#define CCM_CCGR84_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR84_TOG_CG_SHIFT))&CCM_CCGR84_TOG_CG_MASK) +/* CCGR85 Bit Fields */ +#define CCM_CCGR85_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR85_CG_SHIFT 0 +#define CCM_CCGR85_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_CG_SHIFT))&CCM_CCGR85_CG_MASK) +/* CCGR85_SET Bit Fields */ +#define CCM_CCGR85_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR85_SET_CG_SHIFT 0 +#define CCM_CCGR85_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_SET_CG_SHIFT))&CCM_CCGR85_SET_CG_MASK) +/* CCGR85_CLR Bit Fields */ +#define CCM_CCGR85_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR85_CLR_CG_SHIFT 0 +#define CCM_CCGR85_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_CLR_CG_SHIFT))&CCM_CCGR85_CLR_CG_MASK) +/* CCGR85_TOG Bit Fields */ +#define CCM_CCGR85_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR85_TOG_CG_SHIFT 0 +#define CCM_CCGR85_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR85_TOG_CG_SHIFT))&CCM_CCGR85_TOG_CG_MASK) +/* CCGR86 Bit Fields */ +#define CCM_CCGR86_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR86_CG_SHIFT 0 +#define CCM_CCGR86_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_CG_SHIFT))&CCM_CCGR86_CG_MASK) +/* CCGR86_SET Bit Fields */ +#define CCM_CCGR86_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR86_SET_CG_SHIFT 0 +#define CCM_CCGR86_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_SET_CG_SHIFT))&CCM_CCGR86_SET_CG_MASK) +/* CCGR86_CLR Bit Fields */ +#define CCM_CCGR86_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR86_CLR_CG_SHIFT 0 +#define CCM_CCGR86_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_CLR_CG_SHIFT))&CCM_CCGR86_CLR_CG_MASK) +/* CCGR86_TOG Bit Fields */ +#define CCM_CCGR86_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR86_TOG_CG_SHIFT 0 +#define CCM_CCGR86_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR86_TOG_CG_SHIFT))&CCM_CCGR86_TOG_CG_MASK) +/* CCGR87 Bit Fields */ +#define CCM_CCGR87_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR87_CG_SHIFT 0 +#define CCM_CCGR87_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_CG_SHIFT))&CCM_CCGR87_CG_MASK) +/* CCGR87_SET Bit Fields */ +#define CCM_CCGR87_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR87_SET_CG_SHIFT 0 +#define CCM_CCGR87_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_SET_CG_SHIFT))&CCM_CCGR87_SET_CG_MASK) +/* CCGR87_CLR Bit Fields */ +#define CCM_CCGR87_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR87_CLR_CG_SHIFT 0 +#define CCM_CCGR87_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_CLR_CG_SHIFT))&CCM_CCGR87_CLR_CG_MASK) +/* CCGR87_TOG Bit Fields */ +#define CCM_CCGR87_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR87_TOG_CG_SHIFT 0 +#define CCM_CCGR87_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR87_TOG_CG_SHIFT))&CCM_CCGR87_TOG_CG_MASK) +/* CCGR88 Bit Fields */ +#define CCM_CCGR88_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR88_CG_SHIFT 0 +#define CCM_CCGR88_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_CG_SHIFT))&CCM_CCGR88_CG_MASK) +/* CCGR88_SET Bit Fields */ +#define CCM_CCGR88_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR88_SET_CG_SHIFT 0 +#define CCM_CCGR88_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_SET_CG_SHIFT))&CCM_CCGR88_SET_CG_MASK) +/* CCGR88_CLR Bit Fields */ +#define CCM_CCGR88_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR88_CLR_CG_SHIFT 0 +#define CCM_CCGR88_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_CLR_CG_SHIFT))&CCM_CCGR88_CLR_CG_MASK) +/* CCGR88_TOG Bit Fields */ +#define CCM_CCGR88_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR88_TOG_CG_SHIFT 0 +#define CCM_CCGR88_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR88_TOG_CG_SHIFT))&CCM_CCGR88_TOG_CG_MASK) +/* CCGR89 Bit Fields */ +#define CCM_CCGR89_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR89_CG_SHIFT 0 +#define CCM_CCGR89_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_CG_SHIFT))&CCM_CCGR89_CG_MASK) +/* CCGR89_SET Bit Fields */ +#define CCM_CCGR89_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR89_SET_CG_SHIFT 0 +#define CCM_CCGR89_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_SET_CG_SHIFT))&CCM_CCGR89_SET_CG_MASK) +/* CCGR89_CLR Bit Fields */ +#define CCM_CCGR89_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR89_CLR_CG_SHIFT 0 +#define CCM_CCGR89_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_CLR_CG_SHIFT))&CCM_CCGR89_CLR_CG_MASK) +/* CCGR89_TOG Bit Fields */ +#define CCM_CCGR89_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR89_TOG_CG_SHIFT 0 +#define CCM_CCGR89_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR89_TOG_CG_SHIFT))&CCM_CCGR89_TOG_CG_MASK) +/* CCGR90 Bit Fields */ +#define CCM_CCGR90_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR90_CG_SHIFT 0 +#define CCM_CCGR90_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_CG_SHIFT))&CCM_CCGR90_CG_MASK) +/* CCGR90_SET Bit Fields */ +#define CCM_CCGR90_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR90_SET_CG_SHIFT 0 +#define CCM_CCGR90_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_SET_CG_SHIFT))&CCM_CCGR90_SET_CG_MASK) +/* CCGR90_CLR Bit Fields */ +#define CCM_CCGR90_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR90_CLR_CG_SHIFT 0 +#define CCM_CCGR90_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_CLR_CG_SHIFT))&CCM_CCGR90_CLR_CG_MASK) +/* CCGR90_TOG Bit Fields */ +#define CCM_CCGR90_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR90_TOG_CG_SHIFT 0 +#define CCM_CCGR90_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR90_TOG_CG_SHIFT))&CCM_CCGR90_TOG_CG_MASK) +/* CCGR91 Bit Fields */ +#define CCM_CCGR91_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR91_CG_SHIFT 0 +#define CCM_CCGR91_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_CG_SHIFT))&CCM_CCGR91_CG_MASK) +/* CCGR91_SET Bit Fields */ +#define CCM_CCGR91_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR91_SET_CG_SHIFT 0 +#define CCM_CCGR91_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_SET_CG_SHIFT))&CCM_CCGR91_SET_CG_MASK) +/* CCGR91_CLR Bit Fields */ +#define CCM_CCGR91_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR91_CLR_CG_SHIFT 0 +#define CCM_CCGR91_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_CLR_CG_SHIFT))&CCM_CCGR91_CLR_CG_MASK) +/* CCGR91_TOG Bit Fields */ +#define CCM_CCGR91_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR91_TOG_CG_SHIFT 0 +#define CCM_CCGR91_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR91_TOG_CG_SHIFT))&CCM_CCGR91_TOG_CG_MASK) +/* CCGR92 Bit Fields */ +#define CCM_CCGR92_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR92_CG_SHIFT 0 +#define CCM_CCGR92_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_CG_SHIFT))&CCM_CCGR92_CG_MASK) +/* CCGR92_SET Bit Fields */ +#define CCM_CCGR92_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR92_SET_CG_SHIFT 0 +#define CCM_CCGR92_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_SET_CG_SHIFT))&CCM_CCGR92_SET_CG_MASK) +/* CCGR92_CLR Bit Fields */ +#define CCM_CCGR92_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR92_CLR_CG_SHIFT 0 +#define CCM_CCGR92_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_CLR_CG_SHIFT))&CCM_CCGR92_CLR_CG_MASK) +/* CCGR92_TOG Bit Fields */ +#define CCM_CCGR92_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR92_TOG_CG_SHIFT 0 +#define CCM_CCGR92_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR92_TOG_CG_SHIFT))&CCM_CCGR92_TOG_CG_MASK) +/* CCGR93 Bit Fields */ +#define CCM_CCGR93_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR93_CG_SHIFT 0 +#define CCM_CCGR93_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_CG_SHIFT))&CCM_CCGR93_CG_MASK) +/* CCGR93_SET Bit Fields */ +#define CCM_CCGR93_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR93_SET_CG_SHIFT 0 +#define CCM_CCGR93_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_SET_CG_SHIFT))&CCM_CCGR93_SET_CG_MASK) +/* CCGR93_CLR Bit Fields */ +#define CCM_CCGR93_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR93_CLR_CG_SHIFT 0 +#define CCM_CCGR93_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_CLR_CG_SHIFT))&CCM_CCGR93_CLR_CG_MASK) +/* CCGR93_TOG Bit Fields */ +#define CCM_CCGR93_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR93_TOG_CG_SHIFT 0 +#define CCM_CCGR93_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR93_TOG_CG_SHIFT))&CCM_CCGR93_TOG_CG_MASK) +/* CCGR94 Bit Fields */ +#define CCM_CCGR94_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR94_CG_SHIFT 0 +#define CCM_CCGR94_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_CG_SHIFT))&CCM_CCGR94_CG_MASK) +/* CCGR94_SET Bit Fields */ +#define CCM_CCGR94_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR94_SET_CG_SHIFT 0 +#define CCM_CCGR94_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_SET_CG_SHIFT))&CCM_CCGR94_SET_CG_MASK) +/* CCGR94_CLR Bit Fields */ +#define CCM_CCGR94_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR94_CLR_CG_SHIFT 0 +#define CCM_CCGR94_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_CLR_CG_SHIFT))&CCM_CCGR94_CLR_CG_MASK) +/* CCGR94_TOG Bit Fields */ +#define CCM_CCGR94_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR94_TOG_CG_SHIFT 0 +#define CCM_CCGR94_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR94_TOG_CG_SHIFT))&CCM_CCGR94_TOG_CG_MASK) +/* CCGR95 Bit Fields */ +#define CCM_CCGR95_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR95_CG_SHIFT 0 +#define CCM_CCGR95_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_CG_SHIFT))&CCM_CCGR95_CG_MASK) +/* CCGR95_SET Bit Fields */ +#define CCM_CCGR95_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR95_SET_CG_SHIFT 0 +#define CCM_CCGR95_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_SET_CG_SHIFT))&CCM_CCGR95_SET_CG_MASK) +/* CCGR95_CLR Bit Fields */ +#define CCM_CCGR95_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR95_CLR_CG_SHIFT 0 +#define CCM_CCGR95_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_CLR_CG_SHIFT))&CCM_CCGR95_CLR_CG_MASK) +/* CCGR95_TOG Bit Fields */ +#define CCM_CCGR95_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR95_TOG_CG_SHIFT 0 +#define CCM_CCGR95_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR95_TOG_CG_SHIFT))&CCM_CCGR95_TOG_CG_MASK) +/* CCGR96 Bit Fields */ +#define CCM_CCGR96_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR96_CG_SHIFT 0 +#define CCM_CCGR96_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_CG_SHIFT))&CCM_CCGR96_CG_MASK) +/* CCGR96_SET Bit Fields */ +#define CCM_CCGR96_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR96_SET_CG_SHIFT 0 +#define CCM_CCGR96_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_SET_CG_SHIFT))&CCM_CCGR96_SET_CG_MASK) +/* CCGR96_CLR Bit Fields */ +#define CCM_CCGR96_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR96_CLR_CG_SHIFT 0 +#define CCM_CCGR96_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_CLR_CG_SHIFT))&CCM_CCGR96_CLR_CG_MASK) +/* CCGR96_TOG Bit Fields */ +#define CCM_CCGR96_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR96_TOG_CG_SHIFT 0 +#define CCM_CCGR96_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR96_TOG_CG_SHIFT))&CCM_CCGR96_TOG_CG_MASK) +/* CCGR97 Bit Fields */ +#define CCM_CCGR97_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR97_CG_SHIFT 0 +#define CCM_CCGR97_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_CG_SHIFT))&CCM_CCGR97_CG_MASK) +/* CCGR97_SET Bit Fields */ +#define CCM_CCGR97_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR97_SET_CG_SHIFT 0 +#define CCM_CCGR97_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_SET_CG_SHIFT))&CCM_CCGR97_SET_CG_MASK) +/* CCGR97_CLR Bit Fields */ +#define CCM_CCGR97_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR97_CLR_CG_SHIFT 0 +#define CCM_CCGR97_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_CLR_CG_SHIFT))&CCM_CCGR97_CLR_CG_MASK) +/* CCGR97_TOG Bit Fields */ +#define CCM_CCGR97_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR97_TOG_CG_SHIFT 0 +#define CCM_CCGR97_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR97_TOG_CG_SHIFT))&CCM_CCGR97_TOG_CG_MASK) +/* CCGR98 Bit Fields */ +#define CCM_CCGR98_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR98_CG_SHIFT 0 +#define CCM_CCGR98_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_CG_SHIFT))&CCM_CCGR98_CG_MASK) +/* CCGR98_SET Bit Fields */ +#define CCM_CCGR98_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR98_SET_CG_SHIFT 0 +#define CCM_CCGR98_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_SET_CG_SHIFT))&CCM_CCGR98_SET_CG_MASK) +/* CCGR98_CLR Bit Fields */ +#define CCM_CCGR98_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR98_CLR_CG_SHIFT 0 +#define CCM_CCGR98_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_CLR_CG_SHIFT))&CCM_CCGR98_CLR_CG_MASK) +/* CCGR98_TOG Bit Fields */ +#define CCM_CCGR98_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR98_TOG_CG_SHIFT 0 +#define CCM_CCGR98_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR98_TOG_CG_SHIFT))&CCM_CCGR98_TOG_CG_MASK) +/* CCGR99 Bit Fields */ +#define CCM_CCGR99_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR99_CG_SHIFT 0 +#define CCM_CCGR99_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_CG_SHIFT))&CCM_CCGR99_CG_MASK) +/* CCGR99_SET Bit Fields */ +#define CCM_CCGR99_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR99_SET_CG_SHIFT 0 +#define CCM_CCGR99_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_SET_CG_SHIFT))&CCM_CCGR99_SET_CG_MASK) +/* CCGR99_CLR Bit Fields */ +#define CCM_CCGR99_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR99_CLR_CG_SHIFT 0 +#define CCM_CCGR99_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_CLR_CG_SHIFT))&CCM_CCGR99_CLR_CG_MASK) +/* CCGR99_TOG Bit Fields */ +#define CCM_CCGR99_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR99_TOG_CG_SHIFT 0 +#define CCM_CCGR99_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR99_TOG_CG_SHIFT))&CCM_CCGR99_TOG_CG_MASK) +/* CCGR100 Bit Fields */ +#define CCM_CCGR100_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR100_CG_SHIFT 0 +#define CCM_CCGR100_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_CG_SHIFT))&CCM_CCGR100_CG_MASK) +/* CCGR100_SET Bit Fields */ +#define CCM_CCGR100_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR100_SET_CG_SHIFT 0 +#define CCM_CCGR100_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_SET_CG_SHIFT))&CCM_CCGR100_SET_CG_MASK) +/* CCGR100_CLR Bit Fields */ +#define CCM_CCGR100_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR100_CLR_CG_SHIFT 0 +#define CCM_CCGR100_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_CLR_CG_SHIFT))&CCM_CCGR100_CLR_CG_MASK) +/* CCGR100_TOG Bit Fields */ +#define CCM_CCGR100_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR100_TOG_CG_SHIFT 0 +#define CCM_CCGR100_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR100_TOG_CG_SHIFT))&CCM_CCGR100_TOG_CG_MASK) +/* CCGR101 Bit Fields */ +#define CCM_CCGR101_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR101_CG_SHIFT 0 +#define CCM_CCGR101_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_CG_SHIFT))&CCM_CCGR101_CG_MASK) +/* CCGR101_SET Bit Fields */ +#define CCM_CCGR101_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR101_SET_CG_SHIFT 0 +#define CCM_CCGR101_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_SET_CG_SHIFT))&CCM_CCGR101_SET_CG_MASK) +/* CCGR101_CLR Bit Fields */ +#define CCM_CCGR101_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR101_CLR_CG_SHIFT 0 +#define CCM_CCGR101_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_CLR_CG_SHIFT))&CCM_CCGR101_CLR_CG_MASK) +/* CCGR101_TOG Bit Fields */ +#define CCM_CCGR101_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR101_TOG_CG_SHIFT 0 +#define CCM_CCGR101_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR101_TOG_CG_SHIFT))&CCM_CCGR101_TOG_CG_MASK) +/* CCGR102 Bit Fields */ +#define CCM_CCGR102_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR102_CG_SHIFT 0 +#define CCM_CCGR102_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_CG_SHIFT))&CCM_CCGR102_CG_MASK) +/* CCGR102_SET Bit Fields */ +#define CCM_CCGR102_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR102_SET_CG_SHIFT 0 +#define CCM_CCGR102_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_SET_CG_SHIFT))&CCM_CCGR102_SET_CG_MASK) +/* CCGR102_CLR Bit Fields */ +#define CCM_CCGR102_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR102_CLR_CG_SHIFT 0 +#define CCM_CCGR102_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_CLR_CG_SHIFT))&CCM_CCGR102_CLR_CG_MASK) +/* CCGR102_TOG Bit Fields */ +#define CCM_CCGR102_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR102_TOG_CG_SHIFT 0 +#define CCM_CCGR102_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR102_TOG_CG_SHIFT))&CCM_CCGR102_TOG_CG_MASK) +/* CCGR103 Bit Fields */ +#define CCM_CCGR103_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR103_CG_SHIFT 0 +#define CCM_CCGR103_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_CG_SHIFT))&CCM_CCGR103_CG_MASK) +/* CCGR103_SET Bit Fields */ +#define CCM_CCGR103_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR103_SET_CG_SHIFT 0 +#define CCM_CCGR103_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_SET_CG_SHIFT))&CCM_CCGR103_SET_CG_MASK) +/* CCGR103_CLR Bit Fields */ +#define CCM_CCGR103_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR103_CLR_CG_SHIFT 0 +#define CCM_CCGR103_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_CLR_CG_SHIFT))&CCM_CCGR103_CLR_CG_MASK) +/* CCGR103_TOG Bit Fields */ +#define CCM_CCGR103_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR103_TOG_CG_SHIFT 0 +#define CCM_CCGR103_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR103_TOG_CG_SHIFT))&CCM_CCGR103_TOG_CG_MASK) +/* CCGR104 Bit Fields */ +#define CCM_CCGR104_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR104_CG_SHIFT 0 +#define CCM_CCGR104_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_CG_SHIFT))&CCM_CCGR104_CG_MASK) +/* CCGR104_SET Bit Fields */ +#define CCM_CCGR104_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR104_SET_CG_SHIFT 0 +#define CCM_CCGR104_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_SET_CG_SHIFT))&CCM_CCGR104_SET_CG_MASK) +/* CCGR104_CLR Bit Fields */ +#define CCM_CCGR104_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR104_CLR_CG_SHIFT 0 +#define CCM_CCGR104_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_CLR_CG_SHIFT))&CCM_CCGR104_CLR_CG_MASK) +/* CCGR104_TOG Bit Fields */ +#define CCM_CCGR104_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR104_TOG_CG_SHIFT 0 +#define CCM_CCGR104_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR104_TOG_CG_SHIFT))&CCM_CCGR104_TOG_CG_MASK) +/* CCGR105 Bit Fields */ +#define CCM_CCGR105_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR105_CG_SHIFT 0 +#define CCM_CCGR105_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_CG_SHIFT))&CCM_CCGR105_CG_MASK) +/* CCGR105_SET Bit Fields */ +#define CCM_CCGR105_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR105_SET_CG_SHIFT 0 +#define CCM_CCGR105_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_SET_CG_SHIFT))&CCM_CCGR105_SET_CG_MASK) +/* CCGR105_CLR Bit Fields */ +#define CCM_CCGR105_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR105_CLR_CG_SHIFT 0 +#define CCM_CCGR105_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_CLR_CG_SHIFT))&CCM_CCGR105_CLR_CG_MASK) +/* CCGR105_TOG Bit Fields */ +#define CCM_CCGR105_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR105_TOG_CG_SHIFT 0 +#define CCM_CCGR105_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR105_TOG_CG_SHIFT))&CCM_CCGR105_TOG_CG_MASK) +/* CCGR106 Bit Fields */ +#define CCM_CCGR106_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR106_CG_SHIFT 0 +#define CCM_CCGR106_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_CG_SHIFT))&CCM_CCGR106_CG_MASK) +/* CCGR106_SET Bit Fields */ +#define CCM_CCGR106_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR106_SET_CG_SHIFT 0 +#define CCM_CCGR106_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_SET_CG_SHIFT))&CCM_CCGR106_SET_CG_MASK) +/* CCGR106_CLR Bit Fields */ +#define CCM_CCGR106_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR106_CLR_CG_SHIFT 0 +#define CCM_CCGR106_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_CLR_CG_SHIFT))&CCM_CCGR106_CLR_CG_MASK) +/* CCGR106_TOG Bit Fields */ +#define CCM_CCGR106_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR106_TOG_CG_SHIFT 0 +#define CCM_CCGR106_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR106_TOG_CG_SHIFT))&CCM_CCGR106_TOG_CG_MASK) +/* CCGR107 Bit Fields */ +#define CCM_CCGR107_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR107_CG_SHIFT 0 +#define CCM_CCGR107_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_CG_SHIFT))&CCM_CCGR107_CG_MASK) +/* CCGR107_SET Bit Fields */ +#define CCM_CCGR107_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR107_SET_CG_SHIFT 0 +#define CCM_CCGR107_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_SET_CG_SHIFT))&CCM_CCGR107_SET_CG_MASK) +/* CCGR107_CLR Bit Fields */ +#define CCM_CCGR107_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR107_CLR_CG_SHIFT 0 +#define CCM_CCGR107_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_CLR_CG_SHIFT))&CCM_CCGR107_CLR_CG_MASK) +/* CCGR107_TOG Bit Fields */ +#define CCM_CCGR107_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR107_TOG_CG_SHIFT 0 +#define CCM_CCGR107_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR107_TOG_CG_SHIFT))&CCM_CCGR107_TOG_CG_MASK) +/* CCGR108 Bit Fields */ +#define CCM_CCGR108_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR108_CG_SHIFT 0 +#define CCM_CCGR108_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_CG_SHIFT))&CCM_CCGR108_CG_MASK) +/* CCGR108_SET Bit Fields */ +#define CCM_CCGR108_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR108_SET_CG_SHIFT 0 +#define CCM_CCGR108_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_SET_CG_SHIFT))&CCM_CCGR108_SET_CG_MASK) +/* CCGR108_CLR Bit Fields */ +#define CCM_CCGR108_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR108_CLR_CG_SHIFT 0 +#define CCM_CCGR108_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_CLR_CG_SHIFT))&CCM_CCGR108_CLR_CG_MASK) +/* CCGR108_TOG Bit Fields */ +#define CCM_CCGR108_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR108_TOG_CG_SHIFT 0 +#define CCM_CCGR108_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR108_TOG_CG_SHIFT))&CCM_CCGR108_TOG_CG_MASK) +/* CCGR109 Bit Fields */ +#define CCM_CCGR109_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR109_CG_SHIFT 0 +#define CCM_CCGR109_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_CG_SHIFT))&CCM_CCGR109_CG_MASK) +/* CCGR109_SET Bit Fields */ +#define CCM_CCGR109_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR109_SET_CG_SHIFT 0 +#define CCM_CCGR109_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_SET_CG_SHIFT))&CCM_CCGR109_SET_CG_MASK) +/* CCGR109_CLR Bit Fields */ +#define CCM_CCGR109_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR109_CLR_CG_SHIFT 0 +#define CCM_CCGR109_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_CLR_CG_SHIFT))&CCM_CCGR109_CLR_CG_MASK) +/* CCGR109_TOG Bit Fields */ +#define CCM_CCGR109_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR109_TOG_CG_SHIFT 0 +#define CCM_CCGR109_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR109_TOG_CG_SHIFT))&CCM_CCGR109_TOG_CG_MASK) +/* CCGR110 Bit Fields */ +#define CCM_CCGR110_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR110_CG_SHIFT 0 +#define CCM_CCGR110_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_CG_SHIFT))&CCM_CCGR110_CG_MASK) +/* CCGR110_SET Bit Fields */ +#define CCM_CCGR110_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR110_SET_CG_SHIFT 0 +#define CCM_CCGR110_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_SET_CG_SHIFT))&CCM_CCGR110_SET_CG_MASK) +/* CCGR110_CLR Bit Fields */ +#define CCM_CCGR110_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR110_CLR_CG_SHIFT 0 +#define CCM_CCGR110_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_CLR_CG_SHIFT))&CCM_CCGR110_CLR_CG_MASK) +/* CCGR110_TOG Bit Fields */ +#define CCM_CCGR110_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR110_TOG_CG_SHIFT 0 +#define CCM_CCGR110_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR110_TOG_CG_SHIFT))&CCM_CCGR110_TOG_CG_MASK) +/* CCGR111 Bit Fields */ +#define CCM_CCGR111_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR111_CG_SHIFT 0 +#define CCM_CCGR111_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_CG_SHIFT))&CCM_CCGR111_CG_MASK) +/* CCGR111_SET Bit Fields */ +#define CCM_CCGR111_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR111_SET_CG_SHIFT 0 +#define CCM_CCGR111_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_SET_CG_SHIFT))&CCM_CCGR111_SET_CG_MASK) +/* CCGR111_CLR Bit Fields */ +#define CCM_CCGR111_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR111_CLR_CG_SHIFT 0 +#define CCM_CCGR111_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_CLR_CG_SHIFT))&CCM_CCGR111_CLR_CG_MASK) +/* CCGR111_TOG Bit Fields */ +#define CCM_CCGR111_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR111_TOG_CG_SHIFT 0 +#define CCM_CCGR111_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR111_TOG_CG_SHIFT))&CCM_CCGR111_TOG_CG_MASK) +/* CCGR112 Bit Fields */ +#define CCM_CCGR112_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR112_CG_SHIFT 0 +#define CCM_CCGR112_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_CG_SHIFT))&CCM_CCGR112_CG_MASK) +/* CCGR112_SET Bit Fields */ +#define CCM_CCGR112_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR112_SET_CG_SHIFT 0 +#define CCM_CCGR112_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_SET_CG_SHIFT))&CCM_CCGR112_SET_CG_MASK) +/* CCGR112_CLR Bit Fields */ +#define CCM_CCGR112_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR112_CLR_CG_SHIFT 0 +#define CCM_CCGR112_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_CLR_CG_SHIFT))&CCM_CCGR112_CLR_CG_MASK) +/* CCGR112_TOG Bit Fields */ +#define CCM_CCGR112_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR112_TOG_CG_SHIFT 0 +#define CCM_CCGR112_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR112_TOG_CG_SHIFT))&CCM_CCGR112_TOG_CG_MASK) +/* CCGR113 Bit Fields */ +#define CCM_CCGR113_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR113_CG_SHIFT 0 +#define CCM_CCGR113_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_CG_SHIFT))&CCM_CCGR113_CG_MASK) +/* CCGR113_SET Bit Fields */ +#define CCM_CCGR113_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR113_SET_CG_SHIFT 0 +#define CCM_CCGR113_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_SET_CG_SHIFT))&CCM_CCGR113_SET_CG_MASK) +/* CCGR113_CLR Bit Fields */ +#define CCM_CCGR113_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR113_CLR_CG_SHIFT 0 +#define CCM_CCGR113_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_CLR_CG_SHIFT))&CCM_CCGR113_CLR_CG_MASK) +/* CCGR113_TOG Bit Fields */ +#define CCM_CCGR113_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR113_TOG_CG_SHIFT 0 +#define CCM_CCGR113_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR113_TOG_CG_SHIFT))&CCM_CCGR113_TOG_CG_MASK) +/* CCGR114 Bit Fields */ +#define CCM_CCGR114_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR114_CG_SHIFT 0 +#define CCM_CCGR114_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_CG_SHIFT))&CCM_CCGR114_CG_MASK) +/* CCGR114_SET Bit Fields */ +#define CCM_CCGR114_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR114_SET_CG_SHIFT 0 +#define CCM_CCGR114_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_SET_CG_SHIFT))&CCM_CCGR114_SET_CG_MASK) +/* CCGR114_CLR Bit Fields */ +#define CCM_CCGR114_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR114_CLR_CG_SHIFT 0 +#define CCM_CCGR114_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_CLR_CG_SHIFT))&CCM_CCGR114_CLR_CG_MASK) +/* CCGR114_TOG Bit Fields */ +#define CCM_CCGR114_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR114_TOG_CG_SHIFT 0 +#define CCM_CCGR114_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR114_TOG_CG_SHIFT))&CCM_CCGR114_TOG_CG_MASK) +/* CCGR115 Bit Fields */ +#define CCM_CCGR115_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR115_CG_SHIFT 0 +#define CCM_CCGR115_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_CG_SHIFT))&CCM_CCGR115_CG_MASK) +/* CCGR115_SET Bit Fields */ +#define CCM_CCGR115_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR115_SET_CG_SHIFT 0 +#define CCM_CCGR115_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_SET_CG_SHIFT))&CCM_CCGR115_SET_CG_MASK) +/* CCGR115_CLR Bit Fields */ +#define CCM_CCGR115_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR115_CLR_CG_SHIFT 0 +#define CCM_CCGR115_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_CLR_CG_SHIFT))&CCM_CCGR115_CLR_CG_MASK) +/* CCGR115_TOG Bit Fields */ +#define CCM_CCGR115_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR115_TOG_CG_SHIFT 0 +#define CCM_CCGR115_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR115_TOG_CG_SHIFT))&CCM_CCGR115_TOG_CG_MASK) +/* CCGR116 Bit Fields */ +#define CCM_CCGR116_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR116_CG_SHIFT 0 +#define CCM_CCGR116_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_CG_SHIFT))&CCM_CCGR116_CG_MASK) +/* CCGR116_SET Bit Fields */ +#define CCM_CCGR116_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR116_SET_CG_SHIFT 0 +#define CCM_CCGR116_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_SET_CG_SHIFT))&CCM_CCGR116_SET_CG_MASK) +/* CCGR116_CLR Bit Fields */ +#define CCM_CCGR116_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR116_CLR_CG_SHIFT 0 +#define CCM_CCGR116_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_CLR_CG_SHIFT))&CCM_CCGR116_CLR_CG_MASK) +/* CCGR116_TOG Bit Fields */ +#define CCM_CCGR116_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR116_TOG_CG_SHIFT 0 +#define CCM_CCGR116_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR116_TOG_CG_SHIFT))&CCM_CCGR116_TOG_CG_MASK) +/* CCGR117 Bit Fields */ +#define CCM_CCGR117_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR117_CG_SHIFT 0 +#define CCM_CCGR117_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_CG_SHIFT))&CCM_CCGR117_CG_MASK) +/* CCGR117_SET Bit Fields */ +#define CCM_CCGR117_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR117_SET_CG_SHIFT 0 +#define CCM_CCGR117_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_SET_CG_SHIFT))&CCM_CCGR117_SET_CG_MASK) +/* CCGR117_CLR Bit Fields */ +#define CCM_CCGR117_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR117_CLR_CG_SHIFT 0 +#define CCM_CCGR117_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_CLR_CG_SHIFT))&CCM_CCGR117_CLR_CG_MASK) +/* CCGR117_TOG Bit Fields */ +#define CCM_CCGR117_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR117_TOG_CG_SHIFT 0 +#define CCM_CCGR117_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR117_TOG_CG_SHIFT))&CCM_CCGR117_TOG_CG_MASK) +/* CCGR118 Bit Fields */ +#define CCM_CCGR118_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR118_CG_SHIFT 0 +#define CCM_CCGR118_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_CG_SHIFT))&CCM_CCGR118_CG_MASK) +/* CCGR118_SET Bit Fields */ +#define CCM_CCGR118_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR118_SET_CG_SHIFT 0 +#define CCM_CCGR118_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_SET_CG_SHIFT))&CCM_CCGR118_SET_CG_MASK) +/* CCGR118_CLR Bit Fields */ +#define CCM_CCGR118_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR118_CLR_CG_SHIFT 0 +#define CCM_CCGR118_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_CLR_CG_SHIFT))&CCM_CCGR118_CLR_CG_MASK) +/* CCGR118_TOG Bit Fields */ +#define CCM_CCGR118_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR118_TOG_CG_SHIFT 0 +#define CCM_CCGR118_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR118_TOG_CG_SHIFT))&CCM_CCGR118_TOG_CG_MASK) +/* CCGR119 Bit Fields */ +#define CCM_CCGR119_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR119_CG_SHIFT 0 +#define CCM_CCGR119_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_CG_SHIFT))&CCM_CCGR119_CG_MASK) +/* CCGR119_SET Bit Fields */ +#define CCM_CCGR119_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR119_SET_CG_SHIFT 0 +#define CCM_CCGR119_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_SET_CG_SHIFT))&CCM_CCGR119_SET_CG_MASK) +/* CCGR119_CLR Bit Fields */ +#define CCM_CCGR119_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR119_CLR_CG_SHIFT 0 +#define CCM_CCGR119_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_CLR_CG_SHIFT))&CCM_CCGR119_CLR_CG_MASK) +/* CCGR119_TOG Bit Fields */ +#define CCM_CCGR119_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR119_TOG_CG_SHIFT 0 +#define CCM_CCGR119_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR119_TOG_CG_SHIFT))&CCM_CCGR119_TOG_CG_MASK) +/* CCGR120 Bit Fields */ +#define CCM_CCGR120_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR120_CG_SHIFT 0 +#define CCM_CCGR120_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_CG_SHIFT))&CCM_CCGR120_CG_MASK) +/* CCGR120_SET Bit Fields */ +#define CCM_CCGR120_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR120_SET_CG_SHIFT 0 +#define CCM_CCGR120_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_SET_CG_SHIFT))&CCM_CCGR120_SET_CG_MASK) +/* CCGR120_CLR Bit Fields */ +#define CCM_CCGR120_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR120_CLR_CG_SHIFT 0 +#define CCM_CCGR120_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_CLR_CG_SHIFT))&CCM_CCGR120_CLR_CG_MASK) +/* CCGR120_TOG Bit Fields */ +#define CCM_CCGR120_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR120_TOG_CG_SHIFT 0 +#define CCM_CCGR120_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR120_TOG_CG_SHIFT))&CCM_CCGR120_TOG_CG_MASK) +/* CCGR121 Bit Fields */ +#define CCM_CCGR121_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR121_CG_SHIFT 0 +#define CCM_CCGR121_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_CG_SHIFT))&CCM_CCGR121_CG_MASK) +/* CCGR121_SET Bit Fields */ +#define CCM_CCGR121_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR121_SET_CG_SHIFT 0 +#define CCM_CCGR121_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_SET_CG_SHIFT))&CCM_CCGR121_SET_CG_MASK) +/* CCGR121_CLR Bit Fields */ +#define CCM_CCGR121_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR121_CLR_CG_SHIFT 0 +#define CCM_CCGR121_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_CLR_CG_SHIFT))&CCM_CCGR121_CLR_CG_MASK) +/* CCGR121_TOG Bit Fields */ +#define CCM_CCGR121_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR121_TOG_CG_SHIFT 0 +#define CCM_CCGR121_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR121_TOG_CG_SHIFT))&CCM_CCGR121_TOG_CG_MASK) +/* CCGR122 Bit Fields */ +#define CCM_CCGR122_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR122_CG_SHIFT 0 +#define CCM_CCGR122_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_CG_SHIFT))&CCM_CCGR122_CG_MASK) +/* CCGR122_SET Bit Fields */ +#define CCM_CCGR122_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR122_SET_CG_SHIFT 0 +#define CCM_CCGR122_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_SET_CG_SHIFT))&CCM_CCGR122_SET_CG_MASK) +/* CCGR122_CLR Bit Fields */ +#define CCM_CCGR122_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR122_CLR_CG_SHIFT 0 +#define CCM_CCGR122_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_CLR_CG_SHIFT))&CCM_CCGR122_CLR_CG_MASK) +/* CCGR122_TOG Bit Fields */ +#define CCM_CCGR122_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR122_TOG_CG_SHIFT 0 +#define CCM_CCGR122_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR122_TOG_CG_SHIFT))&CCM_CCGR122_TOG_CG_MASK) +/* CCGR123 Bit Fields */ +#define CCM_CCGR123_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR123_CG_SHIFT 0 +#define CCM_CCGR123_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_CG_SHIFT))&CCM_CCGR123_CG_MASK) +/* CCGR123_SET Bit Fields */ +#define CCM_CCGR123_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR123_SET_CG_SHIFT 0 +#define CCM_CCGR123_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_SET_CG_SHIFT))&CCM_CCGR123_SET_CG_MASK) +/* CCGR123_CLR Bit Fields */ +#define CCM_CCGR123_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR123_CLR_CG_SHIFT 0 +#define CCM_CCGR123_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_CLR_CG_SHIFT))&CCM_CCGR123_CLR_CG_MASK) +/* CCGR123_TOG Bit Fields */ +#define CCM_CCGR123_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR123_TOG_CG_SHIFT 0 +#define CCM_CCGR123_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR123_TOG_CG_SHIFT))&CCM_CCGR123_TOG_CG_MASK) +/* CCGR124 Bit Fields */ +#define CCM_CCGR124_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR124_CG_SHIFT 0 +#define CCM_CCGR124_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_CG_SHIFT))&CCM_CCGR124_CG_MASK) +/* CCGR124_SET Bit Fields */ +#define CCM_CCGR124_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR124_SET_CG_SHIFT 0 +#define CCM_CCGR124_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_SET_CG_SHIFT))&CCM_CCGR124_SET_CG_MASK) +/* CCGR124_CLR Bit Fields */ +#define CCM_CCGR124_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR124_CLR_CG_SHIFT 0 +#define CCM_CCGR124_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_CLR_CG_SHIFT))&CCM_CCGR124_CLR_CG_MASK) +/* CCGR124_TOG Bit Fields */ +#define CCM_CCGR124_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR124_TOG_CG_SHIFT 0 +#define CCM_CCGR124_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR124_TOG_CG_SHIFT))&CCM_CCGR124_TOG_CG_MASK) +/* CCGR125 Bit Fields */ +#define CCM_CCGR125_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR125_CG_SHIFT 0 +#define CCM_CCGR125_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_CG_SHIFT))&CCM_CCGR125_CG_MASK) +/* CCGR125_SET Bit Fields */ +#define CCM_CCGR125_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR125_SET_CG_SHIFT 0 +#define CCM_CCGR125_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_SET_CG_SHIFT))&CCM_CCGR125_SET_CG_MASK) +/* CCGR125_CLR Bit Fields */ +#define CCM_CCGR125_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR125_CLR_CG_SHIFT 0 +#define CCM_CCGR125_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_CLR_CG_SHIFT))&CCM_CCGR125_CLR_CG_MASK) +/* CCGR125_TOG Bit Fields */ +#define CCM_CCGR125_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR125_TOG_CG_SHIFT 0 +#define CCM_CCGR125_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR125_TOG_CG_SHIFT))&CCM_CCGR125_TOG_CG_MASK) +/* CCGR126 Bit Fields */ +#define CCM_CCGR126_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR126_CG_SHIFT 0 +#define CCM_CCGR126_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_CG_SHIFT))&CCM_CCGR126_CG_MASK) +/* CCGR126_SET Bit Fields */ +#define CCM_CCGR126_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR126_SET_CG_SHIFT 0 +#define CCM_CCGR126_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_SET_CG_SHIFT))&CCM_CCGR126_SET_CG_MASK) +/* CCGR126_CLR Bit Fields */ +#define CCM_CCGR126_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR126_CLR_CG_SHIFT 0 +#define CCM_CCGR126_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_CLR_CG_SHIFT))&CCM_CCGR126_CLR_CG_MASK) +/* CCGR126_TOG Bit Fields */ +#define CCM_CCGR126_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR126_TOG_CG_SHIFT 0 +#define CCM_CCGR126_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR126_TOG_CG_SHIFT))&CCM_CCGR126_TOG_CG_MASK) +/* CCGR127 Bit Fields */ +#define CCM_CCGR127_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR127_CG_SHIFT 0 +#define CCM_CCGR127_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_CG_SHIFT))&CCM_CCGR127_CG_MASK) +/* CCGR127_SET Bit Fields */ +#define CCM_CCGR127_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR127_SET_CG_SHIFT 0 +#define CCM_CCGR127_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_SET_CG_SHIFT))&CCM_CCGR127_SET_CG_MASK) +/* CCGR127_CLR Bit Fields */ +#define CCM_CCGR127_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR127_CLR_CG_SHIFT 0 +#define CCM_CCGR127_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_CLR_CG_SHIFT))&CCM_CCGR127_CLR_CG_MASK) +/* CCGR127_TOG Bit Fields */ +#define CCM_CCGR127_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR127_TOG_CG_SHIFT 0 +#define CCM_CCGR127_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR127_TOG_CG_SHIFT))&CCM_CCGR127_TOG_CG_MASK) +/* CCGR128 Bit Fields */ +#define CCM_CCGR128_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR128_CG_SHIFT 0 +#define CCM_CCGR128_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_CG_SHIFT))&CCM_CCGR128_CG_MASK) +/* CCGR128_SET Bit Fields */ +#define CCM_CCGR128_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR128_SET_CG_SHIFT 0 +#define CCM_CCGR128_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_SET_CG_SHIFT))&CCM_CCGR128_SET_CG_MASK) +/* CCGR128_CLR Bit Fields */ +#define CCM_CCGR128_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR128_CLR_CG_SHIFT 0 +#define CCM_CCGR128_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_CLR_CG_SHIFT))&CCM_CCGR128_CLR_CG_MASK) +/* CCGR128_TOG Bit Fields */ +#define CCM_CCGR128_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR128_TOG_CG_SHIFT 0 +#define CCM_CCGR128_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR128_TOG_CG_SHIFT))&CCM_CCGR128_TOG_CG_MASK) +/* CCGR129 Bit Fields */ +#define CCM_CCGR129_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR129_CG_SHIFT 0 +#define CCM_CCGR129_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_CG_SHIFT))&CCM_CCGR129_CG_MASK) +/* CCGR129_SET Bit Fields */ +#define CCM_CCGR129_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR129_SET_CG_SHIFT 0 +#define CCM_CCGR129_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_SET_CG_SHIFT))&CCM_CCGR129_SET_CG_MASK) +/* CCGR129_CLR Bit Fields */ +#define CCM_CCGR129_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR129_CLR_CG_SHIFT 0 +#define CCM_CCGR129_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_CLR_CG_SHIFT))&CCM_CCGR129_CLR_CG_MASK) +/* CCGR129_TOG Bit Fields */ +#define CCM_CCGR129_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR129_TOG_CG_SHIFT 0 +#define CCM_CCGR129_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR129_TOG_CG_SHIFT))&CCM_CCGR129_TOG_CG_MASK) +/* CCGR130 Bit Fields */ +#define CCM_CCGR130_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR130_CG_SHIFT 0 +#define CCM_CCGR130_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_CG_SHIFT))&CCM_CCGR130_CG_MASK) +/* CCGR130_SET Bit Fields */ +#define CCM_CCGR130_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR130_SET_CG_SHIFT 0 +#define CCM_CCGR130_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_SET_CG_SHIFT))&CCM_CCGR130_SET_CG_MASK) +/* CCGR130_CLR Bit Fields */ +#define CCM_CCGR130_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR130_CLR_CG_SHIFT 0 +#define CCM_CCGR130_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_CLR_CG_SHIFT))&CCM_CCGR130_CLR_CG_MASK) +/* CCGR130_TOG Bit Fields */ +#define CCM_CCGR130_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR130_TOG_CG_SHIFT 0 +#define CCM_CCGR130_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR130_TOG_CG_SHIFT))&CCM_CCGR130_TOG_CG_MASK) +/* CCGR131 Bit Fields */ +#define CCM_CCGR131_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR131_CG_SHIFT 0 +#define CCM_CCGR131_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_CG_SHIFT))&CCM_CCGR131_CG_MASK) +/* CCGR131_SET Bit Fields */ +#define CCM_CCGR131_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR131_SET_CG_SHIFT 0 +#define CCM_CCGR131_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_SET_CG_SHIFT))&CCM_CCGR131_SET_CG_MASK) +/* CCGR131_CLR Bit Fields */ +#define CCM_CCGR131_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR131_CLR_CG_SHIFT 0 +#define CCM_CCGR131_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_CLR_CG_SHIFT))&CCM_CCGR131_CLR_CG_MASK) +/* CCGR131_TOG Bit Fields */ +#define CCM_CCGR131_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR131_TOG_CG_SHIFT 0 +#define CCM_CCGR131_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR131_TOG_CG_SHIFT))&CCM_CCGR131_TOG_CG_MASK) +/* CCGR132 Bit Fields */ +#define CCM_CCGR132_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR132_CG_SHIFT 0 +#define CCM_CCGR132_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_CG_SHIFT))&CCM_CCGR132_CG_MASK) +/* CCGR132_SET Bit Fields */ +#define CCM_CCGR132_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR132_SET_CG_SHIFT 0 +#define CCM_CCGR132_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_SET_CG_SHIFT))&CCM_CCGR132_SET_CG_MASK) +/* CCGR132_CLR Bit Fields */ +#define CCM_CCGR132_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR132_CLR_CG_SHIFT 0 +#define CCM_CCGR132_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_CLR_CG_SHIFT))&CCM_CCGR132_CLR_CG_MASK) +/* CCGR132_TOG Bit Fields */ +#define CCM_CCGR132_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR132_TOG_CG_SHIFT 0 +#define CCM_CCGR132_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR132_TOG_CG_SHIFT))&CCM_CCGR132_TOG_CG_MASK) +/* CCGR133 Bit Fields */ +#define CCM_CCGR133_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR133_CG_SHIFT 0 +#define CCM_CCGR133_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_CG_SHIFT))&CCM_CCGR133_CG_MASK) +/* CCGR133_SET Bit Fields */ +#define CCM_CCGR133_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR133_SET_CG_SHIFT 0 +#define CCM_CCGR133_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_SET_CG_SHIFT))&CCM_CCGR133_SET_CG_MASK) +/* CCGR133_CLR Bit Fields */ +#define CCM_CCGR133_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR133_CLR_CG_SHIFT 0 +#define CCM_CCGR133_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_CLR_CG_SHIFT))&CCM_CCGR133_CLR_CG_MASK) +/* CCGR133_TOG Bit Fields */ +#define CCM_CCGR133_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR133_TOG_CG_SHIFT 0 +#define CCM_CCGR133_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR133_TOG_CG_SHIFT))&CCM_CCGR133_TOG_CG_MASK) +/* CCGR134 Bit Fields */ +#define CCM_CCGR134_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR134_CG_SHIFT 0 +#define CCM_CCGR134_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_CG_SHIFT))&CCM_CCGR134_CG_MASK) +/* CCGR134_SET Bit Fields */ +#define CCM_CCGR134_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR134_SET_CG_SHIFT 0 +#define CCM_CCGR134_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_SET_CG_SHIFT))&CCM_CCGR134_SET_CG_MASK) +/* CCGR134_CLR Bit Fields */ +#define CCM_CCGR134_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR134_CLR_CG_SHIFT 0 +#define CCM_CCGR134_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_CLR_CG_SHIFT))&CCM_CCGR134_CLR_CG_MASK) +/* CCGR134_TOG Bit Fields */ +#define CCM_CCGR134_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR134_TOG_CG_SHIFT 0 +#define CCM_CCGR134_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR134_TOG_CG_SHIFT))&CCM_CCGR134_TOG_CG_MASK) +/* CCGR135 Bit Fields */ +#define CCM_CCGR135_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR135_CG_SHIFT 0 +#define CCM_CCGR135_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_CG_SHIFT))&CCM_CCGR135_CG_MASK) +/* CCGR135_SET Bit Fields */ +#define CCM_CCGR135_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR135_SET_CG_SHIFT 0 +#define CCM_CCGR135_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_SET_CG_SHIFT))&CCM_CCGR135_SET_CG_MASK) +/* CCGR135_CLR Bit Fields */ +#define CCM_CCGR135_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR135_CLR_CG_SHIFT 0 +#define CCM_CCGR135_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_CLR_CG_SHIFT))&CCM_CCGR135_CLR_CG_MASK) +/* CCGR135_TOG Bit Fields */ +#define CCM_CCGR135_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR135_TOG_CG_SHIFT 0 +#define CCM_CCGR135_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR135_TOG_CG_SHIFT))&CCM_CCGR135_TOG_CG_MASK) +/* CCGR136 Bit Fields */ +#define CCM_CCGR136_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR136_CG_SHIFT 0 +#define CCM_CCGR136_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_CG_SHIFT))&CCM_CCGR136_CG_MASK) +/* CCGR136_SET Bit Fields */ +#define CCM_CCGR136_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR136_SET_CG_SHIFT 0 +#define CCM_CCGR136_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_SET_CG_SHIFT))&CCM_CCGR136_SET_CG_MASK) +/* CCGR136_CLR Bit Fields */ +#define CCM_CCGR136_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR136_CLR_CG_SHIFT 0 +#define CCM_CCGR136_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_CLR_CG_SHIFT))&CCM_CCGR136_CLR_CG_MASK) +/* CCGR136_TOG Bit Fields */ +#define CCM_CCGR136_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR136_TOG_CG_SHIFT 0 +#define CCM_CCGR136_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR136_TOG_CG_SHIFT))&CCM_CCGR136_TOG_CG_MASK) +/* CCGR137 Bit Fields */ +#define CCM_CCGR137_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR137_CG_SHIFT 0 +#define CCM_CCGR137_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_CG_SHIFT))&CCM_CCGR137_CG_MASK) +/* CCGR137_SET Bit Fields */ +#define CCM_CCGR137_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR137_SET_CG_SHIFT 0 +#define CCM_CCGR137_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_SET_CG_SHIFT))&CCM_CCGR137_SET_CG_MASK) +/* CCGR137_CLR Bit Fields */ +#define CCM_CCGR137_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR137_CLR_CG_SHIFT 0 +#define CCM_CCGR137_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_CLR_CG_SHIFT))&CCM_CCGR137_CLR_CG_MASK) +/* CCGR137_TOG Bit Fields */ +#define CCM_CCGR137_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR137_TOG_CG_SHIFT 0 +#define CCM_CCGR137_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR137_TOG_CG_SHIFT))&CCM_CCGR137_TOG_CG_MASK) +/* CCGR138 Bit Fields */ +#define CCM_CCGR138_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR138_CG_SHIFT 0 +#define CCM_CCGR138_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_CG_SHIFT))&CCM_CCGR138_CG_MASK) +/* CCGR138_SET Bit Fields */ +#define CCM_CCGR138_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR138_SET_CG_SHIFT 0 +#define CCM_CCGR138_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_SET_CG_SHIFT))&CCM_CCGR138_SET_CG_MASK) +/* CCGR138_CLR Bit Fields */ +#define CCM_CCGR138_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR138_CLR_CG_SHIFT 0 +#define CCM_CCGR138_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_CLR_CG_SHIFT))&CCM_CCGR138_CLR_CG_MASK) +/* CCGR138_TOG Bit Fields */ +#define CCM_CCGR138_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR138_TOG_CG_SHIFT 0 +#define CCM_CCGR138_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR138_TOG_CG_SHIFT))&CCM_CCGR138_TOG_CG_MASK) +/* CCGR139 Bit Fields */ +#define CCM_CCGR139_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR139_CG_SHIFT 0 +#define CCM_CCGR139_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_CG_SHIFT))&CCM_CCGR139_CG_MASK) +/* CCGR139_SET Bit Fields */ +#define CCM_CCGR139_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR139_SET_CG_SHIFT 0 +#define CCM_CCGR139_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_SET_CG_SHIFT))&CCM_CCGR139_SET_CG_MASK) +/* CCGR139_CLR Bit Fields */ +#define CCM_CCGR139_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR139_CLR_CG_SHIFT 0 +#define CCM_CCGR139_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_CLR_CG_SHIFT))&CCM_CCGR139_CLR_CG_MASK) +/* CCGR139_TOG Bit Fields */ +#define CCM_CCGR139_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR139_TOG_CG_SHIFT 0 +#define CCM_CCGR139_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR139_TOG_CG_SHIFT))&CCM_CCGR139_TOG_CG_MASK) +/* CCGR140 Bit Fields */ +#define CCM_CCGR140_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR140_CG_SHIFT 0 +#define CCM_CCGR140_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_CG_SHIFT))&CCM_CCGR140_CG_MASK) +/* CCGR140_SET Bit Fields */ +#define CCM_CCGR140_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR140_SET_CG_SHIFT 0 +#define CCM_CCGR140_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_SET_CG_SHIFT))&CCM_CCGR140_SET_CG_MASK) +/* CCGR140_CLR Bit Fields */ +#define CCM_CCGR140_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR140_CLR_CG_SHIFT 0 +#define CCM_CCGR140_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_CLR_CG_SHIFT))&CCM_CCGR140_CLR_CG_MASK) +/* CCGR140_TOG Bit Fields */ +#define CCM_CCGR140_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR140_TOG_CG_SHIFT 0 +#define CCM_CCGR140_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR140_TOG_CG_SHIFT))&CCM_CCGR140_TOG_CG_MASK) +/* CCGR141 Bit Fields */ +#define CCM_CCGR141_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR141_CG_SHIFT 0 +#define CCM_CCGR141_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_CG_SHIFT))&CCM_CCGR141_CG_MASK) +/* CCGR141_SET Bit Fields */ +#define CCM_CCGR141_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR141_SET_CG_SHIFT 0 +#define CCM_CCGR141_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_SET_CG_SHIFT))&CCM_CCGR141_SET_CG_MASK) +/* CCGR141_CLR Bit Fields */ +#define CCM_CCGR141_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR141_CLR_CG_SHIFT 0 +#define CCM_CCGR141_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_CLR_CG_SHIFT))&CCM_CCGR141_CLR_CG_MASK) +/* CCGR141_TOG Bit Fields */ +#define CCM_CCGR141_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR141_TOG_CG_SHIFT 0 +#define CCM_CCGR141_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR141_TOG_CG_SHIFT))&CCM_CCGR141_TOG_CG_MASK) +/* CCGR142 Bit Fields */ +#define CCM_CCGR142_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR142_CG_SHIFT 0 +#define CCM_CCGR142_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_CG_SHIFT))&CCM_CCGR142_CG_MASK) +/* CCGR142_SET Bit Fields */ +#define CCM_CCGR142_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR142_SET_CG_SHIFT 0 +#define CCM_CCGR142_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_SET_CG_SHIFT))&CCM_CCGR142_SET_CG_MASK) +/* CCGR142_CLR Bit Fields */ +#define CCM_CCGR142_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR142_CLR_CG_SHIFT 0 +#define CCM_CCGR142_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_CLR_CG_SHIFT))&CCM_CCGR142_CLR_CG_MASK) +/* CCGR142_TOG Bit Fields */ +#define CCM_CCGR142_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR142_TOG_CG_SHIFT 0 +#define CCM_CCGR142_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR142_TOG_CG_SHIFT))&CCM_CCGR142_TOG_CG_MASK) +/* CCGR143 Bit Fields */ +#define CCM_CCGR143_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR143_CG_SHIFT 0 +#define CCM_CCGR143_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_CG_SHIFT))&CCM_CCGR143_CG_MASK) +/* CCGR143_SET Bit Fields */ +#define CCM_CCGR143_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR143_SET_CG_SHIFT 0 +#define CCM_CCGR143_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_SET_CG_SHIFT))&CCM_CCGR143_SET_CG_MASK) +/* CCGR143_CLR Bit Fields */ +#define CCM_CCGR143_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR143_CLR_CG_SHIFT 0 +#define CCM_CCGR143_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_CLR_CG_SHIFT))&CCM_CCGR143_CLR_CG_MASK) +/* CCGR143_TOG Bit Fields */ +#define CCM_CCGR143_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR143_TOG_CG_SHIFT 0 +#define CCM_CCGR143_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR143_TOG_CG_SHIFT))&CCM_CCGR143_TOG_CG_MASK) +/* CCGR144 Bit Fields */ +#define CCM_CCGR144_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR144_CG_SHIFT 0 +#define CCM_CCGR144_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_CG_SHIFT))&CCM_CCGR144_CG_MASK) +/* CCGR144_SET Bit Fields */ +#define CCM_CCGR144_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR144_SET_CG_SHIFT 0 +#define CCM_CCGR144_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_SET_CG_SHIFT))&CCM_CCGR144_SET_CG_MASK) +/* CCGR144_CLR Bit Fields */ +#define CCM_CCGR144_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR144_CLR_CG_SHIFT 0 +#define CCM_CCGR144_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_CLR_CG_SHIFT))&CCM_CCGR144_CLR_CG_MASK) +/* CCGR144_TOG Bit Fields */ +#define CCM_CCGR144_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR144_TOG_CG_SHIFT 0 +#define CCM_CCGR144_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR144_TOG_CG_SHIFT))&CCM_CCGR144_TOG_CG_MASK) +/* CCGR145 Bit Fields */ +#define CCM_CCGR145_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR145_CG_SHIFT 0 +#define CCM_CCGR145_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_CG_SHIFT))&CCM_CCGR145_CG_MASK) +/* CCGR145_SET Bit Fields */ +#define CCM_CCGR145_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR145_SET_CG_SHIFT 0 +#define CCM_CCGR145_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_SET_CG_SHIFT))&CCM_CCGR145_SET_CG_MASK) +/* CCGR145_CLR Bit Fields */ +#define CCM_CCGR145_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR145_CLR_CG_SHIFT 0 +#define CCM_CCGR145_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_CLR_CG_SHIFT))&CCM_CCGR145_CLR_CG_MASK) +/* CCGR145_TOG Bit Fields */ +#define CCM_CCGR145_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR145_TOG_CG_SHIFT 0 +#define CCM_CCGR145_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR145_TOG_CG_SHIFT))&CCM_CCGR145_TOG_CG_MASK) +/* CCGR146 Bit Fields */ +#define CCM_CCGR146_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR146_CG_SHIFT 0 +#define CCM_CCGR146_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_CG_SHIFT))&CCM_CCGR146_CG_MASK) +/* CCGR146_SET Bit Fields */ +#define CCM_CCGR146_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR146_SET_CG_SHIFT 0 +#define CCM_CCGR146_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_SET_CG_SHIFT))&CCM_CCGR146_SET_CG_MASK) +/* CCGR146_CLR Bit Fields */ +#define CCM_CCGR146_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR146_CLR_CG_SHIFT 0 +#define CCM_CCGR146_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_CLR_CG_SHIFT))&CCM_CCGR146_CLR_CG_MASK) +/* CCGR146_TOG Bit Fields */ +#define CCM_CCGR146_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR146_TOG_CG_SHIFT 0 +#define CCM_CCGR146_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR146_TOG_CG_SHIFT))&CCM_CCGR146_TOG_CG_MASK) +/* CCGR147 Bit Fields */ +#define CCM_CCGR147_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR147_CG_SHIFT 0 +#define CCM_CCGR147_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_CG_SHIFT))&CCM_CCGR147_CG_MASK) +/* CCGR147_SET Bit Fields */ +#define CCM_CCGR147_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR147_SET_CG_SHIFT 0 +#define CCM_CCGR147_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_SET_CG_SHIFT))&CCM_CCGR147_SET_CG_MASK) +/* CCGR147_CLR Bit Fields */ +#define CCM_CCGR147_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR147_CLR_CG_SHIFT 0 +#define CCM_CCGR147_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_CLR_CG_SHIFT))&CCM_CCGR147_CLR_CG_MASK) +/* CCGR147_TOG Bit Fields */ +#define CCM_CCGR147_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR147_TOG_CG_SHIFT 0 +#define CCM_CCGR147_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR147_TOG_CG_SHIFT))&CCM_CCGR147_TOG_CG_MASK) +/* CCGR148 Bit Fields */ +#define CCM_CCGR148_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR148_CG_SHIFT 0 +#define CCM_CCGR148_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_CG_SHIFT))&CCM_CCGR148_CG_MASK) +/* CCGR148_SET Bit Fields */ +#define CCM_CCGR148_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR148_SET_CG_SHIFT 0 +#define CCM_CCGR148_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_SET_CG_SHIFT))&CCM_CCGR148_SET_CG_MASK) +/* CCGR148_CLR Bit Fields */ +#define CCM_CCGR148_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR148_CLR_CG_SHIFT 0 +#define CCM_CCGR148_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_CLR_CG_SHIFT))&CCM_CCGR148_CLR_CG_MASK) +/* CCGR148_TOG Bit Fields */ +#define CCM_CCGR148_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR148_TOG_CG_SHIFT 0 +#define CCM_CCGR148_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR148_TOG_CG_SHIFT))&CCM_CCGR148_TOG_CG_MASK) +/* CCGR149 Bit Fields */ +#define CCM_CCGR149_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR149_CG_SHIFT 0 +#define CCM_CCGR149_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_CG_SHIFT))&CCM_CCGR149_CG_MASK) +/* CCGR149_SET Bit Fields */ +#define CCM_CCGR149_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR149_SET_CG_SHIFT 0 +#define CCM_CCGR149_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_SET_CG_SHIFT))&CCM_CCGR149_SET_CG_MASK) +/* CCGR149_CLR Bit Fields */ +#define CCM_CCGR149_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR149_CLR_CG_SHIFT 0 +#define CCM_CCGR149_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_CLR_CG_SHIFT))&CCM_CCGR149_CLR_CG_MASK) +/* CCGR149_TOG Bit Fields */ +#define CCM_CCGR149_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR149_TOG_CG_SHIFT 0 +#define CCM_CCGR149_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR149_TOG_CG_SHIFT))&CCM_CCGR149_TOG_CG_MASK) +/* CCGR150 Bit Fields */ +#define CCM_CCGR150_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR150_CG_SHIFT 0 +#define CCM_CCGR150_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_CG_SHIFT))&CCM_CCGR150_CG_MASK) +/* CCGR150_SET Bit Fields */ +#define CCM_CCGR150_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR150_SET_CG_SHIFT 0 +#define CCM_CCGR150_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_SET_CG_SHIFT))&CCM_CCGR150_SET_CG_MASK) +/* CCGR150_CLR Bit Fields */ +#define CCM_CCGR150_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR150_CLR_CG_SHIFT 0 +#define CCM_CCGR150_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_CLR_CG_SHIFT))&CCM_CCGR150_CLR_CG_MASK) +/* CCGR150_TOG Bit Fields */ +#define CCM_CCGR150_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR150_TOG_CG_SHIFT 0 +#define CCM_CCGR150_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR150_TOG_CG_SHIFT))&CCM_CCGR150_TOG_CG_MASK) +/* CCGR151 Bit Fields */ +#define CCM_CCGR151_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR151_CG_SHIFT 0 +#define CCM_CCGR151_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_CG_SHIFT))&CCM_CCGR151_CG_MASK) +/* CCGR151_SET Bit Fields */ +#define CCM_CCGR151_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR151_SET_CG_SHIFT 0 +#define CCM_CCGR151_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_SET_CG_SHIFT))&CCM_CCGR151_SET_CG_MASK) +/* CCGR151_CLR Bit Fields */ +#define CCM_CCGR151_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR151_CLR_CG_SHIFT 0 +#define CCM_CCGR151_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_CLR_CG_SHIFT))&CCM_CCGR151_CLR_CG_MASK) +/* CCGR151_TOG Bit Fields */ +#define CCM_CCGR151_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR151_TOG_CG_SHIFT 0 +#define CCM_CCGR151_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR151_TOG_CG_SHIFT))&CCM_CCGR151_TOG_CG_MASK) +/* CCGR152 Bit Fields */ +#define CCM_CCGR152_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR152_CG_SHIFT 0 +#define CCM_CCGR152_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_CG_SHIFT))&CCM_CCGR152_CG_MASK) +/* CCGR152_SET Bit Fields */ +#define CCM_CCGR152_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR152_SET_CG_SHIFT 0 +#define CCM_CCGR152_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_SET_CG_SHIFT))&CCM_CCGR152_SET_CG_MASK) +/* CCGR152_CLR Bit Fields */ +#define CCM_CCGR152_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR152_CLR_CG_SHIFT 0 +#define CCM_CCGR152_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_CLR_CG_SHIFT))&CCM_CCGR152_CLR_CG_MASK) +/* CCGR152_TOG Bit Fields */ +#define CCM_CCGR152_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR152_TOG_CG_SHIFT 0 +#define CCM_CCGR152_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR152_TOG_CG_SHIFT))&CCM_CCGR152_TOG_CG_MASK) +/* CCGR153 Bit Fields */ +#define CCM_CCGR153_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR153_CG_SHIFT 0 +#define CCM_CCGR153_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_CG_SHIFT))&CCM_CCGR153_CG_MASK) +/* CCGR153_SET Bit Fields */ +#define CCM_CCGR153_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR153_SET_CG_SHIFT 0 +#define CCM_CCGR153_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_SET_CG_SHIFT))&CCM_CCGR153_SET_CG_MASK) +/* CCGR153_CLR Bit Fields */ +#define CCM_CCGR153_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR153_CLR_CG_SHIFT 0 +#define CCM_CCGR153_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_CLR_CG_SHIFT))&CCM_CCGR153_CLR_CG_MASK) +/* CCGR153_TOG Bit Fields */ +#define CCM_CCGR153_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR153_TOG_CG_SHIFT 0 +#define CCM_CCGR153_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR153_TOG_CG_SHIFT))&CCM_CCGR153_TOG_CG_MASK) +/* CCGR154 Bit Fields */ +#define CCM_CCGR154_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR154_CG_SHIFT 0 +#define CCM_CCGR154_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_CG_SHIFT))&CCM_CCGR154_CG_MASK) +/* CCGR154_SET Bit Fields */ +#define CCM_CCGR154_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR154_SET_CG_SHIFT 0 +#define CCM_CCGR154_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_SET_CG_SHIFT))&CCM_CCGR154_SET_CG_MASK) +/* CCGR154_CLR Bit Fields */ +#define CCM_CCGR154_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR154_CLR_CG_SHIFT 0 +#define CCM_CCGR154_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_CLR_CG_SHIFT))&CCM_CCGR154_CLR_CG_MASK) +/* CCGR154_TOG Bit Fields */ +#define CCM_CCGR154_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR154_TOG_CG_SHIFT 0 +#define CCM_CCGR154_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR154_TOG_CG_SHIFT))&CCM_CCGR154_TOG_CG_MASK) +/* CCGR155 Bit Fields */ +#define CCM_CCGR155_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR155_CG_SHIFT 0 +#define CCM_CCGR155_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_CG_SHIFT))&CCM_CCGR155_CG_MASK) +/* CCGR155_SET Bit Fields */ +#define CCM_CCGR155_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR155_SET_CG_SHIFT 0 +#define CCM_CCGR155_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_SET_CG_SHIFT))&CCM_CCGR155_SET_CG_MASK) +/* CCGR155_CLR Bit Fields */ +#define CCM_CCGR155_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR155_CLR_CG_SHIFT 0 +#define CCM_CCGR155_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_CLR_CG_SHIFT))&CCM_CCGR155_CLR_CG_MASK) +/* CCGR155_TOG Bit Fields */ +#define CCM_CCGR155_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR155_TOG_CG_SHIFT 0 +#define CCM_CCGR155_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR155_TOG_CG_SHIFT))&CCM_CCGR155_TOG_CG_MASK) +/* CCGR156 Bit Fields */ +#define CCM_CCGR156_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR156_CG_SHIFT 0 +#define CCM_CCGR156_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_CG_SHIFT))&CCM_CCGR156_CG_MASK) +/* CCGR156_SET Bit Fields */ +#define CCM_CCGR156_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR156_SET_CG_SHIFT 0 +#define CCM_CCGR156_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_SET_CG_SHIFT))&CCM_CCGR156_SET_CG_MASK) +/* CCGR156_CLR Bit Fields */ +#define CCM_CCGR156_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR156_CLR_CG_SHIFT 0 +#define CCM_CCGR156_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_CLR_CG_SHIFT))&CCM_CCGR156_CLR_CG_MASK) +/* CCGR156_TOG Bit Fields */ +#define CCM_CCGR156_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR156_TOG_CG_SHIFT 0 +#define CCM_CCGR156_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR156_TOG_CG_SHIFT))&CCM_CCGR156_TOG_CG_MASK) +/* CCGR157 Bit Fields */ +#define CCM_CCGR157_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR157_CG_SHIFT 0 +#define CCM_CCGR157_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_CG_SHIFT))&CCM_CCGR157_CG_MASK) +/* CCGR157_SET Bit Fields */ +#define CCM_CCGR157_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR157_SET_CG_SHIFT 0 +#define CCM_CCGR157_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_SET_CG_SHIFT))&CCM_CCGR157_SET_CG_MASK) +/* CCGR157_CLR Bit Fields */ +#define CCM_CCGR157_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR157_CLR_CG_SHIFT 0 +#define CCM_CCGR157_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_CLR_CG_SHIFT))&CCM_CCGR157_CLR_CG_MASK) +/* CCGR157_TOG Bit Fields */ +#define CCM_CCGR157_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR157_TOG_CG_SHIFT 0 +#define CCM_CCGR157_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR157_TOG_CG_SHIFT))&CCM_CCGR157_TOG_CG_MASK) +/* CCGR158 Bit Fields */ +#define CCM_CCGR158_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR158_CG_SHIFT 0 +#define CCM_CCGR158_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_CG_SHIFT))&CCM_CCGR158_CG_MASK) +/* CCGR158_SET Bit Fields */ +#define CCM_CCGR158_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR158_SET_CG_SHIFT 0 +#define CCM_CCGR158_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_SET_CG_SHIFT))&CCM_CCGR158_SET_CG_MASK) +/* CCGR158_CLR Bit Fields */ +#define CCM_CCGR158_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR158_CLR_CG_SHIFT 0 +#define CCM_CCGR158_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_CLR_CG_SHIFT))&CCM_CCGR158_CLR_CG_MASK) +/* CCGR158_TOG Bit Fields */ +#define CCM_CCGR158_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR158_TOG_CG_SHIFT 0 +#define CCM_CCGR158_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR158_TOG_CG_SHIFT))&CCM_CCGR158_TOG_CG_MASK) +/* CCGR159 Bit Fields */ +#define CCM_CCGR159_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR159_CG_SHIFT 0 +#define CCM_CCGR159_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_CG_SHIFT))&CCM_CCGR159_CG_MASK) +/* CCGR159_SET Bit Fields */ +#define CCM_CCGR159_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR159_SET_CG_SHIFT 0 +#define CCM_CCGR159_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_SET_CG_SHIFT))&CCM_CCGR159_SET_CG_MASK) +/* CCGR159_CLR Bit Fields */ +#define CCM_CCGR159_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR159_CLR_CG_SHIFT 0 +#define CCM_CCGR159_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_CLR_CG_SHIFT))&CCM_CCGR159_CLR_CG_MASK) +/* CCGR159_TOG Bit Fields */ +#define CCM_CCGR159_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR159_TOG_CG_SHIFT 0 +#define CCM_CCGR159_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR159_TOG_CG_SHIFT))&CCM_CCGR159_TOG_CG_MASK) +/* CCGR160 Bit Fields */ +#define CCM_CCGR160_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR160_CG_SHIFT 0 +#define CCM_CCGR160_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_CG_SHIFT))&CCM_CCGR160_CG_MASK) +/* CCGR160_SET Bit Fields */ +#define CCM_CCGR160_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR160_SET_CG_SHIFT 0 +#define CCM_CCGR160_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_SET_CG_SHIFT))&CCM_CCGR160_SET_CG_MASK) +/* CCGR160_CLR Bit Fields */ +#define CCM_CCGR160_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR160_CLR_CG_SHIFT 0 +#define CCM_CCGR160_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_CLR_CG_SHIFT))&CCM_CCGR160_CLR_CG_MASK) +/* CCGR160_TOG Bit Fields */ +#define CCM_CCGR160_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR160_TOG_CG_SHIFT 0 +#define CCM_CCGR160_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR160_TOG_CG_SHIFT))&CCM_CCGR160_TOG_CG_MASK) +/* CCGR161 Bit Fields */ +#define CCM_CCGR161_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR161_CG_SHIFT 0 +#define CCM_CCGR161_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_CG_SHIFT))&CCM_CCGR161_CG_MASK) +/* CCGR161_SET Bit Fields */ +#define CCM_CCGR161_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR161_SET_CG_SHIFT 0 +#define CCM_CCGR161_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_SET_CG_SHIFT))&CCM_CCGR161_SET_CG_MASK) +/* CCGR161_CLR Bit Fields */ +#define CCM_CCGR161_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR161_CLR_CG_SHIFT 0 +#define CCM_CCGR161_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_CLR_CG_SHIFT))&CCM_CCGR161_CLR_CG_MASK) +/* CCGR161_TOG Bit Fields */ +#define CCM_CCGR161_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR161_TOG_CG_SHIFT 0 +#define CCM_CCGR161_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR161_TOG_CG_SHIFT))&CCM_CCGR161_TOG_CG_MASK) +/* CCGR162 Bit Fields */ +#define CCM_CCGR162_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR162_CG_SHIFT 0 +#define CCM_CCGR162_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_CG_SHIFT))&CCM_CCGR162_CG_MASK) +/* CCGR162_SET Bit Fields */ +#define CCM_CCGR162_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR162_SET_CG_SHIFT 0 +#define CCM_CCGR162_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_SET_CG_SHIFT))&CCM_CCGR162_SET_CG_MASK) +/* CCGR162_CLR Bit Fields */ +#define CCM_CCGR162_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR162_CLR_CG_SHIFT 0 +#define CCM_CCGR162_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_CLR_CG_SHIFT))&CCM_CCGR162_CLR_CG_MASK) +/* CCGR162_TOG Bit Fields */ +#define CCM_CCGR162_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR162_TOG_CG_SHIFT 0 +#define CCM_CCGR162_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR162_TOG_CG_SHIFT))&CCM_CCGR162_TOG_CG_MASK) +/* CCGR163 Bit Fields */ +#define CCM_CCGR163_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR163_CG_SHIFT 0 +#define CCM_CCGR163_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_CG_SHIFT))&CCM_CCGR163_CG_MASK) +/* CCGR163_SET Bit Fields */ +#define CCM_CCGR163_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR163_SET_CG_SHIFT 0 +#define CCM_CCGR163_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_SET_CG_SHIFT))&CCM_CCGR163_SET_CG_MASK) +/* CCGR163_CLR Bit Fields */ +#define CCM_CCGR163_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR163_CLR_CG_SHIFT 0 +#define CCM_CCGR163_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_CLR_CG_SHIFT))&CCM_CCGR163_CLR_CG_MASK) +/* CCGR163_TOG Bit Fields */ +#define CCM_CCGR163_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR163_TOG_CG_SHIFT 0 +#define CCM_CCGR163_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR163_TOG_CG_SHIFT))&CCM_CCGR163_TOG_CG_MASK) +/* CCGR164 Bit Fields */ +#define CCM_CCGR164_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR164_CG_SHIFT 0 +#define CCM_CCGR164_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_CG_SHIFT))&CCM_CCGR164_CG_MASK) +/* CCGR164_SET Bit Fields */ +#define CCM_CCGR164_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR164_SET_CG_SHIFT 0 +#define CCM_CCGR164_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_SET_CG_SHIFT))&CCM_CCGR164_SET_CG_MASK) +/* CCGR164_CLR Bit Fields */ +#define CCM_CCGR164_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR164_CLR_CG_SHIFT 0 +#define CCM_CCGR164_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_CLR_CG_SHIFT))&CCM_CCGR164_CLR_CG_MASK) +/* CCGR164_TOG Bit Fields */ +#define CCM_CCGR164_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR164_TOG_CG_SHIFT 0 +#define CCM_CCGR164_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR164_TOG_CG_SHIFT))&CCM_CCGR164_TOG_CG_MASK) +/* CCGR165 Bit Fields */ +#define CCM_CCGR165_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR165_CG_SHIFT 0 +#define CCM_CCGR165_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_CG_SHIFT))&CCM_CCGR165_CG_MASK) +/* CCGR165_SET Bit Fields */ +#define CCM_CCGR165_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR165_SET_CG_SHIFT 0 +#define CCM_CCGR165_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_SET_CG_SHIFT))&CCM_CCGR165_SET_CG_MASK) +/* CCGR165_CLR Bit Fields */ +#define CCM_CCGR165_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR165_CLR_CG_SHIFT 0 +#define CCM_CCGR165_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_CLR_CG_SHIFT))&CCM_CCGR165_CLR_CG_MASK) +/* CCGR165_TOG Bit Fields */ +#define CCM_CCGR165_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR165_TOG_CG_SHIFT 0 +#define CCM_CCGR165_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR165_TOG_CG_SHIFT))&CCM_CCGR165_TOG_CG_MASK) +/* CCGR166 Bit Fields */ +#define CCM_CCGR166_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR166_CG_SHIFT 0 +#define CCM_CCGR166_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_CG_SHIFT))&CCM_CCGR166_CG_MASK) +/* CCGR166_SET Bit Fields */ +#define CCM_CCGR166_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR166_SET_CG_SHIFT 0 +#define CCM_CCGR166_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_SET_CG_SHIFT))&CCM_CCGR166_SET_CG_MASK) +/* CCGR166_CLR Bit Fields */ +#define CCM_CCGR166_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR166_CLR_CG_SHIFT 0 +#define CCM_CCGR166_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_CLR_CG_SHIFT))&CCM_CCGR166_CLR_CG_MASK) +/* CCGR166_TOG Bit Fields */ +#define CCM_CCGR166_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR166_TOG_CG_SHIFT 0 +#define CCM_CCGR166_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR166_TOG_CG_SHIFT))&CCM_CCGR166_TOG_CG_MASK) +/* CCGR167 Bit Fields */ +#define CCM_CCGR167_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR167_CG_SHIFT 0 +#define CCM_CCGR167_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_CG_SHIFT))&CCM_CCGR167_CG_MASK) +/* CCGR167_SET Bit Fields */ +#define CCM_CCGR167_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR167_SET_CG_SHIFT 0 +#define CCM_CCGR167_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_SET_CG_SHIFT))&CCM_CCGR167_SET_CG_MASK) +/* CCGR167_CLR Bit Fields */ +#define CCM_CCGR167_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR167_CLR_CG_SHIFT 0 +#define CCM_CCGR167_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_CLR_CG_SHIFT))&CCM_CCGR167_CLR_CG_MASK) +/* CCGR167_TOG Bit Fields */ +#define CCM_CCGR167_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR167_TOG_CG_SHIFT 0 +#define CCM_CCGR167_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR167_TOG_CG_SHIFT))&CCM_CCGR167_TOG_CG_MASK) +/* CCGR168 Bit Fields */ +#define CCM_CCGR168_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR168_CG_SHIFT 0 +#define CCM_CCGR168_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_CG_SHIFT))&CCM_CCGR168_CG_MASK) +/* CCGR168_SET Bit Fields */ +#define CCM_CCGR168_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR168_SET_CG_SHIFT 0 +#define CCM_CCGR168_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_SET_CG_SHIFT))&CCM_CCGR168_SET_CG_MASK) +/* CCGR168_CLR Bit Fields */ +#define CCM_CCGR168_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR168_CLR_CG_SHIFT 0 +#define CCM_CCGR168_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_CLR_CG_SHIFT))&CCM_CCGR168_CLR_CG_MASK) +/* CCGR168_TOG Bit Fields */ +#define CCM_CCGR168_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR168_TOG_CG_SHIFT 0 +#define CCM_CCGR168_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR168_TOG_CG_SHIFT))&CCM_CCGR168_TOG_CG_MASK) +/* CCGR169 Bit Fields */ +#define CCM_CCGR169_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR169_CG_SHIFT 0 +#define CCM_CCGR169_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_CG_SHIFT))&CCM_CCGR169_CG_MASK) +/* CCGR169_SET Bit Fields */ +#define CCM_CCGR169_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR169_SET_CG_SHIFT 0 +#define CCM_CCGR169_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_SET_CG_SHIFT))&CCM_CCGR169_SET_CG_MASK) +/* CCGR169_CLR Bit Fields */ +#define CCM_CCGR169_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR169_CLR_CG_SHIFT 0 +#define CCM_CCGR169_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_CLR_CG_SHIFT))&CCM_CCGR169_CLR_CG_MASK) +/* CCGR169_TOG Bit Fields */ +#define CCM_CCGR169_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR169_TOG_CG_SHIFT 0 +#define CCM_CCGR169_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR169_TOG_CG_SHIFT))&CCM_CCGR169_TOG_CG_MASK) +/* CCGR170 Bit Fields */ +#define CCM_CCGR170_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR170_CG_SHIFT 0 +#define CCM_CCGR170_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_CG_SHIFT))&CCM_CCGR170_CG_MASK) +/* CCGR170_SET Bit Fields */ +#define CCM_CCGR170_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR170_SET_CG_SHIFT 0 +#define CCM_CCGR170_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_SET_CG_SHIFT))&CCM_CCGR170_SET_CG_MASK) +/* CCGR170_CLR Bit Fields */ +#define CCM_CCGR170_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR170_CLR_CG_SHIFT 0 +#define CCM_CCGR170_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_CLR_CG_SHIFT))&CCM_CCGR170_CLR_CG_MASK) +/* CCGR170_TOG Bit Fields */ +#define CCM_CCGR170_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR170_TOG_CG_SHIFT 0 +#define CCM_CCGR170_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR170_TOG_CG_SHIFT))&CCM_CCGR170_TOG_CG_MASK) +/* CCGR171 Bit Fields */ +#define CCM_CCGR171_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR171_CG_SHIFT 0 +#define CCM_CCGR171_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_CG_SHIFT))&CCM_CCGR171_CG_MASK) +/* CCGR171_SET Bit Fields */ +#define CCM_CCGR171_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR171_SET_CG_SHIFT 0 +#define CCM_CCGR171_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_SET_CG_SHIFT))&CCM_CCGR171_SET_CG_MASK) +/* CCGR171_CLR Bit Fields */ +#define CCM_CCGR171_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR171_CLR_CG_SHIFT 0 +#define CCM_CCGR171_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_CLR_CG_SHIFT))&CCM_CCGR171_CLR_CG_MASK) +/* CCGR171_TOG Bit Fields */ +#define CCM_CCGR171_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR171_TOG_CG_SHIFT 0 +#define CCM_CCGR171_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR171_TOG_CG_SHIFT))&CCM_CCGR171_TOG_CG_MASK) +/* CCGR172 Bit Fields */ +#define CCM_CCGR172_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR172_CG_SHIFT 0 +#define CCM_CCGR172_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_CG_SHIFT))&CCM_CCGR172_CG_MASK) +/* CCGR172_SET Bit Fields */ +#define CCM_CCGR172_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR172_SET_CG_SHIFT 0 +#define CCM_CCGR172_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_SET_CG_SHIFT))&CCM_CCGR172_SET_CG_MASK) +/* CCGR172_CLR Bit Fields */ +#define CCM_CCGR172_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR172_CLR_CG_SHIFT 0 +#define CCM_CCGR172_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_CLR_CG_SHIFT))&CCM_CCGR172_CLR_CG_MASK) +/* CCGR172_TOG Bit Fields */ +#define CCM_CCGR172_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR172_TOG_CG_SHIFT 0 +#define CCM_CCGR172_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR172_TOG_CG_SHIFT))&CCM_CCGR172_TOG_CG_MASK) +/* CCGR173 Bit Fields */ +#define CCM_CCGR173_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR173_CG_SHIFT 0 +#define CCM_CCGR173_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_CG_SHIFT))&CCM_CCGR173_CG_MASK) +/* CCGR173_SET Bit Fields */ +#define CCM_CCGR173_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR173_SET_CG_SHIFT 0 +#define CCM_CCGR173_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_SET_CG_SHIFT))&CCM_CCGR173_SET_CG_MASK) +/* CCGR173_CLR Bit Fields */ +#define CCM_CCGR173_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR173_CLR_CG_SHIFT 0 +#define CCM_CCGR173_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_CLR_CG_SHIFT))&CCM_CCGR173_CLR_CG_MASK) +/* CCGR173_TOG Bit Fields */ +#define CCM_CCGR173_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR173_TOG_CG_SHIFT 0 +#define CCM_CCGR173_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR173_TOG_CG_SHIFT))&CCM_CCGR173_TOG_CG_MASK) +/* CCGR174 Bit Fields */ +#define CCM_CCGR174_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR174_CG_SHIFT 0 +#define CCM_CCGR174_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_CG_SHIFT))&CCM_CCGR174_CG_MASK) +/* CCGR174_SET Bit Fields */ +#define CCM_CCGR174_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR174_SET_CG_SHIFT 0 +#define CCM_CCGR174_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_SET_CG_SHIFT))&CCM_CCGR174_SET_CG_MASK) +/* CCGR174_CLR Bit Fields */ +#define CCM_CCGR174_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR174_CLR_CG_SHIFT 0 +#define CCM_CCGR174_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_CLR_CG_SHIFT))&CCM_CCGR174_CLR_CG_MASK) +/* CCGR174_TOG Bit Fields */ +#define CCM_CCGR174_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR174_TOG_CG_SHIFT 0 +#define CCM_CCGR174_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR174_TOG_CG_SHIFT))&CCM_CCGR174_TOG_CG_MASK) +/* CCGR175 Bit Fields */ +#define CCM_CCGR175_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR175_CG_SHIFT 0 +#define CCM_CCGR175_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_CG_SHIFT))&CCM_CCGR175_CG_MASK) +/* CCGR175_SET Bit Fields */ +#define CCM_CCGR175_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR175_SET_CG_SHIFT 0 +#define CCM_CCGR175_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_SET_CG_SHIFT))&CCM_CCGR175_SET_CG_MASK) +/* CCGR175_CLR Bit Fields */ +#define CCM_CCGR175_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR175_CLR_CG_SHIFT 0 +#define CCM_CCGR175_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_CLR_CG_SHIFT))&CCM_CCGR175_CLR_CG_MASK) +/* CCGR175_TOG Bit Fields */ +#define CCM_CCGR175_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR175_TOG_CG_SHIFT 0 +#define CCM_CCGR175_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR175_TOG_CG_SHIFT))&CCM_CCGR175_TOG_CG_MASK) +/* CCGR176 Bit Fields */ +#define CCM_CCGR176_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR176_CG_SHIFT 0 +#define CCM_CCGR176_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_CG_SHIFT))&CCM_CCGR176_CG_MASK) +/* CCGR176_SET Bit Fields */ +#define CCM_CCGR176_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR176_SET_CG_SHIFT 0 +#define CCM_CCGR176_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_SET_CG_SHIFT))&CCM_CCGR176_SET_CG_MASK) +/* CCGR176_CLR Bit Fields */ +#define CCM_CCGR176_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR176_CLR_CG_SHIFT 0 +#define CCM_CCGR176_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_CLR_CG_SHIFT))&CCM_CCGR176_CLR_CG_MASK) +/* CCGR176_TOG Bit Fields */ +#define CCM_CCGR176_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR176_TOG_CG_SHIFT 0 +#define CCM_CCGR176_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR176_TOG_CG_SHIFT))&CCM_CCGR176_TOG_CG_MASK) +/* CCGR177 Bit Fields */ +#define CCM_CCGR177_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR177_CG_SHIFT 0 +#define CCM_CCGR177_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_CG_SHIFT))&CCM_CCGR177_CG_MASK) +/* CCGR177_SET Bit Fields */ +#define CCM_CCGR177_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR177_SET_CG_SHIFT 0 +#define CCM_CCGR177_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_SET_CG_SHIFT))&CCM_CCGR177_SET_CG_MASK) +/* CCGR177_CLR Bit Fields */ +#define CCM_CCGR177_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR177_CLR_CG_SHIFT 0 +#define CCM_CCGR177_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_CLR_CG_SHIFT))&CCM_CCGR177_CLR_CG_MASK) +/* CCGR177_TOG Bit Fields */ +#define CCM_CCGR177_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR177_TOG_CG_SHIFT 0 +#define CCM_CCGR177_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR177_TOG_CG_SHIFT))&CCM_CCGR177_TOG_CG_MASK) +/* CCGR178 Bit Fields */ +#define CCM_CCGR178_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR178_CG_SHIFT 0 +#define CCM_CCGR178_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_CG_SHIFT))&CCM_CCGR178_CG_MASK) +/* CCGR178_SET Bit Fields */ +#define CCM_CCGR178_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR178_SET_CG_SHIFT 0 +#define CCM_CCGR178_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_SET_CG_SHIFT))&CCM_CCGR178_SET_CG_MASK) +/* CCGR178_CLR Bit Fields */ +#define CCM_CCGR178_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR178_CLR_CG_SHIFT 0 +#define CCM_CCGR178_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_CLR_CG_SHIFT))&CCM_CCGR178_CLR_CG_MASK) +/* CCGR178_TOG Bit Fields */ +#define CCM_CCGR178_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR178_TOG_CG_SHIFT 0 +#define CCM_CCGR178_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR178_TOG_CG_SHIFT))&CCM_CCGR178_TOG_CG_MASK) +/* CCGR179 Bit Fields */ +#define CCM_CCGR179_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR179_CG_SHIFT 0 +#define CCM_CCGR179_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_CG_SHIFT))&CCM_CCGR179_CG_MASK) +/* CCGR179_SET Bit Fields */ +#define CCM_CCGR179_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR179_SET_CG_SHIFT 0 +#define CCM_CCGR179_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_SET_CG_SHIFT))&CCM_CCGR179_SET_CG_MASK) +/* CCGR179_CLR Bit Fields */ +#define CCM_CCGR179_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR179_CLR_CG_SHIFT 0 +#define CCM_CCGR179_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_CLR_CG_SHIFT))&CCM_CCGR179_CLR_CG_MASK) +/* CCGR179_TOG Bit Fields */ +#define CCM_CCGR179_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR179_TOG_CG_SHIFT 0 +#define CCM_CCGR179_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR179_TOG_CG_SHIFT))&CCM_CCGR179_TOG_CG_MASK) +/* CCGR180 Bit Fields */ +#define CCM_CCGR180_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR180_CG_SHIFT 0 +#define CCM_CCGR180_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_CG_SHIFT))&CCM_CCGR180_CG_MASK) +/* CCGR180_SET Bit Fields */ +#define CCM_CCGR180_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR180_SET_CG_SHIFT 0 +#define CCM_CCGR180_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_SET_CG_SHIFT))&CCM_CCGR180_SET_CG_MASK) +/* CCGR180_CLR Bit Fields */ +#define CCM_CCGR180_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR180_CLR_CG_SHIFT 0 +#define CCM_CCGR180_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_CLR_CG_SHIFT))&CCM_CCGR180_CLR_CG_MASK) +/* CCGR180_TOG Bit Fields */ +#define CCM_CCGR180_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR180_TOG_CG_SHIFT 0 +#define CCM_CCGR180_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR180_TOG_CG_SHIFT))&CCM_CCGR180_TOG_CG_MASK) +/* CCGR181 Bit Fields */ +#define CCM_CCGR181_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR181_CG_SHIFT 0 +#define CCM_CCGR181_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_CG_SHIFT))&CCM_CCGR181_CG_MASK) +/* CCGR181_SET Bit Fields */ +#define CCM_CCGR181_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR181_SET_CG_SHIFT 0 +#define CCM_CCGR181_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_SET_CG_SHIFT))&CCM_CCGR181_SET_CG_MASK) +/* CCGR181_CLR Bit Fields */ +#define CCM_CCGR181_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR181_CLR_CG_SHIFT 0 +#define CCM_CCGR181_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_CLR_CG_SHIFT))&CCM_CCGR181_CLR_CG_MASK) +/* CCGR181_TOG Bit Fields */ +#define CCM_CCGR181_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR181_TOG_CG_SHIFT 0 +#define CCM_CCGR181_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR181_TOG_CG_SHIFT))&CCM_CCGR181_TOG_CG_MASK) +/* CCGR182 Bit Fields */ +#define CCM_CCGR182_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR182_CG_SHIFT 0 +#define CCM_CCGR182_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_CG_SHIFT))&CCM_CCGR182_CG_MASK) +/* CCGR182_SET Bit Fields */ +#define CCM_CCGR182_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR182_SET_CG_SHIFT 0 +#define CCM_CCGR182_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_SET_CG_SHIFT))&CCM_CCGR182_SET_CG_MASK) +/* CCGR182_CLR Bit Fields */ +#define CCM_CCGR182_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR182_CLR_CG_SHIFT 0 +#define CCM_CCGR182_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_CLR_CG_SHIFT))&CCM_CCGR182_CLR_CG_MASK) +/* CCGR182_TOG Bit Fields */ +#define CCM_CCGR182_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR182_TOG_CG_SHIFT 0 +#define CCM_CCGR182_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR182_TOG_CG_SHIFT))&CCM_CCGR182_TOG_CG_MASK) +/* CCGR183 Bit Fields */ +#define CCM_CCGR183_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR183_CG_SHIFT 0 +#define CCM_CCGR183_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_CG_SHIFT))&CCM_CCGR183_CG_MASK) +/* CCGR183_SET Bit Fields */ +#define CCM_CCGR183_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR183_SET_CG_SHIFT 0 +#define CCM_CCGR183_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_SET_CG_SHIFT))&CCM_CCGR183_SET_CG_MASK) +/* CCGR183_CLR Bit Fields */ +#define CCM_CCGR183_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR183_CLR_CG_SHIFT 0 +#define CCM_CCGR183_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_CLR_CG_SHIFT))&CCM_CCGR183_CLR_CG_MASK) +/* CCGR183_TOG Bit Fields */ +#define CCM_CCGR183_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR183_TOG_CG_SHIFT 0 +#define CCM_CCGR183_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR183_TOG_CG_SHIFT))&CCM_CCGR183_TOG_CG_MASK) +/* CCGR184 Bit Fields */ +#define CCM_CCGR184_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR184_CG_SHIFT 0 +#define CCM_CCGR184_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_CG_SHIFT))&CCM_CCGR184_CG_MASK) +/* CCGR184_SET Bit Fields */ +#define CCM_CCGR184_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR184_SET_CG_SHIFT 0 +#define CCM_CCGR184_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_SET_CG_SHIFT))&CCM_CCGR184_SET_CG_MASK) +/* CCGR184_CLR Bit Fields */ +#define CCM_CCGR184_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR184_CLR_CG_SHIFT 0 +#define CCM_CCGR184_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_CLR_CG_SHIFT))&CCM_CCGR184_CLR_CG_MASK) +/* CCGR184_TOG Bit Fields */ +#define CCM_CCGR184_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR184_TOG_CG_SHIFT 0 +#define CCM_CCGR184_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR184_TOG_CG_SHIFT))&CCM_CCGR184_TOG_CG_MASK) +/* CCGR185 Bit Fields */ +#define CCM_CCGR185_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR185_CG_SHIFT 0 +#define CCM_CCGR185_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_CG_SHIFT))&CCM_CCGR185_CG_MASK) +/* CCGR185_SET Bit Fields */ +#define CCM_CCGR185_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR185_SET_CG_SHIFT 0 +#define CCM_CCGR185_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_SET_CG_SHIFT))&CCM_CCGR185_SET_CG_MASK) +/* CCGR185_CLR Bit Fields */ +#define CCM_CCGR185_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR185_CLR_CG_SHIFT 0 +#define CCM_CCGR185_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_CLR_CG_SHIFT))&CCM_CCGR185_CLR_CG_MASK) +/* CCGR185_TOG Bit Fields */ +#define CCM_CCGR185_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR185_TOG_CG_SHIFT 0 +#define CCM_CCGR185_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR185_TOG_CG_SHIFT))&CCM_CCGR185_TOG_CG_MASK) +/* CCGR186 Bit Fields */ +#define CCM_CCGR186_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR186_CG_SHIFT 0 +#define CCM_CCGR186_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_CG_SHIFT))&CCM_CCGR186_CG_MASK) +/* CCGR186_SET Bit Fields */ +#define CCM_CCGR186_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR186_SET_CG_SHIFT 0 +#define CCM_CCGR186_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_SET_CG_SHIFT))&CCM_CCGR186_SET_CG_MASK) +/* CCGR186_CLR Bit Fields */ +#define CCM_CCGR186_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR186_CLR_CG_SHIFT 0 +#define CCM_CCGR186_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_CLR_CG_SHIFT))&CCM_CCGR186_CLR_CG_MASK) +/* CCGR186_TOG Bit Fields */ +#define CCM_CCGR186_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR186_TOG_CG_SHIFT 0 +#define CCM_CCGR186_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR186_TOG_CG_SHIFT))&CCM_CCGR186_TOG_CG_MASK) +/* CCGR187 Bit Fields */ +#define CCM_CCGR187_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR187_CG_SHIFT 0 +#define CCM_CCGR187_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_CG_SHIFT))&CCM_CCGR187_CG_MASK) +/* CCGR187_SET Bit Fields */ +#define CCM_CCGR187_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR187_SET_CG_SHIFT 0 +#define CCM_CCGR187_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_SET_CG_SHIFT))&CCM_CCGR187_SET_CG_MASK) +/* CCGR187_CLR Bit Fields */ +#define CCM_CCGR187_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR187_CLR_CG_SHIFT 0 +#define CCM_CCGR187_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_CLR_CG_SHIFT))&CCM_CCGR187_CLR_CG_MASK) +/* CCGR187_TOG Bit Fields */ +#define CCM_CCGR187_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR187_TOG_CG_SHIFT 0 +#define CCM_CCGR187_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR187_TOG_CG_SHIFT))&CCM_CCGR187_TOG_CG_MASK) +/* CCGR188 Bit Fields */ +#define CCM_CCGR188_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR188_CG_SHIFT 0 +#define CCM_CCGR188_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_CG_SHIFT))&CCM_CCGR188_CG_MASK) +/* CCGR188_SET Bit Fields */ +#define CCM_CCGR188_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR188_SET_CG_SHIFT 0 +#define CCM_CCGR188_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_SET_CG_SHIFT))&CCM_CCGR188_SET_CG_MASK) +/* CCGR188_CLR Bit Fields */ +#define CCM_CCGR188_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR188_CLR_CG_SHIFT 0 +#define CCM_CCGR188_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_CLR_CG_SHIFT))&CCM_CCGR188_CLR_CG_MASK) +/* CCGR188_TOG Bit Fields */ +#define CCM_CCGR188_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR188_TOG_CG_SHIFT 0 +#define CCM_CCGR188_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR188_TOG_CG_SHIFT))&CCM_CCGR188_TOG_CG_MASK) +/* CCGR189 Bit Fields */ +#define CCM_CCGR189_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR189_CG_SHIFT 0 +#define CCM_CCGR189_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_CG_SHIFT))&CCM_CCGR189_CG_MASK) +/* CCGR189_SET Bit Fields */ +#define CCM_CCGR189_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR189_SET_CG_SHIFT 0 +#define CCM_CCGR189_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_SET_CG_SHIFT))&CCM_CCGR189_SET_CG_MASK) +/* CCGR189_CLR Bit Fields */ +#define CCM_CCGR189_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR189_CLR_CG_SHIFT 0 +#define CCM_CCGR189_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_CLR_CG_SHIFT))&CCM_CCGR189_CLR_CG_MASK) +/* CCGR189_TOG Bit Fields */ +#define CCM_CCGR189_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR189_TOG_CG_SHIFT 0 +#define CCM_CCGR189_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR189_TOG_CG_SHIFT))&CCM_CCGR189_TOG_CG_MASK) +/* CCGR190 Bit Fields */ +#define CCM_CCGR190_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR190_CG_SHIFT 0 +#define CCM_CCGR190_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_CG_SHIFT))&CCM_CCGR190_CG_MASK) +/* CCGR190_SET Bit Fields */ +#define CCM_CCGR190_SET_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR190_SET_CG_SHIFT 0 +#define CCM_CCGR190_SET_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_SET_CG_SHIFT))&CCM_CCGR190_SET_CG_MASK) +/* CCGR190_CLR Bit Fields */ +#define CCM_CCGR190_CLR_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR190_CLR_CG_SHIFT 0 +#define CCM_CCGR190_CLR_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_CLR_CG_SHIFT))&CCM_CCGR190_CLR_CG_MASK) +/* CCGR190_TOG Bit Fields */ +#define CCM_CCGR190_TOG_CG_MASK 0xFFFFFFFFu +#define CCM_CCGR190_TOG_CG_SHIFT 0 +#define CCM_CCGR190_TOG_CG(x) (((uint32_t)(((uint32_t)(x))<<CCM_CCGR190_TOG_CG_SHIFT))&CCM_CCGR190_TOG_CG_MASK) +/* TARGET_ROOT0 Bit Fields */ +#define CCM_TARGET_ROOT0_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT0_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT0_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_POST_PODF_MASK) +#define CCM_TARGET_ROOT0_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT0_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT0_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT0_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT0_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT0_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT0_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT0_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT0_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT0_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_PRE_PODF_MASK) +#define CCM_TARGET_ROOT0_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT0_MUX_SHIFT 24 +#define CCM_TARGET_ROOT0_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_MUX_SHIFT))&CCM_TARGET_ROOT0_MUX_MASK) +#define CCM_TARGET_ROOT0_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT0_ENABLE_SHIFT 28 +/* TARGET_ROOT0_SET Bit Fields */ +#define CCM_TARGET_ROOT0_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT0_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT0_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT0_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT0_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT0_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT0_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT0_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT0_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT0_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT0_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT0_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT0_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT0_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT0_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT0_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_SET_MUX_SHIFT))&CCM_TARGET_ROOT0_SET_MUX_MASK) +#define CCM_TARGET_ROOT0_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT0_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT0_CLR Bit Fields */ +#define CCM_TARGET_ROOT0_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT0_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT0_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT0_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT0_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT0_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT0_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT0_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT0_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT0_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT0_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT0_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT0_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_CLR_MUX_SHIFT))&CCM_TARGET_ROOT0_CLR_MUX_MASK) +#define CCM_TARGET_ROOT0_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT0_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT0_TOG Bit Fields */ +#define CCM_TARGET_ROOT0_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT0_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT0_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT0_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT0_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT0_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT0_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT0_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT0_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT0_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT0_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT0_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT0_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT0_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT0_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT0_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT0_TOG_MUX_SHIFT))&CCM_TARGET_ROOT0_TOG_MUX_MASK) +#define CCM_TARGET_ROOT0_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT0_TOG_ENABLE_SHIFT 28 +/* POST0 Bit Fields */ +#define CCM_POST0_POST_PODF_MASK 0x3Fu +#define CCM_POST0_POST_PODF_SHIFT 0 +#define CCM_POST0_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST0_POST_PODF_SHIFT))&CCM_POST0_POST_PODF_MASK) +#define CCM_POST0_BUSY1_MASK 0x80u +#define CCM_POST0_BUSY1_SHIFT 7 +#define CCM_POST0_AUTO_PODF_MASK 0x700u +#define CCM_POST0_AUTO_PODF_SHIFT 8 +#define CCM_POST0_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST0_AUTO_PODF_SHIFT))&CCM_POST0_AUTO_PODF_MASK) +#define CCM_POST0_AUTO_EN_MASK 0x1000u +#define CCM_POST0_AUTO_EN_SHIFT 12 +#define CCM_POST0_SLOW_MASK 0x8000u +#define CCM_POST0_SLOW_SHIFT 15 +#define CCM_POST0_SELECT_MASK 0x10000000u +#define CCM_POST0_SELECT_SHIFT 28 +#define CCM_POST0_BUSY2_MASK 0x80000000u +#define CCM_POST0_BUSY2_SHIFT 31 +/* POST_ROOT0_SET Bit Fields */ +#define CCM_POST_ROOT0_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT0_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT0_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_SET_POST_PODF_SHIFT))&CCM_POST_ROOT0_SET_POST_PODF_MASK) +#define CCM_POST_ROOT0_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT0_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT0_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT0_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT0_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT0_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT0_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT0_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT0_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT0_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT0_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT0_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT0_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT0_SET_BUSY2_SHIFT 31 +/* POST_ROOT0_CLR Bit Fields */ +#define CCM_POST_ROOT0_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT0_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT0_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT0_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT0_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT0_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT0_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT0_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT0_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT0_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT0_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT0_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT0_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT0_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT0_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT0_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT0_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT0_CLR_BUSY2_SHIFT 31 +/* POST_ROOT0_TOG Bit Fields */ +#define CCM_POST_ROOT0_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT0_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT0_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT0_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT0_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT0_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT0_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT0_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT0_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT0_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT0_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT0_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT0_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT0_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT0_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT0_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT0_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT0_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT0_TOG_BUSY2_SHIFT 31 +/* PRE0 Bit Fields */ +#define CCM_PRE0_PRE_PODF_B_MASK 0x7u +#define CCM_PRE0_PRE_PODF_B_SHIFT 0 +#define CCM_PRE0_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_PRE_PODF_B_SHIFT))&CCM_PRE0_PRE_PODF_B_MASK) +#define CCM_PRE0_BUSY0_MASK 0x8u +#define CCM_PRE0_BUSY0_SHIFT 3 +#define CCM_PRE0_MUX_B_MASK 0x700u +#define CCM_PRE0_MUX_B_SHIFT 8 +#define CCM_PRE0_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_MUX_B_SHIFT))&CCM_PRE0_MUX_B_MASK) +#define CCM_PRE0_EN_B_MASK 0x1000u +#define CCM_PRE0_EN_B_SHIFT 12 +#define CCM_PRE0_BUSY1_MASK 0x8000u +#define CCM_PRE0_BUSY1_SHIFT 15 +#define CCM_PRE0_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE0_PRE_PODF_A_SHIFT 16 +#define CCM_PRE0_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_PRE_PODF_A_SHIFT))&CCM_PRE0_PRE_PODF_A_MASK) +#define CCM_PRE0_BUSY3_MASK 0x80000u +#define CCM_PRE0_BUSY3_SHIFT 19 +#define CCM_PRE0_MUX_A_MASK 0x7000000u +#define CCM_PRE0_MUX_A_SHIFT 24 +#define CCM_PRE0_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE0_MUX_A_SHIFT))&CCM_PRE0_MUX_A_MASK) +#define CCM_PRE0_EN_A_MASK 0x10000000u +#define CCM_PRE0_EN_A_SHIFT 28 +#define CCM_PRE0_BUSY4_MASK 0x80000000u +#define CCM_PRE0_BUSY4_SHIFT 31 +/* PRE_ROOT0_SET Bit Fields */ +#define CCM_PRE_ROOT0_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT0_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT0_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT0_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT0_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT0_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT0_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT0_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT0_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_MUX_B_SHIFT))&CCM_PRE_ROOT0_SET_MUX_B_MASK) +#define CCM_PRE_ROOT0_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT0_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT0_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT0_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT0_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT0_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT0_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT0_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT0_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT0_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT0_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT0_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT0_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_SET_MUX_A_SHIFT))&CCM_PRE_ROOT0_SET_MUX_A_MASK) +#define CCM_PRE_ROOT0_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT0_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT0_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT0_SET_BUSY4_SHIFT 31 +/* PRE_ROOT0_CLR Bit Fields */ +#define CCM_PRE_ROOT0_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT0_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT0_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT0_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT0_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT0_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT0_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT0_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT0_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT0_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT0_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT0_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT0_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT0_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT0_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT0_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT0_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT0_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT0_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT0_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT0_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT0_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT0_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT0_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT0_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT0_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT0_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT0_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT0_TOG Bit Fields */ +#define CCM_PRE_ROOT0_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT0_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT0_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT0_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT0_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT0_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT0_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT0_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT0_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT0_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT0_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT0_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT0_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT0_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT0_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT0_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT0_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT0_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT0_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT0_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT0_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT0_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT0_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT0_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT0_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT0_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT0_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT0_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT0_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL0 Bit Fields */ +#define CCM_ACCESS_CTRL0_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL0_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL0_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL0_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL0_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL0_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL0_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL0_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL0_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL0_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL0_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL0_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL0_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL0_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL0_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL0_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL0_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL0_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL0_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL0_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL0_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL0_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL0_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL0_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL0_LOCK_SHIFT 31 +/* ACCESS_CTRL0_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL0_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL0_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL0_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL0_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL0_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL0_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL0_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL0_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL0_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL0_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL0_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL0_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL0_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL0_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL0_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL0_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL0_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL0_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT1 Bit Fields */ +#define CCM_TARGET_ROOT1_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT1_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT1_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_POST_PODF_MASK) +#define CCM_TARGET_ROOT1_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT1_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT1_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT1_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT1_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT1_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT1_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT1_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT1_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT1_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_PRE_PODF_MASK) +#define CCM_TARGET_ROOT1_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT1_MUX_SHIFT 24 +#define CCM_TARGET_ROOT1_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_MUX_SHIFT))&CCM_TARGET_ROOT1_MUX_MASK) +#define CCM_TARGET_ROOT1_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT1_ENABLE_SHIFT 28 +/* TARGET_ROOT1_SET Bit Fields */ +#define CCM_TARGET_ROOT1_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT1_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT1_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT1_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT1_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT1_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT1_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT1_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT1_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT1_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT1_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT1_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT1_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT1_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT1_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT1_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_SET_MUX_SHIFT))&CCM_TARGET_ROOT1_SET_MUX_MASK) +#define CCM_TARGET_ROOT1_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT1_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT1_CLR Bit Fields */ +#define CCM_TARGET_ROOT1_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT1_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT1_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT1_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT1_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT1_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT1_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT1_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT1_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT1_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT1_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT1_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT1_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_CLR_MUX_SHIFT))&CCM_TARGET_ROOT1_CLR_MUX_MASK) +#define CCM_TARGET_ROOT1_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT1_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT1_TOG Bit Fields */ +#define CCM_TARGET_ROOT1_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT1_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT1_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT1_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT1_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT1_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT1_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT1_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT1_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT1_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT1_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT1_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT1_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT1_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT1_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT1_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT1_TOG_MUX_SHIFT))&CCM_TARGET_ROOT1_TOG_MUX_MASK) +#define CCM_TARGET_ROOT1_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT1_TOG_ENABLE_SHIFT 28 +/* POST1 Bit Fields */ +#define CCM_POST1_POST_PODF_MASK 0x3Fu +#define CCM_POST1_POST_PODF_SHIFT 0 +#define CCM_POST1_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST1_POST_PODF_SHIFT))&CCM_POST1_POST_PODF_MASK) +#define CCM_POST1_BUSY1_MASK 0x80u +#define CCM_POST1_BUSY1_SHIFT 7 +#define CCM_POST1_AUTO_PODF_MASK 0x700u +#define CCM_POST1_AUTO_PODF_SHIFT 8 +#define CCM_POST1_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST1_AUTO_PODF_SHIFT))&CCM_POST1_AUTO_PODF_MASK) +#define CCM_POST1_AUTO_EN_MASK 0x1000u +#define CCM_POST1_AUTO_EN_SHIFT 12 +#define CCM_POST1_SLOW_MASK 0x8000u +#define CCM_POST1_SLOW_SHIFT 15 +#define CCM_POST1_SELECT_MASK 0x10000000u +#define CCM_POST1_SELECT_SHIFT 28 +#define CCM_POST1_BUSY2_MASK 0x80000000u +#define CCM_POST1_BUSY2_SHIFT 31 +/* POST_ROOT1_SET Bit Fields */ +#define CCM_POST_ROOT1_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT1_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT1_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_SET_POST_PODF_SHIFT))&CCM_POST_ROOT1_SET_POST_PODF_MASK) +#define CCM_POST_ROOT1_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT1_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT1_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT1_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT1_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT1_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT1_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT1_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT1_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT1_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT1_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT1_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT1_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT1_SET_BUSY2_SHIFT 31 +/* POST_ROOT1_CLR Bit Fields */ +#define CCM_POST_ROOT1_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT1_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT1_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT1_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT1_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT1_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT1_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT1_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT1_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT1_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT1_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT1_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT1_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT1_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT1_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT1_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT1_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT1_CLR_BUSY2_SHIFT 31 +/* POST_ROOT1_TOG Bit Fields */ +#define CCM_POST_ROOT1_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT1_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT1_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT1_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT1_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT1_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT1_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT1_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT1_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT1_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT1_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT1_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT1_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT1_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT1_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT1_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT1_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT1_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT1_TOG_BUSY2_SHIFT 31 +/* PRE1 Bit Fields */ +#define CCM_PRE1_PRE_PODF_B_MASK 0x7u +#define CCM_PRE1_PRE_PODF_B_SHIFT 0 +#define CCM_PRE1_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_PRE_PODF_B_SHIFT))&CCM_PRE1_PRE_PODF_B_MASK) +#define CCM_PRE1_BUSY0_MASK 0x8u +#define CCM_PRE1_BUSY0_SHIFT 3 +#define CCM_PRE1_MUX_B_MASK 0x700u +#define CCM_PRE1_MUX_B_SHIFT 8 +#define CCM_PRE1_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_MUX_B_SHIFT))&CCM_PRE1_MUX_B_MASK) +#define CCM_PRE1_EN_B_MASK 0x1000u +#define CCM_PRE1_EN_B_SHIFT 12 +#define CCM_PRE1_BUSY1_MASK 0x8000u +#define CCM_PRE1_BUSY1_SHIFT 15 +#define CCM_PRE1_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE1_PRE_PODF_A_SHIFT 16 +#define CCM_PRE1_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_PRE_PODF_A_SHIFT))&CCM_PRE1_PRE_PODF_A_MASK) +#define CCM_PRE1_BUSY3_MASK 0x80000u +#define CCM_PRE1_BUSY3_SHIFT 19 +#define CCM_PRE1_MUX_A_MASK 0x7000000u +#define CCM_PRE1_MUX_A_SHIFT 24 +#define CCM_PRE1_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE1_MUX_A_SHIFT))&CCM_PRE1_MUX_A_MASK) +#define CCM_PRE1_EN_A_MASK 0x10000000u +#define CCM_PRE1_EN_A_SHIFT 28 +#define CCM_PRE1_BUSY4_MASK 0x80000000u +#define CCM_PRE1_BUSY4_SHIFT 31 +/* PRE_ROOT1_SET Bit Fields */ +#define CCM_PRE_ROOT1_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT1_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT1_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT1_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT1_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT1_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT1_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT1_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT1_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_MUX_B_SHIFT))&CCM_PRE_ROOT1_SET_MUX_B_MASK) +#define CCM_PRE_ROOT1_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT1_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT1_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT1_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT1_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT1_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT1_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT1_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT1_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT1_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT1_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT1_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT1_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_SET_MUX_A_SHIFT))&CCM_PRE_ROOT1_SET_MUX_A_MASK) +#define CCM_PRE_ROOT1_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT1_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT1_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT1_SET_BUSY4_SHIFT 31 +/* PRE_ROOT1_CLR Bit Fields */ +#define CCM_PRE_ROOT1_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT1_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT1_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT1_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT1_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT1_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT1_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT1_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT1_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT1_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT1_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT1_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT1_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT1_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT1_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT1_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT1_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT1_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT1_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT1_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT1_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT1_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT1_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT1_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT1_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT1_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT1_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT1_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT1_TOG Bit Fields */ +#define CCM_PRE_ROOT1_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT1_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT1_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT1_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT1_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT1_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT1_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT1_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT1_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT1_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT1_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT1_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT1_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT1_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT1_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT1_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT1_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT1_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT1_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT1_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT1_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT1_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT1_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT1_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT1_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT1_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT1_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT1_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT1_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL1 Bit Fields */ +#define CCM_ACCESS_CTRL1_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL1_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL1_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL1_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL1_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL1_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL1_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL1_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL1_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL1_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL1_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL1_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL1_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL1_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL1_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL1_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL1_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL1_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL1_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL1_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL1_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL1_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL1_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL1_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL1_LOCK_SHIFT 31 +/* ACCESS_CTRL1_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL1_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL1_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL1_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL1_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL1_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL1_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL1_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL1_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL1_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL1_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL1_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL1_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL1_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL1_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL1_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL1_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL1_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL1_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT2 Bit Fields */ +#define CCM_TARGET_ROOT2_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT2_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT2_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_POST_PODF_MASK) +#define CCM_TARGET_ROOT2_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT2_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT2_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT2_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT2_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT2_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT2_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT2_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT2_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT2_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_PRE_PODF_MASK) +#define CCM_TARGET_ROOT2_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT2_MUX_SHIFT 24 +#define CCM_TARGET_ROOT2_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_MUX_SHIFT))&CCM_TARGET_ROOT2_MUX_MASK) +#define CCM_TARGET_ROOT2_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT2_ENABLE_SHIFT 28 +/* TARGET_ROOT2_SET Bit Fields */ +#define CCM_TARGET_ROOT2_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT2_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT2_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT2_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT2_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT2_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT2_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT2_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT2_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT2_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT2_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT2_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT2_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT2_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT2_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT2_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_SET_MUX_SHIFT))&CCM_TARGET_ROOT2_SET_MUX_MASK) +#define CCM_TARGET_ROOT2_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT2_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT2_CLR Bit Fields */ +#define CCM_TARGET_ROOT2_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT2_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT2_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT2_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT2_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT2_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT2_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT2_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT2_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT2_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT2_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT2_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT2_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_CLR_MUX_SHIFT))&CCM_TARGET_ROOT2_CLR_MUX_MASK) +#define CCM_TARGET_ROOT2_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT2_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT2_TOG Bit Fields */ +#define CCM_TARGET_ROOT2_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT2_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT2_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT2_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT2_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT2_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT2_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT2_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT2_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT2_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT2_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT2_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT2_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT2_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT2_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT2_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT2_TOG_MUX_SHIFT))&CCM_TARGET_ROOT2_TOG_MUX_MASK) +#define CCM_TARGET_ROOT2_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT2_TOG_ENABLE_SHIFT 28 +/* POST2 Bit Fields */ +#define CCM_POST2_POST_PODF_MASK 0x3Fu +#define CCM_POST2_POST_PODF_SHIFT 0 +#define CCM_POST2_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST2_POST_PODF_SHIFT))&CCM_POST2_POST_PODF_MASK) +#define CCM_POST2_BUSY1_MASK 0x80u +#define CCM_POST2_BUSY1_SHIFT 7 +#define CCM_POST2_AUTO_PODF_MASK 0x700u +#define CCM_POST2_AUTO_PODF_SHIFT 8 +#define CCM_POST2_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST2_AUTO_PODF_SHIFT))&CCM_POST2_AUTO_PODF_MASK) +#define CCM_POST2_AUTO_EN_MASK 0x1000u +#define CCM_POST2_AUTO_EN_SHIFT 12 +#define CCM_POST2_SLOW_MASK 0x8000u +#define CCM_POST2_SLOW_SHIFT 15 +#define CCM_POST2_SELECT_MASK 0x10000000u +#define CCM_POST2_SELECT_SHIFT 28 +#define CCM_POST2_BUSY2_MASK 0x80000000u +#define CCM_POST2_BUSY2_SHIFT 31 +/* POST_ROOT2_SET Bit Fields */ +#define CCM_POST_ROOT2_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT2_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT2_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_SET_POST_PODF_SHIFT))&CCM_POST_ROOT2_SET_POST_PODF_MASK) +#define CCM_POST_ROOT2_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT2_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT2_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT2_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT2_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT2_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT2_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT2_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT2_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT2_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT2_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT2_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT2_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT2_SET_BUSY2_SHIFT 31 +/* POST_ROOT2_CLR Bit Fields */ +#define CCM_POST_ROOT2_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT2_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT2_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT2_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT2_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT2_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT2_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT2_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT2_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT2_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT2_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT2_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT2_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT2_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT2_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT2_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT2_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT2_CLR_BUSY2_SHIFT 31 +/* POST_ROOT2_TOG Bit Fields */ +#define CCM_POST_ROOT2_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT2_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT2_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT2_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT2_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT2_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT2_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT2_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT2_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT2_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT2_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT2_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT2_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT2_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT2_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT2_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT2_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT2_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT2_TOG_BUSY2_SHIFT 31 +/* PRE2 Bit Fields */ +#define CCM_PRE2_PRE_PODF_B_MASK 0x7u +#define CCM_PRE2_PRE_PODF_B_SHIFT 0 +#define CCM_PRE2_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_PRE_PODF_B_SHIFT))&CCM_PRE2_PRE_PODF_B_MASK) +#define CCM_PRE2_BUSY0_MASK 0x8u +#define CCM_PRE2_BUSY0_SHIFT 3 +#define CCM_PRE2_MUX_B_MASK 0x700u +#define CCM_PRE2_MUX_B_SHIFT 8 +#define CCM_PRE2_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_MUX_B_SHIFT))&CCM_PRE2_MUX_B_MASK) +#define CCM_PRE2_EN_B_MASK 0x1000u +#define CCM_PRE2_EN_B_SHIFT 12 +#define CCM_PRE2_BUSY1_MASK 0x8000u +#define CCM_PRE2_BUSY1_SHIFT 15 +#define CCM_PRE2_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE2_PRE_PODF_A_SHIFT 16 +#define CCM_PRE2_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_PRE_PODF_A_SHIFT))&CCM_PRE2_PRE_PODF_A_MASK) +#define CCM_PRE2_BUSY3_MASK 0x80000u +#define CCM_PRE2_BUSY3_SHIFT 19 +#define CCM_PRE2_MUX_A_MASK 0x7000000u +#define CCM_PRE2_MUX_A_SHIFT 24 +#define CCM_PRE2_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE2_MUX_A_SHIFT))&CCM_PRE2_MUX_A_MASK) +#define CCM_PRE2_EN_A_MASK 0x10000000u +#define CCM_PRE2_EN_A_SHIFT 28 +#define CCM_PRE2_BUSY4_MASK 0x80000000u +#define CCM_PRE2_BUSY4_SHIFT 31 +/* PRE_ROOT2_SET Bit Fields */ +#define CCM_PRE_ROOT2_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT2_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT2_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT2_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT2_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT2_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT2_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT2_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT2_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_MUX_B_SHIFT))&CCM_PRE_ROOT2_SET_MUX_B_MASK) +#define CCM_PRE_ROOT2_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT2_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT2_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT2_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT2_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT2_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT2_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT2_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT2_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT2_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT2_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT2_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT2_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_SET_MUX_A_SHIFT))&CCM_PRE_ROOT2_SET_MUX_A_MASK) +#define CCM_PRE_ROOT2_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT2_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT2_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT2_SET_BUSY4_SHIFT 31 +/* PRE_ROOT2_CLR Bit Fields */ +#define CCM_PRE_ROOT2_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT2_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT2_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT2_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT2_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT2_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT2_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT2_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT2_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT2_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT2_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT2_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT2_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT2_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT2_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT2_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT2_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT2_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT2_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT2_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT2_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT2_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT2_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT2_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT2_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT2_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT2_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT2_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT2_TOG Bit Fields */ +#define CCM_PRE_ROOT2_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT2_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT2_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT2_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT2_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT2_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT2_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT2_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT2_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT2_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT2_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT2_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT2_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT2_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT2_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT2_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT2_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT2_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT2_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT2_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT2_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT2_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT2_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT2_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT2_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT2_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT2_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT2_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT2_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL2 Bit Fields */ +#define CCM_ACCESS_CTRL2_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL2_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL2_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL2_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL2_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL2_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL2_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL2_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL2_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL2_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL2_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL2_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL2_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL2_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL2_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL2_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL2_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL2_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL2_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL2_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL2_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL2_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL2_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL2_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL2_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL2_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL2_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL2_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL2_LOCK_SHIFT 31 +/* ACCESS_CTRL2_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL2_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL2_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL2_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL2_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL2_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL2_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL2_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL2_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL2_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL2_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL2_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL2_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL2_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL2_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL2_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL2_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL2_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL2_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT3 Bit Fields */ +#define CCM_TARGET_ROOT3_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT3_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT3_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_POST_PODF_MASK) +#define CCM_TARGET_ROOT3_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT3_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT3_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT3_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT3_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT3_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT3_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT3_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT3_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT3_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_PRE_PODF_MASK) +#define CCM_TARGET_ROOT3_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT3_MUX_SHIFT 24 +#define CCM_TARGET_ROOT3_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_MUX_SHIFT))&CCM_TARGET_ROOT3_MUX_MASK) +#define CCM_TARGET_ROOT3_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT3_ENABLE_SHIFT 28 +/* TARGET_ROOT3_SET Bit Fields */ +#define CCM_TARGET_ROOT3_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT3_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT3_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT3_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT3_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT3_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT3_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT3_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT3_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT3_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT3_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT3_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT3_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT3_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT3_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT3_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_SET_MUX_SHIFT))&CCM_TARGET_ROOT3_SET_MUX_MASK) +#define CCM_TARGET_ROOT3_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT3_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT3_CLR Bit Fields */ +#define CCM_TARGET_ROOT3_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT3_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT3_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT3_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT3_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT3_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT3_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT3_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT3_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT3_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT3_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT3_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT3_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_CLR_MUX_SHIFT))&CCM_TARGET_ROOT3_CLR_MUX_MASK) +#define CCM_TARGET_ROOT3_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT3_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT3_TOG Bit Fields */ +#define CCM_TARGET_ROOT3_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT3_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT3_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT3_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT3_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT3_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT3_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT3_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT3_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT3_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT3_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT3_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT3_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT3_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT3_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT3_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT3_TOG_MUX_SHIFT))&CCM_TARGET_ROOT3_TOG_MUX_MASK) +#define CCM_TARGET_ROOT3_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT3_TOG_ENABLE_SHIFT 28 +/* POST3 Bit Fields */ +#define CCM_POST3_POST_PODF_MASK 0x3Fu +#define CCM_POST3_POST_PODF_SHIFT 0 +#define CCM_POST3_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST3_POST_PODF_SHIFT))&CCM_POST3_POST_PODF_MASK) +#define CCM_POST3_BUSY1_MASK 0x80u +#define CCM_POST3_BUSY1_SHIFT 7 +#define CCM_POST3_AUTO_PODF_MASK 0x700u +#define CCM_POST3_AUTO_PODF_SHIFT 8 +#define CCM_POST3_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST3_AUTO_PODF_SHIFT))&CCM_POST3_AUTO_PODF_MASK) +#define CCM_POST3_AUTO_EN_MASK 0x1000u +#define CCM_POST3_AUTO_EN_SHIFT 12 +#define CCM_POST3_SLOW_MASK 0x8000u +#define CCM_POST3_SLOW_SHIFT 15 +#define CCM_POST3_SELECT_MASK 0x10000000u +#define CCM_POST3_SELECT_SHIFT 28 +#define CCM_POST3_BUSY2_MASK 0x80000000u +#define CCM_POST3_BUSY2_SHIFT 31 +/* POST_ROOT3_SET Bit Fields */ +#define CCM_POST_ROOT3_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT3_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT3_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_SET_POST_PODF_SHIFT))&CCM_POST_ROOT3_SET_POST_PODF_MASK) +#define CCM_POST_ROOT3_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT3_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT3_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT3_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT3_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT3_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT3_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT3_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT3_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT3_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT3_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT3_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT3_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT3_SET_BUSY2_SHIFT 31 +/* POST_ROOT3_CLR Bit Fields */ +#define CCM_POST_ROOT3_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT3_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT3_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT3_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT3_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT3_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT3_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT3_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT3_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT3_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT3_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT3_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT3_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT3_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT3_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT3_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT3_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT3_CLR_BUSY2_SHIFT 31 +/* POST_ROOT3_TOG Bit Fields */ +#define CCM_POST_ROOT3_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT3_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT3_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT3_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT3_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT3_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT3_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT3_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT3_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT3_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT3_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT3_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT3_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT3_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT3_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT3_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT3_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT3_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT3_TOG_BUSY2_SHIFT 31 +/* PRE3 Bit Fields */ +#define CCM_PRE3_PRE_PODF_B_MASK 0x7u +#define CCM_PRE3_PRE_PODF_B_SHIFT 0 +#define CCM_PRE3_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_PRE_PODF_B_SHIFT))&CCM_PRE3_PRE_PODF_B_MASK) +#define CCM_PRE3_BUSY0_MASK 0x8u +#define CCM_PRE3_BUSY0_SHIFT 3 +#define CCM_PRE3_MUX_B_MASK 0x700u +#define CCM_PRE3_MUX_B_SHIFT 8 +#define CCM_PRE3_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_MUX_B_SHIFT))&CCM_PRE3_MUX_B_MASK) +#define CCM_PRE3_EN_B_MASK 0x1000u +#define CCM_PRE3_EN_B_SHIFT 12 +#define CCM_PRE3_BUSY1_MASK 0x8000u +#define CCM_PRE3_BUSY1_SHIFT 15 +#define CCM_PRE3_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE3_PRE_PODF_A_SHIFT 16 +#define CCM_PRE3_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_PRE_PODF_A_SHIFT))&CCM_PRE3_PRE_PODF_A_MASK) +#define CCM_PRE3_BUSY3_MASK 0x80000u +#define CCM_PRE3_BUSY3_SHIFT 19 +#define CCM_PRE3_MUX_A_MASK 0x7000000u +#define CCM_PRE3_MUX_A_SHIFT 24 +#define CCM_PRE3_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE3_MUX_A_SHIFT))&CCM_PRE3_MUX_A_MASK) +#define CCM_PRE3_EN_A_MASK 0x10000000u +#define CCM_PRE3_EN_A_SHIFT 28 +#define CCM_PRE3_BUSY4_MASK 0x80000000u +#define CCM_PRE3_BUSY4_SHIFT 31 +/* PRE_ROOT3_SET Bit Fields */ +#define CCM_PRE_ROOT3_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT3_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT3_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT3_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT3_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT3_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT3_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT3_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT3_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_MUX_B_SHIFT))&CCM_PRE_ROOT3_SET_MUX_B_MASK) +#define CCM_PRE_ROOT3_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT3_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT3_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT3_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT3_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT3_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT3_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT3_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT3_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT3_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT3_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT3_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT3_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_SET_MUX_A_SHIFT))&CCM_PRE_ROOT3_SET_MUX_A_MASK) +#define CCM_PRE_ROOT3_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT3_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT3_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT3_SET_BUSY4_SHIFT 31 +/* PRE_ROOT3_CLR Bit Fields */ +#define CCM_PRE_ROOT3_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT3_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT3_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT3_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT3_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT3_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT3_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT3_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT3_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT3_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT3_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT3_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT3_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT3_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT3_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT3_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT3_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT3_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT3_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT3_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT3_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT3_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT3_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT3_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT3_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT3_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT3_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT3_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT3_TOG Bit Fields */ +#define CCM_PRE_ROOT3_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT3_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT3_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT3_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT3_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT3_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT3_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT3_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT3_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT3_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT3_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT3_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT3_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT3_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT3_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT3_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT3_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT3_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT3_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT3_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT3_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT3_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT3_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT3_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT3_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT3_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT3_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT3_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT3_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL3 Bit Fields */ +#define CCM_ACCESS_CTRL3_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL3_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL3_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL3_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL3_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL3_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL3_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL3_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL3_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL3_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL3_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL3_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL3_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL3_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL3_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL3_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL3_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL3_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL3_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL3_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL3_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL3_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL3_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL3_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL3_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL3_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL3_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL3_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL3_LOCK_SHIFT 31 +/* ACCESS_CTRL3_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL3_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL3_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL3_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL3_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL3_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL3_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL3_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL3_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL3_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL3_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL3_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL3_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL3_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL3_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL3_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL3_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL3_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL3_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT4 Bit Fields */ +#define CCM_TARGET_ROOT4_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT4_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT4_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_POST_PODF_MASK) +#define CCM_TARGET_ROOT4_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT4_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT4_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT4_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT4_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT4_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT4_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT4_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT4_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT4_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_PRE_PODF_MASK) +#define CCM_TARGET_ROOT4_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT4_MUX_SHIFT 24 +#define CCM_TARGET_ROOT4_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_MUX_SHIFT))&CCM_TARGET_ROOT4_MUX_MASK) +#define CCM_TARGET_ROOT4_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT4_ENABLE_SHIFT 28 +/* TARGET_ROOT4_SET Bit Fields */ +#define CCM_TARGET_ROOT4_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT4_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT4_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT4_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT4_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT4_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT4_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT4_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT4_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT4_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT4_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT4_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT4_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT4_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT4_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT4_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_SET_MUX_SHIFT))&CCM_TARGET_ROOT4_SET_MUX_MASK) +#define CCM_TARGET_ROOT4_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT4_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT4_CLR Bit Fields */ +#define CCM_TARGET_ROOT4_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT4_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT4_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT4_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT4_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT4_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT4_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT4_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT4_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT4_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT4_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT4_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT4_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_CLR_MUX_SHIFT))&CCM_TARGET_ROOT4_CLR_MUX_MASK) +#define CCM_TARGET_ROOT4_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT4_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT4_TOG Bit Fields */ +#define CCM_TARGET_ROOT4_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT4_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT4_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT4_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT4_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT4_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT4_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT4_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT4_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT4_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT4_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT4_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT4_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT4_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT4_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT4_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT4_TOG_MUX_SHIFT))&CCM_TARGET_ROOT4_TOG_MUX_MASK) +#define CCM_TARGET_ROOT4_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT4_TOG_ENABLE_SHIFT 28 +/* POST4 Bit Fields */ +#define CCM_POST4_POST_PODF_MASK 0x3Fu +#define CCM_POST4_POST_PODF_SHIFT 0 +#define CCM_POST4_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST4_POST_PODF_SHIFT))&CCM_POST4_POST_PODF_MASK) +#define CCM_POST4_BUSY1_MASK 0x80u +#define CCM_POST4_BUSY1_SHIFT 7 +#define CCM_POST4_AUTO_PODF_MASK 0x700u +#define CCM_POST4_AUTO_PODF_SHIFT 8 +#define CCM_POST4_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST4_AUTO_PODF_SHIFT))&CCM_POST4_AUTO_PODF_MASK) +#define CCM_POST4_AUTO_EN_MASK 0x1000u +#define CCM_POST4_AUTO_EN_SHIFT 12 +#define CCM_POST4_SLOW_MASK 0x8000u +#define CCM_POST4_SLOW_SHIFT 15 +#define CCM_POST4_SELECT_MASK 0x10000000u +#define CCM_POST4_SELECT_SHIFT 28 +#define CCM_POST4_BUSY2_MASK 0x80000000u +#define CCM_POST4_BUSY2_SHIFT 31 +/* POST_ROOT4_SET Bit Fields */ +#define CCM_POST_ROOT4_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT4_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT4_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_SET_POST_PODF_SHIFT))&CCM_POST_ROOT4_SET_POST_PODF_MASK) +#define CCM_POST_ROOT4_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT4_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT4_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT4_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT4_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT4_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT4_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT4_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT4_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT4_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT4_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT4_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT4_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT4_SET_BUSY2_SHIFT 31 +/* POST_ROOT4_CLR Bit Fields */ +#define CCM_POST_ROOT4_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT4_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT4_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT4_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT4_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT4_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT4_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT4_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT4_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT4_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT4_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT4_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT4_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT4_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT4_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT4_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT4_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT4_CLR_BUSY2_SHIFT 31 +/* POST_ROOT4_TOG Bit Fields */ +#define CCM_POST_ROOT4_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT4_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT4_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT4_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT4_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT4_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT4_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT4_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT4_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT4_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT4_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT4_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT4_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT4_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT4_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT4_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT4_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT4_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT4_TOG_BUSY2_SHIFT 31 +/* PRE4 Bit Fields */ +#define CCM_PRE4_PRE_PODF_B_MASK 0x7u +#define CCM_PRE4_PRE_PODF_B_SHIFT 0 +#define CCM_PRE4_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_PRE_PODF_B_SHIFT))&CCM_PRE4_PRE_PODF_B_MASK) +#define CCM_PRE4_BUSY0_MASK 0x8u +#define CCM_PRE4_BUSY0_SHIFT 3 +#define CCM_PRE4_MUX_B_MASK 0x700u +#define CCM_PRE4_MUX_B_SHIFT 8 +#define CCM_PRE4_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_MUX_B_SHIFT))&CCM_PRE4_MUX_B_MASK) +#define CCM_PRE4_EN_B_MASK 0x1000u +#define CCM_PRE4_EN_B_SHIFT 12 +#define CCM_PRE4_BUSY1_MASK 0x8000u +#define CCM_PRE4_BUSY1_SHIFT 15 +#define CCM_PRE4_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE4_PRE_PODF_A_SHIFT 16 +#define CCM_PRE4_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_PRE_PODF_A_SHIFT))&CCM_PRE4_PRE_PODF_A_MASK) +#define CCM_PRE4_BUSY3_MASK 0x80000u +#define CCM_PRE4_BUSY3_SHIFT 19 +#define CCM_PRE4_MUX_A_MASK 0x7000000u +#define CCM_PRE4_MUX_A_SHIFT 24 +#define CCM_PRE4_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE4_MUX_A_SHIFT))&CCM_PRE4_MUX_A_MASK) +#define CCM_PRE4_EN_A_MASK 0x10000000u +#define CCM_PRE4_EN_A_SHIFT 28 +#define CCM_PRE4_BUSY4_MASK 0x80000000u +#define CCM_PRE4_BUSY4_SHIFT 31 +/* PRE_ROOT4_SET Bit Fields */ +#define CCM_PRE_ROOT4_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT4_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT4_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT4_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT4_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT4_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT4_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT4_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT4_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_MUX_B_SHIFT))&CCM_PRE_ROOT4_SET_MUX_B_MASK) +#define CCM_PRE_ROOT4_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT4_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT4_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT4_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT4_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT4_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT4_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT4_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT4_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT4_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT4_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT4_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT4_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_SET_MUX_A_SHIFT))&CCM_PRE_ROOT4_SET_MUX_A_MASK) +#define CCM_PRE_ROOT4_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT4_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT4_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT4_SET_BUSY4_SHIFT 31 +/* PRE_ROOT4_CLR Bit Fields */ +#define CCM_PRE_ROOT4_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT4_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT4_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT4_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT4_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT4_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT4_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT4_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT4_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT4_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT4_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT4_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT4_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT4_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT4_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT4_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT4_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT4_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT4_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT4_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT4_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT4_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT4_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT4_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT4_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT4_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT4_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT4_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT4_TOG Bit Fields */ +#define CCM_PRE_ROOT4_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT4_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT4_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT4_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT4_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT4_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT4_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT4_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT4_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT4_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT4_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT4_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT4_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT4_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT4_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT4_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT4_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT4_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT4_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT4_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT4_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT4_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT4_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT4_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT4_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT4_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT4_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT4_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT4_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL4 Bit Fields */ +#define CCM_ACCESS_CTRL4_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL4_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL4_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL4_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL4_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL4_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL4_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL4_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL4_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL4_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL4_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL4_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL4_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL4_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL4_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL4_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL4_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL4_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL4_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL4_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL4_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL4_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL4_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL4_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL4_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL4_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL4_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL4_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL4_LOCK_SHIFT 31 +/* ACCESS_CTRL4_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL4_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL4_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL4_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL4_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL4_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL4_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL4_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL4_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL4_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL4_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL4_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL4_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL4_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL4_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL4_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL4_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL4_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL4_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT5 Bit Fields */ +#define CCM_TARGET_ROOT5_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT5_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT5_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_POST_PODF_MASK) +#define CCM_TARGET_ROOT5_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT5_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT5_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT5_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT5_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT5_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT5_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT5_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT5_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT5_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_PRE_PODF_MASK) +#define CCM_TARGET_ROOT5_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT5_MUX_SHIFT 24 +#define CCM_TARGET_ROOT5_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_MUX_SHIFT))&CCM_TARGET_ROOT5_MUX_MASK) +#define CCM_TARGET_ROOT5_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT5_ENABLE_SHIFT 28 +/* TARGET_ROOT5_SET Bit Fields */ +#define CCM_TARGET_ROOT5_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT5_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT5_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT5_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT5_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT5_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT5_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT5_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT5_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT5_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT5_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT5_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT5_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT5_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT5_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT5_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_SET_MUX_SHIFT))&CCM_TARGET_ROOT5_SET_MUX_MASK) +#define CCM_TARGET_ROOT5_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT5_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT5_CLR Bit Fields */ +#define CCM_TARGET_ROOT5_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT5_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT5_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT5_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT5_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT5_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT5_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT5_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT5_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT5_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT5_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT5_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT5_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_CLR_MUX_SHIFT))&CCM_TARGET_ROOT5_CLR_MUX_MASK) +#define CCM_TARGET_ROOT5_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT5_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT5_TOG Bit Fields */ +#define CCM_TARGET_ROOT5_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT5_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT5_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT5_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT5_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT5_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT5_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT5_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT5_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT5_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT5_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT5_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT5_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT5_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT5_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT5_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT5_TOG_MUX_SHIFT))&CCM_TARGET_ROOT5_TOG_MUX_MASK) +#define CCM_TARGET_ROOT5_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT5_TOG_ENABLE_SHIFT 28 +/* POST5 Bit Fields */ +#define CCM_POST5_POST_PODF_MASK 0x3Fu +#define CCM_POST5_POST_PODF_SHIFT 0 +#define CCM_POST5_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST5_POST_PODF_SHIFT))&CCM_POST5_POST_PODF_MASK) +#define CCM_POST5_BUSY1_MASK 0x80u +#define CCM_POST5_BUSY1_SHIFT 7 +#define CCM_POST5_AUTO_PODF_MASK 0x700u +#define CCM_POST5_AUTO_PODF_SHIFT 8 +#define CCM_POST5_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST5_AUTO_PODF_SHIFT))&CCM_POST5_AUTO_PODF_MASK) +#define CCM_POST5_AUTO_EN_MASK 0x1000u +#define CCM_POST5_AUTO_EN_SHIFT 12 +#define CCM_POST5_SLOW_MASK 0x8000u +#define CCM_POST5_SLOW_SHIFT 15 +#define CCM_POST5_SELECT_MASK 0x10000000u +#define CCM_POST5_SELECT_SHIFT 28 +#define CCM_POST5_BUSY2_MASK 0x80000000u +#define CCM_POST5_BUSY2_SHIFT 31 +/* POST_ROOT5_SET Bit Fields */ +#define CCM_POST_ROOT5_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT5_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT5_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_SET_POST_PODF_SHIFT))&CCM_POST_ROOT5_SET_POST_PODF_MASK) +#define CCM_POST_ROOT5_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT5_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT5_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT5_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT5_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT5_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT5_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT5_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT5_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT5_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT5_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT5_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT5_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT5_SET_BUSY2_SHIFT 31 +/* POST_ROOT5_CLR Bit Fields */ +#define CCM_POST_ROOT5_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT5_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT5_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT5_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT5_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT5_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT5_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT5_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT5_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT5_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT5_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT5_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT5_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT5_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT5_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT5_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT5_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT5_CLR_BUSY2_SHIFT 31 +/* POST_ROOT5_TOG Bit Fields */ +#define CCM_POST_ROOT5_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT5_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT5_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT5_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT5_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT5_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT5_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT5_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT5_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT5_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT5_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT5_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT5_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT5_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT5_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT5_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT5_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT5_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT5_TOG_BUSY2_SHIFT 31 +/* PRE5 Bit Fields */ +#define CCM_PRE5_PRE_PODF_B_MASK 0x7u +#define CCM_PRE5_PRE_PODF_B_SHIFT 0 +#define CCM_PRE5_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_PRE_PODF_B_SHIFT))&CCM_PRE5_PRE_PODF_B_MASK) +#define CCM_PRE5_BUSY0_MASK 0x8u +#define CCM_PRE5_BUSY0_SHIFT 3 +#define CCM_PRE5_MUX_B_MASK 0x700u +#define CCM_PRE5_MUX_B_SHIFT 8 +#define CCM_PRE5_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_MUX_B_SHIFT))&CCM_PRE5_MUX_B_MASK) +#define CCM_PRE5_EN_B_MASK 0x1000u +#define CCM_PRE5_EN_B_SHIFT 12 +#define CCM_PRE5_BUSY1_MASK 0x8000u +#define CCM_PRE5_BUSY1_SHIFT 15 +#define CCM_PRE5_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE5_PRE_PODF_A_SHIFT 16 +#define CCM_PRE5_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_PRE_PODF_A_SHIFT))&CCM_PRE5_PRE_PODF_A_MASK) +#define CCM_PRE5_BUSY3_MASK 0x80000u +#define CCM_PRE5_BUSY3_SHIFT 19 +#define CCM_PRE5_MUX_A_MASK 0x7000000u +#define CCM_PRE5_MUX_A_SHIFT 24 +#define CCM_PRE5_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE5_MUX_A_SHIFT))&CCM_PRE5_MUX_A_MASK) +#define CCM_PRE5_EN_A_MASK 0x10000000u +#define CCM_PRE5_EN_A_SHIFT 28 +#define CCM_PRE5_BUSY4_MASK 0x80000000u +#define CCM_PRE5_BUSY4_SHIFT 31 +/* PRE_ROOT5_SET Bit Fields */ +#define CCM_PRE_ROOT5_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT5_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT5_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT5_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT5_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT5_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT5_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT5_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT5_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_MUX_B_SHIFT))&CCM_PRE_ROOT5_SET_MUX_B_MASK) +#define CCM_PRE_ROOT5_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT5_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT5_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT5_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT5_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT5_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT5_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT5_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT5_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT5_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT5_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT5_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT5_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_SET_MUX_A_SHIFT))&CCM_PRE_ROOT5_SET_MUX_A_MASK) +#define CCM_PRE_ROOT5_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT5_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT5_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT5_SET_BUSY4_SHIFT 31 +/* PRE_ROOT5_CLR Bit Fields */ +#define CCM_PRE_ROOT5_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT5_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT5_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT5_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT5_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT5_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT5_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT5_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT5_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT5_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT5_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT5_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT5_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT5_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT5_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT5_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT5_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT5_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT5_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT5_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT5_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT5_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT5_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT5_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT5_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT5_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT5_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT5_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT5_TOG Bit Fields */ +#define CCM_PRE_ROOT5_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT5_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT5_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT5_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT5_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT5_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT5_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT5_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT5_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT5_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT5_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT5_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT5_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT5_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT5_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT5_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT5_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT5_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT5_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT5_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT5_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT5_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT5_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT5_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT5_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT5_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT5_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT5_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT5_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL5 Bit Fields */ +#define CCM_ACCESS_CTRL5_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL5_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL5_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL5_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL5_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL5_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL5_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL5_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL5_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL5_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL5_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL5_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL5_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL5_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL5_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL5_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL5_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL5_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL5_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL5_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL5_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL5_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL5_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL5_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL5_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL5_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL5_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL5_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL5_LOCK_SHIFT 31 +/* ACCESS_CTRL5_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL5_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL5_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL5_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL5_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL5_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL5_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL5_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL5_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL5_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL5_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL5_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL5_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL5_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL5_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL5_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL5_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL5_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL5_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT6 Bit Fields */ +#define CCM_TARGET_ROOT6_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT6_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT6_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_POST_PODF_MASK) +#define CCM_TARGET_ROOT6_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT6_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT6_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT6_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT6_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT6_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT6_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT6_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT6_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT6_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_PRE_PODF_MASK) +#define CCM_TARGET_ROOT6_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT6_MUX_SHIFT 24 +#define CCM_TARGET_ROOT6_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_MUX_SHIFT))&CCM_TARGET_ROOT6_MUX_MASK) +#define CCM_TARGET_ROOT6_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT6_ENABLE_SHIFT 28 +/* TARGET_ROOT6_SET Bit Fields */ +#define CCM_TARGET_ROOT6_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT6_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT6_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT6_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT6_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT6_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT6_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT6_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT6_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT6_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT6_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT6_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT6_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT6_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT6_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT6_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_SET_MUX_SHIFT))&CCM_TARGET_ROOT6_SET_MUX_MASK) +#define CCM_TARGET_ROOT6_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT6_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT6_CLR Bit Fields */ +#define CCM_TARGET_ROOT6_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT6_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT6_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT6_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT6_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT6_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT6_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT6_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT6_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT6_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT6_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT6_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT6_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_CLR_MUX_SHIFT))&CCM_TARGET_ROOT6_CLR_MUX_MASK) +#define CCM_TARGET_ROOT6_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT6_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT6_TOG Bit Fields */ +#define CCM_TARGET_ROOT6_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT6_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT6_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT6_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT6_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT6_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT6_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT6_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT6_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT6_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT6_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT6_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT6_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT6_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT6_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT6_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT6_TOG_MUX_SHIFT))&CCM_TARGET_ROOT6_TOG_MUX_MASK) +#define CCM_TARGET_ROOT6_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT6_TOG_ENABLE_SHIFT 28 +/* POST6 Bit Fields */ +#define CCM_POST6_POST_PODF_MASK 0x3Fu +#define CCM_POST6_POST_PODF_SHIFT 0 +#define CCM_POST6_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST6_POST_PODF_SHIFT))&CCM_POST6_POST_PODF_MASK) +#define CCM_POST6_BUSY1_MASK 0x80u +#define CCM_POST6_BUSY1_SHIFT 7 +#define CCM_POST6_AUTO_PODF_MASK 0x700u +#define CCM_POST6_AUTO_PODF_SHIFT 8 +#define CCM_POST6_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST6_AUTO_PODF_SHIFT))&CCM_POST6_AUTO_PODF_MASK) +#define CCM_POST6_AUTO_EN_MASK 0x1000u +#define CCM_POST6_AUTO_EN_SHIFT 12 +#define CCM_POST6_SLOW_MASK 0x8000u +#define CCM_POST6_SLOW_SHIFT 15 +#define CCM_POST6_SELECT_MASK 0x10000000u +#define CCM_POST6_SELECT_SHIFT 28 +#define CCM_POST6_BUSY2_MASK 0x80000000u +#define CCM_POST6_BUSY2_SHIFT 31 +/* POST_ROOT6_SET Bit Fields */ +#define CCM_POST_ROOT6_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT6_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT6_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_SET_POST_PODF_SHIFT))&CCM_POST_ROOT6_SET_POST_PODF_MASK) +#define CCM_POST_ROOT6_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT6_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT6_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT6_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT6_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT6_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT6_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT6_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT6_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT6_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT6_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT6_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT6_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT6_SET_BUSY2_SHIFT 31 +/* POST_ROOT6_CLR Bit Fields */ +#define CCM_POST_ROOT6_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT6_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT6_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT6_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT6_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT6_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT6_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT6_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT6_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT6_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT6_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT6_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT6_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT6_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT6_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT6_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT6_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT6_CLR_BUSY2_SHIFT 31 +/* POST_ROOT6_TOG Bit Fields */ +#define CCM_POST_ROOT6_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT6_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT6_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT6_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT6_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT6_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT6_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT6_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT6_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT6_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT6_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT6_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT6_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT6_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT6_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT6_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT6_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT6_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT6_TOG_BUSY2_SHIFT 31 +/* PRE6 Bit Fields */ +#define CCM_PRE6_PRE_PODF_B_MASK 0x7u +#define CCM_PRE6_PRE_PODF_B_SHIFT 0 +#define CCM_PRE6_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_PRE_PODF_B_SHIFT))&CCM_PRE6_PRE_PODF_B_MASK) +#define CCM_PRE6_BUSY0_MASK 0x8u +#define CCM_PRE6_BUSY0_SHIFT 3 +#define CCM_PRE6_MUX_B_MASK 0x700u +#define CCM_PRE6_MUX_B_SHIFT 8 +#define CCM_PRE6_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_MUX_B_SHIFT))&CCM_PRE6_MUX_B_MASK) +#define CCM_PRE6_EN_B_MASK 0x1000u +#define CCM_PRE6_EN_B_SHIFT 12 +#define CCM_PRE6_BUSY1_MASK 0x8000u +#define CCM_PRE6_BUSY1_SHIFT 15 +#define CCM_PRE6_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE6_PRE_PODF_A_SHIFT 16 +#define CCM_PRE6_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_PRE_PODF_A_SHIFT))&CCM_PRE6_PRE_PODF_A_MASK) +#define CCM_PRE6_BUSY3_MASK 0x80000u +#define CCM_PRE6_BUSY3_SHIFT 19 +#define CCM_PRE6_MUX_A_MASK 0x7000000u +#define CCM_PRE6_MUX_A_SHIFT 24 +#define CCM_PRE6_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE6_MUX_A_SHIFT))&CCM_PRE6_MUX_A_MASK) +#define CCM_PRE6_EN_A_MASK 0x10000000u +#define CCM_PRE6_EN_A_SHIFT 28 +#define CCM_PRE6_BUSY4_MASK 0x80000000u +#define CCM_PRE6_BUSY4_SHIFT 31 +/* PRE_ROOT6_SET Bit Fields */ +#define CCM_PRE_ROOT6_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT6_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT6_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT6_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT6_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT6_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT6_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT6_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT6_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_MUX_B_SHIFT))&CCM_PRE_ROOT6_SET_MUX_B_MASK) +#define CCM_PRE_ROOT6_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT6_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT6_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT6_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT6_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT6_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT6_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT6_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT6_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT6_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT6_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT6_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT6_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_SET_MUX_A_SHIFT))&CCM_PRE_ROOT6_SET_MUX_A_MASK) +#define CCM_PRE_ROOT6_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT6_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT6_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT6_SET_BUSY4_SHIFT 31 +/* PRE_ROOT6_CLR Bit Fields */ +#define CCM_PRE_ROOT6_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT6_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT6_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT6_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT6_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT6_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT6_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT6_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT6_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT6_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT6_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT6_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT6_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT6_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT6_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT6_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT6_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT6_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT6_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT6_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT6_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT6_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT6_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT6_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT6_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT6_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT6_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT6_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT6_TOG Bit Fields */ +#define CCM_PRE_ROOT6_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT6_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT6_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT6_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT6_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT6_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT6_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT6_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT6_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT6_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT6_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT6_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT6_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT6_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT6_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT6_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT6_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT6_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT6_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT6_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT6_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT6_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT6_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT6_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT6_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT6_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT6_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT6_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT6_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL6 Bit Fields */ +#define CCM_ACCESS_CTRL6_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL6_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL6_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL6_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL6_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL6_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL6_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL6_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL6_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL6_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL6_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL6_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL6_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL6_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL6_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL6_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL6_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL6_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL6_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL6_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL6_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL6_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL6_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL6_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL6_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL6_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL6_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL6_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL6_LOCK_SHIFT 31 +/* ACCESS_CTRL6_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL6_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL6_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL6_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL6_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL6_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL6_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL6_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL6_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL6_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL6_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL6_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL6_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL6_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL6_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL6_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL6_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL6_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL6_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT7 Bit Fields */ +#define CCM_TARGET_ROOT7_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT7_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT7_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_POST_PODF_MASK) +#define CCM_TARGET_ROOT7_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT7_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT7_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT7_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT7_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT7_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT7_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT7_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT7_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT7_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_PRE_PODF_MASK) +#define CCM_TARGET_ROOT7_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT7_MUX_SHIFT 24 +#define CCM_TARGET_ROOT7_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_MUX_SHIFT))&CCM_TARGET_ROOT7_MUX_MASK) +#define CCM_TARGET_ROOT7_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT7_ENABLE_SHIFT 28 +/* TARGET_ROOT7_SET Bit Fields */ +#define CCM_TARGET_ROOT7_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT7_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT7_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT7_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT7_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT7_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT7_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT7_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT7_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT7_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT7_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT7_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT7_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT7_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT7_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT7_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_SET_MUX_SHIFT))&CCM_TARGET_ROOT7_SET_MUX_MASK) +#define CCM_TARGET_ROOT7_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT7_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT7_CLR Bit Fields */ +#define CCM_TARGET_ROOT7_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT7_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT7_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT7_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT7_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT7_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT7_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT7_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT7_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT7_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT7_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT7_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT7_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_CLR_MUX_SHIFT))&CCM_TARGET_ROOT7_CLR_MUX_MASK) +#define CCM_TARGET_ROOT7_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT7_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT7_TOG Bit Fields */ +#define CCM_TARGET_ROOT7_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT7_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT7_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT7_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT7_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT7_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT7_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT7_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT7_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT7_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT7_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT7_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT7_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT7_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT7_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT7_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT7_TOG_MUX_SHIFT))&CCM_TARGET_ROOT7_TOG_MUX_MASK) +#define CCM_TARGET_ROOT7_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT7_TOG_ENABLE_SHIFT 28 +/* POST7 Bit Fields */ +#define CCM_POST7_POST_PODF_MASK 0x3Fu +#define CCM_POST7_POST_PODF_SHIFT 0 +#define CCM_POST7_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST7_POST_PODF_SHIFT))&CCM_POST7_POST_PODF_MASK) +#define CCM_POST7_BUSY1_MASK 0x80u +#define CCM_POST7_BUSY1_SHIFT 7 +#define CCM_POST7_AUTO_PODF_MASK 0x700u +#define CCM_POST7_AUTO_PODF_SHIFT 8 +#define CCM_POST7_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST7_AUTO_PODF_SHIFT))&CCM_POST7_AUTO_PODF_MASK) +#define CCM_POST7_AUTO_EN_MASK 0x1000u +#define CCM_POST7_AUTO_EN_SHIFT 12 +#define CCM_POST7_SLOW_MASK 0x8000u +#define CCM_POST7_SLOW_SHIFT 15 +#define CCM_POST7_SELECT_MASK 0x10000000u +#define CCM_POST7_SELECT_SHIFT 28 +#define CCM_POST7_BUSY2_MASK 0x80000000u +#define CCM_POST7_BUSY2_SHIFT 31 +/* POST_ROOT7_SET Bit Fields */ +#define CCM_POST_ROOT7_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT7_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT7_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_SET_POST_PODF_SHIFT))&CCM_POST_ROOT7_SET_POST_PODF_MASK) +#define CCM_POST_ROOT7_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT7_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT7_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT7_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT7_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT7_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT7_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT7_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT7_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT7_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT7_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT7_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT7_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT7_SET_BUSY2_SHIFT 31 +/* POST_ROOT7_CLR Bit Fields */ +#define CCM_POST_ROOT7_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT7_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT7_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT7_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT7_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT7_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT7_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT7_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT7_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT7_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT7_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT7_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT7_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT7_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT7_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT7_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT7_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT7_CLR_BUSY2_SHIFT 31 +/* POST_ROOT7_TOG Bit Fields */ +#define CCM_POST_ROOT7_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT7_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT7_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT7_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT7_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT7_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT7_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT7_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT7_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT7_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT7_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT7_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT7_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT7_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT7_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT7_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT7_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT7_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT7_TOG_BUSY2_SHIFT 31 +/* PRE7 Bit Fields */ +#define CCM_PRE7_PRE_PODF_B_MASK 0x7u +#define CCM_PRE7_PRE_PODF_B_SHIFT 0 +#define CCM_PRE7_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_PRE_PODF_B_SHIFT))&CCM_PRE7_PRE_PODF_B_MASK) +#define CCM_PRE7_BUSY0_MASK 0x8u +#define CCM_PRE7_BUSY0_SHIFT 3 +#define CCM_PRE7_MUX_B_MASK 0x700u +#define CCM_PRE7_MUX_B_SHIFT 8 +#define CCM_PRE7_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_MUX_B_SHIFT))&CCM_PRE7_MUX_B_MASK) +#define CCM_PRE7_EN_B_MASK 0x1000u +#define CCM_PRE7_EN_B_SHIFT 12 +#define CCM_PRE7_BUSY1_MASK 0x8000u +#define CCM_PRE7_BUSY1_SHIFT 15 +#define CCM_PRE7_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE7_PRE_PODF_A_SHIFT 16 +#define CCM_PRE7_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_PRE_PODF_A_SHIFT))&CCM_PRE7_PRE_PODF_A_MASK) +#define CCM_PRE7_BUSY3_MASK 0x80000u +#define CCM_PRE7_BUSY3_SHIFT 19 +#define CCM_PRE7_MUX_A_MASK 0x7000000u +#define CCM_PRE7_MUX_A_SHIFT 24 +#define CCM_PRE7_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE7_MUX_A_SHIFT))&CCM_PRE7_MUX_A_MASK) +#define CCM_PRE7_EN_A_MASK 0x10000000u +#define CCM_PRE7_EN_A_SHIFT 28 +#define CCM_PRE7_BUSY4_MASK 0x80000000u +#define CCM_PRE7_BUSY4_SHIFT 31 +/* PRE_ROOT7_SET Bit Fields */ +#define CCM_PRE_ROOT7_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT7_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT7_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT7_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT7_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT7_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT7_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT7_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT7_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_MUX_B_SHIFT))&CCM_PRE_ROOT7_SET_MUX_B_MASK) +#define CCM_PRE_ROOT7_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT7_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT7_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT7_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT7_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT7_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT7_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT7_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT7_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT7_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT7_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT7_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT7_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_SET_MUX_A_SHIFT))&CCM_PRE_ROOT7_SET_MUX_A_MASK) +#define CCM_PRE_ROOT7_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT7_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT7_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT7_SET_BUSY4_SHIFT 31 +/* PRE_ROOT7_CLR Bit Fields */ +#define CCM_PRE_ROOT7_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT7_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT7_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT7_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT7_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT7_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT7_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT7_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT7_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT7_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT7_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT7_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT7_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT7_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT7_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT7_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT7_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT7_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT7_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT7_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT7_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT7_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT7_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT7_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT7_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT7_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT7_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT7_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT7_TOG Bit Fields */ +#define CCM_PRE_ROOT7_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT7_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT7_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT7_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT7_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT7_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT7_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT7_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT7_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT7_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT7_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT7_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT7_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT7_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT7_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT7_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT7_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT7_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT7_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT7_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT7_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT7_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT7_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT7_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT7_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT7_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT7_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT7_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT7_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL7 Bit Fields */ +#define CCM_ACCESS_CTRL7_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL7_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL7_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL7_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL7_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL7_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL7_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL7_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL7_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL7_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL7_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL7_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL7_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL7_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL7_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL7_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL7_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL7_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL7_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL7_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL7_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL7_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL7_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL7_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL7_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL7_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL7_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL7_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL7_LOCK_SHIFT 31 +/* ACCESS_CTRL7_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL7_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL7_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL7_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL7_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL7_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL7_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL7_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL7_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL7_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL7_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL7_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL7_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL7_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL7_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL7_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL7_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL7_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL7_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT8 Bit Fields */ +#define CCM_TARGET_ROOT8_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT8_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT8_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_POST_PODF_MASK) +#define CCM_TARGET_ROOT8_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT8_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT8_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT8_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT8_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT8_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT8_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT8_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT8_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT8_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_PRE_PODF_MASK) +#define CCM_TARGET_ROOT8_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT8_MUX_SHIFT 24 +#define CCM_TARGET_ROOT8_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_MUX_SHIFT))&CCM_TARGET_ROOT8_MUX_MASK) +#define CCM_TARGET_ROOT8_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT8_ENABLE_SHIFT 28 +/* TARGET_ROOT8_SET Bit Fields */ +#define CCM_TARGET_ROOT8_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT8_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT8_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT8_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT8_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT8_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT8_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT8_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT8_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT8_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT8_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT8_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT8_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT8_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT8_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT8_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_SET_MUX_SHIFT))&CCM_TARGET_ROOT8_SET_MUX_MASK) +#define CCM_TARGET_ROOT8_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT8_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT8_CLR Bit Fields */ +#define CCM_TARGET_ROOT8_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT8_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT8_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT8_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT8_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT8_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT8_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT8_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT8_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT8_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT8_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT8_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT8_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_CLR_MUX_SHIFT))&CCM_TARGET_ROOT8_CLR_MUX_MASK) +#define CCM_TARGET_ROOT8_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT8_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT8_TOG Bit Fields */ +#define CCM_TARGET_ROOT8_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT8_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT8_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT8_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT8_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT8_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT8_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT8_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT8_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT8_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT8_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT8_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT8_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT8_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT8_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT8_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT8_TOG_MUX_SHIFT))&CCM_TARGET_ROOT8_TOG_MUX_MASK) +#define CCM_TARGET_ROOT8_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT8_TOG_ENABLE_SHIFT 28 +/* POST8 Bit Fields */ +#define CCM_POST8_POST_PODF_MASK 0x3Fu +#define CCM_POST8_POST_PODF_SHIFT 0 +#define CCM_POST8_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST8_POST_PODF_SHIFT))&CCM_POST8_POST_PODF_MASK) +#define CCM_POST8_BUSY1_MASK 0x80u +#define CCM_POST8_BUSY1_SHIFT 7 +#define CCM_POST8_AUTO_PODF_MASK 0x700u +#define CCM_POST8_AUTO_PODF_SHIFT 8 +#define CCM_POST8_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST8_AUTO_PODF_SHIFT))&CCM_POST8_AUTO_PODF_MASK) +#define CCM_POST8_AUTO_EN_MASK 0x1000u +#define CCM_POST8_AUTO_EN_SHIFT 12 +#define CCM_POST8_SLOW_MASK 0x8000u +#define CCM_POST8_SLOW_SHIFT 15 +#define CCM_POST8_SELECT_MASK 0x10000000u +#define CCM_POST8_SELECT_SHIFT 28 +#define CCM_POST8_BUSY2_MASK 0x80000000u +#define CCM_POST8_BUSY2_SHIFT 31 +/* POST_ROOT8_SET Bit Fields */ +#define CCM_POST_ROOT8_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT8_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT8_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_SET_POST_PODF_SHIFT))&CCM_POST_ROOT8_SET_POST_PODF_MASK) +#define CCM_POST_ROOT8_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT8_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT8_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT8_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT8_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT8_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT8_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT8_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT8_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT8_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT8_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT8_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT8_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT8_SET_BUSY2_SHIFT 31 +/* POST_ROOT8_CLR Bit Fields */ +#define CCM_POST_ROOT8_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT8_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT8_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT8_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT8_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT8_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT8_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT8_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT8_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT8_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT8_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT8_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT8_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT8_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT8_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT8_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT8_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT8_CLR_BUSY2_SHIFT 31 +/* POST_ROOT8_TOG Bit Fields */ +#define CCM_POST_ROOT8_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT8_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT8_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT8_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT8_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT8_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT8_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT8_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT8_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT8_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT8_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT8_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT8_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT8_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT8_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT8_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT8_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT8_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT8_TOG_BUSY2_SHIFT 31 +/* PRE8 Bit Fields */ +#define CCM_PRE8_PRE_PODF_B_MASK 0x7u +#define CCM_PRE8_PRE_PODF_B_SHIFT 0 +#define CCM_PRE8_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_PRE_PODF_B_SHIFT))&CCM_PRE8_PRE_PODF_B_MASK) +#define CCM_PRE8_BUSY0_MASK 0x8u +#define CCM_PRE8_BUSY0_SHIFT 3 +#define CCM_PRE8_MUX_B_MASK 0x700u +#define CCM_PRE8_MUX_B_SHIFT 8 +#define CCM_PRE8_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_MUX_B_SHIFT))&CCM_PRE8_MUX_B_MASK) +#define CCM_PRE8_EN_B_MASK 0x1000u +#define CCM_PRE8_EN_B_SHIFT 12 +#define CCM_PRE8_BUSY1_MASK 0x8000u +#define CCM_PRE8_BUSY1_SHIFT 15 +#define CCM_PRE8_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE8_PRE_PODF_A_SHIFT 16 +#define CCM_PRE8_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_PRE_PODF_A_SHIFT))&CCM_PRE8_PRE_PODF_A_MASK) +#define CCM_PRE8_BUSY3_MASK 0x80000u +#define CCM_PRE8_BUSY3_SHIFT 19 +#define CCM_PRE8_MUX_A_MASK 0x7000000u +#define CCM_PRE8_MUX_A_SHIFT 24 +#define CCM_PRE8_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE8_MUX_A_SHIFT))&CCM_PRE8_MUX_A_MASK) +#define CCM_PRE8_EN_A_MASK 0x10000000u +#define CCM_PRE8_EN_A_SHIFT 28 +#define CCM_PRE8_BUSY4_MASK 0x80000000u +#define CCM_PRE8_BUSY4_SHIFT 31 +/* PRE_ROOT8_SET Bit Fields */ +#define CCM_PRE_ROOT8_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT8_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT8_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT8_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT8_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT8_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT8_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT8_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT8_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_MUX_B_SHIFT))&CCM_PRE_ROOT8_SET_MUX_B_MASK) +#define CCM_PRE_ROOT8_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT8_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT8_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT8_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT8_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT8_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT8_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT8_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT8_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT8_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT8_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT8_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT8_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_SET_MUX_A_SHIFT))&CCM_PRE_ROOT8_SET_MUX_A_MASK) +#define CCM_PRE_ROOT8_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT8_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT8_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT8_SET_BUSY4_SHIFT 31 +/* PRE_ROOT8_CLR Bit Fields */ +#define CCM_PRE_ROOT8_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT8_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT8_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT8_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT8_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT8_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT8_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT8_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT8_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT8_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT8_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT8_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT8_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT8_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT8_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT8_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT8_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT8_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT8_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT8_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT8_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT8_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT8_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT8_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT8_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT8_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT8_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT8_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT8_TOG Bit Fields */ +#define CCM_PRE_ROOT8_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT8_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT8_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT8_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT8_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT8_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT8_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT8_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT8_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT8_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT8_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT8_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT8_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT8_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT8_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT8_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT8_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT8_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT8_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT8_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT8_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT8_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT8_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT8_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT8_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT8_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT8_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT8_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT8_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL8 Bit Fields */ +#define CCM_ACCESS_CTRL8_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL8_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL8_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL8_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL8_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL8_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL8_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL8_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL8_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL8_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL8_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL8_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL8_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL8_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL8_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL8_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL8_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL8_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL8_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL8_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL8_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL8_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL8_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL8_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL8_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL8_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL8_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL8_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL8_LOCK_SHIFT 31 +/* ACCESS_CTRL8_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL8_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL8_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL8_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL8_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL8_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL8_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL8_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL8_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL8_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL8_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL8_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL8_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL8_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL8_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL8_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL8_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL8_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL8_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT9 Bit Fields */ +#define CCM_TARGET_ROOT9_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT9_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT9_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_POST_PODF_MASK) +#define CCM_TARGET_ROOT9_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT9_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT9_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT9_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT9_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT9_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT9_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT9_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT9_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT9_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_PRE_PODF_MASK) +#define CCM_TARGET_ROOT9_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT9_MUX_SHIFT 24 +#define CCM_TARGET_ROOT9_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_MUX_SHIFT))&CCM_TARGET_ROOT9_MUX_MASK) +#define CCM_TARGET_ROOT9_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT9_ENABLE_SHIFT 28 +/* TARGET_ROOT9_SET Bit Fields */ +#define CCM_TARGET_ROOT9_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT9_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT9_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT9_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT9_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT9_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT9_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT9_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT9_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT9_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT9_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT9_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT9_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT9_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT9_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT9_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_SET_MUX_SHIFT))&CCM_TARGET_ROOT9_SET_MUX_MASK) +#define CCM_TARGET_ROOT9_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT9_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT9_CLR Bit Fields */ +#define CCM_TARGET_ROOT9_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT9_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT9_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT9_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT9_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT9_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT9_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT9_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT9_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT9_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT9_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT9_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT9_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_CLR_MUX_SHIFT))&CCM_TARGET_ROOT9_CLR_MUX_MASK) +#define CCM_TARGET_ROOT9_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT9_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT9_TOG Bit Fields */ +#define CCM_TARGET_ROOT9_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT9_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT9_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT9_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT9_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT9_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT9_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT9_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT9_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT9_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT9_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT9_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT9_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT9_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT9_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT9_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT9_TOG_MUX_SHIFT))&CCM_TARGET_ROOT9_TOG_MUX_MASK) +#define CCM_TARGET_ROOT9_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT9_TOG_ENABLE_SHIFT 28 +/* POST9 Bit Fields */ +#define CCM_POST9_POST_PODF_MASK 0x3Fu +#define CCM_POST9_POST_PODF_SHIFT 0 +#define CCM_POST9_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST9_POST_PODF_SHIFT))&CCM_POST9_POST_PODF_MASK) +#define CCM_POST9_BUSY1_MASK 0x80u +#define CCM_POST9_BUSY1_SHIFT 7 +#define CCM_POST9_AUTO_PODF_MASK 0x700u +#define CCM_POST9_AUTO_PODF_SHIFT 8 +#define CCM_POST9_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST9_AUTO_PODF_SHIFT))&CCM_POST9_AUTO_PODF_MASK) +#define CCM_POST9_AUTO_EN_MASK 0x1000u +#define CCM_POST9_AUTO_EN_SHIFT 12 +#define CCM_POST9_SLOW_MASK 0x8000u +#define CCM_POST9_SLOW_SHIFT 15 +#define CCM_POST9_SELECT_MASK 0x10000000u +#define CCM_POST9_SELECT_SHIFT 28 +#define CCM_POST9_BUSY2_MASK 0x80000000u +#define CCM_POST9_BUSY2_SHIFT 31 +/* POST_ROOT9_SET Bit Fields */ +#define CCM_POST_ROOT9_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT9_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT9_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_SET_POST_PODF_SHIFT))&CCM_POST_ROOT9_SET_POST_PODF_MASK) +#define CCM_POST_ROOT9_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT9_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT9_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT9_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT9_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT9_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT9_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT9_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT9_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT9_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT9_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT9_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT9_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT9_SET_BUSY2_SHIFT 31 +/* POST_ROOT9_CLR Bit Fields */ +#define CCM_POST_ROOT9_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT9_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT9_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT9_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT9_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT9_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT9_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT9_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT9_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT9_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT9_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT9_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT9_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT9_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT9_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT9_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT9_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT9_CLR_BUSY2_SHIFT 31 +/* POST_ROOT9_TOG Bit Fields */ +#define CCM_POST_ROOT9_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT9_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT9_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT9_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT9_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT9_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT9_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT9_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT9_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT9_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT9_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT9_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT9_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT9_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT9_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT9_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT9_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT9_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT9_TOG_BUSY2_SHIFT 31 +/* PRE9 Bit Fields */ +#define CCM_PRE9_PRE_PODF_B_MASK 0x7u +#define CCM_PRE9_PRE_PODF_B_SHIFT 0 +#define CCM_PRE9_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_PRE_PODF_B_SHIFT))&CCM_PRE9_PRE_PODF_B_MASK) +#define CCM_PRE9_BUSY0_MASK 0x8u +#define CCM_PRE9_BUSY0_SHIFT 3 +#define CCM_PRE9_MUX_B_MASK 0x700u +#define CCM_PRE9_MUX_B_SHIFT 8 +#define CCM_PRE9_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_MUX_B_SHIFT))&CCM_PRE9_MUX_B_MASK) +#define CCM_PRE9_EN_B_MASK 0x1000u +#define CCM_PRE9_EN_B_SHIFT 12 +#define CCM_PRE9_BUSY1_MASK 0x8000u +#define CCM_PRE9_BUSY1_SHIFT 15 +#define CCM_PRE9_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE9_PRE_PODF_A_SHIFT 16 +#define CCM_PRE9_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_PRE_PODF_A_SHIFT))&CCM_PRE9_PRE_PODF_A_MASK) +#define CCM_PRE9_BUSY3_MASK 0x80000u +#define CCM_PRE9_BUSY3_SHIFT 19 +#define CCM_PRE9_MUX_A_MASK 0x7000000u +#define CCM_PRE9_MUX_A_SHIFT 24 +#define CCM_PRE9_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE9_MUX_A_SHIFT))&CCM_PRE9_MUX_A_MASK) +#define CCM_PRE9_EN_A_MASK 0x10000000u +#define CCM_PRE9_EN_A_SHIFT 28 +#define CCM_PRE9_BUSY4_MASK 0x80000000u +#define CCM_PRE9_BUSY4_SHIFT 31 +/* PRE_ROOT9_SET Bit Fields */ +#define CCM_PRE_ROOT9_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT9_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT9_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT9_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT9_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT9_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT9_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT9_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT9_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_MUX_B_SHIFT))&CCM_PRE_ROOT9_SET_MUX_B_MASK) +#define CCM_PRE_ROOT9_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT9_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT9_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT9_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT9_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT9_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT9_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT9_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT9_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT9_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT9_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT9_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT9_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_SET_MUX_A_SHIFT))&CCM_PRE_ROOT9_SET_MUX_A_MASK) +#define CCM_PRE_ROOT9_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT9_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT9_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT9_SET_BUSY4_SHIFT 31 +/* PRE_ROOT9_CLR Bit Fields */ +#define CCM_PRE_ROOT9_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT9_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT9_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT9_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT9_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT9_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT9_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT9_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT9_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT9_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT9_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT9_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT9_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT9_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT9_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT9_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT9_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT9_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT9_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT9_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT9_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT9_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT9_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT9_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT9_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT9_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT9_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT9_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT9_TOG Bit Fields */ +#define CCM_PRE_ROOT9_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT9_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT9_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT9_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT9_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT9_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT9_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT9_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT9_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT9_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT9_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT9_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT9_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT9_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT9_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT9_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT9_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT9_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT9_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT9_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT9_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT9_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT9_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT9_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT9_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT9_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT9_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT9_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT9_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL9 Bit Fields */ +#define CCM_ACCESS_CTRL9_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL9_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL9_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL9_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL9_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL9_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL9_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL9_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL9_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL9_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL9_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL9_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL9_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL9_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL9_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL9_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL9_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL9_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL9_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL9_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL9_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL9_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL9_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL9_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL9_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL9_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL9_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL9_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL9_LOCK_SHIFT 31 +/* ACCESS_CTRL9_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL9_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL9_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL9_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL9_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL9_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL9_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL9_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL9_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL9_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL9_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL9_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL9_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL9_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL9_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL9_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL9_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL9_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL9_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT10 Bit Fields */ +#define CCM_TARGET_ROOT10_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT10_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT10_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_POST_PODF_MASK) +#define CCM_TARGET_ROOT10_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT10_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT10_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT10_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT10_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT10_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT10_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT10_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT10_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT10_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_PRE_PODF_MASK) +#define CCM_TARGET_ROOT10_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT10_MUX_SHIFT 24 +#define CCM_TARGET_ROOT10_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_MUX_SHIFT))&CCM_TARGET_ROOT10_MUX_MASK) +#define CCM_TARGET_ROOT10_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT10_ENABLE_SHIFT 28 +/* TARGET_ROOT10_SET Bit Fields */ +#define CCM_TARGET_ROOT10_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT10_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT10_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT10_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT10_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT10_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT10_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT10_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT10_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT10_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT10_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT10_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT10_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT10_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT10_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT10_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_SET_MUX_SHIFT))&CCM_TARGET_ROOT10_SET_MUX_MASK) +#define CCM_TARGET_ROOT10_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT10_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT10_CLR Bit Fields */ +#define CCM_TARGET_ROOT10_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT10_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT10_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT10_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT10_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT10_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT10_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT10_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT10_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT10_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT10_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT10_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT10_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_CLR_MUX_SHIFT))&CCM_TARGET_ROOT10_CLR_MUX_MASK) +#define CCM_TARGET_ROOT10_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT10_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT10_TOG Bit Fields */ +#define CCM_TARGET_ROOT10_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT10_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT10_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT10_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT10_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT10_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT10_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT10_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT10_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT10_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT10_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT10_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT10_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT10_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT10_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT10_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT10_TOG_MUX_SHIFT))&CCM_TARGET_ROOT10_TOG_MUX_MASK) +#define CCM_TARGET_ROOT10_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT10_TOG_ENABLE_SHIFT 28 +/* POST10 Bit Fields */ +#define CCM_POST10_POST_PODF_MASK 0x3Fu +#define CCM_POST10_POST_PODF_SHIFT 0 +#define CCM_POST10_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST10_POST_PODF_SHIFT))&CCM_POST10_POST_PODF_MASK) +#define CCM_POST10_BUSY1_MASK 0x80u +#define CCM_POST10_BUSY1_SHIFT 7 +#define CCM_POST10_AUTO_PODF_MASK 0x700u +#define CCM_POST10_AUTO_PODF_SHIFT 8 +#define CCM_POST10_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST10_AUTO_PODF_SHIFT))&CCM_POST10_AUTO_PODF_MASK) +#define CCM_POST10_AUTO_EN_MASK 0x1000u +#define CCM_POST10_AUTO_EN_SHIFT 12 +#define CCM_POST10_SLOW_MASK 0x8000u +#define CCM_POST10_SLOW_SHIFT 15 +#define CCM_POST10_SELECT_MASK 0x10000000u +#define CCM_POST10_SELECT_SHIFT 28 +#define CCM_POST10_BUSY2_MASK 0x80000000u +#define CCM_POST10_BUSY2_SHIFT 31 +/* POST_ROOT10_SET Bit Fields */ +#define CCM_POST_ROOT10_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT10_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT10_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_SET_POST_PODF_SHIFT))&CCM_POST_ROOT10_SET_POST_PODF_MASK) +#define CCM_POST_ROOT10_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT10_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT10_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT10_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT10_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT10_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT10_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT10_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT10_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT10_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT10_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT10_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT10_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT10_SET_BUSY2_SHIFT 31 +/* POST_ROOT10_CLR Bit Fields */ +#define CCM_POST_ROOT10_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT10_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT10_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT10_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT10_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT10_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT10_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT10_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT10_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT10_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT10_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT10_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT10_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT10_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT10_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT10_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT10_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT10_CLR_BUSY2_SHIFT 31 +/* POST_ROOT10_TOG Bit Fields */ +#define CCM_POST_ROOT10_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT10_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT10_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT10_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT10_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT10_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT10_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT10_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT10_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT10_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT10_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT10_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT10_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT10_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT10_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT10_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT10_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT10_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT10_TOG_BUSY2_SHIFT 31 +/* PRE10 Bit Fields */ +#define CCM_PRE10_PRE_PODF_B_MASK 0x7u +#define CCM_PRE10_PRE_PODF_B_SHIFT 0 +#define CCM_PRE10_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_PRE_PODF_B_SHIFT))&CCM_PRE10_PRE_PODF_B_MASK) +#define CCM_PRE10_BUSY0_MASK 0x8u +#define CCM_PRE10_BUSY0_SHIFT 3 +#define CCM_PRE10_MUX_B_MASK 0x700u +#define CCM_PRE10_MUX_B_SHIFT 8 +#define CCM_PRE10_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_MUX_B_SHIFT))&CCM_PRE10_MUX_B_MASK) +#define CCM_PRE10_EN_B_MASK 0x1000u +#define CCM_PRE10_EN_B_SHIFT 12 +#define CCM_PRE10_BUSY1_MASK 0x8000u +#define CCM_PRE10_BUSY1_SHIFT 15 +#define CCM_PRE10_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE10_PRE_PODF_A_SHIFT 16 +#define CCM_PRE10_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_PRE_PODF_A_SHIFT))&CCM_PRE10_PRE_PODF_A_MASK) +#define CCM_PRE10_BUSY3_MASK 0x80000u +#define CCM_PRE10_BUSY3_SHIFT 19 +#define CCM_PRE10_MUX_A_MASK 0x7000000u +#define CCM_PRE10_MUX_A_SHIFT 24 +#define CCM_PRE10_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE10_MUX_A_SHIFT))&CCM_PRE10_MUX_A_MASK) +#define CCM_PRE10_EN_A_MASK 0x10000000u +#define CCM_PRE10_EN_A_SHIFT 28 +#define CCM_PRE10_BUSY4_MASK 0x80000000u +#define CCM_PRE10_BUSY4_SHIFT 31 +/* PRE_ROOT10_SET Bit Fields */ +#define CCM_PRE_ROOT10_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT10_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT10_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT10_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT10_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT10_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT10_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT10_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT10_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_MUX_B_SHIFT))&CCM_PRE_ROOT10_SET_MUX_B_MASK) +#define CCM_PRE_ROOT10_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT10_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT10_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT10_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT10_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT10_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT10_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT10_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT10_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT10_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT10_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT10_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT10_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_SET_MUX_A_SHIFT))&CCM_PRE_ROOT10_SET_MUX_A_MASK) +#define CCM_PRE_ROOT10_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT10_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT10_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT10_SET_BUSY4_SHIFT 31 +/* PRE_ROOT10_CLR Bit Fields */ +#define CCM_PRE_ROOT10_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT10_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT10_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT10_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT10_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT10_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT10_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT10_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT10_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT10_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT10_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT10_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT10_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT10_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT10_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT10_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT10_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT10_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT10_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT10_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT10_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT10_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT10_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT10_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT10_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT10_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT10_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT10_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT10_TOG Bit Fields */ +#define CCM_PRE_ROOT10_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT10_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT10_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT10_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT10_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT10_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT10_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT10_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT10_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT10_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT10_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT10_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT10_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT10_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT10_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT10_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT10_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT10_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT10_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT10_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT10_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT10_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT10_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT10_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT10_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT10_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT10_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT10_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT10_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL10 Bit Fields */ +#define CCM_ACCESS_CTRL10_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL10_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL10_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL10_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL10_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL10_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL10_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL10_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL10_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL10_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL10_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL10_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL10_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL10_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL10_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL10_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL10_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL10_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL10_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL10_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL10_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL10_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL10_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL10_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL10_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL10_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL10_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL10_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL10_LOCK_SHIFT 31 +/* ACCESS_CTRL10_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL10_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL10_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL10_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL10_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL10_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL10_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL10_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL10_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL10_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL10_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL10_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL10_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL10_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL10_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL10_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL10_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL10_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL10_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT11 Bit Fields */ +#define CCM_TARGET_ROOT11_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT11_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT11_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_POST_PODF_MASK) +#define CCM_TARGET_ROOT11_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT11_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT11_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT11_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT11_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT11_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT11_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT11_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT11_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT11_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_PRE_PODF_MASK) +#define CCM_TARGET_ROOT11_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT11_MUX_SHIFT 24 +#define CCM_TARGET_ROOT11_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_MUX_SHIFT))&CCM_TARGET_ROOT11_MUX_MASK) +#define CCM_TARGET_ROOT11_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT11_ENABLE_SHIFT 28 +/* TARGET_ROOT11_SET Bit Fields */ +#define CCM_TARGET_ROOT11_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT11_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT11_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT11_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT11_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT11_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT11_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT11_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT11_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT11_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT11_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT11_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT11_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT11_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT11_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT11_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_SET_MUX_SHIFT))&CCM_TARGET_ROOT11_SET_MUX_MASK) +#define CCM_TARGET_ROOT11_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT11_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT11_CLR Bit Fields */ +#define CCM_TARGET_ROOT11_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT11_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT11_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT11_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT11_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT11_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT11_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT11_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT11_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT11_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT11_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT11_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT11_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_CLR_MUX_SHIFT))&CCM_TARGET_ROOT11_CLR_MUX_MASK) +#define CCM_TARGET_ROOT11_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT11_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT11_TOG Bit Fields */ +#define CCM_TARGET_ROOT11_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT11_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT11_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT11_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT11_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT11_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT11_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT11_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT11_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT11_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT11_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT11_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT11_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT11_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT11_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT11_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT11_TOG_MUX_SHIFT))&CCM_TARGET_ROOT11_TOG_MUX_MASK) +#define CCM_TARGET_ROOT11_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT11_TOG_ENABLE_SHIFT 28 +/* POST11 Bit Fields */ +#define CCM_POST11_POST_PODF_MASK 0x3Fu +#define CCM_POST11_POST_PODF_SHIFT 0 +#define CCM_POST11_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST11_POST_PODF_SHIFT))&CCM_POST11_POST_PODF_MASK) +#define CCM_POST11_BUSY1_MASK 0x80u +#define CCM_POST11_BUSY1_SHIFT 7 +#define CCM_POST11_AUTO_PODF_MASK 0x700u +#define CCM_POST11_AUTO_PODF_SHIFT 8 +#define CCM_POST11_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST11_AUTO_PODF_SHIFT))&CCM_POST11_AUTO_PODF_MASK) +#define CCM_POST11_AUTO_EN_MASK 0x1000u +#define CCM_POST11_AUTO_EN_SHIFT 12 +#define CCM_POST11_SLOW_MASK 0x8000u +#define CCM_POST11_SLOW_SHIFT 15 +#define CCM_POST11_SELECT_MASK 0x10000000u +#define CCM_POST11_SELECT_SHIFT 28 +#define CCM_POST11_BUSY2_MASK 0x80000000u +#define CCM_POST11_BUSY2_SHIFT 31 +/* POST_ROOT11_SET Bit Fields */ +#define CCM_POST_ROOT11_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT11_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT11_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_SET_POST_PODF_SHIFT))&CCM_POST_ROOT11_SET_POST_PODF_MASK) +#define CCM_POST_ROOT11_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT11_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT11_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT11_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT11_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT11_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT11_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT11_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT11_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT11_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT11_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT11_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT11_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT11_SET_BUSY2_SHIFT 31 +/* POST_ROOT11_CLR Bit Fields */ +#define CCM_POST_ROOT11_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT11_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT11_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT11_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT11_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT11_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT11_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT11_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT11_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT11_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT11_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT11_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT11_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT11_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT11_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT11_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT11_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT11_CLR_BUSY2_SHIFT 31 +/* POST_ROOT11_TOG Bit Fields */ +#define CCM_POST_ROOT11_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT11_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT11_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT11_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT11_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT11_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT11_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT11_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT11_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT11_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT11_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT11_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT11_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT11_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT11_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT11_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT11_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT11_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT11_TOG_BUSY2_SHIFT 31 +/* PRE11 Bit Fields */ +#define CCM_PRE11_PRE_PODF_B_MASK 0x7u +#define CCM_PRE11_PRE_PODF_B_SHIFT 0 +#define CCM_PRE11_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_PRE_PODF_B_SHIFT))&CCM_PRE11_PRE_PODF_B_MASK) +#define CCM_PRE11_BUSY0_MASK 0x8u +#define CCM_PRE11_BUSY0_SHIFT 3 +#define CCM_PRE11_MUX_B_MASK 0x700u +#define CCM_PRE11_MUX_B_SHIFT 8 +#define CCM_PRE11_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_MUX_B_SHIFT))&CCM_PRE11_MUX_B_MASK) +#define CCM_PRE11_EN_B_MASK 0x1000u +#define CCM_PRE11_EN_B_SHIFT 12 +#define CCM_PRE11_BUSY1_MASK 0x8000u +#define CCM_PRE11_BUSY1_SHIFT 15 +#define CCM_PRE11_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE11_PRE_PODF_A_SHIFT 16 +#define CCM_PRE11_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_PRE_PODF_A_SHIFT))&CCM_PRE11_PRE_PODF_A_MASK) +#define CCM_PRE11_BUSY3_MASK 0x80000u +#define CCM_PRE11_BUSY3_SHIFT 19 +#define CCM_PRE11_MUX_A_MASK 0x7000000u +#define CCM_PRE11_MUX_A_SHIFT 24 +#define CCM_PRE11_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE11_MUX_A_SHIFT))&CCM_PRE11_MUX_A_MASK) +#define CCM_PRE11_EN_A_MASK 0x10000000u +#define CCM_PRE11_EN_A_SHIFT 28 +#define CCM_PRE11_BUSY4_MASK 0x80000000u +#define CCM_PRE11_BUSY4_SHIFT 31 +/* PRE_ROOT11_SET Bit Fields */ +#define CCM_PRE_ROOT11_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT11_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT11_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT11_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT11_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT11_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT11_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT11_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT11_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_MUX_B_SHIFT))&CCM_PRE_ROOT11_SET_MUX_B_MASK) +#define CCM_PRE_ROOT11_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT11_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT11_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT11_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT11_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT11_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT11_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT11_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT11_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT11_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT11_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT11_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT11_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_SET_MUX_A_SHIFT))&CCM_PRE_ROOT11_SET_MUX_A_MASK) +#define CCM_PRE_ROOT11_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT11_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT11_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT11_SET_BUSY4_SHIFT 31 +/* PRE_ROOT11_CLR Bit Fields */ +#define CCM_PRE_ROOT11_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT11_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT11_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT11_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT11_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT11_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT11_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT11_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT11_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT11_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT11_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT11_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT11_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT11_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT11_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT11_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT11_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT11_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT11_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT11_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT11_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT11_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT11_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT11_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT11_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT11_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT11_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT11_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT11_TOG Bit Fields */ +#define CCM_PRE_ROOT11_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT11_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT11_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT11_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT11_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT11_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT11_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT11_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT11_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT11_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT11_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT11_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT11_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT11_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT11_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT11_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT11_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT11_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT11_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT11_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT11_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT11_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT11_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT11_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT11_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT11_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT11_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT11_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT11_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL11 Bit Fields */ +#define CCM_ACCESS_CTRL11_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL11_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL11_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL11_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL11_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL11_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL11_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL11_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL11_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL11_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL11_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL11_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL11_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL11_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL11_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL11_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL11_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL11_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL11_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL11_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL11_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL11_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL11_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL11_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL11_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL11_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL11_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL11_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL11_LOCK_SHIFT 31 +/* ACCESS_CTRL11_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL11_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL11_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL11_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL11_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL11_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL11_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL11_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL11_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL11_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL11_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL11_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL11_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL11_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL11_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL11_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL11_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL11_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL11_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT12 Bit Fields */ +#define CCM_TARGET_ROOT12_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT12_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT12_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_POST_PODF_MASK) +#define CCM_TARGET_ROOT12_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT12_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT12_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT12_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT12_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT12_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT12_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT12_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT12_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT12_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_PRE_PODF_MASK) +#define CCM_TARGET_ROOT12_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT12_MUX_SHIFT 24 +#define CCM_TARGET_ROOT12_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_MUX_SHIFT))&CCM_TARGET_ROOT12_MUX_MASK) +#define CCM_TARGET_ROOT12_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT12_ENABLE_SHIFT 28 +/* TARGET_ROOT12_SET Bit Fields */ +#define CCM_TARGET_ROOT12_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT12_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT12_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT12_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT12_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT12_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT12_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT12_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT12_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT12_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT12_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT12_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT12_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT12_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT12_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT12_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_SET_MUX_SHIFT))&CCM_TARGET_ROOT12_SET_MUX_MASK) +#define CCM_TARGET_ROOT12_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT12_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT12_CLR Bit Fields */ +#define CCM_TARGET_ROOT12_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT12_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT12_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT12_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT12_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT12_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT12_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT12_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT12_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT12_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT12_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT12_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT12_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_CLR_MUX_SHIFT))&CCM_TARGET_ROOT12_CLR_MUX_MASK) +#define CCM_TARGET_ROOT12_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT12_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT12_TOG Bit Fields */ +#define CCM_TARGET_ROOT12_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT12_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT12_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT12_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT12_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT12_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT12_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT12_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT12_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT12_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT12_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT12_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT12_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT12_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT12_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT12_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT12_TOG_MUX_SHIFT))&CCM_TARGET_ROOT12_TOG_MUX_MASK) +#define CCM_TARGET_ROOT12_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT12_TOG_ENABLE_SHIFT 28 +/* POST12 Bit Fields */ +#define CCM_POST12_POST_PODF_MASK 0x3Fu +#define CCM_POST12_POST_PODF_SHIFT 0 +#define CCM_POST12_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST12_POST_PODF_SHIFT))&CCM_POST12_POST_PODF_MASK) +#define CCM_POST12_BUSY1_MASK 0x80u +#define CCM_POST12_BUSY1_SHIFT 7 +#define CCM_POST12_AUTO_PODF_MASK 0x700u +#define CCM_POST12_AUTO_PODF_SHIFT 8 +#define CCM_POST12_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST12_AUTO_PODF_SHIFT))&CCM_POST12_AUTO_PODF_MASK) +#define CCM_POST12_AUTO_EN_MASK 0x1000u +#define CCM_POST12_AUTO_EN_SHIFT 12 +#define CCM_POST12_SLOW_MASK 0x8000u +#define CCM_POST12_SLOW_SHIFT 15 +#define CCM_POST12_SELECT_MASK 0x10000000u +#define CCM_POST12_SELECT_SHIFT 28 +#define CCM_POST12_BUSY2_MASK 0x80000000u +#define CCM_POST12_BUSY2_SHIFT 31 +/* POST_ROOT12_SET Bit Fields */ +#define CCM_POST_ROOT12_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT12_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT12_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_SET_POST_PODF_SHIFT))&CCM_POST_ROOT12_SET_POST_PODF_MASK) +#define CCM_POST_ROOT12_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT12_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT12_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT12_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT12_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT12_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT12_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT12_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT12_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT12_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT12_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT12_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT12_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT12_SET_BUSY2_SHIFT 31 +/* POST_ROOT12_CLR Bit Fields */ +#define CCM_POST_ROOT12_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT12_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT12_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT12_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT12_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT12_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT12_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT12_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT12_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT12_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT12_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT12_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT12_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT12_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT12_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT12_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT12_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT12_CLR_BUSY2_SHIFT 31 +/* POST_ROOT12_TOG Bit Fields */ +#define CCM_POST_ROOT12_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT12_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT12_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT12_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT12_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT12_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT12_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT12_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT12_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT12_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT12_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT12_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT12_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT12_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT12_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT12_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT12_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT12_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT12_TOG_BUSY2_SHIFT 31 +/* PRE12 Bit Fields */ +#define CCM_PRE12_PRE_PODF_B_MASK 0x7u +#define CCM_PRE12_PRE_PODF_B_SHIFT 0 +#define CCM_PRE12_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_PRE_PODF_B_SHIFT))&CCM_PRE12_PRE_PODF_B_MASK) +#define CCM_PRE12_BUSY0_MASK 0x8u +#define CCM_PRE12_BUSY0_SHIFT 3 +#define CCM_PRE12_MUX_B_MASK 0x700u +#define CCM_PRE12_MUX_B_SHIFT 8 +#define CCM_PRE12_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_MUX_B_SHIFT))&CCM_PRE12_MUX_B_MASK) +#define CCM_PRE12_EN_B_MASK 0x1000u +#define CCM_PRE12_EN_B_SHIFT 12 +#define CCM_PRE12_BUSY1_MASK 0x8000u +#define CCM_PRE12_BUSY1_SHIFT 15 +#define CCM_PRE12_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE12_PRE_PODF_A_SHIFT 16 +#define CCM_PRE12_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_PRE_PODF_A_SHIFT))&CCM_PRE12_PRE_PODF_A_MASK) +#define CCM_PRE12_BUSY3_MASK 0x80000u +#define CCM_PRE12_BUSY3_SHIFT 19 +#define CCM_PRE12_MUX_A_MASK 0x7000000u +#define CCM_PRE12_MUX_A_SHIFT 24 +#define CCM_PRE12_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE12_MUX_A_SHIFT))&CCM_PRE12_MUX_A_MASK) +#define CCM_PRE12_EN_A_MASK 0x10000000u +#define CCM_PRE12_EN_A_SHIFT 28 +#define CCM_PRE12_BUSY4_MASK 0x80000000u +#define CCM_PRE12_BUSY4_SHIFT 31 +/* PRE_ROOT12_SET Bit Fields */ +#define CCM_PRE_ROOT12_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT12_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT12_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT12_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT12_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT12_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT12_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT12_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT12_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_MUX_B_SHIFT))&CCM_PRE_ROOT12_SET_MUX_B_MASK) +#define CCM_PRE_ROOT12_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT12_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT12_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT12_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT12_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT12_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT12_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT12_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT12_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT12_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT12_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT12_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT12_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_SET_MUX_A_SHIFT))&CCM_PRE_ROOT12_SET_MUX_A_MASK) +#define CCM_PRE_ROOT12_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT12_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT12_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT12_SET_BUSY4_SHIFT 31 +/* PRE_ROOT12_CLR Bit Fields */ +#define CCM_PRE_ROOT12_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT12_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT12_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT12_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT12_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT12_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT12_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT12_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT12_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT12_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT12_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT12_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT12_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT12_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT12_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT12_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT12_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT12_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT12_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT12_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT12_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT12_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT12_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT12_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT12_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT12_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT12_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT12_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT12_TOG Bit Fields */ +#define CCM_PRE_ROOT12_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT12_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT12_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT12_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT12_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT12_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT12_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT12_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT12_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT12_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT12_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT12_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT12_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT12_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT12_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT12_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT12_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT12_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT12_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT12_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT12_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT12_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT12_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT12_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT12_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT12_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT12_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT12_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT12_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL12 Bit Fields */ +#define CCM_ACCESS_CTRL12_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL12_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL12_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL12_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL12_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL12_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL12_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL12_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL12_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL12_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL12_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL12_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL12_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL12_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL12_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL12_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL12_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL12_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL12_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL12_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL12_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL12_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL12_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL12_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL12_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL12_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL12_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL12_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL12_LOCK_SHIFT 31 +/* ACCESS_CTRL12_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL12_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL12_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL12_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL12_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL12_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL12_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL12_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL12_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL12_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL12_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL12_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL12_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL12_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL12_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL12_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL12_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL12_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL12_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT13 Bit Fields */ +#define CCM_TARGET_ROOT13_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT13_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT13_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_POST_PODF_MASK) +#define CCM_TARGET_ROOT13_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT13_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT13_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT13_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT13_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT13_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT13_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT13_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT13_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT13_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_PRE_PODF_MASK) +#define CCM_TARGET_ROOT13_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT13_MUX_SHIFT 24 +#define CCM_TARGET_ROOT13_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_MUX_SHIFT))&CCM_TARGET_ROOT13_MUX_MASK) +#define CCM_TARGET_ROOT13_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT13_ENABLE_SHIFT 28 +/* TARGET_ROOT13_SET Bit Fields */ +#define CCM_TARGET_ROOT13_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT13_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT13_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT13_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT13_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT13_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT13_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT13_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT13_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT13_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT13_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT13_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT13_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT13_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT13_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT13_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_SET_MUX_SHIFT))&CCM_TARGET_ROOT13_SET_MUX_MASK) +#define CCM_TARGET_ROOT13_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT13_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT13_CLR Bit Fields */ +#define CCM_TARGET_ROOT13_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT13_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT13_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT13_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT13_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT13_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT13_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT13_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT13_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT13_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT13_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT13_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT13_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_CLR_MUX_SHIFT))&CCM_TARGET_ROOT13_CLR_MUX_MASK) +#define CCM_TARGET_ROOT13_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT13_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT13_TOG Bit Fields */ +#define CCM_TARGET_ROOT13_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT13_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT13_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT13_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT13_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT13_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT13_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT13_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT13_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT13_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT13_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT13_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT13_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT13_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT13_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT13_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT13_TOG_MUX_SHIFT))&CCM_TARGET_ROOT13_TOG_MUX_MASK) +#define CCM_TARGET_ROOT13_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT13_TOG_ENABLE_SHIFT 28 +/* POST13 Bit Fields */ +#define CCM_POST13_POST_PODF_MASK 0x3Fu +#define CCM_POST13_POST_PODF_SHIFT 0 +#define CCM_POST13_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST13_POST_PODF_SHIFT))&CCM_POST13_POST_PODF_MASK) +#define CCM_POST13_BUSY1_MASK 0x80u +#define CCM_POST13_BUSY1_SHIFT 7 +#define CCM_POST13_AUTO_PODF_MASK 0x700u +#define CCM_POST13_AUTO_PODF_SHIFT 8 +#define CCM_POST13_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST13_AUTO_PODF_SHIFT))&CCM_POST13_AUTO_PODF_MASK) +#define CCM_POST13_AUTO_EN_MASK 0x1000u +#define CCM_POST13_AUTO_EN_SHIFT 12 +#define CCM_POST13_SLOW_MASK 0x8000u +#define CCM_POST13_SLOW_SHIFT 15 +#define CCM_POST13_SELECT_MASK 0x10000000u +#define CCM_POST13_SELECT_SHIFT 28 +#define CCM_POST13_BUSY2_MASK 0x80000000u +#define CCM_POST13_BUSY2_SHIFT 31 +/* POST_ROOT13_SET Bit Fields */ +#define CCM_POST_ROOT13_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT13_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT13_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_SET_POST_PODF_SHIFT))&CCM_POST_ROOT13_SET_POST_PODF_MASK) +#define CCM_POST_ROOT13_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT13_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT13_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT13_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT13_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT13_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT13_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT13_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT13_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT13_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT13_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT13_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT13_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT13_SET_BUSY2_SHIFT 31 +/* POST_ROOT13_CLR Bit Fields */ +#define CCM_POST_ROOT13_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT13_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT13_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT13_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT13_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT13_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT13_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT13_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT13_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT13_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT13_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT13_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT13_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT13_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT13_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT13_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT13_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT13_CLR_BUSY2_SHIFT 31 +/* POST_ROOT13_TOG Bit Fields */ +#define CCM_POST_ROOT13_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT13_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT13_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT13_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT13_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT13_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT13_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT13_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT13_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT13_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT13_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT13_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT13_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT13_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT13_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT13_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT13_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT13_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT13_TOG_BUSY2_SHIFT 31 +/* PRE13 Bit Fields */ +#define CCM_PRE13_PRE_PODF_B_MASK 0x7u +#define CCM_PRE13_PRE_PODF_B_SHIFT 0 +#define CCM_PRE13_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_PRE_PODF_B_SHIFT))&CCM_PRE13_PRE_PODF_B_MASK) +#define CCM_PRE13_BUSY0_MASK 0x8u +#define CCM_PRE13_BUSY0_SHIFT 3 +#define CCM_PRE13_MUX_B_MASK 0x700u +#define CCM_PRE13_MUX_B_SHIFT 8 +#define CCM_PRE13_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_MUX_B_SHIFT))&CCM_PRE13_MUX_B_MASK) +#define CCM_PRE13_EN_B_MASK 0x1000u +#define CCM_PRE13_EN_B_SHIFT 12 +#define CCM_PRE13_BUSY1_MASK 0x8000u +#define CCM_PRE13_BUSY1_SHIFT 15 +#define CCM_PRE13_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE13_PRE_PODF_A_SHIFT 16 +#define CCM_PRE13_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_PRE_PODF_A_SHIFT))&CCM_PRE13_PRE_PODF_A_MASK) +#define CCM_PRE13_BUSY3_MASK 0x80000u +#define CCM_PRE13_BUSY3_SHIFT 19 +#define CCM_PRE13_MUX_A_MASK 0x7000000u +#define CCM_PRE13_MUX_A_SHIFT 24 +#define CCM_PRE13_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE13_MUX_A_SHIFT))&CCM_PRE13_MUX_A_MASK) +#define CCM_PRE13_EN_A_MASK 0x10000000u +#define CCM_PRE13_EN_A_SHIFT 28 +#define CCM_PRE13_BUSY4_MASK 0x80000000u +#define CCM_PRE13_BUSY4_SHIFT 31 +/* PRE_ROOT13_SET Bit Fields */ +#define CCM_PRE_ROOT13_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT13_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT13_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT13_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT13_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT13_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT13_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT13_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT13_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_MUX_B_SHIFT))&CCM_PRE_ROOT13_SET_MUX_B_MASK) +#define CCM_PRE_ROOT13_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT13_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT13_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT13_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT13_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT13_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT13_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT13_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT13_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT13_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT13_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT13_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT13_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_SET_MUX_A_SHIFT))&CCM_PRE_ROOT13_SET_MUX_A_MASK) +#define CCM_PRE_ROOT13_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT13_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT13_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT13_SET_BUSY4_SHIFT 31 +/* PRE_ROOT13_CLR Bit Fields */ +#define CCM_PRE_ROOT13_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT13_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT13_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT13_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT13_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT13_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT13_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT13_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT13_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT13_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT13_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT13_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT13_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT13_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT13_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT13_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT13_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT13_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT13_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT13_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT13_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT13_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT13_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT13_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT13_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT13_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT13_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT13_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT13_TOG Bit Fields */ +#define CCM_PRE_ROOT13_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT13_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT13_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT13_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT13_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT13_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT13_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT13_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT13_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT13_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT13_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT13_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT13_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT13_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT13_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT13_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT13_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT13_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT13_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT13_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT13_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT13_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT13_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT13_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT13_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT13_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT13_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT13_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT13_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL13 Bit Fields */ +#define CCM_ACCESS_CTRL13_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL13_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL13_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL13_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL13_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL13_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL13_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL13_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL13_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL13_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL13_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL13_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL13_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL13_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL13_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL13_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL13_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL13_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL13_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL13_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL13_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL13_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL13_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL13_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL13_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL13_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL13_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL13_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL13_LOCK_SHIFT 31 +/* ACCESS_CTRL13_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL13_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL13_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL13_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL13_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL13_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL13_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL13_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL13_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL13_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL13_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL13_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL13_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL13_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL13_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL13_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL13_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL13_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL13_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT14 Bit Fields */ +#define CCM_TARGET_ROOT14_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT14_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT14_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_POST_PODF_MASK) +#define CCM_TARGET_ROOT14_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT14_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT14_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT14_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT14_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT14_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT14_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT14_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT14_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT14_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_PRE_PODF_MASK) +#define CCM_TARGET_ROOT14_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT14_MUX_SHIFT 24 +#define CCM_TARGET_ROOT14_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_MUX_SHIFT))&CCM_TARGET_ROOT14_MUX_MASK) +#define CCM_TARGET_ROOT14_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT14_ENABLE_SHIFT 28 +/* TARGET_ROOT14_SET Bit Fields */ +#define CCM_TARGET_ROOT14_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT14_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT14_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT14_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT14_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT14_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT14_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT14_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT14_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT14_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT14_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT14_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT14_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT14_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT14_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT14_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_SET_MUX_SHIFT))&CCM_TARGET_ROOT14_SET_MUX_MASK) +#define CCM_TARGET_ROOT14_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT14_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT14_CLR Bit Fields */ +#define CCM_TARGET_ROOT14_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT14_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT14_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT14_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT14_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT14_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT14_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT14_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT14_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT14_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT14_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT14_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT14_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_CLR_MUX_SHIFT))&CCM_TARGET_ROOT14_CLR_MUX_MASK) +#define CCM_TARGET_ROOT14_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT14_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT14_TOG Bit Fields */ +#define CCM_TARGET_ROOT14_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT14_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT14_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT14_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT14_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT14_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT14_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT14_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT14_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT14_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT14_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT14_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT14_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT14_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT14_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT14_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT14_TOG_MUX_SHIFT))&CCM_TARGET_ROOT14_TOG_MUX_MASK) +#define CCM_TARGET_ROOT14_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT14_TOG_ENABLE_SHIFT 28 +/* POST14 Bit Fields */ +#define CCM_POST14_POST_PODF_MASK 0x3Fu +#define CCM_POST14_POST_PODF_SHIFT 0 +#define CCM_POST14_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST14_POST_PODF_SHIFT))&CCM_POST14_POST_PODF_MASK) +#define CCM_POST14_BUSY1_MASK 0x80u +#define CCM_POST14_BUSY1_SHIFT 7 +#define CCM_POST14_AUTO_PODF_MASK 0x700u +#define CCM_POST14_AUTO_PODF_SHIFT 8 +#define CCM_POST14_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST14_AUTO_PODF_SHIFT))&CCM_POST14_AUTO_PODF_MASK) +#define CCM_POST14_AUTO_EN_MASK 0x1000u +#define CCM_POST14_AUTO_EN_SHIFT 12 +#define CCM_POST14_SLOW_MASK 0x8000u +#define CCM_POST14_SLOW_SHIFT 15 +#define CCM_POST14_SELECT_MASK 0x10000000u +#define CCM_POST14_SELECT_SHIFT 28 +#define CCM_POST14_BUSY2_MASK 0x80000000u +#define CCM_POST14_BUSY2_SHIFT 31 +/* POST_ROOT14_SET Bit Fields */ +#define CCM_POST_ROOT14_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT14_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT14_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_SET_POST_PODF_SHIFT))&CCM_POST_ROOT14_SET_POST_PODF_MASK) +#define CCM_POST_ROOT14_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT14_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT14_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT14_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT14_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT14_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT14_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT14_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT14_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT14_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT14_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT14_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT14_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT14_SET_BUSY2_SHIFT 31 +/* POST_ROOT14_CLR Bit Fields */ +#define CCM_POST_ROOT14_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT14_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT14_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT14_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT14_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT14_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT14_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT14_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT14_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT14_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT14_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT14_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT14_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT14_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT14_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT14_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT14_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT14_CLR_BUSY2_SHIFT 31 +/* POST_ROOT14_TOG Bit Fields */ +#define CCM_POST_ROOT14_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT14_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT14_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT14_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT14_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT14_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT14_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT14_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT14_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT14_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT14_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT14_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT14_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT14_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT14_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT14_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT14_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT14_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT14_TOG_BUSY2_SHIFT 31 +/* PRE14 Bit Fields */ +#define CCM_PRE14_PRE_PODF_B_MASK 0x7u +#define CCM_PRE14_PRE_PODF_B_SHIFT 0 +#define CCM_PRE14_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_PRE_PODF_B_SHIFT))&CCM_PRE14_PRE_PODF_B_MASK) +#define CCM_PRE14_BUSY0_MASK 0x8u +#define CCM_PRE14_BUSY0_SHIFT 3 +#define CCM_PRE14_MUX_B_MASK 0x700u +#define CCM_PRE14_MUX_B_SHIFT 8 +#define CCM_PRE14_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_MUX_B_SHIFT))&CCM_PRE14_MUX_B_MASK) +#define CCM_PRE14_EN_B_MASK 0x1000u +#define CCM_PRE14_EN_B_SHIFT 12 +#define CCM_PRE14_BUSY1_MASK 0x8000u +#define CCM_PRE14_BUSY1_SHIFT 15 +#define CCM_PRE14_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE14_PRE_PODF_A_SHIFT 16 +#define CCM_PRE14_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_PRE_PODF_A_SHIFT))&CCM_PRE14_PRE_PODF_A_MASK) +#define CCM_PRE14_BUSY3_MASK 0x80000u +#define CCM_PRE14_BUSY3_SHIFT 19 +#define CCM_PRE14_MUX_A_MASK 0x7000000u +#define CCM_PRE14_MUX_A_SHIFT 24 +#define CCM_PRE14_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE14_MUX_A_SHIFT))&CCM_PRE14_MUX_A_MASK) +#define CCM_PRE14_EN_A_MASK 0x10000000u +#define CCM_PRE14_EN_A_SHIFT 28 +#define CCM_PRE14_BUSY4_MASK 0x80000000u +#define CCM_PRE14_BUSY4_SHIFT 31 +/* PRE_ROOT14_SET Bit Fields */ +#define CCM_PRE_ROOT14_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT14_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT14_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT14_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT14_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT14_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT14_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT14_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT14_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_MUX_B_SHIFT))&CCM_PRE_ROOT14_SET_MUX_B_MASK) +#define CCM_PRE_ROOT14_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT14_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT14_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT14_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT14_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT14_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT14_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT14_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT14_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT14_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT14_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT14_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT14_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_SET_MUX_A_SHIFT))&CCM_PRE_ROOT14_SET_MUX_A_MASK) +#define CCM_PRE_ROOT14_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT14_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT14_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT14_SET_BUSY4_SHIFT 31 +/* PRE_ROOT14_CLR Bit Fields */ +#define CCM_PRE_ROOT14_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT14_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT14_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT14_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT14_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT14_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT14_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT14_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT14_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT14_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT14_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT14_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT14_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT14_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT14_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT14_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT14_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT14_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT14_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT14_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT14_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT14_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT14_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT14_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT14_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT14_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT14_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT14_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT14_TOG Bit Fields */ +#define CCM_PRE_ROOT14_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT14_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT14_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT14_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT14_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT14_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT14_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT14_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT14_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT14_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT14_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT14_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT14_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT14_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT14_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT14_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT14_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT14_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT14_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT14_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT14_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT14_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT14_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT14_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT14_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT14_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT14_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT14_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT14_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL14 Bit Fields */ +#define CCM_ACCESS_CTRL14_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL14_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL14_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL14_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL14_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL14_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL14_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL14_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL14_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL14_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL14_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL14_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL14_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL14_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL14_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL14_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL14_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL14_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL14_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL14_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL14_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL14_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL14_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL14_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL14_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL14_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL14_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL14_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL14_LOCK_SHIFT 31 +/* ACCESS_CTRL14_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL14_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL14_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL14_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL14_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL14_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL14_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL14_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL14_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL14_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL14_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL14_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL14_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL14_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL14_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL14_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL14_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL14_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL14_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT15 Bit Fields */ +#define CCM_TARGET_ROOT15_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT15_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT15_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_POST_PODF_MASK) +#define CCM_TARGET_ROOT15_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT15_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT15_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT15_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT15_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT15_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT15_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT15_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT15_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT15_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_PRE_PODF_MASK) +#define CCM_TARGET_ROOT15_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT15_MUX_SHIFT 24 +#define CCM_TARGET_ROOT15_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_MUX_SHIFT))&CCM_TARGET_ROOT15_MUX_MASK) +#define CCM_TARGET_ROOT15_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT15_ENABLE_SHIFT 28 +/* TARGET_ROOT15_SET Bit Fields */ +#define CCM_TARGET_ROOT15_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT15_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT15_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT15_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT15_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT15_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT15_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT15_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT15_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT15_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT15_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT15_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT15_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT15_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT15_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT15_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_SET_MUX_SHIFT))&CCM_TARGET_ROOT15_SET_MUX_MASK) +#define CCM_TARGET_ROOT15_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT15_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT15_CLR Bit Fields */ +#define CCM_TARGET_ROOT15_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT15_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT15_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT15_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT15_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT15_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT15_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT15_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT15_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT15_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT15_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT15_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT15_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_CLR_MUX_SHIFT))&CCM_TARGET_ROOT15_CLR_MUX_MASK) +#define CCM_TARGET_ROOT15_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT15_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT15_TOG Bit Fields */ +#define CCM_TARGET_ROOT15_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT15_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT15_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT15_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT15_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT15_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT15_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT15_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT15_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT15_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT15_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT15_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT15_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT15_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT15_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT15_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT15_TOG_MUX_SHIFT))&CCM_TARGET_ROOT15_TOG_MUX_MASK) +#define CCM_TARGET_ROOT15_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT15_TOG_ENABLE_SHIFT 28 +/* POST15 Bit Fields */ +#define CCM_POST15_POST_PODF_MASK 0x3Fu +#define CCM_POST15_POST_PODF_SHIFT 0 +#define CCM_POST15_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST15_POST_PODF_SHIFT))&CCM_POST15_POST_PODF_MASK) +#define CCM_POST15_BUSY1_MASK 0x80u +#define CCM_POST15_BUSY1_SHIFT 7 +#define CCM_POST15_AUTO_PODF_MASK 0x700u +#define CCM_POST15_AUTO_PODF_SHIFT 8 +#define CCM_POST15_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST15_AUTO_PODF_SHIFT))&CCM_POST15_AUTO_PODF_MASK) +#define CCM_POST15_AUTO_EN_MASK 0x1000u +#define CCM_POST15_AUTO_EN_SHIFT 12 +#define CCM_POST15_SLOW_MASK 0x8000u +#define CCM_POST15_SLOW_SHIFT 15 +#define CCM_POST15_SELECT_MASK 0x10000000u +#define CCM_POST15_SELECT_SHIFT 28 +#define CCM_POST15_BUSY2_MASK 0x80000000u +#define CCM_POST15_BUSY2_SHIFT 31 +/* POST_ROOT15_SET Bit Fields */ +#define CCM_POST_ROOT15_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT15_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT15_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_SET_POST_PODF_SHIFT))&CCM_POST_ROOT15_SET_POST_PODF_MASK) +#define CCM_POST_ROOT15_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT15_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT15_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT15_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT15_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT15_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT15_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT15_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT15_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT15_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT15_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT15_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT15_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT15_SET_BUSY2_SHIFT 31 +/* POST_ROOT15_CLR Bit Fields */ +#define CCM_POST_ROOT15_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT15_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT15_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT15_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT15_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT15_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT15_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT15_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT15_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT15_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT15_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT15_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT15_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT15_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT15_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT15_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT15_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT15_CLR_BUSY2_SHIFT 31 +/* POST_ROOT15_TOG Bit Fields */ +#define CCM_POST_ROOT15_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT15_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT15_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT15_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT15_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT15_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT15_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT15_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT15_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT15_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT15_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT15_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT15_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT15_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT15_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT15_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT15_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT15_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT15_TOG_BUSY2_SHIFT 31 +/* PRE15 Bit Fields */ +#define CCM_PRE15_PRE_PODF_B_MASK 0x7u +#define CCM_PRE15_PRE_PODF_B_SHIFT 0 +#define CCM_PRE15_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_PRE_PODF_B_SHIFT))&CCM_PRE15_PRE_PODF_B_MASK) +#define CCM_PRE15_BUSY0_MASK 0x8u +#define CCM_PRE15_BUSY0_SHIFT 3 +#define CCM_PRE15_MUX_B_MASK 0x700u +#define CCM_PRE15_MUX_B_SHIFT 8 +#define CCM_PRE15_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_MUX_B_SHIFT))&CCM_PRE15_MUX_B_MASK) +#define CCM_PRE15_EN_B_MASK 0x1000u +#define CCM_PRE15_EN_B_SHIFT 12 +#define CCM_PRE15_BUSY1_MASK 0x8000u +#define CCM_PRE15_BUSY1_SHIFT 15 +#define CCM_PRE15_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE15_PRE_PODF_A_SHIFT 16 +#define CCM_PRE15_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_PRE_PODF_A_SHIFT))&CCM_PRE15_PRE_PODF_A_MASK) +#define CCM_PRE15_BUSY3_MASK 0x80000u +#define CCM_PRE15_BUSY3_SHIFT 19 +#define CCM_PRE15_MUX_A_MASK 0x7000000u +#define CCM_PRE15_MUX_A_SHIFT 24 +#define CCM_PRE15_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE15_MUX_A_SHIFT))&CCM_PRE15_MUX_A_MASK) +#define CCM_PRE15_EN_A_MASK 0x10000000u +#define CCM_PRE15_EN_A_SHIFT 28 +#define CCM_PRE15_BUSY4_MASK 0x80000000u +#define CCM_PRE15_BUSY4_SHIFT 31 +/* PRE_ROOT15_SET Bit Fields */ +#define CCM_PRE_ROOT15_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT15_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT15_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT15_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT15_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT15_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT15_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT15_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT15_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_MUX_B_SHIFT))&CCM_PRE_ROOT15_SET_MUX_B_MASK) +#define CCM_PRE_ROOT15_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT15_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT15_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT15_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT15_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT15_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT15_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT15_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT15_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT15_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT15_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT15_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT15_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_SET_MUX_A_SHIFT))&CCM_PRE_ROOT15_SET_MUX_A_MASK) +#define CCM_PRE_ROOT15_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT15_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT15_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT15_SET_BUSY4_SHIFT 31 +/* PRE_ROOT15_CLR Bit Fields */ +#define CCM_PRE_ROOT15_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT15_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT15_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT15_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT15_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT15_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT15_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT15_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT15_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT15_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT15_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT15_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT15_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT15_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT15_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT15_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT15_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT15_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT15_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT15_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT15_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT15_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT15_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT15_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT15_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT15_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT15_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT15_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT15_TOG Bit Fields */ +#define CCM_PRE_ROOT15_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT15_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT15_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT15_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT15_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT15_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT15_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT15_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT15_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT15_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT15_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT15_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT15_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT15_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT15_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT15_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT15_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT15_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT15_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT15_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT15_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT15_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT15_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT15_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT15_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT15_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT15_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT15_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT15_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL15 Bit Fields */ +#define CCM_ACCESS_CTRL15_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL15_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL15_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL15_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL15_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL15_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL15_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL15_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL15_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL15_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL15_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL15_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL15_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL15_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL15_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL15_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL15_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL15_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL15_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL15_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL15_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL15_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL15_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL15_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL15_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL15_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL15_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL15_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL15_LOCK_SHIFT 31 +/* ACCESS_CTRL15_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL15_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL15_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL15_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL15_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL15_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL15_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL15_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL15_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL15_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL15_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL15_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL15_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL15_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL15_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL15_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL15_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL15_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL15_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT16 Bit Fields */ +#define CCM_TARGET_ROOT16_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT16_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT16_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_POST_PODF_MASK) +#define CCM_TARGET_ROOT16_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT16_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT16_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT16_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT16_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT16_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT16_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT16_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT16_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT16_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_PRE_PODF_MASK) +#define CCM_TARGET_ROOT16_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT16_MUX_SHIFT 24 +#define CCM_TARGET_ROOT16_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_MUX_SHIFT))&CCM_TARGET_ROOT16_MUX_MASK) +#define CCM_TARGET_ROOT16_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT16_ENABLE_SHIFT 28 +/* TARGET_ROOT16_SET Bit Fields */ +#define CCM_TARGET_ROOT16_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT16_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT16_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT16_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT16_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT16_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT16_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT16_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT16_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT16_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT16_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT16_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT16_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT16_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT16_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT16_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_SET_MUX_SHIFT))&CCM_TARGET_ROOT16_SET_MUX_MASK) +#define CCM_TARGET_ROOT16_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT16_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT16_CLR Bit Fields */ +#define CCM_TARGET_ROOT16_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT16_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT16_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT16_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT16_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT16_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT16_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT16_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT16_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT16_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT16_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT16_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT16_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_CLR_MUX_SHIFT))&CCM_TARGET_ROOT16_CLR_MUX_MASK) +#define CCM_TARGET_ROOT16_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT16_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT16_TOG Bit Fields */ +#define CCM_TARGET_ROOT16_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT16_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT16_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT16_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT16_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT16_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT16_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT16_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT16_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT16_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT16_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT16_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT16_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT16_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT16_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT16_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT16_TOG_MUX_SHIFT))&CCM_TARGET_ROOT16_TOG_MUX_MASK) +#define CCM_TARGET_ROOT16_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT16_TOG_ENABLE_SHIFT 28 +/* POST16 Bit Fields */ +#define CCM_POST16_POST_PODF_MASK 0x3Fu +#define CCM_POST16_POST_PODF_SHIFT 0 +#define CCM_POST16_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST16_POST_PODF_SHIFT))&CCM_POST16_POST_PODF_MASK) +#define CCM_POST16_BUSY1_MASK 0x80u +#define CCM_POST16_BUSY1_SHIFT 7 +#define CCM_POST16_AUTO_PODF_MASK 0x700u +#define CCM_POST16_AUTO_PODF_SHIFT 8 +#define CCM_POST16_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST16_AUTO_PODF_SHIFT))&CCM_POST16_AUTO_PODF_MASK) +#define CCM_POST16_AUTO_EN_MASK 0x1000u +#define CCM_POST16_AUTO_EN_SHIFT 12 +#define CCM_POST16_SLOW_MASK 0x8000u +#define CCM_POST16_SLOW_SHIFT 15 +#define CCM_POST16_SELECT_MASK 0x10000000u +#define CCM_POST16_SELECT_SHIFT 28 +#define CCM_POST16_BUSY2_MASK 0x80000000u +#define CCM_POST16_BUSY2_SHIFT 31 +/* POST_ROOT16_SET Bit Fields */ +#define CCM_POST_ROOT16_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT16_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT16_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_SET_POST_PODF_SHIFT))&CCM_POST_ROOT16_SET_POST_PODF_MASK) +#define CCM_POST_ROOT16_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT16_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT16_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT16_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT16_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT16_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT16_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT16_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT16_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT16_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT16_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT16_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT16_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT16_SET_BUSY2_SHIFT 31 +/* POST_ROOT16_CLR Bit Fields */ +#define CCM_POST_ROOT16_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT16_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT16_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT16_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT16_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT16_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT16_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT16_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT16_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT16_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT16_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT16_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT16_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT16_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT16_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT16_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT16_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT16_CLR_BUSY2_SHIFT 31 +/* POST_ROOT16_TOG Bit Fields */ +#define CCM_POST_ROOT16_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT16_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT16_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT16_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT16_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT16_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT16_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT16_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT16_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT16_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT16_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT16_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT16_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT16_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT16_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT16_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT16_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT16_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT16_TOG_BUSY2_SHIFT 31 +/* PRE16 Bit Fields */ +#define CCM_PRE16_PRE_PODF_B_MASK 0x7u +#define CCM_PRE16_PRE_PODF_B_SHIFT 0 +#define CCM_PRE16_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_PRE_PODF_B_SHIFT))&CCM_PRE16_PRE_PODF_B_MASK) +#define CCM_PRE16_BUSY0_MASK 0x8u +#define CCM_PRE16_BUSY0_SHIFT 3 +#define CCM_PRE16_MUX_B_MASK 0x700u +#define CCM_PRE16_MUX_B_SHIFT 8 +#define CCM_PRE16_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_MUX_B_SHIFT))&CCM_PRE16_MUX_B_MASK) +#define CCM_PRE16_EN_B_MASK 0x1000u +#define CCM_PRE16_EN_B_SHIFT 12 +#define CCM_PRE16_BUSY1_MASK 0x8000u +#define CCM_PRE16_BUSY1_SHIFT 15 +#define CCM_PRE16_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE16_PRE_PODF_A_SHIFT 16 +#define CCM_PRE16_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_PRE_PODF_A_SHIFT))&CCM_PRE16_PRE_PODF_A_MASK) +#define CCM_PRE16_BUSY3_MASK 0x80000u +#define CCM_PRE16_BUSY3_SHIFT 19 +#define CCM_PRE16_MUX_A_MASK 0x7000000u +#define CCM_PRE16_MUX_A_SHIFT 24 +#define CCM_PRE16_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE16_MUX_A_SHIFT))&CCM_PRE16_MUX_A_MASK) +#define CCM_PRE16_EN_A_MASK 0x10000000u +#define CCM_PRE16_EN_A_SHIFT 28 +#define CCM_PRE16_BUSY4_MASK 0x80000000u +#define CCM_PRE16_BUSY4_SHIFT 31 +/* PRE_ROOT16_SET Bit Fields */ +#define CCM_PRE_ROOT16_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT16_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT16_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT16_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT16_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT16_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT16_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT16_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT16_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_MUX_B_SHIFT))&CCM_PRE_ROOT16_SET_MUX_B_MASK) +#define CCM_PRE_ROOT16_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT16_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT16_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT16_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT16_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT16_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT16_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT16_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT16_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT16_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT16_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT16_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT16_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_SET_MUX_A_SHIFT))&CCM_PRE_ROOT16_SET_MUX_A_MASK) +#define CCM_PRE_ROOT16_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT16_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT16_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT16_SET_BUSY4_SHIFT 31 +/* PRE_ROOT16_CLR Bit Fields */ +#define CCM_PRE_ROOT16_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT16_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT16_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT16_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT16_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT16_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT16_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT16_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT16_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT16_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT16_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT16_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT16_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT16_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT16_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT16_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT16_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT16_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT16_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT16_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT16_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT16_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT16_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT16_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT16_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT16_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT16_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT16_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT16_TOG Bit Fields */ +#define CCM_PRE_ROOT16_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT16_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT16_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT16_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT16_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT16_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT16_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT16_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT16_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT16_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT16_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT16_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT16_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT16_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT16_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT16_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT16_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT16_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT16_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT16_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT16_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT16_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT16_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT16_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT16_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT16_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT16_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT16_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT16_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL16 Bit Fields */ +#define CCM_ACCESS_CTRL16_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL16_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL16_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL16_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL16_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL16_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL16_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL16_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL16_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL16_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL16_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL16_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL16_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL16_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL16_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL16_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL16_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL16_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL16_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL16_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL16_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL16_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL16_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL16_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL16_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL16_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL16_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL16_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL16_LOCK_SHIFT 31 +/* ACCESS_CTRL16_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL16_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL16_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL16_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL16_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL16_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL16_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL16_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL16_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL16_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL16_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL16_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL16_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL16_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL16_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL16_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL16_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL16_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL16_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT17 Bit Fields */ +#define CCM_TARGET_ROOT17_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT17_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT17_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_POST_PODF_MASK) +#define CCM_TARGET_ROOT17_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT17_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT17_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT17_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT17_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT17_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT17_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT17_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT17_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT17_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_PRE_PODF_MASK) +#define CCM_TARGET_ROOT17_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT17_MUX_SHIFT 24 +#define CCM_TARGET_ROOT17_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_MUX_SHIFT))&CCM_TARGET_ROOT17_MUX_MASK) +#define CCM_TARGET_ROOT17_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT17_ENABLE_SHIFT 28 +/* TARGET_ROOT17_SET Bit Fields */ +#define CCM_TARGET_ROOT17_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT17_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT17_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT17_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT17_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT17_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT17_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT17_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT17_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT17_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT17_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT17_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT17_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT17_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT17_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT17_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_SET_MUX_SHIFT))&CCM_TARGET_ROOT17_SET_MUX_MASK) +#define CCM_TARGET_ROOT17_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT17_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT17_CLR Bit Fields */ +#define CCM_TARGET_ROOT17_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT17_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT17_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT17_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT17_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT17_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT17_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT17_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT17_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT17_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT17_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT17_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT17_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_CLR_MUX_SHIFT))&CCM_TARGET_ROOT17_CLR_MUX_MASK) +#define CCM_TARGET_ROOT17_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT17_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT17_TOG Bit Fields */ +#define CCM_TARGET_ROOT17_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT17_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT17_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT17_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT17_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT17_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT17_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT17_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT17_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT17_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT17_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT17_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT17_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT17_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT17_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT17_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT17_TOG_MUX_SHIFT))&CCM_TARGET_ROOT17_TOG_MUX_MASK) +#define CCM_TARGET_ROOT17_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT17_TOG_ENABLE_SHIFT 28 +/* POST17 Bit Fields */ +#define CCM_POST17_POST_PODF_MASK 0x3Fu +#define CCM_POST17_POST_PODF_SHIFT 0 +#define CCM_POST17_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST17_POST_PODF_SHIFT))&CCM_POST17_POST_PODF_MASK) +#define CCM_POST17_BUSY1_MASK 0x80u +#define CCM_POST17_BUSY1_SHIFT 7 +#define CCM_POST17_AUTO_PODF_MASK 0x700u +#define CCM_POST17_AUTO_PODF_SHIFT 8 +#define CCM_POST17_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST17_AUTO_PODF_SHIFT))&CCM_POST17_AUTO_PODF_MASK) +#define CCM_POST17_AUTO_EN_MASK 0x1000u +#define CCM_POST17_AUTO_EN_SHIFT 12 +#define CCM_POST17_SLOW_MASK 0x8000u +#define CCM_POST17_SLOW_SHIFT 15 +#define CCM_POST17_SELECT_MASK 0x10000000u +#define CCM_POST17_SELECT_SHIFT 28 +#define CCM_POST17_BUSY2_MASK 0x80000000u +#define CCM_POST17_BUSY2_SHIFT 31 +/* POST_ROOT17_SET Bit Fields */ +#define CCM_POST_ROOT17_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT17_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT17_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_SET_POST_PODF_SHIFT))&CCM_POST_ROOT17_SET_POST_PODF_MASK) +#define CCM_POST_ROOT17_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT17_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT17_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT17_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT17_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT17_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT17_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT17_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT17_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT17_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT17_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT17_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT17_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT17_SET_BUSY2_SHIFT 31 +/* POST_ROOT17_CLR Bit Fields */ +#define CCM_POST_ROOT17_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT17_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT17_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT17_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT17_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT17_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT17_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT17_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT17_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT17_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT17_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT17_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT17_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT17_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT17_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT17_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT17_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT17_CLR_BUSY2_SHIFT 31 +/* POST_ROOT17_TOG Bit Fields */ +#define CCM_POST_ROOT17_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT17_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT17_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT17_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT17_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT17_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT17_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT17_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT17_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT17_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT17_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT17_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT17_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT17_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT17_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT17_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT17_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT17_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT17_TOG_BUSY2_SHIFT 31 +/* PRE17 Bit Fields */ +#define CCM_PRE17_PRE_PODF_B_MASK 0x7u +#define CCM_PRE17_PRE_PODF_B_SHIFT 0 +#define CCM_PRE17_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_PRE_PODF_B_SHIFT))&CCM_PRE17_PRE_PODF_B_MASK) +#define CCM_PRE17_BUSY0_MASK 0x8u +#define CCM_PRE17_BUSY0_SHIFT 3 +#define CCM_PRE17_MUX_B_MASK 0x700u +#define CCM_PRE17_MUX_B_SHIFT 8 +#define CCM_PRE17_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_MUX_B_SHIFT))&CCM_PRE17_MUX_B_MASK) +#define CCM_PRE17_EN_B_MASK 0x1000u +#define CCM_PRE17_EN_B_SHIFT 12 +#define CCM_PRE17_BUSY1_MASK 0x8000u +#define CCM_PRE17_BUSY1_SHIFT 15 +#define CCM_PRE17_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE17_PRE_PODF_A_SHIFT 16 +#define CCM_PRE17_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_PRE_PODF_A_SHIFT))&CCM_PRE17_PRE_PODF_A_MASK) +#define CCM_PRE17_BUSY3_MASK 0x80000u +#define CCM_PRE17_BUSY3_SHIFT 19 +#define CCM_PRE17_MUX_A_MASK 0x7000000u +#define CCM_PRE17_MUX_A_SHIFT 24 +#define CCM_PRE17_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE17_MUX_A_SHIFT))&CCM_PRE17_MUX_A_MASK) +#define CCM_PRE17_EN_A_MASK 0x10000000u +#define CCM_PRE17_EN_A_SHIFT 28 +#define CCM_PRE17_BUSY4_MASK 0x80000000u +#define CCM_PRE17_BUSY4_SHIFT 31 +/* PRE_ROOT17_SET Bit Fields */ +#define CCM_PRE_ROOT17_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT17_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT17_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT17_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT17_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT17_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT17_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT17_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT17_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_MUX_B_SHIFT))&CCM_PRE_ROOT17_SET_MUX_B_MASK) +#define CCM_PRE_ROOT17_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT17_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT17_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT17_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT17_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT17_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT17_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT17_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT17_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT17_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT17_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT17_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT17_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_SET_MUX_A_SHIFT))&CCM_PRE_ROOT17_SET_MUX_A_MASK) +#define CCM_PRE_ROOT17_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT17_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT17_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT17_SET_BUSY4_SHIFT 31 +/* PRE_ROOT17_CLR Bit Fields */ +#define CCM_PRE_ROOT17_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT17_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT17_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT17_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT17_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT17_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT17_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT17_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT17_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT17_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT17_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT17_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT17_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT17_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT17_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT17_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT17_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT17_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT17_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT17_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT17_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT17_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT17_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT17_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT17_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT17_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT17_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT17_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT17_TOG Bit Fields */ +#define CCM_PRE_ROOT17_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT17_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT17_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT17_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT17_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT17_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT17_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT17_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT17_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT17_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT17_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT17_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT17_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT17_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT17_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT17_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT17_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT17_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT17_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT17_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT17_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT17_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT17_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT17_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT17_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT17_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT17_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT17_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT17_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL17 Bit Fields */ +#define CCM_ACCESS_CTRL17_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL17_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL17_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL17_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL17_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL17_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL17_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL17_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL17_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL17_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL17_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL17_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL17_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL17_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL17_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL17_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL17_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL17_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL17_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL17_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL17_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL17_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL17_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL17_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL17_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL17_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL17_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL17_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL17_LOCK_SHIFT 31 +/* ACCESS_CTRL17_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL17_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL17_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL17_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL17_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL17_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL17_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL17_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL17_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL17_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL17_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL17_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL17_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL17_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL17_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL17_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL17_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL17_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL17_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT18 Bit Fields */ +#define CCM_TARGET_ROOT18_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT18_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT18_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_POST_PODF_MASK) +#define CCM_TARGET_ROOT18_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT18_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT18_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT18_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT18_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT18_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT18_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT18_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT18_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT18_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_PRE_PODF_MASK) +#define CCM_TARGET_ROOT18_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT18_MUX_SHIFT 24 +#define CCM_TARGET_ROOT18_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_MUX_SHIFT))&CCM_TARGET_ROOT18_MUX_MASK) +#define CCM_TARGET_ROOT18_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT18_ENABLE_SHIFT 28 +/* TARGET_ROOT18_SET Bit Fields */ +#define CCM_TARGET_ROOT18_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT18_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT18_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT18_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT18_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT18_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT18_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT18_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT18_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT18_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT18_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT18_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT18_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT18_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT18_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT18_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_SET_MUX_SHIFT))&CCM_TARGET_ROOT18_SET_MUX_MASK) +#define CCM_TARGET_ROOT18_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT18_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT18_CLR Bit Fields */ +#define CCM_TARGET_ROOT18_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT18_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT18_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT18_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT18_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT18_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT18_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT18_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT18_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT18_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT18_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT18_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT18_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_CLR_MUX_SHIFT))&CCM_TARGET_ROOT18_CLR_MUX_MASK) +#define CCM_TARGET_ROOT18_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT18_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT18_TOG Bit Fields */ +#define CCM_TARGET_ROOT18_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT18_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT18_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT18_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT18_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT18_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT18_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT18_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT18_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT18_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT18_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT18_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT18_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT18_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT18_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT18_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT18_TOG_MUX_SHIFT))&CCM_TARGET_ROOT18_TOG_MUX_MASK) +#define CCM_TARGET_ROOT18_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT18_TOG_ENABLE_SHIFT 28 +/* POST18 Bit Fields */ +#define CCM_POST18_POST_PODF_MASK 0x3Fu +#define CCM_POST18_POST_PODF_SHIFT 0 +#define CCM_POST18_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST18_POST_PODF_SHIFT))&CCM_POST18_POST_PODF_MASK) +#define CCM_POST18_BUSY1_MASK 0x80u +#define CCM_POST18_BUSY1_SHIFT 7 +#define CCM_POST18_AUTO_PODF_MASK 0x700u +#define CCM_POST18_AUTO_PODF_SHIFT 8 +#define CCM_POST18_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST18_AUTO_PODF_SHIFT))&CCM_POST18_AUTO_PODF_MASK) +#define CCM_POST18_AUTO_EN_MASK 0x1000u +#define CCM_POST18_AUTO_EN_SHIFT 12 +#define CCM_POST18_SLOW_MASK 0x8000u +#define CCM_POST18_SLOW_SHIFT 15 +#define CCM_POST18_SELECT_MASK 0x10000000u +#define CCM_POST18_SELECT_SHIFT 28 +#define CCM_POST18_BUSY2_MASK 0x80000000u +#define CCM_POST18_BUSY2_SHIFT 31 +/* POST_ROOT18_SET Bit Fields */ +#define CCM_POST_ROOT18_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT18_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT18_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_SET_POST_PODF_SHIFT))&CCM_POST_ROOT18_SET_POST_PODF_MASK) +#define CCM_POST_ROOT18_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT18_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT18_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT18_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT18_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT18_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT18_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT18_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT18_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT18_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT18_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT18_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT18_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT18_SET_BUSY2_SHIFT 31 +/* POST_ROOT18_CLR Bit Fields */ +#define CCM_POST_ROOT18_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT18_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT18_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT18_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT18_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT18_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT18_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT18_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT18_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT18_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT18_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT18_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT18_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT18_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT18_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT18_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT18_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT18_CLR_BUSY2_SHIFT 31 +/* POST_ROOT18_TOG Bit Fields */ +#define CCM_POST_ROOT18_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT18_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT18_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT18_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT18_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT18_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT18_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT18_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT18_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT18_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT18_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT18_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT18_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT18_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT18_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT18_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT18_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT18_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT18_TOG_BUSY2_SHIFT 31 +/* PRE18 Bit Fields */ +#define CCM_PRE18_PRE_PODF_B_MASK 0x7u +#define CCM_PRE18_PRE_PODF_B_SHIFT 0 +#define CCM_PRE18_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_PRE_PODF_B_SHIFT))&CCM_PRE18_PRE_PODF_B_MASK) +#define CCM_PRE18_BUSY0_MASK 0x8u +#define CCM_PRE18_BUSY0_SHIFT 3 +#define CCM_PRE18_MUX_B_MASK 0x700u +#define CCM_PRE18_MUX_B_SHIFT 8 +#define CCM_PRE18_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_MUX_B_SHIFT))&CCM_PRE18_MUX_B_MASK) +#define CCM_PRE18_EN_B_MASK 0x1000u +#define CCM_PRE18_EN_B_SHIFT 12 +#define CCM_PRE18_BUSY1_MASK 0x8000u +#define CCM_PRE18_BUSY1_SHIFT 15 +#define CCM_PRE18_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE18_PRE_PODF_A_SHIFT 16 +#define CCM_PRE18_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_PRE_PODF_A_SHIFT))&CCM_PRE18_PRE_PODF_A_MASK) +#define CCM_PRE18_BUSY3_MASK 0x80000u +#define CCM_PRE18_BUSY3_SHIFT 19 +#define CCM_PRE18_MUX_A_MASK 0x7000000u +#define CCM_PRE18_MUX_A_SHIFT 24 +#define CCM_PRE18_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE18_MUX_A_SHIFT))&CCM_PRE18_MUX_A_MASK) +#define CCM_PRE18_EN_A_MASK 0x10000000u +#define CCM_PRE18_EN_A_SHIFT 28 +#define CCM_PRE18_BUSY4_MASK 0x80000000u +#define CCM_PRE18_BUSY4_SHIFT 31 +/* PRE_ROOT18_SET Bit Fields */ +#define CCM_PRE_ROOT18_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT18_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT18_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT18_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT18_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT18_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT18_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT18_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT18_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_MUX_B_SHIFT))&CCM_PRE_ROOT18_SET_MUX_B_MASK) +#define CCM_PRE_ROOT18_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT18_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT18_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT18_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT18_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT18_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT18_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT18_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT18_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT18_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT18_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT18_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT18_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_SET_MUX_A_SHIFT))&CCM_PRE_ROOT18_SET_MUX_A_MASK) +#define CCM_PRE_ROOT18_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT18_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT18_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT18_SET_BUSY4_SHIFT 31 +/* PRE_ROOT18_CLR Bit Fields */ +#define CCM_PRE_ROOT18_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT18_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT18_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT18_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT18_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT18_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT18_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT18_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT18_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT18_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT18_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT18_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT18_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT18_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT18_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT18_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT18_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT18_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT18_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT18_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT18_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT18_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT18_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT18_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT18_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT18_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT18_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT18_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT18_TOG Bit Fields */ +#define CCM_PRE_ROOT18_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT18_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT18_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT18_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT18_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT18_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT18_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT18_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT18_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT18_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT18_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT18_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT18_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT18_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT18_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT18_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT18_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT18_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT18_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT18_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT18_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT18_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT18_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT18_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT18_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT18_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT18_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT18_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT18_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL18 Bit Fields */ +#define CCM_ACCESS_CTRL18_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL18_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL18_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL18_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL18_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL18_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL18_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL18_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL18_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL18_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL18_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL18_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL18_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL18_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL18_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL18_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL18_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL18_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL18_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL18_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL18_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL18_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL18_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL18_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL18_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL18_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL18_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL18_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL18_LOCK_SHIFT 31 +/* ACCESS_CTRL18_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL18_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL18_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL18_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL18_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL18_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL18_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL18_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL18_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL18_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL18_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL18_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL18_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL18_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL18_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL18_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL18_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL18_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL18_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT19 Bit Fields */ +#define CCM_TARGET_ROOT19_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT19_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT19_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_POST_PODF_MASK) +#define CCM_TARGET_ROOT19_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT19_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT19_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT19_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT19_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT19_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT19_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT19_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT19_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT19_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_PRE_PODF_MASK) +#define CCM_TARGET_ROOT19_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT19_MUX_SHIFT 24 +#define CCM_TARGET_ROOT19_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_MUX_SHIFT))&CCM_TARGET_ROOT19_MUX_MASK) +#define CCM_TARGET_ROOT19_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT19_ENABLE_SHIFT 28 +/* TARGET_ROOT19_SET Bit Fields */ +#define CCM_TARGET_ROOT19_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT19_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT19_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT19_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT19_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT19_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT19_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT19_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT19_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT19_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT19_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT19_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT19_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT19_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT19_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT19_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_SET_MUX_SHIFT))&CCM_TARGET_ROOT19_SET_MUX_MASK) +#define CCM_TARGET_ROOT19_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT19_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT19_CLR Bit Fields */ +#define CCM_TARGET_ROOT19_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT19_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT19_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT19_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT19_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT19_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT19_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT19_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT19_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT19_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT19_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT19_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT19_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_CLR_MUX_SHIFT))&CCM_TARGET_ROOT19_CLR_MUX_MASK) +#define CCM_TARGET_ROOT19_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT19_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT19_TOG Bit Fields */ +#define CCM_TARGET_ROOT19_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT19_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT19_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT19_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT19_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT19_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT19_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT19_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT19_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT19_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT19_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT19_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT19_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT19_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT19_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT19_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT19_TOG_MUX_SHIFT))&CCM_TARGET_ROOT19_TOG_MUX_MASK) +#define CCM_TARGET_ROOT19_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT19_TOG_ENABLE_SHIFT 28 +/* POST19 Bit Fields */ +#define CCM_POST19_POST_PODF_MASK 0x3Fu +#define CCM_POST19_POST_PODF_SHIFT 0 +#define CCM_POST19_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST19_POST_PODF_SHIFT))&CCM_POST19_POST_PODF_MASK) +#define CCM_POST19_BUSY1_MASK 0x80u +#define CCM_POST19_BUSY1_SHIFT 7 +#define CCM_POST19_AUTO_PODF_MASK 0x700u +#define CCM_POST19_AUTO_PODF_SHIFT 8 +#define CCM_POST19_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST19_AUTO_PODF_SHIFT))&CCM_POST19_AUTO_PODF_MASK) +#define CCM_POST19_AUTO_EN_MASK 0x1000u +#define CCM_POST19_AUTO_EN_SHIFT 12 +#define CCM_POST19_SLOW_MASK 0x8000u +#define CCM_POST19_SLOW_SHIFT 15 +#define CCM_POST19_SELECT_MASK 0x10000000u +#define CCM_POST19_SELECT_SHIFT 28 +#define CCM_POST19_BUSY2_MASK 0x80000000u +#define CCM_POST19_BUSY2_SHIFT 31 +/* POST_ROOT19_SET Bit Fields */ +#define CCM_POST_ROOT19_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT19_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT19_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_SET_POST_PODF_SHIFT))&CCM_POST_ROOT19_SET_POST_PODF_MASK) +#define CCM_POST_ROOT19_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT19_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT19_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT19_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT19_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT19_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT19_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT19_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT19_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT19_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT19_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT19_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT19_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT19_SET_BUSY2_SHIFT 31 +/* POST_ROOT19_CLR Bit Fields */ +#define CCM_POST_ROOT19_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT19_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT19_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT19_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT19_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT19_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT19_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT19_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT19_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT19_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT19_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT19_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT19_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT19_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT19_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT19_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT19_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT19_CLR_BUSY2_SHIFT 31 +/* POST_ROOT19_TOG Bit Fields */ +#define CCM_POST_ROOT19_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT19_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT19_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT19_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT19_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT19_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT19_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT19_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT19_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT19_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT19_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT19_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT19_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT19_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT19_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT19_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT19_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT19_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT19_TOG_BUSY2_SHIFT 31 +/* PRE19 Bit Fields */ +#define CCM_PRE19_PRE_PODF_B_MASK 0x7u +#define CCM_PRE19_PRE_PODF_B_SHIFT 0 +#define CCM_PRE19_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_PRE_PODF_B_SHIFT))&CCM_PRE19_PRE_PODF_B_MASK) +#define CCM_PRE19_BUSY0_MASK 0x8u +#define CCM_PRE19_BUSY0_SHIFT 3 +#define CCM_PRE19_MUX_B_MASK 0x700u +#define CCM_PRE19_MUX_B_SHIFT 8 +#define CCM_PRE19_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_MUX_B_SHIFT))&CCM_PRE19_MUX_B_MASK) +#define CCM_PRE19_EN_B_MASK 0x1000u +#define CCM_PRE19_EN_B_SHIFT 12 +#define CCM_PRE19_BUSY1_MASK 0x8000u +#define CCM_PRE19_BUSY1_SHIFT 15 +#define CCM_PRE19_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE19_PRE_PODF_A_SHIFT 16 +#define CCM_PRE19_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_PRE_PODF_A_SHIFT))&CCM_PRE19_PRE_PODF_A_MASK) +#define CCM_PRE19_BUSY3_MASK 0x80000u +#define CCM_PRE19_BUSY3_SHIFT 19 +#define CCM_PRE19_MUX_A_MASK 0x7000000u +#define CCM_PRE19_MUX_A_SHIFT 24 +#define CCM_PRE19_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE19_MUX_A_SHIFT))&CCM_PRE19_MUX_A_MASK) +#define CCM_PRE19_EN_A_MASK 0x10000000u +#define CCM_PRE19_EN_A_SHIFT 28 +#define CCM_PRE19_BUSY4_MASK 0x80000000u +#define CCM_PRE19_BUSY4_SHIFT 31 +/* PRE_ROOT19_SET Bit Fields */ +#define CCM_PRE_ROOT19_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT19_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT19_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT19_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT19_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT19_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT19_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT19_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT19_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_MUX_B_SHIFT))&CCM_PRE_ROOT19_SET_MUX_B_MASK) +#define CCM_PRE_ROOT19_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT19_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT19_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT19_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT19_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT19_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT19_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT19_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT19_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT19_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT19_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT19_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT19_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_SET_MUX_A_SHIFT))&CCM_PRE_ROOT19_SET_MUX_A_MASK) +#define CCM_PRE_ROOT19_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT19_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT19_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT19_SET_BUSY4_SHIFT 31 +/* PRE_ROOT19_CLR Bit Fields */ +#define CCM_PRE_ROOT19_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT19_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT19_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT19_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT19_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT19_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT19_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT19_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT19_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT19_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT19_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT19_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT19_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT19_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT19_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT19_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT19_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT19_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT19_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT19_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT19_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT19_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT19_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT19_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT19_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT19_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT19_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT19_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT19_TOG Bit Fields */ +#define CCM_PRE_ROOT19_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT19_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT19_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT19_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT19_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT19_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT19_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT19_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT19_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT19_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT19_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT19_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT19_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT19_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT19_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT19_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT19_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT19_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT19_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT19_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT19_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT19_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT19_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT19_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT19_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT19_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT19_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT19_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT19_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL19 Bit Fields */ +#define CCM_ACCESS_CTRL19_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL19_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL19_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL19_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL19_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL19_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL19_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL19_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL19_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL19_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL19_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL19_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL19_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL19_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL19_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL19_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL19_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL19_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL19_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL19_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL19_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL19_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL19_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL19_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL19_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL19_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL19_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL19_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL19_LOCK_SHIFT 31 +/* ACCESS_CTRL19_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL19_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL19_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL19_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL19_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL19_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL19_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL19_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL19_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL19_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL19_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL19_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL19_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL19_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL19_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL19_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL19_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL19_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL19_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT20 Bit Fields */ +#define CCM_TARGET_ROOT20_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT20_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT20_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_POST_PODF_MASK) +#define CCM_TARGET_ROOT20_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT20_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT20_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT20_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT20_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT20_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT20_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT20_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT20_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT20_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_PRE_PODF_MASK) +#define CCM_TARGET_ROOT20_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT20_MUX_SHIFT 24 +#define CCM_TARGET_ROOT20_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_MUX_SHIFT))&CCM_TARGET_ROOT20_MUX_MASK) +#define CCM_TARGET_ROOT20_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT20_ENABLE_SHIFT 28 +/* TARGET_ROOT20_SET Bit Fields */ +#define CCM_TARGET_ROOT20_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT20_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT20_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT20_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT20_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT20_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT20_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT20_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT20_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT20_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT20_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT20_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT20_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT20_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT20_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT20_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_SET_MUX_SHIFT))&CCM_TARGET_ROOT20_SET_MUX_MASK) +#define CCM_TARGET_ROOT20_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT20_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT20_CLR Bit Fields */ +#define CCM_TARGET_ROOT20_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT20_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT20_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT20_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT20_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT20_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT20_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT20_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT20_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT20_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT20_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT20_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT20_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_CLR_MUX_SHIFT))&CCM_TARGET_ROOT20_CLR_MUX_MASK) +#define CCM_TARGET_ROOT20_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT20_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT20_TOG Bit Fields */ +#define CCM_TARGET_ROOT20_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT20_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT20_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT20_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT20_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT20_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT20_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT20_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT20_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT20_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT20_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT20_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT20_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT20_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT20_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT20_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT20_TOG_MUX_SHIFT))&CCM_TARGET_ROOT20_TOG_MUX_MASK) +#define CCM_TARGET_ROOT20_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT20_TOG_ENABLE_SHIFT 28 +/* POST20 Bit Fields */ +#define CCM_POST20_POST_PODF_MASK 0x3Fu +#define CCM_POST20_POST_PODF_SHIFT 0 +#define CCM_POST20_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST20_POST_PODF_SHIFT))&CCM_POST20_POST_PODF_MASK) +#define CCM_POST20_BUSY1_MASK 0x80u +#define CCM_POST20_BUSY1_SHIFT 7 +#define CCM_POST20_AUTO_PODF_MASK 0x700u +#define CCM_POST20_AUTO_PODF_SHIFT 8 +#define CCM_POST20_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST20_AUTO_PODF_SHIFT))&CCM_POST20_AUTO_PODF_MASK) +#define CCM_POST20_AUTO_EN_MASK 0x1000u +#define CCM_POST20_AUTO_EN_SHIFT 12 +#define CCM_POST20_SLOW_MASK 0x8000u +#define CCM_POST20_SLOW_SHIFT 15 +#define CCM_POST20_SELECT_MASK 0x10000000u +#define CCM_POST20_SELECT_SHIFT 28 +#define CCM_POST20_BUSY2_MASK 0x80000000u +#define CCM_POST20_BUSY2_SHIFT 31 +/* POST_ROOT20_SET Bit Fields */ +#define CCM_POST_ROOT20_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT20_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT20_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_SET_POST_PODF_SHIFT))&CCM_POST_ROOT20_SET_POST_PODF_MASK) +#define CCM_POST_ROOT20_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT20_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT20_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT20_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT20_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT20_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT20_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT20_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT20_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT20_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT20_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT20_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT20_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT20_SET_BUSY2_SHIFT 31 +/* POST_ROOT20_CLR Bit Fields */ +#define CCM_POST_ROOT20_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT20_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT20_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT20_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT20_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT20_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT20_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT20_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT20_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT20_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT20_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT20_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT20_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT20_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT20_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT20_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT20_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT20_CLR_BUSY2_SHIFT 31 +/* POST_ROOT20_TOG Bit Fields */ +#define CCM_POST_ROOT20_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT20_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT20_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT20_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT20_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT20_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT20_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT20_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT20_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT20_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT20_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT20_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT20_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT20_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT20_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT20_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT20_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT20_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT20_TOG_BUSY2_SHIFT 31 +/* PRE20 Bit Fields */ +#define CCM_PRE20_PRE_PODF_B_MASK 0x7u +#define CCM_PRE20_PRE_PODF_B_SHIFT 0 +#define CCM_PRE20_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_PRE_PODF_B_SHIFT))&CCM_PRE20_PRE_PODF_B_MASK) +#define CCM_PRE20_BUSY0_MASK 0x8u +#define CCM_PRE20_BUSY0_SHIFT 3 +#define CCM_PRE20_MUX_B_MASK 0x700u +#define CCM_PRE20_MUX_B_SHIFT 8 +#define CCM_PRE20_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_MUX_B_SHIFT))&CCM_PRE20_MUX_B_MASK) +#define CCM_PRE20_EN_B_MASK 0x1000u +#define CCM_PRE20_EN_B_SHIFT 12 +#define CCM_PRE20_BUSY1_MASK 0x8000u +#define CCM_PRE20_BUSY1_SHIFT 15 +#define CCM_PRE20_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE20_PRE_PODF_A_SHIFT 16 +#define CCM_PRE20_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_PRE_PODF_A_SHIFT))&CCM_PRE20_PRE_PODF_A_MASK) +#define CCM_PRE20_BUSY3_MASK 0x80000u +#define CCM_PRE20_BUSY3_SHIFT 19 +#define CCM_PRE20_MUX_A_MASK 0x7000000u +#define CCM_PRE20_MUX_A_SHIFT 24 +#define CCM_PRE20_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE20_MUX_A_SHIFT))&CCM_PRE20_MUX_A_MASK) +#define CCM_PRE20_EN_A_MASK 0x10000000u +#define CCM_PRE20_EN_A_SHIFT 28 +#define CCM_PRE20_BUSY4_MASK 0x80000000u +#define CCM_PRE20_BUSY4_SHIFT 31 +/* PRE_ROOT20_SET Bit Fields */ +#define CCM_PRE_ROOT20_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT20_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT20_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT20_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT20_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT20_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT20_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT20_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT20_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_MUX_B_SHIFT))&CCM_PRE_ROOT20_SET_MUX_B_MASK) +#define CCM_PRE_ROOT20_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT20_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT20_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT20_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT20_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT20_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT20_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT20_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT20_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT20_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT20_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT20_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT20_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_SET_MUX_A_SHIFT))&CCM_PRE_ROOT20_SET_MUX_A_MASK) +#define CCM_PRE_ROOT20_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT20_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT20_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT20_SET_BUSY4_SHIFT 31 +/* PRE_ROOT20_CLR Bit Fields */ +#define CCM_PRE_ROOT20_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT20_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT20_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT20_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT20_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT20_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT20_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT20_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT20_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT20_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT20_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT20_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT20_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT20_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT20_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT20_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT20_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT20_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT20_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT20_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT20_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT20_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT20_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT20_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT20_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT20_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT20_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT20_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT20_TOG Bit Fields */ +#define CCM_PRE_ROOT20_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT20_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT20_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT20_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT20_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT20_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT20_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT20_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT20_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT20_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT20_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT20_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT20_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT20_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT20_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT20_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT20_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT20_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT20_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT20_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT20_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT20_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT20_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT20_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT20_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT20_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT20_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT20_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT20_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL20 Bit Fields */ +#define CCM_ACCESS_CTRL20_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL20_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL20_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL20_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL20_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL20_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL20_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL20_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL20_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL20_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL20_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL20_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL20_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL20_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL20_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL20_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL20_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL20_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL20_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL20_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL20_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL20_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL20_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL20_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL20_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL20_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL20_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL20_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL20_LOCK_SHIFT 31 +/* ACCESS_CTRL20_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL20_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL20_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL20_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL20_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL20_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL20_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL20_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL20_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL20_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL20_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL20_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL20_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL20_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL20_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL20_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL20_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL20_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL20_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT21 Bit Fields */ +#define CCM_TARGET_ROOT21_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT21_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT21_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_POST_PODF_MASK) +#define CCM_TARGET_ROOT21_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT21_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT21_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT21_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT21_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT21_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT21_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT21_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT21_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT21_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_PRE_PODF_MASK) +#define CCM_TARGET_ROOT21_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT21_MUX_SHIFT 24 +#define CCM_TARGET_ROOT21_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_MUX_SHIFT))&CCM_TARGET_ROOT21_MUX_MASK) +#define CCM_TARGET_ROOT21_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT21_ENABLE_SHIFT 28 +/* TARGET_ROOT21_SET Bit Fields */ +#define CCM_TARGET_ROOT21_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT21_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT21_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT21_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT21_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT21_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT21_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT21_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT21_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT21_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT21_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT21_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT21_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT21_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT21_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT21_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_SET_MUX_SHIFT))&CCM_TARGET_ROOT21_SET_MUX_MASK) +#define CCM_TARGET_ROOT21_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT21_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT21_CLR Bit Fields */ +#define CCM_TARGET_ROOT21_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT21_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT21_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT21_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT21_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT21_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT21_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT21_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT21_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT21_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT21_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT21_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT21_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_CLR_MUX_SHIFT))&CCM_TARGET_ROOT21_CLR_MUX_MASK) +#define CCM_TARGET_ROOT21_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT21_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT21_TOG Bit Fields */ +#define CCM_TARGET_ROOT21_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT21_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT21_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT21_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT21_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT21_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT21_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT21_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT21_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT21_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT21_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT21_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT21_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT21_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT21_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT21_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT21_TOG_MUX_SHIFT))&CCM_TARGET_ROOT21_TOG_MUX_MASK) +#define CCM_TARGET_ROOT21_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT21_TOG_ENABLE_SHIFT 28 +/* POST21 Bit Fields */ +#define CCM_POST21_POST_PODF_MASK 0x3Fu +#define CCM_POST21_POST_PODF_SHIFT 0 +#define CCM_POST21_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST21_POST_PODF_SHIFT))&CCM_POST21_POST_PODF_MASK) +#define CCM_POST21_BUSY1_MASK 0x80u +#define CCM_POST21_BUSY1_SHIFT 7 +#define CCM_POST21_AUTO_PODF_MASK 0x700u +#define CCM_POST21_AUTO_PODF_SHIFT 8 +#define CCM_POST21_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST21_AUTO_PODF_SHIFT))&CCM_POST21_AUTO_PODF_MASK) +#define CCM_POST21_AUTO_EN_MASK 0x1000u +#define CCM_POST21_AUTO_EN_SHIFT 12 +#define CCM_POST21_SLOW_MASK 0x8000u +#define CCM_POST21_SLOW_SHIFT 15 +#define CCM_POST21_SELECT_MASK 0x10000000u +#define CCM_POST21_SELECT_SHIFT 28 +#define CCM_POST21_BUSY2_MASK 0x80000000u +#define CCM_POST21_BUSY2_SHIFT 31 +/* POST_ROOT21_SET Bit Fields */ +#define CCM_POST_ROOT21_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT21_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT21_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_SET_POST_PODF_SHIFT))&CCM_POST_ROOT21_SET_POST_PODF_MASK) +#define CCM_POST_ROOT21_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT21_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT21_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT21_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT21_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT21_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT21_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT21_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT21_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT21_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT21_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT21_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT21_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT21_SET_BUSY2_SHIFT 31 +/* POST_ROOT21_CLR Bit Fields */ +#define CCM_POST_ROOT21_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT21_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT21_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT21_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT21_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT21_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT21_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT21_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT21_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT21_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT21_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT21_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT21_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT21_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT21_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT21_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT21_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT21_CLR_BUSY2_SHIFT 31 +/* POST_ROOT21_TOG Bit Fields */ +#define CCM_POST_ROOT21_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT21_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT21_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT21_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT21_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT21_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT21_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT21_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT21_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT21_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT21_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT21_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT21_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT21_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT21_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT21_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT21_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT21_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT21_TOG_BUSY2_SHIFT 31 +/* PRE21 Bit Fields */ +#define CCM_PRE21_PRE_PODF_B_MASK 0x7u +#define CCM_PRE21_PRE_PODF_B_SHIFT 0 +#define CCM_PRE21_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_PRE_PODF_B_SHIFT))&CCM_PRE21_PRE_PODF_B_MASK) +#define CCM_PRE21_BUSY0_MASK 0x8u +#define CCM_PRE21_BUSY0_SHIFT 3 +#define CCM_PRE21_MUX_B_MASK 0x700u +#define CCM_PRE21_MUX_B_SHIFT 8 +#define CCM_PRE21_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_MUX_B_SHIFT))&CCM_PRE21_MUX_B_MASK) +#define CCM_PRE21_EN_B_MASK 0x1000u +#define CCM_PRE21_EN_B_SHIFT 12 +#define CCM_PRE21_BUSY1_MASK 0x8000u +#define CCM_PRE21_BUSY1_SHIFT 15 +#define CCM_PRE21_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE21_PRE_PODF_A_SHIFT 16 +#define CCM_PRE21_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_PRE_PODF_A_SHIFT))&CCM_PRE21_PRE_PODF_A_MASK) +#define CCM_PRE21_BUSY3_MASK 0x80000u +#define CCM_PRE21_BUSY3_SHIFT 19 +#define CCM_PRE21_MUX_A_MASK 0x7000000u +#define CCM_PRE21_MUX_A_SHIFT 24 +#define CCM_PRE21_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE21_MUX_A_SHIFT))&CCM_PRE21_MUX_A_MASK) +#define CCM_PRE21_EN_A_MASK 0x10000000u +#define CCM_PRE21_EN_A_SHIFT 28 +#define CCM_PRE21_BUSY4_MASK 0x80000000u +#define CCM_PRE21_BUSY4_SHIFT 31 +/* PRE_ROOT21_SET Bit Fields */ +#define CCM_PRE_ROOT21_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT21_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT21_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT21_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT21_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT21_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT21_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT21_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT21_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_MUX_B_SHIFT))&CCM_PRE_ROOT21_SET_MUX_B_MASK) +#define CCM_PRE_ROOT21_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT21_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT21_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT21_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT21_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT21_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT21_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT21_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT21_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT21_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT21_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT21_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT21_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_SET_MUX_A_SHIFT))&CCM_PRE_ROOT21_SET_MUX_A_MASK) +#define CCM_PRE_ROOT21_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT21_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT21_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT21_SET_BUSY4_SHIFT 31 +/* PRE_ROOT21_CLR Bit Fields */ +#define CCM_PRE_ROOT21_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT21_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT21_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT21_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT21_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT21_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT21_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT21_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT21_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT21_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT21_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT21_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT21_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT21_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT21_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT21_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT21_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT21_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT21_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT21_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT21_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT21_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT21_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT21_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT21_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT21_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT21_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT21_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT21_TOG Bit Fields */ +#define CCM_PRE_ROOT21_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT21_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT21_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT21_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT21_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT21_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT21_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT21_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT21_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT21_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT21_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT21_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT21_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT21_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT21_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT21_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT21_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT21_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT21_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT21_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT21_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT21_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT21_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT21_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT21_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT21_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT21_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT21_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT21_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL21 Bit Fields */ +#define CCM_ACCESS_CTRL21_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL21_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL21_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL21_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL21_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL21_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL21_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL21_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL21_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL21_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL21_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL21_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL21_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL21_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL21_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL21_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL21_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL21_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL21_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL21_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL21_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL21_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL21_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL21_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL21_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL21_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL21_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL21_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL21_LOCK_SHIFT 31 +/* ACCESS_CTRL21_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL21_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL21_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL21_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL21_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL21_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL21_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL21_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL21_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL21_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL21_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL21_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL21_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL21_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL21_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL21_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL21_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL21_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL21_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT22 Bit Fields */ +#define CCM_TARGET_ROOT22_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT22_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT22_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_POST_PODF_MASK) +#define CCM_TARGET_ROOT22_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT22_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT22_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT22_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT22_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT22_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT22_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT22_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT22_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT22_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_PRE_PODF_MASK) +#define CCM_TARGET_ROOT22_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT22_MUX_SHIFT 24 +#define CCM_TARGET_ROOT22_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_MUX_SHIFT))&CCM_TARGET_ROOT22_MUX_MASK) +#define CCM_TARGET_ROOT22_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT22_ENABLE_SHIFT 28 +/* TARGET_ROOT22_SET Bit Fields */ +#define CCM_TARGET_ROOT22_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT22_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT22_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT22_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT22_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT22_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT22_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT22_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT22_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT22_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT22_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT22_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT22_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT22_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT22_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT22_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_SET_MUX_SHIFT))&CCM_TARGET_ROOT22_SET_MUX_MASK) +#define CCM_TARGET_ROOT22_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT22_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT22_CLR Bit Fields */ +#define CCM_TARGET_ROOT22_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT22_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT22_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT22_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT22_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT22_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT22_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT22_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT22_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT22_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT22_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT22_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT22_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_CLR_MUX_SHIFT))&CCM_TARGET_ROOT22_CLR_MUX_MASK) +#define CCM_TARGET_ROOT22_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT22_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT22_TOG Bit Fields */ +#define CCM_TARGET_ROOT22_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT22_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT22_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT22_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT22_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT22_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT22_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT22_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT22_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT22_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT22_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT22_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT22_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT22_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT22_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT22_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT22_TOG_MUX_SHIFT))&CCM_TARGET_ROOT22_TOG_MUX_MASK) +#define CCM_TARGET_ROOT22_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT22_TOG_ENABLE_SHIFT 28 +/* POST22 Bit Fields */ +#define CCM_POST22_POST_PODF_MASK 0x3Fu +#define CCM_POST22_POST_PODF_SHIFT 0 +#define CCM_POST22_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST22_POST_PODF_SHIFT))&CCM_POST22_POST_PODF_MASK) +#define CCM_POST22_BUSY1_MASK 0x80u +#define CCM_POST22_BUSY1_SHIFT 7 +#define CCM_POST22_AUTO_PODF_MASK 0x700u +#define CCM_POST22_AUTO_PODF_SHIFT 8 +#define CCM_POST22_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST22_AUTO_PODF_SHIFT))&CCM_POST22_AUTO_PODF_MASK) +#define CCM_POST22_AUTO_EN_MASK 0x1000u +#define CCM_POST22_AUTO_EN_SHIFT 12 +#define CCM_POST22_SLOW_MASK 0x8000u +#define CCM_POST22_SLOW_SHIFT 15 +#define CCM_POST22_SELECT_MASK 0x10000000u +#define CCM_POST22_SELECT_SHIFT 28 +#define CCM_POST22_BUSY2_MASK 0x80000000u +#define CCM_POST22_BUSY2_SHIFT 31 +/* POST_ROOT22_SET Bit Fields */ +#define CCM_POST_ROOT22_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT22_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT22_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_SET_POST_PODF_SHIFT))&CCM_POST_ROOT22_SET_POST_PODF_MASK) +#define CCM_POST_ROOT22_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT22_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT22_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT22_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT22_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT22_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT22_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT22_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT22_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT22_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT22_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT22_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT22_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT22_SET_BUSY2_SHIFT 31 +/* POST_ROOT22_CLR Bit Fields */ +#define CCM_POST_ROOT22_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT22_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT22_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT22_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT22_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT22_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT22_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT22_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT22_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT22_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT22_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT22_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT22_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT22_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT22_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT22_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT22_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT22_CLR_BUSY2_SHIFT 31 +/* POST_ROOT22_TOG Bit Fields */ +#define CCM_POST_ROOT22_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT22_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT22_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT22_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT22_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT22_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT22_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT22_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT22_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT22_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT22_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT22_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT22_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT22_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT22_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT22_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT22_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT22_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT22_TOG_BUSY2_SHIFT 31 +/* PRE22 Bit Fields */ +#define CCM_PRE22_PRE_PODF_B_MASK 0x7u +#define CCM_PRE22_PRE_PODF_B_SHIFT 0 +#define CCM_PRE22_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_PRE_PODF_B_SHIFT))&CCM_PRE22_PRE_PODF_B_MASK) +#define CCM_PRE22_BUSY0_MASK 0x8u +#define CCM_PRE22_BUSY0_SHIFT 3 +#define CCM_PRE22_MUX_B_MASK 0x700u +#define CCM_PRE22_MUX_B_SHIFT 8 +#define CCM_PRE22_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_MUX_B_SHIFT))&CCM_PRE22_MUX_B_MASK) +#define CCM_PRE22_EN_B_MASK 0x1000u +#define CCM_PRE22_EN_B_SHIFT 12 +#define CCM_PRE22_BUSY1_MASK 0x8000u +#define CCM_PRE22_BUSY1_SHIFT 15 +#define CCM_PRE22_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE22_PRE_PODF_A_SHIFT 16 +#define CCM_PRE22_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_PRE_PODF_A_SHIFT))&CCM_PRE22_PRE_PODF_A_MASK) +#define CCM_PRE22_BUSY3_MASK 0x80000u +#define CCM_PRE22_BUSY3_SHIFT 19 +#define CCM_PRE22_MUX_A_MASK 0x7000000u +#define CCM_PRE22_MUX_A_SHIFT 24 +#define CCM_PRE22_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE22_MUX_A_SHIFT))&CCM_PRE22_MUX_A_MASK) +#define CCM_PRE22_EN_A_MASK 0x10000000u +#define CCM_PRE22_EN_A_SHIFT 28 +#define CCM_PRE22_BUSY4_MASK 0x80000000u +#define CCM_PRE22_BUSY4_SHIFT 31 +/* PRE_ROOT22_SET Bit Fields */ +#define CCM_PRE_ROOT22_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT22_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT22_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT22_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT22_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT22_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT22_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT22_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT22_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_MUX_B_SHIFT))&CCM_PRE_ROOT22_SET_MUX_B_MASK) +#define CCM_PRE_ROOT22_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT22_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT22_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT22_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT22_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT22_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT22_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT22_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT22_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT22_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT22_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT22_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT22_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_SET_MUX_A_SHIFT))&CCM_PRE_ROOT22_SET_MUX_A_MASK) +#define CCM_PRE_ROOT22_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT22_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT22_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT22_SET_BUSY4_SHIFT 31 +/* PRE_ROOT22_CLR Bit Fields */ +#define CCM_PRE_ROOT22_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT22_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT22_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT22_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT22_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT22_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT22_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT22_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT22_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT22_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT22_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT22_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT22_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT22_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT22_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT22_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT22_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT22_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT22_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT22_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT22_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT22_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT22_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT22_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT22_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT22_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT22_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT22_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT22_TOG Bit Fields */ +#define CCM_PRE_ROOT22_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT22_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT22_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT22_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT22_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT22_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT22_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT22_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT22_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT22_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT22_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT22_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT22_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT22_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT22_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT22_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT22_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT22_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT22_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT22_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT22_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT22_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT22_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT22_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT22_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT22_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT22_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT22_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT22_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL22 Bit Fields */ +#define CCM_ACCESS_CTRL22_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL22_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL22_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL22_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL22_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL22_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL22_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL22_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL22_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL22_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL22_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL22_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL22_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL22_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL22_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL22_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL22_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL22_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL22_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL22_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL22_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL22_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL22_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL22_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL22_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL22_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL22_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL22_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL22_LOCK_SHIFT 31 +/* ACCESS_CTRL22_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL22_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL22_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL22_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL22_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL22_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL22_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL22_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL22_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL22_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL22_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL22_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL22_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL22_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL22_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL22_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL22_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL22_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL22_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT23 Bit Fields */ +#define CCM_TARGET_ROOT23_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT23_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT23_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_POST_PODF_MASK) +#define CCM_TARGET_ROOT23_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT23_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT23_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT23_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT23_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT23_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT23_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT23_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT23_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT23_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_PRE_PODF_MASK) +#define CCM_TARGET_ROOT23_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT23_MUX_SHIFT 24 +#define CCM_TARGET_ROOT23_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_MUX_SHIFT))&CCM_TARGET_ROOT23_MUX_MASK) +#define CCM_TARGET_ROOT23_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT23_ENABLE_SHIFT 28 +/* TARGET_ROOT23_SET Bit Fields */ +#define CCM_TARGET_ROOT23_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT23_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT23_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT23_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT23_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT23_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT23_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT23_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT23_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT23_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT23_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT23_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT23_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT23_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT23_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT23_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_SET_MUX_SHIFT))&CCM_TARGET_ROOT23_SET_MUX_MASK) +#define CCM_TARGET_ROOT23_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT23_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT23_CLR Bit Fields */ +#define CCM_TARGET_ROOT23_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT23_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT23_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT23_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT23_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT23_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT23_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT23_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT23_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT23_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT23_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT23_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT23_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_CLR_MUX_SHIFT))&CCM_TARGET_ROOT23_CLR_MUX_MASK) +#define CCM_TARGET_ROOT23_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT23_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT23_TOG Bit Fields */ +#define CCM_TARGET_ROOT23_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT23_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT23_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT23_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT23_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT23_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT23_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT23_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT23_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT23_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT23_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT23_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT23_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT23_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT23_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT23_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT23_TOG_MUX_SHIFT))&CCM_TARGET_ROOT23_TOG_MUX_MASK) +#define CCM_TARGET_ROOT23_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT23_TOG_ENABLE_SHIFT 28 +/* POST23 Bit Fields */ +#define CCM_POST23_POST_PODF_MASK 0x3Fu +#define CCM_POST23_POST_PODF_SHIFT 0 +#define CCM_POST23_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST23_POST_PODF_SHIFT))&CCM_POST23_POST_PODF_MASK) +#define CCM_POST23_BUSY1_MASK 0x80u +#define CCM_POST23_BUSY1_SHIFT 7 +#define CCM_POST23_AUTO_PODF_MASK 0x700u +#define CCM_POST23_AUTO_PODF_SHIFT 8 +#define CCM_POST23_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST23_AUTO_PODF_SHIFT))&CCM_POST23_AUTO_PODF_MASK) +#define CCM_POST23_AUTO_EN_MASK 0x1000u +#define CCM_POST23_AUTO_EN_SHIFT 12 +#define CCM_POST23_SLOW_MASK 0x8000u +#define CCM_POST23_SLOW_SHIFT 15 +#define CCM_POST23_SELECT_MASK 0x10000000u +#define CCM_POST23_SELECT_SHIFT 28 +#define CCM_POST23_BUSY2_MASK 0x80000000u +#define CCM_POST23_BUSY2_SHIFT 31 +/* POST_ROOT23_SET Bit Fields */ +#define CCM_POST_ROOT23_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT23_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT23_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_SET_POST_PODF_SHIFT))&CCM_POST_ROOT23_SET_POST_PODF_MASK) +#define CCM_POST_ROOT23_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT23_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT23_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT23_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT23_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT23_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT23_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT23_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT23_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT23_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT23_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT23_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT23_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT23_SET_BUSY2_SHIFT 31 +/* POST_ROOT23_CLR Bit Fields */ +#define CCM_POST_ROOT23_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT23_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT23_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT23_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT23_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT23_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT23_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT23_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT23_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT23_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT23_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT23_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT23_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT23_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT23_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT23_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT23_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT23_CLR_BUSY2_SHIFT 31 +/* POST_ROOT23_TOG Bit Fields */ +#define CCM_POST_ROOT23_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT23_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT23_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT23_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT23_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT23_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT23_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT23_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT23_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT23_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT23_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT23_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT23_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT23_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT23_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT23_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT23_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT23_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT23_TOG_BUSY2_SHIFT 31 +/* PRE23 Bit Fields */ +#define CCM_PRE23_PRE_PODF_B_MASK 0x7u +#define CCM_PRE23_PRE_PODF_B_SHIFT 0 +#define CCM_PRE23_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_PRE_PODF_B_SHIFT))&CCM_PRE23_PRE_PODF_B_MASK) +#define CCM_PRE23_BUSY0_MASK 0x8u +#define CCM_PRE23_BUSY0_SHIFT 3 +#define CCM_PRE23_MUX_B_MASK 0x700u +#define CCM_PRE23_MUX_B_SHIFT 8 +#define CCM_PRE23_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_MUX_B_SHIFT))&CCM_PRE23_MUX_B_MASK) +#define CCM_PRE23_EN_B_MASK 0x1000u +#define CCM_PRE23_EN_B_SHIFT 12 +#define CCM_PRE23_BUSY1_MASK 0x8000u +#define CCM_PRE23_BUSY1_SHIFT 15 +#define CCM_PRE23_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE23_PRE_PODF_A_SHIFT 16 +#define CCM_PRE23_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_PRE_PODF_A_SHIFT))&CCM_PRE23_PRE_PODF_A_MASK) +#define CCM_PRE23_BUSY3_MASK 0x80000u +#define CCM_PRE23_BUSY3_SHIFT 19 +#define CCM_PRE23_MUX_A_MASK 0x7000000u +#define CCM_PRE23_MUX_A_SHIFT 24 +#define CCM_PRE23_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE23_MUX_A_SHIFT))&CCM_PRE23_MUX_A_MASK) +#define CCM_PRE23_EN_A_MASK 0x10000000u +#define CCM_PRE23_EN_A_SHIFT 28 +#define CCM_PRE23_BUSY4_MASK 0x80000000u +#define CCM_PRE23_BUSY4_SHIFT 31 +/* PRE_ROOT23_SET Bit Fields */ +#define CCM_PRE_ROOT23_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT23_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT23_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT23_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT23_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT23_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT23_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT23_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT23_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_MUX_B_SHIFT))&CCM_PRE_ROOT23_SET_MUX_B_MASK) +#define CCM_PRE_ROOT23_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT23_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT23_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT23_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT23_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT23_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT23_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT23_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT23_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT23_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT23_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT23_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT23_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_SET_MUX_A_SHIFT))&CCM_PRE_ROOT23_SET_MUX_A_MASK) +#define CCM_PRE_ROOT23_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT23_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT23_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT23_SET_BUSY4_SHIFT 31 +/* PRE_ROOT23_CLR Bit Fields */ +#define CCM_PRE_ROOT23_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT23_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT23_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT23_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT23_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT23_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT23_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT23_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT23_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT23_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT23_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT23_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT23_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT23_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT23_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT23_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT23_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT23_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT23_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT23_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT23_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT23_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT23_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT23_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT23_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT23_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT23_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT23_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT23_TOG Bit Fields */ +#define CCM_PRE_ROOT23_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT23_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT23_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT23_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT23_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT23_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT23_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT23_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT23_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT23_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT23_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT23_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT23_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT23_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT23_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT23_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT23_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT23_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT23_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT23_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT23_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT23_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT23_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT23_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT23_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT23_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT23_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT23_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT23_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL23 Bit Fields */ +#define CCM_ACCESS_CTRL23_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL23_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL23_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL23_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL23_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL23_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL23_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL23_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL23_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL23_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL23_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL23_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL23_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL23_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL23_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL23_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL23_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL23_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL23_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL23_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL23_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL23_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL23_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL23_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL23_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL23_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL23_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL23_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL23_LOCK_SHIFT 31 +/* ACCESS_CTRL23_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL23_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL23_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL23_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL23_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL23_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL23_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL23_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL23_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL23_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL23_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL23_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL23_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL23_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL23_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL23_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL23_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL23_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL23_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT24 Bit Fields */ +#define CCM_TARGET_ROOT24_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT24_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT24_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_POST_PODF_MASK) +#define CCM_TARGET_ROOT24_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT24_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT24_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT24_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT24_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT24_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT24_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT24_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT24_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT24_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_PRE_PODF_MASK) +#define CCM_TARGET_ROOT24_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT24_MUX_SHIFT 24 +#define CCM_TARGET_ROOT24_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_MUX_SHIFT))&CCM_TARGET_ROOT24_MUX_MASK) +#define CCM_TARGET_ROOT24_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT24_ENABLE_SHIFT 28 +/* TARGET_ROOT24_SET Bit Fields */ +#define CCM_TARGET_ROOT24_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT24_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT24_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT24_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT24_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT24_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT24_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT24_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT24_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT24_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT24_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT24_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT24_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT24_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT24_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT24_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_SET_MUX_SHIFT))&CCM_TARGET_ROOT24_SET_MUX_MASK) +#define CCM_TARGET_ROOT24_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT24_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT24_CLR Bit Fields */ +#define CCM_TARGET_ROOT24_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT24_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT24_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT24_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT24_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT24_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT24_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT24_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT24_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT24_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT24_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT24_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT24_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_CLR_MUX_SHIFT))&CCM_TARGET_ROOT24_CLR_MUX_MASK) +#define CCM_TARGET_ROOT24_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT24_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT24_TOG Bit Fields */ +#define CCM_TARGET_ROOT24_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT24_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT24_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT24_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT24_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT24_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT24_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT24_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT24_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT24_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT24_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT24_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT24_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT24_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT24_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT24_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT24_TOG_MUX_SHIFT))&CCM_TARGET_ROOT24_TOG_MUX_MASK) +#define CCM_TARGET_ROOT24_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT24_TOG_ENABLE_SHIFT 28 +/* POST24 Bit Fields */ +#define CCM_POST24_POST_PODF_MASK 0x3Fu +#define CCM_POST24_POST_PODF_SHIFT 0 +#define CCM_POST24_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST24_POST_PODF_SHIFT))&CCM_POST24_POST_PODF_MASK) +#define CCM_POST24_BUSY1_MASK 0x80u +#define CCM_POST24_BUSY1_SHIFT 7 +#define CCM_POST24_AUTO_PODF_MASK 0x700u +#define CCM_POST24_AUTO_PODF_SHIFT 8 +#define CCM_POST24_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST24_AUTO_PODF_SHIFT))&CCM_POST24_AUTO_PODF_MASK) +#define CCM_POST24_AUTO_EN_MASK 0x1000u +#define CCM_POST24_AUTO_EN_SHIFT 12 +#define CCM_POST24_SLOW_MASK 0x8000u +#define CCM_POST24_SLOW_SHIFT 15 +#define CCM_POST24_SELECT_MASK 0x10000000u +#define CCM_POST24_SELECT_SHIFT 28 +#define CCM_POST24_BUSY2_MASK 0x80000000u +#define CCM_POST24_BUSY2_SHIFT 31 +/* POST_ROOT24_SET Bit Fields */ +#define CCM_POST_ROOT24_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT24_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT24_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_SET_POST_PODF_SHIFT))&CCM_POST_ROOT24_SET_POST_PODF_MASK) +#define CCM_POST_ROOT24_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT24_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT24_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT24_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT24_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT24_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT24_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT24_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT24_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT24_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT24_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT24_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT24_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT24_SET_BUSY2_SHIFT 31 +/* POST_ROOT24_CLR Bit Fields */ +#define CCM_POST_ROOT24_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT24_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT24_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT24_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT24_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT24_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT24_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT24_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT24_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT24_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT24_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT24_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT24_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT24_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT24_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT24_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT24_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT24_CLR_BUSY2_SHIFT 31 +/* POST_ROOT24_TOG Bit Fields */ +#define CCM_POST_ROOT24_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT24_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT24_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT24_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT24_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT24_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT24_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT24_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT24_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT24_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT24_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT24_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT24_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT24_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT24_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT24_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT24_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT24_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT24_TOG_BUSY2_SHIFT 31 +/* PRE24 Bit Fields */ +#define CCM_PRE24_PRE_PODF_B_MASK 0x7u +#define CCM_PRE24_PRE_PODF_B_SHIFT 0 +#define CCM_PRE24_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_PRE_PODF_B_SHIFT))&CCM_PRE24_PRE_PODF_B_MASK) +#define CCM_PRE24_BUSY0_MASK 0x8u +#define CCM_PRE24_BUSY0_SHIFT 3 +#define CCM_PRE24_MUX_B_MASK 0x700u +#define CCM_PRE24_MUX_B_SHIFT 8 +#define CCM_PRE24_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_MUX_B_SHIFT))&CCM_PRE24_MUX_B_MASK) +#define CCM_PRE24_EN_B_MASK 0x1000u +#define CCM_PRE24_EN_B_SHIFT 12 +#define CCM_PRE24_BUSY1_MASK 0x8000u +#define CCM_PRE24_BUSY1_SHIFT 15 +#define CCM_PRE24_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE24_PRE_PODF_A_SHIFT 16 +#define CCM_PRE24_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_PRE_PODF_A_SHIFT))&CCM_PRE24_PRE_PODF_A_MASK) +#define CCM_PRE24_BUSY3_MASK 0x80000u +#define CCM_PRE24_BUSY3_SHIFT 19 +#define CCM_PRE24_MUX_A_MASK 0x7000000u +#define CCM_PRE24_MUX_A_SHIFT 24 +#define CCM_PRE24_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE24_MUX_A_SHIFT))&CCM_PRE24_MUX_A_MASK) +#define CCM_PRE24_EN_A_MASK 0x10000000u +#define CCM_PRE24_EN_A_SHIFT 28 +#define CCM_PRE24_BUSY4_MASK 0x80000000u +#define CCM_PRE24_BUSY4_SHIFT 31 +/* PRE_ROOT24_SET Bit Fields */ +#define CCM_PRE_ROOT24_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT24_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT24_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT24_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT24_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT24_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT24_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT24_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT24_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_MUX_B_SHIFT))&CCM_PRE_ROOT24_SET_MUX_B_MASK) +#define CCM_PRE_ROOT24_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT24_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT24_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT24_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT24_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT24_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT24_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT24_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT24_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT24_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT24_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT24_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT24_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_SET_MUX_A_SHIFT))&CCM_PRE_ROOT24_SET_MUX_A_MASK) +#define CCM_PRE_ROOT24_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT24_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT24_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT24_SET_BUSY4_SHIFT 31 +/* PRE_ROOT24_CLR Bit Fields */ +#define CCM_PRE_ROOT24_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT24_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT24_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT24_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT24_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT24_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT24_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT24_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT24_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT24_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT24_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT24_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT24_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT24_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT24_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT24_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT24_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT24_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT24_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT24_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT24_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT24_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT24_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT24_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT24_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT24_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT24_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT24_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT24_TOG Bit Fields */ +#define CCM_PRE_ROOT24_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT24_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT24_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT24_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT24_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT24_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT24_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT24_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT24_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT24_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT24_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT24_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT24_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT24_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT24_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT24_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT24_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT24_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT24_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT24_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT24_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT24_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT24_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT24_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT24_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT24_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT24_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT24_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT24_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL24 Bit Fields */ +#define CCM_ACCESS_CTRL24_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL24_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL24_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL24_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL24_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL24_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL24_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL24_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL24_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL24_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL24_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL24_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL24_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL24_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL24_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL24_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL24_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL24_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL24_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL24_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL24_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL24_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL24_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL24_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL24_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL24_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL24_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL24_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL24_LOCK_SHIFT 31 +/* ACCESS_CTRL24_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL24_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL24_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL24_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL24_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL24_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL24_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL24_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL24_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL24_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL24_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL24_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL24_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL24_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL24_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL24_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL24_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL24_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL24_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT25 Bit Fields */ +#define CCM_TARGET_ROOT25_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT25_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT25_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_POST_PODF_MASK) +#define CCM_TARGET_ROOT25_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT25_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT25_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT25_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT25_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT25_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT25_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT25_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT25_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT25_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_PRE_PODF_MASK) +#define CCM_TARGET_ROOT25_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT25_MUX_SHIFT 24 +#define CCM_TARGET_ROOT25_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_MUX_SHIFT))&CCM_TARGET_ROOT25_MUX_MASK) +#define CCM_TARGET_ROOT25_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT25_ENABLE_SHIFT 28 +/* TARGET_ROOT25_SET Bit Fields */ +#define CCM_TARGET_ROOT25_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT25_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT25_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT25_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT25_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT25_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT25_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT25_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT25_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT25_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT25_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT25_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT25_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT25_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT25_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT25_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_SET_MUX_SHIFT))&CCM_TARGET_ROOT25_SET_MUX_MASK) +#define CCM_TARGET_ROOT25_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT25_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT25_CLR Bit Fields */ +#define CCM_TARGET_ROOT25_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT25_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT25_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT25_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT25_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT25_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT25_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT25_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT25_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT25_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT25_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT25_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT25_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_CLR_MUX_SHIFT))&CCM_TARGET_ROOT25_CLR_MUX_MASK) +#define CCM_TARGET_ROOT25_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT25_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT25_TOG Bit Fields */ +#define CCM_TARGET_ROOT25_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT25_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT25_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT25_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT25_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT25_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT25_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT25_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT25_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT25_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT25_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT25_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT25_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT25_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT25_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT25_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT25_TOG_MUX_SHIFT))&CCM_TARGET_ROOT25_TOG_MUX_MASK) +#define CCM_TARGET_ROOT25_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT25_TOG_ENABLE_SHIFT 28 +/* POST25 Bit Fields */ +#define CCM_POST25_POST_PODF_MASK 0x3Fu +#define CCM_POST25_POST_PODF_SHIFT 0 +#define CCM_POST25_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST25_POST_PODF_SHIFT))&CCM_POST25_POST_PODF_MASK) +#define CCM_POST25_BUSY1_MASK 0x80u +#define CCM_POST25_BUSY1_SHIFT 7 +#define CCM_POST25_AUTO_PODF_MASK 0x700u +#define CCM_POST25_AUTO_PODF_SHIFT 8 +#define CCM_POST25_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST25_AUTO_PODF_SHIFT))&CCM_POST25_AUTO_PODF_MASK) +#define CCM_POST25_AUTO_EN_MASK 0x1000u +#define CCM_POST25_AUTO_EN_SHIFT 12 +#define CCM_POST25_SLOW_MASK 0x8000u +#define CCM_POST25_SLOW_SHIFT 15 +#define CCM_POST25_SELECT_MASK 0x10000000u +#define CCM_POST25_SELECT_SHIFT 28 +#define CCM_POST25_BUSY2_MASK 0x80000000u +#define CCM_POST25_BUSY2_SHIFT 31 +/* POST_ROOT25_SET Bit Fields */ +#define CCM_POST_ROOT25_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT25_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT25_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_SET_POST_PODF_SHIFT))&CCM_POST_ROOT25_SET_POST_PODF_MASK) +#define CCM_POST_ROOT25_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT25_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT25_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT25_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT25_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT25_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT25_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT25_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT25_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT25_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT25_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT25_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT25_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT25_SET_BUSY2_SHIFT 31 +/* POST_ROOT25_CLR Bit Fields */ +#define CCM_POST_ROOT25_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT25_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT25_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT25_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT25_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT25_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT25_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT25_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT25_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT25_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT25_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT25_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT25_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT25_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT25_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT25_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT25_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT25_CLR_BUSY2_SHIFT 31 +/* POST_ROOT25_TOG Bit Fields */ +#define CCM_POST_ROOT25_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT25_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT25_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT25_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT25_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT25_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT25_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT25_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT25_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT25_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT25_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT25_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT25_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT25_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT25_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT25_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT25_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT25_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT25_TOG_BUSY2_SHIFT 31 +/* PRE25 Bit Fields */ +#define CCM_PRE25_PRE_PODF_B_MASK 0x7u +#define CCM_PRE25_PRE_PODF_B_SHIFT 0 +#define CCM_PRE25_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_PRE_PODF_B_SHIFT))&CCM_PRE25_PRE_PODF_B_MASK) +#define CCM_PRE25_BUSY0_MASK 0x8u +#define CCM_PRE25_BUSY0_SHIFT 3 +#define CCM_PRE25_MUX_B_MASK 0x700u +#define CCM_PRE25_MUX_B_SHIFT 8 +#define CCM_PRE25_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_MUX_B_SHIFT))&CCM_PRE25_MUX_B_MASK) +#define CCM_PRE25_EN_B_MASK 0x1000u +#define CCM_PRE25_EN_B_SHIFT 12 +#define CCM_PRE25_BUSY1_MASK 0x8000u +#define CCM_PRE25_BUSY1_SHIFT 15 +#define CCM_PRE25_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE25_PRE_PODF_A_SHIFT 16 +#define CCM_PRE25_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_PRE_PODF_A_SHIFT))&CCM_PRE25_PRE_PODF_A_MASK) +#define CCM_PRE25_BUSY3_MASK 0x80000u +#define CCM_PRE25_BUSY3_SHIFT 19 +#define CCM_PRE25_MUX_A_MASK 0x7000000u +#define CCM_PRE25_MUX_A_SHIFT 24 +#define CCM_PRE25_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE25_MUX_A_SHIFT))&CCM_PRE25_MUX_A_MASK) +#define CCM_PRE25_EN_A_MASK 0x10000000u +#define CCM_PRE25_EN_A_SHIFT 28 +#define CCM_PRE25_BUSY4_MASK 0x80000000u +#define CCM_PRE25_BUSY4_SHIFT 31 +/* PRE_ROOT25_SET Bit Fields */ +#define CCM_PRE_ROOT25_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT25_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT25_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT25_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT25_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT25_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT25_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT25_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT25_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_MUX_B_SHIFT))&CCM_PRE_ROOT25_SET_MUX_B_MASK) +#define CCM_PRE_ROOT25_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT25_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT25_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT25_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT25_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT25_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT25_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT25_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT25_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT25_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT25_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT25_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT25_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_SET_MUX_A_SHIFT))&CCM_PRE_ROOT25_SET_MUX_A_MASK) +#define CCM_PRE_ROOT25_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT25_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT25_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT25_SET_BUSY4_SHIFT 31 +/* PRE_ROOT25_CLR Bit Fields */ +#define CCM_PRE_ROOT25_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT25_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT25_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT25_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT25_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT25_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT25_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT25_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT25_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT25_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT25_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT25_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT25_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT25_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT25_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT25_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT25_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT25_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT25_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT25_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT25_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT25_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT25_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT25_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT25_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT25_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT25_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT25_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT25_TOG Bit Fields */ +#define CCM_PRE_ROOT25_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT25_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT25_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT25_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT25_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT25_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT25_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT25_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT25_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT25_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT25_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT25_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT25_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT25_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT25_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT25_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT25_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT25_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT25_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT25_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT25_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT25_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT25_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT25_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT25_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT25_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT25_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT25_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT25_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL25 Bit Fields */ +#define CCM_ACCESS_CTRL25_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL25_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL25_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL25_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL25_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL25_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL25_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL25_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL25_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL25_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL25_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL25_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL25_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL25_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL25_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL25_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL25_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL25_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL25_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL25_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL25_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL25_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL25_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL25_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL25_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL25_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL25_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL25_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL25_LOCK_SHIFT 31 +/* ACCESS_CTRL25_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL25_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL25_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL25_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL25_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL25_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL25_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL25_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL25_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL25_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL25_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL25_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL25_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL25_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL25_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL25_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL25_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL25_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL25_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT26 Bit Fields */ +#define CCM_TARGET_ROOT26_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT26_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT26_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_POST_PODF_MASK) +#define CCM_TARGET_ROOT26_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT26_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT26_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT26_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT26_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT26_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT26_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT26_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT26_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT26_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_PRE_PODF_MASK) +#define CCM_TARGET_ROOT26_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT26_MUX_SHIFT 24 +#define CCM_TARGET_ROOT26_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_MUX_SHIFT))&CCM_TARGET_ROOT26_MUX_MASK) +#define CCM_TARGET_ROOT26_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT26_ENABLE_SHIFT 28 +/* TARGET_ROOT26_SET Bit Fields */ +#define CCM_TARGET_ROOT26_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT26_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT26_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT26_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT26_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT26_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT26_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT26_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT26_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT26_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT26_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT26_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT26_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT26_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT26_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT26_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_SET_MUX_SHIFT))&CCM_TARGET_ROOT26_SET_MUX_MASK) +#define CCM_TARGET_ROOT26_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT26_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT26_CLR Bit Fields */ +#define CCM_TARGET_ROOT26_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT26_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT26_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT26_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT26_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT26_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT26_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT26_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT26_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT26_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT26_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT26_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT26_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_CLR_MUX_SHIFT))&CCM_TARGET_ROOT26_CLR_MUX_MASK) +#define CCM_TARGET_ROOT26_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT26_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT26_TOG Bit Fields */ +#define CCM_TARGET_ROOT26_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT26_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT26_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT26_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT26_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT26_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT26_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT26_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT26_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT26_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT26_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT26_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT26_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT26_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT26_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT26_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT26_TOG_MUX_SHIFT))&CCM_TARGET_ROOT26_TOG_MUX_MASK) +#define CCM_TARGET_ROOT26_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT26_TOG_ENABLE_SHIFT 28 +/* POST26 Bit Fields */ +#define CCM_POST26_POST_PODF_MASK 0x3Fu +#define CCM_POST26_POST_PODF_SHIFT 0 +#define CCM_POST26_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST26_POST_PODF_SHIFT))&CCM_POST26_POST_PODF_MASK) +#define CCM_POST26_BUSY1_MASK 0x80u +#define CCM_POST26_BUSY1_SHIFT 7 +#define CCM_POST26_AUTO_PODF_MASK 0x700u +#define CCM_POST26_AUTO_PODF_SHIFT 8 +#define CCM_POST26_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST26_AUTO_PODF_SHIFT))&CCM_POST26_AUTO_PODF_MASK) +#define CCM_POST26_AUTO_EN_MASK 0x1000u +#define CCM_POST26_AUTO_EN_SHIFT 12 +#define CCM_POST26_SLOW_MASK 0x8000u +#define CCM_POST26_SLOW_SHIFT 15 +#define CCM_POST26_SELECT_MASK 0x10000000u +#define CCM_POST26_SELECT_SHIFT 28 +#define CCM_POST26_BUSY2_MASK 0x80000000u +#define CCM_POST26_BUSY2_SHIFT 31 +/* POST_ROOT26_SET Bit Fields */ +#define CCM_POST_ROOT26_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT26_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT26_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_SET_POST_PODF_SHIFT))&CCM_POST_ROOT26_SET_POST_PODF_MASK) +#define CCM_POST_ROOT26_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT26_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT26_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT26_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT26_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT26_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT26_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT26_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT26_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT26_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT26_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT26_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT26_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT26_SET_BUSY2_SHIFT 31 +/* POST_ROOT26_CLR Bit Fields */ +#define CCM_POST_ROOT26_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT26_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT26_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT26_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT26_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT26_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT26_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT26_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT26_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT26_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT26_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT26_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT26_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT26_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT26_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT26_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT26_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT26_CLR_BUSY2_SHIFT 31 +/* POST_ROOT26_TOG Bit Fields */ +#define CCM_POST_ROOT26_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT26_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT26_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT26_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT26_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT26_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT26_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT26_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT26_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT26_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT26_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT26_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT26_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT26_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT26_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT26_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT26_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT26_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT26_TOG_BUSY2_SHIFT 31 +/* PRE26 Bit Fields */ +#define CCM_PRE26_PRE_PODF_B_MASK 0x7u +#define CCM_PRE26_PRE_PODF_B_SHIFT 0 +#define CCM_PRE26_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_PRE_PODF_B_SHIFT))&CCM_PRE26_PRE_PODF_B_MASK) +#define CCM_PRE26_BUSY0_MASK 0x8u +#define CCM_PRE26_BUSY0_SHIFT 3 +#define CCM_PRE26_MUX_B_MASK 0x700u +#define CCM_PRE26_MUX_B_SHIFT 8 +#define CCM_PRE26_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_MUX_B_SHIFT))&CCM_PRE26_MUX_B_MASK) +#define CCM_PRE26_EN_B_MASK 0x1000u +#define CCM_PRE26_EN_B_SHIFT 12 +#define CCM_PRE26_BUSY1_MASK 0x8000u +#define CCM_PRE26_BUSY1_SHIFT 15 +#define CCM_PRE26_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE26_PRE_PODF_A_SHIFT 16 +#define CCM_PRE26_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_PRE_PODF_A_SHIFT))&CCM_PRE26_PRE_PODF_A_MASK) +#define CCM_PRE26_BUSY3_MASK 0x80000u +#define CCM_PRE26_BUSY3_SHIFT 19 +#define CCM_PRE26_MUX_A_MASK 0x7000000u +#define CCM_PRE26_MUX_A_SHIFT 24 +#define CCM_PRE26_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE26_MUX_A_SHIFT))&CCM_PRE26_MUX_A_MASK) +#define CCM_PRE26_EN_A_MASK 0x10000000u +#define CCM_PRE26_EN_A_SHIFT 28 +#define CCM_PRE26_BUSY4_MASK 0x80000000u +#define CCM_PRE26_BUSY4_SHIFT 31 +/* PRE_ROOT26_SET Bit Fields */ +#define CCM_PRE_ROOT26_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT26_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT26_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT26_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT26_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT26_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT26_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT26_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT26_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_MUX_B_SHIFT))&CCM_PRE_ROOT26_SET_MUX_B_MASK) +#define CCM_PRE_ROOT26_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT26_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT26_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT26_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT26_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT26_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT26_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT26_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT26_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT26_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT26_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT26_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT26_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_SET_MUX_A_SHIFT))&CCM_PRE_ROOT26_SET_MUX_A_MASK) +#define CCM_PRE_ROOT26_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT26_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT26_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT26_SET_BUSY4_SHIFT 31 +/* PRE_ROOT26_CLR Bit Fields */ +#define CCM_PRE_ROOT26_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT26_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT26_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT26_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT26_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT26_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT26_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT26_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT26_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT26_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT26_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT26_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT26_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT26_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT26_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT26_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT26_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT26_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT26_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT26_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT26_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT26_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT26_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT26_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT26_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT26_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT26_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT26_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT26_TOG Bit Fields */ +#define CCM_PRE_ROOT26_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT26_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT26_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT26_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT26_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT26_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT26_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT26_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT26_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT26_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT26_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT26_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT26_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT26_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT26_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT26_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT26_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT26_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT26_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT26_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT26_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT26_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT26_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT26_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT26_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT26_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT26_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT26_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT26_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL26 Bit Fields */ +#define CCM_ACCESS_CTRL26_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL26_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL26_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL26_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL26_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL26_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL26_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL26_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL26_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL26_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL26_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL26_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL26_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL26_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL26_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL26_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL26_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL26_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL26_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL26_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL26_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL26_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL26_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL26_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL26_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL26_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL26_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL26_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL26_LOCK_SHIFT 31 +/* ACCESS_CTRL26_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL26_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL26_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL26_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL26_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL26_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL26_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL26_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL26_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL26_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL26_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL26_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL26_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL26_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL26_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL26_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL26_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL26_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL26_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT27 Bit Fields */ +#define CCM_TARGET_ROOT27_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT27_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT27_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_POST_PODF_MASK) +#define CCM_TARGET_ROOT27_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT27_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT27_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT27_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT27_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT27_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT27_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT27_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT27_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT27_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_PRE_PODF_MASK) +#define CCM_TARGET_ROOT27_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT27_MUX_SHIFT 24 +#define CCM_TARGET_ROOT27_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_MUX_SHIFT))&CCM_TARGET_ROOT27_MUX_MASK) +#define CCM_TARGET_ROOT27_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT27_ENABLE_SHIFT 28 +/* TARGET_ROOT27_SET Bit Fields */ +#define CCM_TARGET_ROOT27_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT27_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT27_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT27_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT27_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT27_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT27_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT27_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT27_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT27_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT27_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT27_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT27_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT27_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT27_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT27_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_SET_MUX_SHIFT))&CCM_TARGET_ROOT27_SET_MUX_MASK) +#define CCM_TARGET_ROOT27_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT27_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT27_CLR Bit Fields */ +#define CCM_TARGET_ROOT27_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT27_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT27_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT27_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT27_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT27_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT27_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT27_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT27_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT27_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT27_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT27_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT27_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_CLR_MUX_SHIFT))&CCM_TARGET_ROOT27_CLR_MUX_MASK) +#define CCM_TARGET_ROOT27_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT27_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT27_TOG Bit Fields */ +#define CCM_TARGET_ROOT27_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT27_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT27_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT27_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT27_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT27_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT27_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT27_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT27_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT27_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT27_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT27_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT27_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT27_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT27_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT27_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT27_TOG_MUX_SHIFT))&CCM_TARGET_ROOT27_TOG_MUX_MASK) +#define CCM_TARGET_ROOT27_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT27_TOG_ENABLE_SHIFT 28 +/* POST27 Bit Fields */ +#define CCM_POST27_POST_PODF_MASK 0x3Fu +#define CCM_POST27_POST_PODF_SHIFT 0 +#define CCM_POST27_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST27_POST_PODF_SHIFT))&CCM_POST27_POST_PODF_MASK) +#define CCM_POST27_BUSY1_MASK 0x80u +#define CCM_POST27_BUSY1_SHIFT 7 +#define CCM_POST27_AUTO_PODF_MASK 0x700u +#define CCM_POST27_AUTO_PODF_SHIFT 8 +#define CCM_POST27_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST27_AUTO_PODF_SHIFT))&CCM_POST27_AUTO_PODF_MASK) +#define CCM_POST27_AUTO_EN_MASK 0x1000u +#define CCM_POST27_AUTO_EN_SHIFT 12 +#define CCM_POST27_SLOW_MASK 0x8000u +#define CCM_POST27_SLOW_SHIFT 15 +#define CCM_POST27_SELECT_MASK 0x10000000u +#define CCM_POST27_SELECT_SHIFT 28 +#define CCM_POST27_BUSY2_MASK 0x80000000u +#define CCM_POST27_BUSY2_SHIFT 31 +/* POST_ROOT27_SET Bit Fields */ +#define CCM_POST_ROOT27_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT27_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT27_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_SET_POST_PODF_SHIFT))&CCM_POST_ROOT27_SET_POST_PODF_MASK) +#define CCM_POST_ROOT27_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT27_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT27_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT27_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT27_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT27_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT27_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT27_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT27_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT27_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT27_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT27_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT27_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT27_SET_BUSY2_SHIFT 31 +/* POST_ROOT27_CLR Bit Fields */ +#define CCM_POST_ROOT27_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT27_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT27_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT27_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT27_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT27_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT27_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT27_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT27_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT27_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT27_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT27_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT27_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT27_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT27_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT27_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT27_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT27_CLR_BUSY2_SHIFT 31 +/* POST_ROOT27_TOG Bit Fields */ +#define CCM_POST_ROOT27_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT27_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT27_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT27_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT27_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT27_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT27_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT27_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT27_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT27_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT27_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT27_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT27_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT27_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT27_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT27_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT27_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT27_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT27_TOG_BUSY2_SHIFT 31 +/* PRE27 Bit Fields */ +#define CCM_PRE27_PRE_PODF_B_MASK 0x7u +#define CCM_PRE27_PRE_PODF_B_SHIFT 0 +#define CCM_PRE27_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_PRE_PODF_B_SHIFT))&CCM_PRE27_PRE_PODF_B_MASK) +#define CCM_PRE27_BUSY0_MASK 0x8u +#define CCM_PRE27_BUSY0_SHIFT 3 +#define CCM_PRE27_MUX_B_MASK 0x700u +#define CCM_PRE27_MUX_B_SHIFT 8 +#define CCM_PRE27_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_MUX_B_SHIFT))&CCM_PRE27_MUX_B_MASK) +#define CCM_PRE27_EN_B_MASK 0x1000u +#define CCM_PRE27_EN_B_SHIFT 12 +#define CCM_PRE27_BUSY1_MASK 0x8000u +#define CCM_PRE27_BUSY1_SHIFT 15 +#define CCM_PRE27_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE27_PRE_PODF_A_SHIFT 16 +#define CCM_PRE27_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_PRE_PODF_A_SHIFT))&CCM_PRE27_PRE_PODF_A_MASK) +#define CCM_PRE27_BUSY3_MASK 0x80000u +#define CCM_PRE27_BUSY3_SHIFT 19 +#define CCM_PRE27_MUX_A_MASK 0x7000000u +#define CCM_PRE27_MUX_A_SHIFT 24 +#define CCM_PRE27_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE27_MUX_A_SHIFT))&CCM_PRE27_MUX_A_MASK) +#define CCM_PRE27_EN_A_MASK 0x10000000u +#define CCM_PRE27_EN_A_SHIFT 28 +#define CCM_PRE27_BUSY4_MASK 0x80000000u +#define CCM_PRE27_BUSY4_SHIFT 31 +/* PRE_ROOT27_SET Bit Fields */ +#define CCM_PRE_ROOT27_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT27_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT27_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT27_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT27_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT27_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT27_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT27_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT27_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_MUX_B_SHIFT))&CCM_PRE_ROOT27_SET_MUX_B_MASK) +#define CCM_PRE_ROOT27_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT27_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT27_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT27_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT27_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT27_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT27_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT27_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT27_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT27_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT27_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT27_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT27_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_SET_MUX_A_SHIFT))&CCM_PRE_ROOT27_SET_MUX_A_MASK) +#define CCM_PRE_ROOT27_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT27_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT27_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT27_SET_BUSY4_SHIFT 31 +/* PRE_ROOT27_CLR Bit Fields */ +#define CCM_PRE_ROOT27_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT27_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT27_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT27_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT27_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT27_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT27_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT27_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT27_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT27_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT27_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT27_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT27_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT27_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT27_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT27_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT27_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT27_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT27_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT27_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT27_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT27_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT27_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT27_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT27_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT27_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT27_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT27_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT27_TOG Bit Fields */ +#define CCM_PRE_ROOT27_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT27_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT27_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT27_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT27_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT27_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT27_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT27_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT27_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT27_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT27_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT27_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT27_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT27_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT27_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT27_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT27_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT27_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT27_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT27_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT27_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT27_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT27_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT27_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT27_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT27_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT27_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT27_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT27_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL27 Bit Fields */ +#define CCM_ACCESS_CTRL27_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL27_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL27_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL27_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL27_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL27_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL27_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL27_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL27_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL27_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL27_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL27_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL27_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL27_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL27_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL27_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL27_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL27_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL27_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL27_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL27_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL27_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL27_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL27_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL27_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL27_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL27_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL27_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL27_LOCK_SHIFT 31 +/* ACCESS_CTRL27_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL27_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL27_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL27_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL27_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL27_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL27_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL27_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL27_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL27_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL27_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL27_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL27_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL27_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL27_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL27_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL27_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL27_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL27_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT28 Bit Fields */ +#define CCM_TARGET_ROOT28_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT28_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT28_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_POST_PODF_MASK) +#define CCM_TARGET_ROOT28_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT28_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT28_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT28_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT28_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT28_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT28_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT28_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT28_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT28_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_PRE_PODF_MASK) +#define CCM_TARGET_ROOT28_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT28_MUX_SHIFT 24 +#define CCM_TARGET_ROOT28_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_MUX_SHIFT))&CCM_TARGET_ROOT28_MUX_MASK) +#define CCM_TARGET_ROOT28_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT28_ENABLE_SHIFT 28 +/* TARGET_ROOT28_SET Bit Fields */ +#define CCM_TARGET_ROOT28_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT28_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT28_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT28_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT28_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT28_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT28_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT28_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT28_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT28_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT28_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT28_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT28_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT28_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT28_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT28_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_SET_MUX_SHIFT))&CCM_TARGET_ROOT28_SET_MUX_MASK) +#define CCM_TARGET_ROOT28_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT28_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT28_CLR Bit Fields */ +#define CCM_TARGET_ROOT28_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT28_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT28_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT28_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT28_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT28_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT28_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT28_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT28_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT28_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT28_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT28_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT28_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_CLR_MUX_SHIFT))&CCM_TARGET_ROOT28_CLR_MUX_MASK) +#define CCM_TARGET_ROOT28_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT28_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT28_TOG Bit Fields */ +#define CCM_TARGET_ROOT28_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT28_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT28_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT28_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT28_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT28_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT28_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT28_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT28_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT28_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT28_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT28_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT28_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT28_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT28_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT28_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT28_TOG_MUX_SHIFT))&CCM_TARGET_ROOT28_TOG_MUX_MASK) +#define CCM_TARGET_ROOT28_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT28_TOG_ENABLE_SHIFT 28 +/* POST28 Bit Fields */ +#define CCM_POST28_POST_PODF_MASK 0x3Fu +#define CCM_POST28_POST_PODF_SHIFT 0 +#define CCM_POST28_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST28_POST_PODF_SHIFT))&CCM_POST28_POST_PODF_MASK) +#define CCM_POST28_BUSY1_MASK 0x80u +#define CCM_POST28_BUSY1_SHIFT 7 +#define CCM_POST28_AUTO_PODF_MASK 0x700u +#define CCM_POST28_AUTO_PODF_SHIFT 8 +#define CCM_POST28_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST28_AUTO_PODF_SHIFT))&CCM_POST28_AUTO_PODF_MASK) +#define CCM_POST28_AUTO_EN_MASK 0x1000u +#define CCM_POST28_AUTO_EN_SHIFT 12 +#define CCM_POST28_SLOW_MASK 0x8000u +#define CCM_POST28_SLOW_SHIFT 15 +#define CCM_POST28_SELECT_MASK 0x10000000u +#define CCM_POST28_SELECT_SHIFT 28 +#define CCM_POST28_BUSY2_MASK 0x80000000u +#define CCM_POST28_BUSY2_SHIFT 31 +/* POST_ROOT28_SET Bit Fields */ +#define CCM_POST_ROOT28_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT28_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT28_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_SET_POST_PODF_SHIFT))&CCM_POST_ROOT28_SET_POST_PODF_MASK) +#define CCM_POST_ROOT28_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT28_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT28_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT28_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT28_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT28_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT28_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT28_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT28_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT28_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT28_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT28_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT28_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT28_SET_BUSY2_SHIFT 31 +/* POST_ROOT28_CLR Bit Fields */ +#define CCM_POST_ROOT28_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT28_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT28_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT28_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT28_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT28_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT28_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT28_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT28_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT28_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT28_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT28_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT28_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT28_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT28_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT28_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT28_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT28_CLR_BUSY2_SHIFT 31 +/* POST_ROOT28_TOG Bit Fields */ +#define CCM_POST_ROOT28_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT28_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT28_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT28_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT28_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT28_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT28_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT28_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT28_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT28_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT28_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT28_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT28_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT28_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT28_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT28_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT28_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT28_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT28_TOG_BUSY2_SHIFT 31 +/* PRE28 Bit Fields */ +#define CCM_PRE28_PRE_PODF_B_MASK 0x7u +#define CCM_PRE28_PRE_PODF_B_SHIFT 0 +#define CCM_PRE28_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_PRE_PODF_B_SHIFT))&CCM_PRE28_PRE_PODF_B_MASK) +#define CCM_PRE28_BUSY0_MASK 0x8u +#define CCM_PRE28_BUSY0_SHIFT 3 +#define CCM_PRE28_MUX_B_MASK 0x700u +#define CCM_PRE28_MUX_B_SHIFT 8 +#define CCM_PRE28_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_MUX_B_SHIFT))&CCM_PRE28_MUX_B_MASK) +#define CCM_PRE28_EN_B_MASK 0x1000u +#define CCM_PRE28_EN_B_SHIFT 12 +#define CCM_PRE28_BUSY1_MASK 0x8000u +#define CCM_PRE28_BUSY1_SHIFT 15 +#define CCM_PRE28_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE28_PRE_PODF_A_SHIFT 16 +#define CCM_PRE28_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_PRE_PODF_A_SHIFT))&CCM_PRE28_PRE_PODF_A_MASK) +#define CCM_PRE28_BUSY3_MASK 0x80000u +#define CCM_PRE28_BUSY3_SHIFT 19 +#define CCM_PRE28_MUX_A_MASK 0x7000000u +#define CCM_PRE28_MUX_A_SHIFT 24 +#define CCM_PRE28_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE28_MUX_A_SHIFT))&CCM_PRE28_MUX_A_MASK) +#define CCM_PRE28_EN_A_MASK 0x10000000u +#define CCM_PRE28_EN_A_SHIFT 28 +#define CCM_PRE28_BUSY4_MASK 0x80000000u +#define CCM_PRE28_BUSY4_SHIFT 31 +/* PRE_ROOT28_SET Bit Fields */ +#define CCM_PRE_ROOT28_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT28_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT28_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT28_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT28_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT28_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT28_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT28_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT28_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_MUX_B_SHIFT))&CCM_PRE_ROOT28_SET_MUX_B_MASK) +#define CCM_PRE_ROOT28_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT28_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT28_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT28_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT28_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT28_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT28_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT28_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT28_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT28_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT28_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT28_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT28_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_SET_MUX_A_SHIFT))&CCM_PRE_ROOT28_SET_MUX_A_MASK) +#define CCM_PRE_ROOT28_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT28_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT28_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT28_SET_BUSY4_SHIFT 31 +/* PRE_ROOT28_CLR Bit Fields */ +#define CCM_PRE_ROOT28_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT28_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT28_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT28_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT28_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT28_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT28_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT28_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT28_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT28_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT28_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT28_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT28_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT28_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT28_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT28_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT28_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT28_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT28_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT28_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT28_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT28_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT28_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT28_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT28_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT28_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT28_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT28_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT28_TOG Bit Fields */ +#define CCM_PRE_ROOT28_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT28_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT28_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT28_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT28_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT28_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT28_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT28_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT28_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT28_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT28_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT28_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT28_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT28_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT28_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT28_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT28_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT28_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT28_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT28_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT28_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT28_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT28_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT28_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT28_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT28_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT28_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT28_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT28_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL28 Bit Fields */ +#define CCM_ACCESS_CTRL28_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL28_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL28_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL28_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL28_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL28_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL28_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL28_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL28_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL28_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL28_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL28_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL28_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL28_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL28_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL28_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL28_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL28_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL28_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL28_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL28_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL28_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL28_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL28_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL28_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL28_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL28_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL28_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL28_LOCK_SHIFT 31 +/* ACCESS_CTRL28_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL28_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL28_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL28_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL28_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL28_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL28_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL28_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL28_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL28_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL28_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL28_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL28_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL28_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL28_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL28_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL28_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL28_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL28_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT29 Bit Fields */ +#define CCM_TARGET_ROOT29_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT29_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT29_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_POST_PODF_MASK) +#define CCM_TARGET_ROOT29_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT29_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT29_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT29_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT29_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT29_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT29_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT29_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT29_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT29_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_PRE_PODF_MASK) +#define CCM_TARGET_ROOT29_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT29_MUX_SHIFT 24 +#define CCM_TARGET_ROOT29_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_MUX_SHIFT))&CCM_TARGET_ROOT29_MUX_MASK) +#define CCM_TARGET_ROOT29_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT29_ENABLE_SHIFT 28 +/* TARGET_ROOT29_SET Bit Fields */ +#define CCM_TARGET_ROOT29_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT29_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT29_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT29_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT29_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT29_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT29_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT29_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT29_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT29_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT29_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT29_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT29_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT29_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT29_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT29_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_SET_MUX_SHIFT))&CCM_TARGET_ROOT29_SET_MUX_MASK) +#define CCM_TARGET_ROOT29_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT29_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT29_CLR Bit Fields */ +#define CCM_TARGET_ROOT29_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT29_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT29_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT29_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT29_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT29_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT29_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT29_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT29_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT29_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT29_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT29_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT29_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_CLR_MUX_SHIFT))&CCM_TARGET_ROOT29_CLR_MUX_MASK) +#define CCM_TARGET_ROOT29_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT29_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT29_TOG Bit Fields */ +#define CCM_TARGET_ROOT29_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT29_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT29_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT29_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT29_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT29_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT29_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT29_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT29_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT29_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT29_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT29_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT29_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT29_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT29_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT29_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT29_TOG_MUX_SHIFT))&CCM_TARGET_ROOT29_TOG_MUX_MASK) +#define CCM_TARGET_ROOT29_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT29_TOG_ENABLE_SHIFT 28 +/* POST29 Bit Fields */ +#define CCM_POST29_POST_PODF_MASK 0x3Fu +#define CCM_POST29_POST_PODF_SHIFT 0 +#define CCM_POST29_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST29_POST_PODF_SHIFT))&CCM_POST29_POST_PODF_MASK) +#define CCM_POST29_BUSY1_MASK 0x80u +#define CCM_POST29_BUSY1_SHIFT 7 +#define CCM_POST29_AUTO_PODF_MASK 0x700u +#define CCM_POST29_AUTO_PODF_SHIFT 8 +#define CCM_POST29_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST29_AUTO_PODF_SHIFT))&CCM_POST29_AUTO_PODF_MASK) +#define CCM_POST29_AUTO_EN_MASK 0x1000u +#define CCM_POST29_AUTO_EN_SHIFT 12 +#define CCM_POST29_SLOW_MASK 0x8000u +#define CCM_POST29_SLOW_SHIFT 15 +#define CCM_POST29_SELECT_MASK 0x10000000u +#define CCM_POST29_SELECT_SHIFT 28 +#define CCM_POST29_BUSY2_MASK 0x80000000u +#define CCM_POST29_BUSY2_SHIFT 31 +/* POST_ROOT29_SET Bit Fields */ +#define CCM_POST_ROOT29_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT29_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT29_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_SET_POST_PODF_SHIFT))&CCM_POST_ROOT29_SET_POST_PODF_MASK) +#define CCM_POST_ROOT29_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT29_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT29_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT29_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT29_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT29_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT29_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT29_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT29_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT29_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT29_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT29_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT29_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT29_SET_BUSY2_SHIFT 31 +/* POST_ROOT29_CLR Bit Fields */ +#define CCM_POST_ROOT29_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT29_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT29_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT29_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT29_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT29_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT29_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT29_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT29_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT29_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT29_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT29_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT29_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT29_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT29_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT29_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT29_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT29_CLR_BUSY2_SHIFT 31 +/* POST_ROOT29_TOG Bit Fields */ +#define CCM_POST_ROOT29_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT29_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT29_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT29_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT29_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT29_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT29_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT29_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT29_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT29_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT29_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT29_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT29_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT29_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT29_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT29_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT29_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT29_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT29_TOG_BUSY2_SHIFT 31 +/* PRE29 Bit Fields */ +#define CCM_PRE29_PRE_PODF_B_MASK 0x7u +#define CCM_PRE29_PRE_PODF_B_SHIFT 0 +#define CCM_PRE29_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_PRE_PODF_B_SHIFT))&CCM_PRE29_PRE_PODF_B_MASK) +#define CCM_PRE29_BUSY0_MASK 0x8u +#define CCM_PRE29_BUSY0_SHIFT 3 +#define CCM_PRE29_MUX_B_MASK 0x700u +#define CCM_PRE29_MUX_B_SHIFT 8 +#define CCM_PRE29_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_MUX_B_SHIFT))&CCM_PRE29_MUX_B_MASK) +#define CCM_PRE29_EN_B_MASK 0x1000u +#define CCM_PRE29_EN_B_SHIFT 12 +#define CCM_PRE29_BUSY1_MASK 0x8000u +#define CCM_PRE29_BUSY1_SHIFT 15 +#define CCM_PRE29_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE29_PRE_PODF_A_SHIFT 16 +#define CCM_PRE29_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_PRE_PODF_A_SHIFT))&CCM_PRE29_PRE_PODF_A_MASK) +#define CCM_PRE29_BUSY3_MASK 0x80000u +#define CCM_PRE29_BUSY3_SHIFT 19 +#define CCM_PRE29_MUX_A_MASK 0x7000000u +#define CCM_PRE29_MUX_A_SHIFT 24 +#define CCM_PRE29_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE29_MUX_A_SHIFT))&CCM_PRE29_MUX_A_MASK) +#define CCM_PRE29_EN_A_MASK 0x10000000u +#define CCM_PRE29_EN_A_SHIFT 28 +#define CCM_PRE29_BUSY4_MASK 0x80000000u +#define CCM_PRE29_BUSY4_SHIFT 31 +/* PRE_ROOT29_SET Bit Fields */ +#define CCM_PRE_ROOT29_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT29_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT29_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT29_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT29_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT29_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT29_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT29_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT29_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_MUX_B_SHIFT))&CCM_PRE_ROOT29_SET_MUX_B_MASK) +#define CCM_PRE_ROOT29_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT29_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT29_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT29_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT29_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT29_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT29_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT29_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT29_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT29_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT29_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT29_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT29_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_SET_MUX_A_SHIFT))&CCM_PRE_ROOT29_SET_MUX_A_MASK) +#define CCM_PRE_ROOT29_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT29_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT29_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT29_SET_BUSY4_SHIFT 31 +/* PRE_ROOT29_CLR Bit Fields */ +#define CCM_PRE_ROOT29_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT29_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT29_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT29_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT29_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT29_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT29_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT29_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT29_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT29_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT29_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT29_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT29_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT29_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT29_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT29_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT29_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT29_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT29_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT29_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT29_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT29_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT29_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT29_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT29_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT29_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT29_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT29_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT29_TOG Bit Fields */ +#define CCM_PRE_ROOT29_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT29_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT29_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT29_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT29_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT29_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT29_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT29_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT29_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT29_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT29_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT29_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT29_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT29_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT29_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT29_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT29_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT29_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT29_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT29_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT29_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT29_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT29_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT29_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT29_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT29_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT29_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT29_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT29_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL29 Bit Fields */ +#define CCM_ACCESS_CTRL29_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL29_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL29_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL29_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL29_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL29_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL29_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL29_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL29_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL29_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL29_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL29_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL29_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL29_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL29_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL29_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL29_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL29_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL29_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL29_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL29_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL29_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL29_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL29_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL29_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL29_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL29_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL29_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL29_LOCK_SHIFT 31 +/* ACCESS_CTRL29_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL29_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL29_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL29_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL29_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL29_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL29_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL29_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL29_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL29_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL29_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL29_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL29_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL29_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL29_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL29_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL29_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL29_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL29_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT30 Bit Fields */ +#define CCM_TARGET_ROOT30_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT30_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT30_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_POST_PODF_MASK) +#define CCM_TARGET_ROOT30_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT30_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT30_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT30_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT30_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT30_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT30_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT30_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT30_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT30_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_PRE_PODF_MASK) +#define CCM_TARGET_ROOT30_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT30_MUX_SHIFT 24 +#define CCM_TARGET_ROOT30_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_MUX_SHIFT))&CCM_TARGET_ROOT30_MUX_MASK) +#define CCM_TARGET_ROOT30_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT30_ENABLE_SHIFT 28 +/* TARGET_ROOT30_SET Bit Fields */ +#define CCM_TARGET_ROOT30_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT30_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT30_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT30_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT30_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT30_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT30_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT30_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT30_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT30_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT30_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT30_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT30_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT30_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT30_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT30_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_SET_MUX_SHIFT))&CCM_TARGET_ROOT30_SET_MUX_MASK) +#define CCM_TARGET_ROOT30_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT30_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT30_CLR Bit Fields */ +#define CCM_TARGET_ROOT30_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT30_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT30_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT30_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT30_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT30_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT30_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT30_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT30_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT30_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT30_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT30_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT30_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_CLR_MUX_SHIFT))&CCM_TARGET_ROOT30_CLR_MUX_MASK) +#define CCM_TARGET_ROOT30_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT30_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT30_TOG Bit Fields */ +#define CCM_TARGET_ROOT30_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT30_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT30_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT30_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT30_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT30_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT30_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT30_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT30_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT30_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT30_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT30_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT30_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT30_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT30_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT30_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT30_TOG_MUX_SHIFT))&CCM_TARGET_ROOT30_TOG_MUX_MASK) +#define CCM_TARGET_ROOT30_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT30_TOG_ENABLE_SHIFT 28 +/* POST30 Bit Fields */ +#define CCM_POST30_POST_PODF_MASK 0x3Fu +#define CCM_POST30_POST_PODF_SHIFT 0 +#define CCM_POST30_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST30_POST_PODF_SHIFT))&CCM_POST30_POST_PODF_MASK) +#define CCM_POST30_BUSY1_MASK 0x80u +#define CCM_POST30_BUSY1_SHIFT 7 +#define CCM_POST30_AUTO_PODF_MASK 0x700u +#define CCM_POST30_AUTO_PODF_SHIFT 8 +#define CCM_POST30_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST30_AUTO_PODF_SHIFT))&CCM_POST30_AUTO_PODF_MASK) +#define CCM_POST30_AUTO_EN_MASK 0x1000u +#define CCM_POST30_AUTO_EN_SHIFT 12 +#define CCM_POST30_SLOW_MASK 0x8000u +#define CCM_POST30_SLOW_SHIFT 15 +#define CCM_POST30_SELECT_MASK 0x10000000u +#define CCM_POST30_SELECT_SHIFT 28 +#define CCM_POST30_BUSY2_MASK 0x80000000u +#define CCM_POST30_BUSY2_SHIFT 31 +/* POST_ROOT30_SET Bit Fields */ +#define CCM_POST_ROOT30_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT30_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT30_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_SET_POST_PODF_SHIFT))&CCM_POST_ROOT30_SET_POST_PODF_MASK) +#define CCM_POST_ROOT30_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT30_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT30_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT30_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT30_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT30_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT30_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT30_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT30_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT30_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT30_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT30_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT30_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT30_SET_BUSY2_SHIFT 31 +/* POST_ROOT30_CLR Bit Fields */ +#define CCM_POST_ROOT30_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT30_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT30_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT30_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT30_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT30_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT30_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT30_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT30_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT30_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT30_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT30_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT30_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT30_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT30_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT30_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT30_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT30_CLR_BUSY2_SHIFT 31 +/* POST_ROOT30_TOG Bit Fields */ +#define CCM_POST_ROOT30_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT30_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT30_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT30_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT30_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT30_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT30_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT30_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT30_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT30_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT30_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT30_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT30_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT30_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT30_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT30_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT30_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT30_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT30_TOG_BUSY2_SHIFT 31 +/* PRE30 Bit Fields */ +#define CCM_PRE30_PRE_PODF_B_MASK 0x7u +#define CCM_PRE30_PRE_PODF_B_SHIFT 0 +#define CCM_PRE30_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_PRE_PODF_B_SHIFT))&CCM_PRE30_PRE_PODF_B_MASK) +#define CCM_PRE30_BUSY0_MASK 0x8u +#define CCM_PRE30_BUSY0_SHIFT 3 +#define CCM_PRE30_MUX_B_MASK 0x700u +#define CCM_PRE30_MUX_B_SHIFT 8 +#define CCM_PRE30_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_MUX_B_SHIFT))&CCM_PRE30_MUX_B_MASK) +#define CCM_PRE30_EN_B_MASK 0x1000u +#define CCM_PRE30_EN_B_SHIFT 12 +#define CCM_PRE30_BUSY1_MASK 0x8000u +#define CCM_PRE30_BUSY1_SHIFT 15 +#define CCM_PRE30_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE30_PRE_PODF_A_SHIFT 16 +#define CCM_PRE30_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_PRE_PODF_A_SHIFT))&CCM_PRE30_PRE_PODF_A_MASK) +#define CCM_PRE30_BUSY3_MASK 0x80000u +#define CCM_PRE30_BUSY3_SHIFT 19 +#define CCM_PRE30_MUX_A_MASK 0x7000000u +#define CCM_PRE30_MUX_A_SHIFT 24 +#define CCM_PRE30_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE30_MUX_A_SHIFT))&CCM_PRE30_MUX_A_MASK) +#define CCM_PRE30_EN_A_MASK 0x10000000u +#define CCM_PRE30_EN_A_SHIFT 28 +#define CCM_PRE30_BUSY4_MASK 0x80000000u +#define CCM_PRE30_BUSY4_SHIFT 31 +/* PRE_ROOT30_SET Bit Fields */ +#define CCM_PRE_ROOT30_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT30_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT30_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT30_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT30_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT30_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT30_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT30_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT30_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_MUX_B_SHIFT))&CCM_PRE_ROOT30_SET_MUX_B_MASK) +#define CCM_PRE_ROOT30_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT30_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT30_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT30_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT30_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT30_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT30_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT30_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT30_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT30_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT30_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT30_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT30_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_SET_MUX_A_SHIFT))&CCM_PRE_ROOT30_SET_MUX_A_MASK) +#define CCM_PRE_ROOT30_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT30_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT30_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT30_SET_BUSY4_SHIFT 31 +/* PRE_ROOT30_CLR Bit Fields */ +#define CCM_PRE_ROOT30_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT30_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT30_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT30_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT30_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT30_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT30_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT30_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT30_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT30_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT30_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT30_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT30_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT30_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT30_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT30_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT30_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT30_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT30_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT30_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT30_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT30_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT30_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT30_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT30_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT30_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT30_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT30_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT30_TOG Bit Fields */ +#define CCM_PRE_ROOT30_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT30_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT30_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT30_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT30_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT30_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT30_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT30_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT30_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT30_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT30_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT30_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT30_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT30_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT30_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT30_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT30_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT30_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT30_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT30_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT30_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT30_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT30_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT30_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT30_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT30_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT30_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT30_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT30_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL30 Bit Fields */ +#define CCM_ACCESS_CTRL30_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL30_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL30_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL30_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL30_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL30_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL30_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL30_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL30_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL30_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL30_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL30_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL30_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL30_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL30_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL30_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL30_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL30_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL30_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL30_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL30_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL30_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL30_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL30_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL30_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL30_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL30_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL30_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL30_LOCK_SHIFT 31 +/* ACCESS_CTRL30_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL30_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL30_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL30_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL30_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL30_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL30_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL30_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL30_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL30_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL30_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL30_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL30_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL30_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL30_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL30_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL30_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL30_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL30_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT31 Bit Fields */ +#define CCM_TARGET_ROOT31_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT31_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT31_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_POST_PODF_MASK) +#define CCM_TARGET_ROOT31_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT31_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT31_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT31_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT31_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT31_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT31_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT31_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT31_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT31_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_PRE_PODF_MASK) +#define CCM_TARGET_ROOT31_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT31_MUX_SHIFT 24 +#define CCM_TARGET_ROOT31_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_MUX_SHIFT))&CCM_TARGET_ROOT31_MUX_MASK) +#define CCM_TARGET_ROOT31_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT31_ENABLE_SHIFT 28 +/* TARGET_ROOT31_SET Bit Fields */ +#define CCM_TARGET_ROOT31_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT31_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT31_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT31_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT31_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT31_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT31_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT31_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT31_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT31_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT31_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT31_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT31_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT31_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT31_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT31_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_SET_MUX_SHIFT))&CCM_TARGET_ROOT31_SET_MUX_MASK) +#define CCM_TARGET_ROOT31_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT31_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT31_CLR Bit Fields */ +#define CCM_TARGET_ROOT31_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT31_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT31_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT31_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT31_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT31_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT31_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT31_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT31_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT31_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT31_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT31_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT31_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_CLR_MUX_SHIFT))&CCM_TARGET_ROOT31_CLR_MUX_MASK) +#define CCM_TARGET_ROOT31_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT31_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT31_TOG Bit Fields */ +#define CCM_TARGET_ROOT31_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT31_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT31_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT31_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT31_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT31_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT31_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT31_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT31_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT31_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT31_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT31_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT31_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT31_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT31_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT31_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT31_TOG_MUX_SHIFT))&CCM_TARGET_ROOT31_TOG_MUX_MASK) +#define CCM_TARGET_ROOT31_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT31_TOG_ENABLE_SHIFT 28 +/* POST31 Bit Fields */ +#define CCM_POST31_POST_PODF_MASK 0x3Fu +#define CCM_POST31_POST_PODF_SHIFT 0 +#define CCM_POST31_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST31_POST_PODF_SHIFT))&CCM_POST31_POST_PODF_MASK) +#define CCM_POST31_BUSY1_MASK 0x80u +#define CCM_POST31_BUSY1_SHIFT 7 +#define CCM_POST31_AUTO_PODF_MASK 0x700u +#define CCM_POST31_AUTO_PODF_SHIFT 8 +#define CCM_POST31_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST31_AUTO_PODF_SHIFT))&CCM_POST31_AUTO_PODF_MASK) +#define CCM_POST31_AUTO_EN_MASK 0x1000u +#define CCM_POST31_AUTO_EN_SHIFT 12 +#define CCM_POST31_SLOW_MASK 0x8000u +#define CCM_POST31_SLOW_SHIFT 15 +#define CCM_POST31_SELECT_MASK 0x10000000u +#define CCM_POST31_SELECT_SHIFT 28 +#define CCM_POST31_BUSY2_MASK 0x80000000u +#define CCM_POST31_BUSY2_SHIFT 31 +/* POST_ROOT31_SET Bit Fields */ +#define CCM_POST_ROOT31_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT31_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT31_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_SET_POST_PODF_SHIFT))&CCM_POST_ROOT31_SET_POST_PODF_MASK) +#define CCM_POST_ROOT31_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT31_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT31_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT31_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT31_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT31_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT31_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT31_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT31_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT31_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT31_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT31_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT31_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT31_SET_BUSY2_SHIFT 31 +/* POST_ROOT31_CLR Bit Fields */ +#define CCM_POST_ROOT31_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT31_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT31_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT31_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT31_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT31_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT31_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT31_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT31_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT31_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT31_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT31_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT31_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT31_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT31_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT31_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT31_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT31_CLR_BUSY2_SHIFT 31 +/* POST_ROOT31_TOG Bit Fields */ +#define CCM_POST_ROOT31_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT31_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT31_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT31_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT31_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT31_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT31_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT31_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT31_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT31_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT31_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT31_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT31_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT31_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT31_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT31_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT31_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT31_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT31_TOG_BUSY2_SHIFT 31 +/* PRE31 Bit Fields */ +#define CCM_PRE31_PRE_PODF_B_MASK 0x7u +#define CCM_PRE31_PRE_PODF_B_SHIFT 0 +#define CCM_PRE31_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_PRE_PODF_B_SHIFT))&CCM_PRE31_PRE_PODF_B_MASK) +#define CCM_PRE31_BUSY0_MASK 0x8u +#define CCM_PRE31_BUSY0_SHIFT 3 +#define CCM_PRE31_MUX_B_MASK 0x700u +#define CCM_PRE31_MUX_B_SHIFT 8 +#define CCM_PRE31_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_MUX_B_SHIFT))&CCM_PRE31_MUX_B_MASK) +#define CCM_PRE31_EN_B_MASK 0x1000u +#define CCM_PRE31_EN_B_SHIFT 12 +#define CCM_PRE31_BUSY1_MASK 0x8000u +#define CCM_PRE31_BUSY1_SHIFT 15 +#define CCM_PRE31_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE31_PRE_PODF_A_SHIFT 16 +#define CCM_PRE31_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_PRE_PODF_A_SHIFT))&CCM_PRE31_PRE_PODF_A_MASK) +#define CCM_PRE31_BUSY3_MASK 0x80000u +#define CCM_PRE31_BUSY3_SHIFT 19 +#define CCM_PRE31_MUX_A_MASK 0x7000000u +#define CCM_PRE31_MUX_A_SHIFT 24 +#define CCM_PRE31_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE31_MUX_A_SHIFT))&CCM_PRE31_MUX_A_MASK) +#define CCM_PRE31_EN_A_MASK 0x10000000u +#define CCM_PRE31_EN_A_SHIFT 28 +#define CCM_PRE31_BUSY4_MASK 0x80000000u +#define CCM_PRE31_BUSY4_SHIFT 31 +/* PRE_ROOT31_SET Bit Fields */ +#define CCM_PRE_ROOT31_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT31_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT31_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT31_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT31_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT31_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT31_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT31_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT31_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_MUX_B_SHIFT))&CCM_PRE_ROOT31_SET_MUX_B_MASK) +#define CCM_PRE_ROOT31_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT31_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT31_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT31_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT31_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT31_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT31_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT31_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT31_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT31_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT31_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT31_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT31_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_SET_MUX_A_SHIFT))&CCM_PRE_ROOT31_SET_MUX_A_MASK) +#define CCM_PRE_ROOT31_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT31_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT31_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT31_SET_BUSY4_SHIFT 31 +/* PRE_ROOT31_CLR Bit Fields */ +#define CCM_PRE_ROOT31_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT31_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT31_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT31_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT31_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT31_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT31_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT31_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT31_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT31_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT31_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT31_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT31_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT31_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT31_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT31_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT31_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT31_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT31_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT31_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT31_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT31_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT31_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT31_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT31_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT31_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT31_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT31_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT31_TOG Bit Fields */ +#define CCM_PRE_ROOT31_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT31_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT31_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT31_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT31_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT31_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT31_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT31_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT31_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT31_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT31_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT31_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT31_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT31_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT31_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT31_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT31_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT31_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT31_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT31_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT31_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT31_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT31_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT31_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT31_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT31_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT31_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT31_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT31_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL31 Bit Fields */ +#define CCM_ACCESS_CTRL31_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL31_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL31_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL31_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL31_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL31_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL31_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL31_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL31_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL31_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL31_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL31_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL31_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL31_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL31_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL31_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL31_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL31_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL31_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL31_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL31_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL31_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL31_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL31_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL31_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL31_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL31_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL31_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL31_LOCK_SHIFT 31 +/* ACCESS_CTRL31_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL31_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL31_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL31_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL31_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL31_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL31_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL31_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL31_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL31_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL31_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL31_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL31_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL31_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL31_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL31_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL31_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL31_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL31_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT32 Bit Fields */ +#define CCM_TARGET_ROOT32_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT32_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT32_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_POST_PODF_MASK) +#define CCM_TARGET_ROOT32_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT32_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT32_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT32_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT32_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT32_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT32_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT32_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT32_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT32_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_PRE_PODF_MASK) +#define CCM_TARGET_ROOT32_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT32_MUX_SHIFT 24 +#define CCM_TARGET_ROOT32_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_MUX_SHIFT))&CCM_TARGET_ROOT32_MUX_MASK) +#define CCM_TARGET_ROOT32_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT32_ENABLE_SHIFT 28 +/* TARGET_ROOT32_SET Bit Fields */ +#define CCM_TARGET_ROOT32_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT32_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT32_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT32_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT32_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT32_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT32_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT32_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT32_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT32_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT32_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT32_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT32_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT32_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT32_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT32_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_SET_MUX_SHIFT))&CCM_TARGET_ROOT32_SET_MUX_MASK) +#define CCM_TARGET_ROOT32_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT32_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT32_CLR Bit Fields */ +#define CCM_TARGET_ROOT32_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT32_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT32_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT32_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT32_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT32_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT32_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT32_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT32_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT32_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT32_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT32_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT32_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_CLR_MUX_SHIFT))&CCM_TARGET_ROOT32_CLR_MUX_MASK) +#define CCM_TARGET_ROOT32_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT32_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT32_TOG Bit Fields */ +#define CCM_TARGET_ROOT32_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT32_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT32_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT32_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT32_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT32_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT32_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT32_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT32_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT32_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT32_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT32_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT32_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT32_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT32_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT32_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT32_TOG_MUX_SHIFT))&CCM_TARGET_ROOT32_TOG_MUX_MASK) +#define CCM_TARGET_ROOT32_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT32_TOG_ENABLE_SHIFT 28 +/* POST32 Bit Fields */ +#define CCM_POST32_POST_PODF_MASK 0x3Fu +#define CCM_POST32_POST_PODF_SHIFT 0 +#define CCM_POST32_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST32_POST_PODF_SHIFT))&CCM_POST32_POST_PODF_MASK) +#define CCM_POST32_BUSY1_MASK 0x80u +#define CCM_POST32_BUSY1_SHIFT 7 +#define CCM_POST32_AUTO_PODF_MASK 0x700u +#define CCM_POST32_AUTO_PODF_SHIFT 8 +#define CCM_POST32_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST32_AUTO_PODF_SHIFT))&CCM_POST32_AUTO_PODF_MASK) +#define CCM_POST32_AUTO_EN_MASK 0x1000u +#define CCM_POST32_AUTO_EN_SHIFT 12 +#define CCM_POST32_SLOW_MASK 0x8000u +#define CCM_POST32_SLOW_SHIFT 15 +#define CCM_POST32_SELECT_MASK 0x10000000u +#define CCM_POST32_SELECT_SHIFT 28 +#define CCM_POST32_BUSY2_MASK 0x80000000u +#define CCM_POST32_BUSY2_SHIFT 31 +/* POST_ROOT32_SET Bit Fields */ +#define CCM_POST_ROOT32_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT32_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT32_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_SET_POST_PODF_SHIFT))&CCM_POST_ROOT32_SET_POST_PODF_MASK) +#define CCM_POST_ROOT32_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT32_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT32_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT32_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT32_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT32_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT32_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT32_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT32_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT32_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT32_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT32_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT32_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT32_SET_BUSY2_SHIFT 31 +/* POST_ROOT32_CLR Bit Fields */ +#define CCM_POST_ROOT32_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT32_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT32_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT32_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT32_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT32_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT32_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT32_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT32_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT32_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT32_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT32_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT32_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT32_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT32_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT32_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT32_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT32_CLR_BUSY2_SHIFT 31 +/* POST_ROOT32_TOG Bit Fields */ +#define CCM_POST_ROOT32_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT32_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT32_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT32_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT32_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT32_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT32_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT32_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT32_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT32_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT32_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT32_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT32_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT32_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT32_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT32_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT32_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT32_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT32_TOG_BUSY2_SHIFT 31 +/* PRE32 Bit Fields */ +#define CCM_PRE32_PRE_PODF_B_MASK 0x7u +#define CCM_PRE32_PRE_PODF_B_SHIFT 0 +#define CCM_PRE32_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_PRE_PODF_B_SHIFT))&CCM_PRE32_PRE_PODF_B_MASK) +#define CCM_PRE32_BUSY0_MASK 0x8u +#define CCM_PRE32_BUSY0_SHIFT 3 +#define CCM_PRE32_MUX_B_MASK 0x700u +#define CCM_PRE32_MUX_B_SHIFT 8 +#define CCM_PRE32_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_MUX_B_SHIFT))&CCM_PRE32_MUX_B_MASK) +#define CCM_PRE32_EN_B_MASK 0x1000u +#define CCM_PRE32_EN_B_SHIFT 12 +#define CCM_PRE32_BUSY1_MASK 0x8000u +#define CCM_PRE32_BUSY1_SHIFT 15 +#define CCM_PRE32_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE32_PRE_PODF_A_SHIFT 16 +#define CCM_PRE32_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_PRE_PODF_A_SHIFT))&CCM_PRE32_PRE_PODF_A_MASK) +#define CCM_PRE32_BUSY3_MASK 0x80000u +#define CCM_PRE32_BUSY3_SHIFT 19 +#define CCM_PRE32_MUX_A_MASK 0x7000000u +#define CCM_PRE32_MUX_A_SHIFT 24 +#define CCM_PRE32_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE32_MUX_A_SHIFT))&CCM_PRE32_MUX_A_MASK) +#define CCM_PRE32_EN_A_MASK 0x10000000u +#define CCM_PRE32_EN_A_SHIFT 28 +#define CCM_PRE32_BUSY4_MASK 0x80000000u +#define CCM_PRE32_BUSY4_SHIFT 31 +/* PRE_ROOT32_SET Bit Fields */ +#define CCM_PRE_ROOT32_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT32_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT32_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT32_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT32_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT32_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT32_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT32_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT32_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_MUX_B_SHIFT))&CCM_PRE_ROOT32_SET_MUX_B_MASK) +#define CCM_PRE_ROOT32_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT32_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT32_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT32_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT32_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT32_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT32_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT32_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT32_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT32_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT32_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT32_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT32_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_SET_MUX_A_SHIFT))&CCM_PRE_ROOT32_SET_MUX_A_MASK) +#define CCM_PRE_ROOT32_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT32_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT32_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT32_SET_BUSY4_SHIFT 31 +/* PRE_ROOT32_CLR Bit Fields */ +#define CCM_PRE_ROOT32_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT32_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT32_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT32_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT32_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT32_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT32_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT32_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT32_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT32_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT32_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT32_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT32_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT32_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT32_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT32_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT32_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT32_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT32_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT32_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT32_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT32_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT32_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT32_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT32_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT32_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT32_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT32_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT32_TOG Bit Fields */ +#define CCM_PRE_ROOT32_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT32_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT32_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT32_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT32_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT32_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT32_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT32_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT32_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT32_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT32_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT32_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT32_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT32_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT32_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT32_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT32_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT32_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT32_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT32_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT32_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT32_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT32_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT32_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT32_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT32_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT32_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT32_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT32_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL32 Bit Fields */ +#define CCM_ACCESS_CTRL32_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL32_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL32_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL32_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL32_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL32_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL32_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL32_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL32_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL32_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL32_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL32_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL32_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL32_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL32_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL32_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL32_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL32_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL32_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL32_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL32_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL32_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL32_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL32_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL32_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL32_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL32_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL32_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL32_LOCK_SHIFT 31 +/* ACCESS_CTRL32_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL32_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL32_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL32_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL32_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL32_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL32_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL32_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL32_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL32_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL32_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL32_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL32_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL32_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL32_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL32_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL32_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL32_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL32_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT33 Bit Fields */ +#define CCM_TARGET_ROOT33_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT33_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT33_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_POST_PODF_MASK) +#define CCM_TARGET_ROOT33_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT33_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT33_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT33_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT33_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT33_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT33_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT33_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT33_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT33_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_PRE_PODF_MASK) +#define CCM_TARGET_ROOT33_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT33_MUX_SHIFT 24 +#define CCM_TARGET_ROOT33_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_MUX_SHIFT))&CCM_TARGET_ROOT33_MUX_MASK) +#define CCM_TARGET_ROOT33_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT33_ENABLE_SHIFT 28 +/* TARGET_ROOT33_SET Bit Fields */ +#define CCM_TARGET_ROOT33_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT33_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT33_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT33_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT33_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT33_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT33_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT33_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT33_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT33_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT33_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT33_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT33_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT33_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT33_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT33_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_SET_MUX_SHIFT))&CCM_TARGET_ROOT33_SET_MUX_MASK) +#define CCM_TARGET_ROOT33_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT33_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT33_CLR Bit Fields */ +#define CCM_TARGET_ROOT33_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT33_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT33_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT33_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT33_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT33_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT33_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT33_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT33_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT33_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT33_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT33_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT33_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_CLR_MUX_SHIFT))&CCM_TARGET_ROOT33_CLR_MUX_MASK) +#define CCM_TARGET_ROOT33_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT33_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT33_TOG Bit Fields */ +#define CCM_TARGET_ROOT33_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT33_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT33_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT33_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT33_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT33_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT33_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT33_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT33_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT33_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT33_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT33_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT33_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT33_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT33_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT33_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT33_TOG_MUX_SHIFT))&CCM_TARGET_ROOT33_TOG_MUX_MASK) +#define CCM_TARGET_ROOT33_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT33_TOG_ENABLE_SHIFT 28 +/* POST33 Bit Fields */ +#define CCM_POST33_POST_PODF_MASK 0x3Fu +#define CCM_POST33_POST_PODF_SHIFT 0 +#define CCM_POST33_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST33_POST_PODF_SHIFT))&CCM_POST33_POST_PODF_MASK) +#define CCM_POST33_BUSY1_MASK 0x80u +#define CCM_POST33_BUSY1_SHIFT 7 +#define CCM_POST33_AUTO_PODF_MASK 0x700u +#define CCM_POST33_AUTO_PODF_SHIFT 8 +#define CCM_POST33_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST33_AUTO_PODF_SHIFT))&CCM_POST33_AUTO_PODF_MASK) +#define CCM_POST33_AUTO_EN_MASK 0x1000u +#define CCM_POST33_AUTO_EN_SHIFT 12 +#define CCM_POST33_SLOW_MASK 0x8000u +#define CCM_POST33_SLOW_SHIFT 15 +#define CCM_POST33_SELECT_MASK 0x10000000u +#define CCM_POST33_SELECT_SHIFT 28 +#define CCM_POST33_BUSY2_MASK 0x80000000u +#define CCM_POST33_BUSY2_SHIFT 31 +/* POST_ROOT33_SET Bit Fields */ +#define CCM_POST_ROOT33_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT33_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT33_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_SET_POST_PODF_SHIFT))&CCM_POST_ROOT33_SET_POST_PODF_MASK) +#define CCM_POST_ROOT33_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT33_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT33_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT33_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT33_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT33_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT33_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT33_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT33_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT33_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT33_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT33_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT33_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT33_SET_BUSY2_SHIFT 31 +/* POST_ROOT33_CLR Bit Fields */ +#define CCM_POST_ROOT33_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT33_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT33_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT33_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT33_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT33_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT33_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT33_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT33_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT33_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT33_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT33_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT33_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT33_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT33_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT33_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT33_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT33_CLR_BUSY2_SHIFT 31 +/* POST_ROOT33_TOG Bit Fields */ +#define CCM_POST_ROOT33_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT33_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT33_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT33_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT33_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT33_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT33_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT33_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT33_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT33_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT33_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT33_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT33_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT33_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT33_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT33_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT33_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT33_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT33_TOG_BUSY2_SHIFT 31 +/* PRE33 Bit Fields */ +#define CCM_PRE33_PRE_PODF_B_MASK 0x7u +#define CCM_PRE33_PRE_PODF_B_SHIFT 0 +#define CCM_PRE33_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_PRE_PODF_B_SHIFT))&CCM_PRE33_PRE_PODF_B_MASK) +#define CCM_PRE33_BUSY0_MASK 0x8u +#define CCM_PRE33_BUSY0_SHIFT 3 +#define CCM_PRE33_MUX_B_MASK 0x700u +#define CCM_PRE33_MUX_B_SHIFT 8 +#define CCM_PRE33_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_MUX_B_SHIFT))&CCM_PRE33_MUX_B_MASK) +#define CCM_PRE33_EN_B_MASK 0x1000u +#define CCM_PRE33_EN_B_SHIFT 12 +#define CCM_PRE33_BUSY1_MASK 0x8000u +#define CCM_PRE33_BUSY1_SHIFT 15 +#define CCM_PRE33_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE33_PRE_PODF_A_SHIFT 16 +#define CCM_PRE33_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_PRE_PODF_A_SHIFT))&CCM_PRE33_PRE_PODF_A_MASK) +#define CCM_PRE33_BUSY3_MASK 0x80000u +#define CCM_PRE33_BUSY3_SHIFT 19 +#define CCM_PRE33_MUX_A_MASK 0x7000000u +#define CCM_PRE33_MUX_A_SHIFT 24 +#define CCM_PRE33_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE33_MUX_A_SHIFT))&CCM_PRE33_MUX_A_MASK) +#define CCM_PRE33_EN_A_MASK 0x10000000u +#define CCM_PRE33_EN_A_SHIFT 28 +#define CCM_PRE33_BUSY4_MASK 0x80000000u +#define CCM_PRE33_BUSY4_SHIFT 31 +/* PRE_ROOT33_SET Bit Fields */ +#define CCM_PRE_ROOT33_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT33_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT33_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT33_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT33_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT33_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT33_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT33_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT33_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_MUX_B_SHIFT))&CCM_PRE_ROOT33_SET_MUX_B_MASK) +#define CCM_PRE_ROOT33_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT33_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT33_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT33_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT33_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT33_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT33_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT33_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT33_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT33_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT33_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT33_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT33_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_SET_MUX_A_SHIFT))&CCM_PRE_ROOT33_SET_MUX_A_MASK) +#define CCM_PRE_ROOT33_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT33_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT33_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT33_SET_BUSY4_SHIFT 31 +/* PRE_ROOT33_CLR Bit Fields */ +#define CCM_PRE_ROOT33_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT33_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT33_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT33_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT33_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT33_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT33_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT33_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT33_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT33_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT33_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT33_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT33_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT33_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT33_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT33_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT33_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT33_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT33_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT33_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT33_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT33_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT33_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT33_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT33_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT33_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT33_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT33_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT33_TOG Bit Fields */ +#define CCM_PRE_ROOT33_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT33_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT33_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT33_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT33_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT33_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT33_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT33_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT33_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT33_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT33_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT33_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT33_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT33_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT33_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT33_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT33_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT33_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT33_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT33_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT33_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT33_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT33_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT33_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT33_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT33_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT33_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT33_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT33_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL33 Bit Fields */ +#define CCM_ACCESS_CTRL33_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL33_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL33_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL33_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL33_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL33_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL33_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL33_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL33_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL33_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL33_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL33_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL33_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL33_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL33_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL33_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL33_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL33_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL33_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL33_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL33_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL33_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL33_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL33_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL33_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL33_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL33_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL33_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL33_LOCK_SHIFT 31 +/* ACCESS_CTRL33_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL33_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL33_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL33_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL33_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL33_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL33_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL33_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL33_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL33_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL33_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL33_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL33_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL33_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL33_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL33_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL33_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL33_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL33_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT34 Bit Fields */ +#define CCM_TARGET_ROOT34_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT34_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT34_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_POST_PODF_MASK) +#define CCM_TARGET_ROOT34_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT34_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT34_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT34_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT34_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT34_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT34_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT34_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT34_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT34_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_PRE_PODF_MASK) +#define CCM_TARGET_ROOT34_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT34_MUX_SHIFT 24 +#define CCM_TARGET_ROOT34_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_MUX_SHIFT))&CCM_TARGET_ROOT34_MUX_MASK) +#define CCM_TARGET_ROOT34_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT34_ENABLE_SHIFT 28 +/* TARGET_ROOT34_SET Bit Fields */ +#define CCM_TARGET_ROOT34_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT34_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT34_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT34_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT34_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT34_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT34_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT34_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT34_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT34_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT34_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT34_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT34_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT34_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT34_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT34_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_SET_MUX_SHIFT))&CCM_TARGET_ROOT34_SET_MUX_MASK) +#define CCM_TARGET_ROOT34_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT34_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT34_CLR Bit Fields */ +#define CCM_TARGET_ROOT34_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT34_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT34_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT34_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT34_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT34_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT34_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT34_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT34_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT34_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT34_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT34_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT34_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_CLR_MUX_SHIFT))&CCM_TARGET_ROOT34_CLR_MUX_MASK) +#define CCM_TARGET_ROOT34_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT34_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT34_TOG Bit Fields */ +#define CCM_TARGET_ROOT34_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT34_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT34_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT34_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT34_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT34_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT34_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT34_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT34_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT34_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT34_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT34_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT34_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT34_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT34_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT34_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT34_TOG_MUX_SHIFT))&CCM_TARGET_ROOT34_TOG_MUX_MASK) +#define CCM_TARGET_ROOT34_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT34_TOG_ENABLE_SHIFT 28 +/* POST34 Bit Fields */ +#define CCM_POST34_POST_PODF_MASK 0x3Fu +#define CCM_POST34_POST_PODF_SHIFT 0 +#define CCM_POST34_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST34_POST_PODF_SHIFT))&CCM_POST34_POST_PODF_MASK) +#define CCM_POST34_BUSY1_MASK 0x80u +#define CCM_POST34_BUSY1_SHIFT 7 +#define CCM_POST34_AUTO_PODF_MASK 0x700u +#define CCM_POST34_AUTO_PODF_SHIFT 8 +#define CCM_POST34_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST34_AUTO_PODF_SHIFT))&CCM_POST34_AUTO_PODF_MASK) +#define CCM_POST34_AUTO_EN_MASK 0x1000u +#define CCM_POST34_AUTO_EN_SHIFT 12 +#define CCM_POST34_SLOW_MASK 0x8000u +#define CCM_POST34_SLOW_SHIFT 15 +#define CCM_POST34_SELECT_MASK 0x10000000u +#define CCM_POST34_SELECT_SHIFT 28 +#define CCM_POST34_BUSY2_MASK 0x80000000u +#define CCM_POST34_BUSY2_SHIFT 31 +/* POST_ROOT34_SET Bit Fields */ +#define CCM_POST_ROOT34_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT34_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT34_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_SET_POST_PODF_SHIFT))&CCM_POST_ROOT34_SET_POST_PODF_MASK) +#define CCM_POST_ROOT34_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT34_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT34_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT34_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT34_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT34_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT34_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT34_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT34_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT34_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT34_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT34_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT34_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT34_SET_BUSY2_SHIFT 31 +/* POST_ROOT34_CLR Bit Fields */ +#define CCM_POST_ROOT34_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT34_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT34_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT34_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT34_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT34_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT34_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT34_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT34_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT34_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT34_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT34_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT34_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT34_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT34_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT34_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT34_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT34_CLR_BUSY2_SHIFT 31 +/* POST_ROOT34_TOG Bit Fields */ +#define CCM_POST_ROOT34_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT34_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT34_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT34_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT34_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT34_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT34_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT34_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT34_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT34_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT34_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT34_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT34_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT34_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT34_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT34_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT34_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT34_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT34_TOG_BUSY2_SHIFT 31 +/* PRE34 Bit Fields */ +#define CCM_PRE34_PRE_PODF_B_MASK 0x7u +#define CCM_PRE34_PRE_PODF_B_SHIFT 0 +#define CCM_PRE34_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_PRE_PODF_B_SHIFT))&CCM_PRE34_PRE_PODF_B_MASK) +#define CCM_PRE34_BUSY0_MASK 0x8u +#define CCM_PRE34_BUSY0_SHIFT 3 +#define CCM_PRE34_MUX_B_MASK 0x700u +#define CCM_PRE34_MUX_B_SHIFT 8 +#define CCM_PRE34_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_MUX_B_SHIFT))&CCM_PRE34_MUX_B_MASK) +#define CCM_PRE34_EN_B_MASK 0x1000u +#define CCM_PRE34_EN_B_SHIFT 12 +#define CCM_PRE34_BUSY1_MASK 0x8000u +#define CCM_PRE34_BUSY1_SHIFT 15 +#define CCM_PRE34_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE34_PRE_PODF_A_SHIFT 16 +#define CCM_PRE34_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_PRE_PODF_A_SHIFT))&CCM_PRE34_PRE_PODF_A_MASK) +#define CCM_PRE34_BUSY3_MASK 0x80000u +#define CCM_PRE34_BUSY3_SHIFT 19 +#define CCM_PRE34_MUX_A_MASK 0x7000000u +#define CCM_PRE34_MUX_A_SHIFT 24 +#define CCM_PRE34_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE34_MUX_A_SHIFT))&CCM_PRE34_MUX_A_MASK) +#define CCM_PRE34_EN_A_MASK 0x10000000u +#define CCM_PRE34_EN_A_SHIFT 28 +#define CCM_PRE34_BUSY4_MASK 0x80000000u +#define CCM_PRE34_BUSY4_SHIFT 31 +/* PRE_ROOT34_SET Bit Fields */ +#define CCM_PRE_ROOT34_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT34_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT34_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT34_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT34_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT34_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT34_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT34_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT34_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_MUX_B_SHIFT))&CCM_PRE_ROOT34_SET_MUX_B_MASK) +#define CCM_PRE_ROOT34_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT34_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT34_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT34_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT34_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT34_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT34_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT34_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT34_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT34_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT34_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT34_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT34_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_SET_MUX_A_SHIFT))&CCM_PRE_ROOT34_SET_MUX_A_MASK) +#define CCM_PRE_ROOT34_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT34_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT34_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT34_SET_BUSY4_SHIFT 31 +/* PRE_ROOT34_CLR Bit Fields */ +#define CCM_PRE_ROOT34_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT34_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT34_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT34_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT34_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT34_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT34_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT34_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT34_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT34_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT34_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT34_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT34_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT34_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT34_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT34_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT34_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT34_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT34_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT34_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT34_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT34_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT34_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT34_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT34_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT34_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT34_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT34_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT34_TOG Bit Fields */ +#define CCM_PRE_ROOT34_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT34_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT34_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT34_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT34_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT34_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT34_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT34_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT34_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT34_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT34_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT34_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT34_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT34_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT34_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT34_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT34_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT34_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT34_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT34_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT34_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT34_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT34_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT34_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT34_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT34_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT34_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT34_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT34_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL34 Bit Fields */ +#define CCM_ACCESS_CTRL34_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL34_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL34_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL34_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL34_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL34_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL34_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL34_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL34_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL34_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL34_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL34_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL34_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL34_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL34_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL34_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL34_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL34_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL34_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL34_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL34_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL34_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL34_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL34_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL34_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL34_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL34_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL34_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL34_LOCK_SHIFT 31 +/* ACCESS_CTRL34_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL34_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL34_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL34_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL34_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL34_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL34_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL34_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL34_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL34_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL34_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL34_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL34_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL34_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL34_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL34_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL34_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL34_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL34_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT35 Bit Fields */ +#define CCM_TARGET_ROOT35_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT35_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT35_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_POST_PODF_MASK) +#define CCM_TARGET_ROOT35_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT35_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT35_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT35_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT35_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT35_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT35_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT35_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT35_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT35_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_PRE_PODF_MASK) +#define CCM_TARGET_ROOT35_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT35_MUX_SHIFT 24 +#define CCM_TARGET_ROOT35_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_MUX_SHIFT))&CCM_TARGET_ROOT35_MUX_MASK) +#define CCM_TARGET_ROOT35_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT35_ENABLE_SHIFT 28 +/* TARGET_ROOT35_SET Bit Fields */ +#define CCM_TARGET_ROOT35_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT35_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT35_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT35_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT35_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT35_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT35_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT35_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT35_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT35_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT35_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT35_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT35_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT35_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT35_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT35_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_SET_MUX_SHIFT))&CCM_TARGET_ROOT35_SET_MUX_MASK) +#define CCM_TARGET_ROOT35_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT35_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT35_CLR Bit Fields */ +#define CCM_TARGET_ROOT35_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT35_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT35_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT35_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT35_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT35_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT35_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT35_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT35_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT35_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT35_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT35_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT35_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_CLR_MUX_SHIFT))&CCM_TARGET_ROOT35_CLR_MUX_MASK) +#define CCM_TARGET_ROOT35_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT35_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT35_TOG Bit Fields */ +#define CCM_TARGET_ROOT35_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT35_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT35_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT35_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT35_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT35_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT35_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT35_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT35_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT35_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT35_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT35_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT35_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT35_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT35_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT35_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT35_TOG_MUX_SHIFT))&CCM_TARGET_ROOT35_TOG_MUX_MASK) +#define CCM_TARGET_ROOT35_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT35_TOG_ENABLE_SHIFT 28 +/* POST35 Bit Fields */ +#define CCM_POST35_POST_PODF_MASK 0x3Fu +#define CCM_POST35_POST_PODF_SHIFT 0 +#define CCM_POST35_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST35_POST_PODF_SHIFT))&CCM_POST35_POST_PODF_MASK) +#define CCM_POST35_BUSY1_MASK 0x80u +#define CCM_POST35_BUSY1_SHIFT 7 +#define CCM_POST35_AUTO_PODF_MASK 0x700u +#define CCM_POST35_AUTO_PODF_SHIFT 8 +#define CCM_POST35_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST35_AUTO_PODF_SHIFT))&CCM_POST35_AUTO_PODF_MASK) +#define CCM_POST35_AUTO_EN_MASK 0x1000u +#define CCM_POST35_AUTO_EN_SHIFT 12 +#define CCM_POST35_SLOW_MASK 0x8000u +#define CCM_POST35_SLOW_SHIFT 15 +#define CCM_POST35_SELECT_MASK 0x10000000u +#define CCM_POST35_SELECT_SHIFT 28 +#define CCM_POST35_BUSY2_MASK 0x80000000u +#define CCM_POST35_BUSY2_SHIFT 31 +/* POST_ROOT35_SET Bit Fields */ +#define CCM_POST_ROOT35_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT35_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT35_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_SET_POST_PODF_SHIFT))&CCM_POST_ROOT35_SET_POST_PODF_MASK) +#define CCM_POST_ROOT35_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT35_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT35_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT35_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT35_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT35_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT35_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT35_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT35_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT35_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT35_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT35_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT35_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT35_SET_BUSY2_SHIFT 31 +/* POST_ROOT35_CLR Bit Fields */ +#define CCM_POST_ROOT35_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT35_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT35_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT35_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT35_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT35_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT35_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT35_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT35_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT35_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT35_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT35_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT35_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT35_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT35_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT35_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT35_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT35_CLR_BUSY2_SHIFT 31 +/* POST_ROOT35_TOG Bit Fields */ +#define CCM_POST_ROOT35_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT35_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT35_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT35_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT35_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT35_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT35_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT35_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT35_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT35_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT35_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT35_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT35_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT35_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT35_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT35_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT35_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT35_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT35_TOG_BUSY2_SHIFT 31 +/* PRE35 Bit Fields */ +#define CCM_PRE35_PRE_PODF_B_MASK 0x7u +#define CCM_PRE35_PRE_PODF_B_SHIFT 0 +#define CCM_PRE35_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_PRE_PODF_B_SHIFT))&CCM_PRE35_PRE_PODF_B_MASK) +#define CCM_PRE35_BUSY0_MASK 0x8u +#define CCM_PRE35_BUSY0_SHIFT 3 +#define CCM_PRE35_MUX_B_MASK 0x700u +#define CCM_PRE35_MUX_B_SHIFT 8 +#define CCM_PRE35_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_MUX_B_SHIFT))&CCM_PRE35_MUX_B_MASK) +#define CCM_PRE35_EN_B_MASK 0x1000u +#define CCM_PRE35_EN_B_SHIFT 12 +#define CCM_PRE35_BUSY1_MASK 0x8000u +#define CCM_PRE35_BUSY1_SHIFT 15 +#define CCM_PRE35_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE35_PRE_PODF_A_SHIFT 16 +#define CCM_PRE35_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_PRE_PODF_A_SHIFT))&CCM_PRE35_PRE_PODF_A_MASK) +#define CCM_PRE35_BUSY3_MASK 0x80000u +#define CCM_PRE35_BUSY3_SHIFT 19 +#define CCM_PRE35_MUX_A_MASK 0x7000000u +#define CCM_PRE35_MUX_A_SHIFT 24 +#define CCM_PRE35_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE35_MUX_A_SHIFT))&CCM_PRE35_MUX_A_MASK) +#define CCM_PRE35_EN_A_MASK 0x10000000u +#define CCM_PRE35_EN_A_SHIFT 28 +#define CCM_PRE35_BUSY4_MASK 0x80000000u +#define CCM_PRE35_BUSY4_SHIFT 31 +/* PRE_ROOT35_SET Bit Fields */ +#define CCM_PRE_ROOT35_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT35_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT35_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT35_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT35_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT35_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT35_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT35_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT35_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_MUX_B_SHIFT))&CCM_PRE_ROOT35_SET_MUX_B_MASK) +#define CCM_PRE_ROOT35_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT35_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT35_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT35_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT35_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT35_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT35_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT35_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT35_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT35_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT35_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT35_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT35_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_SET_MUX_A_SHIFT))&CCM_PRE_ROOT35_SET_MUX_A_MASK) +#define CCM_PRE_ROOT35_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT35_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT35_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT35_SET_BUSY4_SHIFT 31 +/* PRE_ROOT35_CLR Bit Fields */ +#define CCM_PRE_ROOT35_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT35_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT35_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT35_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT35_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT35_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT35_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT35_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT35_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT35_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT35_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT35_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT35_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT35_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT35_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT35_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT35_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT35_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT35_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT35_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT35_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT35_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT35_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT35_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT35_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT35_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT35_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT35_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT35_TOG Bit Fields */ +#define CCM_PRE_ROOT35_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT35_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT35_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT35_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT35_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT35_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT35_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT35_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT35_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT35_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT35_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT35_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT35_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT35_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT35_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT35_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT35_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT35_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT35_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT35_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT35_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT35_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT35_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT35_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT35_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT35_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT35_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT35_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT35_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL35 Bit Fields */ +#define CCM_ACCESS_CTRL35_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL35_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL35_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL35_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL35_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL35_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL35_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL35_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL35_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL35_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL35_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL35_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL35_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL35_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL35_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL35_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL35_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL35_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL35_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL35_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL35_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL35_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL35_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL35_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL35_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL35_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL35_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL35_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL35_LOCK_SHIFT 31 +/* ACCESS_CTRL35_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL35_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL35_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL35_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL35_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL35_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL35_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL35_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL35_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL35_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL35_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL35_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL35_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL35_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL35_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL35_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL35_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL35_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL35_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT36 Bit Fields */ +#define CCM_TARGET_ROOT36_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT36_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT36_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_POST_PODF_MASK) +#define CCM_TARGET_ROOT36_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT36_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT36_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT36_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT36_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT36_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT36_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT36_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT36_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT36_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_PRE_PODF_MASK) +#define CCM_TARGET_ROOT36_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT36_MUX_SHIFT 24 +#define CCM_TARGET_ROOT36_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_MUX_SHIFT))&CCM_TARGET_ROOT36_MUX_MASK) +#define CCM_TARGET_ROOT36_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT36_ENABLE_SHIFT 28 +/* TARGET_ROOT36_SET Bit Fields */ +#define CCM_TARGET_ROOT36_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT36_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT36_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT36_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT36_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT36_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT36_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT36_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT36_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT36_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT36_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT36_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT36_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT36_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT36_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT36_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_SET_MUX_SHIFT))&CCM_TARGET_ROOT36_SET_MUX_MASK) +#define CCM_TARGET_ROOT36_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT36_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT36_CLR Bit Fields */ +#define CCM_TARGET_ROOT36_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT36_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT36_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT36_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT36_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT36_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT36_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT36_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT36_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT36_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT36_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT36_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT36_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_CLR_MUX_SHIFT))&CCM_TARGET_ROOT36_CLR_MUX_MASK) +#define CCM_TARGET_ROOT36_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT36_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT36_TOG Bit Fields */ +#define CCM_TARGET_ROOT36_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT36_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT36_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT36_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT36_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT36_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT36_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT36_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT36_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT36_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT36_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT36_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT36_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT36_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT36_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT36_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT36_TOG_MUX_SHIFT))&CCM_TARGET_ROOT36_TOG_MUX_MASK) +#define CCM_TARGET_ROOT36_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT36_TOG_ENABLE_SHIFT 28 +/* POST36 Bit Fields */ +#define CCM_POST36_POST_PODF_MASK 0x3Fu +#define CCM_POST36_POST_PODF_SHIFT 0 +#define CCM_POST36_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST36_POST_PODF_SHIFT))&CCM_POST36_POST_PODF_MASK) +#define CCM_POST36_BUSY1_MASK 0x80u +#define CCM_POST36_BUSY1_SHIFT 7 +#define CCM_POST36_AUTO_PODF_MASK 0x700u +#define CCM_POST36_AUTO_PODF_SHIFT 8 +#define CCM_POST36_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST36_AUTO_PODF_SHIFT))&CCM_POST36_AUTO_PODF_MASK) +#define CCM_POST36_AUTO_EN_MASK 0x1000u +#define CCM_POST36_AUTO_EN_SHIFT 12 +#define CCM_POST36_SLOW_MASK 0x8000u +#define CCM_POST36_SLOW_SHIFT 15 +#define CCM_POST36_SELECT_MASK 0x10000000u +#define CCM_POST36_SELECT_SHIFT 28 +#define CCM_POST36_BUSY2_MASK 0x80000000u +#define CCM_POST36_BUSY2_SHIFT 31 +/* POST_ROOT36_SET Bit Fields */ +#define CCM_POST_ROOT36_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT36_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT36_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_SET_POST_PODF_SHIFT))&CCM_POST_ROOT36_SET_POST_PODF_MASK) +#define CCM_POST_ROOT36_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT36_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT36_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT36_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT36_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT36_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT36_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT36_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT36_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT36_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT36_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT36_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT36_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT36_SET_BUSY2_SHIFT 31 +/* POST_ROOT36_CLR Bit Fields */ +#define CCM_POST_ROOT36_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT36_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT36_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT36_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT36_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT36_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT36_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT36_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT36_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT36_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT36_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT36_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT36_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT36_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT36_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT36_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT36_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT36_CLR_BUSY2_SHIFT 31 +/* POST_ROOT36_TOG Bit Fields */ +#define CCM_POST_ROOT36_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT36_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT36_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT36_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT36_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT36_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT36_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT36_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT36_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT36_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT36_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT36_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT36_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT36_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT36_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT36_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT36_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT36_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT36_TOG_BUSY2_SHIFT 31 +/* PRE36 Bit Fields */ +#define CCM_PRE36_PRE_PODF_B_MASK 0x7u +#define CCM_PRE36_PRE_PODF_B_SHIFT 0 +#define CCM_PRE36_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_PRE_PODF_B_SHIFT))&CCM_PRE36_PRE_PODF_B_MASK) +#define CCM_PRE36_BUSY0_MASK 0x8u +#define CCM_PRE36_BUSY0_SHIFT 3 +#define CCM_PRE36_MUX_B_MASK 0x700u +#define CCM_PRE36_MUX_B_SHIFT 8 +#define CCM_PRE36_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_MUX_B_SHIFT))&CCM_PRE36_MUX_B_MASK) +#define CCM_PRE36_EN_B_MASK 0x1000u +#define CCM_PRE36_EN_B_SHIFT 12 +#define CCM_PRE36_BUSY1_MASK 0x8000u +#define CCM_PRE36_BUSY1_SHIFT 15 +#define CCM_PRE36_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE36_PRE_PODF_A_SHIFT 16 +#define CCM_PRE36_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_PRE_PODF_A_SHIFT))&CCM_PRE36_PRE_PODF_A_MASK) +#define CCM_PRE36_BUSY3_MASK 0x80000u +#define CCM_PRE36_BUSY3_SHIFT 19 +#define CCM_PRE36_MUX_A_MASK 0x7000000u +#define CCM_PRE36_MUX_A_SHIFT 24 +#define CCM_PRE36_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE36_MUX_A_SHIFT))&CCM_PRE36_MUX_A_MASK) +#define CCM_PRE36_EN_A_MASK 0x10000000u +#define CCM_PRE36_EN_A_SHIFT 28 +#define CCM_PRE36_BUSY4_MASK 0x80000000u +#define CCM_PRE36_BUSY4_SHIFT 31 +/* PRE_ROOT36_SET Bit Fields */ +#define CCM_PRE_ROOT36_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT36_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT36_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT36_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT36_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT36_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT36_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT36_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT36_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_MUX_B_SHIFT))&CCM_PRE_ROOT36_SET_MUX_B_MASK) +#define CCM_PRE_ROOT36_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT36_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT36_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT36_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT36_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT36_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT36_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT36_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT36_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT36_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT36_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT36_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT36_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_SET_MUX_A_SHIFT))&CCM_PRE_ROOT36_SET_MUX_A_MASK) +#define CCM_PRE_ROOT36_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT36_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT36_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT36_SET_BUSY4_SHIFT 31 +/* PRE_ROOT36_CLR Bit Fields */ +#define CCM_PRE_ROOT36_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT36_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT36_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT36_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT36_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT36_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT36_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT36_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT36_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT36_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT36_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT36_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT36_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT36_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT36_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT36_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT36_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT36_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT36_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT36_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT36_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT36_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT36_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT36_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT36_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT36_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT36_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT36_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT36_TOG Bit Fields */ +#define CCM_PRE_ROOT36_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT36_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT36_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT36_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT36_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT36_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT36_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT36_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT36_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT36_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT36_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT36_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT36_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT36_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT36_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT36_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT36_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT36_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT36_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT36_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT36_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT36_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT36_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT36_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT36_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT36_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT36_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT36_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT36_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL36 Bit Fields */ +#define CCM_ACCESS_CTRL36_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL36_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL36_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL36_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL36_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL36_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL36_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL36_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL36_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL36_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL36_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL36_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL36_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL36_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL36_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL36_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL36_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL36_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL36_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL36_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL36_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL36_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL36_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL36_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL36_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL36_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL36_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL36_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL36_LOCK_SHIFT 31 +/* ACCESS_CTRL36_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL36_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL36_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL36_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL36_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL36_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL36_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL36_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL36_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL36_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL36_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL36_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL36_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL36_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL36_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL36_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL36_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL36_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL36_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT37 Bit Fields */ +#define CCM_TARGET_ROOT37_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT37_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT37_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_POST_PODF_MASK) +#define CCM_TARGET_ROOT37_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT37_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT37_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT37_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT37_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT37_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT37_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT37_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT37_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT37_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_PRE_PODF_MASK) +#define CCM_TARGET_ROOT37_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT37_MUX_SHIFT 24 +#define CCM_TARGET_ROOT37_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_MUX_SHIFT))&CCM_TARGET_ROOT37_MUX_MASK) +#define CCM_TARGET_ROOT37_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT37_ENABLE_SHIFT 28 +/* TARGET_ROOT37_SET Bit Fields */ +#define CCM_TARGET_ROOT37_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT37_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT37_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT37_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT37_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT37_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT37_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT37_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT37_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT37_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT37_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT37_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT37_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT37_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT37_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT37_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_SET_MUX_SHIFT))&CCM_TARGET_ROOT37_SET_MUX_MASK) +#define CCM_TARGET_ROOT37_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT37_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT37_CLR Bit Fields */ +#define CCM_TARGET_ROOT37_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT37_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT37_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT37_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT37_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT37_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT37_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT37_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT37_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT37_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT37_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT37_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT37_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_CLR_MUX_SHIFT))&CCM_TARGET_ROOT37_CLR_MUX_MASK) +#define CCM_TARGET_ROOT37_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT37_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT37_TOG Bit Fields */ +#define CCM_TARGET_ROOT37_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT37_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT37_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT37_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT37_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT37_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT37_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT37_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT37_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT37_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT37_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT37_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT37_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT37_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT37_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT37_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT37_TOG_MUX_SHIFT))&CCM_TARGET_ROOT37_TOG_MUX_MASK) +#define CCM_TARGET_ROOT37_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT37_TOG_ENABLE_SHIFT 28 +/* POST37 Bit Fields */ +#define CCM_POST37_POST_PODF_MASK 0x3Fu +#define CCM_POST37_POST_PODF_SHIFT 0 +#define CCM_POST37_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST37_POST_PODF_SHIFT))&CCM_POST37_POST_PODF_MASK) +#define CCM_POST37_BUSY1_MASK 0x80u +#define CCM_POST37_BUSY1_SHIFT 7 +#define CCM_POST37_AUTO_PODF_MASK 0x700u +#define CCM_POST37_AUTO_PODF_SHIFT 8 +#define CCM_POST37_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST37_AUTO_PODF_SHIFT))&CCM_POST37_AUTO_PODF_MASK) +#define CCM_POST37_AUTO_EN_MASK 0x1000u +#define CCM_POST37_AUTO_EN_SHIFT 12 +#define CCM_POST37_SLOW_MASK 0x8000u +#define CCM_POST37_SLOW_SHIFT 15 +#define CCM_POST37_SELECT_MASK 0x10000000u +#define CCM_POST37_SELECT_SHIFT 28 +#define CCM_POST37_BUSY2_MASK 0x80000000u +#define CCM_POST37_BUSY2_SHIFT 31 +/* POST_ROOT37_SET Bit Fields */ +#define CCM_POST_ROOT37_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT37_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT37_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_SET_POST_PODF_SHIFT))&CCM_POST_ROOT37_SET_POST_PODF_MASK) +#define CCM_POST_ROOT37_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT37_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT37_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT37_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT37_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT37_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT37_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT37_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT37_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT37_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT37_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT37_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT37_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT37_SET_BUSY2_SHIFT 31 +/* POST_ROOT37_CLR Bit Fields */ +#define CCM_POST_ROOT37_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT37_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT37_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT37_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT37_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT37_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT37_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT37_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT37_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT37_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT37_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT37_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT37_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT37_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT37_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT37_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT37_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT37_CLR_BUSY2_SHIFT 31 +/* POST_ROOT37_TOG Bit Fields */ +#define CCM_POST_ROOT37_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT37_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT37_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT37_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT37_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT37_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT37_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT37_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT37_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT37_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT37_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT37_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT37_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT37_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT37_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT37_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT37_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT37_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT37_TOG_BUSY2_SHIFT 31 +/* PRE37 Bit Fields */ +#define CCM_PRE37_PRE_PODF_B_MASK 0x7u +#define CCM_PRE37_PRE_PODF_B_SHIFT 0 +#define CCM_PRE37_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_PRE_PODF_B_SHIFT))&CCM_PRE37_PRE_PODF_B_MASK) +#define CCM_PRE37_BUSY0_MASK 0x8u +#define CCM_PRE37_BUSY0_SHIFT 3 +#define CCM_PRE37_MUX_B_MASK 0x700u +#define CCM_PRE37_MUX_B_SHIFT 8 +#define CCM_PRE37_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_MUX_B_SHIFT))&CCM_PRE37_MUX_B_MASK) +#define CCM_PRE37_EN_B_MASK 0x1000u +#define CCM_PRE37_EN_B_SHIFT 12 +#define CCM_PRE37_BUSY1_MASK 0x8000u +#define CCM_PRE37_BUSY1_SHIFT 15 +#define CCM_PRE37_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE37_PRE_PODF_A_SHIFT 16 +#define CCM_PRE37_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_PRE_PODF_A_SHIFT))&CCM_PRE37_PRE_PODF_A_MASK) +#define CCM_PRE37_BUSY3_MASK 0x80000u +#define CCM_PRE37_BUSY3_SHIFT 19 +#define CCM_PRE37_MUX_A_MASK 0x7000000u +#define CCM_PRE37_MUX_A_SHIFT 24 +#define CCM_PRE37_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE37_MUX_A_SHIFT))&CCM_PRE37_MUX_A_MASK) +#define CCM_PRE37_EN_A_MASK 0x10000000u +#define CCM_PRE37_EN_A_SHIFT 28 +#define CCM_PRE37_BUSY4_MASK 0x80000000u +#define CCM_PRE37_BUSY4_SHIFT 31 +/* PRE_ROOT37_SET Bit Fields */ +#define CCM_PRE_ROOT37_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT37_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT37_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT37_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT37_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT37_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT37_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT37_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT37_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_MUX_B_SHIFT))&CCM_PRE_ROOT37_SET_MUX_B_MASK) +#define CCM_PRE_ROOT37_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT37_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT37_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT37_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT37_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT37_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT37_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT37_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT37_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT37_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT37_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT37_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT37_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_SET_MUX_A_SHIFT))&CCM_PRE_ROOT37_SET_MUX_A_MASK) +#define CCM_PRE_ROOT37_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT37_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT37_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT37_SET_BUSY4_SHIFT 31 +/* PRE_ROOT37_CLR Bit Fields */ +#define CCM_PRE_ROOT37_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT37_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT37_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT37_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT37_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT37_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT37_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT37_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT37_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT37_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT37_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT37_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT37_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT37_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT37_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT37_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT37_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT37_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT37_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT37_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT37_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT37_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT37_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT37_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT37_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT37_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT37_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT37_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT37_TOG Bit Fields */ +#define CCM_PRE_ROOT37_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT37_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT37_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT37_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT37_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT37_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT37_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT37_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT37_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT37_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT37_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT37_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT37_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT37_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT37_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT37_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT37_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT37_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT37_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT37_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT37_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT37_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT37_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT37_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT37_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT37_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT37_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT37_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT37_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL37 Bit Fields */ +#define CCM_ACCESS_CTRL37_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL37_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL37_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL37_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL37_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL37_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL37_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL37_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL37_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL37_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL37_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL37_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL37_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL37_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL37_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL37_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL37_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL37_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL37_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL37_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL37_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL37_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL37_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL37_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL37_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL37_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL37_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL37_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL37_LOCK_SHIFT 31 +/* ACCESS_CTRL37_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL37_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL37_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL37_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL37_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL37_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL37_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL37_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL37_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL37_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL37_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL37_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL37_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL37_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL37_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL37_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL37_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL37_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL37_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT38 Bit Fields */ +#define CCM_TARGET_ROOT38_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT38_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT38_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_POST_PODF_MASK) +#define CCM_TARGET_ROOT38_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT38_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT38_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT38_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT38_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT38_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT38_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT38_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT38_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT38_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_PRE_PODF_MASK) +#define CCM_TARGET_ROOT38_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT38_MUX_SHIFT 24 +#define CCM_TARGET_ROOT38_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_MUX_SHIFT))&CCM_TARGET_ROOT38_MUX_MASK) +#define CCM_TARGET_ROOT38_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT38_ENABLE_SHIFT 28 +/* TARGET_ROOT38_SET Bit Fields */ +#define CCM_TARGET_ROOT38_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT38_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT38_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT38_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT38_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT38_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT38_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT38_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT38_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT38_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT38_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT38_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT38_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT38_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT38_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT38_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_SET_MUX_SHIFT))&CCM_TARGET_ROOT38_SET_MUX_MASK) +#define CCM_TARGET_ROOT38_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT38_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT38_CLR Bit Fields */ +#define CCM_TARGET_ROOT38_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT38_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT38_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT38_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT38_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT38_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT38_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT38_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT38_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT38_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT38_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT38_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT38_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_CLR_MUX_SHIFT))&CCM_TARGET_ROOT38_CLR_MUX_MASK) +#define CCM_TARGET_ROOT38_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT38_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT38_TOG Bit Fields */ +#define CCM_TARGET_ROOT38_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT38_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT38_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT38_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT38_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT38_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT38_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT38_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT38_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT38_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT38_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT38_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT38_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT38_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT38_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT38_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT38_TOG_MUX_SHIFT))&CCM_TARGET_ROOT38_TOG_MUX_MASK) +#define CCM_TARGET_ROOT38_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT38_TOG_ENABLE_SHIFT 28 +/* POST38 Bit Fields */ +#define CCM_POST38_POST_PODF_MASK 0x3Fu +#define CCM_POST38_POST_PODF_SHIFT 0 +#define CCM_POST38_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST38_POST_PODF_SHIFT))&CCM_POST38_POST_PODF_MASK) +#define CCM_POST38_BUSY1_MASK 0x80u +#define CCM_POST38_BUSY1_SHIFT 7 +#define CCM_POST38_AUTO_PODF_MASK 0x700u +#define CCM_POST38_AUTO_PODF_SHIFT 8 +#define CCM_POST38_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST38_AUTO_PODF_SHIFT))&CCM_POST38_AUTO_PODF_MASK) +#define CCM_POST38_AUTO_EN_MASK 0x1000u +#define CCM_POST38_AUTO_EN_SHIFT 12 +#define CCM_POST38_SLOW_MASK 0x8000u +#define CCM_POST38_SLOW_SHIFT 15 +#define CCM_POST38_SELECT_MASK 0x10000000u +#define CCM_POST38_SELECT_SHIFT 28 +#define CCM_POST38_BUSY2_MASK 0x80000000u +#define CCM_POST38_BUSY2_SHIFT 31 +/* POST_ROOT38_SET Bit Fields */ +#define CCM_POST_ROOT38_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT38_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT38_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_SET_POST_PODF_SHIFT))&CCM_POST_ROOT38_SET_POST_PODF_MASK) +#define CCM_POST_ROOT38_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT38_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT38_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT38_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT38_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT38_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT38_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT38_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT38_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT38_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT38_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT38_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT38_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT38_SET_BUSY2_SHIFT 31 +/* POST_ROOT38_CLR Bit Fields */ +#define CCM_POST_ROOT38_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT38_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT38_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT38_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT38_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT38_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT38_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT38_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT38_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT38_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT38_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT38_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT38_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT38_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT38_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT38_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT38_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT38_CLR_BUSY2_SHIFT 31 +/* POST_ROOT38_TOG Bit Fields */ +#define CCM_POST_ROOT38_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT38_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT38_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT38_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT38_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT38_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT38_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT38_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT38_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT38_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT38_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT38_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT38_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT38_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT38_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT38_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT38_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT38_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT38_TOG_BUSY2_SHIFT 31 +/* PRE38 Bit Fields */ +#define CCM_PRE38_PRE_PODF_B_MASK 0x7u +#define CCM_PRE38_PRE_PODF_B_SHIFT 0 +#define CCM_PRE38_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_PRE_PODF_B_SHIFT))&CCM_PRE38_PRE_PODF_B_MASK) +#define CCM_PRE38_BUSY0_MASK 0x8u +#define CCM_PRE38_BUSY0_SHIFT 3 +#define CCM_PRE38_MUX_B_MASK 0x700u +#define CCM_PRE38_MUX_B_SHIFT 8 +#define CCM_PRE38_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_MUX_B_SHIFT))&CCM_PRE38_MUX_B_MASK) +#define CCM_PRE38_EN_B_MASK 0x1000u +#define CCM_PRE38_EN_B_SHIFT 12 +#define CCM_PRE38_BUSY1_MASK 0x8000u +#define CCM_PRE38_BUSY1_SHIFT 15 +#define CCM_PRE38_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE38_PRE_PODF_A_SHIFT 16 +#define CCM_PRE38_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_PRE_PODF_A_SHIFT))&CCM_PRE38_PRE_PODF_A_MASK) +#define CCM_PRE38_BUSY3_MASK 0x80000u +#define CCM_PRE38_BUSY3_SHIFT 19 +#define CCM_PRE38_MUX_A_MASK 0x7000000u +#define CCM_PRE38_MUX_A_SHIFT 24 +#define CCM_PRE38_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE38_MUX_A_SHIFT))&CCM_PRE38_MUX_A_MASK) +#define CCM_PRE38_EN_A_MASK 0x10000000u +#define CCM_PRE38_EN_A_SHIFT 28 +#define CCM_PRE38_BUSY4_MASK 0x80000000u +#define CCM_PRE38_BUSY4_SHIFT 31 +/* PRE_ROOT38_SET Bit Fields */ +#define CCM_PRE_ROOT38_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT38_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT38_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT38_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT38_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT38_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT38_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT38_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT38_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_MUX_B_SHIFT))&CCM_PRE_ROOT38_SET_MUX_B_MASK) +#define CCM_PRE_ROOT38_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT38_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT38_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT38_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT38_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT38_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT38_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT38_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT38_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT38_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT38_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT38_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT38_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_SET_MUX_A_SHIFT))&CCM_PRE_ROOT38_SET_MUX_A_MASK) +#define CCM_PRE_ROOT38_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT38_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT38_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT38_SET_BUSY4_SHIFT 31 +/* PRE_ROOT38_CLR Bit Fields */ +#define CCM_PRE_ROOT38_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT38_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT38_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT38_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT38_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT38_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT38_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT38_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT38_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT38_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT38_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT38_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT38_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT38_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT38_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT38_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT38_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT38_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT38_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT38_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT38_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT38_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT38_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT38_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT38_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT38_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT38_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT38_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT38_TOG Bit Fields */ +#define CCM_PRE_ROOT38_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT38_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT38_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT38_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT38_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT38_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT38_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT38_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT38_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT38_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT38_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT38_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT38_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT38_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT38_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT38_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT38_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT38_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT38_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT38_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT38_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT38_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT38_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT38_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT38_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT38_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT38_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT38_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT38_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL38 Bit Fields */ +#define CCM_ACCESS_CTRL38_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL38_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL38_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL38_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL38_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL38_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL38_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL38_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL38_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL38_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL38_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL38_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL38_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL38_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL38_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL38_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL38_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL38_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL38_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL38_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL38_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL38_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL38_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL38_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL38_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL38_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL38_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL38_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL38_LOCK_SHIFT 31 +/* ACCESS_CTRL38_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL38_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL38_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL38_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL38_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL38_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL38_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL38_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL38_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL38_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL38_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL38_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL38_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL38_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL38_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL38_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL38_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL38_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL38_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT39 Bit Fields */ +#define CCM_TARGET_ROOT39_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT39_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT39_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_POST_PODF_MASK) +#define CCM_TARGET_ROOT39_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT39_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT39_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT39_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT39_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT39_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT39_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT39_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT39_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT39_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_PRE_PODF_MASK) +#define CCM_TARGET_ROOT39_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT39_MUX_SHIFT 24 +#define CCM_TARGET_ROOT39_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_MUX_SHIFT))&CCM_TARGET_ROOT39_MUX_MASK) +#define CCM_TARGET_ROOT39_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT39_ENABLE_SHIFT 28 +/* TARGET_ROOT39_SET Bit Fields */ +#define CCM_TARGET_ROOT39_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT39_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT39_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT39_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT39_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT39_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT39_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT39_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT39_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT39_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT39_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT39_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT39_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT39_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT39_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT39_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_SET_MUX_SHIFT))&CCM_TARGET_ROOT39_SET_MUX_MASK) +#define CCM_TARGET_ROOT39_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT39_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT39_CLR Bit Fields */ +#define CCM_TARGET_ROOT39_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT39_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT39_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT39_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT39_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT39_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT39_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT39_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT39_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT39_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT39_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT39_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT39_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_CLR_MUX_SHIFT))&CCM_TARGET_ROOT39_CLR_MUX_MASK) +#define CCM_TARGET_ROOT39_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT39_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT39_TOG Bit Fields */ +#define CCM_TARGET_ROOT39_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT39_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT39_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT39_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT39_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT39_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT39_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT39_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT39_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT39_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT39_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT39_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT39_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT39_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT39_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT39_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT39_TOG_MUX_SHIFT))&CCM_TARGET_ROOT39_TOG_MUX_MASK) +#define CCM_TARGET_ROOT39_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT39_TOG_ENABLE_SHIFT 28 +/* POST39 Bit Fields */ +#define CCM_POST39_POST_PODF_MASK 0x3Fu +#define CCM_POST39_POST_PODF_SHIFT 0 +#define CCM_POST39_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST39_POST_PODF_SHIFT))&CCM_POST39_POST_PODF_MASK) +#define CCM_POST39_BUSY1_MASK 0x80u +#define CCM_POST39_BUSY1_SHIFT 7 +#define CCM_POST39_AUTO_PODF_MASK 0x700u +#define CCM_POST39_AUTO_PODF_SHIFT 8 +#define CCM_POST39_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST39_AUTO_PODF_SHIFT))&CCM_POST39_AUTO_PODF_MASK) +#define CCM_POST39_AUTO_EN_MASK 0x1000u +#define CCM_POST39_AUTO_EN_SHIFT 12 +#define CCM_POST39_SLOW_MASK 0x8000u +#define CCM_POST39_SLOW_SHIFT 15 +#define CCM_POST39_SELECT_MASK 0x10000000u +#define CCM_POST39_SELECT_SHIFT 28 +#define CCM_POST39_BUSY2_MASK 0x80000000u +#define CCM_POST39_BUSY2_SHIFT 31 +/* POST_ROOT39_SET Bit Fields */ +#define CCM_POST_ROOT39_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT39_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT39_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_SET_POST_PODF_SHIFT))&CCM_POST_ROOT39_SET_POST_PODF_MASK) +#define CCM_POST_ROOT39_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT39_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT39_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT39_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT39_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT39_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT39_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT39_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT39_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT39_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT39_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT39_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT39_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT39_SET_BUSY2_SHIFT 31 +/* POST_ROOT39_CLR Bit Fields */ +#define CCM_POST_ROOT39_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT39_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT39_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT39_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT39_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT39_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT39_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT39_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT39_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT39_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT39_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT39_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT39_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT39_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT39_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT39_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT39_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT39_CLR_BUSY2_SHIFT 31 +/* POST_ROOT39_TOG Bit Fields */ +#define CCM_POST_ROOT39_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT39_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT39_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT39_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT39_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT39_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT39_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT39_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT39_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT39_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT39_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT39_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT39_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT39_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT39_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT39_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT39_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT39_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT39_TOG_BUSY2_SHIFT 31 +/* PRE39 Bit Fields */ +#define CCM_PRE39_PRE_PODF_B_MASK 0x7u +#define CCM_PRE39_PRE_PODF_B_SHIFT 0 +#define CCM_PRE39_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_PRE_PODF_B_SHIFT))&CCM_PRE39_PRE_PODF_B_MASK) +#define CCM_PRE39_BUSY0_MASK 0x8u +#define CCM_PRE39_BUSY0_SHIFT 3 +#define CCM_PRE39_MUX_B_MASK 0x700u +#define CCM_PRE39_MUX_B_SHIFT 8 +#define CCM_PRE39_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_MUX_B_SHIFT))&CCM_PRE39_MUX_B_MASK) +#define CCM_PRE39_EN_B_MASK 0x1000u +#define CCM_PRE39_EN_B_SHIFT 12 +#define CCM_PRE39_BUSY1_MASK 0x8000u +#define CCM_PRE39_BUSY1_SHIFT 15 +#define CCM_PRE39_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE39_PRE_PODF_A_SHIFT 16 +#define CCM_PRE39_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_PRE_PODF_A_SHIFT))&CCM_PRE39_PRE_PODF_A_MASK) +#define CCM_PRE39_BUSY3_MASK 0x80000u +#define CCM_PRE39_BUSY3_SHIFT 19 +#define CCM_PRE39_MUX_A_MASK 0x7000000u +#define CCM_PRE39_MUX_A_SHIFT 24 +#define CCM_PRE39_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE39_MUX_A_SHIFT))&CCM_PRE39_MUX_A_MASK) +#define CCM_PRE39_EN_A_MASK 0x10000000u +#define CCM_PRE39_EN_A_SHIFT 28 +#define CCM_PRE39_BUSY4_MASK 0x80000000u +#define CCM_PRE39_BUSY4_SHIFT 31 +/* PRE_ROOT39_SET Bit Fields */ +#define CCM_PRE_ROOT39_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT39_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT39_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT39_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT39_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT39_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT39_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT39_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT39_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_MUX_B_SHIFT))&CCM_PRE_ROOT39_SET_MUX_B_MASK) +#define CCM_PRE_ROOT39_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT39_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT39_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT39_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT39_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT39_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT39_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT39_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT39_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT39_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT39_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT39_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT39_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_SET_MUX_A_SHIFT))&CCM_PRE_ROOT39_SET_MUX_A_MASK) +#define CCM_PRE_ROOT39_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT39_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT39_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT39_SET_BUSY4_SHIFT 31 +/* PRE_ROOT39_CLR Bit Fields */ +#define CCM_PRE_ROOT39_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT39_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT39_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT39_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT39_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT39_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT39_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT39_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT39_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT39_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT39_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT39_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT39_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT39_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT39_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT39_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT39_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT39_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT39_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT39_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT39_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT39_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT39_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT39_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT39_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT39_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT39_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT39_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT39_TOG Bit Fields */ +#define CCM_PRE_ROOT39_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT39_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT39_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT39_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT39_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT39_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT39_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT39_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT39_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT39_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT39_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT39_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT39_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT39_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT39_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT39_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT39_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT39_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT39_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT39_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT39_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT39_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT39_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT39_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT39_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT39_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT39_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT39_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT39_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL39 Bit Fields */ +#define CCM_ACCESS_CTRL39_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL39_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL39_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL39_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL39_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL39_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL39_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL39_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL39_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL39_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL39_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL39_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL39_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL39_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL39_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL39_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL39_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL39_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL39_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL39_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL39_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL39_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL39_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL39_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL39_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL39_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL39_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL39_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL39_LOCK_SHIFT 31 +/* ACCESS_CTRL39_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL39_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL39_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL39_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL39_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL39_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL39_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL39_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL39_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL39_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL39_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL39_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL39_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL39_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL39_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL39_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL39_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL39_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL39_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT40 Bit Fields */ +#define CCM_TARGET_ROOT40_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT40_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT40_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_POST_PODF_MASK) +#define CCM_TARGET_ROOT40_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT40_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT40_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT40_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT40_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT40_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT40_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT40_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT40_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT40_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_PRE_PODF_MASK) +#define CCM_TARGET_ROOT40_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT40_MUX_SHIFT 24 +#define CCM_TARGET_ROOT40_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_MUX_SHIFT))&CCM_TARGET_ROOT40_MUX_MASK) +#define CCM_TARGET_ROOT40_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT40_ENABLE_SHIFT 28 +/* TARGET_ROOT40_SET Bit Fields */ +#define CCM_TARGET_ROOT40_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT40_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT40_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT40_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT40_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT40_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT40_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT40_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT40_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT40_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT40_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT40_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT40_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT40_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT40_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT40_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_SET_MUX_SHIFT))&CCM_TARGET_ROOT40_SET_MUX_MASK) +#define CCM_TARGET_ROOT40_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT40_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT40_CLR Bit Fields */ +#define CCM_TARGET_ROOT40_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT40_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT40_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT40_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT40_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT40_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT40_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT40_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT40_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT40_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT40_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT40_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT40_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_CLR_MUX_SHIFT))&CCM_TARGET_ROOT40_CLR_MUX_MASK) +#define CCM_TARGET_ROOT40_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT40_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT40_TOG Bit Fields */ +#define CCM_TARGET_ROOT40_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT40_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT40_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT40_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT40_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT40_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT40_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT40_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT40_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT40_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT40_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT40_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT40_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT40_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT40_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT40_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT40_TOG_MUX_SHIFT))&CCM_TARGET_ROOT40_TOG_MUX_MASK) +#define CCM_TARGET_ROOT40_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT40_TOG_ENABLE_SHIFT 28 +/* POST40 Bit Fields */ +#define CCM_POST40_POST_PODF_MASK 0x3Fu +#define CCM_POST40_POST_PODF_SHIFT 0 +#define CCM_POST40_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST40_POST_PODF_SHIFT))&CCM_POST40_POST_PODF_MASK) +#define CCM_POST40_BUSY1_MASK 0x80u +#define CCM_POST40_BUSY1_SHIFT 7 +#define CCM_POST40_AUTO_PODF_MASK 0x700u +#define CCM_POST40_AUTO_PODF_SHIFT 8 +#define CCM_POST40_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST40_AUTO_PODF_SHIFT))&CCM_POST40_AUTO_PODF_MASK) +#define CCM_POST40_AUTO_EN_MASK 0x1000u +#define CCM_POST40_AUTO_EN_SHIFT 12 +#define CCM_POST40_SLOW_MASK 0x8000u +#define CCM_POST40_SLOW_SHIFT 15 +#define CCM_POST40_SELECT_MASK 0x10000000u +#define CCM_POST40_SELECT_SHIFT 28 +#define CCM_POST40_BUSY2_MASK 0x80000000u +#define CCM_POST40_BUSY2_SHIFT 31 +/* POST_ROOT40_SET Bit Fields */ +#define CCM_POST_ROOT40_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT40_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT40_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_SET_POST_PODF_SHIFT))&CCM_POST_ROOT40_SET_POST_PODF_MASK) +#define CCM_POST_ROOT40_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT40_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT40_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT40_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT40_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT40_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT40_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT40_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT40_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT40_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT40_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT40_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT40_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT40_SET_BUSY2_SHIFT 31 +/* POST_ROOT40_CLR Bit Fields */ +#define CCM_POST_ROOT40_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT40_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT40_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT40_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT40_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT40_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT40_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT40_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT40_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT40_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT40_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT40_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT40_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT40_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT40_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT40_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT40_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT40_CLR_BUSY2_SHIFT 31 +/* POST_ROOT40_TOG Bit Fields */ +#define CCM_POST_ROOT40_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT40_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT40_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT40_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT40_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT40_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT40_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT40_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT40_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT40_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT40_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT40_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT40_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT40_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT40_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT40_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT40_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT40_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT40_TOG_BUSY2_SHIFT 31 +/* PRE40 Bit Fields */ +#define CCM_PRE40_PRE_PODF_B_MASK 0x7u +#define CCM_PRE40_PRE_PODF_B_SHIFT 0 +#define CCM_PRE40_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_PRE_PODF_B_SHIFT))&CCM_PRE40_PRE_PODF_B_MASK) +#define CCM_PRE40_BUSY0_MASK 0x8u +#define CCM_PRE40_BUSY0_SHIFT 3 +#define CCM_PRE40_MUX_B_MASK 0x700u +#define CCM_PRE40_MUX_B_SHIFT 8 +#define CCM_PRE40_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_MUX_B_SHIFT))&CCM_PRE40_MUX_B_MASK) +#define CCM_PRE40_EN_B_MASK 0x1000u +#define CCM_PRE40_EN_B_SHIFT 12 +#define CCM_PRE40_BUSY1_MASK 0x8000u +#define CCM_PRE40_BUSY1_SHIFT 15 +#define CCM_PRE40_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE40_PRE_PODF_A_SHIFT 16 +#define CCM_PRE40_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_PRE_PODF_A_SHIFT))&CCM_PRE40_PRE_PODF_A_MASK) +#define CCM_PRE40_BUSY3_MASK 0x80000u +#define CCM_PRE40_BUSY3_SHIFT 19 +#define CCM_PRE40_MUX_A_MASK 0x7000000u +#define CCM_PRE40_MUX_A_SHIFT 24 +#define CCM_PRE40_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE40_MUX_A_SHIFT))&CCM_PRE40_MUX_A_MASK) +#define CCM_PRE40_EN_A_MASK 0x10000000u +#define CCM_PRE40_EN_A_SHIFT 28 +#define CCM_PRE40_BUSY4_MASK 0x80000000u +#define CCM_PRE40_BUSY4_SHIFT 31 +/* PRE_ROOT40_SET Bit Fields */ +#define CCM_PRE_ROOT40_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT40_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT40_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT40_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT40_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT40_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT40_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT40_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT40_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_MUX_B_SHIFT))&CCM_PRE_ROOT40_SET_MUX_B_MASK) +#define CCM_PRE_ROOT40_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT40_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT40_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT40_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT40_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT40_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT40_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT40_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT40_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT40_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT40_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT40_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT40_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_SET_MUX_A_SHIFT))&CCM_PRE_ROOT40_SET_MUX_A_MASK) +#define CCM_PRE_ROOT40_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT40_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT40_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT40_SET_BUSY4_SHIFT 31 +/* PRE_ROOT40_CLR Bit Fields */ +#define CCM_PRE_ROOT40_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT40_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT40_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT40_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT40_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT40_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT40_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT40_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT40_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT40_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT40_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT40_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT40_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT40_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT40_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT40_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT40_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT40_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT40_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT40_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT40_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT40_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT40_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT40_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT40_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT40_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT40_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT40_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT40_TOG Bit Fields */ +#define CCM_PRE_ROOT40_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT40_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT40_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT40_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT40_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT40_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT40_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT40_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT40_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT40_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT40_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT40_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT40_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT40_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT40_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT40_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT40_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT40_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT40_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT40_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT40_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT40_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT40_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT40_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT40_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT40_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT40_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT40_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT40_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL40 Bit Fields */ +#define CCM_ACCESS_CTRL40_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL40_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL40_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL40_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL40_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL40_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL40_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL40_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL40_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL40_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL40_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL40_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL40_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL40_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL40_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL40_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL40_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL40_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL40_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL40_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL40_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL40_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL40_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL40_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL40_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL40_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL40_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL40_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL40_LOCK_SHIFT 31 +/* ACCESS_CTRL40_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL40_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL40_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL40_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL40_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL40_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL40_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL40_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL40_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL40_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL40_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL40_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL40_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL40_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL40_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL40_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL40_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL40_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL40_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT41 Bit Fields */ +#define CCM_TARGET_ROOT41_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT41_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT41_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_POST_PODF_MASK) +#define CCM_TARGET_ROOT41_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT41_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT41_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT41_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT41_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT41_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT41_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT41_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT41_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT41_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_PRE_PODF_MASK) +#define CCM_TARGET_ROOT41_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT41_MUX_SHIFT 24 +#define CCM_TARGET_ROOT41_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_MUX_SHIFT))&CCM_TARGET_ROOT41_MUX_MASK) +#define CCM_TARGET_ROOT41_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT41_ENABLE_SHIFT 28 +/* TARGET_ROOT41_SET Bit Fields */ +#define CCM_TARGET_ROOT41_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT41_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT41_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT41_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT41_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT41_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT41_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT41_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT41_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT41_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT41_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT41_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT41_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT41_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT41_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT41_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_SET_MUX_SHIFT))&CCM_TARGET_ROOT41_SET_MUX_MASK) +#define CCM_TARGET_ROOT41_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT41_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT41_CLR Bit Fields */ +#define CCM_TARGET_ROOT41_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT41_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT41_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT41_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT41_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT41_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT41_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT41_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT41_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT41_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT41_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT41_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT41_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_CLR_MUX_SHIFT))&CCM_TARGET_ROOT41_CLR_MUX_MASK) +#define CCM_TARGET_ROOT41_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT41_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT41_TOG Bit Fields */ +#define CCM_TARGET_ROOT41_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT41_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT41_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT41_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT41_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT41_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT41_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT41_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT41_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT41_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT41_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT41_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT41_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT41_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT41_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT41_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT41_TOG_MUX_SHIFT))&CCM_TARGET_ROOT41_TOG_MUX_MASK) +#define CCM_TARGET_ROOT41_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT41_TOG_ENABLE_SHIFT 28 +/* POST41 Bit Fields */ +#define CCM_POST41_POST_PODF_MASK 0x3Fu +#define CCM_POST41_POST_PODF_SHIFT 0 +#define CCM_POST41_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST41_POST_PODF_SHIFT))&CCM_POST41_POST_PODF_MASK) +#define CCM_POST41_BUSY1_MASK 0x80u +#define CCM_POST41_BUSY1_SHIFT 7 +#define CCM_POST41_AUTO_PODF_MASK 0x700u +#define CCM_POST41_AUTO_PODF_SHIFT 8 +#define CCM_POST41_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST41_AUTO_PODF_SHIFT))&CCM_POST41_AUTO_PODF_MASK) +#define CCM_POST41_AUTO_EN_MASK 0x1000u +#define CCM_POST41_AUTO_EN_SHIFT 12 +#define CCM_POST41_SLOW_MASK 0x8000u +#define CCM_POST41_SLOW_SHIFT 15 +#define CCM_POST41_SELECT_MASK 0x10000000u +#define CCM_POST41_SELECT_SHIFT 28 +#define CCM_POST41_BUSY2_MASK 0x80000000u +#define CCM_POST41_BUSY2_SHIFT 31 +/* POST_ROOT41_SET Bit Fields */ +#define CCM_POST_ROOT41_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT41_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT41_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_SET_POST_PODF_SHIFT))&CCM_POST_ROOT41_SET_POST_PODF_MASK) +#define CCM_POST_ROOT41_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT41_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT41_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT41_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT41_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT41_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT41_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT41_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT41_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT41_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT41_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT41_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT41_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT41_SET_BUSY2_SHIFT 31 +/* POST_ROOT41_CLR Bit Fields */ +#define CCM_POST_ROOT41_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT41_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT41_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT41_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT41_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT41_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT41_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT41_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT41_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT41_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT41_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT41_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT41_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT41_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT41_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT41_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT41_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT41_CLR_BUSY2_SHIFT 31 +/* POST_ROOT41_TOG Bit Fields */ +#define CCM_POST_ROOT41_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT41_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT41_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT41_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT41_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT41_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT41_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT41_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT41_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT41_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT41_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT41_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT41_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT41_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT41_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT41_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT41_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT41_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT41_TOG_BUSY2_SHIFT 31 +/* PRE41 Bit Fields */ +#define CCM_PRE41_PRE_PODF_B_MASK 0x7u +#define CCM_PRE41_PRE_PODF_B_SHIFT 0 +#define CCM_PRE41_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_PRE_PODF_B_SHIFT))&CCM_PRE41_PRE_PODF_B_MASK) +#define CCM_PRE41_BUSY0_MASK 0x8u +#define CCM_PRE41_BUSY0_SHIFT 3 +#define CCM_PRE41_MUX_B_MASK 0x700u +#define CCM_PRE41_MUX_B_SHIFT 8 +#define CCM_PRE41_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_MUX_B_SHIFT))&CCM_PRE41_MUX_B_MASK) +#define CCM_PRE41_EN_B_MASK 0x1000u +#define CCM_PRE41_EN_B_SHIFT 12 +#define CCM_PRE41_BUSY1_MASK 0x8000u +#define CCM_PRE41_BUSY1_SHIFT 15 +#define CCM_PRE41_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE41_PRE_PODF_A_SHIFT 16 +#define CCM_PRE41_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_PRE_PODF_A_SHIFT))&CCM_PRE41_PRE_PODF_A_MASK) +#define CCM_PRE41_BUSY3_MASK 0x80000u +#define CCM_PRE41_BUSY3_SHIFT 19 +#define CCM_PRE41_MUX_A_MASK 0x7000000u +#define CCM_PRE41_MUX_A_SHIFT 24 +#define CCM_PRE41_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE41_MUX_A_SHIFT))&CCM_PRE41_MUX_A_MASK) +#define CCM_PRE41_EN_A_MASK 0x10000000u +#define CCM_PRE41_EN_A_SHIFT 28 +#define CCM_PRE41_BUSY4_MASK 0x80000000u +#define CCM_PRE41_BUSY4_SHIFT 31 +/* PRE_ROOT41_SET Bit Fields */ +#define CCM_PRE_ROOT41_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT41_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT41_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT41_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT41_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT41_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT41_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT41_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT41_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_MUX_B_SHIFT))&CCM_PRE_ROOT41_SET_MUX_B_MASK) +#define CCM_PRE_ROOT41_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT41_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT41_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT41_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT41_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT41_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT41_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT41_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT41_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT41_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT41_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT41_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT41_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_SET_MUX_A_SHIFT))&CCM_PRE_ROOT41_SET_MUX_A_MASK) +#define CCM_PRE_ROOT41_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT41_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT41_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT41_SET_BUSY4_SHIFT 31 +/* PRE_ROOT41_CLR Bit Fields */ +#define CCM_PRE_ROOT41_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT41_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT41_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT41_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT41_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT41_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT41_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT41_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT41_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT41_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT41_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT41_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT41_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT41_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT41_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT41_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT41_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT41_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT41_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT41_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT41_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT41_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT41_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT41_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT41_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT41_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT41_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT41_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT41_TOG Bit Fields */ +#define CCM_PRE_ROOT41_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT41_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT41_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT41_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT41_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT41_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT41_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT41_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT41_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT41_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT41_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT41_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT41_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT41_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT41_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT41_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT41_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT41_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT41_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT41_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT41_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT41_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT41_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT41_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT41_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT41_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT41_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT41_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT41_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL41 Bit Fields */ +#define CCM_ACCESS_CTRL41_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL41_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL41_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL41_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL41_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL41_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL41_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL41_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL41_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL41_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL41_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL41_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL41_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL41_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL41_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL41_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL41_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL41_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL41_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL41_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL41_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL41_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL41_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL41_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL41_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL41_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL41_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL41_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL41_LOCK_SHIFT 31 +/* ACCESS_CTRL41_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL41_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL41_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL41_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL41_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL41_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL41_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL41_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL41_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL41_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL41_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL41_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL41_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL41_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL41_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL41_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL41_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL41_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL41_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT42 Bit Fields */ +#define CCM_TARGET_ROOT42_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT42_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT42_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_POST_PODF_MASK) +#define CCM_TARGET_ROOT42_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT42_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT42_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT42_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT42_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT42_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT42_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT42_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT42_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT42_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_PRE_PODF_MASK) +#define CCM_TARGET_ROOT42_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT42_MUX_SHIFT 24 +#define CCM_TARGET_ROOT42_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_MUX_SHIFT))&CCM_TARGET_ROOT42_MUX_MASK) +#define CCM_TARGET_ROOT42_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT42_ENABLE_SHIFT 28 +/* TARGET_ROOT42_SET Bit Fields */ +#define CCM_TARGET_ROOT42_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT42_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT42_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT42_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT42_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT42_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT42_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT42_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT42_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT42_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT42_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT42_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT42_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT42_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT42_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT42_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_SET_MUX_SHIFT))&CCM_TARGET_ROOT42_SET_MUX_MASK) +#define CCM_TARGET_ROOT42_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT42_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT42_CLR Bit Fields */ +#define CCM_TARGET_ROOT42_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT42_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT42_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT42_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT42_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT42_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT42_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT42_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT42_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT42_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT42_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT42_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT42_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_CLR_MUX_SHIFT))&CCM_TARGET_ROOT42_CLR_MUX_MASK) +#define CCM_TARGET_ROOT42_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT42_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT42_TOG Bit Fields */ +#define CCM_TARGET_ROOT42_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT42_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT42_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT42_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT42_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT42_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT42_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT42_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT42_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT42_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT42_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT42_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT42_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT42_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT42_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT42_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT42_TOG_MUX_SHIFT))&CCM_TARGET_ROOT42_TOG_MUX_MASK) +#define CCM_TARGET_ROOT42_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT42_TOG_ENABLE_SHIFT 28 +/* POST42 Bit Fields */ +#define CCM_POST42_POST_PODF_MASK 0x3Fu +#define CCM_POST42_POST_PODF_SHIFT 0 +#define CCM_POST42_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST42_POST_PODF_SHIFT))&CCM_POST42_POST_PODF_MASK) +#define CCM_POST42_BUSY1_MASK 0x80u +#define CCM_POST42_BUSY1_SHIFT 7 +#define CCM_POST42_AUTO_PODF_MASK 0x700u +#define CCM_POST42_AUTO_PODF_SHIFT 8 +#define CCM_POST42_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST42_AUTO_PODF_SHIFT))&CCM_POST42_AUTO_PODF_MASK) +#define CCM_POST42_AUTO_EN_MASK 0x1000u +#define CCM_POST42_AUTO_EN_SHIFT 12 +#define CCM_POST42_SLOW_MASK 0x8000u +#define CCM_POST42_SLOW_SHIFT 15 +#define CCM_POST42_SELECT_MASK 0x10000000u +#define CCM_POST42_SELECT_SHIFT 28 +#define CCM_POST42_BUSY2_MASK 0x80000000u +#define CCM_POST42_BUSY2_SHIFT 31 +/* POST_ROOT42_SET Bit Fields */ +#define CCM_POST_ROOT42_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT42_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT42_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_SET_POST_PODF_SHIFT))&CCM_POST_ROOT42_SET_POST_PODF_MASK) +#define CCM_POST_ROOT42_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT42_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT42_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT42_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT42_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT42_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT42_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT42_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT42_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT42_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT42_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT42_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT42_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT42_SET_BUSY2_SHIFT 31 +/* POST_ROOT42_CLR Bit Fields */ +#define CCM_POST_ROOT42_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT42_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT42_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT42_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT42_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT42_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT42_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT42_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT42_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT42_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT42_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT42_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT42_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT42_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT42_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT42_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT42_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT42_CLR_BUSY2_SHIFT 31 +/* POST_ROOT42_TOG Bit Fields */ +#define CCM_POST_ROOT42_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT42_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT42_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT42_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT42_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT42_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT42_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT42_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT42_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT42_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT42_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT42_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT42_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT42_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT42_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT42_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT42_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT42_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT42_TOG_BUSY2_SHIFT 31 +/* PRE42 Bit Fields */ +#define CCM_PRE42_PRE_PODF_B_MASK 0x7u +#define CCM_PRE42_PRE_PODF_B_SHIFT 0 +#define CCM_PRE42_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_PRE_PODF_B_SHIFT))&CCM_PRE42_PRE_PODF_B_MASK) +#define CCM_PRE42_BUSY0_MASK 0x8u +#define CCM_PRE42_BUSY0_SHIFT 3 +#define CCM_PRE42_MUX_B_MASK 0x700u +#define CCM_PRE42_MUX_B_SHIFT 8 +#define CCM_PRE42_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_MUX_B_SHIFT))&CCM_PRE42_MUX_B_MASK) +#define CCM_PRE42_EN_B_MASK 0x1000u +#define CCM_PRE42_EN_B_SHIFT 12 +#define CCM_PRE42_BUSY1_MASK 0x8000u +#define CCM_PRE42_BUSY1_SHIFT 15 +#define CCM_PRE42_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE42_PRE_PODF_A_SHIFT 16 +#define CCM_PRE42_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_PRE_PODF_A_SHIFT))&CCM_PRE42_PRE_PODF_A_MASK) +#define CCM_PRE42_BUSY3_MASK 0x80000u +#define CCM_PRE42_BUSY3_SHIFT 19 +#define CCM_PRE42_MUX_A_MASK 0x7000000u +#define CCM_PRE42_MUX_A_SHIFT 24 +#define CCM_PRE42_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE42_MUX_A_SHIFT))&CCM_PRE42_MUX_A_MASK) +#define CCM_PRE42_EN_A_MASK 0x10000000u +#define CCM_PRE42_EN_A_SHIFT 28 +#define CCM_PRE42_BUSY4_MASK 0x80000000u +#define CCM_PRE42_BUSY4_SHIFT 31 +/* PRE_ROOT42_SET Bit Fields */ +#define CCM_PRE_ROOT42_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT42_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT42_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT42_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT42_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT42_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT42_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT42_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT42_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_MUX_B_SHIFT))&CCM_PRE_ROOT42_SET_MUX_B_MASK) +#define CCM_PRE_ROOT42_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT42_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT42_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT42_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT42_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT42_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT42_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT42_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT42_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT42_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT42_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT42_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT42_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_SET_MUX_A_SHIFT))&CCM_PRE_ROOT42_SET_MUX_A_MASK) +#define CCM_PRE_ROOT42_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT42_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT42_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT42_SET_BUSY4_SHIFT 31 +/* PRE_ROOT42_CLR Bit Fields */ +#define CCM_PRE_ROOT42_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT42_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT42_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT42_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT42_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT42_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT42_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT42_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT42_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT42_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT42_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT42_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT42_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT42_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT42_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT42_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT42_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT42_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT42_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT42_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT42_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT42_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT42_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT42_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT42_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT42_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT42_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT42_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT42_TOG Bit Fields */ +#define CCM_PRE_ROOT42_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT42_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT42_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT42_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT42_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT42_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT42_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT42_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT42_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT42_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT42_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT42_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT42_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT42_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT42_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT42_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT42_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT42_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT42_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT42_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT42_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT42_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT42_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT42_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT42_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT42_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT42_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT42_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT42_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL42 Bit Fields */ +#define CCM_ACCESS_CTRL42_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL42_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL42_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL42_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL42_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL42_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL42_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL42_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL42_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL42_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL42_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL42_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL42_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL42_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL42_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL42_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL42_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL42_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL42_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL42_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL42_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL42_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL42_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL42_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL42_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL42_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL42_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL42_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL42_LOCK_SHIFT 31 +/* ACCESS_CTRL42_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL42_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL42_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL42_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL42_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL42_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL42_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL42_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL42_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL42_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL42_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL42_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL42_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL42_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL42_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL42_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL42_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL42_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL42_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT43 Bit Fields */ +#define CCM_TARGET_ROOT43_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT43_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT43_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_POST_PODF_MASK) +#define CCM_TARGET_ROOT43_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT43_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT43_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT43_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT43_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT43_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT43_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT43_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT43_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT43_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_PRE_PODF_MASK) +#define CCM_TARGET_ROOT43_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT43_MUX_SHIFT 24 +#define CCM_TARGET_ROOT43_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_MUX_SHIFT))&CCM_TARGET_ROOT43_MUX_MASK) +#define CCM_TARGET_ROOT43_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT43_ENABLE_SHIFT 28 +/* TARGET_ROOT43_SET Bit Fields */ +#define CCM_TARGET_ROOT43_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT43_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT43_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT43_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT43_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT43_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT43_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT43_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT43_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT43_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT43_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT43_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT43_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT43_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT43_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT43_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_SET_MUX_SHIFT))&CCM_TARGET_ROOT43_SET_MUX_MASK) +#define CCM_TARGET_ROOT43_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT43_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT43_CLR Bit Fields */ +#define CCM_TARGET_ROOT43_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT43_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT43_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT43_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT43_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT43_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT43_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT43_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT43_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT43_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT43_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT43_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT43_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_CLR_MUX_SHIFT))&CCM_TARGET_ROOT43_CLR_MUX_MASK) +#define CCM_TARGET_ROOT43_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT43_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT43_TOG Bit Fields */ +#define CCM_TARGET_ROOT43_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT43_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT43_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT43_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT43_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT43_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT43_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT43_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT43_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT43_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT43_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT43_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT43_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT43_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT43_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT43_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT43_TOG_MUX_SHIFT))&CCM_TARGET_ROOT43_TOG_MUX_MASK) +#define CCM_TARGET_ROOT43_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT43_TOG_ENABLE_SHIFT 28 +/* POST43 Bit Fields */ +#define CCM_POST43_POST_PODF_MASK 0x3Fu +#define CCM_POST43_POST_PODF_SHIFT 0 +#define CCM_POST43_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST43_POST_PODF_SHIFT))&CCM_POST43_POST_PODF_MASK) +#define CCM_POST43_BUSY1_MASK 0x80u +#define CCM_POST43_BUSY1_SHIFT 7 +#define CCM_POST43_AUTO_PODF_MASK 0x700u +#define CCM_POST43_AUTO_PODF_SHIFT 8 +#define CCM_POST43_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST43_AUTO_PODF_SHIFT))&CCM_POST43_AUTO_PODF_MASK) +#define CCM_POST43_AUTO_EN_MASK 0x1000u +#define CCM_POST43_AUTO_EN_SHIFT 12 +#define CCM_POST43_SLOW_MASK 0x8000u +#define CCM_POST43_SLOW_SHIFT 15 +#define CCM_POST43_SELECT_MASK 0x10000000u +#define CCM_POST43_SELECT_SHIFT 28 +#define CCM_POST43_BUSY2_MASK 0x80000000u +#define CCM_POST43_BUSY2_SHIFT 31 +/* POST_ROOT43_SET Bit Fields */ +#define CCM_POST_ROOT43_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT43_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT43_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_SET_POST_PODF_SHIFT))&CCM_POST_ROOT43_SET_POST_PODF_MASK) +#define CCM_POST_ROOT43_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT43_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT43_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT43_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT43_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT43_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT43_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT43_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT43_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT43_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT43_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT43_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT43_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT43_SET_BUSY2_SHIFT 31 +/* POST_ROOT43_CLR Bit Fields */ +#define CCM_POST_ROOT43_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT43_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT43_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT43_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT43_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT43_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT43_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT43_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT43_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT43_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT43_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT43_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT43_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT43_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT43_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT43_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT43_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT43_CLR_BUSY2_SHIFT 31 +/* POST_ROOT43_TOG Bit Fields */ +#define CCM_POST_ROOT43_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT43_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT43_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT43_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT43_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT43_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT43_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT43_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT43_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT43_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT43_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT43_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT43_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT43_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT43_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT43_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT43_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT43_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT43_TOG_BUSY2_SHIFT 31 +/* PRE43 Bit Fields */ +#define CCM_PRE43_PRE_PODF_B_MASK 0x7u +#define CCM_PRE43_PRE_PODF_B_SHIFT 0 +#define CCM_PRE43_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_PRE_PODF_B_SHIFT))&CCM_PRE43_PRE_PODF_B_MASK) +#define CCM_PRE43_BUSY0_MASK 0x8u +#define CCM_PRE43_BUSY0_SHIFT 3 +#define CCM_PRE43_MUX_B_MASK 0x700u +#define CCM_PRE43_MUX_B_SHIFT 8 +#define CCM_PRE43_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_MUX_B_SHIFT))&CCM_PRE43_MUX_B_MASK) +#define CCM_PRE43_EN_B_MASK 0x1000u +#define CCM_PRE43_EN_B_SHIFT 12 +#define CCM_PRE43_BUSY1_MASK 0x8000u +#define CCM_PRE43_BUSY1_SHIFT 15 +#define CCM_PRE43_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE43_PRE_PODF_A_SHIFT 16 +#define CCM_PRE43_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_PRE_PODF_A_SHIFT))&CCM_PRE43_PRE_PODF_A_MASK) +#define CCM_PRE43_BUSY3_MASK 0x80000u +#define CCM_PRE43_BUSY3_SHIFT 19 +#define CCM_PRE43_MUX_A_MASK 0x7000000u +#define CCM_PRE43_MUX_A_SHIFT 24 +#define CCM_PRE43_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE43_MUX_A_SHIFT))&CCM_PRE43_MUX_A_MASK) +#define CCM_PRE43_EN_A_MASK 0x10000000u +#define CCM_PRE43_EN_A_SHIFT 28 +#define CCM_PRE43_BUSY4_MASK 0x80000000u +#define CCM_PRE43_BUSY4_SHIFT 31 +/* PRE_ROOT43_SET Bit Fields */ +#define CCM_PRE_ROOT43_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT43_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT43_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT43_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT43_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT43_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT43_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT43_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT43_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_MUX_B_SHIFT))&CCM_PRE_ROOT43_SET_MUX_B_MASK) +#define CCM_PRE_ROOT43_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT43_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT43_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT43_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT43_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT43_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT43_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT43_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT43_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT43_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT43_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT43_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT43_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_SET_MUX_A_SHIFT))&CCM_PRE_ROOT43_SET_MUX_A_MASK) +#define CCM_PRE_ROOT43_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT43_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT43_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT43_SET_BUSY4_SHIFT 31 +/* PRE_ROOT43_CLR Bit Fields */ +#define CCM_PRE_ROOT43_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT43_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT43_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT43_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT43_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT43_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT43_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT43_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT43_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT43_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT43_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT43_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT43_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT43_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT43_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT43_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT43_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT43_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT43_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT43_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT43_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT43_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT43_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT43_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT43_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT43_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT43_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT43_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT43_TOG Bit Fields */ +#define CCM_PRE_ROOT43_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT43_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT43_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT43_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT43_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT43_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT43_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT43_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT43_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT43_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT43_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT43_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT43_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT43_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT43_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT43_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT43_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT43_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT43_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT43_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT43_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT43_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT43_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT43_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT43_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT43_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT43_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT43_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT43_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL43 Bit Fields */ +#define CCM_ACCESS_CTRL43_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL43_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL43_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL43_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL43_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL43_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL43_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL43_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL43_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL43_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL43_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL43_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL43_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL43_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL43_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL43_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL43_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL43_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL43_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL43_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL43_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL43_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL43_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL43_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL43_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL43_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL43_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL43_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL43_LOCK_SHIFT 31 +/* ACCESS_CTRL43_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL43_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL43_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL43_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL43_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL43_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL43_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL43_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL43_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL43_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL43_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL43_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL43_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL43_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL43_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL43_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL43_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL43_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL43_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT44 Bit Fields */ +#define CCM_TARGET_ROOT44_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT44_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT44_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_POST_PODF_MASK) +#define CCM_TARGET_ROOT44_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT44_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT44_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT44_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT44_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT44_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT44_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT44_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT44_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT44_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_PRE_PODF_MASK) +#define CCM_TARGET_ROOT44_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT44_MUX_SHIFT 24 +#define CCM_TARGET_ROOT44_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_MUX_SHIFT))&CCM_TARGET_ROOT44_MUX_MASK) +#define CCM_TARGET_ROOT44_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT44_ENABLE_SHIFT 28 +/* TARGET_ROOT44_SET Bit Fields */ +#define CCM_TARGET_ROOT44_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT44_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT44_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT44_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT44_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT44_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT44_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT44_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT44_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT44_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT44_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT44_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT44_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT44_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT44_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT44_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_SET_MUX_SHIFT))&CCM_TARGET_ROOT44_SET_MUX_MASK) +#define CCM_TARGET_ROOT44_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT44_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT44_CLR Bit Fields */ +#define CCM_TARGET_ROOT44_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT44_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT44_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT44_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT44_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT44_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT44_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT44_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT44_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT44_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT44_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT44_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT44_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_CLR_MUX_SHIFT))&CCM_TARGET_ROOT44_CLR_MUX_MASK) +#define CCM_TARGET_ROOT44_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT44_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT44_TOG Bit Fields */ +#define CCM_TARGET_ROOT44_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT44_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT44_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT44_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT44_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT44_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT44_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT44_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT44_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT44_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT44_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT44_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT44_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT44_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT44_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT44_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT44_TOG_MUX_SHIFT))&CCM_TARGET_ROOT44_TOG_MUX_MASK) +#define CCM_TARGET_ROOT44_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT44_TOG_ENABLE_SHIFT 28 +/* POST44 Bit Fields */ +#define CCM_POST44_POST_PODF_MASK 0x3Fu +#define CCM_POST44_POST_PODF_SHIFT 0 +#define CCM_POST44_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST44_POST_PODF_SHIFT))&CCM_POST44_POST_PODF_MASK) +#define CCM_POST44_BUSY1_MASK 0x80u +#define CCM_POST44_BUSY1_SHIFT 7 +#define CCM_POST44_AUTO_PODF_MASK 0x700u +#define CCM_POST44_AUTO_PODF_SHIFT 8 +#define CCM_POST44_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST44_AUTO_PODF_SHIFT))&CCM_POST44_AUTO_PODF_MASK) +#define CCM_POST44_AUTO_EN_MASK 0x1000u +#define CCM_POST44_AUTO_EN_SHIFT 12 +#define CCM_POST44_SLOW_MASK 0x8000u +#define CCM_POST44_SLOW_SHIFT 15 +#define CCM_POST44_SELECT_MASK 0x10000000u +#define CCM_POST44_SELECT_SHIFT 28 +#define CCM_POST44_BUSY2_MASK 0x80000000u +#define CCM_POST44_BUSY2_SHIFT 31 +/* POST_ROOT44_SET Bit Fields */ +#define CCM_POST_ROOT44_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT44_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT44_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_SET_POST_PODF_SHIFT))&CCM_POST_ROOT44_SET_POST_PODF_MASK) +#define CCM_POST_ROOT44_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT44_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT44_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT44_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT44_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT44_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT44_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT44_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT44_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT44_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT44_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT44_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT44_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT44_SET_BUSY2_SHIFT 31 +/* POST_ROOT44_CLR Bit Fields */ +#define CCM_POST_ROOT44_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT44_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT44_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT44_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT44_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT44_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT44_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT44_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT44_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT44_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT44_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT44_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT44_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT44_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT44_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT44_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT44_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT44_CLR_BUSY2_SHIFT 31 +/* POST_ROOT44_TOG Bit Fields */ +#define CCM_POST_ROOT44_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT44_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT44_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT44_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT44_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT44_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT44_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT44_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT44_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT44_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT44_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT44_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT44_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT44_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT44_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT44_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT44_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT44_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT44_TOG_BUSY2_SHIFT 31 +/* PRE44 Bit Fields */ +#define CCM_PRE44_PRE_PODF_B_MASK 0x7u +#define CCM_PRE44_PRE_PODF_B_SHIFT 0 +#define CCM_PRE44_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_PRE_PODF_B_SHIFT))&CCM_PRE44_PRE_PODF_B_MASK) +#define CCM_PRE44_BUSY0_MASK 0x8u +#define CCM_PRE44_BUSY0_SHIFT 3 +#define CCM_PRE44_MUX_B_MASK 0x700u +#define CCM_PRE44_MUX_B_SHIFT 8 +#define CCM_PRE44_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_MUX_B_SHIFT))&CCM_PRE44_MUX_B_MASK) +#define CCM_PRE44_EN_B_MASK 0x1000u +#define CCM_PRE44_EN_B_SHIFT 12 +#define CCM_PRE44_BUSY1_MASK 0x8000u +#define CCM_PRE44_BUSY1_SHIFT 15 +#define CCM_PRE44_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE44_PRE_PODF_A_SHIFT 16 +#define CCM_PRE44_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_PRE_PODF_A_SHIFT))&CCM_PRE44_PRE_PODF_A_MASK) +#define CCM_PRE44_BUSY3_MASK 0x80000u +#define CCM_PRE44_BUSY3_SHIFT 19 +#define CCM_PRE44_MUX_A_MASK 0x7000000u +#define CCM_PRE44_MUX_A_SHIFT 24 +#define CCM_PRE44_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE44_MUX_A_SHIFT))&CCM_PRE44_MUX_A_MASK) +#define CCM_PRE44_EN_A_MASK 0x10000000u +#define CCM_PRE44_EN_A_SHIFT 28 +#define CCM_PRE44_BUSY4_MASK 0x80000000u +#define CCM_PRE44_BUSY4_SHIFT 31 +/* PRE_ROOT44_SET Bit Fields */ +#define CCM_PRE_ROOT44_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT44_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT44_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT44_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT44_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT44_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT44_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT44_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT44_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_MUX_B_SHIFT))&CCM_PRE_ROOT44_SET_MUX_B_MASK) +#define CCM_PRE_ROOT44_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT44_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT44_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT44_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT44_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT44_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT44_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT44_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT44_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT44_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT44_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT44_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT44_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_SET_MUX_A_SHIFT))&CCM_PRE_ROOT44_SET_MUX_A_MASK) +#define CCM_PRE_ROOT44_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT44_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT44_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT44_SET_BUSY4_SHIFT 31 +/* PRE_ROOT44_CLR Bit Fields */ +#define CCM_PRE_ROOT44_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT44_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT44_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT44_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT44_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT44_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT44_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT44_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT44_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT44_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT44_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT44_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT44_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT44_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT44_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT44_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT44_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT44_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT44_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT44_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT44_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT44_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT44_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT44_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT44_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT44_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT44_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT44_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT44_TOG Bit Fields */ +#define CCM_PRE_ROOT44_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT44_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT44_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT44_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT44_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT44_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT44_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT44_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT44_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT44_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT44_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT44_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT44_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT44_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT44_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT44_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT44_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT44_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT44_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT44_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT44_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT44_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT44_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT44_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT44_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT44_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT44_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT44_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT44_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL44 Bit Fields */ +#define CCM_ACCESS_CTRL44_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL44_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL44_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL44_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL44_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL44_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL44_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL44_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL44_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL44_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL44_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL44_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL44_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL44_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL44_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL44_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL44_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL44_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL44_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL44_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL44_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL44_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL44_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL44_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL44_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL44_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL44_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL44_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL44_LOCK_SHIFT 31 +/* ACCESS_CTRL44_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL44_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL44_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL44_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL44_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL44_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL44_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL44_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL44_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL44_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL44_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL44_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL44_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL44_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL44_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL44_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL44_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL44_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL44_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT45 Bit Fields */ +#define CCM_TARGET_ROOT45_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT45_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT45_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_POST_PODF_MASK) +#define CCM_TARGET_ROOT45_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT45_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT45_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT45_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT45_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT45_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT45_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT45_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT45_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT45_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_PRE_PODF_MASK) +#define CCM_TARGET_ROOT45_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT45_MUX_SHIFT 24 +#define CCM_TARGET_ROOT45_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_MUX_SHIFT))&CCM_TARGET_ROOT45_MUX_MASK) +#define CCM_TARGET_ROOT45_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT45_ENABLE_SHIFT 28 +/* TARGET_ROOT45_SET Bit Fields */ +#define CCM_TARGET_ROOT45_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT45_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT45_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT45_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT45_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT45_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT45_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT45_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT45_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT45_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT45_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT45_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT45_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT45_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT45_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT45_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_SET_MUX_SHIFT))&CCM_TARGET_ROOT45_SET_MUX_MASK) +#define CCM_TARGET_ROOT45_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT45_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT45_CLR Bit Fields */ +#define CCM_TARGET_ROOT45_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT45_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT45_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT45_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT45_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT45_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT45_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT45_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT45_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT45_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT45_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT45_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT45_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_CLR_MUX_SHIFT))&CCM_TARGET_ROOT45_CLR_MUX_MASK) +#define CCM_TARGET_ROOT45_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT45_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT45_TOG Bit Fields */ +#define CCM_TARGET_ROOT45_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT45_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT45_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT45_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT45_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT45_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT45_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT45_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT45_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT45_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT45_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT45_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT45_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT45_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT45_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT45_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT45_TOG_MUX_SHIFT))&CCM_TARGET_ROOT45_TOG_MUX_MASK) +#define CCM_TARGET_ROOT45_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT45_TOG_ENABLE_SHIFT 28 +/* POST45 Bit Fields */ +#define CCM_POST45_POST_PODF_MASK 0x3Fu +#define CCM_POST45_POST_PODF_SHIFT 0 +#define CCM_POST45_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST45_POST_PODF_SHIFT))&CCM_POST45_POST_PODF_MASK) +#define CCM_POST45_BUSY1_MASK 0x80u +#define CCM_POST45_BUSY1_SHIFT 7 +#define CCM_POST45_AUTO_PODF_MASK 0x700u +#define CCM_POST45_AUTO_PODF_SHIFT 8 +#define CCM_POST45_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST45_AUTO_PODF_SHIFT))&CCM_POST45_AUTO_PODF_MASK) +#define CCM_POST45_AUTO_EN_MASK 0x1000u +#define CCM_POST45_AUTO_EN_SHIFT 12 +#define CCM_POST45_SLOW_MASK 0x8000u +#define CCM_POST45_SLOW_SHIFT 15 +#define CCM_POST45_SELECT_MASK 0x10000000u +#define CCM_POST45_SELECT_SHIFT 28 +#define CCM_POST45_BUSY2_MASK 0x80000000u +#define CCM_POST45_BUSY2_SHIFT 31 +/* POST_ROOT45_SET Bit Fields */ +#define CCM_POST_ROOT45_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT45_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT45_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_SET_POST_PODF_SHIFT))&CCM_POST_ROOT45_SET_POST_PODF_MASK) +#define CCM_POST_ROOT45_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT45_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT45_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT45_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT45_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT45_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT45_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT45_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT45_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT45_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT45_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT45_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT45_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT45_SET_BUSY2_SHIFT 31 +/* POST_ROOT45_CLR Bit Fields */ +#define CCM_POST_ROOT45_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT45_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT45_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT45_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT45_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT45_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT45_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT45_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT45_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT45_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT45_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT45_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT45_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT45_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT45_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT45_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT45_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT45_CLR_BUSY2_SHIFT 31 +/* POST_ROOT45_TOG Bit Fields */ +#define CCM_POST_ROOT45_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT45_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT45_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT45_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT45_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT45_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT45_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT45_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT45_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT45_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT45_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT45_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT45_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT45_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT45_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT45_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT45_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT45_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT45_TOG_BUSY2_SHIFT 31 +/* PRE45 Bit Fields */ +#define CCM_PRE45_PRE_PODF_B_MASK 0x7u +#define CCM_PRE45_PRE_PODF_B_SHIFT 0 +#define CCM_PRE45_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_PRE_PODF_B_SHIFT))&CCM_PRE45_PRE_PODF_B_MASK) +#define CCM_PRE45_BUSY0_MASK 0x8u +#define CCM_PRE45_BUSY0_SHIFT 3 +#define CCM_PRE45_MUX_B_MASK 0x700u +#define CCM_PRE45_MUX_B_SHIFT 8 +#define CCM_PRE45_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_MUX_B_SHIFT))&CCM_PRE45_MUX_B_MASK) +#define CCM_PRE45_EN_B_MASK 0x1000u +#define CCM_PRE45_EN_B_SHIFT 12 +#define CCM_PRE45_BUSY1_MASK 0x8000u +#define CCM_PRE45_BUSY1_SHIFT 15 +#define CCM_PRE45_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE45_PRE_PODF_A_SHIFT 16 +#define CCM_PRE45_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_PRE_PODF_A_SHIFT))&CCM_PRE45_PRE_PODF_A_MASK) +#define CCM_PRE45_BUSY3_MASK 0x80000u +#define CCM_PRE45_BUSY3_SHIFT 19 +#define CCM_PRE45_MUX_A_MASK 0x7000000u +#define CCM_PRE45_MUX_A_SHIFT 24 +#define CCM_PRE45_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE45_MUX_A_SHIFT))&CCM_PRE45_MUX_A_MASK) +#define CCM_PRE45_EN_A_MASK 0x10000000u +#define CCM_PRE45_EN_A_SHIFT 28 +#define CCM_PRE45_BUSY4_MASK 0x80000000u +#define CCM_PRE45_BUSY4_SHIFT 31 +/* PRE_ROOT45_SET Bit Fields */ +#define CCM_PRE_ROOT45_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT45_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT45_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT45_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT45_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT45_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT45_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT45_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT45_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_MUX_B_SHIFT))&CCM_PRE_ROOT45_SET_MUX_B_MASK) +#define CCM_PRE_ROOT45_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT45_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT45_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT45_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT45_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT45_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT45_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT45_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT45_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT45_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT45_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT45_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT45_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_SET_MUX_A_SHIFT))&CCM_PRE_ROOT45_SET_MUX_A_MASK) +#define CCM_PRE_ROOT45_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT45_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT45_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT45_SET_BUSY4_SHIFT 31 +/* PRE_ROOT45_CLR Bit Fields */ +#define CCM_PRE_ROOT45_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT45_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT45_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT45_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT45_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT45_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT45_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT45_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT45_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT45_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT45_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT45_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT45_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT45_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT45_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT45_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT45_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT45_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT45_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT45_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT45_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT45_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT45_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT45_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT45_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT45_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT45_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT45_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT45_TOG Bit Fields */ +#define CCM_PRE_ROOT45_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT45_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT45_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT45_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT45_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT45_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT45_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT45_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT45_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT45_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT45_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT45_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT45_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT45_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT45_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT45_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT45_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT45_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT45_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT45_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT45_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT45_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT45_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT45_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT45_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT45_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT45_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT45_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT45_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL45 Bit Fields */ +#define CCM_ACCESS_CTRL45_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL45_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL45_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL45_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL45_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL45_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL45_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL45_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL45_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL45_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL45_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL45_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL45_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL45_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL45_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL45_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL45_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL45_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL45_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL45_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL45_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL45_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL45_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL45_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL45_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL45_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL45_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL45_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL45_LOCK_SHIFT 31 +/* ACCESS_CTRL45_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL45_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL45_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL45_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL45_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL45_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL45_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL45_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL45_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL45_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL45_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL45_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL45_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL45_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL45_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL45_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL45_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL45_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL45_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT46 Bit Fields */ +#define CCM_TARGET_ROOT46_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT46_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT46_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_POST_PODF_MASK) +#define CCM_TARGET_ROOT46_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT46_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT46_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT46_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT46_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT46_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT46_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT46_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT46_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT46_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_PRE_PODF_MASK) +#define CCM_TARGET_ROOT46_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT46_MUX_SHIFT 24 +#define CCM_TARGET_ROOT46_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_MUX_SHIFT))&CCM_TARGET_ROOT46_MUX_MASK) +#define CCM_TARGET_ROOT46_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT46_ENABLE_SHIFT 28 +/* TARGET_ROOT46_SET Bit Fields */ +#define CCM_TARGET_ROOT46_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT46_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT46_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT46_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT46_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT46_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT46_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT46_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT46_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT46_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT46_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT46_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT46_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT46_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT46_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT46_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_SET_MUX_SHIFT))&CCM_TARGET_ROOT46_SET_MUX_MASK) +#define CCM_TARGET_ROOT46_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT46_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT46_CLR Bit Fields */ +#define CCM_TARGET_ROOT46_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT46_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT46_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT46_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT46_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT46_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT46_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT46_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT46_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT46_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT46_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT46_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT46_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_CLR_MUX_SHIFT))&CCM_TARGET_ROOT46_CLR_MUX_MASK) +#define CCM_TARGET_ROOT46_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT46_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT46_TOG Bit Fields */ +#define CCM_TARGET_ROOT46_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT46_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT46_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT46_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT46_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT46_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT46_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT46_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT46_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT46_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT46_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT46_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT46_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT46_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT46_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT46_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT46_TOG_MUX_SHIFT))&CCM_TARGET_ROOT46_TOG_MUX_MASK) +#define CCM_TARGET_ROOT46_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT46_TOG_ENABLE_SHIFT 28 +/* POST46 Bit Fields */ +#define CCM_POST46_POST_PODF_MASK 0x3Fu +#define CCM_POST46_POST_PODF_SHIFT 0 +#define CCM_POST46_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST46_POST_PODF_SHIFT))&CCM_POST46_POST_PODF_MASK) +#define CCM_POST46_BUSY1_MASK 0x80u +#define CCM_POST46_BUSY1_SHIFT 7 +#define CCM_POST46_AUTO_PODF_MASK 0x700u +#define CCM_POST46_AUTO_PODF_SHIFT 8 +#define CCM_POST46_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST46_AUTO_PODF_SHIFT))&CCM_POST46_AUTO_PODF_MASK) +#define CCM_POST46_AUTO_EN_MASK 0x1000u +#define CCM_POST46_AUTO_EN_SHIFT 12 +#define CCM_POST46_SLOW_MASK 0x8000u +#define CCM_POST46_SLOW_SHIFT 15 +#define CCM_POST46_SELECT_MASK 0x10000000u +#define CCM_POST46_SELECT_SHIFT 28 +#define CCM_POST46_BUSY2_MASK 0x80000000u +#define CCM_POST46_BUSY2_SHIFT 31 +/* POST_ROOT46_SET Bit Fields */ +#define CCM_POST_ROOT46_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT46_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT46_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_SET_POST_PODF_SHIFT))&CCM_POST_ROOT46_SET_POST_PODF_MASK) +#define CCM_POST_ROOT46_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT46_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT46_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT46_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT46_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT46_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT46_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT46_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT46_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT46_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT46_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT46_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT46_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT46_SET_BUSY2_SHIFT 31 +/* POST_ROOT46_CLR Bit Fields */ +#define CCM_POST_ROOT46_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT46_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT46_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT46_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT46_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT46_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT46_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT46_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT46_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT46_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT46_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT46_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT46_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT46_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT46_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT46_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT46_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT46_CLR_BUSY2_SHIFT 31 +/* POST_ROOT46_TOG Bit Fields */ +#define CCM_POST_ROOT46_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT46_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT46_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT46_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT46_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT46_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT46_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT46_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT46_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT46_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT46_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT46_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT46_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT46_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT46_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT46_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT46_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT46_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT46_TOG_BUSY2_SHIFT 31 +/* PRE46 Bit Fields */ +#define CCM_PRE46_PRE_PODF_B_MASK 0x7u +#define CCM_PRE46_PRE_PODF_B_SHIFT 0 +#define CCM_PRE46_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_PRE_PODF_B_SHIFT))&CCM_PRE46_PRE_PODF_B_MASK) +#define CCM_PRE46_BUSY0_MASK 0x8u +#define CCM_PRE46_BUSY0_SHIFT 3 +#define CCM_PRE46_MUX_B_MASK 0x700u +#define CCM_PRE46_MUX_B_SHIFT 8 +#define CCM_PRE46_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_MUX_B_SHIFT))&CCM_PRE46_MUX_B_MASK) +#define CCM_PRE46_EN_B_MASK 0x1000u +#define CCM_PRE46_EN_B_SHIFT 12 +#define CCM_PRE46_BUSY1_MASK 0x8000u +#define CCM_PRE46_BUSY1_SHIFT 15 +#define CCM_PRE46_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE46_PRE_PODF_A_SHIFT 16 +#define CCM_PRE46_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_PRE_PODF_A_SHIFT))&CCM_PRE46_PRE_PODF_A_MASK) +#define CCM_PRE46_BUSY3_MASK 0x80000u +#define CCM_PRE46_BUSY3_SHIFT 19 +#define CCM_PRE46_MUX_A_MASK 0x7000000u +#define CCM_PRE46_MUX_A_SHIFT 24 +#define CCM_PRE46_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE46_MUX_A_SHIFT))&CCM_PRE46_MUX_A_MASK) +#define CCM_PRE46_EN_A_MASK 0x10000000u +#define CCM_PRE46_EN_A_SHIFT 28 +#define CCM_PRE46_BUSY4_MASK 0x80000000u +#define CCM_PRE46_BUSY4_SHIFT 31 +/* PRE_ROOT46_SET Bit Fields */ +#define CCM_PRE_ROOT46_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT46_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT46_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT46_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT46_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT46_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT46_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT46_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT46_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_MUX_B_SHIFT))&CCM_PRE_ROOT46_SET_MUX_B_MASK) +#define CCM_PRE_ROOT46_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT46_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT46_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT46_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT46_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT46_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT46_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT46_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT46_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT46_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT46_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT46_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT46_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_SET_MUX_A_SHIFT))&CCM_PRE_ROOT46_SET_MUX_A_MASK) +#define CCM_PRE_ROOT46_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT46_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT46_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT46_SET_BUSY4_SHIFT 31 +/* PRE_ROOT46_CLR Bit Fields */ +#define CCM_PRE_ROOT46_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT46_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT46_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT46_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT46_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT46_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT46_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT46_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT46_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT46_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT46_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT46_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT46_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT46_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT46_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT46_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT46_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT46_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT46_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT46_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT46_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT46_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT46_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT46_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT46_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT46_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT46_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT46_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT46_TOG Bit Fields */ +#define CCM_PRE_ROOT46_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT46_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT46_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT46_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT46_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT46_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT46_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT46_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT46_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT46_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT46_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT46_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT46_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT46_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT46_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT46_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT46_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT46_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT46_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT46_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT46_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT46_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT46_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT46_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT46_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT46_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT46_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT46_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT46_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL46 Bit Fields */ +#define CCM_ACCESS_CTRL46_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL46_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL46_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL46_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL46_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL46_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL46_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL46_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL46_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL46_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL46_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL46_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL46_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL46_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL46_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL46_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL46_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL46_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL46_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL46_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL46_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL46_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL46_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL46_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL46_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL46_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL46_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL46_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL46_LOCK_SHIFT 31 +/* ACCESS_CTRL46_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL46_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL46_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL46_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL46_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL46_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL46_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL46_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL46_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL46_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL46_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL46_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL46_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL46_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL46_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL46_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL46_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL46_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL46_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT47 Bit Fields */ +#define CCM_TARGET_ROOT47_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT47_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT47_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_POST_PODF_MASK) +#define CCM_TARGET_ROOT47_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT47_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT47_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT47_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT47_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT47_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT47_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT47_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT47_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT47_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_PRE_PODF_MASK) +#define CCM_TARGET_ROOT47_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT47_MUX_SHIFT 24 +#define CCM_TARGET_ROOT47_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_MUX_SHIFT))&CCM_TARGET_ROOT47_MUX_MASK) +#define CCM_TARGET_ROOT47_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT47_ENABLE_SHIFT 28 +/* TARGET_ROOT47_SET Bit Fields */ +#define CCM_TARGET_ROOT47_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT47_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT47_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT47_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT47_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT47_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT47_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT47_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT47_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT47_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT47_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT47_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT47_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT47_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT47_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT47_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_SET_MUX_SHIFT))&CCM_TARGET_ROOT47_SET_MUX_MASK) +#define CCM_TARGET_ROOT47_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT47_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT47_CLR Bit Fields */ +#define CCM_TARGET_ROOT47_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT47_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT47_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT47_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT47_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT47_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT47_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT47_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT47_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT47_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT47_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT47_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT47_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_CLR_MUX_SHIFT))&CCM_TARGET_ROOT47_CLR_MUX_MASK) +#define CCM_TARGET_ROOT47_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT47_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT47_TOG Bit Fields */ +#define CCM_TARGET_ROOT47_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT47_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT47_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT47_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT47_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT47_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT47_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT47_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT47_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT47_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT47_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT47_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT47_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT47_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT47_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT47_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT47_TOG_MUX_SHIFT))&CCM_TARGET_ROOT47_TOG_MUX_MASK) +#define CCM_TARGET_ROOT47_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT47_TOG_ENABLE_SHIFT 28 +/* POST47 Bit Fields */ +#define CCM_POST47_POST_PODF_MASK 0x3Fu +#define CCM_POST47_POST_PODF_SHIFT 0 +#define CCM_POST47_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST47_POST_PODF_SHIFT))&CCM_POST47_POST_PODF_MASK) +#define CCM_POST47_BUSY1_MASK 0x80u +#define CCM_POST47_BUSY1_SHIFT 7 +#define CCM_POST47_AUTO_PODF_MASK 0x700u +#define CCM_POST47_AUTO_PODF_SHIFT 8 +#define CCM_POST47_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST47_AUTO_PODF_SHIFT))&CCM_POST47_AUTO_PODF_MASK) +#define CCM_POST47_AUTO_EN_MASK 0x1000u +#define CCM_POST47_AUTO_EN_SHIFT 12 +#define CCM_POST47_SLOW_MASK 0x8000u +#define CCM_POST47_SLOW_SHIFT 15 +#define CCM_POST47_SELECT_MASK 0x10000000u +#define CCM_POST47_SELECT_SHIFT 28 +#define CCM_POST47_BUSY2_MASK 0x80000000u +#define CCM_POST47_BUSY2_SHIFT 31 +/* POST_ROOT47_SET Bit Fields */ +#define CCM_POST_ROOT47_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT47_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT47_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_SET_POST_PODF_SHIFT))&CCM_POST_ROOT47_SET_POST_PODF_MASK) +#define CCM_POST_ROOT47_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT47_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT47_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT47_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT47_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT47_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT47_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT47_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT47_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT47_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT47_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT47_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT47_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT47_SET_BUSY2_SHIFT 31 +/* POST_ROOT47_CLR Bit Fields */ +#define CCM_POST_ROOT47_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT47_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT47_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT47_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT47_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT47_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT47_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT47_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT47_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT47_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT47_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT47_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT47_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT47_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT47_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT47_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT47_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT47_CLR_BUSY2_SHIFT 31 +/* POST_ROOT47_TOG Bit Fields */ +#define CCM_POST_ROOT47_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT47_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT47_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT47_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT47_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT47_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT47_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT47_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT47_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT47_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT47_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT47_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT47_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT47_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT47_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT47_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT47_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT47_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT47_TOG_BUSY2_SHIFT 31 +/* PRE47 Bit Fields */ +#define CCM_PRE47_PRE_PODF_B_MASK 0x7u +#define CCM_PRE47_PRE_PODF_B_SHIFT 0 +#define CCM_PRE47_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_PRE_PODF_B_SHIFT))&CCM_PRE47_PRE_PODF_B_MASK) +#define CCM_PRE47_BUSY0_MASK 0x8u +#define CCM_PRE47_BUSY0_SHIFT 3 +#define CCM_PRE47_MUX_B_MASK 0x700u +#define CCM_PRE47_MUX_B_SHIFT 8 +#define CCM_PRE47_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_MUX_B_SHIFT))&CCM_PRE47_MUX_B_MASK) +#define CCM_PRE47_EN_B_MASK 0x1000u +#define CCM_PRE47_EN_B_SHIFT 12 +#define CCM_PRE47_BUSY1_MASK 0x8000u +#define CCM_PRE47_BUSY1_SHIFT 15 +#define CCM_PRE47_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE47_PRE_PODF_A_SHIFT 16 +#define CCM_PRE47_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_PRE_PODF_A_SHIFT))&CCM_PRE47_PRE_PODF_A_MASK) +#define CCM_PRE47_BUSY3_MASK 0x80000u +#define CCM_PRE47_BUSY3_SHIFT 19 +#define CCM_PRE47_MUX_A_MASK 0x7000000u +#define CCM_PRE47_MUX_A_SHIFT 24 +#define CCM_PRE47_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE47_MUX_A_SHIFT))&CCM_PRE47_MUX_A_MASK) +#define CCM_PRE47_EN_A_MASK 0x10000000u +#define CCM_PRE47_EN_A_SHIFT 28 +#define CCM_PRE47_BUSY4_MASK 0x80000000u +#define CCM_PRE47_BUSY4_SHIFT 31 +/* PRE_ROOT47_SET Bit Fields */ +#define CCM_PRE_ROOT47_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT47_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT47_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT47_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT47_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT47_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT47_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT47_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT47_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_MUX_B_SHIFT))&CCM_PRE_ROOT47_SET_MUX_B_MASK) +#define CCM_PRE_ROOT47_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT47_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT47_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT47_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT47_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT47_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT47_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT47_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT47_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT47_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT47_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT47_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT47_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_SET_MUX_A_SHIFT))&CCM_PRE_ROOT47_SET_MUX_A_MASK) +#define CCM_PRE_ROOT47_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT47_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT47_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT47_SET_BUSY4_SHIFT 31 +/* PRE_ROOT47_CLR Bit Fields */ +#define CCM_PRE_ROOT47_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT47_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT47_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT47_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT47_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT47_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT47_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT47_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT47_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT47_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT47_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT47_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT47_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT47_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT47_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT47_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT47_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT47_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT47_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT47_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT47_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT47_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT47_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT47_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT47_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT47_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT47_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT47_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT47_TOG Bit Fields */ +#define CCM_PRE_ROOT47_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT47_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT47_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT47_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT47_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT47_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT47_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT47_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT47_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT47_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT47_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT47_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT47_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT47_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT47_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT47_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT47_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT47_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT47_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT47_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT47_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT47_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT47_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT47_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT47_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT47_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT47_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT47_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT47_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL47 Bit Fields */ +#define CCM_ACCESS_CTRL47_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL47_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL47_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL47_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL47_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL47_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL47_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL47_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL47_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL47_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL47_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL47_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL47_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL47_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL47_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL47_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL47_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL47_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL47_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL47_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL47_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL47_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL47_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL47_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL47_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL47_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL47_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL47_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL47_LOCK_SHIFT 31 +/* ACCESS_CTRL47_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL47_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL47_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL47_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL47_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL47_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL47_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL47_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL47_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL47_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL47_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL47_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL47_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL47_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL47_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL47_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL47_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL47_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL47_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT48 Bit Fields */ +#define CCM_TARGET_ROOT48_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT48_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT48_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_POST_PODF_MASK) +#define CCM_TARGET_ROOT48_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT48_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT48_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT48_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT48_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT48_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT48_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT48_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT48_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT48_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_PRE_PODF_MASK) +#define CCM_TARGET_ROOT48_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT48_MUX_SHIFT 24 +#define CCM_TARGET_ROOT48_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_MUX_SHIFT))&CCM_TARGET_ROOT48_MUX_MASK) +#define CCM_TARGET_ROOT48_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT48_ENABLE_SHIFT 28 +/* TARGET_ROOT48_SET Bit Fields */ +#define CCM_TARGET_ROOT48_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT48_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT48_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT48_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT48_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT48_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT48_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT48_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT48_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT48_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT48_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT48_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT48_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT48_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT48_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT48_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_SET_MUX_SHIFT))&CCM_TARGET_ROOT48_SET_MUX_MASK) +#define CCM_TARGET_ROOT48_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT48_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT48_CLR Bit Fields */ +#define CCM_TARGET_ROOT48_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT48_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT48_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT48_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT48_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT48_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT48_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT48_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT48_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT48_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT48_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT48_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT48_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_CLR_MUX_SHIFT))&CCM_TARGET_ROOT48_CLR_MUX_MASK) +#define CCM_TARGET_ROOT48_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT48_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT48_TOG Bit Fields */ +#define CCM_TARGET_ROOT48_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT48_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT48_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT48_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT48_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT48_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT48_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT48_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT48_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT48_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT48_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT48_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT48_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT48_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT48_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT48_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT48_TOG_MUX_SHIFT))&CCM_TARGET_ROOT48_TOG_MUX_MASK) +#define CCM_TARGET_ROOT48_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT48_TOG_ENABLE_SHIFT 28 +/* POST48 Bit Fields */ +#define CCM_POST48_POST_PODF_MASK 0x3Fu +#define CCM_POST48_POST_PODF_SHIFT 0 +#define CCM_POST48_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST48_POST_PODF_SHIFT))&CCM_POST48_POST_PODF_MASK) +#define CCM_POST48_BUSY1_MASK 0x80u +#define CCM_POST48_BUSY1_SHIFT 7 +#define CCM_POST48_AUTO_PODF_MASK 0x700u +#define CCM_POST48_AUTO_PODF_SHIFT 8 +#define CCM_POST48_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST48_AUTO_PODF_SHIFT))&CCM_POST48_AUTO_PODF_MASK) +#define CCM_POST48_AUTO_EN_MASK 0x1000u +#define CCM_POST48_AUTO_EN_SHIFT 12 +#define CCM_POST48_SLOW_MASK 0x8000u +#define CCM_POST48_SLOW_SHIFT 15 +#define CCM_POST48_SELECT_MASK 0x10000000u +#define CCM_POST48_SELECT_SHIFT 28 +#define CCM_POST48_BUSY2_MASK 0x80000000u +#define CCM_POST48_BUSY2_SHIFT 31 +/* POST_ROOT48_SET Bit Fields */ +#define CCM_POST_ROOT48_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT48_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT48_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_SET_POST_PODF_SHIFT))&CCM_POST_ROOT48_SET_POST_PODF_MASK) +#define CCM_POST_ROOT48_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT48_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT48_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT48_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT48_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT48_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT48_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT48_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT48_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT48_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT48_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT48_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT48_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT48_SET_BUSY2_SHIFT 31 +/* POST_ROOT48_CLR Bit Fields */ +#define CCM_POST_ROOT48_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT48_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT48_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT48_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT48_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT48_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT48_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT48_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT48_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT48_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT48_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT48_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT48_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT48_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT48_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT48_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT48_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT48_CLR_BUSY2_SHIFT 31 +/* POST_ROOT48_TOG Bit Fields */ +#define CCM_POST_ROOT48_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT48_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT48_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT48_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT48_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT48_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT48_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT48_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT48_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT48_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT48_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT48_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT48_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT48_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT48_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT48_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT48_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT48_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT48_TOG_BUSY2_SHIFT 31 +/* PRE48 Bit Fields */ +#define CCM_PRE48_PRE_PODF_B_MASK 0x7u +#define CCM_PRE48_PRE_PODF_B_SHIFT 0 +#define CCM_PRE48_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_PRE_PODF_B_SHIFT))&CCM_PRE48_PRE_PODF_B_MASK) +#define CCM_PRE48_BUSY0_MASK 0x8u +#define CCM_PRE48_BUSY0_SHIFT 3 +#define CCM_PRE48_MUX_B_MASK 0x700u +#define CCM_PRE48_MUX_B_SHIFT 8 +#define CCM_PRE48_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_MUX_B_SHIFT))&CCM_PRE48_MUX_B_MASK) +#define CCM_PRE48_EN_B_MASK 0x1000u +#define CCM_PRE48_EN_B_SHIFT 12 +#define CCM_PRE48_BUSY1_MASK 0x8000u +#define CCM_PRE48_BUSY1_SHIFT 15 +#define CCM_PRE48_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE48_PRE_PODF_A_SHIFT 16 +#define CCM_PRE48_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_PRE_PODF_A_SHIFT))&CCM_PRE48_PRE_PODF_A_MASK) +#define CCM_PRE48_BUSY3_MASK 0x80000u +#define CCM_PRE48_BUSY3_SHIFT 19 +#define CCM_PRE48_MUX_A_MASK 0x7000000u +#define CCM_PRE48_MUX_A_SHIFT 24 +#define CCM_PRE48_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE48_MUX_A_SHIFT))&CCM_PRE48_MUX_A_MASK) +#define CCM_PRE48_EN_A_MASK 0x10000000u +#define CCM_PRE48_EN_A_SHIFT 28 +#define CCM_PRE48_BUSY4_MASK 0x80000000u +#define CCM_PRE48_BUSY4_SHIFT 31 +/* PRE_ROOT48_SET Bit Fields */ +#define CCM_PRE_ROOT48_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT48_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT48_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT48_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT48_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT48_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT48_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT48_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT48_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_MUX_B_SHIFT))&CCM_PRE_ROOT48_SET_MUX_B_MASK) +#define CCM_PRE_ROOT48_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT48_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT48_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT48_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT48_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT48_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT48_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT48_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT48_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT48_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT48_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT48_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT48_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_SET_MUX_A_SHIFT))&CCM_PRE_ROOT48_SET_MUX_A_MASK) +#define CCM_PRE_ROOT48_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT48_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT48_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT48_SET_BUSY4_SHIFT 31 +/* PRE_ROOT48_CLR Bit Fields */ +#define CCM_PRE_ROOT48_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT48_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT48_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT48_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT48_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT48_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT48_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT48_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT48_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT48_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT48_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT48_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT48_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT48_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT48_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT48_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT48_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT48_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT48_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT48_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT48_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT48_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT48_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT48_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT48_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT48_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT48_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT48_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT48_TOG Bit Fields */ +#define CCM_PRE_ROOT48_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT48_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT48_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT48_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT48_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT48_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT48_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT48_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT48_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT48_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT48_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT48_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT48_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT48_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT48_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT48_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT48_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT48_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT48_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT48_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT48_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT48_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT48_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT48_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT48_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT48_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT48_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT48_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT48_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL48 Bit Fields */ +#define CCM_ACCESS_CTRL48_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL48_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL48_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL48_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL48_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL48_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL48_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL48_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL48_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL48_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL48_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL48_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL48_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL48_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL48_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL48_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL48_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL48_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL48_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL48_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL48_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL48_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL48_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL48_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL48_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL48_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL48_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL48_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL48_LOCK_SHIFT 31 +/* ACCESS_CTRL48_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL48_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL48_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL48_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL48_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL48_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL48_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL48_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL48_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL48_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL48_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL48_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL48_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL48_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL48_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL48_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL48_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL48_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL48_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT49 Bit Fields */ +#define CCM_TARGET_ROOT49_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT49_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT49_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_POST_PODF_MASK) +#define CCM_TARGET_ROOT49_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT49_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT49_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT49_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT49_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT49_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT49_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT49_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT49_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT49_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_PRE_PODF_MASK) +#define CCM_TARGET_ROOT49_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT49_MUX_SHIFT 24 +#define CCM_TARGET_ROOT49_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_MUX_SHIFT))&CCM_TARGET_ROOT49_MUX_MASK) +#define CCM_TARGET_ROOT49_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT49_ENABLE_SHIFT 28 +/* TARGET_ROOT49_SET Bit Fields */ +#define CCM_TARGET_ROOT49_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT49_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT49_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT49_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT49_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT49_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT49_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT49_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT49_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT49_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT49_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT49_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT49_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT49_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT49_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT49_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_SET_MUX_SHIFT))&CCM_TARGET_ROOT49_SET_MUX_MASK) +#define CCM_TARGET_ROOT49_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT49_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT49_CLR Bit Fields */ +#define CCM_TARGET_ROOT49_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT49_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT49_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT49_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT49_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT49_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT49_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT49_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT49_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT49_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT49_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT49_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT49_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_CLR_MUX_SHIFT))&CCM_TARGET_ROOT49_CLR_MUX_MASK) +#define CCM_TARGET_ROOT49_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT49_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT49_TOG Bit Fields */ +#define CCM_TARGET_ROOT49_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT49_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT49_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT49_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT49_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT49_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT49_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT49_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT49_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT49_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT49_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT49_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT49_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT49_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT49_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT49_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT49_TOG_MUX_SHIFT))&CCM_TARGET_ROOT49_TOG_MUX_MASK) +#define CCM_TARGET_ROOT49_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT49_TOG_ENABLE_SHIFT 28 +/* POST49 Bit Fields */ +#define CCM_POST49_POST_PODF_MASK 0x3Fu +#define CCM_POST49_POST_PODF_SHIFT 0 +#define CCM_POST49_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST49_POST_PODF_SHIFT))&CCM_POST49_POST_PODF_MASK) +#define CCM_POST49_BUSY1_MASK 0x80u +#define CCM_POST49_BUSY1_SHIFT 7 +#define CCM_POST49_AUTO_PODF_MASK 0x700u +#define CCM_POST49_AUTO_PODF_SHIFT 8 +#define CCM_POST49_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST49_AUTO_PODF_SHIFT))&CCM_POST49_AUTO_PODF_MASK) +#define CCM_POST49_AUTO_EN_MASK 0x1000u +#define CCM_POST49_AUTO_EN_SHIFT 12 +#define CCM_POST49_SLOW_MASK 0x8000u +#define CCM_POST49_SLOW_SHIFT 15 +#define CCM_POST49_SELECT_MASK 0x10000000u +#define CCM_POST49_SELECT_SHIFT 28 +#define CCM_POST49_BUSY2_MASK 0x80000000u +#define CCM_POST49_BUSY2_SHIFT 31 +/* POST_ROOT49_SET Bit Fields */ +#define CCM_POST_ROOT49_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT49_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT49_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_SET_POST_PODF_SHIFT))&CCM_POST_ROOT49_SET_POST_PODF_MASK) +#define CCM_POST_ROOT49_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT49_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT49_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT49_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT49_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT49_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT49_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT49_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT49_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT49_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT49_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT49_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT49_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT49_SET_BUSY2_SHIFT 31 +/* POST_ROOT49_CLR Bit Fields */ +#define CCM_POST_ROOT49_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT49_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT49_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT49_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT49_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT49_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT49_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT49_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT49_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT49_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT49_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT49_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT49_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT49_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT49_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT49_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT49_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT49_CLR_BUSY2_SHIFT 31 +/* POST_ROOT49_TOG Bit Fields */ +#define CCM_POST_ROOT49_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT49_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT49_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT49_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT49_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT49_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT49_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT49_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT49_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT49_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT49_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT49_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT49_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT49_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT49_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT49_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT49_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT49_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT49_TOG_BUSY2_SHIFT 31 +/* PRE49 Bit Fields */ +#define CCM_PRE49_PRE_PODF_B_MASK 0x7u +#define CCM_PRE49_PRE_PODF_B_SHIFT 0 +#define CCM_PRE49_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_PRE_PODF_B_SHIFT))&CCM_PRE49_PRE_PODF_B_MASK) +#define CCM_PRE49_BUSY0_MASK 0x8u +#define CCM_PRE49_BUSY0_SHIFT 3 +#define CCM_PRE49_MUX_B_MASK 0x700u +#define CCM_PRE49_MUX_B_SHIFT 8 +#define CCM_PRE49_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_MUX_B_SHIFT))&CCM_PRE49_MUX_B_MASK) +#define CCM_PRE49_EN_B_MASK 0x1000u +#define CCM_PRE49_EN_B_SHIFT 12 +#define CCM_PRE49_BUSY1_MASK 0x8000u +#define CCM_PRE49_BUSY1_SHIFT 15 +#define CCM_PRE49_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE49_PRE_PODF_A_SHIFT 16 +#define CCM_PRE49_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_PRE_PODF_A_SHIFT))&CCM_PRE49_PRE_PODF_A_MASK) +#define CCM_PRE49_BUSY3_MASK 0x80000u +#define CCM_PRE49_BUSY3_SHIFT 19 +#define CCM_PRE49_MUX_A_MASK 0x7000000u +#define CCM_PRE49_MUX_A_SHIFT 24 +#define CCM_PRE49_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE49_MUX_A_SHIFT))&CCM_PRE49_MUX_A_MASK) +#define CCM_PRE49_EN_A_MASK 0x10000000u +#define CCM_PRE49_EN_A_SHIFT 28 +#define CCM_PRE49_BUSY4_MASK 0x80000000u +#define CCM_PRE49_BUSY4_SHIFT 31 +/* PRE_ROOT49_SET Bit Fields */ +#define CCM_PRE_ROOT49_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT49_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT49_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT49_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT49_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT49_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT49_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT49_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT49_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_MUX_B_SHIFT))&CCM_PRE_ROOT49_SET_MUX_B_MASK) +#define CCM_PRE_ROOT49_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT49_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT49_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT49_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT49_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT49_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT49_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT49_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT49_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT49_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT49_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT49_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT49_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_SET_MUX_A_SHIFT))&CCM_PRE_ROOT49_SET_MUX_A_MASK) +#define CCM_PRE_ROOT49_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT49_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT49_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT49_SET_BUSY4_SHIFT 31 +/* PRE_ROOT49_CLR Bit Fields */ +#define CCM_PRE_ROOT49_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT49_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT49_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT49_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT49_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT49_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT49_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT49_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT49_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT49_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT49_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT49_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT49_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT49_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT49_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT49_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT49_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT49_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT49_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT49_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT49_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT49_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT49_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT49_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT49_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT49_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT49_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT49_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT49_TOG Bit Fields */ +#define CCM_PRE_ROOT49_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT49_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT49_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT49_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT49_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT49_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT49_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT49_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT49_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT49_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT49_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT49_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT49_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT49_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT49_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT49_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT49_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT49_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT49_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT49_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT49_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT49_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT49_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT49_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT49_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT49_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT49_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT49_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT49_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL49 Bit Fields */ +#define CCM_ACCESS_CTRL49_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL49_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL49_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL49_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL49_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL49_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL49_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL49_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL49_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL49_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL49_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL49_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL49_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL49_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL49_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL49_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL49_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL49_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL49_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL49_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL49_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL49_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL49_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL49_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL49_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL49_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL49_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL49_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL49_LOCK_SHIFT 31 +/* ACCESS_CTRL49_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL49_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL49_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL49_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL49_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL49_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL49_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL49_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL49_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL49_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL49_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL49_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL49_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL49_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL49_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL49_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL49_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL49_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL49_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT50 Bit Fields */ +#define CCM_TARGET_ROOT50_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT50_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT50_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_POST_PODF_MASK) +#define CCM_TARGET_ROOT50_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT50_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT50_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT50_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT50_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT50_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT50_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT50_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT50_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT50_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_PRE_PODF_MASK) +#define CCM_TARGET_ROOT50_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT50_MUX_SHIFT 24 +#define CCM_TARGET_ROOT50_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_MUX_SHIFT))&CCM_TARGET_ROOT50_MUX_MASK) +#define CCM_TARGET_ROOT50_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT50_ENABLE_SHIFT 28 +/* TARGET_ROOT50_SET Bit Fields */ +#define CCM_TARGET_ROOT50_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT50_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT50_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT50_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT50_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT50_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT50_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT50_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT50_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT50_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT50_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT50_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT50_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT50_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT50_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT50_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_SET_MUX_SHIFT))&CCM_TARGET_ROOT50_SET_MUX_MASK) +#define CCM_TARGET_ROOT50_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT50_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT50_CLR Bit Fields */ +#define CCM_TARGET_ROOT50_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT50_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT50_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT50_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT50_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT50_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT50_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT50_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT50_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT50_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT50_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT50_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT50_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_CLR_MUX_SHIFT))&CCM_TARGET_ROOT50_CLR_MUX_MASK) +#define CCM_TARGET_ROOT50_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT50_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT50_TOG Bit Fields */ +#define CCM_TARGET_ROOT50_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT50_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT50_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT50_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT50_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT50_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT50_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT50_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT50_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT50_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT50_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT50_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT50_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT50_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT50_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT50_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT50_TOG_MUX_SHIFT))&CCM_TARGET_ROOT50_TOG_MUX_MASK) +#define CCM_TARGET_ROOT50_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT50_TOG_ENABLE_SHIFT 28 +/* POST50 Bit Fields */ +#define CCM_POST50_POST_PODF_MASK 0x3Fu +#define CCM_POST50_POST_PODF_SHIFT 0 +#define CCM_POST50_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST50_POST_PODF_SHIFT))&CCM_POST50_POST_PODF_MASK) +#define CCM_POST50_BUSY1_MASK 0x80u +#define CCM_POST50_BUSY1_SHIFT 7 +#define CCM_POST50_AUTO_PODF_MASK 0x700u +#define CCM_POST50_AUTO_PODF_SHIFT 8 +#define CCM_POST50_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST50_AUTO_PODF_SHIFT))&CCM_POST50_AUTO_PODF_MASK) +#define CCM_POST50_AUTO_EN_MASK 0x1000u +#define CCM_POST50_AUTO_EN_SHIFT 12 +#define CCM_POST50_SLOW_MASK 0x8000u +#define CCM_POST50_SLOW_SHIFT 15 +#define CCM_POST50_SELECT_MASK 0x10000000u +#define CCM_POST50_SELECT_SHIFT 28 +#define CCM_POST50_BUSY2_MASK 0x80000000u +#define CCM_POST50_BUSY2_SHIFT 31 +/* POST_ROOT50_SET Bit Fields */ +#define CCM_POST_ROOT50_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT50_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT50_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_SET_POST_PODF_SHIFT))&CCM_POST_ROOT50_SET_POST_PODF_MASK) +#define CCM_POST_ROOT50_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT50_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT50_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT50_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT50_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT50_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT50_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT50_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT50_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT50_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT50_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT50_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT50_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT50_SET_BUSY2_SHIFT 31 +/* POST_ROOT50_CLR Bit Fields */ +#define CCM_POST_ROOT50_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT50_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT50_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT50_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT50_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT50_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT50_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT50_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT50_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT50_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT50_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT50_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT50_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT50_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT50_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT50_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT50_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT50_CLR_BUSY2_SHIFT 31 +/* POST_ROOT50_TOG Bit Fields */ +#define CCM_POST_ROOT50_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT50_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT50_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT50_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT50_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT50_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT50_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT50_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT50_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT50_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT50_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT50_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT50_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT50_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT50_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT50_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT50_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT50_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT50_TOG_BUSY2_SHIFT 31 +/* PRE50 Bit Fields */ +#define CCM_PRE50_PRE_PODF_B_MASK 0x7u +#define CCM_PRE50_PRE_PODF_B_SHIFT 0 +#define CCM_PRE50_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_PRE_PODF_B_SHIFT))&CCM_PRE50_PRE_PODF_B_MASK) +#define CCM_PRE50_BUSY0_MASK 0x8u +#define CCM_PRE50_BUSY0_SHIFT 3 +#define CCM_PRE50_MUX_B_MASK 0x700u +#define CCM_PRE50_MUX_B_SHIFT 8 +#define CCM_PRE50_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_MUX_B_SHIFT))&CCM_PRE50_MUX_B_MASK) +#define CCM_PRE50_EN_B_MASK 0x1000u +#define CCM_PRE50_EN_B_SHIFT 12 +#define CCM_PRE50_BUSY1_MASK 0x8000u +#define CCM_PRE50_BUSY1_SHIFT 15 +#define CCM_PRE50_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE50_PRE_PODF_A_SHIFT 16 +#define CCM_PRE50_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_PRE_PODF_A_SHIFT))&CCM_PRE50_PRE_PODF_A_MASK) +#define CCM_PRE50_BUSY3_MASK 0x80000u +#define CCM_PRE50_BUSY3_SHIFT 19 +#define CCM_PRE50_MUX_A_MASK 0x7000000u +#define CCM_PRE50_MUX_A_SHIFT 24 +#define CCM_PRE50_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE50_MUX_A_SHIFT))&CCM_PRE50_MUX_A_MASK) +#define CCM_PRE50_EN_A_MASK 0x10000000u +#define CCM_PRE50_EN_A_SHIFT 28 +#define CCM_PRE50_BUSY4_MASK 0x80000000u +#define CCM_PRE50_BUSY4_SHIFT 31 +/* PRE_ROOT50_SET Bit Fields */ +#define CCM_PRE_ROOT50_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT50_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT50_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT50_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT50_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT50_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT50_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT50_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT50_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_MUX_B_SHIFT))&CCM_PRE_ROOT50_SET_MUX_B_MASK) +#define CCM_PRE_ROOT50_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT50_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT50_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT50_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT50_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT50_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT50_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT50_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT50_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT50_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT50_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT50_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT50_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_SET_MUX_A_SHIFT))&CCM_PRE_ROOT50_SET_MUX_A_MASK) +#define CCM_PRE_ROOT50_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT50_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT50_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT50_SET_BUSY4_SHIFT 31 +/* PRE_ROOT50_CLR Bit Fields */ +#define CCM_PRE_ROOT50_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT50_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT50_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT50_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT50_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT50_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT50_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT50_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT50_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT50_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT50_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT50_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT50_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT50_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT50_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT50_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT50_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT50_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT50_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT50_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT50_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT50_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT50_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT50_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT50_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT50_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT50_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT50_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT50_TOG Bit Fields */ +#define CCM_PRE_ROOT50_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT50_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT50_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT50_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT50_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT50_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT50_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT50_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT50_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT50_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT50_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT50_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT50_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT50_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT50_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT50_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT50_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT50_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT50_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT50_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT50_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT50_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT50_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT50_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT50_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT50_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT50_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT50_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT50_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL50 Bit Fields */ +#define CCM_ACCESS_CTRL50_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL50_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL50_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL50_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL50_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL50_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL50_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL50_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL50_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL50_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL50_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL50_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL50_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL50_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL50_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL50_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL50_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL50_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL50_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL50_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL50_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL50_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL50_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL50_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL50_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL50_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL50_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL50_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL50_LOCK_SHIFT 31 +/* ACCESS_CTRL50_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL50_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL50_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL50_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL50_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL50_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL50_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL50_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL50_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL50_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL50_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL50_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL50_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL50_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL50_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL50_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL50_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL50_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL50_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT51 Bit Fields */ +#define CCM_TARGET_ROOT51_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT51_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT51_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_POST_PODF_MASK) +#define CCM_TARGET_ROOT51_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT51_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT51_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT51_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT51_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT51_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT51_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT51_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT51_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT51_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_PRE_PODF_MASK) +#define CCM_TARGET_ROOT51_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT51_MUX_SHIFT 24 +#define CCM_TARGET_ROOT51_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_MUX_SHIFT))&CCM_TARGET_ROOT51_MUX_MASK) +#define CCM_TARGET_ROOT51_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT51_ENABLE_SHIFT 28 +/* TARGET_ROOT51_SET Bit Fields */ +#define CCM_TARGET_ROOT51_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT51_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT51_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT51_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT51_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT51_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT51_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT51_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT51_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT51_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT51_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT51_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT51_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT51_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT51_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT51_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_SET_MUX_SHIFT))&CCM_TARGET_ROOT51_SET_MUX_MASK) +#define CCM_TARGET_ROOT51_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT51_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT51_CLR Bit Fields */ +#define CCM_TARGET_ROOT51_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT51_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT51_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT51_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT51_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT51_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT51_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT51_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT51_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT51_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT51_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT51_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT51_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_CLR_MUX_SHIFT))&CCM_TARGET_ROOT51_CLR_MUX_MASK) +#define CCM_TARGET_ROOT51_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT51_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT51_TOG Bit Fields */ +#define CCM_TARGET_ROOT51_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT51_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT51_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT51_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT51_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT51_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT51_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT51_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT51_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT51_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT51_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT51_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT51_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT51_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT51_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT51_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT51_TOG_MUX_SHIFT))&CCM_TARGET_ROOT51_TOG_MUX_MASK) +#define CCM_TARGET_ROOT51_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT51_TOG_ENABLE_SHIFT 28 +/* POST51 Bit Fields */ +#define CCM_POST51_POST_PODF_MASK 0x3Fu +#define CCM_POST51_POST_PODF_SHIFT 0 +#define CCM_POST51_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST51_POST_PODF_SHIFT))&CCM_POST51_POST_PODF_MASK) +#define CCM_POST51_BUSY1_MASK 0x80u +#define CCM_POST51_BUSY1_SHIFT 7 +#define CCM_POST51_AUTO_PODF_MASK 0x700u +#define CCM_POST51_AUTO_PODF_SHIFT 8 +#define CCM_POST51_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST51_AUTO_PODF_SHIFT))&CCM_POST51_AUTO_PODF_MASK) +#define CCM_POST51_AUTO_EN_MASK 0x1000u +#define CCM_POST51_AUTO_EN_SHIFT 12 +#define CCM_POST51_SLOW_MASK 0x8000u +#define CCM_POST51_SLOW_SHIFT 15 +#define CCM_POST51_SELECT_MASK 0x10000000u +#define CCM_POST51_SELECT_SHIFT 28 +#define CCM_POST51_BUSY2_MASK 0x80000000u +#define CCM_POST51_BUSY2_SHIFT 31 +/* POST_ROOT51_SET Bit Fields */ +#define CCM_POST_ROOT51_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT51_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT51_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_SET_POST_PODF_SHIFT))&CCM_POST_ROOT51_SET_POST_PODF_MASK) +#define CCM_POST_ROOT51_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT51_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT51_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT51_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT51_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT51_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT51_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT51_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT51_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT51_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT51_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT51_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT51_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT51_SET_BUSY2_SHIFT 31 +/* POST_ROOT51_CLR Bit Fields */ +#define CCM_POST_ROOT51_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT51_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT51_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT51_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT51_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT51_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT51_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT51_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT51_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT51_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT51_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT51_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT51_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT51_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT51_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT51_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT51_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT51_CLR_BUSY2_SHIFT 31 +/* POST_ROOT51_TOG Bit Fields */ +#define CCM_POST_ROOT51_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT51_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT51_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT51_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT51_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT51_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT51_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT51_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT51_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT51_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT51_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT51_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT51_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT51_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT51_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT51_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT51_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT51_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT51_TOG_BUSY2_SHIFT 31 +/* PRE51 Bit Fields */ +#define CCM_PRE51_PRE_PODF_B_MASK 0x7u +#define CCM_PRE51_PRE_PODF_B_SHIFT 0 +#define CCM_PRE51_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_PRE_PODF_B_SHIFT))&CCM_PRE51_PRE_PODF_B_MASK) +#define CCM_PRE51_BUSY0_MASK 0x8u +#define CCM_PRE51_BUSY0_SHIFT 3 +#define CCM_PRE51_MUX_B_MASK 0x700u +#define CCM_PRE51_MUX_B_SHIFT 8 +#define CCM_PRE51_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_MUX_B_SHIFT))&CCM_PRE51_MUX_B_MASK) +#define CCM_PRE51_EN_B_MASK 0x1000u +#define CCM_PRE51_EN_B_SHIFT 12 +#define CCM_PRE51_BUSY1_MASK 0x8000u +#define CCM_PRE51_BUSY1_SHIFT 15 +#define CCM_PRE51_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE51_PRE_PODF_A_SHIFT 16 +#define CCM_PRE51_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_PRE_PODF_A_SHIFT))&CCM_PRE51_PRE_PODF_A_MASK) +#define CCM_PRE51_BUSY3_MASK 0x80000u +#define CCM_PRE51_BUSY3_SHIFT 19 +#define CCM_PRE51_MUX_A_MASK 0x7000000u +#define CCM_PRE51_MUX_A_SHIFT 24 +#define CCM_PRE51_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE51_MUX_A_SHIFT))&CCM_PRE51_MUX_A_MASK) +#define CCM_PRE51_EN_A_MASK 0x10000000u +#define CCM_PRE51_EN_A_SHIFT 28 +#define CCM_PRE51_BUSY4_MASK 0x80000000u +#define CCM_PRE51_BUSY4_SHIFT 31 +/* PRE_ROOT51_SET Bit Fields */ +#define CCM_PRE_ROOT51_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT51_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT51_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT51_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT51_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT51_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT51_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT51_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT51_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_MUX_B_SHIFT))&CCM_PRE_ROOT51_SET_MUX_B_MASK) +#define CCM_PRE_ROOT51_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT51_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT51_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT51_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT51_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT51_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT51_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT51_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT51_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT51_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT51_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT51_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT51_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_SET_MUX_A_SHIFT))&CCM_PRE_ROOT51_SET_MUX_A_MASK) +#define CCM_PRE_ROOT51_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT51_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT51_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT51_SET_BUSY4_SHIFT 31 +/* PRE_ROOT51_CLR Bit Fields */ +#define CCM_PRE_ROOT51_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT51_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT51_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT51_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT51_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT51_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT51_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT51_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT51_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT51_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT51_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT51_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT51_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT51_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT51_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT51_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT51_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT51_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT51_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT51_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT51_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT51_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT51_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT51_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT51_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT51_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT51_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT51_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT51_TOG Bit Fields */ +#define CCM_PRE_ROOT51_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT51_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT51_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT51_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT51_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT51_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT51_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT51_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT51_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT51_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT51_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT51_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT51_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT51_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT51_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT51_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT51_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT51_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT51_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT51_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT51_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT51_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT51_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT51_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT51_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT51_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT51_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT51_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT51_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL51 Bit Fields */ +#define CCM_ACCESS_CTRL51_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL51_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL51_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL51_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL51_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL51_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL51_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL51_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL51_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL51_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL51_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL51_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL51_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL51_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL51_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL51_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL51_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL51_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL51_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL51_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL51_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL51_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL51_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL51_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL51_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL51_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL51_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL51_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL51_LOCK_SHIFT 31 +/* ACCESS_CTRL51_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL51_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL51_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL51_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL51_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL51_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL51_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL51_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL51_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL51_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL51_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL51_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL51_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL51_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL51_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL51_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL51_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL51_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL51_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT52 Bit Fields */ +#define CCM_TARGET_ROOT52_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT52_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT52_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_POST_PODF_MASK) +#define CCM_TARGET_ROOT52_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT52_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT52_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT52_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT52_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT52_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT52_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT52_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT52_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT52_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_PRE_PODF_MASK) +#define CCM_TARGET_ROOT52_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT52_MUX_SHIFT 24 +#define CCM_TARGET_ROOT52_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_MUX_SHIFT))&CCM_TARGET_ROOT52_MUX_MASK) +#define CCM_TARGET_ROOT52_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT52_ENABLE_SHIFT 28 +/* TARGET_ROOT52_SET Bit Fields */ +#define CCM_TARGET_ROOT52_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT52_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT52_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT52_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT52_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT52_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT52_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT52_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT52_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT52_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT52_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT52_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT52_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT52_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT52_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT52_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_SET_MUX_SHIFT))&CCM_TARGET_ROOT52_SET_MUX_MASK) +#define CCM_TARGET_ROOT52_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT52_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT52_CLR Bit Fields */ +#define CCM_TARGET_ROOT52_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT52_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT52_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT52_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT52_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT52_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT52_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT52_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT52_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT52_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT52_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT52_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT52_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_CLR_MUX_SHIFT))&CCM_TARGET_ROOT52_CLR_MUX_MASK) +#define CCM_TARGET_ROOT52_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT52_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT52_TOG Bit Fields */ +#define CCM_TARGET_ROOT52_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT52_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT52_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT52_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT52_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT52_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT52_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT52_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT52_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT52_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT52_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT52_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT52_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT52_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT52_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT52_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT52_TOG_MUX_SHIFT))&CCM_TARGET_ROOT52_TOG_MUX_MASK) +#define CCM_TARGET_ROOT52_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT52_TOG_ENABLE_SHIFT 28 +/* POST52 Bit Fields */ +#define CCM_POST52_POST_PODF_MASK 0x3Fu +#define CCM_POST52_POST_PODF_SHIFT 0 +#define CCM_POST52_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST52_POST_PODF_SHIFT))&CCM_POST52_POST_PODF_MASK) +#define CCM_POST52_BUSY1_MASK 0x80u +#define CCM_POST52_BUSY1_SHIFT 7 +#define CCM_POST52_AUTO_PODF_MASK 0x700u +#define CCM_POST52_AUTO_PODF_SHIFT 8 +#define CCM_POST52_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST52_AUTO_PODF_SHIFT))&CCM_POST52_AUTO_PODF_MASK) +#define CCM_POST52_AUTO_EN_MASK 0x1000u +#define CCM_POST52_AUTO_EN_SHIFT 12 +#define CCM_POST52_SLOW_MASK 0x8000u +#define CCM_POST52_SLOW_SHIFT 15 +#define CCM_POST52_SELECT_MASK 0x10000000u +#define CCM_POST52_SELECT_SHIFT 28 +#define CCM_POST52_BUSY2_MASK 0x80000000u +#define CCM_POST52_BUSY2_SHIFT 31 +/* POST_ROOT52_SET Bit Fields */ +#define CCM_POST_ROOT52_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT52_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT52_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_SET_POST_PODF_SHIFT))&CCM_POST_ROOT52_SET_POST_PODF_MASK) +#define CCM_POST_ROOT52_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT52_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT52_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT52_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT52_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT52_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT52_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT52_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT52_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT52_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT52_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT52_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT52_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT52_SET_BUSY2_SHIFT 31 +/* POST_ROOT52_CLR Bit Fields */ +#define CCM_POST_ROOT52_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT52_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT52_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT52_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT52_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT52_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT52_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT52_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT52_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT52_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT52_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT52_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT52_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT52_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT52_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT52_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT52_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT52_CLR_BUSY2_SHIFT 31 +/* POST_ROOT52_TOG Bit Fields */ +#define CCM_POST_ROOT52_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT52_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT52_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT52_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT52_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT52_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT52_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT52_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT52_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT52_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT52_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT52_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT52_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT52_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT52_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT52_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT52_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT52_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT52_TOG_BUSY2_SHIFT 31 +/* PRE52 Bit Fields */ +#define CCM_PRE52_PRE_PODF_B_MASK 0x7u +#define CCM_PRE52_PRE_PODF_B_SHIFT 0 +#define CCM_PRE52_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_PRE_PODF_B_SHIFT))&CCM_PRE52_PRE_PODF_B_MASK) +#define CCM_PRE52_BUSY0_MASK 0x8u +#define CCM_PRE52_BUSY0_SHIFT 3 +#define CCM_PRE52_MUX_B_MASK 0x700u +#define CCM_PRE52_MUX_B_SHIFT 8 +#define CCM_PRE52_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_MUX_B_SHIFT))&CCM_PRE52_MUX_B_MASK) +#define CCM_PRE52_EN_B_MASK 0x1000u +#define CCM_PRE52_EN_B_SHIFT 12 +#define CCM_PRE52_BUSY1_MASK 0x8000u +#define CCM_PRE52_BUSY1_SHIFT 15 +#define CCM_PRE52_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE52_PRE_PODF_A_SHIFT 16 +#define CCM_PRE52_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_PRE_PODF_A_SHIFT))&CCM_PRE52_PRE_PODF_A_MASK) +#define CCM_PRE52_BUSY3_MASK 0x80000u +#define CCM_PRE52_BUSY3_SHIFT 19 +#define CCM_PRE52_MUX_A_MASK 0x7000000u +#define CCM_PRE52_MUX_A_SHIFT 24 +#define CCM_PRE52_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE52_MUX_A_SHIFT))&CCM_PRE52_MUX_A_MASK) +#define CCM_PRE52_EN_A_MASK 0x10000000u +#define CCM_PRE52_EN_A_SHIFT 28 +#define CCM_PRE52_BUSY4_MASK 0x80000000u +#define CCM_PRE52_BUSY4_SHIFT 31 +/* PRE_ROOT52_SET Bit Fields */ +#define CCM_PRE_ROOT52_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT52_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT52_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT52_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT52_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT52_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT52_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT52_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT52_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_MUX_B_SHIFT))&CCM_PRE_ROOT52_SET_MUX_B_MASK) +#define CCM_PRE_ROOT52_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT52_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT52_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT52_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT52_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT52_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT52_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT52_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT52_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT52_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT52_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT52_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT52_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_SET_MUX_A_SHIFT))&CCM_PRE_ROOT52_SET_MUX_A_MASK) +#define CCM_PRE_ROOT52_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT52_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT52_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT52_SET_BUSY4_SHIFT 31 +/* PRE_ROOT52_CLR Bit Fields */ +#define CCM_PRE_ROOT52_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT52_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT52_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT52_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT52_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT52_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT52_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT52_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT52_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT52_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT52_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT52_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT52_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT52_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT52_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT52_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT52_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT52_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT52_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT52_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT52_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT52_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT52_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT52_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT52_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT52_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT52_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT52_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT52_TOG Bit Fields */ +#define CCM_PRE_ROOT52_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT52_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT52_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT52_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT52_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT52_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT52_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT52_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT52_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT52_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT52_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT52_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT52_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT52_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT52_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT52_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT52_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT52_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT52_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT52_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT52_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT52_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT52_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT52_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT52_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT52_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT52_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT52_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT52_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL52 Bit Fields */ +#define CCM_ACCESS_CTRL52_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL52_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL52_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL52_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL52_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL52_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL52_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL52_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL52_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL52_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL52_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL52_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL52_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL52_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL52_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL52_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL52_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL52_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL52_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL52_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL52_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL52_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL52_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL52_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL52_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL52_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL52_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL52_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL52_LOCK_SHIFT 31 +/* ACCESS_CTRL52_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL52_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL52_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL52_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL52_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL52_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL52_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL52_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL52_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL52_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL52_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL52_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL52_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL52_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL52_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL52_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL52_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL52_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL52_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT53 Bit Fields */ +#define CCM_TARGET_ROOT53_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT53_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT53_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_POST_PODF_MASK) +#define CCM_TARGET_ROOT53_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT53_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT53_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT53_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT53_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT53_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT53_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT53_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT53_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT53_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_PRE_PODF_MASK) +#define CCM_TARGET_ROOT53_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT53_MUX_SHIFT 24 +#define CCM_TARGET_ROOT53_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_MUX_SHIFT))&CCM_TARGET_ROOT53_MUX_MASK) +#define CCM_TARGET_ROOT53_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT53_ENABLE_SHIFT 28 +/* TARGET_ROOT53_SET Bit Fields */ +#define CCM_TARGET_ROOT53_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT53_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT53_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT53_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT53_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT53_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT53_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT53_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT53_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT53_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT53_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT53_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT53_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT53_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT53_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT53_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_SET_MUX_SHIFT))&CCM_TARGET_ROOT53_SET_MUX_MASK) +#define CCM_TARGET_ROOT53_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT53_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT53_CLR Bit Fields */ +#define CCM_TARGET_ROOT53_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT53_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT53_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT53_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT53_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT53_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT53_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT53_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT53_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT53_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT53_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT53_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT53_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_CLR_MUX_SHIFT))&CCM_TARGET_ROOT53_CLR_MUX_MASK) +#define CCM_TARGET_ROOT53_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT53_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT53_TOG Bit Fields */ +#define CCM_TARGET_ROOT53_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT53_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT53_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT53_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT53_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT53_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT53_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT53_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT53_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT53_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT53_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT53_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT53_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT53_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT53_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT53_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT53_TOG_MUX_SHIFT))&CCM_TARGET_ROOT53_TOG_MUX_MASK) +#define CCM_TARGET_ROOT53_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT53_TOG_ENABLE_SHIFT 28 +/* POST53 Bit Fields */ +#define CCM_POST53_POST_PODF_MASK 0x3Fu +#define CCM_POST53_POST_PODF_SHIFT 0 +#define CCM_POST53_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST53_POST_PODF_SHIFT))&CCM_POST53_POST_PODF_MASK) +#define CCM_POST53_BUSY1_MASK 0x80u +#define CCM_POST53_BUSY1_SHIFT 7 +#define CCM_POST53_AUTO_PODF_MASK 0x700u +#define CCM_POST53_AUTO_PODF_SHIFT 8 +#define CCM_POST53_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST53_AUTO_PODF_SHIFT))&CCM_POST53_AUTO_PODF_MASK) +#define CCM_POST53_AUTO_EN_MASK 0x1000u +#define CCM_POST53_AUTO_EN_SHIFT 12 +#define CCM_POST53_SLOW_MASK 0x8000u +#define CCM_POST53_SLOW_SHIFT 15 +#define CCM_POST53_SELECT_MASK 0x10000000u +#define CCM_POST53_SELECT_SHIFT 28 +#define CCM_POST53_BUSY2_MASK 0x80000000u +#define CCM_POST53_BUSY2_SHIFT 31 +/* POST_ROOT53_SET Bit Fields */ +#define CCM_POST_ROOT53_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT53_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT53_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_SET_POST_PODF_SHIFT))&CCM_POST_ROOT53_SET_POST_PODF_MASK) +#define CCM_POST_ROOT53_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT53_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT53_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT53_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT53_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT53_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT53_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT53_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT53_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT53_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT53_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT53_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT53_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT53_SET_BUSY2_SHIFT 31 +/* POST_ROOT53_CLR Bit Fields */ +#define CCM_POST_ROOT53_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT53_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT53_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT53_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT53_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT53_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT53_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT53_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT53_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT53_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT53_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT53_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT53_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT53_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT53_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT53_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT53_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT53_CLR_BUSY2_SHIFT 31 +/* POST_ROOT53_TOG Bit Fields */ +#define CCM_POST_ROOT53_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT53_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT53_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT53_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT53_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT53_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT53_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT53_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT53_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT53_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT53_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT53_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT53_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT53_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT53_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT53_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT53_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT53_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT53_TOG_BUSY2_SHIFT 31 +/* PRE53 Bit Fields */ +#define CCM_PRE53_PRE_PODF_B_MASK 0x7u +#define CCM_PRE53_PRE_PODF_B_SHIFT 0 +#define CCM_PRE53_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_PRE_PODF_B_SHIFT))&CCM_PRE53_PRE_PODF_B_MASK) +#define CCM_PRE53_BUSY0_MASK 0x8u +#define CCM_PRE53_BUSY0_SHIFT 3 +#define CCM_PRE53_MUX_B_MASK 0x700u +#define CCM_PRE53_MUX_B_SHIFT 8 +#define CCM_PRE53_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_MUX_B_SHIFT))&CCM_PRE53_MUX_B_MASK) +#define CCM_PRE53_EN_B_MASK 0x1000u +#define CCM_PRE53_EN_B_SHIFT 12 +#define CCM_PRE53_BUSY1_MASK 0x8000u +#define CCM_PRE53_BUSY1_SHIFT 15 +#define CCM_PRE53_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE53_PRE_PODF_A_SHIFT 16 +#define CCM_PRE53_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_PRE_PODF_A_SHIFT))&CCM_PRE53_PRE_PODF_A_MASK) +#define CCM_PRE53_BUSY3_MASK 0x80000u +#define CCM_PRE53_BUSY3_SHIFT 19 +#define CCM_PRE53_MUX_A_MASK 0x7000000u +#define CCM_PRE53_MUX_A_SHIFT 24 +#define CCM_PRE53_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE53_MUX_A_SHIFT))&CCM_PRE53_MUX_A_MASK) +#define CCM_PRE53_EN_A_MASK 0x10000000u +#define CCM_PRE53_EN_A_SHIFT 28 +#define CCM_PRE53_BUSY4_MASK 0x80000000u +#define CCM_PRE53_BUSY4_SHIFT 31 +/* PRE_ROOT53_SET Bit Fields */ +#define CCM_PRE_ROOT53_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT53_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT53_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT53_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT53_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT53_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT53_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT53_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT53_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_MUX_B_SHIFT))&CCM_PRE_ROOT53_SET_MUX_B_MASK) +#define CCM_PRE_ROOT53_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT53_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT53_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT53_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT53_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT53_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT53_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT53_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT53_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT53_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT53_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT53_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT53_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_SET_MUX_A_SHIFT))&CCM_PRE_ROOT53_SET_MUX_A_MASK) +#define CCM_PRE_ROOT53_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT53_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT53_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT53_SET_BUSY4_SHIFT 31 +/* PRE_ROOT53_CLR Bit Fields */ +#define CCM_PRE_ROOT53_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT53_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT53_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT53_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT53_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT53_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT53_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT53_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT53_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT53_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT53_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT53_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT53_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT53_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT53_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT53_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT53_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT53_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT53_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT53_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT53_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT53_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT53_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT53_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT53_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT53_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT53_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT53_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT53_TOG Bit Fields */ +#define CCM_PRE_ROOT53_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT53_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT53_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT53_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT53_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT53_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT53_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT53_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT53_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT53_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT53_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT53_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT53_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT53_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT53_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT53_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT53_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT53_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT53_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT53_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT53_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT53_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT53_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT53_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT53_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT53_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT53_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT53_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT53_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL53 Bit Fields */ +#define CCM_ACCESS_CTRL53_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL53_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL53_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL53_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL53_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL53_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL53_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL53_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL53_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL53_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL53_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL53_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL53_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL53_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL53_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL53_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL53_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL53_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL53_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL53_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL53_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL53_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL53_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL53_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL53_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL53_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL53_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL53_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL53_LOCK_SHIFT 31 +/* ACCESS_CTRL53_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL53_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL53_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL53_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL53_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL53_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL53_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL53_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL53_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL53_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL53_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL53_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL53_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL53_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL53_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL53_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL53_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL53_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL53_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT54 Bit Fields */ +#define CCM_TARGET_ROOT54_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT54_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT54_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_POST_PODF_MASK) +#define CCM_TARGET_ROOT54_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT54_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT54_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT54_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT54_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT54_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT54_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT54_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT54_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT54_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_PRE_PODF_MASK) +#define CCM_TARGET_ROOT54_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT54_MUX_SHIFT 24 +#define CCM_TARGET_ROOT54_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_MUX_SHIFT))&CCM_TARGET_ROOT54_MUX_MASK) +#define CCM_TARGET_ROOT54_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT54_ENABLE_SHIFT 28 +/* TARGET_ROOT54_SET Bit Fields */ +#define CCM_TARGET_ROOT54_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT54_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT54_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT54_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT54_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT54_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT54_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT54_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT54_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT54_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT54_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT54_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT54_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT54_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT54_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT54_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_SET_MUX_SHIFT))&CCM_TARGET_ROOT54_SET_MUX_MASK) +#define CCM_TARGET_ROOT54_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT54_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT54_CLR Bit Fields */ +#define CCM_TARGET_ROOT54_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT54_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT54_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT54_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT54_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT54_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT54_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT54_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT54_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT54_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT54_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT54_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT54_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_CLR_MUX_SHIFT))&CCM_TARGET_ROOT54_CLR_MUX_MASK) +#define CCM_TARGET_ROOT54_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT54_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT54_TOG Bit Fields */ +#define CCM_TARGET_ROOT54_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT54_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT54_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT54_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT54_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT54_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT54_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT54_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT54_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT54_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT54_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT54_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT54_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT54_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT54_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT54_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT54_TOG_MUX_SHIFT))&CCM_TARGET_ROOT54_TOG_MUX_MASK) +#define CCM_TARGET_ROOT54_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT54_TOG_ENABLE_SHIFT 28 +/* POST54 Bit Fields */ +#define CCM_POST54_POST_PODF_MASK 0x3Fu +#define CCM_POST54_POST_PODF_SHIFT 0 +#define CCM_POST54_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST54_POST_PODF_SHIFT))&CCM_POST54_POST_PODF_MASK) +#define CCM_POST54_BUSY1_MASK 0x80u +#define CCM_POST54_BUSY1_SHIFT 7 +#define CCM_POST54_AUTO_PODF_MASK 0x700u +#define CCM_POST54_AUTO_PODF_SHIFT 8 +#define CCM_POST54_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST54_AUTO_PODF_SHIFT))&CCM_POST54_AUTO_PODF_MASK) +#define CCM_POST54_AUTO_EN_MASK 0x1000u +#define CCM_POST54_AUTO_EN_SHIFT 12 +#define CCM_POST54_SLOW_MASK 0x8000u +#define CCM_POST54_SLOW_SHIFT 15 +#define CCM_POST54_SELECT_MASK 0x10000000u +#define CCM_POST54_SELECT_SHIFT 28 +#define CCM_POST54_BUSY2_MASK 0x80000000u +#define CCM_POST54_BUSY2_SHIFT 31 +/* POST_ROOT54_SET Bit Fields */ +#define CCM_POST_ROOT54_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT54_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT54_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_SET_POST_PODF_SHIFT))&CCM_POST_ROOT54_SET_POST_PODF_MASK) +#define CCM_POST_ROOT54_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT54_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT54_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT54_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT54_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT54_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT54_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT54_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT54_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT54_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT54_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT54_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT54_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT54_SET_BUSY2_SHIFT 31 +/* POST_ROOT54_CLR Bit Fields */ +#define CCM_POST_ROOT54_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT54_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT54_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT54_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT54_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT54_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT54_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT54_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT54_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT54_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT54_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT54_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT54_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT54_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT54_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT54_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT54_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT54_CLR_BUSY2_SHIFT 31 +/* POST_ROOT54_TOG Bit Fields */ +#define CCM_POST_ROOT54_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT54_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT54_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT54_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT54_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT54_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT54_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT54_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT54_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT54_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT54_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT54_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT54_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT54_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT54_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT54_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT54_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT54_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT54_TOG_BUSY2_SHIFT 31 +/* PRE54 Bit Fields */ +#define CCM_PRE54_PRE_PODF_B_MASK 0x7u +#define CCM_PRE54_PRE_PODF_B_SHIFT 0 +#define CCM_PRE54_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_PRE_PODF_B_SHIFT))&CCM_PRE54_PRE_PODF_B_MASK) +#define CCM_PRE54_BUSY0_MASK 0x8u +#define CCM_PRE54_BUSY0_SHIFT 3 +#define CCM_PRE54_MUX_B_MASK 0x700u +#define CCM_PRE54_MUX_B_SHIFT 8 +#define CCM_PRE54_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_MUX_B_SHIFT))&CCM_PRE54_MUX_B_MASK) +#define CCM_PRE54_EN_B_MASK 0x1000u +#define CCM_PRE54_EN_B_SHIFT 12 +#define CCM_PRE54_BUSY1_MASK 0x8000u +#define CCM_PRE54_BUSY1_SHIFT 15 +#define CCM_PRE54_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE54_PRE_PODF_A_SHIFT 16 +#define CCM_PRE54_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_PRE_PODF_A_SHIFT))&CCM_PRE54_PRE_PODF_A_MASK) +#define CCM_PRE54_BUSY3_MASK 0x80000u +#define CCM_PRE54_BUSY3_SHIFT 19 +#define CCM_PRE54_MUX_A_MASK 0x7000000u +#define CCM_PRE54_MUX_A_SHIFT 24 +#define CCM_PRE54_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE54_MUX_A_SHIFT))&CCM_PRE54_MUX_A_MASK) +#define CCM_PRE54_EN_A_MASK 0x10000000u +#define CCM_PRE54_EN_A_SHIFT 28 +#define CCM_PRE54_BUSY4_MASK 0x80000000u +#define CCM_PRE54_BUSY4_SHIFT 31 +/* PRE_ROOT54_SET Bit Fields */ +#define CCM_PRE_ROOT54_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT54_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT54_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT54_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT54_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT54_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT54_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT54_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT54_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_MUX_B_SHIFT))&CCM_PRE_ROOT54_SET_MUX_B_MASK) +#define CCM_PRE_ROOT54_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT54_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT54_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT54_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT54_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT54_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT54_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT54_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT54_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT54_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT54_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT54_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT54_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_SET_MUX_A_SHIFT))&CCM_PRE_ROOT54_SET_MUX_A_MASK) +#define CCM_PRE_ROOT54_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT54_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT54_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT54_SET_BUSY4_SHIFT 31 +/* PRE_ROOT54_CLR Bit Fields */ +#define CCM_PRE_ROOT54_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT54_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT54_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT54_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT54_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT54_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT54_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT54_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT54_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT54_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT54_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT54_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT54_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT54_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT54_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT54_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT54_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT54_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT54_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT54_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT54_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT54_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT54_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT54_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT54_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT54_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT54_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT54_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT54_TOG Bit Fields */ +#define CCM_PRE_ROOT54_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT54_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT54_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT54_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT54_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT54_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT54_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT54_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT54_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT54_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT54_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT54_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT54_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT54_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT54_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT54_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT54_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT54_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT54_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT54_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT54_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT54_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT54_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT54_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT54_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT54_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT54_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT54_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT54_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL54 Bit Fields */ +#define CCM_ACCESS_CTRL54_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL54_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL54_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL54_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL54_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL54_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL54_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL54_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL54_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL54_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL54_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL54_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL54_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL54_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL54_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL54_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL54_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL54_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL54_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL54_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL54_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL54_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL54_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL54_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL54_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL54_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL54_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL54_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL54_LOCK_SHIFT 31 +/* ACCESS_CTRL54_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL54_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL54_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL54_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL54_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL54_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL54_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL54_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL54_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL54_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL54_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL54_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL54_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL54_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL54_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL54_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL54_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL54_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL54_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT55 Bit Fields */ +#define CCM_TARGET_ROOT55_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT55_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT55_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_POST_PODF_MASK) +#define CCM_TARGET_ROOT55_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT55_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT55_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT55_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT55_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT55_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT55_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT55_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT55_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT55_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_PRE_PODF_MASK) +#define CCM_TARGET_ROOT55_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT55_MUX_SHIFT 24 +#define CCM_TARGET_ROOT55_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_MUX_SHIFT))&CCM_TARGET_ROOT55_MUX_MASK) +#define CCM_TARGET_ROOT55_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT55_ENABLE_SHIFT 28 +/* TARGET_ROOT55_SET Bit Fields */ +#define CCM_TARGET_ROOT55_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT55_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT55_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT55_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT55_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT55_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT55_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT55_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT55_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT55_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT55_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT55_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT55_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT55_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT55_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT55_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_SET_MUX_SHIFT))&CCM_TARGET_ROOT55_SET_MUX_MASK) +#define CCM_TARGET_ROOT55_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT55_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT55_CLR Bit Fields */ +#define CCM_TARGET_ROOT55_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT55_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT55_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT55_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT55_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT55_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT55_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT55_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT55_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT55_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT55_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT55_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT55_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_CLR_MUX_SHIFT))&CCM_TARGET_ROOT55_CLR_MUX_MASK) +#define CCM_TARGET_ROOT55_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT55_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT55_TOG Bit Fields */ +#define CCM_TARGET_ROOT55_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT55_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT55_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT55_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT55_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT55_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT55_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT55_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT55_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT55_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT55_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT55_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT55_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT55_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT55_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT55_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT55_TOG_MUX_SHIFT))&CCM_TARGET_ROOT55_TOG_MUX_MASK) +#define CCM_TARGET_ROOT55_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT55_TOG_ENABLE_SHIFT 28 +/* POST55 Bit Fields */ +#define CCM_POST55_POST_PODF_MASK 0x3Fu +#define CCM_POST55_POST_PODF_SHIFT 0 +#define CCM_POST55_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST55_POST_PODF_SHIFT))&CCM_POST55_POST_PODF_MASK) +#define CCM_POST55_BUSY1_MASK 0x80u +#define CCM_POST55_BUSY1_SHIFT 7 +#define CCM_POST55_AUTO_PODF_MASK 0x700u +#define CCM_POST55_AUTO_PODF_SHIFT 8 +#define CCM_POST55_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST55_AUTO_PODF_SHIFT))&CCM_POST55_AUTO_PODF_MASK) +#define CCM_POST55_AUTO_EN_MASK 0x1000u +#define CCM_POST55_AUTO_EN_SHIFT 12 +#define CCM_POST55_SLOW_MASK 0x8000u +#define CCM_POST55_SLOW_SHIFT 15 +#define CCM_POST55_SELECT_MASK 0x10000000u +#define CCM_POST55_SELECT_SHIFT 28 +#define CCM_POST55_BUSY2_MASK 0x80000000u +#define CCM_POST55_BUSY2_SHIFT 31 +/* POST_ROOT55_SET Bit Fields */ +#define CCM_POST_ROOT55_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT55_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT55_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_SET_POST_PODF_SHIFT))&CCM_POST_ROOT55_SET_POST_PODF_MASK) +#define CCM_POST_ROOT55_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT55_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT55_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT55_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT55_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT55_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT55_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT55_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT55_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT55_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT55_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT55_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT55_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT55_SET_BUSY2_SHIFT 31 +/* POST_ROOT55_CLR Bit Fields */ +#define CCM_POST_ROOT55_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT55_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT55_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT55_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT55_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT55_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT55_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT55_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT55_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT55_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT55_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT55_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT55_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT55_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT55_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT55_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT55_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT55_CLR_BUSY2_SHIFT 31 +/* POST_ROOT55_TOG Bit Fields */ +#define CCM_POST_ROOT55_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT55_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT55_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT55_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT55_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT55_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT55_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT55_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT55_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT55_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT55_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT55_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT55_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT55_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT55_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT55_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT55_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT55_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT55_TOG_BUSY2_SHIFT 31 +/* PRE55 Bit Fields */ +#define CCM_PRE55_PRE_PODF_B_MASK 0x7u +#define CCM_PRE55_PRE_PODF_B_SHIFT 0 +#define CCM_PRE55_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_PRE_PODF_B_SHIFT))&CCM_PRE55_PRE_PODF_B_MASK) +#define CCM_PRE55_BUSY0_MASK 0x8u +#define CCM_PRE55_BUSY0_SHIFT 3 +#define CCM_PRE55_MUX_B_MASK 0x700u +#define CCM_PRE55_MUX_B_SHIFT 8 +#define CCM_PRE55_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_MUX_B_SHIFT))&CCM_PRE55_MUX_B_MASK) +#define CCM_PRE55_EN_B_MASK 0x1000u +#define CCM_PRE55_EN_B_SHIFT 12 +#define CCM_PRE55_BUSY1_MASK 0x8000u +#define CCM_PRE55_BUSY1_SHIFT 15 +#define CCM_PRE55_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE55_PRE_PODF_A_SHIFT 16 +#define CCM_PRE55_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_PRE_PODF_A_SHIFT))&CCM_PRE55_PRE_PODF_A_MASK) +#define CCM_PRE55_BUSY3_MASK 0x80000u +#define CCM_PRE55_BUSY3_SHIFT 19 +#define CCM_PRE55_MUX_A_MASK 0x7000000u +#define CCM_PRE55_MUX_A_SHIFT 24 +#define CCM_PRE55_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE55_MUX_A_SHIFT))&CCM_PRE55_MUX_A_MASK) +#define CCM_PRE55_EN_A_MASK 0x10000000u +#define CCM_PRE55_EN_A_SHIFT 28 +#define CCM_PRE55_BUSY4_MASK 0x80000000u +#define CCM_PRE55_BUSY4_SHIFT 31 +/* PRE_ROOT55_SET Bit Fields */ +#define CCM_PRE_ROOT55_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT55_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT55_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT55_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT55_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT55_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT55_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT55_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT55_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_MUX_B_SHIFT))&CCM_PRE_ROOT55_SET_MUX_B_MASK) +#define CCM_PRE_ROOT55_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT55_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT55_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT55_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT55_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT55_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT55_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT55_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT55_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT55_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT55_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT55_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT55_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_SET_MUX_A_SHIFT))&CCM_PRE_ROOT55_SET_MUX_A_MASK) +#define CCM_PRE_ROOT55_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT55_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT55_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT55_SET_BUSY4_SHIFT 31 +/* PRE_ROOT55_CLR Bit Fields */ +#define CCM_PRE_ROOT55_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT55_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT55_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT55_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT55_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT55_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT55_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT55_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT55_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT55_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT55_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT55_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT55_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT55_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT55_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT55_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT55_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT55_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT55_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT55_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT55_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT55_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT55_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT55_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT55_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT55_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT55_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT55_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT55_TOG Bit Fields */ +#define CCM_PRE_ROOT55_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT55_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT55_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT55_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT55_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT55_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT55_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT55_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT55_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT55_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT55_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT55_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT55_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT55_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT55_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT55_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT55_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT55_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT55_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT55_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT55_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT55_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT55_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT55_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT55_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT55_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT55_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT55_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT55_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL55 Bit Fields */ +#define CCM_ACCESS_CTRL55_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL55_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL55_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL55_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL55_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL55_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL55_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL55_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL55_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL55_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL55_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL55_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL55_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL55_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL55_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL55_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL55_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL55_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL55_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL55_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL55_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL55_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL55_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL55_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL55_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL55_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL55_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL55_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL55_LOCK_SHIFT 31 +/* ACCESS_CTRL55_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL55_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL55_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL55_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL55_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL55_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL55_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL55_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL55_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL55_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL55_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL55_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL55_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL55_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL55_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL55_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL55_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL55_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL55_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT56 Bit Fields */ +#define CCM_TARGET_ROOT56_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT56_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT56_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_POST_PODF_MASK) +#define CCM_TARGET_ROOT56_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT56_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT56_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT56_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT56_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT56_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT56_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT56_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT56_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT56_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_PRE_PODF_MASK) +#define CCM_TARGET_ROOT56_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT56_MUX_SHIFT 24 +#define CCM_TARGET_ROOT56_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_MUX_SHIFT))&CCM_TARGET_ROOT56_MUX_MASK) +#define CCM_TARGET_ROOT56_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT56_ENABLE_SHIFT 28 +/* TARGET_ROOT56_SET Bit Fields */ +#define CCM_TARGET_ROOT56_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT56_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT56_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT56_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT56_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT56_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT56_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT56_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT56_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT56_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT56_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT56_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT56_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT56_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT56_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT56_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_SET_MUX_SHIFT))&CCM_TARGET_ROOT56_SET_MUX_MASK) +#define CCM_TARGET_ROOT56_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT56_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT56_CLR Bit Fields */ +#define CCM_TARGET_ROOT56_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT56_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT56_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT56_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT56_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT56_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT56_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT56_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT56_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT56_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT56_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT56_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT56_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_CLR_MUX_SHIFT))&CCM_TARGET_ROOT56_CLR_MUX_MASK) +#define CCM_TARGET_ROOT56_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT56_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT56_TOG Bit Fields */ +#define CCM_TARGET_ROOT56_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT56_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT56_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT56_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT56_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT56_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT56_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT56_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT56_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT56_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT56_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT56_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT56_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT56_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT56_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT56_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT56_TOG_MUX_SHIFT))&CCM_TARGET_ROOT56_TOG_MUX_MASK) +#define CCM_TARGET_ROOT56_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT56_TOG_ENABLE_SHIFT 28 +/* POST56 Bit Fields */ +#define CCM_POST56_POST_PODF_MASK 0x3Fu +#define CCM_POST56_POST_PODF_SHIFT 0 +#define CCM_POST56_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST56_POST_PODF_SHIFT))&CCM_POST56_POST_PODF_MASK) +#define CCM_POST56_BUSY1_MASK 0x80u +#define CCM_POST56_BUSY1_SHIFT 7 +#define CCM_POST56_AUTO_PODF_MASK 0x700u +#define CCM_POST56_AUTO_PODF_SHIFT 8 +#define CCM_POST56_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST56_AUTO_PODF_SHIFT))&CCM_POST56_AUTO_PODF_MASK) +#define CCM_POST56_AUTO_EN_MASK 0x1000u +#define CCM_POST56_AUTO_EN_SHIFT 12 +#define CCM_POST56_SLOW_MASK 0x8000u +#define CCM_POST56_SLOW_SHIFT 15 +#define CCM_POST56_SELECT_MASK 0x10000000u +#define CCM_POST56_SELECT_SHIFT 28 +#define CCM_POST56_BUSY2_MASK 0x80000000u +#define CCM_POST56_BUSY2_SHIFT 31 +/* POST_ROOT56_SET Bit Fields */ +#define CCM_POST_ROOT56_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT56_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT56_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_SET_POST_PODF_SHIFT))&CCM_POST_ROOT56_SET_POST_PODF_MASK) +#define CCM_POST_ROOT56_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT56_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT56_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT56_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT56_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT56_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT56_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT56_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT56_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT56_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT56_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT56_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT56_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT56_SET_BUSY2_SHIFT 31 +/* POST_ROOT56_CLR Bit Fields */ +#define CCM_POST_ROOT56_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT56_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT56_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT56_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT56_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT56_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT56_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT56_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT56_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT56_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT56_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT56_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT56_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT56_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT56_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT56_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT56_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT56_CLR_BUSY2_SHIFT 31 +/* POST_ROOT56_TOG Bit Fields */ +#define CCM_POST_ROOT56_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT56_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT56_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT56_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT56_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT56_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT56_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT56_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT56_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT56_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT56_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT56_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT56_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT56_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT56_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT56_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT56_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT56_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT56_TOG_BUSY2_SHIFT 31 +/* PRE56 Bit Fields */ +#define CCM_PRE56_PRE_PODF_B_MASK 0x7u +#define CCM_PRE56_PRE_PODF_B_SHIFT 0 +#define CCM_PRE56_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_PRE_PODF_B_SHIFT))&CCM_PRE56_PRE_PODF_B_MASK) +#define CCM_PRE56_BUSY0_MASK 0x8u +#define CCM_PRE56_BUSY0_SHIFT 3 +#define CCM_PRE56_MUX_B_MASK 0x700u +#define CCM_PRE56_MUX_B_SHIFT 8 +#define CCM_PRE56_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_MUX_B_SHIFT))&CCM_PRE56_MUX_B_MASK) +#define CCM_PRE56_EN_B_MASK 0x1000u +#define CCM_PRE56_EN_B_SHIFT 12 +#define CCM_PRE56_BUSY1_MASK 0x8000u +#define CCM_PRE56_BUSY1_SHIFT 15 +#define CCM_PRE56_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE56_PRE_PODF_A_SHIFT 16 +#define CCM_PRE56_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_PRE_PODF_A_SHIFT))&CCM_PRE56_PRE_PODF_A_MASK) +#define CCM_PRE56_BUSY3_MASK 0x80000u +#define CCM_PRE56_BUSY3_SHIFT 19 +#define CCM_PRE56_MUX_A_MASK 0x7000000u +#define CCM_PRE56_MUX_A_SHIFT 24 +#define CCM_PRE56_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE56_MUX_A_SHIFT))&CCM_PRE56_MUX_A_MASK) +#define CCM_PRE56_EN_A_MASK 0x10000000u +#define CCM_PRE56_EN_A_SHIFT 28 +#define CCM_PRE56_BUSY4_MASK 0x80000000u +#define CCM_PRE56_BUSY4_SHIFT 31 +/* PRE_ROOT56_SET Bit Fields */ +#define CCM_PRE_ROOT56_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT56_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT56_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT56_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT56_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT56_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT56_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT56_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT56_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_MUX_B_SHIFT))&CCM_PRE_ROOT56_SET_MUX_B_MASK) +#define CCM_PRE_ROOT56_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT56_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT56_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT56_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT56_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT56_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT56_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT56_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT56_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT56_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT56_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT56_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT56_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_SET_MUX_A_SHIFT))&CCM_PRE_ROOT56_SET_MUX_A_MASK) +#define CCM_PRE_ROOT56_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT56_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT56_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT56_SET_BUSY4_SHIFT 31 +/* PRE_ROOT56_CLR Bit Fields */ +#define CCM_PRE_ROOT56_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT56_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT56_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT56_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT56_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT56_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT56_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT56_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT56_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT56_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT56_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT56_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT56_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT56_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT56_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT56_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT56_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT56_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT56_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT56_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT56_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT56_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT56_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT56_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT56_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT56_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT56_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT56_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT56_TOG Bit Fields */ +#define CCM_PRE_ROOT56_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT56_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT56_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT56_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT56_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT56_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT56_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT56_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT56_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT56_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT56_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT56_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT56_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT56_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT56_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT56_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT56_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT56_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT56_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT56_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT56_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT56_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT56_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT56_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT56_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT56_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT56_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT56_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT56_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL56 Bit Fields */ +#define CCM_ACCESS_CTRL56_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL56_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL56_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL56_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL56_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL56_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL56_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL56_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL56_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL56_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL56_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL56_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL56_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL56_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL56_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL56_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL56_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL56_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL56_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL56_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL56_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL56_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL56_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL56_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL56_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL56_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL56_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL56_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL56_LOCK_SHIFT 31 +/* ACCESS_CTRL56_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL56_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL56_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL56_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL56_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL56_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL56_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL56_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL56_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL56_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL56_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL56_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL56_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL56_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL56_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL56_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL56_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL56_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL56_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT57 Bit Fields */ +#define CCM_TARGET_ROOT57_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT57_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT57_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_POST_PODF_MASK) +#define CCM_TARGET_ROOT57_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT57_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT57_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT57_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT57_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT57_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT57_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT57_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT57_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT57_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_PRE_PODF_MASK) +#define CCM_TARGET_ROOT57_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT57_MUX_SHIFT 24 +#define CCM_TARGET_ROOT57_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_MUX_SHIFT))&CCM_TARGET_ROOT57_MUX_MASK) +#define CCM_TARGET_ROOT57_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT57_ENABLE_SHIFT 28 +/* TARGET_ROOT57_SET Bit Fields */ +#define CCM_TARGET_ROOT57_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT57_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT57_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT57_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT57_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT57_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT57_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT57_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT57_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT57_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT57_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT57_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT57_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT57_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT57_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT57_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_SET_MUX_SHIFT))&CCM_TARGET_ROOT57_SET_MUX_MASK) +#define CCM_TARGET_ROOT57_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT57_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT57_CLR Bit Fields */ +#define CCM_TARGET_ROOT57_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT57_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT57_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT57_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT57_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT57_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT57_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT57_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT57_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT57_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT57_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT57_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT57_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_CLR_MUX_SHIFT))&CCM_TARGET_ROOT57_CLR_MUX_MASK) +#define CCM_TARGET_ROOT57_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT57_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT57_TOG Bit Fields */ +#define CCM_TARGET_ROOT57_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT57_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT57_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT57_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT57_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT57_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT57_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT57_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT57_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT57_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT57_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT57_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT57_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT57_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT57_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT57_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT57_TOG_MUX_SHIFT))&CCM_TARGET_ROOT57_TOG_MUX_MASK) +#define CCM_TARGET_ROOT57_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT57_TOG_ENABLE_SHIFT 28 +/* POST57 Bit Fields */ +#define CCM_POST57_POST_PODF_MASK 0x3Fu +#define CCM_POST57_POST_PODF_SHIFT 0 +#define CCM_POST57_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST57_POST_PODF_SHIFT))&CCM_POST57_POST_PODF_MASK) +#define CCM_POST57_BUSY1_MASK 0x80u +#define CCM_POST57_BUSY1_SHIFT 7 +#define CCM_POST57_AUTO_PODF_MASK 0x700u +#define CCM_POST57_AUTO_PODF_SHIFT 8 +#define CCM_POST57_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST57_AUTO_PODF_SHIFT))&CCM_POST57_AUTO_PODF_MASK) +#define CCM_POST57_AUTO_EN_MASK 0x1000u +#define CCM_POST57_AUTO_EN_SHIFT 12 +#define CCM_POST57_SLOW_MASK 0x8000u +#define CCM_POST57_SLOW_SHIFT 15 +#define CCM_POST57_SELECT_MASK 0x10000000u +#define CCM_POST57_SELECT_SHIFT 28 +#define CCM_POST57_BUSY2_MASK 0x80000000u +#define CCM_POST57_BUSY2_SHIFT 31 +/* POST_ROOT57_SET Bit Fields */ +#define CCM_POST_ROOT57_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT57_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT57_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_SET_POST_PODF_SHIFT))&CCM_POST_ROOT57_SET_POST_PODF_MASK) +#define CCM_POST_ROOT57_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT57_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT57_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT57_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT57_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT57_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT57_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT57_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT57_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT57_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT57_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT57_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT57_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT57_SET_BUSY2_SHIFT 31 +/* POST_ROOT57_CLR Bit Fields */ +#define CCM_POST_ROOT57_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT57_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT57_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT57_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT57_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT57_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT57_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT57_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT57_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT57_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT57_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT57_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT57_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT57_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT57_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT57_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT57_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT57_CLR_BUSY2_SHIFT 31 +/* POST_ROOT57_TOG Bit Fields */ +#define CCM_POST_ROOT57_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT57_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT57_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT57_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT57_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT57_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT57_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT57_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT57_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT57_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT57_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT57_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT57_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT57_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT57_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT57_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT57_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT57_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT57_TOG_BUSY2_SHIFT 31 +/* PRE57 Bit Fields */ +#define CCM_PRE57_PRE_PODF_B_MASK 0x7u +#define CCM_PRE57_PRE_PODF_B_SHIFT 0 +#define CCM_PRE57_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_PRE_PODF_B_SHIFT))&CCM_PRE57_PRE_PODF_B_MASK) +#define CCM_PRE57_BUSY0_MASK 0x8u +#define CCM_PRE57_BUSY0_SHIFT 3 +#define CCM_PRE57_MUX_B_MASK 0x700u +#define CCM_PRE57_MUX_B_SHIFT 8 +#define CCM_PRE57_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_MUX_B_SHIFT))&CCM_PRE57_MUX_B_MASK) +#define CCM_PRE57_EN_B_MASK 0x1000u +#define CCM_PRE57_EN_B_SHIFT 12 +#define CCM_PRE57_BUSY1_MASK 0x8000u +#define CCM_PRE57_BUSY1_SHIFT 15 +#define CCM_PRE57_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE57_PRE_PODF_A_SHIFT 16 +#define CCM_PRE57_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_PRE_PODF_A_SHIFT))&CCM_PRE57_PRE_PODF_A_MASK) +#define CCM_PRE57_BUSY3_MASK 0x80000u +#define CCM_PRE57_BUSY3_SHIFT 19 +#define CCM_PRE57_MUX_A_MASK 0x7000000u +#define CCM_PRE57_MUX_A_SHIFT 24 +#define CCM_PRE57_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE57_MUX_A_SHIFT))&CCM_PRE57_MUX_A_MASK) +#define CCM_PRE57_EN_A_MASK 0x10000000u +#define CCM_PRE57_EN_A_SHIFT 28 +#define CCM_PRE57_BUSY4_MASK 0x80000000u +#define CCM_PRE57_BUSY4_SHIFT 31 +/* PRE_ROOT57_SET Bit Fields */ +#define CCM_PRE_ROOT57_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT57_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT57_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT57_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT57_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT57_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT57_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT57_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT57_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_MUX_B_SHIFT))&CCM_PRE_ROOT57_SET_MUX_B_MASK) +#define CCM_PRE_ROOT57_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT57_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT57_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT57_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT57_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT57_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT57_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT57_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT57_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT57_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT57_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT57_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT57_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_SET_MUX_A_SHIFT))&CCM_PRE_ROOT57_SET_MUX_A_MASK) +#define CCM_PRE_ROOT57_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT57_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT57_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT57_SET_BUSY4_SHIFT 31 +/* PRE_ROOT57_CLR Bit Fields */ +#define CCM_PRE_ROOT57_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT57_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT57_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT57_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT57_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT57_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT57_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT57_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT57_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT57_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT57_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT57_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT57_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT57_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT57_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT57_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT57_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT57_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT57_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT57_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT57_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT57_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT57_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT57_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT57_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT57_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT57_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT57_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT57_TOG Bit Fields */ +#define CCM_PRE_ROOT57_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT57_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT57_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT57_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT57_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT57_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT57_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT57_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT57_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT57_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT57_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT57_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT57_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT57_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT57_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT57_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT57_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT57_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT57_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT57_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT57_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT57_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT57_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT57_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT57_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT57_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT57_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT57_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT57_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL57 Bit Fields */ +#define CCM_ACCESS_CTRL57_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL57_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL57_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL57_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL57_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL57_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL57_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL57_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL57_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL57_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL57_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL57_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL57_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL57_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL57_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL57_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL57_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL57_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL57_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL57_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL57_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL57_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL57_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL57_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL57_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL57_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL57_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL57_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL57_LOCK_SHIFT 31 +/* ACCESS_CTRL57_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL57_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL57_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL57_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL57_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL57_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL57_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL57_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL57_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL57_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL57_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL57_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL57_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL57_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL57_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL57_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL57_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL57_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL57_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT58 Bit Fields */ +#define CCM_TARGET_ROOT58_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT58_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT58_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_POST_PODF_MASK) +#define CCM_TARGET_ROOT58_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT58_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT58_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT58_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT58_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT58_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT58_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT58_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT58_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT58_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_PRE_PODF_MASK) +#define CCM_TARGET_ROOT58_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT58_MUX_SHIFT 24 +#define CCM_TARGET_ROOT58_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_MUX_SHIFT))&CCM_TARGET_ROOT58_MUX_MASK) +#define CCM_TARGET_ROOT58_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT58_ENABLE_SHIFT 28 +/* TARGET_ROOT58_SET Bit Fields */ +#define CCM_TARGET_ROOT58_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT58_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT58_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT58_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT58_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT58_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT58_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT58_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT58_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT58_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT58_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT58_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT58_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT58_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT58_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT58_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_SET_MUX_SHIFT))&CCM_TARGET_ROOT58_SET_MUX_MASK) +#define CCM_TARGET_ROOT58_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT58_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT58_CLR Bit Fields */ +#define CCM_TARGET_ROOT58_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT58_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT58_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT58_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT58_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT58_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT58_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT58_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT58_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT58_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT58_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT58_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT58_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_CLR_MUX_SHIFT))&CCM_TARGET_ROOT58_CLR_MUX_MASK) +#define CCM_TARGET_ROOT58_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT58_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT58_TOG Bit Fields */ +#define CCM_TARGET_ROOT58_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT58_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT58_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT58_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT58_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT58_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT58_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT58_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT58_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT58_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT58_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT58_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT58_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT58_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT58_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT58_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT58_TOG_MUX_SHIFT))&CCM_TARGET_ROOT58_TOG_MUX_MASK) +#define CCM_TARGET_ROOT58_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT58_TOG_ENABLE_SHIFT 28 +/* POST58 Bit Fields */ +#define CCM_POST58_POST_PODF_MASK 0x3Fu +#define CCM_POST58_POST_PODF_SHIFT 0 +#define CCM_POST58_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST58_POST_PODF_SHIFT))&CCM_POST58_POST_PODF_MASK) +#define CCM_POST58_BUSY1_MASK 0x80u +#define CCM_POST58_BUSY1_SHIFT 7 +#define CCM_POST58_AUTO_PODF_MASK 0x700u +#define CCM_POST58_AUTO_PODF_SHIFT 8 +#define CCM_POST58_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST58_AUTO_PODF_SHIFT))&CCM_POST58_AUTO_PODF_MASK) +#define CCM_POST58_AUTO_EN_MASK 0x1000u +#define CCM_POST58_AUTO_EN_SHIFT 12 +#define CCM_POST58_SLOW_MASK 0x8000u +#define CCM_POST58_SLOW_SHIFT 15 +#define CCM_POST58_SELECT_MASK 0x10000000u +#define CCM_POST58_SELECT_SHIFT 28 +#define CCM_POST58_BUSY2_MASK 0x80000000u +#define CCM_POST58_BUSY2_SHIFT 31 +/* POST_ROOT58_SET Bit Fields */ +#define CCM_POST_ROOT58_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT58_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT58_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_SET_POST_PODF_SHIFT))&CCM_POST_ROOT58_SET_POST_PODF_MASK) +#define CCM_POST_ROOT58_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT58_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT58_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT58_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT58_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT58_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT58_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT58_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT58_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT58_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT58_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT58_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT58_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT58_SET_BUSY2_SHIFT 31 +/* POST_ROOT58_CLR Bit Fields */ +#define CCM_POST_ROOT58_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT58_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT58_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT58_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT58_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT58_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT58_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT58_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT58_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT58_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT58_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT58_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT58_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT58_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT58_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT58_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT58_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT58_CLR_BUSY2_SHIFT 31 +/* POST_ROOT58_TOG Bit Fields */ +#define CCM_POST_ROOT58_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT58_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT58_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT58_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT58_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT58_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT58_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT58_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT58_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT58_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT58_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT58_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT58_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT58_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT58_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT58_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT58_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT58_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT58_TOG_BUSY2_SHIFT 31 +/* PRE58 Bit Fields */ +#define CCM_PRE58_PRE_PODF_B_MASK 0x7u +#define CCM_PRE58_PRE_PODF_B_SHIFT 0 +#define CCM_PRE58_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_PRE_PODF_B_SHIFT))&CCM_PRE58_PRE_PODF_B_MASK) +#define CCM_PRE58_BUSY0_MASK 0x8u +#define CCM_PRE58_BUSY0_SHIFT 3 +#define CCM_PRE58_MUX_B_MASK 0x700u +#define CCM_PRE58_MUX_B_SHIFT 8 +#define CCM_PRE58_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_MUX_B_SHIFT))&CCM_PRE58_MUX_B_MASK) +#define CCM_PRE58_EN_B_MASK 0x1000u +#define CCM_PRE58_EN_B_SHIFT 12 +#define CCM_PRE58_BUSY1_MASK 0x8000u +#define CCM_PRE58_BUSY1_SHIFT 15 +#define CCM_PRE58_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE58_PRE_PODF_A_SHIFT 16 +#define CCM_PRE58_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_PRE_PODF_A_SHIFT))&CCM_PRE58_PRE_PODF_A_MASK) +#define CCM_PRE58_BUSY3_MASK 0x80000u +#define CCM_PRE58_BUSY3_SHIFT 19 +#define CCM_PRE58_MUX_A_MASK 0x7000000u +#define CCM_PRE58_MUX_A_SHIFT 24 +#define CCM_PRE58_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE58_MUX_A_SHIFT))&CCM_PRE58_MUX_A_MASK) +#define CCM_PRE58_EN_A_MASK 0x10000000u +#define CCM_PRE58_EN_A_SHIFT 28 +#define CCM_PRE58_BUSY4_MASK 0x80000000u +#define CCM_PRE58_BUSY4_SHIFT 31 +/* PRE_ROOT58_SET Bit Fields */ +#define CCM_PRE_ROOT58_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT58_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT58_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT58_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT58_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT58_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT58_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT58_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT58_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_MUX_B_SHIFT))&CCM_PRE_ROOT58_SET_MUX_B_MASK) +#define CCM_PRE_ROOT58_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT58_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT58_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT58_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT58_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT58_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT58_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT58_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT58_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT58_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT58_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT58_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT58_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_SET_MUX_A_SHIFT))&CCM_PRE_ROOT58_SET_MUX_A_MASK) +#define CCM_PRE_ROOT58_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT58_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT58_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT58_SET_BUSY4_SHIFT 31 +/* PRE_ROOT58_CLR Bit Fields */ +#define CCM_PRE_ROOT58_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT58_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT58_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT58_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT58_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT58_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT58_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT58_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT58_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT58_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT58_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT58_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT58_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT58_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT58_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT58_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT58_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT58_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT58_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT58_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT58_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT58_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT58_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT58_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT58_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT58_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT58_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT58_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT58_TOG Bit Fields */ +#define CCM_PRE_ROOT58_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT58_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT58_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT58_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT58_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT58_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT58_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT58_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT58_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT58_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT58_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT58_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT58_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT58_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT58_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT58_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT58_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT58_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT58_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT58_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT58_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT58_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT58_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT58_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT58_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT58_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT58_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT58_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT58_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL58 Bit Fields */ +#define CCM_ACCESS_CTRL58_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL58_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL58_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL58_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL58_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL58_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL58_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL58_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL58_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL58_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL58_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL58_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL58_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL58_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL58_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL58_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL58_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL58_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL58_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL58_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL58_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL58_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL58_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL58_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL58_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL58_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL58_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL58_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL58_LOCK_SHIFT 31 +/* ACCESS_CTRL58_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL58_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL58_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL58_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL58_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL58_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL58_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL58_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL58_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL58_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL58_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL58_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL58_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL58_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL58_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL58_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL58_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL58_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL58_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT59 Bit Fields */ +#define CCM_TARGET_ROOT59_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT59_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT59_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_POST_PODF_MASK) +#define CCM_TARGET_ROOT59_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT59_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT59_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT59_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT59_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT59_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT59_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT59_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT59_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT59_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_PRE_PODF_MASK) +#define CCM_TARGET_ROOT59_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT59_MUX_SHIFT 24 +#define CCM_TARGET_ROOT59_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_MUX_SHIFT))&CCM_TARGET_ROOT59_MUX_MASK) +#define CCM_TARGET_ROOT59_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT59_ENABLE_SHIFT 28 +/* TARGET_ROOT59_SET Bit Fields */ +#define CCM_TARGET_ROOT59_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT59_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT59_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT59_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT59_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT59_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT59_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT59_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT59_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT59_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT59_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT59_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT59_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT59_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT59_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT59_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_SET_MUX_SHIFT))&CCM_TARGET_ROOT59_SET_MUX_MASK) +#define CCM_TARGET_ROOT59_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT59_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT59_CLR Bit Fields */ +#define CCM_TARGET_ROOT59_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT59_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT59_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT59_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT59_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT59_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT59_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT59_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT59_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT59_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT59_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT59_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT59_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_CLR_MUX_SHIFT))&CCM_TARGET_ROOT59_CLR_MUX_MASK) +#define CCM_TARGET_ROOT59_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT59_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT59_TOG Bit Fields */ +#define CCM_TARGET_ROOT59_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT59_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT59_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT59_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT59_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT59_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT59_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT59_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT59_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT59_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT59_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT59_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT59_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT59_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT59_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT59_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT59_TOG_MUX_SHIFT))&CCM_TARGET_ROOT59_TOG_MUX_MASK) +#define CCM_TARGET_ROOT59_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT59_TOG_ENABLE_SHIFT 28 +/* POST59 Bit Fields */ +#define CCM_POST59_POST_PODF_MASK 0x3Fu +#define CCM_POST59_POST_PODF_SHIFT 0 +#define CCM_POST59_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST59_POST_PODF_SHIFT))&CCM_POST59_POST_PODF_MASK) +#define CCM_POST59_BUSY1_MASK 0x80u +#define CCM_POST59_BUSY1_SHIFT 7 +#define CCM_POST59_AUTO_PODF_MASK 0x700u +#define CCM_POST59_AUTO_PODF_SHIFT 8 +#define CCM_POST59_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST59_AUTO_PODF_SHIFT))&CCM_POST59_AUTO_PODF_MASK) +#define CCM_POST59_AUTO_EN_MASK 0x1000u +#define CCM_POST59_AUTO_EN_SHIFT 12 +#define CCM_POST59_SLOW_MASK 0x8000u +#define CCM_POST59_SLOW_SHIFT 15 +#define CCM_POST59_SELECT_MASK 0x10000000u +#define CCM_POST59_SELECT_SHIFT 28 +#define CCM_POST59_BUSY2_MASK 0x80000000u +#define CCM_POST59_BUSY2_SHIFT 31 +/* POST_ROOT59_SET Bit Fields */ +#define CCM_POST_ROOT59_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT59_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT59_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_SET_POST_PODF_SHIFT))&CCM_POST_ROOT59_SET_POST_PODF_MASK) +#define CCM_POST_ROOT59_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT59_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT59_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT59_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT59_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT59_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT59_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT59_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT59_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT59_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT59_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT59_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT59_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT59_SET_BUSY2_SHIFT 31 +/* POST_ROOT59_CLR Bit Fields */ +#define CCM_POST_ROOT59_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT59_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT59_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT59_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT59_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT59_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT59_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT59_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT59_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT59_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT59_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT59_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT59_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT59_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT59_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT59_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT59_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT59_CLR_BUSY2_SHIFT 31 +/* POST_ROOT59_TOG Bit Fields */ +#define CCM_POST_ROOT59_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT59_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT59_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT59_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT59_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT59_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT59_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT59_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT59_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT59_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT59_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT59_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT59_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT59_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT59_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT59_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT59_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT59_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT59_TOG_BUSY2_SHIFT 31 +/* PRE59 Bit Fields */ +#define CCM_PRE59_PRE_PODF_B_MASK 0x7u +#define CCM_PRE59_PRE_PODF_B_SHIFT 0 +#define CCM_PRE59_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_PRE_PODF_B_SHIFT))&CCM_PRE59_PRE_PODF_B_MASK) +#define CCM_PRE59_BUSY0_MASK 0x8u +#define CCM_PRE59_BUSY0_SHIFT 3 +#define CCM_PRE59_MUX_B_MASK 0x700u +#define CCM_PRE59_MUX_B_SHIFT 8 +#define CCM_PRE59_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_MUX_B_SHIFT))&CCM_PRE59_MUX_B_MASK) +#define CCM_PRE59_EN_B_MASK 0x1000u +#define CCM_PRE59_EN_B_SHIFT 12 +#define CCM_PRE59_BUSY1_MASK 0x8000u +#define CCM_PRE59_BUSY1_SHIFT 15 +#define CCM_PRE59_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE59_PRE_PODF_A_SHIFT 16 +#define CCM_PRE59_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_PRE_PODF_A_SHIFT))&CCM_PRE59_PRE_PODF_A_MASK) +#define CCM_PRE59_BUSY3_MASK 0x80000u +#define CCM_PRE59_BUSY3_SHIFT 19 +#define CCM_PRE59_MUX_A_MASK 0x7000000u +#define CCM_PRE59_MUX_A_SHIFT 24 +#define CCM_PRE59_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE59_MUX_A_SHIFT))&CCM_PRE59_MUX_A_MASK) +#define CCM_PRE59_EN_A_MASK 0x10000000u +#define CCM_PRE59_EN_A_SHIFT 28 +#define CCM_PRE59_BUSY4_MASK 0x80000000u +#define CCM_PRE59_BUSY4_SHIFT 31 +/* PRE_ROOT59_SET Bit Fields */ +#define CCM_PRE_ROOT59_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT59_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT59_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT59_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT59_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT59_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT59_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT59_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT59_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_MUX_B_SHIFT))&CCM_PRE_ROOT59_SET_MUX_B_MASK) +#define CCM_PRE_ROOT59_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT59_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT59_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT59_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT59_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT59_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT59_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT59_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT59_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT59_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT59_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT59_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT59_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_SET_MUX_A_SHIFT))&CCM_PRE_ROOT59_SET_MUX_A_MASK) +#define CCM_PRE_ROOT59_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT59_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT59_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT59_SET_BUSY4_SHIFT 31 +/* PRE_ROOT59_CLR Bit Fields */ +#define CCM_PRE_ROOT59_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT59_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT59_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT59_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT59_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT59_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT59_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT59_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT59_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT59_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT59_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT59_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT59_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT59_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT59_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT59_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT59_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT59_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT59_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT59_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT59_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT59_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT59_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT59_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT59_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT59_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT59_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT59_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT59_TOG Bit Fields */ +#define CCM_PRE_ROOT59_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT59_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT59_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT59_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT59_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT59_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT59_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT59_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT59_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT59_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT59_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT59_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT59_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT59_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT59_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT59_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT59_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT59_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT59_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT59_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT59_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT59_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT59_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT59_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT59_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT59_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT59_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT59_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT59_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL59 Bit Fields */ +#define CCM_ACCESS_CTRL59_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL59_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL59_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL59_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL59_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL59_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL59_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL59_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL59_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL59_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL59_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL59_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL59_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL59_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL59_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL59_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL59_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL59_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL59_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL59_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL59_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL59_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL59_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL59_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL59_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL59_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL59_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL59_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL59_LOCK_SHIFT 31 +/* ACCESS_CTRL59_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL59_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL59_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL59_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL59_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL59_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL59_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL59_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL59_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL59_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL59_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL59_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL59_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL59_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL59_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL59_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL59_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL59_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL59_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT60 Bit Fields */ +#define CCM_TARGET_ROOT60_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT60_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT60_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_POST_PODF_MASK) +#define CCM_TARGET_ROOT60_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT60_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT60_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT60_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT60_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT60_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT60_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT60_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT60_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT60_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_PRE_PODF_MASK) +#define CCM_TARGET_ROOT60_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT60_MUX_SHIFT 24 +#define CCM_TARGET_ROOT60_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_MUX_SHIFT))&CCM_TARGET_ROOT60_MUX_MASK) +#define CCM_TARGET_ROOT60_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT60_ENABLE_SHIFT 28 +/* TARGET_ROOT60_SET Bit Fields */ +#define CCM_TARGET_ROOT60_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT60_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT60_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT60_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT60_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT60_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT60_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT60_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT60_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT60_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT60_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT60_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT60_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT60_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT60_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT60_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_SET_MUX_SHIFT))&CCM_TARGET_ROOT60_SET_MUX_MASK) +#define CCM_TARGET_ROOT60_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT60_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT60_CLR Bit Fields */ +#define CCM_TARGET_ROOT60_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT60_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT60_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT60_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT60_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT60_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT60_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT60_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT60_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT60_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT60_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT60_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT60_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_CLR_MUX_SHIFT))&CCM_TARGET_ROOT60_CLR_MUX_MASK) +#define CCM_TARGET_ROOT60_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT60_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT60_TOG Bit Fields */ +#define CCM_TARGET_ROOT60_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT60_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT60_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT60_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT60_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT60_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT60_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT60_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT60_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT60_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT60_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT60_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT60_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT60_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT60_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT60_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT60_TOG_MUX_SHIFT))&CCM_TARGET_ROOT60_TOG_MUX_MASK) +#define CCM_TARGET_ROOT60_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT60_TOG_ENABLE_SHIFT 28 +/* POST60 Bit Fields */ +#define CCM_POST60_POST_PODF_MASK 0x3Fu +#define CCM_POST60_POST_PODF_SHIFT 0 +#define CCM_POST60_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST60_POST_PODF_SHIFT))&CCM_POST60_POST_PODF_MASK) +#define CCM_POST60_BUSY1_MASK 0x80u +#define CCM_POST60_BUSY1_SHIFT 7 +#define CCM_POST60_AUTO_PODF_MASK 0x700u +#define CCM_POST60_AUTO_PODF_SHIFT 8 +#define CCM_POST60_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST60_AUTO_PODF_SHIFT))&CCM_POST60_AUTO_PODF_MASK) +#define CCM_POST60_AUTO_EN_MASK 0x1000u +#define CCM_POST60_AUTO_EN_SHIFT 12 +#define CCM_POST60_SLOW_MASK 0x8000u +#define CCM_POST60_SLOW_SHIFT 15 +#define CCM_POST60_SELECT_MASK 0x10000000u +#define CCM_POST60_SELECT_SHIFT 28 +#define CCM_POST60_BUSY2_MASK 0x80000000u +#define CCM_POST60_BUSY2_SHIFT 31 +/* POST_ROOT60_SET Bit Fields */ +#define CCM_POST_ROOT60_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT60_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT60_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_SET_POST_PODF_SHIFT))&CCM_POST_ROOT60_SET_POST_PODF_MASK) +#define CCM_POST_ROOT60_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT60_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT60_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT60_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT60_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT60_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT60_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT60_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT60_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT60_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT60_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT60_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT60_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT60_SET_BUSY2_SHIFT 31 +/* POST_ROOT60_CLR Bit Fields */ +#define CCM_POST_ROOT60_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT60_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT60_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT60_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT60_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT60_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT60_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT60_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT60_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT60_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT60_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT60_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT60_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT60_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT60_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT60_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT60_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT60_CLR_BUSY2_SHIFT 31 +/* POST_ROOT60_TOG Bit Fields */ +#define CCM_POST_ROOT60_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT60_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT60_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT60_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT60_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT60_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT60_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT60_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT60_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT60_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT60_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT60_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT60_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT60_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT60_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT60_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT60_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT60_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT60_TOG_BUSY2_SHIFT 31 +/* PRE60 Bit Fields */ +#define CCM_PRE60_PRE_PODF_B_MASK 0x7u +#define CCM_PRE60_PRE_PODF_B_SHIFT 0 +#define CCM_PRE60_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_PRE_PODF_B_SHIFT))&CCM_PRE60_PRE_PODF_B_MASK) +#define CCM_PRE60_BUSY0_MASK 0x8u +#define CCM_PRE60_BUSY0_SHIFT 3 +#define CCM_PRE60_MUX_B_MASK 0x700u +#define CCM_PRE60_MUX_B_SHIFT 8 +#define CCM_PRE60_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_MUX_B_SHIFT))&CCM_PRE60_MUX_B_MASK) +#define CCM_PRE60_EN_B_MASK 0x1000u +#define CCM_PRE60_EN_B_SHIFT 12 +#define CCM_PRE60_BUSY1_MASK 0x8000u +#define CCM_PRE60_BUSY1_SHIFT 15 +#define CCM_PRE60_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE60_PRE_PODF_A_SHIFT 16 +#define CCM_PRE60_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_PRE_PODF_A_SHIFT))&CCM_PRE60_PRE_PODF_A_MASK) +#define CCM_PRE60_BUSY3_MASK 0x80000u +#define CCM_PRE60_BUSY3_SHIFT 19 +#define CCM_PRE60_MUX_A_MASK 0x7000000u +#define CCM_PRE60_MUX_A_SHIFT 24 +#define CCM_PRE60_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE60_MUX_A_SHIFT))&CCM_PRE60_MUX_A_MASK) +#define CCM_PRE60_EN_A_MASK 0x10000000u +#define CCM_PRE60_EN_A_SHIFT 28 +#define CCM_PRE60_BUSY4_MASK 0x80000000u +#define CCM_PRE60_BUSY4_SHIFT 31 +/* PRE_ROOT60_SET Bit Fields */ +#define CCM_PRE_ROOT60_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT60_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT60_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT60_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT60_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT60_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT60_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT60_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT60_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_MUX_B_SHIFT))&CCM_PRE_ROOT60_SET_MUX_B_MASK) +#define CCM_PRE_ROOT60_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT60_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT60_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT60_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT60_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT60_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT60_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT60_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT60_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT60_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT60_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT60_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT60_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_SET_MUX_A_SHIFT))&CCM_PRE_ROOT60_SET_MUX_A_MASK) +#define CCM_PRE_ROOT60_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT60_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT60_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT60_SET_BUSY4_SHIFT 31 +/* PRE_ROOT60_CLR Bit Fields */ +#define CCM_PRE_ROOT60_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT60_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT60_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT60_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT60_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT60_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT60_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT60_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT60_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT60_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT60_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT60_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT60_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT60_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT60_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT60_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT60_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT60_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT60_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT60_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT60_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT60_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT60_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT60_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT60_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT60_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT60_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT60_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT60_TOG Bit Fields */ +#define CCM_PRE_ROOT60_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT60_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT60_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT60_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT60_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT60_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT60_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT60_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT60_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT60_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT60_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT60_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT60_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT60_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT60_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT60_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT60_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT60_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT60_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT60_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT60_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT60_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT60_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT60_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT60_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT60_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT60_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT60_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT60_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL60 Bit Fields */ +#define CCM_ACCESS_CTRL60_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL60_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL60_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL60_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL60_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL60_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL60_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL60_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL60_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL60_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL60_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL60_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL60_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL60_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL60_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL60_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL60_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL60_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL60_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL60_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL60_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL60_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL60_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL60_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL60_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL60_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL60_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL60_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL60_LOCK_SHIFT 31 +/* ACCESS_CTRL60_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL60_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL60_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL60_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL60_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL60_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL60_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL60_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL60_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL60_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL60_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL60_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL60_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL60_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL60_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL60_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL60_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL60_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL60_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT61 Bit Fields */ +#define CCM_TARGET_ROOT61_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT61_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT61_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_POST_PODF_MASK) +#define CCM_TARGET_ROOT61_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT61_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT61_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT61_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT61_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT61_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT61_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT61_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT61_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT61_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_PRE_PODF_MASK) +#define CCM_TARGET_ROOT61_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT61_MUX_SHIFT 24 +#define CCM_TARGET_ROOT61_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_MUX_SHIFT))&CCM_TARGET_ROOT61_MUX_MASK) +#define CCM_TARGET_ROOT61_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT61_ENABLE_SHIFT 28 +/* TARGET_ROOT61_SET Bit Fields */ +#define CCM_TARGET_ROOT61_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT61_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT61_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT61_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT61_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT61_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT61_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT61_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT61_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT61_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT61_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT61_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT61_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT61_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT61_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT61_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_SET_MUX_SHIFT))&CCM_TARGET_ROOT61_SET_MUX_MASK) +#define CCM_TARGET_ROOT61_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT61_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT61_CLR Bit Fields */ +#define CCM_TARGET_ROOT61_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT61_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT61_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT61_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT61_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT61_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT61_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT61_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT61_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT61_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT61_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT61_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT61_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_CLR_MUX_SHIFT))&CCM_TARGET_ROOT61_CLR_MUX_MASK) +#define CCM_TARGET_ROOT61_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT61_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT61_TOG Bit Fields */ +#define CCM_TARGET_ROOT61_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT61_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT61_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT61_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT61_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT61_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT61_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT61_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT61_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT61_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT61_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT61_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT61_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT61_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT61_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT61_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT61_TOG_MUX_SHIFT))&CCM_TARGET_ROOT61_TOG_MUX_MASK) +#define CCM_TARGET_ROOT61_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT61_TOG_ENABLE_SHIFT 28 +/* POST61 Bit Fields */ +#define CCM_POST61_POST_PODF_MASK 0x3Fu +#define CCM_POST61_POST_PODF_SHIFT 0 +#define CCM_POST61_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST61_POST_PODF_SHIFT))&CCM_POST61_POST_PODF_MASK) +#define CCM_POST61_BUSY1_MASK 0x80u +#define CCM_POST61_BUSY1_SHIFT 7 +#define CCM_POST61_AUTO_PODF_MASK 0x700u +#define CCM_POST61_AUTO_PODF_SHIFT 8 +#define CCM_POST61_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST61_AUTO_PODF_SHIFT))&CCM_POST61_AUTO_PODF_MASK) +#define CCM_POST61_AUTO_EN_MASK 0x1000u +#define CCM_POST61_AUTO_EN_SHIFT 12 +#define CCM_POST61_SLOW_MASK 0x8000u +#define CCM_POST61_SLOW_SHIFT 15 +#define CCM_POST61_SELECT_MASK 0x10000000u +#define CCM_POST61_SELECT_SHIFT 28 +#define CCM_POST61_BUSY2_MASK 0x80000000u +#define CCM_POST61_BUSY2_SHIFT 31 +/* POST_ROOT61_SET Bit Fields */ +#define CCM_POST_ROOT61_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT61_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT61_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_SET_POST_PODF_SHIFT))&CCM_POST_ROOT61_SET_POST_PODF_MASK) +#define CCM_POST_ROOT61_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT61_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT61_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT61_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT61_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT61_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT61_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT61_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT61_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT61_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT61_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT61_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT61_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT61_SET_BUSY2_SHIFT 31 +/* POST_ROOT61_CLR Bit Fields */ +#define CCM_POST_ROOT61_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT61_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT61_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT61_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT61_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT61_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT61_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT61_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT61_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT61_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT61_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT61_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT61_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT61_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT61_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT61_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT61_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT61_CLR_BUSY2_SHIFT 31 +/* POST_ROOT61_TOG Bit Fields */ +#define CCM_POST_ROOT61_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT61_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT61_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT61_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT61_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT61_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT61_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT61_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT61_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT61_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT61_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT61_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT61_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT61_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT61_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT61_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT61_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT61_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT61_TOG_BUSY2_SHIFT 31 +/* PRE61 Bit Fields */ +#define CCM_PRE61_PRE_PODF_B_MASK 0x7u +#define CCM_PRE61_PRE_PODF_B_SHIFT 0 +#define CCM_PRE61_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_PRE_PODF_B_SHIFT))&CCM_PRE61_PRE_PODF_B_MASK) +#define CCM_PRE61_BUSY0_MASK 0x8u +#define CCM_PRE61_BUSY0_SHIFT 3 +#define CCM_PRE61_MUX_B_MASK 0x700u +#define CCM_PRE61_MUX_B_SHIFT 8 +#define CCM_PRE61_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_MUX_B_SHIFT))&CCM_PRE61_MUX_B_MASK) +#define CCM_PRE61_EN_B_MASK 0x1000u +#define CCM_PRE61_EN_B_SHIFT 12 +#define CCM_PRE61_BUSY1_MASK 0x8000u +#define CCM_PRE61_BUSY1_SHIFT 15 +#define CCM_PRE61_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE61_PRE_PODF_A_SHIFT 16 +#define CCM_PRE61_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_PRE_PODF_A_SHIFT))&CCM_PRE61_PRE_PODF_A_MASK) +#define CCM_PRE61_BUSY3_MASK 0x80000u +#define CCM_PRE61_BUSY3_SHIFT 19 +#define CCM_PRE61_MUX_A_MASK 0x7000000u +#define CCM_PRE61_MUX_A_SHIFT 24 +#define CCM_PRE61_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE61_MUX_A_SHIFT))&CCM_PRE61_MUX_A_MASK) +#define CCM_PRE61_EN_A_MASK 0x10000000u +#define CCM_PRE61_EN_A_SHIFT 28 +#define CCM_PRE61_BUSY4_MASK 0x80000000u +#define CCM_PRE61_BUSY4_SHIFT 31 +/* PRE_ROOT61_SET Bit Fields */ +#define CCM_PRE_ROOT61_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT61_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT61_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT61_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT61_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT61_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT61_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT61_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT61_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_MUX_B_SHIFT))&CCM_PRE_ROOT61_SET_MUX_B_MASK) +#define CCM_PRE_ROOT61_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT61_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT61_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT61_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT61_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT61_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT61_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT61_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT61_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT61_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT61_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT61_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT61_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_SET_MUX_A_SHIFT))&CCM_PRE_ROOT61_SET_MUX_A_MASK) +#define CCM_PRE_ROOT61_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT61_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT61_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT61_SET_BUSY4_SHIFT 31 +/* PRE_ROOT61_CLR Bit Fields */ +#define CCM_PRE_ROOT61_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT61_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT61_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT61_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT61_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT61_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT61_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT61_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT61_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT61_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT61_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT61_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT61_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT61_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT61_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT61_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT61_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT61_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT61_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT61_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT61_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT61_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT61_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT61_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT61_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT61_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT61_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT61_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT61_TOG Bit Fields */ +#define CCM_PRE_ROOT61_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT61_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT61_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT61_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT61_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT61_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT61_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT61_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT61_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT61_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT61_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT61_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT61_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT61_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT61_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT61_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT61_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT61_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT61_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT61_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT61_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT61_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT61_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT61_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT61_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT61_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT61_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT61_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT61_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL61 Bit Fields */ +#define CCM_ACCESS_CTRL61_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL61_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL61_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL61_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL61_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL61_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL61_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL61_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL61_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL61_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL61_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL61_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL61_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL61_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL61_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL61_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL61_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL61_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL61_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL61_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL61_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL61_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL61_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL61_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL61_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL61_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL61_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL61_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL61_LOCK_SHIFT 31 +/* ACCESS_CTRL61_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL61_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL61_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL61_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL61_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL61_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL61_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL61_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL61_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL61_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL61_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL61_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL61_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL61_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL61_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL61_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL61_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL61_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL61_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT62 Bit Fields */ +#define CCM_TARGET_ROOT62_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT62_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT62_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_POST_PODF_MASK) +#define CCM_TARGET_ROOT62_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT62_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT62_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT62_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT62_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT62_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT62_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT62_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT62_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT62_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_PRE_PODF_MASK) +#define CCM_TARGET_ROOT62_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT62_MUX_SHIFT 24 +#define CCM_TARGET_ROOT62_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_MUX_SHIFT))&CCM_TARGET_ROOT62_MUX_MASK) +#define CCM_TARGET_ROOT62_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT62_ENABLE_SHIFT 28 +/* TARGET_ROOT62_SET Bit Fields */ +#define CCM_TARGET_ROOT62_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT62_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT62_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT62_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT62_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT62_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT62_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT62_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT62_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT62_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT62_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT62_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT62_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT62_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT62_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT62_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_SET_MUX_SHIFT))&CCM_TARGET_ROOT62_SET_MUX_MASK) +#define CCM_TARGET_ROOT62_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT62_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT62_CLR Bit Fields */ +#define CCM_TARGET_ROOT62_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT62_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT62_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT62_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT62_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT62_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT62_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT62_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT62_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT62_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT62_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT62_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT62_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_CLR_MUX_SHIFT))&CCM_TARGET_ROOT62_CLR_MUX_MASK) +#define CCM_TARGET_ROOT62_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT62_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT62_TOG Bit Fields */ +#define CCM_TARGET_ROOT62_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT62_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT62_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT62_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT62_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT62_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT62_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT62_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT62_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT62_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT62_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT62_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT62_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT62_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT62_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT62_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT62_TOG_MUX_SHIFT))&CCM_TARGET_ROOT62_TOG_MUX_MASK) +#define CCM_TARGET_ROOT62_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT62_TOG_ENABLE_SHIFT 28 +/* POST62 Bit Fields */ +#define CCM_POST62_POST_PODF_MASK 0x3Fu +#define CCM_POST62_POST_PODF_SHIFT 0 +#define CCM_POST62_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST62_POST_PODF_SHIFT))&CCM_POST62_POST_PODF_MASK) +#define CCM_POST62_BUSY1_MASK 0x80u +#define CCM_POST62_BUSY1_SHIFT 7 +#define CCM_POST62_AUTO_PODF_MASK 0x700u +#define CCM_POST62_AUTO_PODF_SHIFT 8 +#define CCM_POST62_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST62_AUTO_PODF_SHIFT))&CCM_POST62_AUTO_PODF_MASK) +#define CCM_POST62_AUTO_EN_MASK 0x1000u +#define CCM_POST62_AUTO_EN_SHIFT 12 +#define CCM_POST62_SLOW_MASK 0x8000u +#define CCM_POST62_SLOW_SHIFT 15 +#define CCM_POST62_SELECT_MASK 0x10000000u +#define CCM_POST62_SELECT_SHIFT 28 +#define CCM_POST62_BUSY2_MASK 0x80000000u +#define CCM_POST62_BUSY2_SHIFT 31 +/* POST_ROOT62_SET Bit Fields */ +#define CCM_POST_ROOT62_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT62_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT62_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_SET_POST_PODF_SHIFT))&CCM_POST_ROOT62_SET_POST_PODF_MASK) +#define CCM_POST_ROOT62_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT62_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT62_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT62_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT62_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT62_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT62_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT62_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT62_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT62_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT62_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT62_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT62_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT62_SET_BUSY2_SHIFT 31 +/* POST_ROOT62_CLR Bit Fields */ +#define CCM_POST_ROOT62_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT62_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT62_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT62_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT62_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT62_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT62_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT62_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT62_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT62_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT62_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT62_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT62_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT62_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT62_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT62_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT62_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT62_CLR_BUSY2_SHIFT 31 +/* POST_ROOT62_TOG Bit Fields */ +#define CCM_POST_ROOT62_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT62_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT62_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT62_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT62_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT62_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT62_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT62_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT62_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT62_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT62_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT62_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT62_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT62_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT62_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT62_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT62_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT62_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT62_TOG_BUSY2_SHIFT 31 +/* PRE62 Bit Fields */ +#define CCM_PRE62_PRE_PODF_B_MASK 0x7u +#define CCM_PRE62_PRE_PODF_B_SHIFT 0 +#define CCM_PRE62_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_PRE_PODF_B_SHIFT))&CCM_PRE62_PRE_PODF_B_MASK) +#define CCM_PRE62_BUSY0_MASK 0x8u +#define CCM_PRE62_BUSY0_SHIFT 3 +#define CCM_PRE62_MUX_B_MASK 0x700u +#define CCM_PRE62_MUX_B_SHIFT 8 +#define CCM_PRE62_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_MUX_B_SHIFT))&CCM_PRE62_MUX_B_MASK) +#define CCM_PRE62_EN_B_MASK 0x1000u +#define CCM_PRE62_EN_B_SHIFT 12 +#define CCM_PRE62_BUSY1_MASK 0x8000u +#define CCM_PRE62_BUSY1_SHIFT 15 +#define CCM_PRE62_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE62_PRE_PODF_A_SHIFT 16 +#define CCM_PRE62_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_PRE_PODF_A_SHIFT))&CCM_PRE62_PRE_PODF_A_MASK) +#define CCM_PRE62_BUSY3_MASK 0x80000u +#define CCM_PRE62_BUSY3_SHIFT 19 +#define CCM_PRE62_MUX_A_MASK 0x7000000u +#define CCM_PRE62_MUX_A_SHIFT 24 +#define CCM_PRE62_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE62_MUX_A_SHIFT))&CCM_PRE62_MUX_A_MASK) +#define CCM_PRE62_EN_A_MASK 0x10000000u +#define CCM_PRE62_EN_A_SHIFT 28 +#define CCM_PRE62_BUSY4_MASK 0x80000000u +#define CCM_PRE62_BUSY4_SHIFT 31 +/* PRE_ROOT62_SET Bit Fields */ +#define CCM_PRE_ROOT62_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT62_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT62_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT62_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT62_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT62_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT62_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT62_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT62_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_MUX_B_SHIFT))&CCM_PRE_ROOT62_SET_MUX_B_MASK) +#define CCM_PRE_ROOT62_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT62_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT62_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT62_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT62_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT62_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT62_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT62_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT62_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT62_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT62_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT62_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT62_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_SET_MUX_A_SHIFT))&CCM_PRE_ROOT62_SET_MUX_A_MASK) +#define CCM_PRE_ROOT62_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT62_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT62_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT62_SET_BUSY4_SHIFT 31 +/* PRE_ROOT62_CLR Bit Fields */ +#define CCM_PRE_ROOT62_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT62_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT62_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT62_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT62_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT62_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT62_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT62_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT62_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT62_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT62_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT62_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT62_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT62_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT62_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT62_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT62_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT62_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT62_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT62_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT62_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT62_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT62_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT62_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT62_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT62_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT62_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT62_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT62_TOG Bit Fields */ +#define CCM_PRE_ROOT62_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT62_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT62_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT62_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT62_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT62_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT62_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT62_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT62_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT62_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT62_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT62_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT62_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT62_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT62_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT62_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT62_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT62_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT62_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT62_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT62_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT62_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT62_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT62_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT62_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT62_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT62_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT62_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT62_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL62 Bit Fields */ +#define CCM_ACCESS_CTRL62_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL62_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL62_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL62_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL62_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL62_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL62_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL62_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL62_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL62_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL62_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL62_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL62_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL62_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL62_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL62_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL62_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL62_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL62_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL62_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL62_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL62_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL62_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL62_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL62_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL62_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL62_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL62_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL62_LOCK_SHIFT 31 +/* ACCESS_CTRL62_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL62_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL62_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL62_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL62_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL62_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL62_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL62_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL62_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL62_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL62_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL62_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL62_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL62_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL62_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL62_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL62_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL62_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL62_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT63 Bit Fields */ +#define CCM_TARGET_ROOT63_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT63_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT63_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_POST_PODF_MASK) +#define CCM_TARGET_ROOT63_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT63_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT63_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT63_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT63_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT63_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT63_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT63_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT63_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT63_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_PRE_PODF_MASK) +#define CCM_TARGET_ROOT63_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT63_MUX_SHIFT 24 +#define CCM_TARGET_ROOT63_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_MUX_SHIFT))&CCM_TARGET_ROOT63_MUX_MASK) +#define CCM_TARGET_ROOT63_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT63_ENABLE_SHIFT 28 +/* TARGET_ROOT63_SET Bit Fields */ +#define CCM_TARGET_ROOT63_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT63_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT63_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT63_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT63_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT63_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT63_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT63_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT63_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT63_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT63_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT63_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT63_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT63_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT63_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT63_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_SET_MUX_SHIFT))&CCM_TARGET_ROOT63_SET_MUX_MASK) +#define CCM_TARGET_ROOT63_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT63_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT63_CLR Bit Fields */ +#define CCM_TARGET_ROOT63_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT63_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT63_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT63_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT63_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT63_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT63_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT63_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT63_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT63_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT63_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT63_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT63_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_CLR_MUX_SHIFT))&CCM_TARGET_ROOT63_CLR_MUX_MASK) +#define CCM_TARGET_ROOT63_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT63_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT63_TOG Bit Fields */ +#define CCM_TARGET_ROOT63_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT63_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT63_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT63_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT63_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT63_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT63_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT63_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT63_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT63_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT63_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT63_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT63_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT63_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT63_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT63_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT63_TOG_MUX_SHIFT))&CCM_TARGET_ROOT63_TOG_MUX_MASK) +#define CCM_TARGET_ROOT63_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT63_TOG_ENABLE_SHIFT 28 +/* POST63 Bit Fields */ +#define CCM_POST63_POST_PODF_MASK 0x3Fu +#define CCM_POST63_POST_PODF_SHIFT 0 +#define CCM_POST63_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST63_POST_PODF_SHIFT))&CCM_POST63_POST_PODF_MASK) +#define CCM_POST63_BUSY1_MASK 0x80u +#define CCM_POST63_BUSY1_SHIFT 7 +#define CCM_POST63_AUTO_PODF_MASK 0x700u +#define CCM_POST63_AUTO_PODF_SHIFT 8 +#define CCM_POST63_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST63_AUTO_PODF_SHIFT))&CCM_POST63_AUTO_PODF_MASK) +#define CCM_POST63_AUTO_EN_MASK 0x1000u +#define CCM_POST63_AUTO_EN_SHIFT 12 +#define CCM_POST63_SLOW_MASK 0x8000u +#define CCM_POST63_SLOW_SHIFT 15 +#define CCM_POST63_SELECT_MASK 0x10000000u +#define CCM_POST63_SELECT_SHIFT 28 +#define CCM_POST63_BUSY2_MASK 0x80000000u +#define CCM_POST63_BUSY2_SHIFT 31 +/* POST_ROOT63_SET Bit Fields */ +#define CCM_POST_ROOT63_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT63_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT63_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_SET_POST_PODF_SHIFT))&CCM_POST_ROOT63_SET_POST_PODF_MASK) +#define CCM_POST_ROOT63_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT63_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT63_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT63_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT63_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT63_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT63_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT63_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT63_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT63_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT63_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT63_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT63_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT63_SET_BUSY2_SHIFT 31 +/* POST_ROOT63_CLR Bit Fields */ +#define CCM_POST_ROOT63_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT63_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT63_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT63_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT63_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT63_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT63_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT63_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT63_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT63_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT63_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT63_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT63_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT63_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT63_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT63_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT63_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT63_CLR_BUSY2_SHIFT 31 +/* POST_ROOT63_TOG Bit Fields */ +#define CCM_POST_ROOT63_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT63_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT63_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT63_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT63_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT63_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT63_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT63_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT63_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT63_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT63_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT63_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT63_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT63_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT63_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT63_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT63_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT63_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT63_TOG_BUSY2_SHIFT 31 +/* PRE63 Bit Fields */ +#define CCM_PRE63_PRE_PODF_B_MASK 0x7u +#define CCM_PRE63_PRE_PODF_B_SHIFT 0 +#define CCM_PRE63_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_PRE_PODF_B_SHIFT))&CCM_PRE63_PRE_PODF_B_MASK) +#define CCM_PRE63_BUSY0_MASK 0x8u +#define CCM_PRE63_BUSY0_SHIFT 3 +#define CCM_PRE63_MUX_B_MASK 0x700u +#define CCM_PRE63_MUX_B_SHIFT 8 +#define CCM_PRE63_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_MUX_B_SHIFT))&CCM_PRE63_MUX_B_MASK) +#define CCM_PRE63_EN_B_MASK 0x1000u +#define CCM_PRE63_EN_B_SHIFT 12 +#define CCM_PRE63_BUSY1_MASK 0x8000u +#define CCM_PRE63_BUSY1_SHIFT 15 +#define CCM_PRE63_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE63_PRE_PODF_A_SHIFT 16 +#define CCM_PRE63_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_PRE_PODF_A_SHIFT))&CCM_PRE63_PRE_PODF_A_MASK) +#define CCM_PRE63_BUSY3_MASK 0x80000u +#define CCM_PRE63_BUSY3_SHIFT 19 +#define CCM_PRE63_MUX_A_MASK 0x7000000u +#define CCM_PRE63_MUX_A_SHIFT 24 +#define CCM_PRE63_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE63_MUX_A_SHIFT))&CCM_PRE63_MUX_A_MASK) +#define CCM_PRE63_EN_A_MASK 0x10000000u +#define CCM_PRE63_EN_A_SHIFT 28 +#define CCM_PRE63_BUSY4_MASK 0x80000000u +#define CCM_PRE63_BUSY4_SHIFT 31 +/* PRE_ROOT63_SET Bit Fields */ +#define CCM_PRE_ROOT63_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT63_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT63_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT63_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT63_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT63_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT63_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT63_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT63_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_MUX_B_SHIFT))&CCM_PRE_ROOT63_SET_MUX_B_MASK) +#define CCM_PRE_ROOT63_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT63_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT63_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT63_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT63_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT63_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT63_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT63_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT63_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT63_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT63_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT63_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT63_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_SET_MUX_A_SHIFT))&CCM_PRE_ROOT63_SET_MUX_A_MASK) +#define CCM_PRE_ROOT63_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT63_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT63_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT63_SET_BUSY4_SHIFT 31 +/* PRE_ROOT63_CLR Bit Fields */ +#define CCM_PRE_ROOT63_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT63_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT63_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT63_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT63_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT63_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT63_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT63_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT63_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT63_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT63_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT63_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT63_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT63_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT63_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT63_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT63_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT63_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT63_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT63_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT63_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT63_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT63_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT63_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT63_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT63_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT63_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT63_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT63_TOG Bit Fields */ +#define CCM_PRE_ROOT63_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT63_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT63_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT63_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT63_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT63_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT63_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT63_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT63_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT63_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT63_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT63_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT63_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT63_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT63_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT63_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT63_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT63_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT63_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT63_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT63_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT63_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT63_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT63_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT63_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT63_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT63_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT63_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT63_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL63 Bit Fields */ +#define CCM_ACCESS_CTRL63_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL63_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL63_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL63_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL63_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL63_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL63_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL63_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL63_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL63_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL63_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL63_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL63_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL63_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL63_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL63_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL63_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL63_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL63_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL63_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL63_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL63_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL63_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL63_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL63_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL63_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL63_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL63_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL63_LOCK_SHIFT 31 +/* ACCESS_CTRL63_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL63_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL63_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL63_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL63_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL63_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL63_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL63_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL63_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL63_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL63_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL63_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL63_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL63_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL63_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL63_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL63_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL63_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL63_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT64 Bit Fields */ +#define CCM_TARGET_ROOT64_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT64_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT64_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_POST_PODF_MASK) +#define CCM_TARGET_ROOT64_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT64_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT64_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT64_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT64_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT64_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT64_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT64_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT64_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT64_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_PRE_PODF_MASK) +#define CCM_TARGET_ROOT64_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT64_MUX_SHIFT 24 +#define CCM_TARGET_ROOT64_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_MUX_SHIFT))&CCM_TARGET_ROOT64_MUX_MASK) +#define CCM_TARGET_ROOT64_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT64_ENABLE_SHIFT 28 +/* TARGET_ROOT64_SET Bit Fields */ +#define CCM_TARGET_ROOT64_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT64_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT64_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT64_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT64_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT64_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT64_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT64_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT64_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT64_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT64_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT64_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT64_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT64_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT64_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT64_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_SET_MUX_SHIFT))&CCM_TARGET_ROOT64_SET_MUX_MASK) +#define CCM_TARGET_ROOT64_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT64_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT64_CLR Bit Fields */ +#define CCM_TARGET_ROOT64_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT64_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT64_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT64_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT64_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT64_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT64_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT64_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT64_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT64_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT64_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT64_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT64_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_CLR_MUX_SHIFT))&CCM_TARGET_ROOT64_CLR_MUX_MASK) +#define CCM_TARGET_ROOT64_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT64_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT64_TOG Bit Fields */ +#define CCM_TARGET_ROOT64_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT64_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT64_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT64_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT64_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT64_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT64_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT64_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT64_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT64_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT64_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT64_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT64_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT64_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT64_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT64_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT64_TOG_MUX_SHIFT))&CCM_TARGET_ROOT64_TOG_MUX_MASK) +#define CCM_TARGET_ROOT64_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT64_TOG_ENABLE_SHIFT 28 +/* POST64 Bit Fields */ +#define CCM_POST64_POST_PODF_MASK 0x3Fu +#define CCM_POST64_POST_PODF_SHIFT 0 +#define CCM_POST64_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST64_POST_PODF_SHIFT))&CCM_POST64_POST_PODF_MASK) +#define CCM_POST64_BUSY1_MASK 0x80u +#define CCM_POST64_BUSY1_SHIFT 7 +#define CCM_POST64_AUTO_PODF_MASK 0x700u +#define CCM_POST64_AUTO_PODF_SHIFT 8 +#define CCM_POST64_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST64_AUTO_PODF_SHIFT))&CCM_POST64_AUTO_PODF_MASK) +#define CCM_POST64_AUTO_EN_MASK 0x1000u +#define CCM_POST64_AUTO_EN_SHIFT 12 +#define CCM_POST64_SLOW_MASK 0x8000u +#define CCM_POST64_SLOW_SHIFT 15 +#define CCM_POST64_SELECT_MASK 0x10000000u +#define CCM_POST64_SELECT_SHIFT 28 +#define CCM_POST64_BUSY2_MASK 0x80000000u +#define CCM_POST64_BUSY2_SHIFT 31 +/* POST_ROOT64_SET Bit Fields */ +#define CCM_POST_ROOT64_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT64_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT64_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_SET_POST_PODF_SHIFT))&CCM_POST_ROOT64_SET_POST_PODF_MASK) +#define CCM_POST_ROOT64_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT64_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT64_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT64_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT64_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT64_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT64_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT64_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT64_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT64_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT64_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT64_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT64_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT64_SET_BUSY2_SHIFT 31 +/* POST_ROOT64_CLR Bit Fields */ +#define CCM_POST_ROOT64_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT64_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT64_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT64_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT64_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT64_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT64_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT64_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT64_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT64_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT64_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT64_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT64_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT64_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT64_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT64_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT64_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT64_CLR_BUSY2_SHIFT 31 +/* POST_ROOT64_TOG Bit Fields */ +#define CCM_POST_ROOT64_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT64_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT64_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT64_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT64_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT64_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT64_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT64_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT64_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT64_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT64_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT64_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT64_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT64_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT64_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT64_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT64_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT64_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT64_TOG_BUSY2_SHIFT 31 +/* PRE64 Bit Fields */ +#define CCM_PRE64_PRE_PODF_B_MASK 0x7u +#define CCM_PRE64_PRE_PODF_B_SHIFT 0 +#define CCM_PRE64_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_PRE_PODF_B_SHIFT))&CCM_PRE64_PRE_PODF_B_MASK) +#define CCM_PRE64_BUSY0_MASK 0x8u +#define CCM_PRE64_BUSY0_SHIFT 3 +#define CCM_PRE64_MUX_B_MASK 0x700u +#define CCM_PRE64_MUX_B_SHIFT 8 +#define CCM_PRE64_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_MUX_B_SHIFT))&CCM_PRE64_MUX_B_MASK) +#define CCM_PRE64_EN_B_MASK 0x1000u +#define CCM_PRE64_EN_B_SHIFT 12 +#define CCM_PRE64_BUSY1_MASK 0x8000u +#define CCM_PRE64_BUSY1_SHIFT 15 +#define CCM_PRE64_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE64_PRE_PODF_A_SHIFT 16 +#define CCM_PRE64_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_PRE_PODF_A_SHIFT))&CCM_PRE64_PRE_PODF_A_MASK) +#define CCM_PRE64_BUSY3_MASK 0x80000u +#define CCM_PRE64_BUSY3_SHIFT 19 +#define CCM_PRE64_MUX_A_MASK 0x7000000u +#define CCM_PRE64_MUX_A_SHIFT 24 +#define CCM_PRE64_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE64_MUX_A_SHIFT))&CCM_PRE64_MUX_A_MASK) +#define CCM_PRE64_EN_A_MASK 0x10000000u +#define CCM_PRE64_EN_A_SHIFT 28 +#define CCM_PRE64_BUSY4_MASK 0x80000000u +#define CCM_PRE64_BUSY4_SHIFT 31 +/* PRE_ROOT64_SET Bit Fields */ +#define CCM_PRE_ROOT64_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT64_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT64_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT64_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT64_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT64_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT64_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT64_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT64_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_MUX_B_SHIFT))&CCM_PRE_ROOT64_SET_MUX_B_MASK) +#define CCM_PRE_ROOT64_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT64_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT64_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT64_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT64_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT64_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT64_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT64_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT64_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT64_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT64_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT64_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT64_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_SET_MUX_A_SHIFT))&CCM_PRE_ROOT64_SET_MUX_A_MASK) +#define CCM_PRE_ROOT64_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT64_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT64_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT64_SET_BUSY4_SHIFT 31 +/* PRE_ROOT64_CLR Bit Fields */ +#define CCM_PRE_ROOT64_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT64_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT64_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT64_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT64_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT64_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT64_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT64_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT64_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT64_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT64_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT64_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT64_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT64_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT64_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT64_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT64_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT64_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT64_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT64_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT64_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT64_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT64_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT64_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT64_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT64_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT64_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT64_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT64_TOG Bit Fields */ +#define CCM_PRE_ROOT64_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT64_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT64_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT64_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT64_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT64_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT64_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT64_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT64_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT64_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT64_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT64_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT64_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT64_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT64_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT64_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT64_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT64_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT64_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT64_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT64_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT64_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT64_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT64_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT64_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT64_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT64_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT64_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT64_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL64 Bit Fields */ +#define CCM_ACCESS_CTRL64_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL64_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL64_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL64_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL64_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL64_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL64_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL64_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL64_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL64_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL64_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL64_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL64_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL64_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL64_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL64_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL64_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL64_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL64_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL64_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL64_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL64_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL64_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL64_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL64_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL64_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL64_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL64_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL64_LOCK_SHIFT 31 +/* ACCESS_CTRL64_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL64_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL64_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL64_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL64_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL64_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL64_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL64_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL64_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL64_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL64_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL64_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL64_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL64_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL64_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL64_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL64_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL64_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL64_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT65 Bit Fields */ +#define CCM_TARGET_ROOT65_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT65_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT65_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_POST_PODF_MASK) +#define CCM_TARGET_ROOT65_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT65_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT65_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT65_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT65_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT65_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT65_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT65_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT65_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT65_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_PRE_PODF_MASK) +#define CCM_TARGET_ROOT65_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT65_MUX_SHIFT 24 +#define CCM_TARGET_ROOT65_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_MUX_SHIFT))&CCM_TARGET_ROOT65_MUX_MASK) +#define CCM_TARGET_ROOT65_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT65_ENABLE_SHIFT 28 +/* TARGET_ROOT65_SET Bit Fields */ +#define CCM_TARGET_ROOT65_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT65_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT65_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT65_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT65_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT65_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT65_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT65_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT65_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT65_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT65_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT65_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT65_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT65_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT65_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT65_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_SET_MUX_SHIFT))&CCM_TARGET_ROOT65_SET_MUX_MASK) +#define CCM_TARGET_ROOT65_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT65_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT65_CLR Bit Fields */ +#define CCM_TARGET_ROOT65_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT65_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT65_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT65_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT65_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT65_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT65_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT65_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT65_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT65_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT65_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT65_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT65_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_CLR_MUX_SHIFT))&CCM_TARGET_ROOT65_CLR_MUX_MASK) +#define CCM_TARGET_ROOT65_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT65_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT65_TOG Bit Fields */ +#define CCM_TARGET_ROOT65_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT65_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT65_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT65_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT65_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT65_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT65_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT65_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT65_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT65_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT65_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT65_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT65_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT65_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT65_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT65_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT65_TOG_MUX_SHIFT))&CCM_TARGET_ROOT65_TOG_MUX_MASK) +#define CCM_TARGET_ROOT65_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT65_TOG_ENABLE_SHIFT 28 +/* POST65 Bit Fields */ +#define CCM_POST65_POST_PODF_MASK 0x3Fu +#define CCM_POST65_POST_PODF_SHIFT 0 +#define CCM_POST65_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST65_POST_PODF_SHIFT))&CCM_POST65_POST_PODF_MASK) +#define CCM_POST65_BUSY1_MASK 0x80u +#define CCM_POST65_BUSY1_SHIFT 7 +#define CCM_POST65_AUTO_PODF_MASK 0x700u +#define CCM_POST65_AUTO_PODF_SHIFT 8 +#define CCM_POST65_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST65_AUTO_PODF_SHIFT))&CCM_POST65_AUTO_PODF_MASK) +#define CCM_POST65_AUTO_EN_MASK 0x1000u +#define CCM_POST65_AUTO_EN_SHIFT 12 +#define CCM_POST65_SLOW_MASK 0x8000u +#define CCM_POST65_SLOW_SHIFT 15 +#define CCM_POST65_SELECT_MASK 0x10000000u +#define CCM_POST65_SELECT_SHIFT 28 +#define CCM_POST65_BUSY2_MASK 0x80000000u +#define CCM_POST65_BUSY2_SHIFT 31 +/* POST_ROOT65_SET Bit Fields */ +#define CCM_POST_ROOT65_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT65_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT65_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_SET_POST_PODF_SHIFT))&CCM_POST_ROOT65_SET_POST_PODF_MASK) +#define CCM_POST_ROOT65_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT65_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT65_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT65_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT65_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT65_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT65_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT65_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT65_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT65_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT65_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT65_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT65_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT65_SET_BUSY2_SHIFT 31 +/* POST_ROOT65_CLR Bit Fields */ +#define CCM_POST_ROOT65_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT65_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT65_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT65_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT65_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT65_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT65_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT65_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT65_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT65_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT65_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT65_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT65_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT65_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT65_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT65_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT65_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT65_CLR_BUSY2_SHIFT 31 +/* POST_ROOT65_TOG Bit Fields */ +#define CCM_POST_ROOT65_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT65_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT65_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT65_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT65_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT65_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT65_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT65_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT65_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT65_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT65_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT65_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT65_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT65_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT65_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT65_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT65_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT65_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT65_TOG_BUSY2_SHIFT 31 +/* PRE65 Bit Fields */ +#define CCM_PRE65_PRE_PODF_B_MASK 0x7u +#define CCM_PRE65_PRE_PODF_B_SHIFT 0 +#define CCM_PRE65_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_PRE_PODF_B_SHIFT))&CCM_PRE65_PRE_PODF_B_MASK) +#define CCM_PRE65_BUSY0_MASK 0x8u +#define CCM_PRE65_BUSY0_SHIFT 3 +#define CCM_PRE65_MUX_B_MASK 0x700u +#define CCM_PRE65_MUX_B_SHIFT 8 +#define CCM_PRE65_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_MUX_B_SHIFT))&CCM_PRE65_MUX_B_MASK) +#define CCM_PRE65_EN_B_MASK 0x1000u +#define CCM_PRE65_EN_B_SHIFT 12 +#define CCM_PRE65_BUSY1_MASK 0x8000u +#define CCM_PRE65_BUSY1_SHIFT 15 +#define CCM_PRE65_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE65_PRE_PODF_A_SHIFT 16 +#define CCM_PRE65_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_PRE_PODF_A_SHIFT))&CCM_PRE65_PRE_PODF_A_MASK) +#define CCM_PRE65_BUSY3_MASK 0x80000u +#define CCM_PRE65_BUSY3_SHIFT 19 +#define CCM_PRE65_MUX_A_MASK 0x7000000u +#define CCM_PRE65_MUX_A_SHIFT 24 +#define CCM_PRE65_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE65_MUX_A_SHIFT))&CCM_PRE65_MUX_A_MASK) +#define CCM_PRE65_EN_A_MASK 0x10000000u +#define CCM_PRE65_EN_A_SHIFT 28 +#define CCM_PRE65_BUSY4_MASK 0x80000000u +#define CCM_PRE65_BUSY4_SHIFT 31 +/* PRE_ROOT65_SET Bit Fields */ +#define CCM_PRE_ROOT65_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT65_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT65_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT65_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT65_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT65_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT65_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT65_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT65_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_MUX_B_SHIFT))&CCM_PRE_ROOT65_SET_MUX_B_MASK) +#define CCM_PRE_ROOT65_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT65_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT65_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT65_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT65_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT65_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT65_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT65_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT65_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT65_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT65_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT65_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT65_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_SET_MUX_A_SHIFT))&CCM_PRE_ROOT65_SET_MUX_A_MASK) +#define CCM_PRE_ROOT65_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT65_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT65_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT65_SET_BUSY4_SHIFT 31 +/* PRE_ROOT65_CLR Bit Fields */ +#define CCM_PRE_ROOT65_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT65_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT65_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT65_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT65_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT65_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT65_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT65_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT65_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT65_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT65_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT65_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT65_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT65_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT65_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT65_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT65_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT65_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT65_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT65_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT65_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT65_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT65_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT65_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT65_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT65_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT65_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT65_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT65_TOG Bit Fields */ +#define CCM_PRE_ROOT65_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT65_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT65_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT65_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT65_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT65_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT65_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT65_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT65_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT65_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT65_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT65_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT65_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT65_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT65_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT65_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT65_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT65_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT65_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT65_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT65_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT65_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT65_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT65_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT65_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT65_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT65_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT65_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT65_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL65 Bit Fields */ +#define CCM_ACCESS_CTRL65_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL65_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL65_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL65_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL65_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL65_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL65_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL65_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL65_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL65_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL65_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL65_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL65_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL65_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL65_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL65_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL65_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL65_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL65_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL65_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL65_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL65_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL65_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL65_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL65_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL65_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL65_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL65_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL65_LOCK_SHIFT 31 +/* ACCESS_CTRL65_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL65_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL65_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL65_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL65_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL65_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL65_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL65_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL65_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL65_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL65_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL65_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL65_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL65_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL65_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL65_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL65_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL65_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL65_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT66 Bit Fields */ +#define CCM_TARGET_ROOT66_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT66_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT66_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_POST_PODF_MASK) +#define CCM_TARGET_ROOT66_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT66_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT66_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT66_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT66_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT66_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT66_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT66_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT66_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT66_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_PRE_PODF_MASK) +#define CCM_TARGET_ROOT66_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT66_MUX_SHIFT 24 +#define CCM_TARGET_ROOT66_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_MUX_SHIFT))&CCM_TARGET_ROOT66_MUX_MASK) +#define CCM_TARGET_ROOT66_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT66_ENABLE_SHIFT 28 +/* TARGET_ROOT66_SET Bit Fields */ +#define CCM_TARGET_ROOT66_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT66_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT66_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT66_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT66_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT66_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT66_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT66_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT66_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT66_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT66_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT66_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT66_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT66_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT66_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT66_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_SET_MUX_SHIFT))&CCM_TARGET_ROOT66_SET_MUX_MASK) +#define CCM_TARGET_ROOT66_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT66_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT66_CLR Bit Fields */ +#define CCM_TARGET_ROOT66_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT66_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT66_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT66_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT66_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT66_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT66_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT66_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT66_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT66_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT66_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT66_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT66_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_CLR_MUX_SHIFT))&CCM_TARGET_ROOT66_CLR_MUX_MASK) +#define CCM_TARGET_ROOT66_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT66_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT66_TOG Bit Fields */ +#define CCM_TARGET_ROOT66_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT66_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT66_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT66_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT66_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT66_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT66_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT66_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT66_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT66_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT66_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT66_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT66_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT66_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT66_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT66_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT66_TOG_MUX_SHIFT))&CCM_TARGET_ROOT66_TOG_MUX_MASK) +#define CCM_TARGET_ROOT66_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT66_TOG_ENABLE_SHIFT 28 +/* POST66 Bit Fields */ +#define CCM_POST66_POST_PODF_MASK 0x3Fu +#define CCM_POST66_POST_PODF_SHIFT 0 +#define CCM_POST66_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST66_POST_PODF_SHIFT))&CCM_POST66_POST_PODF_MASK) +#define CCM_POST66_BUSY1_MASK 0x80u +#define CCM_POST66_BUSY1_SHIFT 7 +#define CCM_POST66_AUTO_PODF_MASK 0x700u +#define CCM_POST66_AUTO_PODF_SHIFT 8 +#define CCM_POST66_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST66_AUTO_PODF_SHIFT))&CCM_POST66_AUTO_PODF_MASK) +#define CCM_POST66_AUTO_EN_MASK 0x1000u +#define CCM_POST66_AUTO_EN_SHIFT 12 +#define CCM_POST66_SLOW_MASK 0x8000u +#define CCM_POST66_SLOW_SHIFT 15 +#define CCM_POST66_SELECT_MASK 0x10000000u +#define CCM_POST66_SELECT_SHIFT 28 +#define CCM_POST66_BUSY2_MASK 0x80000000u +#define CCM_POST66_BUSY2_SHIFT 31 +/* POST_ROOT66_SET Bit Fields */ +#define CCM_POST_ROOT66_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT66_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT66_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_SET_POST_PODF_SHIFT))&CCM_POST_ROOT66_SET_POST_PODF_MASK) +#define CCM_POST_ROOT66_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT66_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT66_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT66_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT66_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT66_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT66_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT66_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT66_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT66_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT66_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT66_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT66_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT66_SET_BUSY2_SHIFT 31 +/* POST_ROOT66_CLR Bit Fields */ +#define CCM_POST_ROOT66_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT66_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT66_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT66_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT66_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT66_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT66_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT66_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT66_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT66_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT66_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT66_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT66_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT66_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT66_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT66_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT66_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT66_CLR_BUSY2_SHIFT 31 +/* POST_ROOT66_TOG Bit Fields */ +#define CCM_POST_ROOT66_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT66_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT66_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT66_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT66_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT66_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT66_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT66_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT66_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT66_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT66_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT66_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT66_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT66_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT66_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT66_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT66_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT66_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT66_TOG_BUSY2_SHIFT 31 +/* PRE66 Bit Fields */ +#define CCM_PRE66_PRE_PODF_B_MASK 0x7u +#define CCM_PRE66_PRE_PODF_B_SHIFT 0 +#define CCM_PRE66_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_PRE_PODF_B_SHIFT))&CCM_PRE66_PRE_PODF_B_MASK) +#define CCM_PRE66_BUSY0_MASK 0x8u +#define CCM_PRE66_BUSY0_SHIFT 3 +#define CCM_PRE66_MUX_B_MASK 0x700u +#define CCM_PRE66_MUX_B_SHIFT 8 +#define CCM_PRE66_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_MUX_B_SHIFT))&CCM_PRE66_MUX_B_MASK) +#define CCM_PRE66_EN_B_MASK 0x1000u +#define CCM_PRE66_EN_B_SHIFT 12 +#define CCM_PRE66_BUSY1_MASK 0x8000u +#define CCM_PRE66_BUSY1_SHIFT 15 +#define CCM_PRE66_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE66_PRE_PODF_A_SHIFT 16 +#define CCM_PRE66_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_PRE_PODF_A_SHIFT))&CCM_PRE66_PRE_PODF_A_MASK) +#define CCM_PRE66_BUSY3_MASK 0x80000u +#define CCM_PRE66_BUSY3_SHIFT 19 +#define CCM_PRE66_MUX_A_MASK 0x7000000u +#define CCM_PRE66_MUX_A_SHIFT 24 +#define CCM_PRE66_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE66_MUX_A_SHIFT))&CCM_PRE66_MUX_A_MASK) +#define CCM_PRE66_EN_A_MASK 0x10000000u +#define CCM_PRE66_EN_A_SHIFT 28 +#define CCM_PRE66_BUSY4_MASK 0x80000000u +#define CCM_PRE66_BUSY4_SHIFT 31 +/* PRE_ROOT66_SET Bit Fields */ +#define CCM_PRE_ROOT66_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT66_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT66_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT66_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT66_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT66_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT66_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT66_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT66_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_MUX_B_SHIFT))&CCM_PRE_ROOT66_SET_MUX_B_MASK) +#define CCM_PRE_ROOT66_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT66_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT66_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT66_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT66_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT66_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT66_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT66_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT66_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT66_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT66_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT66_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT66_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_SET_MUX_A_SHIFT))&CCM_PRE_ROOT66_SET_MUX_A_MASK) +#define CCM_PRE_ROOT66_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT66_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT66_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT66_SET_BUSY4_SHIFT 31 +/* PRE_ROOT66_CLR Bit Fields */ +#define CCM_PRE_ROOT66_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT66_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT66_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT66_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT66_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT66_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT66_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT66_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT66_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT66_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT66_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT66_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT66_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT66_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT66_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT66_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT66_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT66_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT66_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT66_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT66_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT66_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT66_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT66_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT66_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT66_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT66_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT66_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT66_TOG Bit Fields */ +#define CCM_PRE_ROOT66_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT66_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT66_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT66_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT66_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT66_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT66_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT66_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT66_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT66_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT66_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT66_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT66_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT66_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT66_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT66_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT66_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT66_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT66_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT66_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT66_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT66_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT66_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT66_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT66_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT66_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT66_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT66_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT66_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL66 Bit Fields */ +#define CCM_ACCESS_CTRL66_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL66_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL66_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL66_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL66_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL66_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL66_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL66_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL66_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL66_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL66_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL66_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL66_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL66_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL66_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL66_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL66_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL66_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL66_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL66_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL66_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL66_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL66_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL66_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL66_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL66_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL66_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL66_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL66_LOCK_SHIFT 31 +/* ACCESS_CTRL66_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL66_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL66_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL66_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL66_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL66_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL66_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL66_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL66_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL66_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL66_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL66_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL66_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL66_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL66_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL66_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL66_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL66_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL66_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT67 Bit Fields */ +#define CCM_TARGET_ROOT67_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT67_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT67_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_POST_PODF_MASK) +#define CCM_TARGET_ROOT67_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT67_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT67_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT67_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT67_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT67_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT67_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT67_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT67_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT67_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_PRE_PODF_MASK) +#define CCM_TARGET_ROOT67_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT67_MUX_SHIFT 24 +#define CCM_TARGET_ROOT67_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_MUX_SHIFT))&CCM_TARGET_ROOT67_MUX_MASK) +#define CCM_TARGET_ROOT67_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT67_ENABLE_SHIFT 28 +/* TARGET_ROOT67_SET Bit Fields */ +#define CCM_TARGET_ROOT67_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT67_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT67_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT67_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT67_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT67_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT67_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT67_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT67_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT67_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT67_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT67_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT67_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT67_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT67_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT67_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_SET_MUX_SHIFT))&CCM_TARGET_ROOT67_SET_MUX_MASK) +#define CCM_TARGET_ROOT67_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT67_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT67_CLR Bit Fields */ +#define CCM_TARGET_ROOT67_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT67_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT67_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT67_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT67_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT67_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT67_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT67_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT67_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT67_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT67_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT67_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT67_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_CLR_MUX_SHIFT))&CCM_TARGET_ROOT67_CLR_MUX_MASK) +#define CCM_TARGET_ROOT67_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT67_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT67_TOG Bit Fields */ +#define CCM_TARGET_ROOT67_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT67_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT67_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT67_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT67_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT67_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT67_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT67_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT67_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT67_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT67_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT67_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT67_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT67_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT67_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT67_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT67_TOG_MUX_SHIFT))&CCM_TARGET_ROOT67_TOG_MUX_MASK) +#define CCM_TARGET_ROOT67_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT67_TOG_ENABLE_SHIFT 28 +/* POST67 Bit Fields */ +#define CCM_POST67_POST_PODF_MASK 0x3Fu +#define CCM_POST67_POST_PODF_SHIFT 0 +#define CCM_POST67_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST67_POST_PODF_SHIFT))&CCM_POST67_POST_PODF_MASK) +#define CCM_POST67_BUSY1_MASK 0x80u +#define CCM_POST67_BUSY1_SHIFT 7 +#define CCM_POST67_AUTO_PODF_MASK 0x700u +#define CCM_POST67_AUTO_PODF_SHIFT 8 +#define CCM_POST67_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST67_AUTO_PODF_SHIFT))&CCM_POST67_AUTO_PODF_MASK) +#define CCM_POST67_AUTO_EN_MASK 0x1000u +#define CCM_POST67_AUTO_EN_SHIFT 12 +#define CCM_POST67_SLOW_MASK 0x8000u +#define CCM_POST67_SLOW_SHIFT 15 +#define CCM_POST67_SELECT_MASK 0x10000000u +#define CCM_POST67_SELECT_SHIFT 28 +#define CCM_POST67_BUSY2_MASK 0x80000000u +#define CCM_POST67_BUSY2_SHIFT 31 +/* POST_ROOT67_SET Bit Fields */ +#define CCM_POST_ROOT67_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT67_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT67_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_SET_POST_PODF_SHIFT))&CCM_POST_ROOT67_SET_POST_PODF_MASK) +#define CCM_POST_ROOT67_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT67_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT67_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT67_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT67_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT67_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT67_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT67_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT67_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT67_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT67_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT67_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT67_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT67_SET_BUSY2_SHIFT 31 +/* POST_ROOT67_CLR Bit Fields */ +#define CCM_POST_ROOT67_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT67_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT67_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT67_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT67_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT67_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT67_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT67_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT67_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT67_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT67_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT67_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT67_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT67_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT67_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT67_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT67_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT67_CLR_BUSY2_SHIFT 31 +/* POST_ROOT67_TOG Bit Fields */ +#define CCM_POST_ROOT67_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT67_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT67_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT67_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT67_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT67_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT67_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT67_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT67_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT67_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT67_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT67_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT67_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT67_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT67_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT67_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT67_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT67_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT67_TOG_BUSY2_SHIFT 31 +/* PRE67 Bit Fields */ +#define CCM_PRE67_PRE_PODF_B_MASK 0x7u +#define CCM_PRE67_PRE_PODF_B_SHIFT 0 +#define CCM_PRE67_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_PRE_PODF_B_SHIFT))&CCM_PRE67_PRE_PODF_B_MASK) +#define CCM_PRE67_BUSY0_MASK 0x8u +#define CCM_PRE67_BUSY0_SHIFT 3 +#define CCM_PRE67_MUX_B_MASK 0x700u +#define CCM_PRE67_MUX_B_SHIFT 8 +#define CCM_PRE67_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_MUX_B_SHIFT))&CCM_PRE67_MUX_B_MASK) +#define CCM_PRE67_EN_B_MASK 0x1000u +#define CCM_PRE67_EN_B_SHIFT 12 +#define CCM_PRE67_BUSY1_MASK 0x8000u +#define CCM_PRE67_BUSY1_SHIFT 15 +#define CCM_PRE67_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE67_PRE_PODF_A_SHIFT 16 +#define CCM_PRE67_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_PRE_PODF_A_SHIFT))&CCM_PRE67_PRE_PODF_A_MASK) +#define CCM_PRE67_BUSY3_MASK 0x80000u +#define CCM_PRE67_BUSY3_SHIFT 19 +#define CCM_PRE67_MUX_A_MASK 0x7000000u +#define CCM_PRE67_MUX_A_SHIFT 24 +#define CCM_PRE67_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE67_MUX_A_SHIFT))&CCM_PRE67_MUX_A_MASK) +#define CCM_PRE67_EN_A_MASK 0x10000000u +#define CCM_PRE67_EN_A_SHIFT 28 +#define CCM_PRE67_BUSY4_MASK 0x80000000u +#define CCM_PRE67_BUSY4_SHIFT 31 +/* PRE_ROOT67_SET Bit Fields */ +#define CCM_PRE_ROOT67_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT67_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT67_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT67_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT67_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT67_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT67_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT67_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT67_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_MUX_B_SHIFT))&CCM_PRE_ROOT67_SET_MUX_B_MASK) +#define CCM_PRE_ROOT67_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT67_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT67_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT67_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT67_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT67_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT67_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT67_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT67_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT67_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT67_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT67_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT67_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_SET_MUX_A_SHIFT))&CCM_PRE_ROOT67_SET_MUX_A_MASK) +#define CCM_PRE_ROOT67_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT67_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT67_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT67_SET_BUSY4_SHIFT 31 +/* PRE_ROOT67_CLR Bit Fields */ +#define CCM_PRE_ROOT67_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT67_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT67_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT67_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT67_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT67_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT67_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT67_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT67_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT67_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT67_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT67_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT67_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT67_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT67_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT67_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT67_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT67_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT67_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT67_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT67_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT67_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT67_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT67_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT67_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT67_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT67_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT67_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT67_TOG Bit Fields */ +#define CCM_PRE_ROOT67_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT67_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT67_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT67_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT67_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT67_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT67_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT67_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT67_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT67_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT67_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT67_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT67_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT67_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT67_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT67_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT67_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT67_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT67_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT67_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT67_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT67_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT67_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT67_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT67_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT67_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT67_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT67_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT67_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL67 Bit Fields */ +#define CCM_ACCESS_CTRL67_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL67_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL67_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL67_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL67_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL67_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL67_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL67_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL67_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL67_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL67_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL67_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL67_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL67_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL67_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL67_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL67_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL67_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL67_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL67_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL67_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL67_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL67_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL67_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL67_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL67_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL67_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL67_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL67_LOCK_SHIFT 31 +/* ACCESS_CTRL67_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL67_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL67_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL67_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL67_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL67_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL67_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL67_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL67_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL67_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL67_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL67_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL67_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL67_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL67_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL67_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL67_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL67_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL67_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT68 Bit Fields */ +#define CCM_TARGET_ROOT68_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT68_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT68_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_POST_PODF_MASK) +#define CCM_TARGET_ROOT68_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT68_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT68_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT68_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT68_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT68_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT68_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT68_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT68_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT68_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_PRE_PODF_MASK) +#define CCM_TARGET_ROOT68_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT68_MUX_SHIFT 24 +#define CCM_TARGET_ROOT68_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_MUX_SHIFT))&CCM_TARGET_ROOT68_MUX_MASK) +#define CCM_TARGET_ROOT68_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT68_ENABLE_SHIFT 28 +/* TARGET_ROOT68_SET Bit Fields */ +#define CCM_TARGET_ROOT68_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT68_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT68_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT68_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT68_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT68_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT68_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT68_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT68_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT68_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT68_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT68_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT68_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT68_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT68_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT68_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_SET_MUX_SHIFT))&CCM_TARGET_ROOT68_SET_MUX_MASK) +#define CCM_TARGET_ROOT68_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT68_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT68_CLR Bit Fields */ +#define CCM_TARGET_ROOT68_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT68_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT68_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT68_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT68_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT68_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT68_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT68_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT68_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT68_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT68_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT68_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT68_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_CLR_MUX_SHIFT))&CCM_TARGET_ROOT68_CLR_MUX_MASK) +#define CCM_TARGET_ROOT68_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT68_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT68_TOG Bit Fields */ +#define CCM_TARGET_ROOT68_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT68_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT68_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT68_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT68_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT68_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT68_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT68_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT68_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT68_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT68_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT68_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT68_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT68_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT68_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT68_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT68_TOG_MUX_SHIFT))&CCM_TARGET_ROOT68_TOG_MUX_MASK) +#define CCM_TARGET_ROOT68_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT68_TOG_ENABLE_SHIFT 28 +/* POST68 Bit Fields */ +#define CCM_POST68_POST_PODF_MASK 0x3Fu +#define CCM_POST68_POST_PODF_SHIFT 0 +#define CCM_POST68_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST68_POST_PODF_SHIFT))&CCM_POST68_POST_PODF_MASK) +#define CCM_POST68_BUSY1_MASK 0x80u +#define CCM_POST68_BUSY1_SHIFT 7 +#define CCM_POST68_AUTO_PODF_MASK 0x700u +#define CCM_POST68_AUTO_PODF_SHIFT 8 +#define CCM_POST68_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST68_AUTO_PODF_SHIFT))&CCM_POST68_AUTO_PODF_MASK) +#define CCM_POST68_AUTO_EN_MASK 0x1000u +#define CCM_POST68_AUTO_EN_SHIFT 12 +#define CCM_POST68_SLOW_MASK 0x8000u +#define CCM_POST68_SLOW_SHIFT 15 +#define CCM_POST68_SELECT_MASK 0x10000000u +#define CCM_POST68_SELECT_SHIFT 28 +#define CCM_POST68_BUSY2_MASK 0x80000000u +#define CCM_POST68_BUSY2_SHIFT 31 +/* POST_ROOT68_SET Bit Fields */ +#define CCM_POST_ROOT68_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT68_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT68_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_SET_POST_PODF_SHIFT))&CCM_POST_ROOT68_SET_POST_PODF_MASK) +#define CCM_POST_ROOT68_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT68_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT68_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT68_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT68_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT68_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT68_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT68_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT68_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT68_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT68_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT68_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT68_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT68_SET_BUSY2_SHIFT 31 +/* POST_ROOT68_CLR Bit Fields */ +#define CCM_POST_ROOT68_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT68_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT68_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT68_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT68_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT68_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT68_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT68_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT68_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT68_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT68_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT68_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT68_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT68_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT68_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT68_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT68_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT68_CLR_BUSY2_SHIFT 31 +/* POST_ROOT68_TOG Bit Fields */ +#define CCM_POST_ROOT68_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT68_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT68_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT68_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT68_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT68_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT68_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT68_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT68_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT68_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT68_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT68_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT68_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT68_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT68_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT68_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT68_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT68_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT68_TOG_BUSY2_SHIFT 31 +/* PRE68 Bit Fields */ +#define CCM_PRE68_PRE_PODF_B_MASK 0x7u +#define CCM_PRE68_PRE_PODF_B_SHIFT 0 +#define CCM_PRE68_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_PRE_PODF_B_SHIFT))&CCM_PRE68_PRE_PODF_B_MASK) +#define CCM_PRE68_BUSY0_MASK 0x8u +#define CCM_PRE68_BUSY0_SHIFT 3 +#define CCM_PRE68_MUX_B_MASK 0x700u +#define CCM_PRE68_MUX_B_SHIFT 8 +#define CCM_PRE68_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_MUX_B_SHIFT))&CCM_PRE68_MUX_B_MASK) +#define CCM_PRE68_EN_B_MASK 0x1000u +#define CCM_PRE68_EN_B_SHIFT 12 +#define CCM_PRE68_BUSY1_MASK 0x8000u +#define CCM_PRE68_BUSY1_SHIFT 15 +#define CCM_PRE68_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE68_PRE_PODF_A_SHIFT 16 +#define CCM_PRE68_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_PRE_PODF_A_SHIFT))&CCM_PRE68_PRE_PODF_A_MASK) +#define CCM_PRE68_BUSY3_MASK 0x80000u +#define CCM_PRE68_BUSY3_SHIFT 19 +#define CCM_PRE68_MUX_A_MASK 0x7000000u +#define CCM_PRE68_MUX_A_SHIFT 24 +#define CCM_PRE68_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE68_MUX_A_SHIFT))&CCM_PRE68_MUX_A_MASK) +#define CCM_PRE68_EN_A_MASK 0x10000000u +#define CCM_PRE68_EN_A_SHIFT 28 +#define CCM_PRE68_BUSY4_MASK 0x80000000u +#define CCM_PRE68_BUSY4_SHIFT 31 +/* PRE_ROOT68_SET Bit Fields */ +#define CCM_PRE_ROOT68_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT68_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT68_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT68_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT68_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT68_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT68_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT68_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT68_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_MUX_B_SHIFT))&CCM_PRE_ROOT68_SET_MUX_B_MASK) +#define CCM_PRE_ROOT68_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT68_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT68_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT68_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT68_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT68_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT68_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT68_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT68_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT68_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT68_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT68_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT68_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_SET_MUX_A_SHIFT))&CCM_PRE_ROOT68_SET_MUX_A_MASK) +#define CCM_PRE_ROOT68_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT68_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT68_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT68_SET_BUSY4_SHIFT 31 +/* PRE_ROOT68_CLR Bit Fields */ +#define CCM_PRE_ROOT68_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT68_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT68_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT68_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT68_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT68_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT68_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT68_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT68_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT68_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT68_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT68_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT68_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT68_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT68_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT68_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT68_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT68_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT68_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT68_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT68_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT68_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT68_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT68_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT68_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT68_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT68_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT68_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT68_TOG Bit Fields */ +#define CCM_PRE_ROOT68_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT68_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT68_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT68_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT68_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT68_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT68_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT68_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT68_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT68_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT68_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT68_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT68_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT68_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT68_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT68_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT68_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT68_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT68_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT68_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT68_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT68_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT68_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT68_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT68_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT68_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT68_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT68_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT68_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL68 Bit Fields */ +#define CCM_ACCESS_CTRL68_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL68_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL68_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL68_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL68_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL68_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL68_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL68_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL68_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL68_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL68_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL68_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL68_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL68_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL68_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL68_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL68_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL68_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL68_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL68_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL68_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL68_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL68_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL68_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL68_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL68_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL68_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL68_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL68_LOCK_SHIFT 31 +/* ACCESS_CTRL68_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL68_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL68_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL68_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL68_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL68_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL68_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL68_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL68_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL68_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL68_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL68_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL68_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL68_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL68_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL68_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL68_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL68_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL68_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT69 Bit Fields */ +#define CCM_TARGET_ROOT69_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT69_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT69_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_POST_PODF_MASK) +#define CCM_TARGET_ROOT69_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT69_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT69_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT69_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT69_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT69_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT69_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT69_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT69_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT69_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_PRE_PODF_MASK) +#define CCM_TARGET_ROOT69_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT69_MUX_SHIFT 24 +#define CCM_TARGET_ROOT69_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_MUX_SHIFT))&CCM_TARGET_ROOT69_MUX_MASK) +#define CCM_TARGET_ROOT69_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT69_ENABLE_SHIFT 28 +/* TARGET_ROOT69_SET Bit Fields */ +#define CCM_TARGET_ROOT69_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT69_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT69_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT69_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT69_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT69_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT69_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT69_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT69_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT69_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT69_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT69_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT69_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT69_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT69_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT69_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_SET_MUX_SHIFT))&CCM_TARGET_ROOT69_SET_MUX_MASK) +#define CCM_TARGET_ROOT69_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT69_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT69_CLR Bit Fields */ +#define CCM_TARGET_ROOT69_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT69_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT69_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT69_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT69_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT69_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT69_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT69_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT69_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT69_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT69_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT69_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT69_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_CLR_MUX_SHIFT))&CCM_TARGET_ROOT69_CLR_MUX_MASK) +#define CCM_TARGET_ROOT69_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT69_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT69_TOG Bit Fields */ +#define CCM_TARGET_ROOT69_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT69_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT69_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT69_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT69_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT69_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT69_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT69_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT69_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT69_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT69_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT69_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT69_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT69_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT69_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT69_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT69_TOG_MUX_SHIFT))&CCM_TARGET_ROOT69_TOG_MUX_MASK) +#define CCM_TARGET_ROOT69_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT69_TOG_ENABLE_SHIFT 28 +/* POST69 Bit Fields */ +#define CCM_POST69_POST_PODF_MASK 0x3Fu +#define CCM_POST69_POST_PODF_SHIFT 0 +#define CCM_POST69_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST69_POST_PODF_SHIFT))&CCM_POST69_POST_PODF_MASK) +#define CCM_POST69_BUSY1_MASK 0x80u +#define CCM_POST69_BUSY1_SHIFT 7 +#define CCM_POST69_AUTO_PODF_MASK 0x700u +#define CCM_POST69_AUTO_PODF_SHIFT 8 +#define CCM_POST69_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST69_AUTO_PODF_SHIFT))&CCM_POST69_AUTO_PODF_MASK) +#define CCM_POST69_AUTO_EN_MASK 0x1000u +#define CCM_POST69_AUTO_EN_SHIFT 12 +#define CCM_POST69_SLOW_MASK 0x8000u +#define CCM_POST69_SLOW_SHIFT 15 +#define CCM_POST69_SELECT_MASK 0x10000000u +#define CCM_POST69_SELECT_SHIFT 28 +#define CCM_POST69_BUSY2_MASK 0x80000000u +#define CCM_POST69_BUSY2_SHIFT 31 +/* POST_ROOT69_SET Bit Fields */ +#define CCM_POST_ROOT69_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT69_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT69_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_SET_POST_PODF_SHIFT))&CCM_POST_ROOT69_SET_POST_PODF_MASK) +#define CCM_POST_ROOT69_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT69_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT69_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT69_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT69_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT69_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT69_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT69_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT69_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT69_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT69_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT69_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT69_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT69_SET_BUSY2_SHIFT 31 +/* POST_ROOT69_CLR Bit Fields */ +#define CCM_POST_ROOT69_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT69_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT69_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT69_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT69_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT69_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT69_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT69_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT69_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT69_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT69_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT69_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT69_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT69_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT69_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT69_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT69_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT69_CLR_BUSY2_SHIFT 31 +/* POST_ROOT69_TOG Bit Fields */ +#define CCM_POST_ROOT69_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT69_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT69_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT69_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT69_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT69_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT69_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT69_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT69_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT69_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT69_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT69_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT69_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT69_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT69_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT69_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT69_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT69_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT69_TOG_BUSY2_SHIFT 31 +/* PRE69 Bit Fields */ +#define CCM_PRE69_PRE_PODF_B_MASK 0x7u +#define CCM_PRE69_PRE_PODF_B_SHIFT 0 +#define CCM_PRE69_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_PRE_PODF_B_SHIFT))&CCM_PRE69_PRE_PODF_B_MASK) +#define CCM_PRE69_BUSY0_MASK 0x8u +#define CCM_PRE69_BUSY0_SHIFT 3 +#define CCM_PRE69_MUX_B_MASK 0x700u +#define CCM_PRE69_MUX_B_SHIFT 8 +#define CCM_PRE69_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_MUX_B_SHIFT))&CCM_PRE69_MUX_B_MASK) +#define CCM_PRE69_EN_B_MASK 0x1000u +#define CCM_PRE69_EN_B_SHIFT 12 +#define CCM_PRE69_BUSY1_MASK 0x8000u +#define CCM_PRE69_BUSY1_SHIFT 15 +#define CCM_PRE69_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE69_PRE_PODF_A_SHIFT 16 +#define CCM_PRE69_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_PRE_PODF_A_SHIFT))&CCM_PRE69_PRE_PODF_A_MASK) +#define CCM_PRE69_BUSY3_MASK 0x80000u +#define CCM_PRE69_BUSY3_SHIFT 19 +#define CCM_PRE69_MUX_A_MASK 0x7000000u +#define CCM_PRE69_MUX_A_SHIFT 24 +#define CCM_PRE69_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE69_MUX_A_SHIFT))&CCM_PRE69_MUX_A_MASK) +#define CCM_PRE69_EN_A_MASK 0x10000000u +#define CCM_PRE69_EN_A_SHIFT 28 +#define CCM_PRE69_BUSY4_MASK 0x80000000u +#define CCM_PRE69_BUSY4_SHIFT 31 +/* PRE_ROOT69_SET Bit Fields */ +#define CCM_PRE_ROOT69_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT69_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT69_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT69_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT69_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT69_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT69_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT69_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT69_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_MUX_B_SHIFT))&CCM_PRE_ROOT69_SET_MUX_B_MASK) +#define CCM_PRE_ROOT69_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT69_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT69_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT69_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT69_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT69_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT69_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT69_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT69_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT69_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT69_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT69_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT69_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_SET_MUX_A_SHIFT))&CCM_PRE_ROOT69_SET_MUX_A_MASK) +#define CCM_PRE_ROOT69_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT69_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT69_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT69_SET_BUSY4_SHIFT 31 +/* PRE_ROOT69_CLR Bit Fields */ +#define CCM_PRE_ROOT69_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT69_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT69_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT69_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT69_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT69_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT69_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT69_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT69_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT69_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT69_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT69_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT69_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT69_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT69_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT69_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT69_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT69_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT69_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT69_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT69_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT69_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT69_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT69_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT69_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT69_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT69_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT69_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT69_TOG Bit Fields */ +#define CCM_PRE_ROOT69_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT69_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT69_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT69_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT69_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT69_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT69_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT69_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT69_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT69_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT69_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT69_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT69_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT69_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT69_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT69_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT69_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT69_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT69_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT69_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT69_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT69_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT69_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT69_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT69_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT69_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT69_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT69_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT69_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL69 Bit Fields */ +#define CCM_ACCESS_CTRL69_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL69_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL69_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL69_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL69_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL69_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL69_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL69_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL69_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL69_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL69_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL69_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL69_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL69_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL69_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL69_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL69_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL69_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL69_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL69_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL69_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL69_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL69_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL69_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL69_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL69_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL69_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL69_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL69_LOCK_SHIFT 31 +/* ACCESS_CTRL69_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL69_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL69_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL69_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL69_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL69_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL69_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL69_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL69_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL69_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL69_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL69_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL69_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL69_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL69_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL69_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL69_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL69_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL69_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT70 Bit Fields */ +#define CCM_TARGET_ROOT70_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT70_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT70_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_POST_PODF_MASK) +#define CCM_TARGET_ROOT70_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT70_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT70_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT70_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT70_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT70_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT70_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT70_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT70_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT70_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_PRE_PODF_MASK) +#define CCM_TARGET_ROOT70_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT70_MUX_SHIFT 24 +#define CCM_TARGET_ROOT70_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_MUX_SHIFT))&CCM_TARGET_ROOT70_MUX_MASK) +#define CCM_TARGET_ROOT70_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT70_ENABLE_SHIFT 28 +/* TARGET_ROOT70_SET Bit Fields */ +#define CCM_TARGET_ROOT70_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT70_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT70_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT70_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT70_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT70_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT70_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT70_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT70_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT70_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT70_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT70_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT70_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT70_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT70_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT70_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_SET_MUX_SHIFT))&CCM_TARGET_ROOT70_SET_MUX_MASK) +#define CCM_TARGET_ROOT70_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT70_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT70_CLR Bit Fields */ +#define CCM_TARGET_ROOT70_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT70_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT70_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT70_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT70_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT70_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT70_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT70_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT70_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT70_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT70_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT70_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT70_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_CLR_MUX_SHIFT))&CCM_TARGET_ROOT70_CLR_MUX_MASK) +#define CCM_TARGET_ROOT70_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT70_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT70_TOG Bit Fields */ +#define CCM_TARGET_ROOT70_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT70_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT70_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT70_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT70_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT70_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT70_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT70_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT70_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT70_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT70_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT70_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT70_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT70_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT70_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT70_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT70_TOG_MUX_SHIFT))&CCM_TARGET_ROOT70_TOG_MUX_MASK) +#define CCM_TARGET_ROOT70_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT70_TOG_ENABLE_SHIFT 28 +/* POST70 Bit Fields */ +#define CCM_POST70_POST_PODF_MASK 0x3Fu +#define CCM_POST70_POST_PODF_SHIFT 0 +#define CCM_POST70_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST70_POST_PODF_SHIFT))&CCM_POST70_POST_PODF_MASK) +#define CCM_POST70_BUSY1_MASK 0x80u +#define CCM_POST70_BUSY1_SHIFT 7 +#define CCM_POST70_AUTO_PODF_MASK 0x700u +#define CCM_POST70_AUTO_PODF_SHIFT 8 +#define CCM_POST70_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST70_AUTO_PODF_SHIFT))&CCM_POST70_AUTO_PODF_MASK) +#define CCM_POST70_AUTO_EN_MASK 0x1000u +#define CCM_POST70_AUTO_EN_SHIFT 12 +#define CCM_POST70_SLOW_MASK 0x8000u +#define CCM_POST70_SLOW_SHIFT 15 +#define CCM_POST70_SELECT_MASK 0x10000000u +#define CCM_POST70_SELECT_SHIFT 28 +#define CCM_POST70_BUSY2_MASK 0x80000000u +#define CCM_POST70_BUSY2_SHIFT 31 +/* POST_ROOT70_SET Bit Fields */ +#define CCM_POST_ROOT70_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT70_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT70_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_SET_POST_PODF_SHIFT))&CCM_POST_ROOT70_SET_POST_PODF_MASK) +#define CCM_POST_ROOT70_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT70_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT70_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT70_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT70_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT70_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT70_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT70_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT70_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT70_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT70_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT70_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT70_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT70_SET_BUSY2_SHIFT 31 +/* POST_ROOT70_CLR Bit Fields */ +#define CCM_POST_ROOT70_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT70_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT70_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT70_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT70_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT70_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT70_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT70_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT70_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT70_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT70_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT70_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT70_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT70_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT70_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT70_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT70_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT70_CLR_BUSY2_SHIFT 31 +/* POST_ROOT70_TOG Bit Fields */ +#define CCM_POST_ROOT70_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT70_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT70_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT70_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT70_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT70_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT70_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT70_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT70_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT70_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT70_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT70_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT70_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT70_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT70_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT70_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT70_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT70_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT70_TOG_BUSY2_SHIFT 31 +/* PRE70 Bit Fields */ +#define CCM_PRE70_PRE_PODF_B_MASK 0x7u +#define CCM_PRE70_PRE_PODF_B_SHIFT 0 +#define CCM_PRE70_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_PRE_PODF_B_SHIFT))&CCM_PRE70_PRE_PODF_B_MASK) +#define CCM_PRE70_BUSY0_MASK 0x8u +#define CCM_PRE70_BUSY0_SHIFT 3 +#define CCM_PRE70_MUX_B_MASK 0x700u +#define CCM_PRE70_MUX_B_SHIFT 8 +#define CCM_PRE70_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_MUX_B_SHIFT))&CCM_PRE70_MUX_B_MASK) +#define CCM_PRE70_EN_B_MASK 0x1000u +#define CCM_PRE70_EN_B_SHIFT 12 +#define CCM_PRE70_BUSY1_MASK 0x8000u +#define CCM_PRE70_BUSY1_SHIFT 15 +#define CCM_PRE70_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE70_PRE_PODF_A_SHIFT 16 +#define CCM_PRE70_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_PRE_PODF_A_SHIFT))&CCM_PRE70_PRE_PODF_A_MASK) +#define CCM_PRE70_BUSY3_MASK 0x80000u +#define CCM_PRE70_BUSY3_SHIFT 19 +#define CCM_PRE70_MUX_A_MASK 0x7000000u +#define CCM_PRE70_MUX_A_SHIFT 24 +#define CCM_PRE70_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE70_MUX_A_SHIFT))&CCM_PRE70_MUX_A_MASK) +#define CCM_PRE70_EN_A_MASK 0x10000000u +#define CCM_PRE70_EN_A_SHIFT 28 +#define CCM_PRE70_BUSY4_MASK 0x80000000u +#define CCM_PRE70_BUSY4_SHIFT 31 +/* PRE_ROOT70_SET Bit Fields */ +#define CCM_PRE_ROOT70_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT70_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT70_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT70_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT70_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT70_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT70_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT70_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT70_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_MUX_B_SHIFT))&CCM_PRE_ROOT70_SET_MUX_B_MASK) +#define CCM_PRE_ROOT70_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT70_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT70_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT70_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT70_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT70_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT70_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT70_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT70_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT70_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT70_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT70_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT70_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_SET_MUX_A_SHIFT))&CCM_PRE_ROOT70_SET_MUX_A_MASK) +#define CCM_PRE_ROOT70_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT70_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT70_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT70_SET_BUSY4_SHIFT 31 +/* PRE_ROOT70_CLR Bit Fields */ +#define CCM_PRE_ROOT70_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT70_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT70_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT70_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT70_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT70_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT70_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT70_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT70_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT70_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT70_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT70_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT70_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT70_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT70_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT70_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT70_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT70_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT70_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT70_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT70_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT70_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT70_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT70_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT70_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT70_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT70_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT70_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT70_TOG Bit Fields */ +#define CCM_PRE_ROOT70_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT70_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT70_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT70_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT70_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT70_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT70_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT70_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT70_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT70_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT70_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT70_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT70_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT70_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT70_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT70_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT70_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT70_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT70_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT70_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT70_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT70_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT70_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT70_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT70_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT70_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT70_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT70_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT70_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL70 Bit Fields */ +#define CCM_ACCESS_CTRL70_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL70_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL70_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL70_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL70_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL70_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL70_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL70_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL70_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL70_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL70_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL70_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL70_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL70_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL70_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL70_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL70_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL70_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL70_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL70_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL70_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL70_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL70_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL70_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL70_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL70_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL70_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL70_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL70_LOCK_SHIFT 31 +/* ACCESS_CTRL70_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL70_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL70_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL70_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL70_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL70_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL70_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL70_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL70_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL70_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL70_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL70_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL70_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL70_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL70_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL70_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL70_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL70_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL70_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT71 Bit Fields */ +#define CCM_TARGET_ROOT71_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT71_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT71_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_POST_PODF_MASK) +#define CCM_TARGET_ROOT71_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT71_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT71_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT71_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT71_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT71_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT71_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT71_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT71_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT71_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_PRE_PODF_MASK) +#define CCM_TARGET_ROOT71_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT71_MUX_SHIFT 24 +#define CCM_TARGET_ROOT71_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_MUX_SHIFT))&CCM_TARGET_ROOT71_MUX_MASK) +#define CCM_TARGET_ROOT71_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT71_ENABLE_SHIFT 28 +/* TARGET_ROOT71_SET Bit Fields */ +#define CCM_TARGET_ROOT71_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT71_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT71_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT71_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT71_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT71_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT71_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT71_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT71_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT71_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT71_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT71_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT71_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT71_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT71_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT71_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_SET_MUX_SHIFT))&CCM_TARGET_ROOT71_SET_MUX_MASK) +#define CCM_TARGET_ROOT71_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT71_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT71_CLR Bit Fields */ +#define CCM_TARGET_ROOT71_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT71_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT71_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT71_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT71_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT71_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT71_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT71_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT71_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT71_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT71_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT71_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT71_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_CLR_MUX_SHIFT))&CCM_TARGET_ROOT71_CLR_MUX_MASK) +#define CCM_TARGET_ROOT71_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT71_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT71_TOG Bit Fields */ +#define CCM_TARGET_ROOT71_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT71_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT71_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT71_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT71_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT71_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT71_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT71_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT71_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT71_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT71_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT71_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT71_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT71_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT71_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT71_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT71_TOG_MUX_SHIFT))&CCM_TARGET_ROOT71_TOG_MUX_MASK) +#define CCM_TARGET_ROOT71_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT71_TOG_ENABLE_SHIFT 28 +/* POST71 Bit Fields */ +#define CCM_POST71_POST_PODF_MASK 0x3Fu +#define CCM_POST71_POST_PODF_SHIFT 0 +#define CCM_POST71_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST71_POST_PODF_SHIFT))&CCM_POST71_POST_PODF_MASK) +#define CCM_POST71_BUSY1_MASK 0x80u +#define CCM_POST71_BUSY1_SHIFT 7 +#define CCM_POST71_AUTO_PODF_MASK 0x700u +#define CCM_POST71_AUTO_PODF_SHIFT 8 +#define CCM_POST71_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST71_AUTO_PODF_SHIFT))&CCM_POST71_AUTO_PODF_MASK) +#define CCM_POST71_AUTO_EN_MASK 0x1000u +#define CCM_POST71_AUTO_EN_SHIFT 12 +#define CCM_POST71_SLOW_MASK 0x8000u +#define CCM_POST71_SLOW_SHIFT 15 +#define CCM_POST71_SELECT_MASK 0x10000000u +#define CCM_POST71_SELECT_SHIFT 28 +#define CCM_POST71_BUSY2_MASK 0x80000000u +#define CCM_POST71_BUSY2_SHIFT 31 +/* POST_ROOT71_SET Bit Fields */ +#define CCM_POST_ROOT71_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT71_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT71_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_SET_POST_PODF_SHIFT))&CCM_POST_ROOT71_SET_POST_PODF_MASK) +#define CCM_POST_ROOT71_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT71_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT71_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT71_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT71_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT71_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT71_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT71_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT71_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT71_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT71_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT71_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT71_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT71_SET_BUSY2_SHIFT 31 +/* POST_ROOT71_CLR Bit Fields */ +#define CCM_POST_ROOT71_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT71_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT71_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT71_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT71_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT71_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT71_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT71_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT71_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT71_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT71_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT71_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT71_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT71_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT71_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT71_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT71_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT71_CLR_BUSY2_SHIFT 31 +/* POST_ROOT71_TOG Bit Fields */ +#define CCM_POST_ROOT71_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT71_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT71_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT71_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT71_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT71_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT71_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT71_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT71_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT71_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT71_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT71_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT71_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT71_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT71_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT71_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT71_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT71_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT71_TOG_BUSY2_SHIFT 31 +/* PRE71 Bit Fields */ +#define CCM_PRE71_PRE_PODF_B_MASK 0x7u +#define CCM_PRE71_PRE_PODF_B_SHIFT 0 +#define CCM_PRE71_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_PRE_PODF_B_SHIFT))&CCM_PRE71_PRE_PODF_B_MASK) +#define CCM_PRE71_BUSY0_MASK 0x8u +#define CCM_PRE71_BUSY0_SHIFT 3 +#define CCM_PRE71_MUX_B_MASK 0x700u +#define CCM_PRE71_MUX_B_SHIFT 8 +#define CCM_PRE71_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_MUX_B_SHIFT))&CCM_PRE71_MUX_B_MASK) +#define CCM_PRE71_EN_B_MASK 0x1000u +#define CCM_PRE71_EN_B_SHIFT 12 +#define CCM_PRE71_BUSY1_MASK 0x8000u +#define CCM_PRE71_BUSY1_SHIFT 15 +#define CCM_PRE71_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE71_PRE_PODF_A_SHIFT 16 +#define CCM_PRE71_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_PRE_PODF_A_SHIFT))&CCM_PRE71_PRE_PODF_A_MASK) +#define CCM_PRE71_BUSY3_MASK 0x80000u +#define CCM_PRE71_BUSY3_SHIFT 19 +#define CCM_PRE71_MUX_A_MASK 0x7000000u +#define CCM_PRE71_MUX_A_SHIFT 24 +#define CCM_PRE71_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE71_MUX_A_SHIFT))&CCM_PRE71_MUX_A_MASK) +#define CCM_PRE71_EN_A_MASK 0x10000000u +#define CCM_PRE71_EN_A_SHIFT 28 +#define CCM_PRE71_BUSY4_MASK 0x80000000u +#define CCM_PRE71_BUSY4_SHIFT 31 +/* PRE_ROOT71_SET Bit Fields */ +#define CCM_PRE_ROOT71_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT71_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT71_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT71_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT71_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT71_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT71_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT71_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT71_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_MUX_B_SHIFT))&CCM_PRE_ROOT71_SET_MUX_B_MASK) +#define CCM_PRE_ROOT71_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT71_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT71_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT71_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT71_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT71_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT71_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT71_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT71_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT71_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT71_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT71_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT71_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_SET_MUX_A_SHIFT))&CCM_PRE_ROOT71_SET_MUX_A_MASK) +#define CCM_PRE_ROOT71_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT71_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT71_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT71_SET_BUSY4_SHIFT 31 +/* PRE_ROOT71_CLR Bit Fields */ +#define CCM_PRE_ROOT71_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT71_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT71_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT71_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT71_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT71_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT71_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT71_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT71_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT71_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT71_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT71_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT71_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT71_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT71_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT71_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT71_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT71_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT71_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT71_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT71_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT71_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT71_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT71_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT71_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT71_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT71_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT71_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT71_TOG Bit Fields */ +#define CCM_PRE_ROOT71_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT71_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT71_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT71_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT71_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT71_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT71_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT71_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT71_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT71_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT71_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT71_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT71_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT71_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT71_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT71_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT71_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT71_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT71_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT71_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT71_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT71_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT71_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT71_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT71_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT71_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT71_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT71_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT71_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL71 Bit Fields */ +#define CCM_ACCESS_CTRL71_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL71_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL71_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL71_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL71_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL71_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL71_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL71_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL71_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL71_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL71_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL71_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL71_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL71_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL71_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL71_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL71_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL71_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL71_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL71_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL71_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL71_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL71_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL71_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL71_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL71_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL71_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL71_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL71_LOCK_SHIFT 31 +/* ACCESS_CTRL71_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL71_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL71_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL71_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL71_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL71_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL71_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL71_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL71_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL71_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL71_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL71_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL71_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL71_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL71_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL71_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL71_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL71_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL71_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT72 Bit Fields */ +#define CCM_TARGET_ROOT72_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT72_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT72_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_POST_PODF_MASK) +#define CCM_TARGET_ROOT72_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT72_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT72_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT72_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT72_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT72_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT72_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT72_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT72_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT72_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_PRE_PODF_MASK) +#define CCM_TARGET_ROOT72_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT72_MUX_SHIFT 24 +#define CCM_TARGET_ROOT72_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_MUX_SHIFT))&CCM_TARGET_ROOT72_MUX_MASK) +#define CCM_TARGET_ROOT72_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT72_ENABLE_SHIFT 28 +/* TARGET_ROOT72_SET Bit Fields */ +#define CCM_TARGET_ROOT72_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT72_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT72_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT72_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT72_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT72_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT72_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT72_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT72_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT72_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT72_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT72_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT72_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT72_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT72_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT72_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_SET_MUX_SHIFT))&CCM_TARGET_ROOT72_SET_MUX_MASK) +#define CCM_TARGET_ROOT72_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT72_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT72_CLR Bit Fields */ +#define CCM_TARGET_ROOT72_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT72_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT72_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT72_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT72_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT72_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT72_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT72_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT72_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT72_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT72_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT72_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT72_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_CLR_MUX_SHIFT))&CCM_TARGET_ROOT72_CLR_MUX_MASK) +#define CCM_TARGET_ROOT72_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT72_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT72_TOG Bit Fields */ +#define CCM_TARGET_ROOT72_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT72_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT72_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT72_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT72_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT72_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT72_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT72_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT72_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT72_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT72_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT72_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT72_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT72_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT72_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT72_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT72_TOG_MUX_SHIFT))&CCM_TARGET_ROOT72_TOG_MUX_MASK) +#define CCM_TARGET_ROOT72_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT72_TOG_ENABLE_SHIFT 28 +/* POST72 Bit Fields */ +#define CCM_POST72_POST_PODF_MASK 0x3Fu +#define CCM_POST72_POST_PODF_SHIFT 0 +#define CCM_POST72_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST72_POST_PODF_SHIFT))&CCM_POST72_POST_PODF_MASK) +#define CCM_POST72_BUSY1_MASK 0x80u +#define CCM_POST72_BUSY1_SHIFT 7 +#define CCM_POST72_AUTO_PODF_MASK 0x700u +#define CCM_POST72_AUTO_PODF_SHIFT 8 +#define CCM_POST72_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST72_AUTO_PODF_SHIFT))&CCM_POST72_AUTO_PODF_MASK) +#define CCM_POST72_AUTO_EN_MASK 0x1000u +#define CCM_POST72_AUTO_EN_SHIFT 12 +#define CCM_POST72_SLOW_MASK 0x8000u +#define CCM_POST72_SLOW_SHIFT 15 +#define CCM_POST72_SELECT_MASK 0x10000000u +#define CCM_POST72_SELECT_SHIFT 28 +#define CCM_POST72_BUSY2_MASK 0x80000000u +#define CCM_POST72_BUSY2_SHIFT 31 +/* POST_ROOT72_SET Bit Fields */ +#define CCM_POST_ROOT72_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT72_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT72_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_SET_POST_PODF_SHIFT))&CCM_POST_ROOT72_SET_POST_PODF_MASK) +#define CCM_POST_ROOT72_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT72_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT72_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT72_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT72_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT72_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT72_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT72_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT72_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT72_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT72_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT72_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT72_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT72_SET_BUSY2_SHIFT 31 +/* POST_ROOT72_CLR Bit Fields */ +#define CCM_POST_ROOT72_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT72_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT72_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT72_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT72_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT72_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT72_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT72_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT72_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT72_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT72_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT72_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT72_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT72_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT72_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT72_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT72_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT72_CLR_BUSY2_SHIFT 31 +/* POST_ROOT72_TOG Bit Fields */ +#define CCM_POST_ROOT72_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT72_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT72_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT72_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT72_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT72_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT72_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT72_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT72_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT72_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT72_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT72_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT72_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT72_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT72_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT72_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT72_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT72_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT72_TOG_BUSY2_SHIFT 31 +/* PRE72 Bit Fields */ +#define CCM_PRE72_PRE_PODF_B_MASK 0x7u +#define CCM_PRE72_PRE_PODF_B_SHIFT 0 +#define CCM_PRE72_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_PRE_PODF_B_SHIFT))&CCM_PRE72_PRE_PODF_B_MASK) +#define CCM_PRE72_BUSY0_MASK 0x8u +#define CCM_PRE72_BUSY0_SHIFT 3 +#define CCM_PRE72_MUX_B_MASK 0x700u +#define CCM_PRE72_MUX_B_SHIFT 8 +#define CCM_PRE72_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_MUX_B_SHIFT))&CCM_PRE72_MUX_B_MASK) +#define CCM_PRE72_EN_B_MASK 0x1000u +#define CCM_PRE72_EN_B_SHIFT 12 +#define CCM_PRE72_BUSY1_MASK 0x8000u +#define CCM_PRE72_BUSY1_SHIFT 15 +#define CCM_PRE72_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE72_PRE_PODF_A_SHIFT 16 +#define CCM_PRE72_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_PRE_PODF_A_SHIFT))&CCM_PRE72_PRE_PODF_A_MASK) +#define CCM_PRE72_BUSY3_MASK 0x80000u +#define CCM_PRE72_BUSY3_SHIFT 19 +#define CCM_PRE72_MUX_A_MASK 0x7000000u +#define CCM_PRE72_MUX_A_SHIFT 24 +#define CCM_PRE72_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE72_MUX_A_SHIFT))&CCM_PRE72_MUX_A_MASK) +#define CCM_PRE72_EN_A_MASK 0x10000000u +#define CCM_PRE72_EN_A_SHIFT 28 +#define CCM_PRE72_BUSY4_MASK 0x80000000u +#define CCM_PRE72_BUSY4_SHIFT 31 +/* PRE_ROOT72_SET Bit Fields */ +#define CCM_PRE_ROOT72_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT72_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT72_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT72_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT72_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT72_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT72_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT72_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT72_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_MUX_B_SHIFT))&CCM_PRE_ROOT72_SET_MUX_B_MASK) +#define CCM_PRE_ROOT72_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT72_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT72_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT72_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT72_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT72_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT72_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT72_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT72_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT72_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT72_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT72_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT72_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_SET_MUX_A_SHIFT))&CCM_PRE_ROOT72_SET_MUX_A_MASK) +#define CCM_PRE_ROOT72_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT72_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT72_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT72_SET_BUSY4_SHIFT 31 +/* PRE_ROOT72_CLR Bit Fields */ +#define CCM_PRE_ROOT72_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT72_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT72_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT72_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT72_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT72_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT72_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT72_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT72_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT72_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT72_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT72_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT72_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT72_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT72_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT72_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT72_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT72_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT72_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT72_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT72_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT72_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT72_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT72_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT72_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT72_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT72_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT72_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT72_TOG Bit Fields */ +#define CCM_PRE_ROOT72_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT72_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT72_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT72_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT72_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT72_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT72_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT72_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT72_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT72_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT72_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT72_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT72_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT72_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT72_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT72_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT72_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT72_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT72_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT72_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT72_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT72_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT72_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT72_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT72_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT72_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT72_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT72_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT72_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL72 Bit Fields */ +#define CCM_ACCESS_CTRL72_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL72_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL72_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL72_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL72_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL72_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL72_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL72_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL72_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL72_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL72_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL72_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL72_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL72_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL72_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL72_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL72_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL72_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL72_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL72_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL72_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL72_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL72_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL72_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL72_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL72_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL72_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL72_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL72_LOCK_SHIFT 31 +/* ACCESS_CTRL72_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL72_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL72_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL72_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL72_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL72_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL72_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL72_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL72_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL72_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL72_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL72_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL72_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL72_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL72_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL72_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL72_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL72_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL72_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT73 Bit Fields */ +#define CCM_TARGET_ROOT73_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT73_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT73_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_POST_PODF_MASK) +#define CCM_TARGET_ROOT73_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT73_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT73_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT73_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT73_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT73_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT73_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT73_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT73_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT73_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_PRE_PODF_MASK) +#define CCM_TARGET_ROOT73_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT73_MUX_SHIFT 24 +#define CCM_TARGET_ROOT73_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_MUX_SHIFT))&CCM_TARGET_ROOT73_MUX_MASK) +#define CCM_TARGET_ROOT73_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT73_ENABLE_SHIFT 28 +/* TARGET_ROOT73_SET Bit Fields */ +#define CCM_TARGET_ROOT73_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT73_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT73_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT73_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT73_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT73_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT73_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT73_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT73_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT73_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT73_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT73_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT73_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT73_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT73_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT73_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_SET_MUX_SHIFT))&CCM_TARGET_ROOT73_SET_MUX_MASK) +#define CCM_TARGET_ROOT73_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT73_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT73_CLR Bit Fields */ +#define CCM_TARGET_ROOT73_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT73_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT73_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT73_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT73_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT73_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT73_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT73_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT73_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT73_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT73_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT73_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT73_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_CLR_MUX_SHIFT))&CCM_TARGET_ROOT73_CLR_MUX_MASK) +#define CCM_TARGET_ROOT73_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT73_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT73_TOG Bit Fields */ +#define CCM_TARGET_ROOT73_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT73_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT73_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT73_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT73_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT73_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT73_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT73_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT73_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT73_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT73_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT73_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT73_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT73_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT73_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT73_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT73_TOG_MUX_SHIFT))&CCM_TARGET_ROOT73_TOG_MUX_MASK) +#define CCM_TARGET_ROOT73_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT73_TOG_ENABLE_SHIFT 28 +/* POST73 Bit Fields */ +#define CCM_POST73_POST_PODF_MASK 0x3Fu +#define CCM_POST73_POST_PODF_SHIFT 0 +#define CCM_POST73_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST73_POST_PODF_SHIFT))&CCM_POST73_POST_PODF_MASK) +#define CCM_POST73_BUSY1_MASK 0x80u +#define CCM_POST73_BUSY1_SHIFT 7 +#define CCM_POST73_AUTO_PODF_MASK 0x700u +#define CCM_POST73_AUTO_PODF_SHIFT 8 +#define CCM_POST73_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST73_AUTO_PODF_SHIFT))&CCM_POST73_AUTO_PODF_MASK) +#define CCM_POST73_AUTO_EN_MASK 0x1000u +#define CCM_POST73_AUTO_EN_SHIFT 12 +#define CCM_POST73_SLOW_MASK 0x8000u +#define CCM_POST73_SLOW_SHIFT 15 +#define CCM_POST73_SELECT_MASK 0x10000000u +#define CCM_POST73_SELECT_SHIFT 28 +#define CCM_POST73_BUSY2_MASK 0x80000000u +#define CCM_POST73_BUSY2_SHIFT 31 +/* POST_ROOT73_SET Bit Fields */ +#define CCM_POST_ROOT73_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT73_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT73_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_SET_POST_PODF_SHIFT))&CCM_POST_ROOT73_SET_POST_PODF_MASK) +#define CCM_POST_ROOT73_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT73_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT73_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT73_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT73_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT73_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT73_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT73_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT73_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT73_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT73_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT73_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT73_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT73_SET_BUSY2_SHIFT 31 +/* POST_ROOT73_CLR Bit Fields */ +#define CCM_POST_ROOT73_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT73_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT73_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT73_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT73_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT73_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT73_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT73_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT73_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT73_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT73_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT73_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT73_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT73_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT73_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT73_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT73_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT73_CLR_BUSY2_SHIFT 31 +/* POST_ROOT73_TOG Bit Fields */ +#define CCM_POST_ROOT73_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT73_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT73_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT73_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT73_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT73_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT73_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT73_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT73_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT73_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT73_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT73_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT73_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT73_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT73_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT73_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT73_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT73_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT73_TOG_BUSY2_SHIFT 31 +/* PRE73 Bit Fields */ +#define CCM_PRE73_PRE_PODF_B_MASK 0x7u +#define CCM_PRE73_PRE_PODF_B_SHIFT 0 +#define CCM_PRE73_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_PRE_PODF_B_SHIFT))&CCM_PRE73_PRE_PODF_B_MASK) +#define CCM_PRE73_BUSY0_MASK 0x8u +#define CCM_PRE73_BUSY0_SHIFT 3 +#define CCM_PRE73_MUX_B_MASK 0x700u +#define CCM_PRE73_MUX_B_SHIFT 8 +#define CCM_PRE73_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_MUX_B_SHIFT))&CCM_PRE73_MUX_B_MASK) +#define CCM_PRE73_EN_B_MASK 0x1000u +#define CCM_PRE73_EN_B_SHIFT 12 +#define CCM_PRE73_BUSY1_MASK 0x8000u +#define CCM_PRE73_BUSY1_SHIFT 15 +#define CCM_PRE73_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE73_PRE_PODF_A_SHIFT 16 +#define CCM_PRE73_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_PRE_PODF_A_SHIFT))&CCM_PRE73_PRE_PODF_A_MASK) +#define CCM_PRE73_BUSY3_MASK 0x80000u +#define CCM_PRE73_BUSY3_SHIFT 19 +#define CCM_PRE73_MUX_A_MASK 0x7000000u +#define CCM_PRE73_MUX_A_SHIFT 24 +#define CCM_PRE73_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE73_MUX_A_SHIFT))&CCM_PRE73_MUX_A_MASK) +#define CCM_PRE73_EN_A_MASK 0x10000000u +#define CCM_PRE73_EN_A_SHIFT 28 +#define CCM_PRE73_BUSY4_MASK 0x80000000u +#define CCM_PRE73_BUSY4_SHIFT 31 +/* PRE_ROOT73_SET Bit Fields */ +#define CCM_PRE_ROOT73_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT73_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT73_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT73_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT73_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT73_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT73_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT73_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT73_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_MUX_B_SHIFT))&CCM_PRE_ROOT73_SET_MUX_B_MASK) +#define CCM_PRE_ROOT73_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT73_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT73_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT73_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT73_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT73_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT73_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT73_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT73_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT73_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT73_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT73_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT73_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_SET_MUX_A_SHIFT))&CCM_PRE_ROOT73_SET_MUX_A_MASK) +#define CCM_PRE_ROOT73_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT73_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT73_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT73_SET_BUSY4_SHIFT 31 +/* PRE_ROOT73_CLR Bit Fields */ +#define CCM_PRE_ROOT73_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT73_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT73_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT73_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT73_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT73_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT73_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT73_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT73_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT73_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT73_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT73_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT73_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT73_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT73_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT73_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT73_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT73_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT73_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT73_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT73_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT73_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT73_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT73_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT73_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT73_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT73_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT73_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT73_TOG Bit Fields */ +#define CCM_PRE_ROOT73_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT73_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT73_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT73_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT73_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT73_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT73_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT73_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT73_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT73_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT73_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT73_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT73_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT73_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT73_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT73_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT73_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT73_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT73_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT73_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT73_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT73_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT73_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT73_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT73_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT73_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT73_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT73_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT73_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL73 Bit Fields */ +#define CCM_ACCESS_CTRL73_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL73_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL73_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL73_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL73_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL73_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL73_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL73_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL73_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL73_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL73_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL73_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL73_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL73_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL73_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL73_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL73_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL73_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL73_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL73_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL73_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL73_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL73_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL73_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL73_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL73_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL73_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL73_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL73_LOCK_SHIFT 31 +/* ACCESS_CTRL73_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL73_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL73_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL73_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL73_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL73_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL73_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL73_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL73_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL73_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL73_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL73_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL73_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL73_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL73_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL73_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL73_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL73_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL73_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT74 Bit Fields */ +#define CCM_TARGET_ROOT74_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT74_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT74_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_POST_PODF_MASK) +#define CCM_TARGET_ROOT74_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT74_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT74_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT74_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT74_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT74_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT74_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT74_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT74_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT74_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_PRE_PODF_MASK) +#define CCM_TARGET_ROOT74_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT74_MUX_SHIFT 24 +#define CCM_TARGET_ROOT74_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_MUX_SHIFT))&CCM_TARGET_ROOT74_MUX_MASK) +#define CCM_TARGET_ROOT74_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT74_ENABLE_SHIFT 28 +/* TARGET_ROOT74_SET Bit Fields */ +#define CCM_TARGET_ROOT74_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT74_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT74_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT74_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT74_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT74_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT74_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT74_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT74_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT74_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT74_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT74_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT74_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT74_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT74_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT74_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_SET_MUX_SHIFT))&CCM_TARGET_ROOT74_SET_MUX_MASK) +#define CCM_TARGET_ROOT74_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT74_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT74_CLR Bit Fields */ +#define CCM_TARGET_ROOT74_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT74_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT74_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT74_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT74_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT74_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT74_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT74_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT74_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT74_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT74_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT74_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT74_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_CLR_MUX_SHIFT))&CCM_TARGET_ROOT74_CLR_MUX_MASK) +#define CCM_TARGET_ROOT74_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT74_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT74_TOG Bit Fields */ +#define CCM_TARGET_ROOT74_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT74_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT74_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT74_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT74_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT74_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT74_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT74_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT74_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT74_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT74_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT74_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT74_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT74_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT74_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT74_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT74_TOG_MUX_SHIFT))&CCM_TARGET_ROOT74_TOG_MUX_MASK) +#define CCM_TARGET_ROOT74_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT74_TOG_ENABLE_SHIFT 28 +/* POST74 Bit Fields */ +#define CCM_POST74_POST_PODF_MASK 0x3Fu +#define CCM_POST74_POST_PODF_SHIFT 0 +#define CCM_POST74_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST74_POST_PODF_SHIFT))&CCM_POST74_POST_PODF_MASK) +#define CCM_POST74_BUSY1_MASK 0x80u +#define CCM_POST74_BUSY1_SHIFT 7 +#define CCM_POST74_AUTO_PODF_MASK 0x700u +#define CCM_POST74_AUTO_PODF_SHIFT 8 +#define CCM_POST74_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST74_AUTO_PODF_SHIFT))&CCM_POST74_AUTO_PODF_MASK) +#define CCM_POST74_AUTO_EN_MASK 0x1000u +#define CCM_POST74_AUTO_EN_SHIFT 12 +#define CCM_POST74_SLOW_MASK 0x8000u +#define CCM_POST74_SLOW_SHIFT 15 +#define CCM_POST74_SELECT_MASK 0x10000000u +#define CCM_POST74_SELECT_SHIFT 28 +#define CCM_POST74_BUSY2_MASK 0x80000000u +#define CCM_POST74_BUSY2_SHIFT 31 +/* POST_ROOT74_SET Bit Fields */ +#define CCM_POST_ROOT74_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT74_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT74_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_SET_POST_PODF_SHIFT))&CCM_POST_ROOT74_SET_POST_PODF_MASK) +#define CCM_POST_ROOT74_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT74_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT74_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT74_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT74_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT74_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT74_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT74_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT74_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT74_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT74_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT74_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT74_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT74_SET_BUSY2_SHIFT 31 +/* POST_ROOT74_CLR Bit Fields */ +#define CCM_POST_ROOT74_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT74_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT74_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT74_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT74_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT74_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT74_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT74_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT74_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT74_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT74_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT74_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT74_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT74_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT74_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT74_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT74_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT74_CLR_BUSY2_SHIFT 31 +/* POST_ROOT74_TOG Bit Fields */ +#define CCM_POST_ROOT74_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT74_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT74_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT74_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT74_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT74_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT74_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT74_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT74_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT74_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT74_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT74_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT74_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT74_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT74_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT74_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT74_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT74_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT74_TOG_BUSY2_SHIFT 31 +/* PRE74 Bit Fields */ +#define CCM_PRE74_PRE_PODF_B_MASK 0x7u +#define CCM_PRE74_PRE_PODF_B_SHIFT 0 +#define CCM_PRE74_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_PRE_PODF_B_SHIFT))&CCM_PRE74_PRE_PODF_B_MASK) +#define CCM_PRE74_BUSY0_MASK 0x8u +#define CCM_PRE74_BUSY0_SHIFT 3 +#define CCM_PRE74_MUX_B_MASK 0x700u +#define CCM_PRE74_MUX_B_SHIFT 8 +#define CCM_PRE74_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_MUX_B_SHIFT))&CCM_PRE74_MUX_B_MASK) +#define CCM_PRE74_EN_B_MASK 0x1000u +#define CCM_PRE74_EN_B_SHIFT 12 +#define CCM_PRE74_BUSY1_MASK 0x8000u +#define CCM_PRE74_BUSY1_SHIFT 15 +#define CCM_PRE74_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE74_PRE_PODF_A_SHIFT 16 +#define CCM_PRE74_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_PRE_PODF_A_SHIFT))&CCM_PRE74_PRE_PODF_A_MASK) +#define CCM_PRE74_BUSY3_MASK 0x80000u +#define CCM_PRE74_BUSY3_SHIFT 19 +#define CCM_PRE74_MUX_A_MASK 0x7000000u +#define CCM_PRE74_MUX_A_SHIFT 24 +#define CCM_PRE74_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE74_MUX_A_SHIFT))&CCM_PRE74_MUX_A_MASK) +#define CCM_PRE74_EN_A_MASK 0x10000000u +#define CCM_PRE74_EN_A_SHIFT 28 +#define CCM_PRE74_BUSY4_MASK 0x80000000u +#define CCM_PRE74_BUSY4_SHIFT 31 +/* PRE_ROOT74_SET Bit Fields */ +#define CCM_PRE_ROOT74_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT74_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT74_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT74_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT74_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT74_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT74_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT74_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT74_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_MUX_B_SHIFT))&CCM_PRE_ROOT74_SET_MUX_B_MASK) +#define CCM_PRE_ROOT74_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT74_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT74_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT74_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT74_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT74_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT74_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT74_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT74_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT74_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT74_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT74_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT74_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_SET_MUX_A_SHIFT))&CCM_PRE_ROOT74_SET_MUX_A_MASK) +#define CCM_PRE_ROOT74_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT74_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT74_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT74_SET_BUSY4_SHIFT 31 +/* PRE_ROOT74_CLR Bit Fields */ +#define CCM_PRE_ROOT74_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT74_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT74_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT74_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT74_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT74_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT74_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT74_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT74_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT74_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT74_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT74_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT74_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT74_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT74_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT74_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT74_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT74_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT74_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT74_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT74_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT74_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT74_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT74_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT74_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT74_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT74_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT74_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT74_TOG Bit Fields */ +#define CCM_PRE_ROOT74_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT74_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT74_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT74_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT74_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT74_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT74_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT74_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT74_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT74_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT74_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT74_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT74_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT74_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT74_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT74_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT74_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT74_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT74_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT74_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT74_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT74_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT74_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT74_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT74_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT74_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT74_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT74_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT74_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL74 Bit Fields */ +#define CCM_ACCESS_CTRL74_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL74_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL74_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL74_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL74_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL74_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL74_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL74_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL74_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL74_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL74_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL74_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL74_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL74_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL74_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL74_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL74_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL74_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL74_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL74_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL74_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL74_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL74_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL74_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL74_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL74_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL74_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL74_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL74_LOCK_SHIFT 31 +/* ACCESS_CTRL74_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL74_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL74_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL74_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL74_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL74_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL74_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL74_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL74_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL74_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL74_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL74_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL74_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL74_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL74_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL74_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL74_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL74_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL74_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT75 Bit Fields */ +#define CCM_TARGET_ROOT75_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT75_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT75_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_POST_PODF_MASK) +#define CCM_TARGET_ROOT75_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT75_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT75_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT75_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT75_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT75_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT75_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT75_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT75_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT75_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_PRE_PODF_MASK) +#define CCM_TARGET_ROOT75_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT75_MUX_SHIFT 24 +#define CCM_TARGET_ROOT75_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_MUX_SHIFT))&CCM_TARGET_ROOT75_MUX_MASK) +#define CCM_TARGET_ROOT75_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT75_ENABLE_SHIFT 28 +/* TARGET_ROOT75_SET Bit Fields */ +#define CCM_TARGET_ROOT75_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT75_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT75_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT75_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT75_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT75_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT75_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT75_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT75_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT75_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT75_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT75_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT75_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT75_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT75_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT75_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_SET_MUX_SHIFT))&CCM_TARGET_ROOT75_SET_MUX_MASK) +#define CCM_TARGET_ROOT75_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT75_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT75_CLR Bit Fields */ +#define CCM_TARGET_ROOT75_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT75_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT75_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT75_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT75_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT75_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT75_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT75_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT75_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT75_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT75_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT75_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT75_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_CLR_MUX_SHIFT))&CCM_TARGET_ROOT75_CLR_MUX_MASK) +#define CCM_TARGET_ROOT75_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT75_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT75_TOG Bit Fields */ +#define CCM_TARGET_ROOT75_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT75_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT75_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT75_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT75_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT75_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT75_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT75_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT75_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT75_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT75_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT75_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT75_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT75_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT75_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT75_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT75_TOG_MUX_SHIFT))&CCM_TARGET_ROOT75_TOG_MUX_MASK) +#define CCM_TARGET_ROOT75_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT75_TOG_ENABLE_SHIFT 28 +/* POST75 Bit Fields */ +#define CCM_POST75_POST_PODF_MASK 0x3Fu +#define CCM_POST75_POST_PODF_SHIFT 0 +#define CCM_POST75_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST75_POST_PODF_SHIFT))&CCM_POST75_POST_PODF_MASK) +#define CCM_POST75_BUSY1_MASK 0x80u +#define CCM_POST75_BUSY1_SHIFT 7 +#define CCM_POST75_AUTO_PODF_MASK 0x700u +#define CCM_POST75_AUTO_PODF_SHIFT 8 +#define CCM_POST75_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST75_AUTO_PODF_SHIFT))&CCM_POST75_AUTO_PODF_MASK) +#define CCM_POST75_AUTO_EN_MASK 0x1000u +#define CCM_POST75_AUTO_EN_SHIFT 12 +#define CCM_POST75_SLOW_MASK 0x8000u +#define CCM_POST75_SLOW_SHIFT 15 +#define CCM_POST75_SELECT_MASK 0x10000000u +#define CCM_POST75_SELECT_SHIFT 28 +#define CCM_POST75_BUSY2_MASK 0x80000000u +#define CCM_POST75_BUSY2_SHIFT 31 +/* POST_ROOT75_SET Bit Fields */ +#define CCM_POST_ROOT75_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT75_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT75_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_SET_POST_PODF_SHIFT))&CCM_POST_ROOT75_SET_POST_PODF_MASK) +#define CCM_POST_ROOT75_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT75_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT75_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT75_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT75_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT75_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT75_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT75_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT75_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT75_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT75_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT75_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT75_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT75_SET_BUSY2_SHIFT 31 +/* POST_ROOT75_CLR Bit Fields */ +#define CCM_POST_ROOT75_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT75_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT75_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT75_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT75_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT75_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT75_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT75_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT75_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT75_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT75_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT75_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT75_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT75_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT75_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT75_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT75_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT75_CLR_BUSY2_SHIFT 31 +/* POST_ROOT75_TOG Bit Fields */ +#define CCM_POST_ROOT75_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT75_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT75_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT75_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT75_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT75_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT75_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT75_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT75_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT75_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT75_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT75_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT75_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT75_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT75_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT75_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT75_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT75_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT75_TOG_BUSY2_SHIFT 31 +/* PRE75 Bit Fields */ +#define CCM_PRE75_PRE_PODF_B_MASK 0x7u +#define CCM_PRE75_PRE_PODF_B_SHIFT 0 +#define CCM_PRE75_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_PRE_PODF_B_SHIFT))&CCM_PRE75_PRE_PODF_B_MASK) +#define CCM_PRE75_BUSY0_MASK 0x8u +#define CCM_PRE75_BUSY0_SHIFT 3 +#define CCM_PRE75_MUX_B_MASK 0x700u +#define CCM_PRE75_MUX_B_SHIFT 8 +#define CCM_PRE75_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_MUX_B_SHIFT))&CCM_PRE75_MUX_B_MASK) +#define CCM_PRE75_EN_B_MASK 0x1000u +#define CCM_PRE75_EN_B_SHIFT 12 +#define CCM_PRE75_BUSY1_MASK 0x8000u +#define CCM_PRE75_BUSY1_SHIFT 15 +#define CCM_PRE75_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE75_PRE_PODF_A_SHIFT 16 +#define CCM_PRE75_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_PRE_PODF_A_SHIFT))&CCM_PRE75_PRE_PODF_A_MASK) +#define CCM_PRE75_BUSY3_MASK 0x80000u +#define CCM_PRE75_BUSY3_SHIFT 19 +#define CCM_PRE75_MUX_A_MASK 0x7000000u +#define CCM_PRE75_MUX_A_SHIFT 24 +#define CCM_PRE75_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE75_MUX_A_SHIFT))&CCM_PRE75_MUX_A_MASK) +#define CCM_PRE75_EN_A_MASK 0x10000000u +#define CCM_PRE75_EN_A_SHIFT 28 +#define CCM_PRE75_BUSY4_MASK 0x80000000u +#define CCM_PRE75_BUSY4_SHIFT 31 +/* PRE_ROOT75_SET Bit Fields */ +#define CCM_PRE_ROOT75_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT75_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT75_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT75_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT75_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT75_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT75_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT75_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT75_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_MUX_B_SHIFT))&CCM_PRE_ROOT75_SET_MUX_B_MASK) +#define CCM_PRE_ROOT75_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT75_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT75_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT75_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT75_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT75_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT75_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT75_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT75_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT75_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT75_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT75_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT75_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_SET_MUX_A_SHIFT))&CCM_PRE_ROOT75_SET_MUX_A_MASK) +#define CCM_PRE_ROOT75_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT75_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT75_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT75_SET_BUSY4_SHIFT 31 +/* PRE_ROOT75_CLR Bit Fields */ +#define CCM_PRE_ROOT75_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT75_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT75_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT75_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT75_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT75_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT75_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT75_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT75_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT75_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT75_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT75_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT75_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT75_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT75_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT75_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT75_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT75_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT75_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT75_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT75_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT75_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT75_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT75_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT75_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT75_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT75_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT75_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT75_TOG Bit Fields */ +#define CCM_PRE_ROOT75_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT75_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT75_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT75_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT75_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT75_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT75_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT75_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT75_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT75_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT75_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT75_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT75_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT75_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT75_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT75_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT75_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT75_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT75_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT75_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT75_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT75_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT75_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT75_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT75_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT75_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT75_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT75_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT75_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL75 Bit Fields */ +#define CCM_ACCESS_CTRL75_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL75_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL75_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL75_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL75_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL75_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL75_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL75_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL75_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL75_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL75_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL75_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL75_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL75_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL75_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL75_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL75_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL75_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL75_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL75_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL75_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL75_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL75_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL75_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL75_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL75_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL75_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL75_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL75_LOCK_SHIFT 31 +/* ACCESS_CTRL75_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL75_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL75_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL75_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL75_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL75_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL75_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL75_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL75_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL75_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL75_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL75_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL75_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL75_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL75_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL75_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL75_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL75_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL75_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT76 Bit Fields */ +#define CCM_TARGET_ROOT76_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT76_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT76_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_POST_PODF_MASK) +#define CCM_TARGET_ROOT76_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT76_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT76_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT76_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT76_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT76_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT76_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT76_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT76_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT76_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_PRE_PODF_MASK) +#define CCM_TARGET_ROOT76_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT76_MUX_SHIFT 24 +#define CCM_TARGET_ROOT76_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_MUX_SHIFT))&CCM_TARGET_ROOT76_MUX_MASK) +#define CCM_TARGET_ROOT76_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT76_ENABLE_SHIFT 28 +/* TARGET_ROOT76_SET Bit Fields */ +#define CCM_TARGET_ROOT76_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT76_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT76_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT76_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT76_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT76_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT76_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT76_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT76_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT76_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT76_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT76_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT76_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT76_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT76_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT76_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_SET_MUX_SHIFT))&CCM_TARGET_ROOT76_SET_MUX_MASK) +#define CCM_TARGET_ROOT76_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT76_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT76_CLR Bit Fields */ +#define CCM_TARGET_ROOT76_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT76_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT76_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT76_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT76_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT76_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT76_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT76_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT76_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT76_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT76_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT76_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT76_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_CLR_MUX_SHIFT))&CCM_TARGET_ROOT76_CLR_MUX_MASK) +#define CCM_TARGET_ROOT76_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT76_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT76_TOG Bit Fields */ +#define CCM_TARGET_ROOT76_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT76_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT76_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT76_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT76_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT76_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT76_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT76_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT76_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT76_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT76_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT76_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT76_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT76_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT76_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT76_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT76_TOG_MUX_SHIFT))&CCM_TARGET_ROOT76_TOG_MUX_MASK) +#define CCM_TARGET_ROOT76_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT76_TOG_ENABLE_SHIFT 28 +/* POST76 Bit Fields */ +#define CCM_POST76_POST_PODF_MASK 0x3Fu +#define CCM_POST76_POST_PODF_SHIFT 0 +#define CCM_POST76_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST76_POST_PODF_SHIFT))&CCM_POST76_POST_PODF_MASK) +#define CCM_POST76_BUSY1_MASK 0x80u +#define CCM_POST76_BUSY1_SHIFT 7 +#define CCM_POST76_AUTO_PODF_MASK 0x700u +#define CCM_POST76_AUTO_PODF_SHIFT 8 +#define CCM_POST76_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST76_AUTO_PODF_SHIFT))&CCM_POST76_AUTO_PODF_MASK) +#define CCM_POST76_AUTO_EN_MASK 0x1000u +#define CCM_POST76_AUTO_EN_SHIFT 12 +#define CCM_POST76_SLOW_MASK 0x8000u +#define CCM_POST76_SLOW_SHIFT 15 +#define CCM_POST76_SELECT_MASK 0x10000000u +#define CCM_POST76_SELECT_SHIFT 28 +#define CCM_POST76_BUSY2_MASK 0x80000000u +#define CCM_POST76_BUSY2_SHIFT 31 +/* POST_ROOT76_SET Bit Fields */ +#define CCM_POST_ROOT76_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT76_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT76_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_SET_POST_PODF_SHIFT))&CCM_POST_ROOT76_SET_POST_PODF_MASK) +#define CCM_POST_ROOT76_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT76_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT76_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT76_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT76_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT76_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT76_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT76_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT76_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT76_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT76_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT76_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT76_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT76_SET_BUSY2_SHIFT 31 +/* POST_ROOT76_CLR Bit Fields */ +#define CCM_POST_ROOT76_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT76_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT76_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT76_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT76_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT76_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT76_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT76_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT76_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT76_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT76_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT76_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT76_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT76_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT76_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT76_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT76_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT76_CLR_BUSY2_SHIFT 31 +/* POST_ROOT76_TOG Bit Fields */ +#define CCM_POST_ROOT76_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT76_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT76_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT76_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT76_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT76_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT76_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT76_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT76_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT76_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT76_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT76_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT76_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT76_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT76_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT76_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT76_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT76_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT76_TOG_BUSY2_SHIFT 31 +/* PRE76 Bit Fields */ +#define CCM_PRE76_PRE_PODF_B_MASK 0x7u +#define CCM_PRE76_PRE_PODF_B_SHIFT 0 +#define CCM_PRE76_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_PRE_PODF_B_SHIFT))&CCM_PRE76_PRE_PODF_B_MASK) +#define CCM_PRE76_BUSY0_MASK 0x8u +#define CCM_PRE76_BUSY0_SHIFT 3 +#define CCM_PRE76_MUX_B_MASK 0x700u +#define CCM_PRE76_MUX_B_SHIFT 8 +#define CCM_PRE76_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_MUX_B_SHIFT))&CCM_PRE76_MUX_B_MASK) +#define CCM_PRE76_EN_B_MASK 0x1000u +#define CCM_PRE76_EN_B_SHIFT 12 +#define CCM_PRE76_BUSY1_MASK 0x8000u +#define CCM_PRE76_BUSY1_SHIFT 15 +#define CCM_PRE76_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE76_PRE_PODF_A_SHIFT 16 +#define CCM_PRE76_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_PRE_PODF_A_SHIFT))&CCM_PRE76_PRE_PODF_A_MASK) +#define CCM_PRE76_BUSY3_MASK 0x80000u +#define CCM_PRE76_BUSY3_SHIFT 19 +#define CCM_PRE76_MUX_A_MASK 0x7000000u +#define CCM_PRE76_MUX_A_SHIFT 24 +#define CCM_PRE76_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE76_MUX_A_SHIFT))&CCM_PRE76_MUX_A_MASK) +#define CCM_PRE76_EN_A_MASK 0x10000000u +#define CCM_PRE76_EN_A_SHIFT 28 +#define CCM_PRE76_BUSY4_MASK 0x80000000u +#define CCM_PRE76_BUSY4_SHIFT 31 +/* PRE_ROOT76_SET Bit Fields */ +#define CCM_PRE_ROOT76_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT76_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT76_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT76_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT76_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT76_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT76_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT76_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT76_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_MUX_B_SHIFT))&CCM_PRE_ROOT76_SET_MUX_B_MASK) +#define CCM_PRE_ROOT76_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT76_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT76_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT76_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT76_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT76_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT76_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT76_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT76_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT76_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT76_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT76_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT76_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_SET_MUX_A_SHIFT))&CCM_PRE_ROOT76_SET_MUX_A_MASK) +#define CCM_PRE_ROOT76_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT76_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT76_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT76_SET_BUSY4_SHIFT 31 +/* PRE_ROOT76_CLR Bit Fields */ +#define CCM_PRE_ROOT76_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT76_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT76_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT76_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT76_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT76_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT76_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT76_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT76_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT76_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT76_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT76_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT76_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT76_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT76_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT76_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT76_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT76_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT76_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT76_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT76_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT76_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT76_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT76_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT76_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT76_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT76_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT76_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT76_TOG Bit Fields */ +#define CCM_PRE_ROOT76_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT76_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT76_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT76_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT76_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT76_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT76_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT76_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT76_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT76_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT76_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT76_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT76_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT76_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT76_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT76_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT76_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT76_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT76_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT76_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT76_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT76_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT76_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT76_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT76_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT76_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT76_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT76_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT76_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL76 Bit Fields */ +#define CCM_ACCESS_CTRL76_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL76_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL76_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL76_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL76_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL76_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL76_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL76_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL76_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL76_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL76_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL76_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL76_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL76_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL76_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL76_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL76_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL76_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL76_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL76_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL76_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL76_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL76_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL76_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL76_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL76_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL76_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL76_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL76_LOCK_SHIFT 31 +/* ACCESS_CTRL76_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL76_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL76_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL76_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL76_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL76_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL76_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL76_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL76_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL76_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL76_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL76_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL76_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL76_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL76_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL76_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL76_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL76_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL76_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT77 Bit Fields */ +#define CCM_TARGET_ROOT77_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT77_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT77_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_POST_PODF_MASK) +#define CCM_TARGET_ROOT77_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT77_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT77_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT77_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT77_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT77_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT77_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT77_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT77_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT77_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_PRE_PODF_MASK) +#define CCM_TARGET_ROOT77_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT77_MUX_SHIFT 24 +#define CCM_TARGET_ROOT77_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_MUX_SHIFT))&CCM_TARGET_ROOT77_MUX_MASK) +#define CCM_TARGET_ROOT77_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT77_ENABLE_SHIFT 28 +/* TARGET_ROOT77_SET Bit Fields */ +#define CCM_TARGET_ROOT77_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT77_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT77_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT77_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT77_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT77_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT77_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT77_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT77_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT77_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT77_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT77_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT77_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT77_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT77_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT77_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_SET_MUX_SHIFT))&CCM_TARGET_ROOT77_SET_MUX_MASK) +#define CCM_TARGET_ROOT77_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT77_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT77_CLR Bit Fields */ +#define CCM_TARGET_ROOT77_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT77_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT77_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT77_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT77_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT77_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT77_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT77_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT77_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT77_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT77_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT77_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT77_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_CLR_MUX_SHIFT))&CCM_TARGET_ROOT77_CLR_MUX_MASK) +#define CCM_TARGET_ROOT77_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT77_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT77_TOG Bit Fields */ +#define CCM_TARGET_ROOT77_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT77_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT77_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT77_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT77_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT77_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT77_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT77_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT77_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT77_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT77_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT77_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT77_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT77_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT77_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT77_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT77_TOG_MUX_SHIFT))&CCM_TARGET_ROOT77_TOG_MUX_MASK) +#define CCM_TARGET_ROOT77_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT77_TOG_ENABLE_SHIFT 28 +/* POST77 Bit Fields */ +#define CCM_POST77_POST_PODF_MASK 0x3Fu +#define CCM_POST77_POST_PODF_SHIFT 0 +#define CCM_POST77_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST77_POST_PODF_SHIFT))&CCM_POST77_POST_PODF_MASK) +#define CCM_POST77_BUSY1_MASK 0x80u +#define CCM_POST77_BUSY1_SHIFT 7 +#define CCM_POST77_AUTO_PODF_MASK 0x700u +#define CCM_POST77_AUTO_PODF_SHIFT 8 +#define CCM_POST77_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST77_AUTO_PODF_SHIFT))&CCM_POST77_AUTO_PODF_MASK) +#define CCM_POST77_AUTO_EN_MASK 0x1000u +#define CCM_POST77_AUTO_EN_SHIFT 12 +#define CCM_POST77_SLOW_MASK 0x8000u +#define CCM_POST77_SLOW_SHIFT 15 +#define CCM_POST77_SELECT_MASK 0x10000000u +#define CCM_POST77_SELECT_SHIFT 28 +#define CCM_POST77_BUSY2_MASK 0x80000000u +#define CCM_POST77_BUSY2_SHIFT 31 +/* POST_ROOT77_SET Bit Fields */ +#define CCM_POST_ROOT77_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT77_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT77_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_SET_POST_PODF_SHIFT))&CCM_POST_ROOT77_SET_POST_PODF_MASK) +#define CCM_POST_ROOT77_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT77_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT77_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT77_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT77_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT77_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT77_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT77_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT77_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT77_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT77_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT77_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT77_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT77_SET_BUSY2_SHIFT 31 +/* POST_ROOT77_CLR Bit Fields */ +#define CCM_POST_ROOT77_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT77_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT77_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT77_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT77_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT77_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT77_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT77_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT77_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT77_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT77_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT77_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT77_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT77_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT77_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT77_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT77_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT77_CLR_BUSY2_SHIFT 31 +/* POST_ROOT77_TOG Bit Fields */ +#define CCM_POST_ROOT77_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT77_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT77_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT77_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT77_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT77_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT77_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT77_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT77_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT77_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT77_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT77_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT77_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT77_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT77_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT77_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT77_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT77_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT77_TOG_BUSY2_SHIFT 31 +/* PRE77 Bit Fields */ +#define CCM_PRE77_PRE_PODF_B_MASK 0x7u +#define CCM_PRE77_PRE_PODF_B_SHIFT 0 +#define CCM_PRE77_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_PRE_PODF_B_SHIFT))&CCM_PRE77_PRE_PODF_B_MASK) +#define CCM_PRE77_BUSY0_MASK 0x8u +#define CCM_PRE77_BUSY0_SHIFT 3 +#define CCM_PRE77_MUX_B_MASK 0x700u +#define CCM_PRE77_MUX_B_SHIFT 8 +#define CCM_PRE77_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_MUX_B_SHIFT))&CCM_PRE77_MUX_B_MASK) +#define CCM_PRE77_EN_B_MASK 0x1000u +#define CCM_PRE77_EN_B_SHIFT 12 +#define CCM_PRE77_BUSY1_MASK 0x8000u +#define CCM_PRE77_BUSY1_SHIFT 15 +#define CCM_PRE77_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE77_PRE_PODF_A_SHIFT 16 +#define CCM_PRE77_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_PRE_PODF_A_SHIFT))&CCM_PRE77_PRE_PODF_A_MASK) +#define CCM_PRE77_BUSY3_MASK 0x80000u +#define CCM_PRE77_BUSY3_SHIFT 19 +#define CCM_PRE77_MUX_A_MASK 0x7000000u +#define CCM_PRE77_MUX_A_SHIFT 24 +#define CCM_PRE77_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE77_MUX_A_SHIFT))&CCM_PRE77_MUX_A_MASK) +#define CCM_PRE77_EN_A_MASK 0x10000000u +#define CCM_PRE77_EN_A_SHIFT 28 +#define CCM_PRE77_BUSY4_MASK 0x80000000u +#define CCM_PRE77_BUSY4_SHIFT 31 +/* PRE_ROOT77_SET Bit Fields */ +#define CCM_PRE_ROOT77_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT77_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT77_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT77_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT77_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT77_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT77_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT77_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT77_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_MUX_B_SHIFT))&CCM_PRE_ROOT77_SET_MUX_B_MASK) +#define CCM_PRE_ROOT77_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT77_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT77_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT77_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT77_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT77_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT77_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT77_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT77_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT77_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT77_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT77_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT77_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_SET_MUX_A_SHIFT))&CCM_PRE_ROOT77_SET_MUX_A_MASK) +#define CCM_PRE_ROOT77_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT77_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT77_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT77_SET_BUSY4_SHIFT 31 +/* PRE_ROOT77_CLR Bit Fields */ +#define CCM_PRE_ROOT77_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT77_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT77_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT77_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT77_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT77_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT77_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT77_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT77_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT77_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT77_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT77_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT77_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT77_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT77_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT77_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT77_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT77_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT77_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT77_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT77_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT77_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT77_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT77_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT77_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT77_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT77_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT77_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT77_TOG Bit Fields */ +#define CCM_PRE_ROOT77_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT77_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT77_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT77_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT77_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT77_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT77_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT77_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT77_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT77_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT77_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT77_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT77_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT77_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT77_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT77_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT77_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT77_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT77_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT77_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT77_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT77_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT77_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT77_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT77_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT77_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT77_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT77_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT77_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL77 Bit Fields */ +#define CCM_ACCESS_CTRL77_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL77_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL77_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL77_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL77_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL77_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL77_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL77_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL77_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL77_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL77_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL77_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL77_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL77_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL77_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL77_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL77_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL77_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL77_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL77_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL77_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL77_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL77_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL77_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL77_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL77_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL77_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL77_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL77_LOCK_SHIFT 31 +/* ACCESS_CTRL77_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL77_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL77_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL77_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL77_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL77_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL77_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL77_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL77_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL77_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL77_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL77_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL77_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL77_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL77_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL77_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL77_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL77_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL77_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT78 Bit Fields */ +#define CCM_TARGET_ROOT78_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT78_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT78_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_POST_PODF_MASK) +#define CCM_TARGET_ROOT78_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT78_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT78_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT78_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT78_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT78_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT78_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT78_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT78_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT78_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_PRE_PODF_MASK) +#define CCM_TARGET_ROOT78_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT78_MUX_SHIFT 24 +#define CCM_TARGET_ROOT78_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_MUX_SHIFT))&CCM_TARGET_ROOT78_MUX_MASK) +#define CCM_TARGET_ROOT78_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT78_ENABLE_SHIFT 28 +/* TARGET_ROOT78_SET Bit Fields */ +#define CCM_TARGET_ROOT78_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT78_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT78_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT78_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT78_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT78_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT78_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT78_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT78_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT78_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT78_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT78_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT78_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT78_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT78_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT78_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_SET_MUX_SHIFT))&CCM_TARGET_ROOT78_SET_MUX_MASK) +#define CCM_TARGET_ROOT78_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT78_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT78_CLR Bit Fields */ +#define CCM_TARGET_ROOT78_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT78_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT78_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT78_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT78_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT78_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT78_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT78_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT78_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT78_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT78_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT78_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT78_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_CLR_MUX_SHIFT))&CCM_TARGET_ROOT78_CLR_MUX_MASK) +#define CCM_TARGET_ROOT78_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT78_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT78_TOG Bit Fields */ +#define CCM_TARGET_ROOT78_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT78_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT78_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT78_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT78_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT78_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT78_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT78_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT78_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT78_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT78_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT78_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT78_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT78_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT78_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT78_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT78_TOG_MUX_SHIFT))&CCM_TARGET_ROOT78_TOG_MUX_MASK) +#define CCM_TARGET_ROOT78_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT78_TOG_ENABLE_SHIFT 28 +/* POST78 Bit Fields */ +#define CCM_POST78_POST_PODF_MASK 0x3Fu +#define CCM_POST78_POST_PODF_SHIFT 0 +#define CCM_POST78_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST78_POST_PODF_SHIFT))&CCM_POST78_POST_PODF_MASK) +#define CCM_POST78_BUSY1_MASK 0x80u +#define CCM_POST78_BUSY1_SHIFT 7 +#define CCM_POST78_AUTO_PODF_MASK 0x700u +#define CCM_POST78_AUTO_PODF_SHIFT 8 +#define CCM_POST78_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST78_AUTO_PODF_SHIFT))&CCM_POST78_AUTO_PODF_MASK) +#define CCM_POST78_AUTO_EN_MASK 0x1000u +#define CCM_POST78_AUTO_EN_SHIFT 12 +#define CCM_POST78_SLOW_MASK 0x8000u +#define CCM_POST78_SLOW_SHIFT 15 +#define CCM_POST78_SELECT_MASK 0x10000000u +#define CCM_POST78_SELECT_SHIFT 28 +#define CCM_POST78_BUSY2_MASK 0x80000000u +#define CCM_POST78_BUSY2_SHIFT 31 +/* POST_ROOT78_SET Bit Fields */ +#define CCM_POST_ROOT78_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT78_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT78_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_SET_POST_PODF_SHIFT))&CCM_POST_ROOT78_SET_POST_PODF_MASK) +#define CCM_POST_ROOT78_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT78_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT78_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT78_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT78_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT78_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT78_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT78_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT78_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT78_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT78_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT78_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT78_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT78_SET_BUSY2_SHIFT 31 +/* POST_ROOT78_CLR Bit Fields */ +#define CCM_POST_ROOT78_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT78_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT78_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT78_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT78_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT78_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT78_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT78_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT78_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT78_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT78_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT78_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT78_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT78_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT78_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT78_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT78_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT78_CLR_BUSY2_SHIFT 31 +/* POST_ROOT78_TOG Bit Fields */ +#define CCM_POST_ROOT78_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT78_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT78_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT78_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT78_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT78_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT78_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT78_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT78_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT78_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT78_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT78_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT78_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT78_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT78_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT78_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT78_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT78_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT78_TOG_BUSY2_SHIFT 31 +/* PRE78 Bit Fields */ +#define CCM_PRE78_PRE_PODF_B_MASK 0x7u +#define CCM_PRE78_PRE_PODF_B_SHIFT 0 +#define CCM_PRE78_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_PRE_PODF_B_SHIFT))&CCM_PRE78_PRE_PODF_B_MASK) +#define CCM_PRE78_BUSY0_MASK 0x8u +#define CCM_PRE78_BUSY0_SHIFT 3 +#define CCM_PRE78_MUX_B_MASK 0x700u +#define CCM_PRE78_MUX_B_SHIFT 8 +#define CCM_PRE78_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_MUX_B_SHIFT))&CCM_PRE78_MUX_B_MASK) +#define CCM_PRE78_EN_B_MASK 0x1000u +#define CCM_PRE78_EN_B_SHIFT 12 +#define CCM_PRE78_BUSY1_MASK 0x8000u +#define CCM_PRE78_BUSY1_SHIFT 15 +#define CCM_PRE78_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE78_PRE_PODF_A_SHIFT 16 +#define CCM_PRE78_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_PRE_PODF_A_SHIFT))&CCM_PRE78_PRE_PODF_A_MASK) +#define CCM_PRE78_BUSY3_MASK 0x80000u +#define CCM_PRE78_BUSY3_SHIFT 19 +#define CCM_PRE78_MUX_A_MASK 0x7000000u +#define CCM_PRE78_MUX_A_SHIFT 24 +#define CCM_PRE78_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE78_MUX_A_SHIFT))&CCM_PRE78_MUX_A_MASK) +#define CCM_PRE78_EN_A_MASK 0x10000000u +#define CCM_PRE78_EN_A_SHIFT 28 +#define CCM_PRE78_BUSY4_MASK 0x80000000u +#define CCM_PRE78_BUSY4_SHIFT 31 +/* PRE_ROOT78_SET Bit Fields */ +#define CCM_PRE_ROOT78_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT78_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT78_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT78_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT78_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT78_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT78_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT78_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT78_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_MUX_B_SHIFT))&CCM_PRE_ROOT78_SET_MUX_B_MASK) +#define CCM_PRE_ROOT78_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT78_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT78_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT78_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT78_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT78_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT78_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT78_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT78_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT78_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT78_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT78_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT78_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_SET_MUX_A_SHIFT))&CCM_PRE_ROOT78_SET_MUX_A_MASK) +#define CCM_PRE_ROOT78_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT78_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT78_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT78_SET_BUSY4_SHIFT 31 +/* PRE_ROOT78_CLR Bit Fields */ +#define CCM_PRE_ROOT78_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT78_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT78_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT78_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT78_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT78_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT78_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT78_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT78_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT78_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT78_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT78_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT78_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT78_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT78_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT78_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT78_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT78_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT78_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT78_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT78_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT78_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT78_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT78_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT78_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT78_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT78_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT78_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT78_TOG Bit Fields */ +#define CCM_PRE_ROOT78_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT78_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT78_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT78_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT78_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT78_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT78_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT78_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT78_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT78_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT78_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT78_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT78_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT78_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT78_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT78_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT78_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT78_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT78_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT78_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT78_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT78_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT78_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT78_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT78_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT78_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT78_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT78_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT78_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL78 Bit Fields */ +#define CCM_ACCESS_CTRL78_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL78_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL78_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL78_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL78_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL78_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL78_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL78_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL78_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL78_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL78_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL78_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL78_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL78_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL78_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL78_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL78_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL78_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL78_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL78_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL78_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL78_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL78_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL78_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL78_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL78_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL78_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL78_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL78_LOCK_SHIFT 31 +/* ACCESS_CTRL78_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL78_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL78_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL78_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL78_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL78_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL78_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL78_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL78_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL78_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL78_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL78_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL78_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL78_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL78_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL78_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL78_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL78_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL78_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT79 Bit Fields */ +#define CCM_TARGET_ROOT79_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT79_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT79_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_POST_PODF_MASK) +#define CCM_TARGET_ROOT79_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT79_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT79_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT79_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT79_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT79_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT79_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT79_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT79_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT79_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_PRE_PODF_MASK) +#define CCM_TARGET_ROOT79_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT79_MUX_SHIFT 24 +#define CCM_TARGET_ROOT79_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_MUX_SHIFT))&CCM_TARGET_ROOT79_MUX_MASK) +#define CCM_TARGET_ROOT79_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT79_ENABLE_SHIFT 28 +/* TARGET_ROOT79_SET Bit Fields */ +#define CCM_TARGET_ROOT79_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT79_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT79_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT79_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT79_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT79_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT79_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT79_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT79_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT79_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT79_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT79_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT79_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT79_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT79_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT79_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_SET_MUX_SHIFT))&CCM_TARGET_ROOT79_SET_MUX_MASK) +#define CCM_TARGET_ROOT79_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT79_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT79_CLR Bit Fields */ +#define CCM_TARGET_ROOT79_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT79_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT79_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT79_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT79_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT79_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT79_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT79_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT79_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT79_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT79_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT79_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT79_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_CLR_MUX_SHIFT))&CCM_TARGET_ROOT79_CLR_MUX_MASK) +#define CCM_TARGET_ROOT79_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT79_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT79_TOG Bit Fields */ +#define CCM_TARGET_ROOT79_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT79_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT79_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT79_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT79_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT79_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT79_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT79_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT79_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT79_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT79_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT79_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT79_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT79_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT79_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT79_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT79_TOG_MUX_SHIFT))&CCM_TARGET_ROOT79_TOG_MUX_MASK) +#define CCM_TARGET_ROOT79_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT79_TOG_ENABLE_SHIFT 28 +/* POST79 Bit Fields */ +#define CCM_POST79_POST_PODF_MASK 0x3Fu +#define CCM_POST79_POST_PODF_SHIFT 0 +#define CCM_POST79_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST79_POST_PODF_SHIFT))&CCM_POST79_POST_PODF_MASK) +#define CCM_POST79_BUSY1_MASK 0x80u +#define CCM_POST79_BUSY1_SHIFT 7 +#define CCM_POST79_AUTO_PODF_MASK 0x700u +#define CCM_POST79_AUTO_PODF_SHIFT 8 +#define CCM_POST79_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST79_AUTO_PODF_SHIFT))&CCM_POST79_AUTO_PODF_MASK) +#define CCM_POST79_AUTO_EN_MASK 0x1000u +#define CCM_POST79_AUTO_EN_SHIFT 12 +#define CCM_POST79_SLOW_MASK 0x8000u +#define CCM_POST79_SLOW_SHIFT 15 +#define CCM_POST79_SELECT_MASK 0x10000000u +#define CCM_POST79_SELECT_SHIFT 28 +#define CCM_POST79_BUSY2_MASK 0x80000000u +#define CCM_POST79_BUSY2_SHIFT 31 +/* POST_ROOT79_SET Bit Fields */ +#define CCM_POST_ROOT79_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT79_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT79_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_SET_POST_PODF_SHIFT))&CCM_POST_ROOT79_SET_POST_PODF_MASK) +#define CCM_POST_ROOT79_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT79_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT79_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT79_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT79_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT79_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT79_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT79_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT79_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT79_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT79_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT79_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT79_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT79_SET_BUSY2_SHIFT 31 +/* POST_ROOT79_CLR Bit Fields */ +#define CCM_POST_ROOT79_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT79_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT79_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT79_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT79_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT79_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT79_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT79_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT79_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT79_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT79_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT79_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT79_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT79_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT79_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT79_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT79_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT79_CLR_BUSY2_SHIFT 31 +/* POST_ROOT79_TOG Bit Fields */ +#define CCM_POST_ROOT79_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT79_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT79_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT79_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT79_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT79_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT79_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT79_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT79_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT79_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT79_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT79_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT79_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT79_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT79_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT79_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT79_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT79_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT79_TOG_BUSY2_SHIFT 31 +/* PRE79 Bit Fields */ +#define CCM_PRE79_PRE_PODF_B_MASK 0x7u +#define CCM_PRE79_PRE_PODF_B_SHIFT 0 +#define CCM_PRE79_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_PRE_PODF_B_SHIFT))&CCM_PRE79_PRE_PODF_B_MASK) +#define CCM_PRE79_BUSY0_MASK 0x8u +#define CCM_PRE79_BUSY0_SHIFT 3 +#define CCM_PRE79_MUX_B_MASK 0x700u +#define CCM_PRE79_MUX_B_SHIFT 8 +#define CCM_PRE79_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_MUX_B_SHIFT))&CCM_PRE79_MUX_B_MASK) +#define CCM_PRE79_EN_B_MASK 0x1000u +#define CCM_PRE79_EN_B_SHIFT 12 +#define CCM_PRE79_BUSY1_MASK 0x8000u +#define CCM_PRE79_BUSY1_SHIFT 15 +#define CCM_PRE79_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE79_PRE_PODF_A_SHIFT 16 +#define CCM_PRE79_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_PRE_PODF_A_SHIFT))&CCM_PRE79_PRE_PODF_A_MASK) +#define CCM_PRE79_BUSY3_MASK 0x80000u +#define CCM_PRE79_BUSY3_SHIFT 19 +#define CCM_PRE79_MUX_A_MASK 0x7000000u +#define CCM_PRE79_MUX_A_SHIFT 24 +#define CCM_PRE79_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE79_MUX_A_SHIFT))&CCM_PRE79_MUX_A_MASK) +#define CCM_PRE79_EN_A_MASK 0x10000000u +#define CCM_PRE79_EN_A_SHIFT 28 +#define CCM_PRE79_BUSY4_MASK 0x80000000u +#define CCM_PRE79_BUSY4_SHIFT 31 +/* PRE_ROOT79_SET Bit Fields */ +#define CCM_PRE_ROOT79_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT79_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT79_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT79_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT79_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT79_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT79_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT79_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT79_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_MUX_B_SHIFT))&CCM_PRE_ROOT79_SET_MUX_B_MASK) +#define CCM_PRE_ROOT79_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT79_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT79_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT79_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT79_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT79_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT79_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT79_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT79_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT79_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT79_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT79_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT79_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_SET_MUX_A_SHIFT))&CCM_PRE_ROOT79_SET_MUX_A_MASK) +#define CCM_PRE_ROOT79_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT79_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT79_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT79_SET_BUSY4_SHIFT 31 +/* PRE_ROOT79_CLR Bit Fields */ +#define CCM_PRE_ROOT79_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT79_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT79_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT79_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT79_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT79_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT79_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT79_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT79_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT79_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT79_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT79_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT79_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT79_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT79_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT79_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT79_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT79_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT79_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT79_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT79_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT79_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT79_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT79_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT79_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT79_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT79_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT79_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT79_TOG Bit Fields */ +#define CCM_PRE_ROOT79_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT79_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT79_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT79_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT79_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT79_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT79_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT79_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT79_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT79_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT79_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT79_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT79_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT79_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT79_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT79_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT79_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT79_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT79_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT79_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT79_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT79_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT79_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT79_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT79_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT79_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT79_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT79_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT79_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL79 Bit Fields */ +#define CCM_ACCESS_CTRL79_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL79_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL79_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL79_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL79_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL79_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL79_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL79_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL79_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL79_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL79_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL79_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL79_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL79_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL79_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL79_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL79_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL79_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL79_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL79_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL79_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL79_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL79_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL79_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL79_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL79_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL79_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL79_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL79_LOCK_SHIFT 31 +/* ACCESS_CTRL79_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL79_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL79_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL79_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL79_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL79_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL79_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL79_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL79_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL79_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL79_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL79_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL79_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL79_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL79_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL79_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL79_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL79_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL79_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT80 Bit Fields */ +#define CCM_TARGET_ROOT80_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT80_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT80_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_POST_PODF_MASK) +#define CCM_TARGET_ROOT80_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT80_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT80_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT80_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT80_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT80_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT80_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT80_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT80_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT80_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_PRE_PODF_MASK) +#define CCM_TARGET_ROOT80_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT80_MUX_SHIFT 24 +#define CCM_TARGET_ROOT80_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_MUX_SHIFT))&CCM_TARGET_ROOT80_MUX_MASK) +#define CCM_TARGET_ROOT80_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT80_ENABLE_SHIFT 28 +/* TARGET_ROOT80_SET Bit Fields */ +#define CCM_TARGET_ROOT80_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT80_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT80_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT80_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT80_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT80_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT80_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT80_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT80_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT80_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT80_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT80_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT80_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT80_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT80_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT80_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_SET_MUX_SHIFT))&CCM_TARGET_ROOT80_SET_MUX_MASK) +#define CCM_TARGET_ROOT80_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT80_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT80_CLR Bit Fields */ +#define CCM_TARGET_ROOT80_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT80_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT80_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT80_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT80_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT80_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT80_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT80_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT80_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT80_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT80_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT80_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT80_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_CLR_MUX_SHIFT))&CCM_TARGET_ROOT80_CLR_MUX_MASK) +#define CCM_TARGET_ROOT80_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT80_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT80_TOG Bit Fields */ +#define CCM_TARGET_ROOT80_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT80_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT80_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT80_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT80_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT80_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT80_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT80_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT80_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT80_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT80_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT80_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT80_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT80_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT80_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT80_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT80_TOG_MUX_SHIFT))&CCM_TARGET_ROOT80_TOG_MUX_MASK) +#define CCM_TARGET_ROOT80_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT80_TOG_ENABLE_SHIFT 28 +/* POST80 Bit Fields */ +#define CCM_POST80_POST_PODF_MASK 0x3Fu +#define CCM_POST80_POST_PODF_SHIFT 0 +#define CCM_POST80_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST80_POST_PODF_SHIFT))&CCM_POST80_POST_PODF_MASK) +#define CCM_POST80_BUSY1_MASK 0x80u +#define CCM_POST80_BUSY1_SHIFT 7 +#define CCM_POST80_AUTO_PODF_MASK 0x700u +#define CCM_POST80_AUTO_PODF_SHIFT 8 +#define CCM_POST80_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST80_AUTO_PODF_SHIFT))&CCM_POST80_AUTO_PODF_MASK) +#define CCM_POST80_AUTO_EN_MASK 0x1000u +#define CCM_POST80_AUTO_EN_SHIFT 12 +#define CCM_POST80_SLOW_MASK 0x8000u +#define CCM_POST80_SLOW_SHIFT 15 +#define CCM_POST80_SELECT_MASK 0x10000000u +#define CCM_POST80_SELECT_SHIFT 28 +#define CCM_POST80_BUSY2_MASK 0x80000000u +#define CCM_POST80_BUSY2_SHIFT 31 +/* POST_ROOT80_SET Bit Fields */ +#define CCM_POST_ROOT80_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT80_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT80_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_SET_POST_PODF_SHIFT))&CCM_POST_ROOT80_SET_POST_PODF_MASK) +#define CCM_POST_ROOT80_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT80_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT80_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT80_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT80_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT80_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT80_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT80_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT80_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT80_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT80_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT80_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT80_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT80_SET_BUSY2_SHIFT 31 +/* POST_ROOT80_CLR Bit Fields */ +#define CCM_POST_ROOT80_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT80_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT80_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT80_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT80_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT80_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT80_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT80_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT80_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT80_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT80_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT80_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT80_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT80_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT80_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT80_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT80_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT80_CLR_BUSY2_SHIFT 31 +/* POST_ROOT80_TOG Bit Fields */ +#define CCM_POST_ROOT80_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT80_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT80_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT80_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT80_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT80_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT80_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT80_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT80_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT80_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT80_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT80_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT80_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT80_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT80_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT80_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT80_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT80_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT80_TOG_BUSY2_SHIFT 31 +/* PRE80 Bit Fields */ +#define CCM_PRE80_PRE_PODF_B_MASK 0x7u +#define CCM_PRE80_PRE_PODF_B_SHIFT 0 +#define CCM_PRE80_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_PRE_PODF_B_SHIFT))&CCM_PRE80_PRE_PODF_B_MASK) +#define CCM_PRE80_BUSY0_MASK 0x8u +#define CCM_PRE80_BUSY0_SHIFT 3 +#define CCM_PRE80_MUX_B_MASK 0x700u +#define CCM_PRE80_MUX_B_SHIFT 8 +#define CCM_PRE80_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_MUX_B_SHIFT))&CCM_PRE80_MUX_B_MASK) +#define CCM_PRE80_EN_B_MASK 0x1000u +#define CCM_PRE80_EN_B_SHIFT 12 +#define CCM_PRE80_BUSY1_MASK 0x8000u +#define CCM_PRE80_BUSY1_SHIFT 15 +#define CCM_PRE80_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE80_PRE_PODF_A_SHIFT 16 +#define CCM_PRE80_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_PRE_PODF_A_SHIFT))&CCM_PRE80_PRE_PODF_A_MASK) +#define CCM_PRE80_BUSY3_MASK 0x80000u +#define CCM_PRE80_BUSY3_SHIFT 19 +#define CCM_PRE80_MUX_A_MASK 0x7000000u +#define CCM_PRE80_MUX_A_SHIFT 24 +#define CCM_PRE80_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE80_MUX_A_SHIFT))&CCM_PRE80_MUX_A_MASK) +#define CCM_PRE80_EN_A_MASK 0x10000000u +#define CCM_PRE80_EN_A_SHIFT 28 +#define CCM_PRE80_BUSY4_MASK 0x80000000u +#define CCM_PRE80_BUSY4_SHIFT 31 +/* PRE_ROOT80_SET Bit Fields */ +#define CCM_PRE_ROOT80_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT80_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT80_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT80_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT80_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT80_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT80_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT80_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT80_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_MUX_B_SHIFT))&CCM_PRE_ROOT80_SET_MUX_B_MASK) +#define CCM_PRE_ROOT80_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT80_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT80_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT80_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT80_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT80_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT80_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT80_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT80_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT80_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT80_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT80_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT80_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_SET_MUX_A_SHIFT))&CCM_PRE_ROOT80_SET_MUX_A_MASK) +#define CCM_PRE_ROOT80_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT80_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT80_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT80_SET_BUSY4_SHIFT 31 +/* PRE_ROOT80_CLR Bit Fields */ +#define CCM_PRE_ROOT80_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT80_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT80_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT80_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT80_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT80_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT80_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT80_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT80_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT80_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT80_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT80_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT80_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT80_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT80_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT80_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT80_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT80_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT80_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT80_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT80_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT80_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT80_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT80_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT80_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT80_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT80_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT80_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT80_TOG Bit Fields */ +#define CCM_PRE_ROOT80_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT80_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT80_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT80_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT80_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT80_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT80_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT80_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT80_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT80_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT80_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT80_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT80_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT80_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT80_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT80_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT80_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT80_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT80_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT80_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT80_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT80_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT80_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT80_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT80_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT80_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT80_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT80_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT80_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL80 Bit Fields */ +#define CCM_ACCESS_CTRL80_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL80_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL80_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL80_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL80_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL80_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL80_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL80_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL80_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL80_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL80_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL80_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL80_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL80_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL80_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL80_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL80_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL80_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL80_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL80_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL80_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL80_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL80_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL80_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL80_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL80_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL80_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL80_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL80_LOCK_SHIFT 31 +/* ACCESS_CTRL80_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL80_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL80_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL80_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL80_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL80_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL80_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL80_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL80_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL80_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL80_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL80_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL80_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL80_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL80_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL80_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL80_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL80_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL80_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT81 Bit Fields */ +#define CCM_TARGET_ROOT81_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT81_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT81_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_POST_PODF_MASK) +#define CCM_TARGET_ROOT81_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT81_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT81_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT81_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT81_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT81_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT81_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT81_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT81_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT81_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_PRE_PODF_MASK) +#define CCM_TARGET_ROOT81_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT81_MUX_SHIFT 24 +#define CCM_TARGET_ROOT81_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_MUX_SHIFT))&CCM_TARGET_ROOT81_MUX_MASK) +#define CCM_TARGET_ROOT81_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT81_ENABLE_SHIFT 28 +/* TARGET_ROOT81_SET Bit Fields */ +#define CCM_TARGET_ROOT81_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT81_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT81_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT81_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT81_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT81_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT81_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT81_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT81_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT81_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT81_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT81_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT81_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT81_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT81_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT81_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_SET_MUX_SHIFT))&CCM_TARGET_ROOT81_SET_MUX_MASK) +#define CCM_TARGET_ROOT81_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT81_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT81_CLR Bit Fields */ +#define CCM_TARGET_ROOT81_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT81_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT81_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT81_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT81_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT81_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT81_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT81_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT81_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT81_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT81_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT81_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT81_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_CLR_MUX_SHIFT))&CCM_TARGET_ROOT81_CLR_MUX_MASK) +#define CCM_TARGET_ROOT81_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT81_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT81_TOG Bit Fields */ +#define CCM_TARGET_ROOT81_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT81_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT81_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT81_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT81_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT81_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT81_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT81_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT81_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT81_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT81_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT81_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT81_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT81_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT81_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT81_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT81_TOG_MUX_SHIFT))&CCM_TARGET_ROOT81_TOG_MUX_MASK) +#define CCM_TARGET_ROOT81_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT81_TOG_ENABLE_SHIFT 28 +/* POST81 Bit Fields */ +#define CCM_POST81_POST_PODF_MASK 0x3Fu +#define CCM_POST81_POST_PODF_SHIFT 0 +#define CCM_POST81_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST81_POST_PODF_SHIFT))&CCM_POST81_POST_PODF_MASK) +#define CCM_POST81_BUSY1_MASK 0x80u +#define CCM_POST81_BUSY1_SHIFT 7 +#define CCM_POST81_AUTO_PODF_MASK 0x700u +#define CCM_POST81_AUTO_PODF_SHIFT 8 +#define CCM_POST81_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST81_AUTO_PODF_SHIFT))&CCM_POST81_AUTO_PODF_MASK) +#define CCM_POST81_AUTO_EN_MASK 0x1000u +#define CCM_POST81_AUTO_EN_SHIFT 12 +#define CCM_POST81_SLOW_MASK 0x8000u +#define CCM_POST81_SLOW_SHIFT 15 +#define CCM_POST81_SELECT_MASK 0x10000000u +#define CCM_POST81_SELECT_SHIFT 28 +#define CCM_POST81_BUSY2_MASK 0x80000000u +#define CCM_POST81_BUSY2_SHIFT 31 +/* POST_ROOT81_SET Bit Fields */ +#define CCM_POST_ROOT81_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT81_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT81_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_SET_POST_PODF_SHIFT))&CCM_POST_ROOT81_SET_POST_PODF_MASK) +#define CCM_POST_ROOT81_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT81_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT81_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT81_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT81_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT81_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT81_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT81_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT81_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT81_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT81_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT81_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT81_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT81_SET_BUSY2_SHIFT 31 +/* POST_ROOT81_CLR Bit Fields */ +#define CCM_POST_ROOT81_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT81_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT81_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT81_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT81_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT81_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT81_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT81_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT81_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT81_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT81_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT81_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT81_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT81_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT81_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT81_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT81_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT81_CLR_BUSY2_SHIFT 31 +/* POST_ROOT81_TOG Bit Fields */ +#define CCM_POST_ROOT81_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT81_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT81_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT81_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT81_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT81_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT81_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT81_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT81_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT81_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT81_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT81_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT81_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT81_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT81_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT81_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT81_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT81_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT81_TOG_BUSY2_SHIFT 31 +/* PRE81 Bit Fields */ +#define CCM_PRE81_PRE_PODF_B_MASK 0x7u +#define CCM_PRE81_PRE_PODF_B_SHIFT 0 +#define CCM_PRE81_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_PRE_PODF_B_SHIFT))&CCM_PRE81_PRE_PODF_B_MASK) +#define CCM_PRE81_BUSY0_MASK 0x8u +#define CCM_PRE81_BUSY0_SHIFT 3 +#define CCM_PRE81_MUX_B_MASK 0x700u +#define CCM_PRE81_MUX_B_SHIFT 8 +#define CCM_PRE81_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_MUX_B_SHIFT))&CCM_PRE81_MUX_B_MASK) +#define CCM_PRE81_EN_B_MASK 0x1000u +#define CCM_PRE81_EN_B_SHIFT 12 +#define CCM_PRE81_BUSY1_MASK 0x8000u +#define CCM_PRE81_BUSY1_SHIFT 15 +#define CCM_PRE81_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE81_PRE_PODF_A_SHIFT 16 +#define CCM_PRE81_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_PRE_PODF_A_SHIFT))&CCM_PRE81_PRE_PODF_A_MASK) +#define CCM_PRE81_BUSY3_MASK 0x80000u +#define CCM_PRE81_BUSY3_SHIFT 19 +#define CCM_PRE81_MUX_A_MASK 0x7000000u +#define CCM_PRE81_MUX_A_SHIFT 24 +#define CCM_PRE81_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE81_MUX_A_SHIFT))&CCM_PRE81_MUX_A_MASK) +#define CCM_PRE81_EN_A_MASK 0x10000000u +#define CCM_PRE81_EN_A_SHIFT 28 +#define CCM_PRE81_BUSY4_MASK 0x80000000u +#define CCM_PRE81_BUSY4_SHIFT 31 +/* PRE_ROOT81_SET Bit Fields */ +#define CCM_PRE_ROOT81_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT81_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT81_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT81_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT81_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT81_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT81_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT81_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT81_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_MUX_B_SHIFT))&CCM_PRE_ROOT81_SET_MUX_B_MASK) +#define CCM_PRE_ROOT81_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT81_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT81_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT81_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT81_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT81_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT81_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT81_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT81_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT81_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT81_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT81_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT81_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_SET_MUX_A_SHIFT))&CCM_PRE_ROOT81_SET_MUX_A_MASK) +#define CCM_PRE_ROOT81_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT81_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT81_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT81_SET_BUSY4_SHIFT 31 +/* PRE_ROOT81_CLR Bit Fields */ +#define CCM_PRE_ROOT81_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT81_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT81_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT81_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT81_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT81_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT81_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT81_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT81_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT81_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT81_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT81_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT81_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT81_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT81_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT81_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT81_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT81_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT81_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT81_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT81_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT81_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT81_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT81_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT81_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT81_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT81_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT81_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT81_TOG Bit Fields */ +#define CCM_PRE_ROOT81_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT81_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT81_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT81_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT81_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT81_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT81_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT81_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT81_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT81_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT81_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT81_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT81_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT81_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT81_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT81_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT81_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT81_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT81_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT81_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT81_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT81_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT81_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT81_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT81_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT81_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT81_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT81_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT81_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL81 Bit Fields */ +#define CCM_ACCESS_CTRL81_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL81_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL81_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL81_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL81_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL81_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL81_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL81_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL81_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL81_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL81_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL81_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL81_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL81_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL81_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL81_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL81_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL81_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL81_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL81_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL81_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL81_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL81_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL81_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL81_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL81_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL81_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL81_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL81_LOCK_SHIFT 31 +/* ACCESS_CTRL81_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL81_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL81_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL81_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL81_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL81_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL81_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL81_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL81_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL81_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL81_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL81_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL81_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL81_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL81_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL81_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL81_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL81_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL81_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT82 Bit Fields */ +#define CCM_TARGET_ROOT82_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT82_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT82_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_POST_PODF_MASK) +#define CCM_TARGET_ROOT82_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT82_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT82_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT82_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT82_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT82_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT82_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT82_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT82_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT82_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_PRE_PODF_MASK) +#define CCM_TARGET_ROOT82_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT82_MUX_SHIFT 24 +#define CCM_TARGET_ROOT82_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_MUX_SHIFT))&CCM_TARGET_ROOT82_MUX_MASK) +#define CCM_TARGET_ROOT82_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT82_ENABLE_SHIFT 28 +/* TARGET_ROOT82_SET Bit Fields */ +#define CCM_TARGET_ROOT82_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT82_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT82_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT82_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT82_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT82_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT82_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT82_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT82_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT82_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT82_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT82_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT82_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT82_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT82_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT82_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_SET_MUX_SHIFT))&CCM_TARGET_ROOT82_SET_MUX_MASK) +#define CCM_TARGET_ROOT82_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT82_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT82_CLR Bit Fields */ +#define CCM_TARGET_ROOT82_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT82_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT82_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT82_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT82_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT82_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT82_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT82_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT82_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT82_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT82_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT82_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT82_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_CLR_MUX_SHIFT))&CCM_TARGET_ROOT82_CLR_MUX_MASK) +#define CCM_TARGET_ROOT82_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT82_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT82_TOG Bit Fields */ +#define CCM_TARGET_ROOT82_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT82_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT82_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT82_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT82_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT82_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT82_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT82_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT82_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT82_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT82_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT82_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT82_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT82_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT82_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT82_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT82_TOG_MUX_SHIFT))&CCM_TARGET_ROOT82_TOG_MUX_MASK) +#define CCM_TARGET_ROOT82_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT82_TOG_ENABLE_SHIFT 28 +/* POST82 Bit Fields */ +#define CCM_POST82_POST_PODF_MASK 0x3Fu +#define CCM_POST82_POST_PODF_SHIFT 0 +#define CCM_POST82_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST82_POST_PODF_SHIFT))&CCM_POST82_POST_PODF_MASK) +#define CCM_POST82_BUSY1_MASK 0x80u +#define CCM_POST82_BUSY1_SHIFT 7 +#define CCM_POST82_AUTO_PODF_MASK 0x700u +#define CCM_POST82_AUTO_PODF_SHIFT 8 +#define CCM_POST82_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST82_AUTO_PODF_SHIFT))&CCM_POST82_AUTO_PODF_MASK) +#define CCM_POST82_AUTO_EN_MASK 0x1000u +#define CCM_POST82_AUTO_EN_SHIFT 12 +#define CCM_POST82_SLOW_MASK 0x8000u +#define CCM_POST82_SLOW_SHIFT 15 +#define CCM_POST82_SELECT_MASK 0x10000000u +#define CCM_POST82_SELECT_SHIFT 28 +#define CCM_POST82_BUSY2_MASK 0x80000000u +#define CCM_POST82_BUSY2_SHIFT 31 +/* POST_ROOT82_SET Bit Fields */ +#define CCM_POST_ROOT82_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT82_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT82_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_SET_POST_PODF_SHIFT))&CCM_POST_ROOT82_SET_POST_PODF_MASK) +#define CCM_POST_ROOT82_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT82_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT82_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT82_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT82_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT82_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT82_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT82_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT82_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT82_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT82_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT82_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT82_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT82_SET_BUSY2_SHIFT 31 +/* POST_ROOT82_CLR Bit Fields */ +#define CCM_POST_ROOT82_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT82_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT82_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT82_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT82_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT82_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT82_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT82_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT82_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT82_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT82_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT82_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT82_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT82_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT82_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT82_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT82_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT82_CLR_BUSY2_SHIFT 31 +/* POST_ROOT82_TOG Bit Fields */ +#define CCM_POST_ROOT82_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT82_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT82_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT82_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT82_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT82_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT82_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT82_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT82_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT82_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT82_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT82_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT82_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT82_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT82_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT82_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT82_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT82_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT82_TOG_BUSY2_SHIFT 31 +/* PRE82 Bit Fields */ +#define CCM_PRE82_PRE_PODF_B_MASK 0x7u +#define CCM_PRE82_PRE_PODF_B_SHIFT 0 +#define CCM_PRE82_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_PRE_PODF_B_SHIFT))&CCM_PRE82_PRE_PODF_B_MASK) +#define CCM_PRE82_BUSY0_MASK 0x8u +#define CCM_PRE82_BUSY0_SHIFT 3 +#define CCM_PRE82_MUX_B_MASK 0x700u +#define CCM_PRE82_MUX_B_SHIFT 8 +#define CCM_PRE82_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_MUX_B_SHIFT))&CCM_PRE82_MUX_B_MASK) +#define CCM_PRE82_EN_B_MASK 0x1000u +#define CCM_PRE82_EN_B_SHIFT 12 +#define CCM_PRE82_BUSY1_MASK 0x8000u +#define CCM_PRE82_BUSY1_SHIFT 15 +#define CCM_PRE82_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE82_PRE_PODF_A_SHIFT 16 +#define CCM_PRE82_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_PRE_PODF_A_SHIFT))&CCM_PRE82_PRE_PODF_A_MASK) +#define CCM_PRE82_BUSY3_MASK 0x80000u +#define CCM_PRE82_BUSY3_SHIFT 19 +#define CCM_PRE82_MUX_A_MASK 0x7000000u +#define CCM_PRE82_MUX_A_SHIFT 24 +#define CCM_PRE82_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE82_MUX_A_SHIFT))&CCM_PRE82_MUX_A_MASK) +#define CCM_PRE82_EN_A_MASK 0x10000000u +#define CCM_PRE82_EN_A_SHIFT 28 +#define CCM_PRE82_BUSY4_MASK 0x80000000u +#define CCM_PRE82_BUSY4_SHIFT 31 +/* PRE_ROOT82_SET Bit Fields */ +#define CCM_PRE_ROOT82_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT82_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT82_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT82_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT82_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT82_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT82_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT82_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT82_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_MUX_B_SHIFT))&CCM_PRE_ROOT82_SET_MUX_B_MASK) +#define CCM_PRE_ROOT82_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT82_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT82_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT82_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT82_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT82_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT82_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT82_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT82_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT82_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT82_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT82_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT82_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_SET_MUX_A_SHIFT))&CCM_PRE_ROOT82_SET_MUX_A_MASK) +#define CCM_PRE_ROOT82_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT82_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT82_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT82_SET_BUSY4_SHIFT 31 +/* PRE_ROOT82_CLR Bit Fields */ +#define CCM_PRE_ROOT82_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT82_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT82_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT82_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT82_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT82_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT82_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT82_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT82_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT82_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT82_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT82_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT82_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT82_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT82_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT82_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT82_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT82_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT82_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT82_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT82_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT82_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT82_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT82_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT82_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT82_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT82_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT82_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT82_TOG Bit Fields */ +#define CCM_PRE_ROOT82_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT82_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT82_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT82_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT82_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT82_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT82_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT82_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT82_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT82_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT82_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT82_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT82_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT82_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT82_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT82_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT82_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT82_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT82_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT82_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT82_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT82_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT82_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT82_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT82_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT82_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT82_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT82_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT82_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL82 Bit Fields */ +#define CCM_ACCESS_CTRL82_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL82_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL82_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL82_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL82_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL82_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL82_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL82_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL82_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL82_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL82_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL82_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL82_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL82_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL82_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL82_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL82_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL82_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL82_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL82_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL82_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL82_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL82_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL82_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL82_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL82_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL82_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL82_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL82_LOCK_SHIFT 31 +/* ACCESS_CTRL82_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL82_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL82_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL82_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL82_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL82_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL82_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL82_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL82_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL82_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL82_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL82_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL82_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL82_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL82_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL82_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL82_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL82_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL82_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT83 Bit Fields */ +#define CCM_TARGET_ROOT83_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT83_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT83_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_POST_PODF_MASK) +#define CCM_TARGET_ROOT83_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT83_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT83_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT83_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT83_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT83_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT83_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT83_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT83_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT83_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_PRE_PODF_MASK) +#define CCM_TARGET_ROOT83_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT83_MUX_SHIFT 24 +#define CCM_TARGET_ROOT83_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_MUX_SHIFT))&CCM_TARGET_ROOT83_MUX_MASK) +#define CCM_TARGET_ROOT83_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT83_ENABLE_SHIFT 28 +/* TARGET_ROOT83_SET Bit Fields */ +#define CCM_TARGET_ROOT83_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT83_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT83_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT83_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT83_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT83_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT83_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT83_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT83_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT83_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT83_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT83_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT83_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT83_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT83_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT83_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_SET_MUX_SHIFT))&CCM_TARGET_ROOT83_SET_MUX_MASK) +#define CCM_TARGET_ROOT83_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT83_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT83_CLR Bit Fields */ +#define CCM_TARGET_ROOT83_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT83_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT83_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT83_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT83_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT83_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT83_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT83_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT83_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT83_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT83_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT83_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT83_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_CLR_MUX_SHIFT))&CCM_TARGET_ROOT83_CLR_MUX_MASK) +#define CCM_TARGET_ROOT83_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT83_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT83_TOG Bit Fields */ +#define CCM_TARGET_ROOT83_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT83_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT83_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT83_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT83_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT83_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT83_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT83_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT83_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT83_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT83_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT83_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT83_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT83_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT83_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT83_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT83_TOG_MUX_SHIFT))&CCM_TARGET_ROOT83_TOG_MUX_MASK) +#define CCM_TARGET_ROOT83_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT83_TOG_ENABLE_SHIFT 28 +/* POST83 Bit Fields */ +#define CCM_POST83_POST_PODF_MASK 0x3Fu +#define CCM_POST83_POST_PODF_SHIFT 0 +#define CCM_POST83_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST83_POST_PODF_SHIFT))&CCM_POST83_POST_PODF_MASK) +#define CCM_POST83_BUSY1_MASK 0x80u +#define CCM_POST83_BUSY1_SHIFT 7 +#define CCM_POST83_AUTO_PODF_MASK 0x700u +#define CCM_POST83_AUTO_PODF_SHIFT 8 +#define CCM_POST83_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST83_AUTO_PODF_SHIFT))&CCM_POST83_AUTO_PODF_MASK) +#define CCM_POST83_AUTO_EN_MASK 0x1000u +#define CCM_POST83_AUTO_EN_SHIFT 12 +#define CCM_POST83_SLOW_MASK 0x8000u +#define CCM_POST83_SLOW_SHIFT 15 +#define CCM_POST83_SELECT_MASK 0x10000000u +#define CCM_POST83_SELECT_SHIFT 28 +#define CCM_POST83_BUSY2_MASK 0x80000000u +#define CCM_POST83_BUSY2_SHIFT 31 +/* POST_ROOT83_SET Bit Fields */ +#define CCM_POST_ROOT83_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT83_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT83_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_SET_POST_PODF_SHIFT))&CCM_POST_ROOT83_SET_POST_PODF_MASK) +#define CCM_POST_ROOT83_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT83_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT83_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT83_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT83_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT83_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT83_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT83_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT83_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT83_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT83_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT83_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT83_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT83_SET_BUSY2_SHIFT 31 +/* POST_ROOT83_CLR Bit Fields */ +#define CCM_POST_ROOT83_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT83_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT83_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT83_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT83_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT83_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT83_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT83_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT83_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT83_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT83_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT83_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT83_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT83_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT83_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT83_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT83_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT83_CLR_BUSY2_SHIFT 31 +/* POST_ROOT83_TOG Bit Fields */ +#define CCM_POST_ROOT83_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT83_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT83_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT83_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT83_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT83_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT83_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT83_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT83_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT83_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT83_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT83_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT83_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT83_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT83_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT83_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT83_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT83_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT83_TOG_BUSY2_SHIFT 31 +/* PRE83 Bit Fields */ +#define CCM_PRE83_PRE_PODF_B_MASK 0x7u +#define CCM_PRE83_PRE_PODF_B_SHIFT 0 +#define CCM_PRE83_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_PRE_PODF_B_SHIFT))&CCM_PRE83_PRE_PODF_B_MASK) +#define CCM_PRE83_BUSY0_MASK 0x8u +#define CCM_PRE83_BUSY0_SHIFT 3 +#define CCM_PRE83_MUX_B_MASK 0x700u +#define CCM_PRE83_MUX_B_SHIFT 8 +#define CCM_PRE83_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_MUX_B_SHIFT))&CCM_PRE83_MUX_B_MASK) +#define CCM_PRE83_EN_B_MASK 0x1000u +#define CCM_PRE83_EN_B_SHIFT 12 +#define CCM_PRE83_BUSY1_MASK 0x8000u +#define CCM_PRE83_BUSY1_SHIFT 15 +#define CCM_PRE83_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE83_PRE_PODF_A_SHIFT 16 +#define CCM_PRE83_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_PRE_PODF_A_SHIFT))&CCM_PRE83_PRE_PODF_A_MASK) +#define CCM_PRE83_BUSY3_MASK 0x80000u +#define CCM_PRE83_BUSY3_SHIFT 19 +#define CCM_PRE83_MUX_A_MASK 0x7000000u +#define CCM_PRE83_MUX_A_SHIFT 24 +#define CCM_PRE83_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE83_MUX_A_SHIFT))&CCM_PRE83_MUX_A_MASK) +#define CCM_PRE83_EN_A_MASK 0x10000000u +#define CCM_PRE83_EN_A_SHIFT 28 +#define CCM_PRE83_BUSY4_MASK 0x80000000u +#define CCM_PRE83_BUSY4_SHIFT 31 +/* PRE_ROOT83_SET Bit Fields */ +#define CCM_PRE_ROOT83_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT83_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT83_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT83_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT83_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT83_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT83_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT83_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT83_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_MUX_B_SHIFT))&CCM_PRE_ROOT83_SET_MUX_B_MASK) +#define CCM_PRE_ROOT83_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT83_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT83_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT83_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT83_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT83_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT83_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT83_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT83_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT83_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT83_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT83_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT83_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_SET_MUX_A_SHIFT))&CCM_PRE_ROOT83_SET_MUX_A_MASK) +#define CCM_PRE_ROOT83_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT83_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT83_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT83_SET_BUSY4_SHIFT 31 +/* PRE_ROOT83_CLR Bit Fields */ +#define CCM_PRE_ROOT83_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT83_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT83_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT83_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT83_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT83_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT83_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT83_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT83_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT83_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT83_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT83_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT83_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT83_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT83_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT83_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT83_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT83_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT83_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT83_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT83_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT83_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT83_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT83_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT83_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT83_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT83_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT83_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT83_TOG Bit Fields */ +#define CCM_PRE_ROOT83_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT83_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT83_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT83_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT83_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT83_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT83_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT83_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT83_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT83_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT83_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT83_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT83_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT83_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT83_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT83_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT83_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT83_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT83_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT83_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT83_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT83_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT83_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT83_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT83_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT83_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT83_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT83_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT83_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL83 Bit Fields */ +#define CCM_ACCESS_CTRL83_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL83_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL83_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL83_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL83_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL83_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL83_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL83_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL83_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL83_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL83_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL83_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL83_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL83_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL83_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL83_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL83_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL83_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL83_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL83_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL83_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL83_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL83_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL83_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL83_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL83_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL83_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL83_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL83_LOCK_SHIFT 31 +/* ACCESS_CTRL83_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL83_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL83_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL83_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL83_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL83_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL83_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL83_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL83_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL83_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL83_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL83_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL83_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL83_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL83_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL83_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL83_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL83_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL83_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT84 Bit Fields */ +#define CCM_TARGET_ROOT84_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT84_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT84_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_POST_PODF_MASK) +#define CCM_TARGET_ROOT84_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT84_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT84_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT84_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT84_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT84_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT84_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT84_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT84_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT84_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_PRE_PODF_MASK) +#define CCM_TARGET_ROOT84_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT84_MUX_SHIFT 24 +#define CCM_TARGET_ROOT84_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_MUX_SHIFT))&CCM_TARGET_ROOT84_MUX_MASK) +#define CCM_TARGET_ROOT84_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT84_ENABLE_SHIFT 28 +/* TARGET_ROOT84_SET Bit Fields */ +#define CCM_TARGET_ROOT84_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT84_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT84_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT84_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT84_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT84_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT84_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT84_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT84_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT84_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT84_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT84_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT84_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT84_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT84_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT84_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_SET_MUX_SHIFT))&CCM_TARGET_ROOT84_SET_MUX_MASK) +#define CCM_TARGET_ROOT84_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT84_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT84_CLR Bit Fields */ +#define CCM_TARGET_ROOT84_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT84_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT84_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT84_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT84_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT84_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT84_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT84_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT84_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT84_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT84_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT84_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT84_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_CLR_MUX_SHIFT))&CCM_TARGET_ROOT84_CLR_MUX_MASK) +#define CCM_TARGET_ROOT84_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT84_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT84_TOG Bit Fields */ +#define CCM_TARGET_ROOT84_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT84_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT84_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT84_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT84_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT84_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT84_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT84_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT84_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT84_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT84_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT84_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT84_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT84_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT84_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT84_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT84_TOG_MUX_SHIFT))&CCM_TARGET_ROOT84_TOG_MUX_MASK) +#define CCM_TARGET_ROOT84_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT84_TOG_ENABLE_SHIFT 28 +/* POST84 Bit Fields */ +#define CCM_POST84_POST_PODF_MASK 0x3Fu +#define CCM_POST84_POST_PODF_SHIFT 0 +#define CCM_POST84_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST84_POST_PODF_SHIFT))&CCM_POST84_POST_PODF_MASK) +#define CCM_POST84_BUSY1_MASK 0x80u +#define CCM_POST84_BUSY1_SHIFT 7 +#define CCM_POST84_AUTO_PODF_MASK 0x700u +#define CCM_POST84_AUTO_PODF_SHIFT 8 +#define CCM_POST84_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST84_AUTO_PODF_SHIFT))&CCM_POST84_AUTO_PODF_MASK) +#define CCM_POST84_AUTO_EN_MASK 0x1000u +#define CCM_POST84_AUTO_EN_SHIFT 12 +#define CCM_POST84_SLOW_MASK 0x8000u +#define CCM_POST84_SLOW_SHIFT 15 +#define CCM_POST84_SELECT_MASK 0x10000000u +#define CCM_POST84_SELECT_SHIFT 28 +#define CCM_POST84_BUSY2_MASK 0x80000000u +#define CCM_POST84_BUSY2_SHIFT 31 +/* POST_ROOT84_SET Bit Fields */ +#define CCM_POST_ROOT84_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT84_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT84_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_SET_POST_PODF_SHIFT))&CCM_POST_ROOT84_SET_POST_PODF_MASK) +#define CCM_POST_ROOT84_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT84_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT84_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT84_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT84_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT84_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT84_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT84_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT84_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT84_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT84_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT84_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT84_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT84_SET_BUSY2_SHIFT 31 +/* POST_ROOT84_CLR Bit Fields */ +#define CCM_POST_ROOT84_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT84_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT84_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT84_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT84_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT84_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT84_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT84_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT84_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT84_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT84_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT84_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT84_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT84_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT84_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT84_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT84_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT84_CLR_BUSY2_SHIFT 31 +/* POST_ROOT84_TOG Bit Fields */ +#define CCM_POST_ROOT84_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT84_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT84_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT84_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT84_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT84_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT84_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT84_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT84_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT84_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT84_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT84_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT84_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT84_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT84_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT84_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT84_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT84_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT84_TOG_BUSY2_SHIFT 31 +/* PRE84 Bit Fields */ +#define CCM_PRE84_PRE_PODF_B_MASK 0x7u +#define CCM_PRE84_PRE_PODF_B_SHIFT 0 +#define CCM_PRE84_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_PRE_PODF_B_SHIFT))&CCM_PRE84_PRE_PODF_B_MASK) +#define CCM_PRE84_BUSY0_MASK 0x8u +#define CCM_PRE84_BUSY0_SHIFT 3 +#define CCM_PRE84_MUX_B_MASK 0x700u +#define CCM_PRE84_MUX_B_SHIFT 8 +#define CCM_PRE84_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_MUX_B_SHIFT))&CCM_PRE84_MUX_B_MASK) +#define CCM_PRE84_EN_B_MASK 0x1000u +#define CCM_PRE84_EN_B_SHIFT 12 +#define CCM_PRE84_BUSY1_MASK 0x8000u +#define CCM_PRE84_BUSY1_SHIFT 15 +#define CCM_PRE84_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE84_PRE_PODF_A_SHIFT 16 +#define CCM_PRE84_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_PRE_PODF_A_SHIFT))&CCM_PRE84_PRE_PODF_A_MASK) +#define CCM_PRE84_BUSY3_MASK 0x80000u +#define CCM_PRE84_BUSY3_SHIFT 19 +#define CCM_PRE84_MUX_A_MASK 0x7000000u +#define CCM_PRE84_MUX_A_SHIFT 24 +#define CCM_PRE84_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE84_MUX_A_SHIFT))&CCM_PRE84_MUX_A_MASK) +#define CCM_PRE84_EN_A_MASK 0x10000000u +#define CCM_PRE84_EN_A_SHIFT 28 +#define CCM_PRE84_BUSY4_MASK 0x80000000u +#define CCM_PRE84_BUSY4_SHIFT 31 +/* PRE_ROOT84_SET Bit Fields */ +#define CCM_PRE_ROOT84_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT84_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT84_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT84_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT84_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT84_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT84_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT84_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT84_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_MUX_B_SHIFT))&CCM_PRE_ROOT84_SET_MUX_B_MASK) +#define CCM_PRE_ROOT84_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT84_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT84_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT84_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT84_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT84_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT84_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT84_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT84_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT84_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT84_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT84_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT84_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_SET_MUX_A_SHIFT))&CCM_PRE_ROOT84_SET_MUX_A_MASK) +#define CCM_PRE_ROOT84_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT84_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT84_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT84_SET_BUSY4_SHIFT 31 +/* PRE_ROOT84_CLR Bit Fields */ +#define CCM_PRE_ROOT84_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT84_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT84_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT84_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT84_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT84_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT84_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT84_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT84_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT84_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT84_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT84_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT84_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT84_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT84_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT84_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT84_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT84_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT84_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT84_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT84_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT84_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT84_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT84_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT84_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT84_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT84_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT84_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT84_TOG Bit Fields */ +#define CCM_PRE_ROOT84_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT84_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT84_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT84_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT84_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT84_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT84_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT84_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT84_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT84_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT84_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT84_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT84_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT84_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT84_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT84_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT84_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT84_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT84_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT84_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT84_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT84_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT84_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT84_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT84_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT84_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT84_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT84_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT84_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL84 Bit Fields */ +#define CCM_ACCESS_CTRL84_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL84_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL84_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL84_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL84_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL84_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL84_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL84_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL84_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL84_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL84_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL84_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL84_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL84_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL84_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL84_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL84_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL84_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL84_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL84_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL84_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL84_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL84_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL84_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL84_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL84_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL84_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL84_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL84_LOCK_SHIFT 31 +/* ACCESS_CTRL84_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL84_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL84_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL84_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL84_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL84_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL84_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL84_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL84_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL84_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL84_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL84_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL84_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL84_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL84_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL84_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL84_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL84_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL84_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT85 Bit Fields */ +#define CCM_TARGET_ROOT85_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT85_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT85_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_POST_PODF_MASK) +#define CCM_TARGET_ROOT85_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT85_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT85_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT85_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT85_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT85_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT85_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT85_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT85_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT85_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_PRE_PODF_MASK) +#define CCM_TARGET_ROOT85_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT85_MUX_SHIFT 24 +#define CCM_TARGET_ROOT85_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_MUX_SHIFT))&CCM_TARGET_ROOT85_MUX_MASK) +#define CCM_TARGET_ROOT85_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT85_ENABLE_SHIFT 28 +/* TARGET_ROOT85_SET Bit Fields */ +#define CCM_TARGET_ROOT85_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT85_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT85_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT85_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT85_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT85_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT85_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT85_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT85_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT85_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT85_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT85_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT85_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT85_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT85_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT85_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_SET_MUX_SHIFT))&CCM_TARGET_ROOT85_SET_MUX_MASK) +#define CCM_TARGET_ROOT85_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT85_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT85_CLR Bit Fields */ +#define CCM_TARGET_ROOT85_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT85_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT85_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT85_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT85_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT85_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT85_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT85_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT85_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT85_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT85_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT85_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT85_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_CLR_MUX_SHIFT))&CCM_TARGET_ROOT85_CLR_MUX_MASK) +#define CCM_TARGET_ROOT85_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT85_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT85_TOG Bit Fields */ +#define CCM_TARGET_ROOT85_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT85_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT85_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT85_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT85_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT85_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT85_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT85_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT85_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT85_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT85_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT85_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT85_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT85_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT85_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT85_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT85_TOG_MUX_SHIFT))&CCM_TARGET_ROOT85_TOG_MUX_MASK) +#define CCM_TARGET_ROOT85_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT85_TOG_ENABLE_SHIFT 28 +/* POST85 Bit Fields */ +#define CCM_POST85_POST_PODF_MASK 0x3Fu +#define CCM_POST85_POST_PODF_SHIFT 0 +#define CCM_POST85_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST85_POST_PODF_SHIFT))&CCM_POST85_POST_PODF_MASK) +#define CCM_POST85_BUSY1_MASK 0x80u +#define CCM_POST85_BUSY1_SHIFT 7 +#define CCM_POST85_AUTO_PODF_MASK 0x700u +#define CCM_POST85_AUTO_PODF_SHIFT 8 +#define CCM_POST85_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST85_AUTO_PODF_SHIFT))&CCM_POST85_AUTO_PODF_MASK) +#define CCM_POST85_AUTO_EN_MASK 0x1000u +#define CCM_POST85_AUTO_EN_SHIFT 12 +#define CCM_POST85_SLOW_MASK 0x8000u +#define CCM_POST85_SLOW_SHIFT 15 +#define CCM_POST85_SELECT_MASK 0x10000000u +#define CCM_POST85_SELECT_SHIFT 28 +#define CCM_POST85_BUSY2_MASK 0x80000000u +#define CCM_POST85_BUSY2_SHIFT 31 +/* POST_ROOT85_SET Bit Fields */ +#define CCM_POST_ROOT85_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT85_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT85_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_SET_POST_PODF_SHIFT))&CCM_POST_ROOT85_SET_POST_PODF_MASK) +#define CCM_POST_ROOT85_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT85_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT85_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT85_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT85_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT85_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT85_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT85_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT85_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT85_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT85_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT85_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT85_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT85_SET_BUSY2_SHIFT 31 +/* POST_ROOT85_CLR Bit Fields */ +#define CCM_POST_ROOT85_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT85_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT85_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT85_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT85_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT85_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT85_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT85_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT85_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT85_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT85_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT85_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT85_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT85_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT85_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT85_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT85_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT85_CLR_BUSY2_SHIFT 31 +/* POST_ROOT85_TOG Bit Fields */ +#define CCM_POST_ROOT85_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT85_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT85_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT85_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT85_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT85_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT85_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT85_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT85_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT85_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT85_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT85_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT85_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT85_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT85_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT85_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT85_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT85_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT85_TOG_BUSY2_SHIFT 31 +/* PRE85 Bit Fields */ +#define CCM_PRE85_PRE_PODF_B_MASK 0x7u +#define CCM_PRE85_PRE_PODF_B_SHIFT 0 +#define CCM_PRE85_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_PRE_PODF_B_SHIFT))&CCM_PRE85_PRE_PODF_B_MASK) +#define CCM_PRE85_BUSY0_MASK 0x8u +#define CCM_PRE85_BUSY0_SHIFT 3 +#define CCM_PRE85_MUX_B_MASK 0x700u +#define CCM_PRE85_MUX_B_SHIFT 8 +#define CCM_PRE85_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_MUX_B_SHIFT))&CCM_PRE85_MUX_B_MASK) +#define CCM_PRE85_EN_B_MASK 0x1000u +#define CCM_PRE85_EN_B_SHIFT 12 +#define CCM_PRE85_BUSY1_MASK 0x8000u +#define CCM_PRE85_BUSY1_SHIFT 15 +#define CCM_PRE85_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE85_PRE_PODF_A_SHIFT 16 +#define CCM_PRE85_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_PRE_PODF_A_SHIFT))&CCM_PRE85_PRE_PODF_A_MASK) +#define CCM_PRE85_BUSY3_MASK 0x80000u +#define CCM_PRE85_BUSY3_SHIFT 19 +#define CCM_PRE85_MUX_A_MASK 0x7000000u +#define CCM_PRE85_MUX_A_SHIFT 24 +#define CCM_PRE85_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE85_MUX_A_SHIFT))&CCM_PRE85_MUX_A_MASK) +#define CCM_PRE85_EN_A_MASK 0x10000000u +#define CCM_PRE85_EN_A_SHIFT 28 +#define CCM_PRE85_BUSY4_MASK 0x80000000u +#define CCM_PRE85_BUSY4_SHIFT 31 +/* PRE_ROOT85_SET Bit Fields */ +#define CCM_PRE_ROOT85_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT85_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT85_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT85_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT85_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT85_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT85_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT85_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT85_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_MUX_B_SHIFT))&CCM_PRE_ROOT85_SET_MUX_B_MASK) +#define CCM_PRE_ROOT85_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT85_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT85_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT85_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT85_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT85_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT85_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT85_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT85_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT85_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT85_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT85_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT85_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_SET_MUX_A_SHIFT))&CCM_PRE_ROOT85_SET_MUX_A_MASK) +#define CCM_PRE_ROOT85_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT85_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT85_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT85_SET_BUSY4_SHIFT 31 +/* PRE_ROOT85_CLR Bit Fields */ +#define CCM_PRE_ROOT85_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT85_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT85_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT85_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT85_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT85_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT85_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT85_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT85_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT85_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT85_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT85_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT85_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT85_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT85_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT85_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT85_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT85_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT85_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT85_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT85_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT85_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT85_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT85_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT85_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT85_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT85_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT85_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT85_TOG Bit Fields */ +#define CCM_PRE_ROOT85_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT85_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT85_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT85_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT85_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT85_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT85_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT85_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT85_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT85_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT85_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT85_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT85_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT85_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT85_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT85_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT85_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT85_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT85_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT85_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT85_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT85_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT85_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT85_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT85_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT85_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT85_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT85_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT85_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL85 Bit Fields */ +#define CCM_ACCESS_CTRL85_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL85_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL85_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL85_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL85_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL85_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL85_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL85_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL85_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL85_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL85_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL85_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL85_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL85_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL85_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL85_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL85_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL85_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL85_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL85_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL85_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL85_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL85_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL85_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL85_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL85_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL85_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL85_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL85_LOCK_SHIFT 31 +/* ACCESS_CTRL85_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL85_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL85_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL85_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL85_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL85_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL85_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL85_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL85_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL85_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL85_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL85_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL85_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL85_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL85_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL85_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL85_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL85_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL85_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT86 Bit Fields */ +#define CCM_TARGET_ROOT86_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT86_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT86_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_POST_PODF_MASK) +#define CCM_TARGET_ROOT86_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT86_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT86_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT86_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT86_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT86_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT86_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT86_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT86_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT86_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_PRE_PODF_MASK) +#define CCM_TARGET_ROOT86_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT86_MUX_SHIFT 24 +#define CCM_TARGET_ROOT86_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_MUX_SHIFT))&CCM_TARGET_ROOT86_MUX_MASK) +#define CCM_TARGET_ROOT86_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT86_ENABLE_SHIFT 28 +/* TARGET_ROOT86_SET Bit Fields */ +#define CCM_TARGET_ROOT86_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT86_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT86_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT86_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT86_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT86_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT86_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT86_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT86_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT86_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT86_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT86_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT86_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT86_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT86_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT86_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_SET_MUX_SHIFT))&CCM_TARGET_ROOT86_SET_MUX_MASK) +#define CCM_TARGET_ROOT86_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT86_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT86_CLR Bit Fields */ +#define CCM_TARGET_ROOT86_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT86_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT86_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT86_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT86_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT86_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT86_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT86_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT86_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT86_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT86_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT86_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT86_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_CLR_MUX_SHIFT))&CCM_TARGET_ROOT86_CLR_MUX_MASK) +#define CCM_TARGET_ROOT86_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT86_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT86_TOG Bit Fields */ +#define CCM_TARGET_ROOT86_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT86_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT86_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT86_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT86_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT86_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT86_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT86_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT86_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT86_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT86_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT86_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT86_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT86_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT86_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT86_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT86_TOG_MUX_SHIFT))&CCM_TARGET_ROOT86_TOG_MUX_MASK) +#define CCM_TARGET_ROOT86_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT86_TOG_ENABLE_SHIFT 28 +/* POST86 Bit Fields */ +#define CCM_POST86_POST_PODF_MASK 0x3Fu +#define CCM_POST86_POST_PODF_SHIFT 0 +#define CCM_POST86_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST86_POST_PODF_SHIFT))&CCM_POST86_POST_PODF_MASK) +#define CCM_POST86_BUSY1_MASK 0x80u +#define CCM_POST86_BUSY1_SHIFT 7 +#define CCM_POST86_AUTO_PODF_MASK 0x700u +#define CCM_POST86_AUTO_PODF_SHIFT 8 +#define CCM_POST86_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST86_AUTO_PODF_SHIFT))&CCM_POST86_AUTO_PODF_MASK) +#define CCM_POST86_AUTO_EN_MASK 0x1000u +#define CCM_POST86_AUTO_EN_SHIFT 12 +#define CCM_POST86_SLOW_MASK 0x8000u +#define CCM_POST86_SLOW_SHIFT 15 +#define CCM_POST86_SELECT_MASK 0x10000000u +#define CCM_POST86_SELECT_SHIFT 28 +#define CCM_POST86_BUSY2_MASK 0x80000000u +#define CCM_POST86_BUSY2_SHIFT 31 +/* POST_ROOT86_SET Bit Fields */ +#define CCM_POST_ROOT86_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT86_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT86_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_SET_POST_PODF_SHIFT))&CCM_POST_ROOT86_SET_POST_PODF_MASK) +#define CCM_POST_ROOT86_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT86_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT86_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT86_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT86_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT86_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT86_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT86_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT86_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT86_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT86_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT86_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT86_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT86_SET_BUSY2_SHIFT 31 +/* POST_ROOT86_CLR Bit Fields */ +#define CCM_POST_ROOT86_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT86_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT86_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT86_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT86_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT86_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT86_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT86_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT86_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT86_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT86_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT86_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT86_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT86_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT86_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT86_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT86_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT86_CLR_BUSY2_SHIFT 31 +/* POST_ROOT86_TOG Bit Fields */ +#define CCM_POST_ROOT86_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT86_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT86_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT86_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT86_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT86_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT86_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT86_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT86_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT86_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT86_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT86_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT86_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT86_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT86_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT86_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT86_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT86_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT86_TOG_BUSY2_SHIFT 31 +/* PRE86 Bit Fields */ +#define CCM_PRE86_PRE_PODF_B_MASK 0x7u +#define CCM_PRE86_PRE_PODF_B_SHIFT 0 +#define CCM_PRE86_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_PRE_PODF_B_SHIFT))&CCM_PRE86_PRE_PODF_B_MASK) +#define CCM_PRE86_BUSY0_MASK 0x8u +#define CCM_PRE86_BUSY0_SHIFT 3 +#define CCM_PRE86_MUX_B_MASK 0x700u +#define CCM_PRE86_MUX_B_SHIFT 8 +#define CCM_PRE86_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_MUX_B_SHIFT))&CCM_PRE86_MUX_B_MASK) +#define CCM_PRE86_EN_B_MASK 0x1000u +#define CCM_PRE86_EN_B_SHIFT 12 +#define CCM_PRE86_BUSY1_MASK 0x8000u +#define CCM_PRE86_BUSY1_SHIFT 15 +#define CCM_PRE86_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE86_PRE_PODF_A_SHIFT 16 +#define CCM_PRE86_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_PRE_PODF_A_SHIFT))&CCM_PRE86_PRE_PODF_A_MASK) +#define CCM_PRE86_BUSY3_MASK 0x80000u +#define CCM_PRE86_BUSY3_SHIFT 19 +#define CCM_PRE86_MUX_A_MASK 0x7000000u +#define CCM_PRE86_MUX_A_SHIFT 24 +#define CCM_PRE86_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE86_MUX_A_SHIFT))&CCM_PRE86_MUX_A_MASK) +#define CCM_PRE86_EN_A_MASK 0x10000000u +#define CCM_PRE86_EN_A_SHIFT 28 +#define CCM_PRE86_BUSY4_MASK 0x80000000u +#define CCM_PRE86_BUSY4_SHIFT 31 +/* PRE_ROOT86_SET Bit Fields */ +#define CCM_PRE_ROOT86_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT86_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT86_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT86_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT86_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT86_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT86_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT86_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT86_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_MUX_B_SHIFT))&CCM_PRE_ROOT86_SET_MUX_B_MASK) +#define CCM_PRE_ROOT86_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT86_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT86_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT86_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT86_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT86_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT86_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT86_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT86_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT86_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT86_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT86_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT86_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_SET_MUX_A_SHIFT))&CCM_PRE_ROOT86_SET_MUX_A_MASK) +#define CCM_PRE_ROOT86_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT86_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT86_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT86_SET_BUSY4_SHIFT 31 +/* PRE_ROOT86_CLR Bit Fields */ +#define CCM_PRE_ROOT86_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT86_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT86_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT86_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT86_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT86_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT86_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT86_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT86_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT86_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT86_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT86_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT86_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT86_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT86_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT86_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT86_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT86_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT86_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT86_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT86_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT86_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT86_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT86_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT86_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT86_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT86_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT86_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT86_TOG Bit Fields */ +#define CCM_PRE_ROOT86_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT86_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT86_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT86_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT86_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT86_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT86_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT86_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT86_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT86_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT86_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT86_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT86_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT86_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT86_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT86_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT86_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT86_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT86_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT86_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT86_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT86_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT86_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT86_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT86_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT86_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT86_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT86_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT86_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL86 Bit Fields */ +#define CCM_ACCESS_CTRL86_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL86_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL86_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL86_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL86_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL86_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL86_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL86_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL86_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL86_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL86_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL86_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL86_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL86_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL86_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL86_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL86_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL86_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL86_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL86_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL86_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL86_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL86_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL86_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL86_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL86_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL86_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL86_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL86_LOCK_SHIFT 31 +/* ACCESS_CTRL86_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL86_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL86_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL86_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL86_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL86_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL86_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL86_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL86_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL86_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL86_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL86_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL86_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL86_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL86_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL86_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL86_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL86_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL86_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT87 Bit Fields */ +#define CCM_TARGET_ROOT87_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT87_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT87_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_POST_PODF_MASK) +#define CCM_TARGET_ROOT87_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT87_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT87_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT87_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT87_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT87_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT87_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT87_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT87_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT87_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_PRE_PODF_MASK) +#define CCM_TARGET_ROOT87_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT87_MUX_SHIFT 24 +#define CCM_TARGET_ROOT87_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_MUX_SHIFT))&CCM_TARGET_ROOT87_MUX_MASK) +#define CCM_TARGET_ROOT87_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT87_ENABLE_SHIFT 28 +/* TARGET_ROOT87_SET Bit Fields */ +#define CCM_TARGET_ROOT87_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT87_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT87_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT87_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT87_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT87_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT87_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT87_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT87_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT87_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT87_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT87_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT87_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT87_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT87_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT87_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_SET_MUX_SHIFT))&CCM_TARGET_ROOT87_SET_MUX_MASK) +#define CCM_TARGET_ROOT87_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT87_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT87_CLR Bit Fields */ +#define CCM_TARGET_ROOT87_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT87_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT87_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT87_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT87_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT87_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT87_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT87_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT87_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT87_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT87_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT87_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT87_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_CLR_MUX_SHIFT))&CCM_TARGET_ROOT87_CLR_MUX_MASK) +#define CCM_TARGET_ROOT87_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT87_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT87_TOG Bit Fields */ +#define CCM_TARGET_ROOT87_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT87_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT87_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT87_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT87_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT87_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT87_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT87_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT87_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT87_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT87_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT87_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT87_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT87_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT87_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT87_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT87_TOG_MUX_SHIFT))&CCM_TARGET_ROOT87_TOG_MUX_MASK) +#define CCM_TARGET_ROOT87_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT87_TOG_ENABLE_SHIFT 28 +/* POST87 Bit Fields */ +#define CCM_POST87_POST_PODF_MASK 0x3Fu +#define CCM_POST87_POST_PODF_SHIFT 0 +#define CCM_POST87_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST87_POST_PODF_SHIFT))&CCM_POST87_POST_PODF_MASK) +#define CCM_POST87_BUSY1_MASK 0x80u +#define CCM_POST87_BUSY1_SHIFT 7 +#define CCM_POST87_AUTO_PODF_MASK 0x700u +#define CCM_POST87_AUTO_PODF_SHIFT 8 +#define CCM_POST87_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST87_AUTO_PODF_SHIFT))&CCM_POST87_AUTO_PODF_MASK) +#define CCM_POST87_AUTO_EN_MASK 0x1000u +#define CCM_POST87_AUTO_EN_SHIFT 12 +#define CCM_POST87_SLOW_MASK 0x8000u +#define CCM_POST87_SLOW_SHIFT 15 +#define CCM_POST87_SELECT_MASK 0x10000000u +#define CCM_POST87_SELECT_SHIFT 28 +#define CCM_POST87_BUSY2_MASK 0x80000000u +#define CCM_POST87_BUSY2_SHIFT 31 +/* POST_ROOT87_SET Bit Fields */ +#define CCM_POST_ROOT87_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT87_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT87_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_SET_POST_PODF_SHIFT))&CCM_POST_ROOT87_SET_POST_PODF_MASK) +#define CCM_POST_ROOT87_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT87_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT87_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT87_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT87_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT87_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT87_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT87_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT87_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT87_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT87_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT87_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT87_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT87_SET_BUSY2_SHIFT 31 +/* POST_ROOT87_CLR Bit Fields */ +#define CCM_POST_ROOT87_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT87_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT87_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT87_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT87_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT87_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT87_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT87_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT87_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT87_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT87_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT87_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT87_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT87_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT87_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT87_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT87_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT87_CLR_BUSY2_SHIFT 31 +/* POST_ROOT87_TOG Bit Fields */ +#define CCM_POST_ROOT87_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT87_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT87_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT87_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT87_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT87_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT87_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT87_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT87_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT87_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT87_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT87_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT87_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT87_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT87_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT87_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT87_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT87_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT87_TOG_BUSY2_SHIFT 31 +/* PRE87 Bit Fields */ +#define CCM_PRE87_PRE_PODF_B_MASK 0x7u +#define CCM_PRE87_PRE_PODF_B_SHIFT 0 +#define CCM_PRE87_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_PRE_PODF_B_SHIFT))&CCM_PRE87_PRE_PODF_B_MASK) +#define CCM_PRE87_BUSY0_MASK 0x8u +#define CCM_PRE87_BUSY0_SHIFT 3 +#define CCM_PRE87_MUX_B_MASK 0x700u +#define CCM_PRE87_MUX_B_SHIFT 8 +#define CCM_PRE87_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_MUX_B_SHIFT))&CCM_PRE87_MUX_B_MASK) +#define CCM_PRE87_EN_B_MASK 0x1000u +#define CCM_PRE87_EN_B_SHIFT 12 +#define CCM_PRE87_BUSY1_MASK 0x8000u +#define CCM_PRE87_BUSY1_SHIFT 15 +#define CCM_PRE87_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE87_PRE_PODF_A_SHIFT 16 +#define CCM_PRE87_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_PRE_PODF_A_SHIFT))&CCM_PRE87_PRE_PODF_A_MASK) +#define CCM_PRE87_BUSY3_MASK 0x80000u +#define CCM_PRE87_BUSY3_SHIFT 19 +#define CCM_PRE87_MUX_A_MASK 0x7000000u +#define CCM_PRE87_MUX_A_SHIFT 24 +#define CCM_PRE87_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE87_MUX_A_SHIFT))&CCM_PRE87_MUX_A_MASK) +#define CCM_PRE87_EN_A_MASK 0x10000000u +#define CCM_PRE87_EN_A_SHIFT 28 +#define CCM_PRE87_BUSY4_MASK 0x80000000u +#define CCM_PRE87_BUSY4_SHIFT 31 +/* PRE_ROOT87_SET Bit Fields */ +#define CCM_PRE_ROOT87_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT87_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT87_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT87_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT87_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT87_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT87_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT87_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT87_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_MUX_B_SHIFT))&CCM_PRE_ROOT87_SET_MUX_B_MASK) +#define CCM_PRE_ROOT87_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT87_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT87_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT87_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT87_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT87_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT87_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT87_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT87_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT87_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT87_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT87_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT87_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_SET_MUX_A_SHIFT))&CCM_PRE_ROOT87_SET_MUX_A_MASK) +#define CCM_PRE_ROOT87_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT87_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT87_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT87_SET_BUSY4_SHIFT 31 +/* PRE_ROOT87_CLR Bit Fields */ +#define CCM_PRE_ROOT87_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT87_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT87_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT87_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT87_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT87_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT87_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT87_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT87_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT87_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT87_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT87_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT87_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT87_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT87_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT87_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT87_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT87_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT87_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT87_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT87_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT87_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT87_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT87_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT87_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT87_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT87_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT87_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT87_TOG Bit Fields */ +#define CCM_PRE_ROOT87_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT87_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT87_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT87_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT87_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT87_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT87_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT87_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT87_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT87_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT87_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT87_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT87_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT87_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT87_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT87_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT87_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT87_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT87_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT87_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT87_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT87_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT87_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT87_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT87_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT87_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT87_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT87_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT87_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL87 Bit Fields */ +#define CCM_ACCESS_CTRL87_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL87_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL87_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL87_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL87_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL87_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL87_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL87_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL87_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL87_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL87_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL87_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL87_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL87_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL87_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL87_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL87_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL87_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL87_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL87_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL87_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL87_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL87_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL87_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL87_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL87_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL87_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL87_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL87_LOCK_SHIFT 31 +/* ACCESS_CTRL87_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL87_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL87_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL87_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL87_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL87_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL87_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL87_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL87_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL87_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL87_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL87_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL87_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL87_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL87_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL87_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL87_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL87_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL87_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT88 Bit Fields */ +#define CCM_TARGET_ROOT88_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT88_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT88_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_POST_PODF_MASK) +#define CCM_TARGET_ROOT88_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT88_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT88_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT88_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT88_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT88_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT88_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT88_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT88_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT88_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_PRE_PODF_MASK) +#define CCM_TARGET_ROOT88_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT88_MUX_SHIFT 24 +#define CCM_TARGET_ROOT88_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_MUX_SHIFT))&CCM_TARGET_ROOT88_MUX_MASK) +#define CCM_TARGET_ROOT88_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT88_ENABLE_SHIFT 28 +/* TARGET_ROOT88_SET Bit Fields */ +#define CCM_TARGET_ROOT88_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT88_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT88_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT88_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT88_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT88_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT88_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT88_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT88_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT88_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT88_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT88_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT88_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT88_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT88_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT88_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_SET_MUX_SHIFT))&CCM_TARGET_ROOT88_SET_MUX_MASK) +#define CCM_TARGET_ROOT88_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT88_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT88_CLR Bit Fields */ +#define CCM_TARGET_ROOT88_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT88_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT88_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT88_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT88_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT88_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT88_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT88_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT88_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT88_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT88_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT88_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT88_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_CLR_MUX_SHIFT))&CCM_TARGET_ROOT88_CLR_MUX_MASK) +#define CCM_TARGET_ROOT88_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT88_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT88_TOG Bit Fields */ +#define CCM_TARGET_ROOT88_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT88_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT88_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT88_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT88_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT88_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT88_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT88_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT88_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT88_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT88_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT88_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT88_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT88_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT88_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT88_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT88_TOG_MUX_SHIFT))&CCM_TARGET_ROOT88_TOG_MUX_MASK) +#define CCM_TARGET_ROOT88_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT88_TOG_ENABLE_SHIFT 28 +/* POST88 Bit Fields */ +#define CCM_POST88_POST_PODF_MASK 0x3Fu +#define CCM_POST88_POST_PODF_SHIFT 0 +#define CCM_POST88_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST88_POST_PODF_SHIFT))&CCM_POST88_POST_PODF_MASK) +#define CCM_POST88_BUSY1_MASK 0x80u +#define CCM_POST88_BUSY1_SHIFT 7 +#define CCM_POST88_AUTO_PODF_MASK 0x700u +#define CCM_POST88_AUTO_PODF_SHIFT 8 +#define CCM_POST88_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST88_AUTO_PODF_SHIFT))&CCM_POST88_AUTO_PODF_MASK) +#define CCM_POST88_AUTO_EN_MASK 0x1000u +#define CCM_POST88_AUTO_EN_SHIFT 12 +#define CCM_POST88_SLOW_MASK 0x8000u +#define CCM_POST88_SLOW_SHIFT 15 +#define CCM_POST88_SELECT_MASK 0x10000000u +#define CCM_POST88_SELECT_SHIFT 28 +#define CCM_POST88_BUSY2_MASK 0x80000000u +#define CCM_POST88_BUSY2_SHIFT 31 +/* POST_ROOT88_SET Bit Fields */ +#define CCM_POST_ROOT88_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT88_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT88_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_SET_POST_PODF_SHIFT))&CCM_POST_ROOT88_SET_POST_PODF_MASK) +#define CCM_POST_ROOT88_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT88_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT88_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT88_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT88_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT88_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT88_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT88_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT88_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT88_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT88_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT88_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT88_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT88_SET_BUSY2_SHIFT 31 +/* POST_ROOT88_CLR Bit Fields */ +#define CCM_POST_ROOT88_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT88_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT88_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT88_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT88_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT88_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT88_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT88_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT88_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT88_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT88_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT88_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT88_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT88_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT88_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT88_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT88_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT88_CLR_BUSY2_SHIFT 31 +/* POST_ROOT88_TOG Bit Fields */ +#define CCM_POST_ROOT88_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT88_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT88_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT88_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT88_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT88_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT88_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT88_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT88_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT88_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT88_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT88_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT88_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT88_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT88_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT88_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT88_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT88_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT88_TOG_BUSY2_SHIFT 31 +/* PRE88 Bit Fields */ +#define CCM_PRE88_PRE_PODF_B_MASK 0x7u +#define CCM_PRE88_PRE_PODF_B_SHIFT 0 +#define CCM_PRE88_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_PRE_PODF_B_SHIFT))&CCM_PRE88_PRE_PODF_B_MASK) +#define CCM_PRE88_BUSY0_MASK 0x8u +#define CCM_PRE88_BUSY0_SHIFT 3 +#define CCM_PRE88_MUX_B_MASK 0x700u +#define CCM_PRE88_MUX_B_SHIFT 8 +#define CCM_PRE88_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_MUX_B_SHIFT))&CCM_PRE88_MUX_B_MASK) +#define CCM_PRE88_EN_B_MASK 0x1000u +#define CCM_PRE88_EN_B_SHIFT 12 +#define CCM_PRE88_BUSY1_MASK 0x8000u +#define CCM_PRE88_BUSY1_SHIFT 15 +#define CCM_PRE88_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE88_PRE_PODF_A_SHIFT 16 +#define CCM_PRE88_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_PRE_PODF_A_SHIFT))&CCM_PRE88_PRE_PODF_A_MASK) +#define CCM_PRE88_BUSY3_MASK 0x80000u +#define CCM_PRE88_BUSY3_SHIFT 19 +#define CCM_PRE88_MUX_A_MASK 0x7000000u +#define CCM_PRE88_MUX_A_SHIFT 24 +#define CCM_PRE88_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE88_MUX_A_SHIFT))&CCM_PRE88_MUX_A_MASK) +#define CCM_PRE88_EN_A_MASK 0x10000000u +#define CCM_PRE88_EN_A_SHIFT 28 +#define CCM_PRE88_BUSY4_MASK 0x80000000u +#define CCM_PRE88_BUSY4_SHIFT 31 +/* PRE_ROOT88_SET Bit Fields */ +#define CCM_PRE_ROOT88_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT88_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT88_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT88_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT88_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT88_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT88_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT88_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT88_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_MUX_B_SHIFT))&CCM_PRE_ROOT88_SET_MUX_B_MASK) +#define CCM_PRE_ROOT88_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT88_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT88_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT88_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT88_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT88_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT88_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT88_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT88_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT88_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT88_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT88_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT88_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_SET_MUX_A_SHIFT))&CCM_PRE_ROOT88_SET_MUX_A_MASK) +#define CCM_PRE_ROOT88_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT88_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT88_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT88_SET_BUSY4_SHIFT 31 +/* PRE_ROOT88_CLR Bit Fields */ +#define CCM_PRE_ROOT88_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT88_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT88_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT88_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT88_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT88_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT88_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT88_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT88_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT88_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT88_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT88_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT88_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT88_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT88_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT88_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT88_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT88_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT88_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT88_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT88_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT88_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT88_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT88_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT88_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT88_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT88_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT88_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT88_TOG Bit Fields */ +#define CCM_PRE_ROOT88_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT88_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT88_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT88_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT88_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT88_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT88_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT88_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT88_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT88_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT88_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT88_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT88_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT88_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT88_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT88_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT88_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT88_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT88_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT88_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT88_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT88_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT88_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT88_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT88_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT88_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT88_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT88_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT88_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL88 Bit Fields */ +#define CCM_ACCESS_CTRL88_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL88_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL88_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL88_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL88_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL88_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL88_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL88_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL88_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL88_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL88_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL88_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL88_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL88_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL88_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL88_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL88_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL88_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL88_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL88_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL88_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL88_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL88_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL88_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL88_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL88_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL88_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL88_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL88_LOCK_SHIFT 31 +/* ACCESS_CTRL88_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL88_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL88_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL88_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL88_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL88_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL88_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL88_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL88_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL88_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL88_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL88_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL88_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL88_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL88_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL88_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL88_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL88_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL88_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT89 Bit Fields */ +#define CCM_TARGET_ROOT89_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT89_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT89_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_POST_PODF_MASK) +#define CCM_TARGET_ROOT89_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT89_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT89_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT89_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT89_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT89_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT89_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT89_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT89_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT89_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_PRE_PODF_MASK) +#define CCM_TARGET_ROOT89_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT89_MUX_SHIFT 24 +#define CCM_TARGET_ROOT89_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_MUX_SHIFT))&CCM_TARGET_ROOT89_MUX_MASK) +#define CCM_TARGET_ROOT89_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT89_ENABLE_SHIFT 28 +/* TARGET_ROOT89_SET Bit Fields */ +#define CCM_TARGET_ROOT89_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT89_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT89_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT89_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT89_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT89_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT89_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT89_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT89_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT89_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT89_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT89_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT89_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT89_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT89_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT89_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_SET_MUX_SHIFT))&CCM_TARGET_ROOT89_SET_MUX_MASK) +#define CCM_TARGET_ROOT89_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT89_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT89_CLR Bit Fields */ +#define CCM_TARGET_ROOT89_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT89_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT89_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT89_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT89_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT89_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT89_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT89_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT89_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT89_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT89_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT89_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT89_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_CLR_MUX_SHIFT))&CCM_TARGET_ROOT89_CLR_MUX_MASK) +#define CCM_TARGET_ROOT89_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT89_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT89_TOG Bit Fields */ +#define CCM_TARGET_ROOT89_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT89_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT89_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT89_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT89_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT89_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT89_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT89_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT89_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT89_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT89_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT89_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT89_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT89_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT89_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT89_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT89_TOG_MUX_SHIFT))&CCM_TARGET_ROOT89_TOG_MUX_MASK) +#define CCM_TARGET_ROOT89_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT89_TOG_ENABLE_SHIFT 28 +/* POST89 Bit Fields */ +#define CCM_POST89_POST_PODF_MASK 0x3Fu +#define CCM_POST89_POST_PODF_SHIFT 0 +#define CCM_POST89_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST89_POST_PODF_SHIFT))&CCM_POST89_POST_PODF_MASK) +#define CCM_POST89_BUSY1_MASK 0x80u +#define CCM_POST89_BUSY1_SHIFT 7 +#define CCM_POST89_AUTO_PODF_MASK 0x700u +#define CCM_POST89_AUTO_PODF_SHIFT 8 +#define CCM_POST89_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST89_AUTO_PODF_SHIFT))&CCM_POST89_AUTO_PODF_MASK) +#define CCM_POST89_AUTO_EN_MASK 0x1000u +#define CCM_POST89_AUTO_EN_SHIFT 12 +#define CCM_POST89_SLOW_MASK 0x8000u +#define CCM_POST89_SLOW_SHIFT 15 +#define CCM_POST89_SELECT_MASK 0x10000000u +#define CCM_POST89_SELECT_SHIFT 28 +#define CCM_POST89_BUSY2_MASK 0x80000000u +#define CCM_POST89_BUSY2_SHIFT 31 +/* POST_ROOT89_SET Bit Fields */ +#define CCM_POST_ROOT89_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT89_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT89_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_SET_POST_PODF_SHIFT))&CCM_POST_ROOT89_SET_POST_PODF_MASK) +#define CCM_POST_ROOT89_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT89_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT89_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT89_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT89_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT89_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT89_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT89_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT89_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT89_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT89_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT89_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT89_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT89_SET_BUSY2_SHIFT 31 +/* POST_ROOT89_CLR Bit Fields */ +#define CCM_POST_ROOT89_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT89_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT89_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT89_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT89_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT89_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT89_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT89_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT89_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT89_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT89_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT89_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT89_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT89_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT89_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT89_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT89_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT89_CLR_BUSY2_SHIFT 31 +/* POST_ROOT89_TOG Bit Fields */ +#define CCM_POST_ROOT89_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT89_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT89_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT89_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT89_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT89_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT89_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT89_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT89_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT89_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT89_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT89_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT89_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT89_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT89_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT89_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT89_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT89_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT89_TOG_BUSY2_SHIFT 31 +/* PRE89 Bit Fields */ +#define CCM_PRE89_PRE_PODF_B_MASK 0x7u +#define CCM_PRE89_PRE_PODF_B_SHIFT 0 +#define CCM_PRE89_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_PRE_PODF_B_SHIFT))&CCM_PRE89_PRE_PODF_B_MASK) +#define CCM_PRE89_BUSY0_MASK 0x8u +#define CCM_PRE89_BUSY0_SHIFT 3 +#define CCM_PRE89_MUX_B_MASK 0x700u +#define CCM_PRE89_MUX_B_SHIFT 8 +#define CCM_PRE89_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_MUX_B_SHIFT))&CCM_PRE89_MUX_B_MASK) +#define CCM_PRE89_EN_B_MASK 0x1000u +#define CCM_PRE89_EN_B_SHIFT 12 +#define CCM_PRE89_BUSY1_MASK 0x8000u +#define CCM_PRE89_BUSY1_SHIFT 15 +#define CCM_PRE89_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE89_PRE_PODF_A_SHIFT 16 +#define CCM_PRE89_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_PRE_PODF_A_SHIFT))&CCM_PRE89_PRE_PODF_A_MASK) +#define CCM_PRE89_BUSY3_MASK 0x80000u +#define CCM_PRE89_BUSY3_SHIFT 19 +#define CCM_PRE89_MUX_A_MASK 0x7000000u +#define CCM_PRE89_MUX_A_SHIFT 24 +#define CCM_PRE89_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE89_MUX_A_SHIFT))&CCM_PRE89_MUX_A_MASK) +#define CCM_PRE89_EN_A_MASK 0x10000000u +#define CCM_PRE89_EN_A_SHIFT 28 +#define CCM_PRE89_BUSY4_MASK 0x80000000u +#define CCM_PRE89_BUSY4_SHIFT 31 +/* PRE_ROOT89_SET Bit Fields */ +#define CCM_PRE_ROOT89_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT89_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT89_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT89_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT89_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT89_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT89_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT89_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT89_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_MUX_B_SHIFT))&CCM_PRE_ROOT89_SET_MUX_B_MASK) +#define CCM_PRE_ROOT89_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT89_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT89_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT89_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT89_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT89_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT89_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT89_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT89_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT89_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT89_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT89_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT89_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_SET_MUX_A_SHIFT))&CCM_PRE_ROOT89_SET_MUX_A_MASK) +#define CCM_PRE_ROOT89_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT89_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT89_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT89_SET_BUSY4_SHIFT 31 +/* PRE_ROOT89_CLR Bit Fields */ +#define CCM_PRE_ROOT89_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT89_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT89_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT89_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT89_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT89_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT89_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT89_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT89_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT89_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT89_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT89_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT89_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT89_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT89_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT89_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT89_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT89_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT89_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT89_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT89_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT89_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT89_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT89_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT89_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT89_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT89_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT89_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT89_TOG Bit Fields */ +#define CCM_PRE_ROOT89_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT89_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT89_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT89_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT89_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT89_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT89_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT89_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT89_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT89_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT89_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT89_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT89_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT89_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT89_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT89_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT89_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT89_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT89_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT89_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT89_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT89_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT89_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT89_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT89_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT89_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT89_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT89_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT89_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL89 Bit Fields */ +#define CCM_ACCESS_CTRL89_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL89_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL89_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL89_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL89_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL89_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL89_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL89_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL89_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL89_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL89_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL89_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL89_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL89_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL89_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL89_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL89_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL89_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL89_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL89_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL89_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL89_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL89_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL89_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL89_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL89_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL89_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL89_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL89_LOCK_SHIFT 31 +/* ACCESS_CTRL89_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL89_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL89_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL89_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL89_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL89_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL89_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL89_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL89_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL89_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL89_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL89_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL89_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL89_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL89_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL89_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL89_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL89_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL89_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT90 Bit Fields */ +#define CCM_TARGET_ROOT90_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT90_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT90_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_POST_PODF_MASK) +#define CCM_TARGET_ROOT90_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT90_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT90_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT90_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT90_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT90_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT90_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT90_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT90_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT90_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_PRE_PODF_MASK) +#define CCM_TARGET_ROOT90_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT90_MUX_SHIFT 24 +#define CCM_TARGET_ROOT90_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_MUX_SHIFT))&CCM_TARGET_ROOT90_MUX_MASK) +#define CCM_TARGET_ROOT90_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT90_ENABLE_SHIFT 28 +/* TARGET_ROOT90_SET Bit Fields */ +#define CCM_TARGET_ROOT90_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT90_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT90_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT90_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT90_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT90_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT90_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT90_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT90_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT90_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT90_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT90_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT90_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT90_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT90_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT90_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_SET_MUX_SHIFT))&CCM_TARGET_ROOT90_SET_MUX_MASK) +#define CCM_TARGET_ROOT90_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT90_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT90_CLR Bit Fields */ +#define CCM_TARGET_ROOT90_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT90_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT90_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT90_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT90_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT90_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT90_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT90_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT90_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT90_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT90_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT90_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT90_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_CLR_MUX_SHIFT))&CCM_TARGET_ROOT90_CLR_MUX_MASK) +#define CCM_TARGET_ROOT90_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT90_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT90_TOG Bit Fields */ +#define CCM_TARGET_ROOT90_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT90_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT90_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT90_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT90_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT90_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT90_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT90_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT90_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT90_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT90_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT90_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT90_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT90_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT90_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT90_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT90_TOG_MUX_SHIFT))&CCM_TARGET_ROOT90_TOG_MUX_MASK) +#define CCM_TARGET_ROOT90_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT90_TOG_ENABLE_SHIFT 28 +/* POST90 Bit Fields */ +#define CCM_POST90_POST_PODF_MASK 0x3Fu +#define CCM_POST90_POST_PODF_SHIFT 0 +#define CCM_POST90_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST90_POST_PODF_SHIFT))&CCM_POST90_POST_PODF_MASK) +#define CCM_POST90_BUSY1_MASK 0x80u +#define CCM_POST90_BUSY1_SHIFT 7 +#define CCM_POST90_AUTO_PODF_MASK 0x700u +#define CCM_POST90_AUTO_PODF_SHIFT 8 +#define CCM_POST90_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST90_AUTO_PODF_SHIFT))&CCM_POST90_AUTO_PODF_MASK) +#define CCM_POST90_AUTO_EN_MASK 0x1000u +#define CCM_POST90_AUTO_EN_SHIFT 12 +#define CCM_POST90_SLOW_MASK 0x8000u +#define CCM_POST90_SLOW_SHIFT 15 +#define CCM_POST90_SELECT_MASK 0x10000000u +#define CCM_POST90_SELECT_SHIFT 28 +#define CCM_POST90_BUSY2_MASK 0x80000000u +#define CCM_POST90_BUSY2_SHIFT 31 +/* POST_ROOT90_SET Bit Fields */ +#define CCM_POST_ROOT90_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT90_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT90_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_SET_POST_PODF_SHIFT))&CCM_POST_ROOT90_SET_POST_PODF_MASK) +#define CCM_POST_ROOT90_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT90_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT90_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT90_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT90_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT90_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT90_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT90_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT90_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT90_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT90_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT90_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT90_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT90_SET_BUSY2_SHIFT 31 +/* POST_ROOT90_CLR Bit Fields */ +#define CCM_POST_ROOT90_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT90_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT90_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT90_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT90_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT90_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT90_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT90_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT90_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT90_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT90_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT90_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT90_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT90_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT90_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT90_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT90_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT90_CLR_BUSY2_SHIFT 31 +/* POST_ROOT90_TOG Bit Fields */ +#define CCM_POST_ROOT90_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT90_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT90_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT90_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT90_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT90_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT90_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT90_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT90_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT90_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT90_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT90_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT90_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT90_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT90_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT90_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT90_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT90_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT90_TOG_BUSY2_SHIFT 31 +/* PRE90 Bit Fields */ +#define CCM_PRE90_PRE_PODF_B_MASK 0x7u +#define CCM_PRE90_PRE_PODF_B_SHIFT 0 +#define CCM_PRE90_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_PRE_PODF_B_SHIFT))&CCM_PRE90_PRE_PODF_B_MASK) +#define CCM_PRE90_BUSY0_MASK 0x8u +#define CCM_PRE90_BUSY0_SHIFT 3 +#define CCM_PRE90_MUX_B_MASK 0x700u +#define CCM_PRE90_MUX_B_SHIFT 8 +#define CCM_PRE90_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_MUX_B_SHIFT))&CCM_PRE90_MUX_B_MASK) +#define CCM_PRE90_EN_B_MASK 0x1000u +#define CCM_PRE90_EN_B_SHIFT 12 +#define CCM_PRE90_BUSY1_MASK 0x8000u +#define CCM_PRE90_BUSY1_SHIFT 15 +#define CCM_PRE90_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE90_PRE_PODF_A_SHIFT 16 +#define CCM_PRE90_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_PRE_PODF_A_SHIFT))&CCM_PRE90_PRE_PODF_A_MASK) +#define CCM_PRE90_BUSY3_MASK 0x80000u +#define CCM_PRE90_BUSY3_SHIFT 19 +#define CCM_PRE90_MUX_A_MASK 0x7000000u +#define CCM_PRE90_MUX_A_SHIFT 24 +#define CCM_PRE90_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE90_MUX_A_SHIFT))&CCM_PRE90_MUX_A_MASK) +#define CCM_PRE90_EN_A_MASK 0x10000000u +#define CCM_PRE90_EN_A_SHIFT 28 +#define CCM_PRE90_BUSY4_MASK 0x80000000u +#define CCM_PRE90_BUSY4_SHIFT 31 +/* PRE_ROOT90_SET Bit Fields */ +#define CCM_PRE_ROOT90_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT90_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT90_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT90_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT90_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT90_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT90_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT90_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT90_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_MUX_B_SHIFT))&CCM_PRE_ROOT90_SET_MUX_B_MASK) +#define CCM_PRE_ROOT90_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT90_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT90_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT90_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT90_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT90_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT90_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT90_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT90_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT90_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT90_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT90_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT90_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_SET_MUX_A_SHIFT))&CCM_PRE_ROOT90_SET_MUX_A_MASK) +#define CCM_PRE_ROOT90_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT90_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT90_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT90_SET_BUSY4_SHIFT 31 +/* PRE_ROOT90_CLR Bit Fields */ +#define CCM_PRE_ROOT90_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT90_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT90_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT90_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT90_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT90_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT90_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT90_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT90_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT90_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT90_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT90_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT90_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT90_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT90_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT90_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT90_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT90_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT90_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT90_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT90_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT90_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT90_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT90_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT90_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT90_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT90_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT90_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT90_TOG Bit Fields */ +#define CCM_PRE_ROOT90_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT90_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT90_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT90_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT90_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT90_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT90_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT90_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT90_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT90_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT90_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT90_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT90_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT90_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT90_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT90_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT90_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT90_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT90_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT90_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT90_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT90_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT90_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT90_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT90_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT90_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT90_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT90_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT90_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL90 Bit Fields */ +#define CCM_ACCESS_CTRL90_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL90_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL90_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL90_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL90_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL90_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL90_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL90_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL90_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL90_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL90_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL90_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL90_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL90_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL90_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL90_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL90_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL90_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL90_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL90_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL90_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL90_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL90_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL90_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL90_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL90_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL90_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL90_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL90_LOCK_SHIFT 31 +/* ACCESS_CTRL90_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL90_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL90_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL90_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL90_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL90_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL90_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL90_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL90_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL90_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL90_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL90_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL90_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL90_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL90_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL90_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL90_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL90_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL90_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT91 Bit Fields */ +#define CCM_TARGET_ROOT91_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT91_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT91_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_POST_PODF_MASK) +#define CCM_TARGET_ROOT91_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT91_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT91_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT91_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT91_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT91_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT91_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT91_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT91_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT91_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_PRE_PODF_MASK) +#define CCM_TARGET_ROOT91_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT91_MUX_SHIFT 24 +#define CCM_TARGET_ROOT91_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_MUX_SHIFT))&CCM_TARGET_ROOT91_MUX_MASK) +#define CCM_TARGET_ROOT91_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT91_ENABLE_SHIFT 28 +/* TARGET_ROOT91_SET Bit Fields */ +#define CCM_TARGET_ROOT91_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT91_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT91_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT91_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT91_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT91_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT91_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT91_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT91_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT91_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT91_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT91_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT91_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT91_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT91_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT91_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_SET_MUX_SHIFT))&CCM_TARGET_ROOT91_SET_MUX_MASK) +#define CCM_TARGET_ROOT91_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT91_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT91_CLR Bit Fields */ +#define CCM_TARGET_ROOT91_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT91_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT91_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT91_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT91_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT91_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT91_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT91_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT91_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT91_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT91_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT91_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT91_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_CLR_MUX_SHIFT))&CCM_TARGET_ROOT91_CLR_MUX_MASK) +#define CCM_TARGET_ROOT91_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT91_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT91_TOG Bit Fields */ +#define CCM_TARGET_ROOT91_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT91_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT91_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT91_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT91_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT91_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT91_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT91_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT91_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT91_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT91_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT91_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT91_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT91_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT91_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT91_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT91_TOG_MUX_SHIFT))&CCM_TARGET_ROOT91_TOG_MUX_MASK) +#define CCM_TARGET_ROOT91_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT91_TOG_ENABLE_SHIFT 28 +/* POST91 Bit Fields */ +#define CCM_POST91_POST_PODF_MASK 0x3Fu +#define CCM_POST91_POST_PODF_SHIFT 0 +#define CCM_POST91_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST91_POST_PODF_SHIFT))&CCM_POST91_POST_PODF_MASK) +#define CCM_POST91_BUSY1_MASK 0x80u +#define CCM_POST91_BUSY1_SHIFT 7 +#define CCM_POST91_AUTO_PODF_MASK 0x700u +#define CCM_POST91_AUTO_PODF_SHIFT 8 +#define CCM_POST91_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST91_AUTO_PODF_SHIFT))&CCM_POST91_AUTO_PODF_MASK) +#define CCM_POST91_AUTO_EN_MASK 0x1000u +#define CCM_POST91_AUTO_EN_SHIFT 12 +#define CCM_POST91_SLOW_MASK 0x8000u +#define CCM_POST91_SLOW_SHIFT 15 +#define CCM_POST91_SELECT_MASK 0x10000000u +#define CCM_POST91_SELECT_SHIFT 28 +#define CCM_POST91_BUSY2_MASK 0x80000000u +#define CCM_POST91_BUSY2_SHIFT 31 +/* POST_ROOT91_SET Bit Fields */ +#define CCM_POST_ROOT91_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT91_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT91_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_SET_POST_PODF_SHIFT))&CCM_POST_ROOT91_SET_POST_PODF_MASK) +#define CCM_POST_ROOT91_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT91_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT91_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT91_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT91_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT91_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT91_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT91_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT91_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT91_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT91_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT91_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT91_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT91_SET_BUSY2_SHIFT 31 +/* POST_ROOT91_CLR Bit Fields */ +#define CCM_POST_ROOT91_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT91_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT91_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT91_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT91_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT91_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT91_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT91_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT91_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT91_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT91_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT91_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT91_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT91_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT91_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT91_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT91_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT91_CLR_BUSY2_SHIFT 31 +/* POST_ROOT91_TOG Bit Fields */ +#define CCM_POST_ROOT91_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT91_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT91_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT91_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT91_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT91_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT91_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT91_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT91_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT91_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT91_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT91_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT91_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT91_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT91_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT91_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT91_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT91_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT91_TOG_BUSY2_SHIFT 31 +/* PRE91 Bit Fields */ +#define CCM_PRE91_PRE_PODF_B_MASK 0x7u +#define CCM_PRE91_PRE_PODF_B_SHIFT 0 +#define CCM_PRE91_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_PRE_PODF_B_SHIFT))&CCM_PRE91_PRE_PODF_B_MASK) +#define CCM_PRE91_BUSY0_MASK 0x8u +#define CCM_PRE91_BUSY0_SHIFT 3 +#define CCM_PRE91_MUX_B_MASK 0x700u +#define CCM_PRE91_MUX_B_SHIFT 8 +#define CCM_PRE91_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_MUX_B_SHIFT))&CCM_PRE91_MUX_B_MASK) +#define CCM_PRE91_EN_B_MASK 0x1000u +#define CCM_PRE91_EN_B_SHIFT 12 +#define CCM_PRE91_BUSY1_MASK 0x8000u +#define CCM_PRE91_BUSY1_SHIFT 15 +#define CCM_PRE91_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE91_PRE_PODF_A_SHIFT 16 +#define CCM_PRE91_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_PRE_PODF_A_SHIFT))&CCM_PRE91_PRE_PODF_A_MASK) +#define CCM_PRE91_BUSY3_MASK 0x80000u +#define CCM_PRE91_BUSY3_SHIFT 19 +#define CCM_PRE91_MUX_A_MASK 0x7000000u +#define CCM_PRE91_MUX_A_SHIFT 24 +#define CCM_PRE91_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE91_MUX_A_SHIFT))&CCM_PRE91_MUX_A_MASK) +#define CCM_PRE91_EN_A_MASK 0x10000000u +#define CCM_PRE91_EN_A_SHIFT 28 +#define CCM_PRE91_BUSY4_MASK 0x80000000u +#define CCM_PRE91_BUSY4_SHIFT 31 +/* PRE_ROOT91_SET Bit Fields */ +#define CCM_PRE_ROOT91_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT91_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT91_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT91_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT91_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT91_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT91_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT91_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT91_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_MUX_B_SHIFT))&CCM_PRE_ROOT91_SET_MUX_B_MASK) +#define CCM_PRE_ROOT91_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT91_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT91_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT91_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT91_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT91_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT91_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT91_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT91_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT91_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT91_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT91_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT91_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_SET_MUX_A_SHIFT))&CCM_PRE_ROOT91_SET_MUX_A_MASK) +#define CCM_PRE_ROOT91_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT91_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT91_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT91_SET_BUSY4_SHIFT 31 +/* PRE_ROOT91_CLR Bit Fields */ +#define CCM_PRE_ROOT91_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT91_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT91_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT91_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT91_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT91_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT91_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT91_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT91_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT91_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT91_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT91_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT91_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT91_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT91_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT91_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT91_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT91_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT91_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT91_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT91_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT91_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT91_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT91_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT91_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT91_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT91_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT91_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT91_TOG Bit Fields */ +#define CCM_PRE_ROOT91_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT91_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT91_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT91_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT91_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT91_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT91_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT91_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT91_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT91_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT91_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT91_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT91_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT91_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT91_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT91_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT91_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT91_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT91_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT91_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT91_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT91_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT91_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT91_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT91_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT91_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT91_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT91_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT91_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL91 Bit Fields */ +#define CCM_ACCESS_CTRL91_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL91_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL91_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL91_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL91_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL91_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL91_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL91_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL91_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL91_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL91_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL91_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL91_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL91_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL91_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL91_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL91_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL91_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL91_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL91_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL91_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL91_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL91_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL91_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL91_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL91_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL91_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL91_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL91_LOCK_SHIFT 31 +/* ACCESS_CTRL91_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL91_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL91_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL91_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL91_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL91_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL91_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL91_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL91_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL91_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL91_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL91_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL91_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL91_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL91_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL91_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL91_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL91_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL91_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT92 Bit Fields */ +#define CCM_TARGET_ROOT92_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT92_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT92_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_POST_PODF_MASK) +#define CCM_TARGET_ROOT92_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT92_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT92_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT92_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT92_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT92_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT92_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT92_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT92_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT92_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_PRE_PODF_MASK) +#define CCM_TARGET_ROOT92_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT92_MUX_SHIFT 24 +#define CCM_TARGET_ROOT92_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_MUX_SHIFT))&CCM_TARGET_ROOT92_MUX_MASK) +#define CCM_TARGET_ROOT92_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT92_ENABLE_SHIFT 28 +/* TARGET_ROOT92_SET Bit Fields */ +#define CCM_TARGET_ROOT92_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT92_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT92_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT92_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT92_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT92_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT92_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT92_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT92_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT92_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT92_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT92_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT92_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT92_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT92_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT92_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_SET_MUX_SHIFT))&CCM_TARGET_ROOT92_SET_MUX_MASK) +#define CCM_TARGET_ROOT92_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT92_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT92_CLR Bit Fields */ +#define CCM_TARGET_ROOT92_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT92_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT92_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT92_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT92_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT92_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT92_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT92_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT92_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT92_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT92_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT92_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT92_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_CLR_MUX_SHIFT))&CCM_TARGET_ROOT92_CLR_MUX_MASK) +#define CCM_TARGET_ROOT92_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT92_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT92_TOG Bit Fields */ +#define CCM_TARGET_ROOT92_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT92_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT92_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT92_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT92_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT92_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT92_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT92_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT92_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT92_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT92_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT92_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT92_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT92_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT92_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT92_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT92_TOG_MUX_SHIFT))&CCM_TARGET_ROOT92_TOG_MUX_MASK) +#define CCM_TARGET_ROOT92_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT92_TOG_ENABLE_SHIFT 28 +/* POST92 Bit Fields */ +#define CCM_POST92_POST_PODF_MASK 0x3Fu +#define CCM_POST92_POST_PODF_SHIFT 0 +#define CCM_POST92_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST92_POST_PODF_SHIFT))&CCM_POST92_POST_PODF_MASK) +#define CCM_POST92_BUSY1_MASK 0x80u +#define CCM_POST92_BUSY1_SHIFT 7 +#define CCM_POST92_AUTO_PODF_MASK 0x700u +#define CCM_POST92_AUTO_PODF_SHIFT 8 +#define CCM_POST92_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST92_AUTO_PODF_SHIFT))&CCM_POST92_AUTO_PODF_MASK) +#define CCM_POST92_AUTO_EN_MASK 0x1000u +#define CCM_POST92_AUTO_EN_SHIFT 12 +#define CCM_POST92_SLOW_MASK 0x8000u +#define CCM_POST92_SLOW_SHIFT 15 +#define CCM_POST92_SELECT_MASK 0x10000000u +#define CCM_POST92_SELECT_SHIFT 28 +#define CCM_POST92_BUSY2_MASK 0x80000000u +#define CCM_POST92_BUSY2_SHIFT 31 +/* POST_ROOT92_SET Bit Fields */ +#define CCM_POST_ROOT92_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT92_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT92_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_SET_POST_PODF_SHIFT))&CCM_POST_ROOT92_SET_POST_PODF_MASK) +#define CCM_POST_ROOT92_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT92_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT92_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT92_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT92_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT92_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT92_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT92_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT92_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT92_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT92_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT92_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT92_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT92_SET_BUSY2_SHIFT 31 +/* POST_ROOT92_CLR Bit Fields */ +#define CCM_POST_ROOT92_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT92_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT92_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT92_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT92_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT92_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT92_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT92_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT92_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT92_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT92_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT92_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT92_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT92_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT92_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT92_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT92_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT92_CLR_BUSY2_SHIFT 31 +/* POST_ROOT92_TOG Bit Fields */ +#define CCM_POST_ROOT92_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT92_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT92_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT92_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT92_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT92_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT92_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT92_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT92_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT92_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT92_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT92_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT92_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT92_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT92_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT92_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT92_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT92_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT92_TOG_BUSY2_SHIFT 31 +/* PRE92 Bit Fields */ +#define CCM_PRE92_PRE_PODF_B_MASK 0x7u +#define CCM_PRE92_PRE_PODF_B_SHIFT 0 +#define CCM_PRE92_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_PRE_PODF_B_SHIFT))&CCM_PRE92_PRE_PODF_B_MASK) +#define CCM_PRE92_BUSY0_MASK 0x8u +#define CCM_PRE92_BUSY0_SHIFT 3 +#define CCM_PRE92_MUX_B_MASK 0x700u +#define CCM_PRE92_MUX_B_SHIFT 8 +#define CCM_PRE92_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_MUX_B_SHIFT))&CCM_PRE92_MUX_B_MASK) +#define CCM_PRE92_EN_B_MASK 0x1000u +#define CCM_PRE92_EN_B_SHIFT 12 +#define CCM_PRE92_BUSY1_MASK 0x8000u +#define CCM_PRE92_BUSY1_SHIFT 15 +#define CCM_PRE92_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE92_PRE_PODF_A_SHIFT 16 +#define CCM_PRE92_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_PRE_PODF_A_SHIFT))&CCM_PRE92_PRE_PODF_A_MASK) +#define CCM_PRE92_BUSY3_MASK 0x80000u +#define CCM_PRE92_BUSY3_SHIFT 19 +#define CCM_PRE92_MUX_A_MASK 0x7000000u +#define CCM_PRE92_MUX_A_SHIFT 24 +#define CCM_PRE92_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE92_MUX_A_SHIFT))&CCM_PRE92_MUX_A_MASK) +#define CCM_PRE92_EN_A_MASK 0x10000000u +#define CCM_PRE92_EN_A_SHIFT 28 +#define CCM_PRE92_BUSY4_MASK 0x80000000u +#define CCM_PRE92_BUSY4_SHIFT 31 +/* PRE_ROOT92_SET Bit Fields */ +#define CCM_PRE_ROOT92_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT92_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT92_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT92_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT92_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT92_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT92_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT92_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT92_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_MUX_B_SHIFT))&CCM_PRE_ROOT92_SET_MUX_B_MASK) +#define CCM_PRE_ROOT92_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT92_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT92_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT92_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT92_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT92_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT92_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT92_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT92_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT92_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT92_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT92_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT92_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_SET_MUX_A_SHIFT))&CCM_PRE_ROOT92_SET_MUX_A_MASK) +#define CCM_PRE_ROOT92_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT92_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT92_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT92_SET_BUSY4_SHIFT 31 +/* PRE_ROOT92_CLR Bit Fields */ +#define CCM_PRE_ROOT92_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT92_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT92_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT92_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT92_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT92_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT92_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT92_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT92_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT92_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT92_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT92_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT92_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT92_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT92_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT92_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT92_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT92_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT92_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT92_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT92_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT92_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT92_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT92_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT92_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT92_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT92_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT92_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT92_TOG Bit Fields */ +#define CCM_PRE_ROOT92_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT92_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT92_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT92_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT92_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT92_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT92_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT92_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT92_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT92_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT92_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT92_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT92_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT92_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT92_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT92_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT92_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT92_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT92_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT92_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT92_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT92_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT92_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT92_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT92_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT92_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT92_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT92_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT92_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL92 Bit Fields */ +#define CCM_ACCESS_CTRL92_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL92_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL92_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL92_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL92_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL92_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL92_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL92_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL92_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL92_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL92_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL92_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL92_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL92_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL92_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL92_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL92_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL92_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL92_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL92_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL92_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL92_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL92_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL92_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL92_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL92_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL92_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL92_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL92_LOCK_SHIFT 31 +/* ACCESS_CTRL92_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL92_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL92_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL92_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL92_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL92_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL92_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL92_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL92_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL92_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL92_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL92_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL92_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL92_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL92_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL92_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL92_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL92_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL92_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT93 Bit Fields */ +#define CCM_TARGET_ROOT93_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT93_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT93_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_POST_PODF_MASK) +#define CCM_TARGET_ROOT93_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT93_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT93_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT93_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT93_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT93_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT93_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT93_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT93_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT93_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_PRE_PODF_MASK) +#define CCM_TARGET_ROOT93_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT93_MUX_SHIFT 24 +#define CCM_TARGET_ROOT93_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_MUX_SHIFT))&CCM_TARGET_ROOT93_MUX_MASK) +#define CCM_TARGET_ROOT93_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT93_ENABLE_SHIFT 28 +/* TARGET_ROOT93_SET Bit Fields */ +#define CCM_TARGET_ROOT93_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT93_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT93_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT93_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT93_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT93_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT93_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT93_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT93_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT93_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT93_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT93_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT93_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT93_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT93_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT93_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_SET_MUX_SHIFT))&CCM_TARGET_ROOT93_SET_MUX_MASK) +#define CCM_TARGET_ROOT93_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT93_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT93_CLR Bit Fields */ +#define CCM_TARGET_ROOT93_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT93_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT93_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT93_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT93_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT93_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT93_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT93_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT93_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT93_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT93_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT93_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT93_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_CLR_MUX_SHIFT))&CCM_TARGET_ROOT93_CLR_MUX_MASK) +#define CCM_TARGET_ROOT93_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT93_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT93_TOG Bit Fields */ +#define CCM_TARGET_ROOT93_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT93_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT93_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT93_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT93_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT93_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT93_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT93_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT93_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT93_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT93_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT93_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT93_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT93_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT93_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT93_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT93_TOG_MUX_SHIFT))&CCM_TARGET_ROOT93_TOG_MUX_MASK) +#define CCM_TARGET_ROOT93_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT93_TOG_ENABLE_SHIFT 28 +/* POST93 Bit Fields */ +#define CCM_POST93_POST_PODF_MASK 0x3Fu +#define CCM_POST93_POST_PODF_SHIFT 0 +#define CCM_POST93_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST93_POST_PODF_SHIFT))&CCM_POST93_POST_PODF_MASK) +#define CCM_POST93_BUSY1_MASK 0x80u +#define CCM_POST93_BUSY1_SHIFT 7 +#define CCM_POST93_AUTO_PODF_MASK 0x700u +#define CCM_POST93_AUTO_PODF_SHIFT 8 +#define CCM_POST93_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST93_AUTO_PODF_SHIFT))&CCM_POST93_AUTO_PODF_MASK) +#define CCM_POST93_AUTO_EN_MASK 0x1000u +#define CCM_POST93_AUTO_EN_SHIFT 12 +#define CCM_POST93_SLOW_MASK 0x8000u +#define CCM_POST93_SLOW_SHIFT 15 +#define CCM_POST93_SELECT_MASK 0x10000000u +#define CCM_POST93_SELECT_SHIFT 28 +#define CCM_POST93_BUSY2_MASK 0x80000000u +#define CCM_POST93_BUSY2_SHIFT 31 +/* POST_ROOT93_SET Bit Fields */ +#define CCM_POST_ROOT93_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT93_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT93_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_SET_POST_PODF_SHIFT))&CCM_POST_ROOT93_SET_POST_PODF_MASK) +#define CCM_POST_ROOT93_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT93_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT93_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT93_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT93_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT93_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT93_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT93_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT93_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT93_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT93_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT93_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT93_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT93_SET_BUSY2_SHIFT 31 +/* POST_ROOT93_CLR Bit Fields */ +#define CCM_POST_ROOT93_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT93_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT93_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT93_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT93_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT93_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT93_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT93_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT93_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT93_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT93_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT93_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT93_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT93_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT93_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT93_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT93_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT93_CLR_BUSY2_SHIFT 31 +/* POST_ROOT93_TOG Bit Fields */ +#define CCM_POST_ROOT93_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT93_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT93_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT93_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT93_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT93_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT93_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT93_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT93_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT93_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT93_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT93_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT93_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT93_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT93_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT93_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT93_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT93_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT93_TOG_BUSY2_SHIFT 31 +/* PRE93 Bit Fields */ +#define CCM_PRE93_PRE_PODF_B_MASK 0x7u +#define CCM_PRE93_PRE_PODF_B_SHIFT 0 +#define CCM_PRE93_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_PRE_PODF_B_SHIFT))&CCM_PRE93_PRE_PODF_B_MASK) +#define CCM_PRE93_BUSY0_MASK 0x8u +#define CCM_PRE93_BUSY0_SHIFT 3 +#define CCM_PRE93_MUX_B_MASK 0x700u +#define CCM_PRE93_MUX_B_SHIFT 8 +#define CCM_PRE93_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_MUX_B_SHIFT))&CCM_PRE93_MUX_B_MASK) +#define CCM_PRE93_EN_B_MASK 0x1000u +#define CCM_PRE93_EN_B_SHIFT 12 +#define CCM_PRE93_BUSY1_MASK 0x8000u +#define CCM_PRE93_BUSY1_SHIFT 15 +#define CCM_PRE93_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE93_PRE_PODF_A_SHIFT 16 +#define CCM_PRE93_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_PRE_PODF_A_SHIFT))&CCM_PRE93_PRE_PODF_A_MASK) +#define CCM_PRE93_BUSY3_MASK 0x80000u +#define CCM_PRE93_BUSY3_SHIFT 19 +#define CCM_PRE93_MUX_A_MASK 0x7000000u +#define CCM_PRE93_MUX_A_SHIFT 24 +#define CCM_PRE93_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE93_MUX_A_SHIFT))&CCM_PRE93_MUX_A_MASK) +#define CCM_PRE93_EN_A_MASK 0x10000000u +#define CCM_PRE93_EN_A_SHIFT 28 +#define CCM_PRE93_BUSY4_MASK 0x80000000u +#define CCM_PRE93_BUSY4_SHIFT 31 +/* PRE_ROOT93_SET Bit Fields */ +#define CCM_PRE_ROOT93_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT93_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT93_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT93_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT93_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT93_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT93_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT93_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT93_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_MUX_B_SHIFT))&CCM_PRE_ROOT93_SET_MUX_B_MASK) +#define CCM_PRE_ROOT93_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT93_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT93_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT93_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT93_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT93_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT93_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT93_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT93_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT93_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT93_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT93_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT93_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_SET_MUX_A_SHIFT))&CCM_PRE_ROOT93_SET_MUX_A_MASK) +#define CCM_PRE_ROOT93_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT93_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT93_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT93_SET_BUSY4_SHIFT 31 +/* PRE_ROOT93_CLR Bit Fields */ +#define CCM_PRE_ROOT93_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT93_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT93_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT93_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT93_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT93_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT93_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT93_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT93_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT93_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT93_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT93_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT93_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT93_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT93_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT93_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT93_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT93_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT93_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT93_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT93_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT93_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT93_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT93_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT93_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT93_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT93_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT93_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT93_TOG Bit Fields */ +#define CCM_PRE_ROOT93_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT93_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT93_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT93_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT93_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT93_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT93_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT93_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT93_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT93_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT93_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT93_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT93_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT93_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT93_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT93_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT93_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT93_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT93_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT93_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT93_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT93_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT93_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT93_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT93_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT93_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT93_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT93_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT93_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL93 Bit Fields */ +#define CCM_ACCESS_CTRL93_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL93_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL93_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL93_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL93_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL93_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL93_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL93_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL93_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL93_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL93_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL93_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL93_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL93_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL93_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL93_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL93_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL93_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL93_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL93_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL93_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL93_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL93_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL93_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL93_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL93_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL93_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL93_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL93_LOCK_SHIFT 31 +/* ACCESS_CTRL93_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL93_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL93_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL93_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL93_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL93_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL93_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL93_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL93_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL93_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL93_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL93_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL93_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL93_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL93_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL93_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL93_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL93_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL93_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT94 Bit Fields */ +#define CCM_TARGET_ROOT94_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT94_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT94_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_POST_PODF_MASK) +#define CCM_TARGET_ROOT94_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT94_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT94_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT94_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT94_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT94_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT94_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT94_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT94_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT94_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_PRE_PODF_MASK) +#define CCM_TARGET_ROOT94_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT94_MUX_SHIFT 24 +#define CCM_TARGET_ROOT94_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_MUX_SHIFT))&CCM_TARGET_ROOT94_MUX_MASK) +#define CCM_TARGET_ROOT94_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT94_ENABLE_SHIFT 28 +/* TARGET_ROOT94_SET Bit Fields */ +#define CCM_TARGET_ROOT94_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT94_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT94_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT94_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT94_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT94_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT94_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT94_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT94_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT94_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT94_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT94_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT94_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT94_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT94_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT94_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_SET_MUX_SHIFT))&CCM_TARGET_ROOT94_SET_MUX_MASK) +#define CCM_TARGET_ROOT94_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT94_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT94_CLR Bit Fields */ +#define CCM_TARGET_ROOT94_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT94_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT94_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT94_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT94_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT94_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT94_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT94_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT94_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT94_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT94_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT94_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT94_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_CLR_MUX_SHIFT))&CCM_TARGET_ROOT94_CLR_MUX_MASK) +#define CCM_TARGET_ROOT94_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT94_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT94_TOG Bit Fields */ +#define CCM_TARGET_ROOT94_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT94_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT94_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT94_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT94_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT94_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT94_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT94_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT94_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT94_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT94_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT94_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT94_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT94_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT94_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT94_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT94_TOG_MUX_SHIFT))&CCM_TARGET_ROOT94_TOG_MUX_MASK) +#define CCM_TARGET_ROOT94_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT94_TOG_ENABLE_SHIFT 28 +/* POST94 Bit Fields */ +#define CCM_POST94_POST_PODF_MASK 0x3Fu +#define CCM_POST94_POST_PODF_SHIFT 0 +#define CCM_POST94_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST94_POST_PODF_SHIFT))&CCM_POST94_POST_PODF_MASK) +#define CCM_POST94_BUSY1_MASK 0x80u +#define CCM_POST94_BUSY1_SHIFT 7 +#define CCM_POST94_AUTO_PODF_MASK 0x700u +#define CCM_POST94_AUTO_PODF_SHIFT 8 +#define CCM_POST94_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST94_AUTO_PODF_SHIFT))&CCM_POST94_AUTO_PODF_MASK) +#define CCM_POST94_AUTO_EN_MASK 0x1000u +#define CCM_POST94_AUTO_EN_SHIFT 12 +#define CCM_POST94_SLOW_MASK 0x8000u +#define CCM_POST94_SLOW_SHIFT 15 +#define CCM_POST94_SELECT_MASK 0x10000000u +#define CCM_POST94_SELECT_SHIFT 28 +#define CCM_POST94_BUSY2_MASK 0x80000000u +#define CCM_POST94_BUSY2_SHIFT 31 +/* POST_ROOT94_SET Bit Fields */ +#define CCM_POST_ROOT94_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT94_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT94_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_SET_POST_PODF_SHIFT))&CCM_POST_ROOT94_SET_POST_PODF_MASK) +#define CCM_POST_ROOT94_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT94_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT94_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT94_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT94_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT94_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT94_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT94_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT94_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT94_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT94_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT94_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT94_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT94_SET_BUSY2_SHIFT 31 +/* POST_ROOT94_CLR Bit Fields */ +#define CCM_POST_ROOT94_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT94_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT94_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT94_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT94_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT94_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT94_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT94_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT94_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT94_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT94_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT94_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT94_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT94_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT94_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT94_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT94_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT94_CLR_BUSY2_SHIFT 31 +/* POST_ROOT94_TOG Bit Fields */ +#define CCM_POST_ROOT94_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT94_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT94_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT94_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT94_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT94_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT94_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT94_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT94_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT94_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT94_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT94_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT94_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT94_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT94_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT94_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT94_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT94_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT94_TOG_BUSY2_SHIFT 31 +/* PRE94 Bit Fields */ +#define CCM_PRE94_PRE_PODF_B_MASK 0x7u +#define CCM_PRE94_PRE_PODF_B_SHIFT 0 +#define CCM_PRE94_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_PRE_PODF_B_SHIFT))&CCM_PRE94_PRE_PODF_B_MASK) +#define CCM_PRE94_BUSY0_MASK 0x8u +#define CCM_PRE94_BUSY0_SHIFT 3 +#define CCM_PRE94_MUX_B_MASK 0x700u +#define CCM_PRE94_MUX_B_SHIFT 8 +#define CCM_PRE94_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_MUX_B_SHIFT))&CCM_PRE94_MUX_B_MASK) +#define CCM_PRE94_EN_B_MASK 0x1000u +#define CCM_PRE94_EN_B_SHIFT 12 +#define CCM_PRE94_BUSY1_MASK 0x8000u +#define CCM_PRE94_BUSY1_SHIFT 15 +#define CCM_PRE94_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE94_PRE_PODF_A_SHIFT 16 +#define CCM_PRE94_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_PRE_PODF_A_SHIFT))&CCM_PRE94_PRE_PODF_A_MASK) +#define CCM_PRE94_BUSY3_MASK 0x80000u +#define CCM_PRE94_BUSY3_SHIFT 19 +#define CCM_PRE94_MUX_A_MASK 0x7000000u +#define CCM_PRE94_MUX_A_SHIFT 24 +#define CCM_PRE94_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE94_MUX_A_SHIFT))&CCM_PRE94_MUX_A_MASK) +#define CCM_PRE94_EN_A_MASK 0x10000000u +#define CCM_PRE94_EN_A_SHIFT 28 +#define CCM_PRE94_BUSY4_MASK 0x80000000u +#define CCM_PRE94_BUSY4_SHIFT 31 +/* PRE_ROOT94_SET Bit Fields */ +#define CCM_PRE_ROOT94_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT94_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT94_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT94_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT94_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT94_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT94_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT94_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT94_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_MUX_B_SHIFT))&CCM_PRE_ROOT94_SET_MUX_B_MASK) +#define CCM_PRE_ROOT94_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT94_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT94_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT94_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT94_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT94_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT94_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT94_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT94_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT94_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT94_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT94_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT94_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_SET_MUX_A_SHIFT))&CCM_PRE_ROOT94_SET_MUX_A_MASK) +#define CCM_PRE_ROOT94_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT94_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT94_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT94_SET_BUSY4_SHIFT 31 +/* PRE_ROOT94_CLR Bit Fields */ +#define CCM_PRE_ROOT94_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT94_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT94_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT94_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT94_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT94_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT94_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT94_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT94_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT94_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT94_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT94_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT94_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT94_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT94_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT94_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT94_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT94_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT94_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT94_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT94_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT94_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT94_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT94_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT94_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT94_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT94_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT94_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT94_TOG Bit Fields */ +#define CCM_PRE_ROOT94_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT94_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT94_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT94_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT94_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT94_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT94_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT94_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT94_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT94_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT94_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT94_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT94_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT94_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT94_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT94_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT94_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT94_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT94_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT94_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT94_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT94_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT94_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT94_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT94_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT94_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT94_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT94_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT94_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL94 Bit Fields */ +#define CCM_ACCESS_CTRL94_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL94_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL94_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL94_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL94_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL94_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL94_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL94_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL94_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL94_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL94_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL94_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL94_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL94_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL94_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL94_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL94_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL94_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL94_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL94_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL94_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL94_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL94_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL94_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL94_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL94_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL94_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL94_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL94_LOCK_SHIFT 31 +/* ACCESS_CTRL94_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL94_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL94_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL94_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL94_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL94_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL94_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL94_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL94_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL94_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL94_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL94_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL94_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL94_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL94_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL94_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL94_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL94_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL94_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT95 Bit Fields */ +#define CCM_TARGET_ROOT95_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT95_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT95_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_POST_PODF_MASK) +#define CCM_TARGET_ROOT95_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT95_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT95_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT95_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT95_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT95_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT95_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT95_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT95_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT95_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_PRE_PODF_MASK) +#define CCM_TARGET_ROOT95_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT95_MUX_SHIFT 24 +#define CCM_TARGET_ROOT95_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_MUX_SHIFT))&CCM_TARGET_ROOT95_MUX_MASK) +#define CCM_TARGET_ROOT95_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT95_ENABLE_SHIFT 28 +/* TARGET_ROOT95_SET Bit Fields */ +#define CCM_TARGET_ROOT95_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT95_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT95_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT95_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT95_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT95_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT95_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT95_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT95_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT95_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT95_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT95_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT95_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT95_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT95_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT95_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_SET_MUX_SHIFT))&CCM_TARGET_ROOT95_SET_MUX_MASK) +#define CCM_TARGET_ROOT95_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT95_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT95_CLR Bit Fields */ +#define CCM_TARGET_ROOT95_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT95_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT95_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT95_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT95_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT95_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT95_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT95_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT95_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT95_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT95_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT95_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT95_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_CLR_MUX_SHIFT))&CCM_TARGET_ROOT95_CLR_MUX_MASK) +#define CCM_TARGET_ROOT95_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT95_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT95_TOG Bit Fields */ +#define CCM_TARGET_ROOT95_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT95_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT95_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT95_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT95_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT95_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT95_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT95_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT95_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT95_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT95_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT95_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT95_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT95_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT95_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT95_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT95_TOG_MUX_SHIFT))&CCM_TARGET_ROOT95_TOG_MUX_MASK) +#define CCM_TARGET_ROOT95_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT95_TOG_ENABLE_SHIFT 28 +/* POST95 Bit Fields */ +#define CCM_POST95_POST_PODF_MASK 0x3Fu +#define CCM_POST95_POST_PODF_SHIFT 0 +#define CCM_POST95_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST95_POST_PODF_SHIFT))&CCM_POST95_POST_PODF_MASK) +#define CCM_POST95_BUSY1_MASK 0x80u +#define CCM_POST95_BUSY1_SHIFT 7 +#define CCM_POST95_AUTO_PODF_MASK 0x700u +#define CCM_POST95_AUTO_PODF_SHIFT 8 +#define CCM_POST95_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST95_AUTO_PODF_SHIFT))&CCM_POST95_AUTO_PODF_MASK) +#define CCM_POST95_AUTO_EN_MASK 0x1000u +#define CCM_POST95_AUTO_EN_SHIFT 12 +#define CCM_POST95_SLOW_MASK 0x8000u +#define CCM_POST95_SLOW_SHIFT 15 +#define CCM_POST95_SELECT_MASK 0x10000000u +#define CCM_POST95_SELECT_SHIFT 28 +#define CCM_POST95_BUSY2_MASK 0x80000000u +#define CCM_POST95_BUSY2_SHIFT 31 +/* POST_ROOT95_SET Bit Fields */ +#define CCM_POST_ROOT95_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT95_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT95_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_SET_POST_PODF_SHIFT))&CCM_POST_ROOT95_SET_POST_PODF_MASK) +#define CCM_POST_ROOT95_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT95_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT95_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT95_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT95_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT95_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT95_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT95_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT95_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT95_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT95_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT95_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT95_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT95_SET_BUSY2_SHIFT 31 +/* POST_ROOT95_CLR Bit Fields */ +#define CCM_POST_ROOT95_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT95_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT95_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT95_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT95_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT95_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT95_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT95_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT95_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT95_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT95_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT95_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT95_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT95_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT95_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT95_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT95_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT95_CLR_BUSY2_SHIFT 31 +/* POST_ROOT95_TOG Bit Fields */ +#define CCM_POST_ROOT95_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT95_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT95_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT95_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT95_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT95_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT95_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT95_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT95_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT95_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT95_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT95_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT95_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT95_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT95_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT95_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT95_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT95_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT95_TOG_BUSY2_SHIFT 31 +/* PRE95 Bit Fields */ +#define CCM_PRE95_PRE_PODF_B_MASK 0x7u +#define CCM_PRE95_PRE_PODF_B_SHIFT 0 +#define CCM_PRE95_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_PRE_PODF_B_SHIFT))&CCM_PRE95_PRE_PODF_B_MASK) +#define CCM_PRE95_BUSY0_MASK 0x8u +#define CCM_PRE95_BUSY0_SHIFT 3 +#define CCM_PRE95_MUX_B_MASK 0x700u +#define CCM_PRE95_MUX_B_SHIFT 8 +#define CCM_PRE95_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_MUX_B_SHIFT))&CCM_PRE95_MUX_B_MASK) +#define CCM_PRE95_EN_B_MASK 0x1000u +#define CCM_PRE95_EN_B_SHIFT 12 +#define CCM_PRE95_BUSY1_MASK 0x8000u +#define CCM_PRE95_BUSY1_SHIFT 15 +#define CCM_PRE95_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE95_PRE_PODF_A_SHIFT 16 +#define CCM_PRE95_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_PRE_PODF_A_SHIFT))&CCM_PRE95_PRE_PODF_A_MASK) +#define CCM_PRE95_BUSY3_MASK 0x80000u +#define CCM_PRE95_BUSY3_SHIFT 19 +#define CCM_PRE95_MUX_A_MASK 0x7000000u +#define CCM_PRE95_MUX_A_SHIFT 24 +#define CCM_PRE95_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE95_MUX_A_SHIFT))&CCM_PRE95_MUX_A_MASK) +#define CCM_PRE95_EN_A_MASK 0x10000000u +#define CCM_PRE95_EN_A_SHIFT 28 +#define CCM_PRE95_BUSY4_MASK 0x80000000u +#define CCM_PRE95_BUSY4_SHIFT 31 +/* PRE_ROOT95_SET Bit Fields */ +#define CCM_PRE_ROOT95_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT95_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT95_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT95_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT95_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT95_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT95_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT95_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT95_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_MUX_B_SHIFT))&CCM_PRE_ROOT95_SET_MUX_B_MASK) +#define CCM_PRE_ROOT95_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT95_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT95_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT95_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT95_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT95_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT95_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT95_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT95_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT95_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT95_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT95_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT95_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_SET_MUX_A_SHIFT))&CCM_PRE_ROOT95_SET_MUX_A_MASK) +#define CCM_PRE_ROOT95_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT95_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT95_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT95_SET_BUSY4_SHIFT 31 +/* PRE_ROOT95_CLR Bit Fields */ +#define CCM_PRE_ROOT95_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT95_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT95_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT95_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT95_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT95_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT95_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT95_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT95_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT95_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT95_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT95_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT95_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT95_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT95_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT95_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT95_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT95_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT95_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT95_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT95_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT95_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT95_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT95_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT95_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT95_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT95_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT95_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT95_TOG Bit Fields */ +#define CCM_PRE_ROOT95_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT95_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT95_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT95_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT95_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT95_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT95_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT95_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT95_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT95_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT95_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT95_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT95_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT95_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT95_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT95_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT95_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT95_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT95_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT95_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT95_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT95_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT95_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT95_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT95_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT95_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT95_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT95_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT95_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL95 Bit Fields */ +#define CCM_ACCESS_CTRL95_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL95_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL95_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL95_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL95_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL95_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL95_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL95_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL95_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL95_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL95_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL95_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL95_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL95_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL95_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL95_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL95_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL95_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL95_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL95_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL95_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL95_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL95_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL95_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL95_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL95_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL95_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL95_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL95_LOCK_SHIFT 31 +/* ACCESS_CTRL95_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL95_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL95_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL95_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL95_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL95_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL95_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL95_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL95_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL95_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL95_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL95_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL95_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL95_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL95_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL95_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL95_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL95_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL95_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT96 Bit Fields */ +#define CCM_TARGET_ROOT96_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT96_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT96_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_POST_PODF_MASK) +#define CCM_TARGET_ROOT96_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT96_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT96_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT96_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT96_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT96_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT96_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT96_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT96_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT96_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_PRE_PODF_MASK) +#define CCM_TARGET_ROOT96_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT96_MUX_SHIFT 24 +#define CCM_TARGET_ROOT96_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_MUX_SHIFT))&CCM_TARGET_ROOT96_MUX_MASK) +#define CCM_TARGET_ROOT96_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT96_ENABLE_SHIFT 28 +/* TARGET_ROOT96_SET Bit Fields */ +#define CCM_TARGET_ROOT96_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT96_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT96_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT96_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT96_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT96_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT96_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT96_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT96_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT96_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT96_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT96_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT96_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT96_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT96_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT96_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_SET_MUX_SHIFT))&CCM_TARGET_ROOT96_SET_MUX_MASK) +#define CCM_TARGET_ROOT96_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT96_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT96_CLR Bit Fields */ +#define CCM_TARGET_ROOT96_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT96_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT96_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT96_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT96_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT96_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT96_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT96_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT96_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT96_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT96_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT96_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT96_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_CLR_MUX_SHIFT))&CCM_TARGET_ROOT96_CLR_MUX_MASK) +#define CCM_TARGET_ROOT96_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT96_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT96_TOG Bit Fields */ +#define CCM_TARGET_ROOT96_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT96_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT96_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT96_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT96_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT96_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT96_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT96_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT96_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT96_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT96_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT96_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT96_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT96_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT96_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT96_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT96_TOG_MUX_SHIFT))&CCM_TARGET_ROOT96_TOG_MUX_MASK) +#define CCM_TARGET_ROOT96_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT96_TOG_ENABLE_SHIFT 28 +/* POST96 Bit Fields */ +#define CCM_POST96_POST_PODF_MASK 0x3Fu +#define CCM_POST96_POST_PODF_SHIFT 0 +#define CCM_POST96_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST96_POST_PODF_SHIFT))&CCM_POST96_POST_PODF_MASK) +#define CCM_POST96_BUSY1_MASK 0x80u +#define CCM_POST96_BUSY1_SHIFT 7 +#define CCM_POST96_AUTO_PODF_MASK 0x700u +#define CCM_POST96_AUTO_PODF_SHIFT 8 +#define CCM_POST96_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST96_AUTO_PODF_SHIFT))&CCM_POST96_AUTO_PODF_MASK) +#define CCM_POST96_AUTO_EN_MASK 0x1000u +#define CCM_POST96_AUTO_EN_SHIFT 12 +#define CCM_POST96_SLOW_MASK 0x8000u +#define CCM_POST96_SLOW_SHIFT 15 +#define CCM_POST96_SELECT_MASK 0x10000000u +#define CCM_POST96_SELECT_SHIFT 28 +#define CCM_POST96_BUSY2_MASK 0x80000000u +#define CCM_POST96_BUSY2_SHIFT 31 +/* POST_ROOT96_SET Bit Fields */ +#define CCM_POST_ROOT96_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT96_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT96_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_SET_POST_PODF_SHIFT))&CCM_POST_ROOT96_SET_POST_PODF_MASK) +#define CCM_POST_ROOT96_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT96_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT96_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT96_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT96_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT96_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT96_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT96_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT96_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT96_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT96_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT96_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT96_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT96_SET_BUSY2_SHIFT 31 +/* POST_ROOT96_CLR Bit Fields */ +#define CCM_POST_ROOT96_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT96_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT96_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT96_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT96_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT96_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT96_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT96_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT96_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT96_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT96_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT96_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT96_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT96_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT96_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT96_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT96_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT96_CLR_BUSY2_SHIFT 31 +/* POST_ROOT96_TOG Bit Fields */ +#define CCM_POST_ROOT96_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT96_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT96_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT96_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT96_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT96_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT96_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT96_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT96_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT96_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT96_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT96_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT96_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT96_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT96_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT96_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT96_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT96_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT96_TOG_BUSY2_SHIFT 31 +/* PRE96 Bit Fields */ +#define CCM_PRE96_PRE_PODF_B_MASK 0x7u +#define CCM_PRE96_PRE_PODF_B_SHIFT 0 +#define CCM_PRE96_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_PRE_PODF_B_SHIFT))&CCM_PRE96_PRE_PODF_B_MASK) +#define CCM_PRE96_BUSY0_MASK 0x8u +#define CCM_PRE96_BUSY0_SHIFT 3 +#define CCM_PRE96_MUX_B_MASK 0x700u +#define CCM_PRE96_MUX_B_SHIFT 8 +#define CCM_PRE96_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_MUX_B_SHIFT))&CCM_PRE96_MUX_B_MASK) +#define CCM_PRE96_EN_B_MASK 0x1000u +#define CCM_PRE96_EN_B_SHIFT 12 +#define CCM_PRE96_BUSY1_MASK 0x8000u +#define CCM_PRE96_BUSY1_SHIFT 15 +#define CCM_PRE96_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE96_PRE_PODF_A_SHIFT 16 +#define CCM_PRE96_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_PRE_PODF_A_SHIFT))&CCM_PRE96_PRE_PODF_A_MASK) +#define CCM_PRE96_BUSY3_MASK 0x80000u +#define CCM_PRE96_BUSY3_SHIFT 19 +#define CCM_PRE96_MUX_A_MASK 0x7000000u +#define CCM_PRE96_MUX_A_SHIFT 24 +#define CCM_PRE96_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE96_MUX_A_SHIFT))&CCM_PRE96_MUX_A_MASK) +#define CCM_PRE96_EN_A_MASK 0x10000000u +#define CCM_PRE96_EN_A_SHIFT 28 +#define CCM_PRE96_BUSY4_MASK 0x80000000u +#define CCM_PRE96_BUSY4_SHIFT 31 +/* PRE_ROOT96_SET Bit Fields */ +#define CCM_PRE_ROOT96_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT96_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT96_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT96_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT96_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT96_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT96_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT96_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT96_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_MUX_B_SHIFT))&CCM_PRE_ROOT96_SET_MUX_B_MASK) +#define CCM_PRE_ROOT96_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT96_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT96_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT96_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT96_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT96_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT96_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT96_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT96_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT96_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT96_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT96_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT96_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_SET_MUX_A_SHIFT))&CCM_PRE_ROOT96_SET_MUX_A_MASK) +#define CCM_PRE_ROOT96_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT96_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT96_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT96_SET_BUSY4_SHIFT 31 +/* PRE_ROOT96_CLR Bit Fields */ +#define CCM_PRE_ROOT96_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT96_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT96_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT96_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT96_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT96_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT96_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT96_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT96_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT96_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT96_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT96_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT96_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT96_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT96_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT96_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT96_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT96_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT96_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT96_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT96_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT96_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT96_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT96_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT96_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT96_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT96_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT96_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT96_TOG Bit Fields */ +#define CCM_PRE_ROOT96_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT96_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT96_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT96_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT96_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT96_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT96_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT96_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT96_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT96_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT96_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT96_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT96_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT96_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT96_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT96_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT96_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT96_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT96_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT96_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT96_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT96_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT96_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT96_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT96_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT96_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT96_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT96_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT96_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL96 Bit Fields */ +#define CCM_ACCESS_CTRL96_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL96_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL96_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL96_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL96_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL96_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL96_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL96_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL96_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL96_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL96_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL96_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL96_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL96_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL96_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL96_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL96_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL96_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL96_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL96_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL96_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL96_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL96_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL96_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL96_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL96_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL96_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL96_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL96_LOCK_SHIFT 31 +/* ACCESS_CTRL96_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL96_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL96_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL96_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL96_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL96_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL96_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL96_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL96_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL96_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL96_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL96_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL96_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL96_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL96_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL96_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL96_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL96_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL96_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT97 Bit Fields */ +#define CCM_TARGET_ROOT97_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT97_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT97_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_POST_PODF_MASK) +#define CCM_TARGET_ROOT97_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT97_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT97_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT97_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT97_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT97_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT97_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT97_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT97_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT97_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_PRE_PODF_MASK) +#define CCM_TARGET_ROOT97_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT97_MUX_SHIFT 24 +#define CCM_TARGET_ROOT97_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_MUX_SHIFT))&CCM_TARGET_ROOT97_MUX_MASK) +#define CCM_TARGET_ROOT97_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT97_ENABLE_SHIFT 28 +/* TARGET_ROOT97_SET Bit Fields */ +#define CCM_TARGET_ROOT97_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT97_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT97_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT97_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT97_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT97_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT97_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT97_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT97_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT97_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT97_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT97_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT97_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT97_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT97_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT97_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_SET_MUX_SHIFT))&CCM_TARGET_ROOT97_SET_MUX_MASK) +#define CCM_TARGET_ROOT97_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT97_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT97_CLR Bit Fields */ +#define CCM_TARGET_ROOT97_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT97_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT97_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT97_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT97_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT97_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT97_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT97_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT97_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT97_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT97_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT97_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT97_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_CLR_MUX_SHIFT))&CCM_TARGET_ROOT97_CLR_MUX_MASK) +#define CCM_TARGET_ROOT97_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT97_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT97_TOG Bit Fields */ +#define CCM_TARGET_ROOT97_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT97_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT97_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT97_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT97_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT97_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT97_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT97_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT97_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT97_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT97_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT97_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT97_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT97_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT97_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT97_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT97_TOG_MUX_SHIFT))&CCM_TARGET_ROOT97_TOG_MUX_MASK) +#define CCM_TARGET_ROOT97_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT97_TOG_ENABLE_SHIFT 28 +/* POST97 Bit Fields */ +#define CCM_POST97_POST_PODF_MASK 0x3Fu +#define CCM_POST97_POST_PODF_SHIFT 0 +#define CCM_POST97_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST97_POST_PODF_SHIFT))&CCM_POST97_POST_PODF_MASK) +#define CCM_POST97_BUSY1_MASK 0x80u +#define CCM_POST97_BUSY1_SHIFT 7 +#define CCM_POST97_AUTO_PODF_MASK 0x700u +#define CCM_POST97_AUTO_PODF_SHIFT 8 +#define CCM_POST97_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST97_AUTO_PODF_SHIFT))&CCM_POST97_AUTO_PODF_MASK) +#define CCM_POST97_AUTO_EN_MASK 0x1000u +#define CCM_POST97_AUTO_EN_SHIFT 12 +#define CCM_POST97_SLOW_MASK 0x8000u +#define CCM_POST97_SLOW_SHIFT 15 +#define CCM_POST97_SELECT_MASK 0x10000000u +#define CCM_POST97_SELECT_SHIFT 28 +#define CCM_POST97_BUSY2_MASK 0x80000000u +#define CCM_POST97_BUSY2_SHIFT 31 +/* POST_ROOT97_SET Bit Fields */ +#define CCM_POST_ROOT97_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT97_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT97_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_SET_POST_PODF_SHIFT))&CCM_POST_ROOT97_SET_POST_PODF_MASK) +#define CCM_POST_ROOT97_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT97_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT97_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT97_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT97_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT97_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT97_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT97_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT97_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT97_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT97_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT97_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT97_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT97_SET_BUSY2_SHIFT 31 +/* POST_ROOT97_CLR Bit Fields */ +#define CCM_POST_ROOT97_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT97_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT97_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT97_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT97_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT97_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT97_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT97_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT97_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT97_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT97_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT97_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT97_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT97_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT97_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT97_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT97_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT97_CLR_BUSY2_SHIFT 31 +/* POST_ROOT97_TOG Bit Fields */ +#define CCM_POST_ROOT97_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT97_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT97_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT97_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT97_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT97_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT97_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT97_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT97_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT97_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT97_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT97_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT97_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT97_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT97_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT97_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT97_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT97_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT97_TOG_BUSY2_SHIFT 31 +/* PRE97 Bit Fields */ +#define CCM_PRE97_PRE_PODF_B_MASK 0x7u +#define CCM_PRE97_PRE_PODF_B_SHIFT 0 +#define CCM_PRE97_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_PRE_PODF_B_SHIFT))&CCM_PRE97_PRE_PODF_B_MASK) +#define CCM_PRE97_BUSY0_MASK 0x8u +#define CCM_PRE97_BUSY0_SHIFT 3 +#define CCM_PRE97_MUX_B_MASK 0x700u +#define CCM_PRE97_MUX_B_SHIFT 8 +#define CCM_PRE97_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_MUX_B_SHIFT))&CCM_PRE97_MUX_B_MASK) +#define CCM_PRE97_EN_B_MASK 0x1000u +#define CCM_PRE97_EN_B_SHIFT 12 +#define CCM_PRE97_BUSY1_MASK 0x8000u +#define CCM_PRE97_BUSY1_SHIFT 15 +#define CCM_PRE97_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE97_PRE_PODF_A_SHIFT 16 +#define CCM_PRE97_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_PRE_PODF_A_SHIFT))&CCM_PRE97_PRE_PODF_A_MASK) +#define CCM_PRE97_BUSY3_MASK 0x80000u +#define CCM_PRE97_BUSY3_SHIFT 19 +#define CCM_PRE97_MUX_A_MASK 0x7000000u +#define CCM_PRE97_MUX_A_SHIFT 24 +#define CCM_PRE97_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE97_MUX_A_SHIFT))&CCM_PRE97_MUX_A_MASK) +#define CCM_PRE97_EN_A_MASK 0x10000000u +#define CCM_PRE97_EN_A_SHIFT 28 +#define CCM_PRE97_BUSY4_MASK 0x80000000u +#define CCM_PRE97_BUSY4_SHIFT 31 +/* PRE_ROOT97_SET Bit Fields */ +#define CCM_PRE_ROOT97_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT97_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT97_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT97_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT97_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT97_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT97_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT97_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT97_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_MUX_B_SHIFT))&CCM_PRE_ROOT97_SET_MUX_B_MASK) +#define CCM_PRE_ROOT97_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT97_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT97_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT97_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT97_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT97_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT97_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT97_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT97_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT97_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT97_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT97_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT97_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_SET_MUX_A_SHIFT))&CCM_PRE_ROOT97_SET_MUX_A_MASK) +#define CCM_PRE_ROOT97_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT97_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT97_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT97_SET_BUSY4_SHIFT 31 +/* PRE_ROOT97_CLR Bit Fields */ +#define CCM_PRE_ROOT97_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT97_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT97_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT97_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT97_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT97_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT97_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT97_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT97_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT97_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT97_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT97_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT97_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT97_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT97_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT97_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT97_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT97_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT97_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT97_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT97_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT97_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT97_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT97_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT97_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT97_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT97_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT97_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT97_TOG Bit Fields */ +#define CCM_PRE_ROOT97_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT97_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT97_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT97_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT97_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT97_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT97_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT97_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT97_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT97_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT97_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT97_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT97_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT97_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT97_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT97_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT97_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT97_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT97_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT97_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT97_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT97_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT97_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT97_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT97_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT97_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT97_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT97_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT97_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL97 Bit Fields */ +#define CCM_ACCESS_CTRL97_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL97_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL97_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL97_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL97_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL97_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL97_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL97_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL97_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL97_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL97_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL97_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL97_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL97_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL97_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL97_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL97_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL97_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL97_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL97_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL97_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL97_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL97_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL97_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL97_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL97_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL97_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL97_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL97_LOCK_SHIFT 31 +/* ACCESS_CTRL97_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL97_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL97_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL97_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL97_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL97_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL97_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL97_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL97_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL97_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL97_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL97_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL97_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL97_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL97_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL97_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL97_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL97_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL97_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT98 Bit Fields */ +#define CCM_TARGET_ROOT98_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT98_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT98_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_POST_PODF_MASK) +#define CCM_TARGET_ROOT98_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT98_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT98_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT98_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT98_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT98_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT98_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT98_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT98_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT98_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_PRE_PODF_MASK) +#define CCM_TARGET_ROOT98_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT98_MUX_SHIFT 24 +#define CCM_TARGET_ROOT98_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_MUX_SHIFT))&CCM_TARGET_ROOT98_MUX_MASK) +#define CCM_TARGET_ROOT98_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT98_ENABLE_SHIFT 28 +/* TARGET_ROOT98_SET Bit Fields */ +#define CCM_TARGET_ROOT98_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT98_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT98_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT98_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT98_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT98_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT98_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT98_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT98_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT98_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT98_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT98_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT98_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT98_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT98_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT98_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_SET_MUX_SHIFT))&CCM_TARGET_ROOT98_SET_MUX_MASK) +#define CCM_TARGET_ROOT98_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT98_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT98_CLR Bit Fields */ +#define CCM_TARGET_ROOT98_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT98_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT98_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT98_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT98_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT98_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT98_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT98_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT98_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT98_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT98_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT98_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT98_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_CLR_MUX_SHIFT))&CCM_TARGET_ROOT98_CLR_MUX_MASK) +#define CCM_TARGET_ROOT98_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT98_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT98_TOG Bit Fields */ +#define CCM_TARGET_ROOT98_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT98_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT98_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT98_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT98_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT98_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT98_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT98_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT98_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT98_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT98_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT98_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT98_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT98_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT98_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT98_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT98_TOG_MUX_SHIFT))&CCM_TARGET_ROOT98_TOG_MUX_MASK) +#define CCM_TARGET_ROOT98_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT98_TOG_ENABLE_SHIFT 28 +/* POST98 Bit Fields */ +#define CCM_POST98_POST_PODF_MASK 0x3Fu +#define CCM_POST98_POST_PODF_SHIFT 0 +#define CCM_POST98_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST98_POST_PODF_SHIFT))&CCM_POST98_POST_PODF_MASK) +#define CCM_POST98_BUSY1_MASK 0x80u +#define CCM_POST98_BUSY1_SHIFT 7 +#define CCM_POST98_AUTO_PODF_MASK 0x700u +#define CCM_POST98_AUTO_PODF_SHIFT 8 +#define CCM_POST98_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST98_AUTO_PODF_SHIFT))&CCM_POST98_AUTO_PODF_MASK) +#define CCM_POST98_AUTO_EN_MASK 0x1000u +#define CCM_POST98_AUTO_EN_SHIFT 12 +#define CCM_POST98_SLOW_MASK 0x8000u +#define CCM_POST98_SLOW_SHIFT 15 +#define CCM_POST98_SELECT_MASK 0x10000000u +#define CCM_POST98_SELECT_SHIFT 28 +#define CCM_POST98_BUSY2_MASK 0x80000000u +#define CCM_POST98_BUSY2_SHIFT 31 +/* POST_ROOT98_SET Bit Fields */ +#define CCM_POST_ROOT98_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT98_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT98_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_SET_POST_PODF_SHIFT))&CCM_POST_ROOT98_SET_POST_PODF_MASK) +#define CCM_POST_ROOT98_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT98_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT98_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT98_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT98_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT98_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT98_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT98_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT98_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT98_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT98_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT98_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT98_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT98_SET_BUSY2_SHIFT 31 +/* POST_ROOT98_CLR Bit Fields */ +#define CCM_POST_ROOT98_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT98_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT98_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT98_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT98_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT98_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT98_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT98_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT98_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT98_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT98_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT98_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT98_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT98_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT98_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT98_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT98_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT98_CLR_BUSY2_SHIFT 31 +/* POST_ROOT98_TOG Bit Fields */ +#define CCM_POST_ROOT98_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT98_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT98_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT98_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT98_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT98_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT98_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT98_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT98_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT98_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT98_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT98_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT98_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT98_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT98_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT98_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT98_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT98_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT98_TOG_BUSY2_SHIFT 31 +/* PRE98 Bit Fields */ +#define CCM_PRE98_PRE_PODF_B_MASK 0x7u +#define CCM_PRE98_PRE_PODF_B_SHIFT 0 +#define CCM_PRE98_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_PRE_PODF_B_SHIFT))&CCM_PRE98_PRE_PODF_B_MASK) +#define CCM_PRE98_BUSY0_MASK 0x8u +#define CCM_PRE98_BUSY0_SHIFT 3 +#define CCM_PRE98_MUX_B_MASK 0x700u +#define CCM_PRE98_MUX_B_SHIFT 8 +#define CCM_PRE98_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_MUX_B_SHIFT))&CCM_PRE98_MUX_B_MASK) +#define CCM_PRE98_EN_B_MASK 0x1000u +#define CCM_PRE98_EN_B_SHIFT 12 +#define CCM_PRE98_BUSY1_MASK 0x8000u +#define CCM_PRE98_BUSY1_SHIFT 15 +#define CCM_PRE98_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE98_PRE_PODF_A_SHIFT 16 +#define CCM_PRE98_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_PRE_PODF_A_SHIFT))&CCM_PRE98_PRE_PODF_A_MASK) +#define CCM_PRE98_BUSY3_MASK 0x80000u +#define CCM_PRE98_BUSY3_SHIFT 19 +#define CCM_PRE98_MUX_A_MASK 0x7000000u +#define CCM_PRE98_MUX_A_SHIFT 24 +#define CCM_PRE98_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE98_MUX_A_SHIFT))&CCM_PRE98_MUX_A_MASK) +#define CCM_PRE98_EN_A_MASK 0x10000000u +#define CCM_PRE98_EN_A_SHIFT 28 +#define CCM_PRE98_BUSY4_MASK 0x80000000u +#define CCM_PRE98_BUSY4_SHIFT 31 +/* PRE_ROOT98_SET Bit Fields */ +#define CCM_PRE_ROOT98_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT98_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT98_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT98_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT98_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT98_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT98_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT98_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT98_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_MUX_B_SHIFT))&CCM_PRE_ROOT98_SET_MUX_B_MASK) +#define CCM_PRE_ROOT98_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT98_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT98_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT98_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT98_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT98_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT98_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT98_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT98_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT98_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT98_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT98_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT98_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_SET_MUX_A_SHIFT))&CCM_PRE_ROOT98_SET_MUX_A_MASK) +#define CCM_PRE_ROOT98_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT98_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT98_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT98_SET_BUSY4_SHIFT 31 +/* PRE_ROOT98_CLR Bit Fields */ +#define CCM_PRE_ROOT98_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT98_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT98_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT98_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT98_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT98_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT98_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT98_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT98_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT98_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT98_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT98_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT98_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT98_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT98_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT98_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT98_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT98_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT98_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT98_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT98_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT98_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT98_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT98_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT98_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT98_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT98_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT98_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT98_TOG Bit Fields */ +#define CCM_PRE_ROOT98_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT98_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT98_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT98_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT98_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT98_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT98_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT98_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT98_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT98_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT98_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT98_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT98_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT98_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT98_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT98_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT98_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT98_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT98_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT98_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT98_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT98_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT98_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT98_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT98_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT98_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT98_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT98_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT98_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL98 Bit Fields */ +#define CCM_ACCESS_CTRL98_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL98_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL98_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL98_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL98_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL98_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL98_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL98_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL98_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL98_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL98_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL98_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL98_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL98_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL98_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL98_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL98_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL98_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL98_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL98_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL98_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL98_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL98_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL98_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL98_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL98_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL98_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL98_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL98_LOCK_SHIFT 31 +/* ACCESS_CTRL98_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL98_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL98_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL98_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL98_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL98_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL98_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL98_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL98_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL98_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL98_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL98_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL98_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL98_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL98_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL98_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL98_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL98_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL98_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT99 Bit Fields */ +#define CCM_TARGET_ROOT99_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT99_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT99_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_POST_PODF_MASK) +#define CCM_TARGET_ROOT99_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT99_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT99_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT99_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT99_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT99_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT99_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT99_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT99_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT99_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_PRE_PODF_MASK) +#define CCM_TARGET_ROOT99_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT99_MUX_SHIFT 24 +#define CCM_TARGET_ROOT99_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_MUX_SHIFT))&CCM_TARGET_ROOT99_MUX_MASK) +#define CCM_TARGET_ROOT99_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT99_ENABLE_SHIFT 28 +/* TARGET_ROOT99_SET Bit Fields */ +#define CCM_TARGET_ROOT99_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT99_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT99_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT99_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT99_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT99_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT99_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT99_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT99_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT99_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT99_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT99_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT99_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT99_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT99_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT99_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_SET_MUX_SHIFT))&CCM_TARGET_ROOT99_SET_MUX_MASK) +#define CCM_TARGET_ROOT99_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT99_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT99_CLR Bit Fields */ +#define CCM_TARGET_ROOT99_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT99_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT99_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT99_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT99_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT99_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT99_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT99_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT99_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT99_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT99_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT99_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT99_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_CLR_MUX_SHIFT))&CCM_TARGET_ROOT99_CLR_MUX_MASK) +#define CCM_TARGET_ROOT99_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT99_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT99_TOG Bit Fields */ +#define CCM_TARGET_ROOT99_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT99_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT99_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT99_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT99_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT99_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT99_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT99_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT99_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT99_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT99_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT99_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT99_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT99_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT99_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT99_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT99_TOG_MUX_SHIFT))&CCM_TARGET_ROOT99_TOG_MUX_MASK) +#define CCM_TARGET_ROOT99_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT99_TOG_ENABLE_SHIFT 28 +/* POST99 Bit Fields */ +#define CCM_POST99_POST_PODF_MASK 0x3Fu +#define CCM_POST99_POST_PODF_SHIFT 0 +#define CCM_POST99_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST99_POST_PODF_SHIFT))&CCM_POST99_POST_PODF_MASK) +#define CCM_POST99_BUSY1_MASK 0x80u +#define CCM_POST99_BUSY1_SHIFT 7 +#define CCM_POST99_AUTO_PODF_MASK 0x700u +#define CCM_POST99_AUTO_PODF_SHIFT 8 +#define CCM_POST99_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST99_AUTO_PODF_SHIFT))&CCM_POST99_AUTO_PODF_MASK) +#define CCM_POST99_AUTO_EN_MASK 0x1000u +#define CCM_POST99_AUTO_EN_SHIFT 12 +#define CCM_POST99_SLOW_MASK 0x8000u +#define CCM_POST99_SLOW_SHIFT 15 +#define CCM_POST99_SELECT_MASK 0x10000000u +#define CCM_POST99_SELECT_SHIFT 28 +#define CCM_POST99_BUSY2_MASK 0x80000000u +#define CCM_POST99_BUSY2_SHIFT 31 +/* POST_ROOT99_SET Bit Fields */ +#define CCM_POST_ROOT99_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT99_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT99_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_SET_POST_PODF_SHIFT))&CCM_POST_ROOT99_SET_POST_PODF_MASK) +#define CCM_POST_ROOT99_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT99_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT99_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT99_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT99_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT99_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT99_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT99_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT99_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT99_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT99_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT99_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT99_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT99_SET_BUSY2_SHIFT 31 +/* POST_ROOT99_CLR Bit Fields */ +#define CCM_POST_ROOT99_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT99_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT99_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT99_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT99_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT99_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT99_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT99_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT99_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT99_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT99_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT99_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT99_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT99_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT99_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT99_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT99_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT99_CLR_BUSY2_SHIFT 31 +/* POST_ROOT99_TOG Bit Fields */ +#define CCM_POST_ROOT99_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT99_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT99_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT99_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT99_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT99_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT99_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT99_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT99_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT99_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT99_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT99_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT99_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT99_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT99_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT99_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT99_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT99_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT99_TOG_BUSY2_SHIFT 31 +/* PRE99 Bit Fields */ +#define CCM_PRE99_PRE_PODF_B_MASK 0x7u +#define CCM_PRE99_PRE_PODF_B_SHIFT 0 +#define CCM_PRE99_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_PRE_PODF_B_SHIFT))&CCM_PRE99_PRE_PODF_B_MASK) +#define CCM_PRE99_BUSY0_MASK 0x8u +#define CCM_PRE99_BUSY0_SHIFT 3 +#define CCM_PRE99_MUX_B_MASK 0x700u +#define CCM_PRE99_MUX_B_SHIFT 8 +#define CCM_PRE99_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_MUX_B_SHIFT))&CCM_PRE99_MUX_B_MASK) +#define CCM_PRE99_EN_B_MASK 0x1000u +#define CCM_PRE99_EN_B_SHIFT 12 +#define CCM_PRE99_BUSY1_MASK 0x8000u +#define CCM_PRE99_BUSY1_SHIFT 15 +#define CCM_PRE99_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE99_PRE_PODF_A_SHIFT 16 +#define CCM_PRE99_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_PRE_PODF_A_SHIFT))&CCM_PRE99_PRE_PODF_A_MASK) +#define CCM_PRE99_BUSY3_MASK 0x80000u +#define CCM_PRE99_BUSY3_SHIFT 19 +#define CCM_PRE99_MUX_A_MASK 0x7000000u +#define CCM_PRE99_MUX_A_SHIFT 24 +#define CCM_PRE99_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE99_MUX_A_SHIFT))&CCM_PRE99_MUX_A_MASK) +#define CCM_PRE99_EN_A_MASK 0x10000000u +#define CCM_PRE99_EN_A_SHIFT 28 +#define CCM_PRE99_BUSY4_MASK 0x80000000u +#define CCM_PRE99_BUSY4_SHIFT 31 +/* PRE_ROOT99_SET Bit Fields */ +#define CCM_PRE_ROOT99_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT99_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT99_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT99_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT99_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT99_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT99_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT99_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT99_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_MUX_B_SHIFT))&CCM_PRE_ROOT99_SET_MUX_B_MASK) +#define CCM_PRE_ROOT99_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT99_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT99_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT99_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT99_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT99_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT99_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT99_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT99_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT99_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT99_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT99_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT99_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_SET_MUX_A_SHIFT))&CCM_PRE_ROOT99_SET_MUX_A_MASK) +#define CCM_PRE_ROOT99_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT99_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT99_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT99_SET_BUSY4_SHIFT 31 +/* PRE_ROOT99_CLR Bit Fields */ +#define CCM_PRE_ROOT99_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT99_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT99_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT99_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT99_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT99_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT99_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT99_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT99_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT99_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT99_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT99_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT99_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT99_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT99_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT99_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT99_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT99_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT99_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT99_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT99_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT99_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT99_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT99_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT99_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT99_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT99_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT99_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT99_TOG Bit Fields */ +#define CCM_PRE_ROOT99_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT99_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT99_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT99_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT99_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT99_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT99_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT99_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT99_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT99_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT99_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT99_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT99_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT99_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT99_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT99_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT99_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT99_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT99_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT99_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT99_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT99_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT99_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT99_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT99_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT99_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT99_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT99_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT99_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL99 Bit Fields */ +#define CCM_ACCESS_CTRL99_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL99_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL99_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL99_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL99_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL99_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL99_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL99_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL99_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL99_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL99_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL99_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL99_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL99_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL99_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL99_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL99_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL99_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL99_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL99_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL99_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL99_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL99_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL99_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL99_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL99_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL99_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL99_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL99_LOCK_SHIFT 31 +/* ACCESS_CTRL99_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL99_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL99_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL99_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL99_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL99_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL99_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL99_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL99_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL99_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL99_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL99_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL99_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL99_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL99_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL99_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL99_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL99_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL99_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT100 Bit Fields */ +#define CCM_TARGET_ROOT100_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT100_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT100_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_POST_PODF_MASK) +#define CCM_TARGET_ROOT100_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT100_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT100_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT100_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT100_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT100_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT100_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT100_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT100_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT100_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_PRE_PODF_MASK) +#define CCM_TARGET_ROOT100_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT100_MUX_SHIFT 24 +#define CCM_TARGET_ROOT100_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_MUX_SHIFT))&CCM_TARGET_ROOT100_MUX_MASK) +#define CCM_TARGET_ROOT100_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT100_ENABLE_SHIFT 28 +/* TARGET_ROOT100_SET Bit Fields */ +#define CCM_TARGET_ROOT100_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT100_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT100_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT100_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT100_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT100_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT100_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT100_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT100_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT100_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT100_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT100_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT100_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT100_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT100_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT100_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_SET_MUX_SHIFT))&CCM_TARGET_ROOT100_SET_MUX_MASK) +#define CCM_TARGET_ROOT100_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT100_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT100_CLR Bit Fields */ +#define CCM_TARGET_ROOT100_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT100_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT100_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT100_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT100_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT100_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT100_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT100_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT100_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT100_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT100_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT100_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT100_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_CLR_MUX_SHIFT))&CCM_TARGET_ROOT100_CLR_MUX_MASK) +#define CCM_TARGET_ROOT100_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT100_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT100_TOG Bit Fields */ +#define CCM_TARGET_ROOT100_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT100_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT100_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT100_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT100_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT100_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT100_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT100_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT100_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT100_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT100_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT100_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT100_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT100_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT100_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT100_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT100_TOG_MUX_SHIFT))&CCM_TARGET_ROOT100_TOG_MUX_MASK) +#define CCM_TARGET_ROOT100_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT100_TOG_ENABLE_SHIFT 28 +/* POST100 Bit Fields */ +#define CCM_POST100_POST_PODF_MASK 0x3Fu +#define CCM_POST100_POST_PODF_SHIFT 0 +#define CCM_POST100_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST100_POST_PODF_SHIFT))&CCM_POST100_POST_PODF_MASK) +#define CCM_POST100_BUSY1_MASK 0x80u +#define CCM_POST100_BUSY1_SHIFT 7 +#define CCM_POST100_AUTO_PODF_MASK 0x700u +#define CCM_POST100_AUTO_PODF_SHIFT 8 +#define CCM_POST100_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST100_AUTO_PODF_SHIFT))&CCM_POST100_AUTO_PODF_MASK) +#define CCM_POST100_AUTO_EN_MASK 0x1000u +#define CCM_POST100_AUTO_EN_SHIFT 12 +#define CCM_POST100_SLOW_MASK 0x8000u +#define CCM_POST100_SLOW_SHIFT 15 +#define CCM_POST100_SELECT_MASK 0x10000000u +#define CCM_POST100_SELECT_SHIFT 28 +#define CCM_POST100_BUSY2_MASK 0x80000000u +#define CCM_POST100_BUSY2_SHIFT 31 +/* POST_ROOT100_SET Bit Fields */ +#define CCM_POST_ROOT100_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT100_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT100_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_SET_POST_PODF_SHIFT))&CCM_POST_ROOT100_SET_POST_PODF_MASK) +#define CCM_POST_ROOT100_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT100_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT100_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT100_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT100_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT100_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT100_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT100_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT100_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT100_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT100_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT100_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT100_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT100_SET_BUSY2_SHIFT 31 +/* POST_ROOT100_CLR Bit Fields */ +#define CCM_POST_ROOT100_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT100_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT100_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT100_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT100_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT100_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT100_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT100_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT100_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT100_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT100_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT100_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT100_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT100_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT100_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT100_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT100_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT100_CLR_BUSY2_SHIFT 31 +/* POST_ROOT100_TOG Bit Fields */ +#define CCM_POST_ROOT100_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT100_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT100_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT100_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT100_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT100_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT100_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT100_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT100_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT100_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT100_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT100_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT100_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT100_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT100_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT100_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT100_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT100_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT100_TOG_BUSY2_SHIFT 31 +/* PRE100 Bit Fields */ +#define CCM_PRE100_PRE_PODF_B_MASK 0x7u +#define CCM_PRE100_PRE_PODF_B_SHIFT 0 +#define CCM_PRE100_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_PRE_PODF_B_SHIFT))&CCM_PRE100_PRE_PODF_B_MASK) +#define CCM_PRE100_BUSY0_MASK 0x8u +#define CCM_PRE100_BUSY0_SHIFT 3 +#define CCM_PRE100_MUX_B_MASK 0x700u +#define CCM_PRE100_MUX_B_SHIFT 8 +#define CCM_PRE100_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_MUX_B_SHIFT))&CCM_PRE100_MUX_B_MASK) +#define CCM_PRE100_EN_B_MASK 0x1000u +#define CCM_PRE100_EN_B_SHIFT 12 +#define CCM_PRE100_BUSY1_MASK 0x8000u +#define CCM_PRE100_BUSY1_SHIFT 15 +#define CCM_PRE100_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE100_PRE_PODF_A_SHIFT 16 +#define CCM_PRE100_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_PRE_PODF_A_SHIFT))&CCM_PRE100_PRE_PODF_A_MASK) +#define CCM_PRE100_BUSY3_MASK 0x80000u +#define CCM_PRE100_BUSY3_SHIFT 19 +#define CCM_PRE100_MUX_A_MASK 0x7000000u +#define CCM_PRE100_MUX_A_SHIFT 24 +#define CCM_PRE100_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE100_MUX_A_SHIFT))&CCM_PRE100_MUX_A_MASK) +#define CCM_PRE100_EN_A_MASK 0x10000000u +#define CCM_PRE100_EN_A_SHIFT 28 +#define CCM_PRE100_BUSY4_MASK 0x80000000u +#define CCM_PRE100_BUSY4_SHIFT 31 +/* PRE_ROOT100_SET Bit Fields */ +#define CCM_PRE_ROOT100_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT100_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT100_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT100_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT100_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT100_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT100_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT100_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT100_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_MUX_B_SHIFT))&CCM_PRE_ROOT100_SET_MUX_B_MASK) +#define CCM_PRE_ROOT100_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT100_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT100_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT100_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT100_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT100_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT100_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT100_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT100_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT100_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT100_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT100_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT100_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_SET_MUX_A_SHIFT))&CCM_PRE_ROOT100_SET_MUX_A_MASK) +#define CCM_PRE_ROOT100_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT100_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT100_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT100_SET_BUSY4_SHIFT 31 +/* PRE_ROOT100_CLR Bit Fields */ +#define CCM_PRE_ROOT100_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT100_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT100_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT100_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT100_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT100_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT100_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT100_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT100_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT100_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT100_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT100_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT100_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT100_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT100_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT100_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT100_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT100_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT100_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT100_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT100_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT100_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT100_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT100_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT100_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT100_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT100_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT100_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT100_TOG Bit Fields */ +#define CCM_PRE_ROOT100_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT100_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT100_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT100_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT100_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT100_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT100_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT100_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT100_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT100_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT100_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT100_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT100_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT100_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT100_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT100_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT100_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT100_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT100_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT100_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT100_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT100_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT100_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT100_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT100_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT100_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT100_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT100_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT100_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL100 Bit Fields */ +#define CCM_ACCESS_CTRL100_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL100_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL100_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL100_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL100_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL100_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL100_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL100_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL100_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL100_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL100_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL100_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL100_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL100_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL100_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL100_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL100_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL100_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL100_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL100_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL100_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL100_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL100_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL100_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL100_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL100_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL100_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL100_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL100_LOCK_SHIFT 31 +/* ACCESS_CTRL100_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL100_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL100_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL100_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL100_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL100_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL100_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL100_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL100_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL100_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL100_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL100_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL100_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL100_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL100_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL100_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL100_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL100_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL100_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT101 Bit Fields */ +#define CCM_TARGET_ROOT101_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT101_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT101_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_POST_PODF_MASK) +#define CCM_TARGET_ROOT101_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT101_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT101_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT101_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT101_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT101_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT101_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT101_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT101_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT101_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_PRE_PODF_MASK) +#define CCM_TARGET_ROOT101_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT101_MUX_SHIFT 24 +#define CCM_TARGET_ROOT101_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_MUX_SHIFT))&CCM_TARGET_ROOT101_MUX_MASK) +#define CCM_TARGET_ROOT101_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT101_ENABLE_SHIFT 28 +/* TARGET_ROOT101_SET Bit Fields */ +#define CCM_TARGET_ROOT101_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT101_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT101_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT101_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT101_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT101_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT101_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT101_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT101_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT101_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT101_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT101_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT101_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT101_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT101_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT101_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_SET_MUX_SHIFT))&CCM_TARGET_ROOT101_SET_MUX_MASK) +#define CCM_TARGET_ROOT101_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT101_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT101_CLR Bit Fields */ +#define CCM_TARGET_ROOT101_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT101_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT101_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT101_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT101_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT101_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT101_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT101_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT101_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT101_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT101_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT101_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT101_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_CLR_MUX_SHIFT))&CCM_TARGET_ROOT101_CLR_MUX_MASK) +#define CCM_TARGET_ROOT101_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT101_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT101_TOG Bit Fields */ +#define CCM_TARGET_ROOT101_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT101_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT101_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT101_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT101_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT101_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT101_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT101_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT101_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT101_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT101_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT101_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT101_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT101_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT101_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT101_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT101_TOG_MUX_SHIFT))&CCM_TARGET_ROOT101_TOG_MUX_MASK) +#define CCM_TARGET_ROOT101_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT101_TOG_ENABLE_SHIFT 28 +/* POST101 Bit Fields */ +#define CCM_POST101_POST_PODF_MASK 0x3Fu +#define CCM_POST101_POST_PODF_SHIFT 0 +#define CCM_POST101_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST101_POST_PODF_SHIFT))&CCM_POST101_POST_PODF_MASK) +#define CCM_POST101_BUSY1_MASK 0x80u +#define CCM_POST101_BUSY1_SHIFT 7 +#define CCM_POST101_AUTO_PODF_MASK 0x700u +#define CCM_POST101_AUTO_PODF_SHIFT 8 +#define CCM_POST101_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST101_AUTO_PODF_SHIFT))&CCM_POST101_AUTO_PODF_MASK) +#define CCM_POST101_AUTO_EN_MASK 0x1000u +#define CCM_POST101_AUTO_EN_SHIFT 12 +#define CCM_POST101_SLOW_MASK 0x8000u +#define CCM_POST101_SLOW_SHIFT 15 +#define CCM_POST101_SELECT_MASK 0x10000000u +#define CCM_POST101_SELECT_SHIFT 28 +#define CCM_POST101_BUSY2_MASK 0x80000000u +#define CCM_POST101_BUSY2_SHIFT 31 +/* POST_ROOT101_SET Bit Fields */ +#define CCM_POST_ROOT101_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT101_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT101_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_SET_POST_PODF_SHIFT))&CCM_POST_ROOT101_SET_POST_PODF_MASK) +#define CCM_POST_ROOT101_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT101_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT101_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT101_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT101_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT101_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT101_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT101_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT101_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT101_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT101_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT101_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT101_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT101_SET_BUSY2_SHIFT 31 +/* POST_ROOT101_CLR Bit Fields */ +#define CCM_POST_ROOT101_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT101_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT101_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT101_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT101_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT101_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT101_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT101_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT101_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT101_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT101_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT101_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT101_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT101_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT101_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT101_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT101_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT101_CLR_BUSY2_SHIFT 31 +/* POST_ROOT101_TOG Bit Fields */ +#define CCM_POST_ROOT101_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT101_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT101_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT101_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT101_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT101_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT101_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT101_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT101_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT101_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT101_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT101_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT101_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT101_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT101_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT101_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT101_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT101_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT101_TOG_BUSY2_SHIFT 31 +/* PRE101 Bit Fields */ +#define CCM_PRE101_PRE_PODF_B_MASK 0x7u +#define CCM_PRE101_PRE_PODF_B_SHIFT 0 +#define CCM_PRE101_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_PRE_PODF_B_SHIFT))&CCM_PRE101_PRE_PODF_B_MASK) +#define CCM_PRE101_BUSY0_MASK 0x8u +#define CCM_PRE101_BUSY0_SHIFT 3 +#define CCM_PRE101_MUX_B_MASK 0x700u +#define CCM_PRE101_MUX_B_SHIFT 8 +#define CCM_PRE101_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_MUX_B_SHIFT))&CCM_PRE101_MUX_B_MASK) +#define CCM_PRE101_EN_B_MASK 0x1000u +#define CCM_PRE101_EN_B_SHIFT 12 +#define CCM_PRE101_BUSY1_MASK 0x8000u +#define CCM_PRE101_BUSY1_SHIFT 15 +#define CCM_PRE101_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE101_PRE_PODF_A_SHIFT 16 +#define CCM_PRE101_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_PRE_PODF_A_SHIFT))&CCM_PRE101_PRE_PODF_A_MASK) +#define CCM_PRE101_BUSY3_MASK 0x80000u +#define CCM_PRE101_BUSY3_SHIFT 19 +#define CCM_PRE101_MUX_A_MASK 0x7000000u +#define CCM_PRE101_MUX_A_SHIFT 24 +#define CCM_PRE101_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE101_MUX_A_SHIFT))&CCM_PRE101_MUX_A_MASK) +#define CCM_PRE101_EN_A_MASK 0x10000000u +#define CCM_PRE101_EN_A_SHIFT 28 +#define CCM_PRE101_BUSY4_MASK 0x80000000u +#define CCM_PRE101_BUSY4_SHIFT 31 +/* PRE_ROOT101_SET Bit Fields */ +#define CCM_PRE_ROOT101_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT101_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT101_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT101_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT101_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT101_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT101_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT101_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT101_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_MUX_B_SHIFT))&CCM_PRE_ROOT101_SET_MUX_B_MASK) +#define CCM_PRE_ROOT101_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT101_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT101_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT101_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT101_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT101_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT101_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT101_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT101_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT101_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT101_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT101_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT101_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_SET_MUX_A_SHIFT))&CCM_PRE_ROOT101_SET_MUX_A_MASK) +#define CCM_PRE_ROOT101_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT101_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT101_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT101_SET_BUSY4_SHIFT 31 +/* PRE_ROOT101_CLR Bit Fields */ +#define CCM_PRE_ROOT101_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT101_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT101_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT101_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT101_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT101_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT101_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT101_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT101_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT101_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT101_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT101_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT101_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT101_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT101_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT101_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT101_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT101_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT101_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT101_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT101_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT101_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT101_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT101_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT101_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT101_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT101_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT101_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT101_TOG Bit Fields */ +#define CCM_PRE_ROOT101_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT101_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT101_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT101_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT101_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT101_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT101_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT101_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT101_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT101_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT101_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT101_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT101_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT101_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT101_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT101_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT101_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT101_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT101_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT101_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT101_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT101_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT101_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT101_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT101_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT101_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT101_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT101_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT101_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL101 Bit Fields */ +#define CCM_ACCESS_CTRL101_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL101_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL101_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL101_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL101_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL101_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL101_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL101_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL101_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL101_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL101_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL101_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL101_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL101_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL101_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL101_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL101_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL101_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL101_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL101_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL101_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL101_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL101_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL101_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL101_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL101_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL101_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL101_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL101_LOCK_SHIFT 31 +/* ACCESS_CTRL101_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL101_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL101_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL101_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL101_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL101_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL101_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL101_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL101_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL101_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL101_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL101_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL101_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL101_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL101_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL101_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL101_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL101_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL101_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT102 Bit Fields */ +#define CCM_TARGET_ROOT102_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT102_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT102_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_POST_PODF_MASK) +#define CCM_TARGET_ROOT102_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT102_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT102_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT102_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT102_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT102_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT102_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT102_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT102_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT102_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_PRE_PODF_MASK) +#define CCM_TARGET_ROOT102_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT102_MUX_SHIFT 24 +#define CCM_TARGET_ROOT102_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_MUX_SHIFT))&CCM_TARGET_ROOT102_MUX_MASK) +#define CCM_TARGET_ROOT102_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT102_ENABLE_SHIFT 28 +/* TARGET_ROOT102_SET Bit Fields */ +#define CCM_TARGET_ROOT102_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT102_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT102_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT102_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT102_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT102_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT102_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT102_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT102_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT102_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT102_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT102_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT102_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT102_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT102_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT102_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_SET_MUX_SHIFT))&CCM_TARGET_ROOT102_SET_MUX_MASK) +#define CCM_TARGET_ROOT102_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT102_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT102_CLR Bit Fields */ +#define CCM_TARGET_ROOT102_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT102_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT102_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT102_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT102_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT102_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT102_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT102_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT102_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT102_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT102_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT102_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT102_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_CLR_MUX_SHIFT))&CCM_TARGET_ROOT102_CLR_MUX_MASK) +#define CCM_TARGET_ROOT102_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT102_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT102_TOG Bit Fields */ +#define CCM_TARGET_ROOT102_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT102_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT102_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT102_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT102_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT102_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT102_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT102_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT102_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT102_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT102_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT102_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT102_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT102_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT102_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT102_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT102_TOG_MUX_SHIFT))&CCM_TARGET_ROOT102_TOG_MUX_MASK) +#define CCM_TARGET_ROOT102_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT102_TOG_ENABLE_SHIFT 28 +/* POST102 Bit Fields */ +#define CCM_POST102_POST_PODF_MASK 0x3Fu +#define CCM_POST102_POST_PODF_SHIFT 0 +#define CCM_POST102_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST102_POST_PODF_SHIFT))&CCM_POST102_POST_PODF_MASK) +#define CCM_POST102_BUSY1_MASK 0x80u +#define CCM_POST102_BUSY1_SHIFT 7 +#define CCM_POST102_AUTO_PODF_MASK 0x700u +#define CCM_POST102_AUTO_PODF_SHIFT 8 +#define CCM_POST102_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST102_AUTO_PODF_SHIFT))&CCM_POST102_AUTO_PODF_MASK) +#define CCM_POST102_AUTO_EN_MASK 0x1000u +#define CCM_POST102_AUTO_EN_SHIFT 12 +#define CCM_POST102_SLOW_MASK 0x8000u +#define CCM_POST102_SLOW_SHIFT 15 +#define CCM_POST102_SELECT_MASK 0x10000000u +#define CCM_POST102_SELECT_SHIFT 28 +#define CCM_POST102_BUSY2_MASK 0x80000000u +#define CCM_POST102_BUSY2_SHIFT 31 +/* POST_ROOT102_SET Bit Fields */ +#define CCM_POST_ROOT102_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT102_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT102_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_SET_POST_PODF_SHIFT))&CCM_POST_ROOT102_SET_POST_PODF_MASK) +#define CCM_POST_ROOT102_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT102_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT102_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT102_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT102_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT102_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT102_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT102_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT102_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT102_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT102_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT102_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT102_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT102_SET_BUSY2_SHIFT 31 +/* POST_ROOT102_CLR Bit Fields */ +#define CCM_POST_ROOT102_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT102_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT102_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT102_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT102_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT102_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT102_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT102_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT102_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT102_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT102_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT102_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT102_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT102_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT102_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT102_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT102_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT102_CLR_BUSY2_SHIFT 31 +/* POST_ROOT102_TOG Bit Fields */ +#define CCM_POST_ROOT102_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT102_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT102_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT102_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT102_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT102_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT102_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT102_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT102_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT102_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT102_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT102_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT102_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT102_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT102_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT102_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT102_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT102_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT102_TOG_BUSY2_SHIFT 31 +/* PRE102 Bit Fields */ +#define CCM_PRE102_PRE_PODF_B_MASK 0x7u +#define CCM_PRE102_PRE_PODF_B_SHIFT 0 +#define CCM_PRE102_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_PRE_PODF_B_SHIFT))&CCM_PRE102_PRE_PODF_B_MASK) +#define CCM_PRE102_BUSY0_MASK 0x8u +#define CCM_PRE102_BUSY0_SHIFT 3 +#define CCM_PRE102_MUX_B_MASK 0x700u +#define CCM_PRE102_MUX_B_SHIFT 8 +#define CCM_PRE102_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_MUX_B_SHIFT))&CCM_PRE102_MUX_B_MASK) +#define CCM_PRE102_EN_B_MASK 0x1000u +#define CCM_PRE102_EN_B_SHIFT 12 +#define CCM_PRE102_BUSY1_MASK 0x8000u +#define CCM_PRE102_BUSY1_SHIFT 15 +#define CCM_PRE102_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE102_PRE_PODF_A_SHIFT 16 +#define CCM_PRE102_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_PRE_PODF_A_SHIFT))&CCM_PRE102_PRE_PODF_A_MASK) +#define CCM_PRE102_BUSY3_MASK 0x80000u +#define CCM_PRE102_BUSY3_SHIFT 19 +#define CCM_PRE102_MUX_A_MASK 0x7000000u +#define CCM_PRE102_MUX_A_SHIFT 24 +#define CCM_PRE102_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE102_MUX_A_SHIFT))&CCM_PRE102_MUX_A_MASK) +#define CCM_PRE102_EN_A_MASK 0x10000000u +#define CCM_PRE102_EN_A_SHIFT 28 +#define CCM_PRE102_BUSY4_MASK 0x80000000u +#define CCM_PRE102_BUSY4_SHIFT 31 +/* PRE_ROOT102_SET Bit Fields */ +#define CCM_PRE_ROOT102_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT102_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT102_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT102_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT102_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT102_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT102_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT102_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT102_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_MUX_B_SHIFT))&CCM_PRE_ROOT102_SET_MUX_B_MASK) +#define CCM_PRE_ROOT102_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT102_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT102_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT102_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT102_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT102_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT102_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT102_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT102_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT102_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT102_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT102_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT102_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_SET_MUX_A_SHIFT))&CCM_PRE_ROOT102_SET_MUX_A_MASK) +#define CCM_PRE_ROOT102_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT102_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT102_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT102_SET_BUSY4_SHIFT 31 +/* PRE_ROOT102_CLR Bit Fields */ +#define CCM_PRE_ROOT102_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT102_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT102_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT102_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT102_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT102_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT102_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT102_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT102_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT102_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT102_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT102_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT102_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT102_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT102_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT102_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT102_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT102_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT102_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT102_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT102_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT102_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT102_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT102_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT102_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT102_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT102_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT102_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT102_TOG Bit Fields */ +#define CCM_PRE_ROOT102_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT102_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT102_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT102_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT102_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT102_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT102_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT102_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT102_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT102_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT102_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT102_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT102_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT102_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT102_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT102_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT102_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT102_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT102_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT102_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT102_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT102_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT102_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT102_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT102_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT102_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT102_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT102_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT102_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL102 Bit Fields */ +#define CCM_ACCESS_CTRL102_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL102_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL102_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL102_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL102_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL102_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL102_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL102_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL102_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL102_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL102_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL102_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL102_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL102_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL102_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL102_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL102_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL102_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL102_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL102_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL102_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL102_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL102_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL102_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL102_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL102_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL102_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL102_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL102_LOCK_SHIFT 31 +/* ACCESS_CTRL102_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL102_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL102_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL102_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL102_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL102_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL102_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL102_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL102_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL102_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL102_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL102_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL102_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL102_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL102_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL102_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL102_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL102_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL102_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT103 Bit Fields */ +#define CCM_TARGET_ROOT103_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT103_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT103_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_POST_PODF_MASK) +#define CCM_TARGET_ROOT103_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT103_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT103_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT103_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT103_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT103_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT103_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT103_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT103_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT103_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_PRE_PODF_MASK) +#define CCM_TARGET_ROOT103_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT103_MUX_SHIFT 24 +#define CCM_TARGET_ROOT103_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_MUX_SHIFT))&CCM_TARGET_ROOT103_MUX_MASK) +#define CCM_TARGET_ROOT103_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT103_ENABLE_SHIFT 28 +/* TARGET_ROOT103_SET Bit Fields */ +#define CCM_TARGET_ROOT103_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT103_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT103_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT103_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT103_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT103_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT103_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT103_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT103_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT103_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT103_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT103_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT103_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT103_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT103_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT103_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_SET_MUX_SHIFT))&CCM_TARGET_ROOT103_SET_MUX_MASK) +#define CCM_TARGET_ROOT103_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT103_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT103_CLR Bit Fields */ +#define CCM_TARGET_ROOT103_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT103_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT103_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT103_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT103_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT103_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT103_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT103_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT103_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT103_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT103_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT103_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT103_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_CLR_MUX_SHIFT))&CCM_TARGET_ROOT103_CLR_MUX_MASK) +#define CCM_TARGET_ROOT103_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT103_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT103_TOG Bit Fields */ +#define CCM_TARGET_ROOT103_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT103_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT103_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT103_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT103_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT103_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT103_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT103_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT103_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT103_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT103_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT103_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT103_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT103_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT103_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT103_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT103_TOG_MUX_SHIFT))&CCM_TARGET_ROOT103_TOG_MUX_MASK) +#define CCM_TARGET_ROOT103_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT103_TOG_ENABLE_SHIFT 28 +/* POST103 Bit Fields */ +#define CCM_POST103_POST_PODF_MASK 0x3Fu +#define CCM_POST103_POST_PODF_SHIFT 0 +#define CCM_POST103_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST103_POST_PODF_SHIFT))&CCM_POST103_POST_PODF_MASK) +#define CCM_POST103_BUSY1_MASK 0x80u +#define CCM_POST103_BUSY1_SHIFT 7 +#define CCM_POST103_AUTO_PODF_MASK 0x700u +#define CCM_POST103_AUTO_PODF_SHIFT 8 +#define CCM_POST103_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST103_AUTO_PODF_SHIFT))&CCM_POST103_AUTO_PODF_MASK) +#define CCM_POST103_AUTO_EN_MASK 0x1000u +#define CCM_POST103_AUTO_EN_SHIFT 12 +#define CCM_POST103_SLOW_MASK 0x8000u +#define CCM_POST103_SLOW_SHIFT 15 +#define CCM_POST103_SELECT_MASK 0x10000000u +#define CCM_POST103_SELECT_SHIFT 28 +#define CCM_POST103_BUSY2_MASK 0x80000000u +#define CCM_POST103_BUSY2_SHIFT 31 +/* POST_ROOT103_SET Bit Fields */ +#define CCM_POST_ROOT103_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT103_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT103_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_SET_POST_PODF_SHIFT))&CCM_POST_ROOT103_SET_POST_PODF_MASK) +#define CCM_POST_ROOT103_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT103_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT103_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT103_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT103_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT103_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT103_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT103_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT103_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT103_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT103_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT103_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT103_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT103_SET_BUSY2_SHIFT 31 +/* POST_ROOT103_CLR Bit Fields */ +#define CCM_POST_ROOT103_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT103_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT103_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT103_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT103_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT103_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT103_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT103_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT103_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT103_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT103_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT103_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT103_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT103_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT103_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT103_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT103_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT103_CLR_BUSY2_SHIFT 31 +/* POST_ROOT103_TOG Bit Fields */ +#define CCM_POST_ROOT103_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT103_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT103_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT103_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT103_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT103_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT103_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT103_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT103_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT103_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT103_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT103_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT103_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT103_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT103_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT103_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT103_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT103_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT103_TOG_BUSY2_SHIFT 31 +/* PRE103 Bit Fields */ +#define CCM_PRE103_PRE_PODF_B_MASK 0x7u +#define CCM_PRE103_PRE_PODF_B_SHIFT 0 +#define CCM_PRE103_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_PRE_PODF_B_SHIFT))&CCM_PRE103_PRE_PODF_B_MASK) +#define CCM_PRE103_BUSY0_MASK 0x8u +#define CCM_PRE103_BUSY0_SHIFT 3 +#define CCM_PRE103_MUX_B_MASK 0x700u +#define CCM_PRE103_MUX_B_SHIFT 8 +#define CCM_PRE103_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_MUX_B_SHIFT))&CCM_PRE103_MUX_B_MASK) +#define CCM_PRE103_EN_B_MASK 0x1000u +#define CCM_PRE103_EN_B_SHIFT 12 +#define CCM_PRE103_BUSY1_MASK 0x8000u +#define CCM_PRE103_BUSY1_SHIFT 15 +#define CCM_PRE103_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE103_PRE_PODF_A_SHIFT 16 +#define CCM_PRE103_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_PRE_PODF_A_SHIFT))&CCM_PRE103_PRE_PODF_A_MASK) +#define CCM_PRE103_BUSY3_MASK 0x80000u +#define CCM_PRE103_BUSY3_SHIFT 19 +#define CCM_PRE103_MUX_A_MASK 0x7000000u +#define CCM_PRE103_MUX_A_SHIFT 24 +#define CCM_PRE103_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE103_MUX_A_SHIFT))&CCM_PRE103_MUX_A_MASK) +#define CCM_PRE103_EN_A_MASK 0x10000000u +#define CCM_PRE103_EN_A_SHIFT 28 +#define CCM_PRE103_BUSY4_MASK 0x80000000u +#define CCM_PRE103_BUSY4_SHIFT 31 +/* PRE_ROOT103_SET Bit Fields */ +#define CCM_PRE_ROOT103_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT103_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT103_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT103_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT103_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT103_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT103_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT103_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT103_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_MUX_B_SHIFT))&CCM_PRE_ROOT103_SET_MUX_B_MASK) +#define CCM_PRE_ROOT103_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT103_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT103_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT103_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT103_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT103_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT103_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT103_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT103_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT103_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT103_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT103_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT103_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_SET_MUX_A_SHIFT))&CCM_PRE_ROOT103_SET_MUX_A_MASK) +#define CCM_PRE_ROOT103_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT103_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT103_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT103_SET_BUSY4_SHIFT 31 +/* PRE_ROOT103_CLR Bit Fields */ +#define CCM_PRE_ROOT103_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT103_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT103_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT103_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT103_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT103_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT103_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT103_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT103_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT103_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT103_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT103_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT103_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT103_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT103_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT103_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT103_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT103_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT103_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT103_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT103_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT103_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT103_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT103_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT103_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT103_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT103_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT103_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT103_TOG Bit Fields */ +#define CCM_PRE_ROOT103_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT103_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT103_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT103_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT103_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT103_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT103_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT103_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT103_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT103_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT103_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT103_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT103_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT103_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT103_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT103_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT103_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT103_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT103_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT103_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT103_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT103_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT103_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT103_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT103_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT103_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT103_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT103_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT103_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL103 Bit Fields */ +#define CCM_ACCESS_CTRL103_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL103_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL103_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL103_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL103_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL103_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL103_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL103_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL103_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL103_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL103_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL103_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL103_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL103_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL103_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL103_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL103_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL103_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL103_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL103_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL103_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL103_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL103_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL103_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL103_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL103_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL103_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL103_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL103_LOCK_SHIFT 31 +/* ACCESS_CTRL103_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL103_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL103_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL103_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL103_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL103_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL103_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL103_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL103_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL103_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL103_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL103_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL103_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL103_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL103_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL103_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL103_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL103_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL103_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT104 Bit Fields */ +#define CCM_TARGET_ROOT104_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT104_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT104_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_POST_PODF_MASK) +#define CCM_TARGET_ROOT104_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT104_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT104_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT104_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT104_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT104_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT104_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT104_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT104_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT104_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_PRE_PODF_MASK) +#define CCM_TARGET_ROOT104_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT104_MUX_SHIFT 24 +#define CCM_TARGET_ROOT104_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_MUX_SHIFT))&CCM_TARGET_ROOT104_MUX_MASK) +#define CCM_TARGET_ROOT104_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT104_ENABLE_SHIFT 28 +/* TARGET_ROOT104_SET Bit Fields */ +#define CCM_TARGET_ROOT104_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT104_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT104_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT104_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT104_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT104_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT104_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT104_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT104_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT104_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT104_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT104_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT104_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT104_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT104_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT104_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_SET_MUX_SHIFT))&CCM_TARGET_ROOT104_SET_MUX_MASK) +#define CCM_TARGET_ROOT104_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT104_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT104_CLR Bit Fields */ +#define CCM_TARGET_ROOT104_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT104_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT104_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT104_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT104_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT104_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT104_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT104_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT104_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT104_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT104_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT104_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT104_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_CLR_MUX_SHIFT))&CCM_TARGET_ROOT104_CLR_MUX_MASK) +#define CCM_TARGET_ROOT104_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT104_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT104_TOG Bit Fields */ +#define CCM_TARGET_ROOT104_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT104_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT104_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT104_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT104_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT104_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT104_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT104_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT104_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT104_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT104_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT104_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT104_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT104_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT104_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT104_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT104_TOG_MUX_SHIFT))&CCM_TARGET_ROOT104_TOG_MUX_MASK) +#define CCM_TARGET_ROOT104_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT104_TOG_ENABLE_SHIFT 28 +/* POST104 Bit Fields */ +#define CCM_POST104_POST_PODF_MASK 0x3Fu +#define CCM_POST104_POST_PODF_SHIFT 0 +#define CCM_POST104_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST104_POST_PODF_SHIFT))&CCM_POST104_POST_PODF_MASK) +#define CCM_POST104_BUSY1_MASK 0x80u +#define CCM_POST104_BUSY1_SHIFT 7 +#define CCM_POST104_AUTO_PODF_MASK 0x700u +#define CCM_POST104_AUTO_PODF_SHIFT 8 +#define CCM_POST104_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST104_AUTO_PODF_SHIFT))&CCM_POST104_AUTO_PODF_MASK) +#define CCM_POST104_AUTO_EN_MASK 0x1000u +#define CCM_POST104_AUTO_EN_SHIFT 12 +#define CCM_POST104_SLOW_MASK 0x8000u +#define CCM_POST104_SLOW_SHIFT 15 +#define CCM_POST104_SELECT_MASK 0x10000000u +#define CCM_POST104_SELECT_SHIFT 28 +#define CCM_POST104_BUSY2_MASK 0x80000000u +#define CCM_POST104_BUSY2_SHIFT 31 +/* POST_ROOT104_SET Bit Fields */ +#define CCM_POST_ROOT104_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT104_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT104_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_SET_POST_PODF_SHIFT))&CCM_POST_ROOT104_SET_POST_PODF_MASK) +#define CCM_POST_ROOT104_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT104_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT104_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT104_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT104_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT104_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT104_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT104_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT104_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT104_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT104_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT104_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT104_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT104_SET_BUSY2_SHIFT 31 +/* POST_ROOT104_CLR Bit Fields */ +#define CCM_POST_ROOT104_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT104_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT104_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT104_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT104_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT104_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT104_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT104_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT104_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT104_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT104_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT104_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT104_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT104_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT104_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT104_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT104_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT104_CLR_BUSY2_SHIFT 31 +/* POST_ROOT104_TOG Bit Fields */ +#define CCM_POST_ROOT104_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT104_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT104_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT104_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT104_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT104_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT104_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT104_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT104_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT104_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT104_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT104_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT104_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT104_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT104_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT104_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT104_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT104_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT104_TOG_BUSY2_SHIFT 31 +/* PRE104 Bit Fields */ +#define CCM_PRE104_PRE_PODF_B_MASK 0x7u +#define CCM_PRE104_PRE_PODF_B_SHIFT 0 +#define CCM_PRE104_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_PRE_PODF_B_SHIFT))&CCM_PRE104_PRE_PODF_B_MASK) +#define CCM_PRE104_BUSY0_MASK 0x8u +#define CCM_PRE104_BUSY0_SHIFT 3 +#define CCM_PRE104_MUX_B_MASK 0x700u +#define CCM_PRE104_MUX_B_SHIFT 8 +#define CCM_PRE104_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_MUX_B_SHIFT))&CCM_PRE104_MUX_B_MASK) +#define CCM_PRE104_EN_B_MASK 0x1000u +#define CCM_PRE104_EN_B_SHIFT 12 +#define CCM_PRE104_BUSY1_MASK 0x8000u +#define CCM_PRE104_BUSY1_SHIFT 15 +#define CCM_PRE104_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE104_PRE_PODF_A_SHIFT 16 +#define CCM_PRE104_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_PRE_PODF_A_SHIFT))&CCM_PRE104_PRE_PODF_A_MASK) +#define CCM_PRE104_BUSY3_MASK 0x80000u +#define CCM_PRE104_BUSY3_SHIFT 19 +#define CCM_PRE104_MUX_A_MASK 0x7000000u +#define CCM_PRE104_MUX_A_SHIFT 24 +#define CCM_PRE104_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE104_MUX_A_SHIFT))&CCM_PRE104_MUX_A_MASK) +#define CCM_PRE104_EN_A_MASK 0x10000000u +#define CCM_PRE104_EN_A_SHIFT 28 +#define CCM_PRE104_BUSY4_MASK 0x80000000u +#define CCM_PRE104_BUSY4_SHIFT 31 +/* PRE_ROOT104_SET Bit Fields */ +#define CCM_PRE_ROOT104_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT104_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT104_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT104_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT104_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT104_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT104_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT104_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT104_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_MUX_B_SHIFT))&CCM_PRE_ROOT104_SET_MUX_B_MASK) +#define CCM_PRE_ROOT104_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT104_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT104_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT104_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT104_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT104_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT104_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT104_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT104_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT104_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT104_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT104_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT104_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_SET_MUX_A_SHIFT))&CCM_PRE_ROOT104_SET_MUX_A_MASK) +#define CCM_PRE_ROOT104_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT104_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT104_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT104_SET_BUSY4_SHIFT 31 +/* PRE_ROOT104_CLR Bit Fields */ +#define CCM_PRE_ROOT104_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT104_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT104_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT104_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT104_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT104_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT104_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT104_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT104_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT104_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT104_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT104_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT104_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT104_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT104_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT104_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT104_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT104_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT104_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT104_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT104_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT104_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT104_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT104_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT104_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT104_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT104_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT104_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT104_TOG Bit Fields */ +#define CCM_PRE_ROOT104_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT104_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT104_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT104_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT104_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT104_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT104_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT104_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT104_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT104_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT104_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT104_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT104_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT104_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT104_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT104_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT104_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT104_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT104_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT104_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT104_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT104_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT104_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT104_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT104_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT104_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT104_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT104_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT104_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL104 Bit Fields */ +#define CCM_ACCESS_CTRL104_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL104_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL104_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL104_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL104_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL104_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL104_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL104_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL104_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL104_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL104_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL104_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL104_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL104_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL104_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL104_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL104_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL104_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL104_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL104_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL104_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL104_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL104_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL104_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL104_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL104_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL104_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL104_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL104_LOCK_SHIFT 31 +/* ACCESS_CTRL104_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL104_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL104_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL104_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL104_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL104_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL104_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL104_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL104_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL104_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL104_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL104_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL104_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL104_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL104_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL104_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL104_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL104_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL104_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT105 Bit Fields */ +#define CCM_TARGET_ROOT105_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT105_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT105_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_POST_PODF_MASK) +#define CCM_TARGET_ROOT105_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT105_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT105_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT105_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT105_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT105_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT105_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT105_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT105_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT105_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_PRE_PODF_MASK) +#define CCM_TARGET_ROOT105_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT105_MUX_SHIFT 24 +#define CCM_TARGET_ROOT105_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_MUX_SHIFT))&CCM_TARGET_ROOT105_MUX_MASK) +#define CCM_TARGET_ROOT105_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT105_ENABLE_SHIFT 28 +/* TARGET_ROOT105_SET Bit Fields */ +#define CCM_TARGET_ROOT105_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT105_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT105_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT105_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT105_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT105_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT105_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT105_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT105_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT105_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT105_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT105_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT105_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT105_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT105_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT105_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_SET_MUX_SHIFT))&CCM_TARGET_ROOT105_SET_MUX_MASK) +#define CCM_TARGET_ROOT105_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT105_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT105_CLR Bit Fields */ +#define CCM_TARGET_ROOT105_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT105_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT105_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT105_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT105_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT105_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT105_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT105_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT105_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT105_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT105_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT105_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT105_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_CLR_MUX_SHIFT))&CCM_TARGET_ROOT105_CLR_MUX_MASK) +#define CCM_TARGET_ROOT105_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT105_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT105_TOG Bit Fields */ +#define CCM_TARGET_ROOT105_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT105_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT105_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT105_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT105_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT105_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT105_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT105_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT105_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT105_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT105_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT105_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT105_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT105_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT105_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT105_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT105_TOG_MUX_SHIFT))&CCM_TARGET_ROOT105_TOG_MUX_MASK) +#define CCM_TARGET_ROOT105_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT105_TOG_ENABLE_SHIFT 28 +/* POST105 Bit Fields */ +#define CCM_POST105_POST_PODF_MASK 0x3Fu +#define CCM_POST105_POST_PODF_SHIFT 0 +#define CCM_POST105_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST105_POST_PODF_SHIFT))&CCM_POST105_POST_PODF_MASK) +#define CCM_POST105_BUSY1_MASK 0x80u +#define CCM_POST105_BUSY1_SHIFT 7 +#define CCM_POST105_AUTO_PODF_MASK 0x700u +#define CCM_POST105_AUTO_PODF_SHIFT 8 +#define CCM_POST105_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST105_AUTO_PODF_SHIFT))&CCM_POST105_AUTO_PODF_MASK) +#define CCM_POST105_AUTO_EN_MASK 0x1000u +#define CCM_POST105_AUTO_EN_SHIFT 12 +#define CCM_POST105_SLOW_MASK 0x8000u +#define CCM_POST105_SLOW_SHIFT 15 +#define CCM_POST105_SELECT_MASK 0x10000000u +#define CCM_POST105_SELECT_SHIFT 28 +#define CCM_POST105_BUSY2_MASK 0x80000000u +#define CCM_POST105_BUSY2_SHIFT 31 +/* POST_ROOT105_SET Bit Fields */ +#define CCM_POST_ROOT105_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT105_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT105_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_SET_POST_PODF_SHIFT))&CCM_POST_ROOT105_SET_POST_PODF_MASK) +#define CCM_POST_ROOT105_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT105_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT105_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT105_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT105_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT105_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT105_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT105_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT105_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT105_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT105_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT105_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT105_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT105_SET_BUSY2_SHIFT 31 +/* POST_ROOT105_CLR Bit Fields */ +#define CCM_POST_ROOT105_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT105_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT105_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT105_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT105_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT105_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT105_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT105_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT105_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT105_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT105_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT105_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT105_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT105_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT105_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT105_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT105_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT105_CLR_BUSY2_SHIFT 31 +/* POST_ROOT105_TOG Bit Fields */ +#define CCM_POST_ROOT105_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT105_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT105_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT105_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT105_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT105_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT105_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT105_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT105_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT105_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT105_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT105_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT105_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT105_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT105_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT105_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT105_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT105_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT105_TOG_BUSY2_SHIFT 31 +/* PRE105 Bit Fields */ +#define CCM_PRE105_PRE_PODF_B_MASK 0x7u +#define CCM_PRE105_PRE_PODF_B_SHIFT 0 +#define CCM_PRE105_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_PRE_PODF_B_SHIFT))&CCM_PRE105_PRE_PODF_B_MASK) +#define CCM_PRE105_BUSY0_MASK 0x8u +#define CCM_PRE105_BUSY0_SHIFT 3 +#define CCM_PRE105_MUX_B_MASK 0x700u +#define CCM_PRE105_MUX_B_SHIFT 8 +#define CCM_PRE105_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_MUX_B_SHIFT))&CCM_PRE105_MUX_B_MASK) +#define CCM_PRE105_EN_B_MASK 0x1000u +#define CCM_PRE105_EN_B_SHIFT 12 +#define CCM_PRE105_BUSY1_MASK 0x8000u +#define CCM_PRE105_BUSY1_SHIFT 15 +#define CCM_PRE105_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE105_PRE_PODF_A_SHIFT 16 +#define CCM_PRE105_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_PRE_PODF_A_SHIFT))&CCM_PRE105_PRE_PODF_A_MASK) +#define CCM_PRE105_BUSY3_MASK 0x80000u +#define CCM_PRE105_BUSY3_SHIFT 19 +#define CCM_PRE105_MUX_A_MASK 0x7000000u +#define CCM_PRE105_MUX_A_SHIFT 24 +#define CCM_PRE105_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE105_MUX_A_SHIFT))&CCM_PRE105_MUX_A_MASK) +#define CCM_PRE105_EN_A_MASK 0x10000000u +#define CCM_PRE105_EN_A_SHIFT 28 +#define CCM_PRE105_BUSY4_MASK 0x80000000u +#define CCM_PRE105_BUSY4_SHIFT 31 +/* PRE_ROOT105_SET Bit Fields */ +#define CCM_PRE_ROOT105_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT105_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT105_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT105_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT105_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT105_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT105_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT105_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT105_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_MUX_B_SHIFT))&CCM_PRE_ROOT105_SET_MUX_B_MASK) +#define CCM_PRE_ROOT105_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT105_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT105_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT105_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT105_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT105_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT105_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT105_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT105_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT105_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT105_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT105_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT105_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_SET_MUX_A_SHIFT))&CCM_PRE_ROOT105_SET_MUX_A_MASK) +#define CCM_PRE_ROOT105_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT105_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT105_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT105_SET_BUSY4_SHIFT 31 +/* PRE_ROOT105_CLR Bit Fields */ +#define CCM_PRE_ROOT105_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT105_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT105_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT105_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT105_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT105_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT105_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT105_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT105_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT105_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT105_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT105_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT105_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT105_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT105_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT105_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT105_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT105_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT105_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT105_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT105_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT105_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT105_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT105_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT105_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT105_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT105_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT105_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT105_TOG Bit Fields */ +#define CCM_PRE_ROOT105_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT105_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT105_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT105_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT105_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT105_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT105_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT105_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT105_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT105_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT105_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT105_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT105_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT105_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT105_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT105_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT105_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT105_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT105_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT105_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT105_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT105_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT105_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT105_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT105_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT105_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT105_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT105_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT105_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL105 Bit Fields */ +#define CCM_ACCESS_CTRL105_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL105_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL105_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL105_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL105_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL105_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL105_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL105_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL105_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL105_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL105_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL105_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL105_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL105_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL105_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL105_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL105_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL105_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL105_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL105_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL105_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL105_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL105_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL105_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL105_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL105_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL105_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL105_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL105_LOCK_SHIFT 31 +/* ACCESS_CTRL105_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL105_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL105_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL105_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL105_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL105_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL105_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL105_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL105_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL105_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL105_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL105_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL105_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL105_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL105_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL105_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL105_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL105_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL105_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT106 Bit Fields */ +#define CCM_TARGET_ROOT106_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT106_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT106_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_POST_PODF_MASK) +#define CCM_TARGET_ROOT106_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT106_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT106_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT106_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT106_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT106_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT106_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT106_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT106_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT106_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_PRE_PODF_MASK) +#define CCM_TARGET_ROOT106_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT106_MUX_SHIFT 24 +#define CCM_TARGET_ROOT106_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_MUX_SHIFT))&CCM_TARGET_ROOT106_MUX_MASK) +#define CCM_TARGET_ROOT106_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT106_ENABLE_SHIFT 28 +/* TARGET_ROOT106_SET Bit Fields */ +#define CCM_TARGET_ROOT106_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT106_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT106_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT106_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT106_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT106_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT106_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT106_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT106_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT106_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT106_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT106_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT106_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT106_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT106_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT106_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_SET_MUX_SHIFT))&CCM_TARGET_ROOT106_SET_MUX_MASK) +#define CCM_TARGET_ROOT106_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT106_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT106_CLR Bit Fields */ +#define CCM_TARGET_ROOT106_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT106_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT106_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT106_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT106_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT106_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT106_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT106_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT106_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT106_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT106_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT106_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT106_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_CLR_MUX_SHIFT))&CCM_TARGET_ROOT106_CLR_MUX_MASK) +#define CCM_TARGET_ROOT106_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT106_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT106_TOG Bit Fields */ +#define CCM_TARGET_ROOT106_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT106_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT106_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT106_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT106_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT106_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT106_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT106_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT106_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT106_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT106_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT106_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT106_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT106_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT106_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT106_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT106_TOG_MUX_SHIFT))&CCM_TARGET_ROOT106_TOG_MUX_MASK) +#define CCM_TARGET_ROOT106_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT106_TOG_ENABLE_SHIFT 28 +/* POST106 Bit Fields */ +#define CCM_POST106_POST_PODF_MASK 0x3Fu +#define CCM_POST106_POST_PODF_SHIFT 0 +#define CCM_POST106_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST106_POST_PODF_SHIFT))&CCM_POST106_POST_PODF_MASK) +#define CCM_POST106_BUSY1_MASK 0x80u +#define CCM_POST106_BUSY1_SHIFT 7 +#define CCM_POST106_AUTO_PODF_MASK 0x700u +#define CCM_POST106_AUTO_PODF_SHIFT 8 +#define CCM_POST106_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST106_AUTO_PODF_SHIFT))&CCM_POST106_AUTO_PODF_MASK) +#define CCM_POST106_AUTO_EN_MASK 0x1000u +#define CCM_POST106_AUTO_EN_SHIFT 12 +#define CCM_POST106_SLOW_MASK 0x8000u +#define CCM_POST106_SLOW_SHIFT 15 +#define CCM_POST106_SELECT_MASK 0x10000000u +#define CCM_POST106_SELECT_SHIFT 28 +#define CCM_POST106_BUSY2_MASK 0x80000000u +#define CCM_POST106_BUSY2_SHIFT 31 +/* POST_ROOT106_SET Bit Fields */ +#define CCM_POST_ROOT106_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT106_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT106_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_SET_POST_PODF_SHIFT))&CCM_POST_ROOT106_SET_POST_PODF_MASK) +#define CCM_POST_ROOT106_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT106_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT106_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT106_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT106_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT106_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT106_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT106_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT106_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT106_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT106_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT106_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT106_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT106_SET_BUSY2_SHIFT 31 +/* POST_ROOT106_CLR Bit Fields */ +#define CCM_POST_ROOT106_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT106_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT106_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT106_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT106_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT106_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT106_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT106_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT106_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT106_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT106_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT106_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT106_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT106_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT106_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT106_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT106_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT106_CLR_BUSY2_SHIFT 31 +/* POST_ROOT106_TOG Bit Fields */ +#define CCM_POST_ROOT106_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT106_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT106_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT106_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT106_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT106_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT106_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT106_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT106_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT106_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT106_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT106_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT106_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT106_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT106_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT106_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT106_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT106_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT106_TOG_BUSY2_SHIFT 31 +/* PRE106 Bit Fields */ +#define CCM_PRE106_PRE_PODF_B_MASK 0x7u +#define CCM_PRE106_PRE_PODF_B_SHIFT 0 +#define CCM_PRE106_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_PRE_PODF_B_SHIFT))&CCM_PRE106_PRE_PODF_B_MASK) +#define CCM_PRE106_BUSY0_MASK 0x8u +#define CCM_PRE106_BUSY0_SHIFT 3 +#define CCM_PRE106_MUX_B_MASK 0x700u +#define CCM_PRE106_MUX_B_SHIFT 8 +#define CCM_PRE106_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_MUX_B_SHIFT))&CCM_PRE106_MUX_B_MASK) +#define CCM_PRE106_EN_B_MASK 0x1000u +#define CCM_PRE106_EN_B_SHIFT 12 +#define CCM_PRE106_BUSY1_MASK 0x8000u +#define CCM_PRE106_BUSY1_SHIFT 15 +#define CCM_PRE106_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE106_PRE_PODF_A_SHIFT 16 +#define CCM_PRE106_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_PRE_PODF_A_SHIFT))&CCM_PRE106_PRE_PODF_A_MASK) +#define CCM_PRE106_BUSY3_MASK 0x80000u +#define CCM_PRE106_BUSY3_SHIFT 19 +#define CCM_PRE106_MUX_A_MASK 0x7000000u +#define CCM_PRE106_MUX_A_SHIFT 24 +#define CCM_PRE106_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE106_MUX_A_SHIFT))&CCM_PRE106_MUX_A_MASK) +#define CCM_PRE106_EN_A_MASK 0x10000000u +#define CCM_PRE106_EN_A_SHIFT 28 +#define CCM_PRE106_BUSY4_MASK 0x80000000u +#define CCM_PRE106_BUSY4_SHIFT 31 +/* PRE_ROOT106_SET Bit Fields */ +#define CCM_PRE_ROOT106_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT106_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT106_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT106_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT106_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT106_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT106_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT106_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT106_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_MUX_B_SHIFT))&CCM_PRE_ROOT106_SET_MUX_B_MASK) +#define CCM_PRE_ROOT106_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT106_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT106_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT106_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT106_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT106_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT106_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT106_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT106_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT106_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT106_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT106_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT106_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_SET_MUX_A_SHIFT))&CCM_PRE_ROOT106_SET_MUX_A_MASK) +#define CCM_PRE_ROOT106_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT106_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT106_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT106_SET_BUSY4_SHIFT 31 +/* PRE_ROOT106_CLR Bit Fields */ +#define CCM_PRE_ROOT106_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT106_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT106_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT106_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT106_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT106_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT106_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT106_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT106_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT106_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT106_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT106_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT106_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT106_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT106_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT106_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT106_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT106_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT106_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT106_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT106_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT106_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT106_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT106_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT106_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT106_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT106_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT106_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT106_TOG Bit Fields */ +#define CCM_PRE_ROOT106_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT106_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT106_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT106_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT106_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT106_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT106_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT106_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT106_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT106_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT106_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT106_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT106_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT106_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT106_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT106_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT106_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT106_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT106_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT106_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT106_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT106_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT106_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT106_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT106_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT106_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT106_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT106_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT106_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL106 Bit Fields */ +#define CCM_ACCESS_CTRL106_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL106_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL106_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL106_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL106_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL106_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL106_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL106_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL106_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL106_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL106_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL106_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL106_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL106_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL106_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL106_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL106_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL106_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL106_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL106_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL106_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL106_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL106_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL106_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL106_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL106_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL106_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL106_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL106_LOCK_SHIFT 31 +/* ACCESS_CTRL106_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL106_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL106_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL106_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL106_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL106_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL106_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL106_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL106_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL106_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL106_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL106_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL106_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL106_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL106_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL106_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL106_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL106_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL106_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT107 Bit Fields */ +#define CCM_TARGET_ROOT107_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT107_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT107_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_POST_PODF_MASK) +#define CCM_TARGET_ROOT107_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT107_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT107_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT107_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT107_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT107_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT107_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT107_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT107_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT107_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_PRE_PODF_MASK) +#define CCM_TARGET_ROOT107_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT107_MUX_SHIFT 24 +#define CCM_TARGET_ROOT107_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_MUX_SHIFT))&CCM_TARGET_ROOT107_MUX_MASK) +#define CCM_TARGET_ROOT107_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT107_ENABLE_SHIFT 28 +/* TARGET_ROOT107_SET Bit Fields */ +#define CCM_TARGET_ROOT107_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT107_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT107_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT107_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT107_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT107_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT107_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT107_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT107_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT107_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT107_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT107_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT107_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT107_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT107_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT107_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_SET_MUX_SHIFT))&CCM_TARGET_ROOT107_SET_MUX_MASK) +#define CCM_TARGET_ROOT107_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT107_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT107_CLR Bit Fields */ +#define CCM_TARGET_ROOT107_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT107_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT107_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT107_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT107_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT107_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT107_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT107_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT107_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT107_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT107_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT107_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT107_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_CLR_MUX_SHIFT))&CCM_TARGET_ROOT107_CLR_MUX_MASK) +#define CCM_TARGET_ROOT107_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT107_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT107_TOG Bit Fields */ +#define CCM_TARGET_ROOT107_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT107_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT107_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT107_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT107_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT107_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT107_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT107_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT107_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT107_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT107_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT107_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT107_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT107_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT107_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT107_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT107_TOG_MUX_SHIFT))&CCM_TARGET_ROOT107_TOG_MUX_MASK) +#define CCM_TARGET_ROOT107_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT107_TOG_ENABLE_SHIFT 28 +/* POST107 Bit Fields */ +#define CCM_POST107_POST_PODF_MASK 0x3Fu +#define CCM_POST107_POST_PODF_SHIFT 0 +#define CCM_POST107_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST107_POST_PODF_SHIFT))&CCM_POST107_POST_PODF_MASK) +#define CCM_POST107_BUSY1_MASK 0x80u +#define CCM_POST107_BUSY1_SHIFT 7 +#define CCM_POST107_AUTO_PODF_MASK 0x700u +#define CCM_POST107_AUTO_PODF_SHIFT 8 +#define CCM_POST107_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST107_AUTO_PODF_SHIFT))&CCM_POST107_AUTO_PODF_MASK) +#define CCM_POST107_AUTO_EN_MASK 0x1000u +#define CCM_POST107_AUTO_EN_SHIFT 12 +#define CCM_POST107_SLOW_MASK 0x8000u +#define CCM_POST107_SLOW_SHIFT 15 +#define CCM_POST107_SELECT_MASK 0x10000000u +#define CCM_POST107_SELECT_SHIFT 28 +#define CCM_POST107_BUSY2_MASK 0x80000000u +#define CCM_POST107_BUSY2_SHIFT 31 +/* POST_ROOT107_SET Bit Fields */ +#define CCM_POST_ROOT107_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT107_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT107_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_SET_POST_PODF_SHIFT))&CCM_POST_ROOT107_SET_POST_PODF_MASK) +#define CCM_POST_ROOT107_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT107_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT107_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT107_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT107_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT107_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT107_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT107_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT107_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT107_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT107_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT107_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT107_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT107_SET_BUSY2_SHIFT 31 +/* POST_ROOT107_CLR Bit Fields */ +#define CCM_POST_ROOT107_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT107_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT107_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT107_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT107_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT107_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT107_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT107_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT107_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT107_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT107_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT107_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT107_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT107_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT107_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT107_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT107_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT107_CLR_BUSY2_SHIFT 31 +/* POST_ROOT107_TOG Bit Fields */ +#define CCM_POST_ROOT107_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT107_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT107_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT107_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT107_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT107_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT107_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT107_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT107_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT107_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT107_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT107_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT107_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT107_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT107_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT107_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT107_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT107_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT107_TOG_BUSY2_SHIFT 31 +/* PRE107 Bit Fields */ +#define CCM_PRE107_PRE_PODF_B_MASK 0x7u +#define CCM_PRE107_PRE_PODF_B_SHIFT 0 +#define CCM_PRE107_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_PRE_PODF_B_SHIFT))&CCM_PRE107_PRE_PODF_B_MASK) +#define CCM_PRE107_BUSY0_MASK 0x8u +#define CCM_PRE107_BUSY0_SHIFT 3 +#define CCM_PRE107_MUX_B_MASK 0x700u +#define CCM_PRE107_MUX_B_SHIFT 8 +#define CCM_PRE107_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_MUX_B_SHIFT))&CCM_PRE107_MUX_B_MASK) +#define CCM_PRE107_EN_B_MASK 0x1000u +#define CCM_PRE107_EN_B_SHIFT 12 +#define CCM_PRE107_BUSY1_MASK 0x8000u +#define CCM_PRE107_BUSY1_SHIFT 15 +#define CCM_PRE107_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE107_PRE_PODF_A_SHIFT 16 +#define CCM_PRE107_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_PRE_PODF_A_SHIFT))&CCM_PRE107_PRE_PODF_A_MASK) +#define CCM_PRE107_BUSY3_MASK 0x80000u +#define CCM_PRE107_BUSY3_SHIFT 19 +#define CCM_PRE107_MUX_A_MASK 0x7000000u +#define CCM_PRE107_MUX_A_SHIFT 24 +#define CCM_PRE107_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE107_MUX_A_SHIFT))&CCM_PRE107_MUX_A_MASK) +#define CCM_PRE107_EN_A_MASK 0x10000000u +#define CCM_PRE107_EN_A_SHIFT 28 +#define CCM_PRE107_BUSY4_MASK 0x80000000u +#define CCM_PRE107_BUSY4_SHIFT 31 +/* PRE_ROOT107_SET Bit Fields */ +#define CCM_PRE_ROOT107_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT107_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT107_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT107_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT107_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT107_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT107_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT107_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT107_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_MUX_B_SHIFT))&CCM_PRE_ROOT107_SET_MUX_B_MASK) +#define CCM_PRE_ROOT107_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT107_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT107_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT107_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT107_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT107_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT107_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT107_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT107_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT107_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT107_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT107_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT107_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_SET_MUX_A_SHIFT))&CCM_PRE_ROOT107_SET_MUX_A_MASK) +#define CCM_PRE_ROOT107_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT107_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT107_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT107_SET_BUSY4_SHIFT 31 +/* PRE_ROOT107_CLR Bit Fields */ +#define CCM_PRE_ROOT107_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT107_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT107_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT107_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT107_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT107_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT107_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT107_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT107_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT107_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT107_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT107_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT107_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT107_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT107_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT107_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT107_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT107_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT107_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT107_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT107_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT107_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT107_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT107_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT107_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT107_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT107_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT107_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT107_TOG Bit Fields */ +#define CCM_PRE_ROOT107_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT107_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT107_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT107_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT107_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT107_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT107_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT107_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT107_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT107_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT107_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT107_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT107_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT107_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT107_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT107_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT107_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT107_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT107_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT107_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT107_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT107_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT107_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT107_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT107_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT107_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT107_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT107_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT107_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL107 Bit Fields */ +#define CCM_ACCESS_CTRL107_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL107_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL107_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL107_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL107_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL107_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL107_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL107_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL107_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL107_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL107_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL107_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL107_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL107_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL107_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL107_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL107_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL107_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL107_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL107_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL107_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL107_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL107_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL107_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL107_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL107_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL107_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL107_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL107_LOCK_SHIFT 31 +/* ACCESS_CTRL107_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL107_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL107_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL107_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL107_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL107_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL107_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL107_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL107_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL107_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL107_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL107_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL107_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL107_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL107_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL107_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL107_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL107_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL107_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT108 Bit Fields */ +#define CCM_TARGET_ROOT108_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT108_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT108_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_POST_PODF_MASK) +#define CCM_TARGET_ROOT108_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT108_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT108_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT108_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT108_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT108_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT108_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT108_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT108_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT108_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_PRE_PODF_MASK) +#define CCM_TARGET_ROOT108_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT108_MUX_SHIFT 24 +#define CCM_TARGET_ROOT108_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_MUX_SHIFT))&CCM_TARGET_ROOT108_MUX_MASK) +#define CCM_TARGET_ROOT108_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT108_ENABLE_SHIFT 28 +/* TARGET_ROOT108_SET Bit Fields */ +#define CCM_TARGET_ROOT108_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT108_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT108_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT108_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT108_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT108_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT108_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT108_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT108_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT108_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT108_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT108_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT108_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT108_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT108_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT108_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_SET_MUX_SHIFT))&CCM_TARGET_ROOT108_SET_MUX_MASK) +#define CCM_TARGET_ROOT108_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT108_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT108_CLR Bit Fields */ +#define CCM_TARGET_ROOT108_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT108_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT108_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT108_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT108_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT108_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT108_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT108_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT108_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT108_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT108_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT108_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT108_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_CLR_MUX_SHIFT))&CCM_TARGET_ROOT108_CLR_MUX_MASK) +#define CCM_TARGET_ROOT108_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT108_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT108_TOG Bit Fields */ +#define CCM_TARGET_ROOT108_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT108_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT108_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT108_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT108_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT108_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT108_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT108_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT108_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT108_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT108_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT108_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT108_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT108_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT108_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT108_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT108_TOG_MUX_SHIFT))&CCM_TARGET_ROOT108_TOG_MUX_MASK) +#define CCM_TARGET_ROOT108_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT108_TOG_ENABLE_SHIFT 28 +/* POST108 Bit Fields */ +#define CCM_POST108_POST_PODF_MASK 0x3Fu +#define CCM_POST108_POST_PODF_SHIFT 0 +#define CCM_POST108_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST108_POST_PODF_SHIFT))&CCM_POST108_POST_PODF_MASK) +#define CCM_POST108_BUSY1_MASK 0x80u +#define CCM_POST108_BUSY1_SHIFT 7 +#define CCM_POST108_AUTO_PODF_MASK 0x700u +#define CCM_POST108_AUTO_PODF_SHIFT 8 +#define CCM_POST108_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST108_AUTO_PODF_SHIFT))&CCM_POST108_AUTO_PODF_MASK) +#define CCM_POST108_AUTO_EN_MASK 0x1000u +#define CCM_POST108_AUTO_EN_SHIFT 12 +#define CCM_POST108_SLOW_MASK 0x8000u +#define CCM_POST108_SLOW_SHIFT 15 +#define CCM_POST108_SELECT_MASK 0x10000000u +#define CCM_POST108_SELECT_SHIFT 28 +#define CCM_POST108_BUSY2_MASK 0x80000000u +#define CCM_POST108_BUSY2_SHIFT 31 +/* POST_ROOT108_SET Bit Fields */ +#define CCM_POST_ROOT108_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT108_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT108_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_SET_POST_PODF_SHIFT))&CCM_POST_ROOT108_SET_POST_PODF_MASK) +#define CCM_POST_ROOT108_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT108_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT108_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT108_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT108_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT108_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT108_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT108_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT108_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT108_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT108_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT108_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT108_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT108_SET_BUSY2_SHIFT 31 +/* POST_ROOT108_CLR Bit Fields */ +#define CCM_POST_ROOT108_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT108_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT108_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT108_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT108_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT108_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT108_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT108_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT108_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT108_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT108_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT108_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT108_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT108_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT108_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT108_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT108_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT108_CLR_BUSY2_SHIFT 31 +/* POST_ROOT108_TOG Bit Fields */ +#define CCM_POST_ROOT108_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT108_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT108_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT108_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT108_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT108_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT108_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT108_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT108_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT108_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT108_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT108_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT108_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT108_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT108_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT108_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT108_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT108_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT108_TOG_BUSY2_SHIFT 31 +/* PRE108 Bit Fields */ +#define CCM_PRE108_PRE_PODF_B_MASK 0x7u +#define CCM_PRE108_PRE_PODF_B_SHIFT 0 +#define CCM_PRE108_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_PRE_PODF_B_SHIFT))&CCM_PRE108_PRE_PODF_B_MASK) +#define CCM_PRE108_BUSY0_MASK 0x8u +#define CCM_PRE108_BUSY0_SHIFT 3 +#define CCM_PRE108_MUX_B_MASK 0x700u +#define CCM_PRE108_MUX_B_SHIFT 8 +#define CCM_PRE108_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_MUX_B_SHIFT))&CCM_PRE108_MUX_B_MASK) +#define CCM_PRE108_EN_B_MASK 0x1000u +#define CCM_PRE108_EN_B_SHIFT 12 +#define CCM_PRE108_BUSY1_MASK 0x8000u +#define CCM_PRE108_BUSY1_SHIFT 15 +#define CCM_PRE108_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE108_PRE_PODF_A_SHIFT 16 +#define CCM_PRE108_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_PRE_PODF_A_SHIFT))&CCM_PRE108_PRE_PODF_A_MASK) +#define CCM_PRE108_BUSY3_MASK 0x80000u +#define CCM_PRE108_BUSY3_SHIFT 19 +#define CCM_PRE108_MUX_A_MASK 0x7000000u +#define CCM_PRE108_MUX_A_SHIFT 24 +#define CCM_PRE108_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE108_MUX_A_SHIFT))&CCM_PRE108_MUX_A_MASK) +#define CCM_PRE108_EN_A_MASK 0x10000000u +#define CCM_PRE108_EN_A_SHIFT 28 +#define CCM_PRE108_BUSY4_MASK 0x80000000u +#define CCM_PRE108_BUSY4_SHIFT 31 +/* PRE_ROOT108_SET Bit Fields */ +#define CCM_PRE_ROOT108_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT108_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT108_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT108_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT108_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT108_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT108_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT108_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT108_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_MUX_B_SHIFT))&CCM_PRE_ROOT108_SET_MUX_B_MASK) +#define CCM_PRE_ROOT108_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT108_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT108_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT108_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT108_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT108_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT108_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT108_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT108_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT108_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT108_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT108_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT108_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_SET_MUX_A_SHIFT))&CCM_PRE_ROOT108_SET_MUX_A_MASK) +#define CCM_PRE_ROOT108_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT108_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT108_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT108_SET_BUSY4_SHIFT 31 +/* PRE_ROOT108_CLR Bit Fields */ +#define CCM_PRE_ROOT108_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT108_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT108_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT108_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT108_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT108_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT108_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT108_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT108_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT108_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT108_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT108_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT108_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT108_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT108_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT108_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT108_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT108_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT108_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT108_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT108_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT108_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT108_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT108_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT108_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT108_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT108_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT108_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT108_TOG Bit Fields */ +#define CCM_PRE_ROOT108_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT108_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT108_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT108_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT108_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT108_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT108_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT108_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT108_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT108_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT108_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT108_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT108_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT108_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT108_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT108_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT108_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT108_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT108_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT108_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT108_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT108_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT108_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT108_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT108_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT108_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT108_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT108_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT108_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL108 Bit Fields */ +#define CCM_ACCESS_CTRL108_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL108_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL108_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL108_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL108_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL108_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL108_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL108_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL108_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL108_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL108_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL108_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL108_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL108_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL108_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL108_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL108_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL108_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL108_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL108_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL108_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL108_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL108_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL108_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL108_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL108_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL108_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL108_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL108_LOCK_SHIFT 31 +/* ACCESS_CTRL108_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL108_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL108_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL108_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL108_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL108_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL108_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL108_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL108_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL108_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL108_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL108_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL108_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL108_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL108_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL108_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL108_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL108_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL108_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT109 Bit Fields */ +#define CCM_TARGET_ROOT109_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT109_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT109_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_POST_PODF_MASK) +#define CCM_TARGET_ROOT109_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT109_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT109_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT109_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT109_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT109_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT109_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT109_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT109_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT109_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_PRE_PODF_MASK) +#define CCM_TARGET_ROOT109_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT109_MUX_SHIFT 24 +#define CCM_TARGET_ROOT109_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_MUX_SHIFT))&CCM_TARGET_ROOT109_MUX_MASK) +#define CCM_TARGET_ROOT109_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT109_ENABLE_SHIFT 28 +/* TARGET_ROOT109_SET Bit Fields */ +#define CCM_TARGET_ROOT109_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT109_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT109_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT109_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT109_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT109_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT109_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT109_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT109_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT109_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT109_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT109_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT109_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT109_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT109_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT109_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_SET_MUX_SHIFT))&CCM_TARGET_ROOT109_SET_MUX_MASK) +#define CCM_TARGET_ROOT109_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT109_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT109_CLR Bit Fields */ +#define CCM_TARGET_ROOT109_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT109_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT109_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT109_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT109_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT109_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT109_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT109_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT109_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT109_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT109_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT109_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT109_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_CLR_MUX_SHIFT))&CCM_TARGET_ROOT109_CLR_MUX_MASK) +#define CCM_TARGET_ROOT109_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT109_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT109_TOG Bit Fields */ +#define CCM_TARGET_ROOT109_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT109_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT109_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT109_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT109_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT109_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT109_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT109_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT109_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT109_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT109_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT109_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT109_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT109_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT109_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT109_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT109_TOG_MUX_SHIFT))&CCM_TARGET_ROOT109_TOG_MUX_MASK) +#define CCM_TARGET_ROOT109_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT109_TOG_ENABLE_SHIFT 28 +/* POST109 Bit Fields */ +#define CCM_POST109_POST_PODF_MASK 0x3Fu +#define CCM_POST109_POST_PODF_SHIFT 0 +#define CCM_POST109_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST109_POST_PODF_SHIFT))&CCM_POST109_POST_PODF_MASK) +#define CCM_POST109_BUSY1_MASK 0x80u +#define CCM_POST109_BUSY1_SHIFT 7 +#define CCM_POST109_AUTO_PODF_MASK 0x700u +#define CCM_POST109_AUTO_PODF_SHIFT 8 +#define CCM_POST109_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST109_AUTO_PODF_SHIFT))&CCM_POST109_AUTO_PODF_MASK) +#define CCM_POST109_AUTO_EN_MASK 0x1000u +#define CCM_POST109_AUTO_EN_SHIFT 12 +#define CCM_POST109_SLOW_MASK 0x8000u +#define CCM_POST109_SLOW_SHIFT 15 +#define CCM_POST109_SELECT_MASK 0x10000000u +#define CCM_POST109_SELECT_SHIFT 28 +#define CCM_POST109_BUSY2_MASK 0x80000000u +#define CCM_POST109_BUSY2_SHIFT 31 +/* POST_ROOT109_SET Bit Fields */ +#define CCM_POST_ROOT109_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT109_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT109_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_SET_POST_PODF_SHIFT))&CCM_POST_ROOT109_SET_POST_PODF_MASK) +#define CCM_POST_ROOT109_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT109_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT109_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT109_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT109_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT109_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT109_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT109_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT109_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT109_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT109_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT109_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT109_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT109_SET_BUSY2_SHIFT 31 +/* POST_ROOT109_CLR Bit Fields */ +#define CCM_POST_ROOT109_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT109_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT109_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT109_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT109_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT109_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT109_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT109_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT109_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT109_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT109_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT109_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT109_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT109_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT109_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT109_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT109_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT109_CLR_BUSY2_SHIFT 31 +/* POST_ROOT109_TOG Bit Fields */ +#define CCM_POST_ROOT109_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT109_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT109_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT109_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT109_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT109_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT109_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT109_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT109_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT109_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT109_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT109_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT109_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT109_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT109_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT109_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT109_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT109_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT109_TOG_BUSY2_SHIFT 31 +/* PRE109 Bit Fields */ +#define CCM_PRE109_PRE_PODF_B_MASK 0x7u +#define CCM_PRE109_PRE_PODF_B_SHIFT 0 +#define CCM_PRE109_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_PRE_PODF_B_SHIFT))&CCM_PRE109_PRE_PODF_B_MASK) +#define CCM_PRE109_BUSY0_MASK 0x8u +#define CCM_PRE109_BUSY0_SHIFT 3 +#define CCM_PRE109_MUX_B_MASK 0x700u +#define CCM_PRE109_MUX_B_SHIFT 8 +#define CCM_PRE109_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_MUX_B_SHIFT))&CCM_PRE109_MUX_B_MASK) +#define CCM_PRE109_EN_B_MASK 0x1000u +#define CCM_PRE109_EN_B_SHIFT 12 +#define CCM_PRE109_BUSY1_MASK 0x8000u +#define CCM_PRE109_BUSY1_SHIFT 15 +#define CCM_PRE109_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE109_PRE_PODF_A_SHIFT 16 +#define CCM_PRE109_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_PRE_PODF_A_SHIFT))&CCM_PRE109_PRE_PODF_A_MASK) +#define CCM_PRE109_BUSY3_MASK 0x80000u +#define CCM_PRE109_BUSY3_SHIFT 19 +#define CCM_PRE109_MUX_A_MASK 0x7000000u +#define CCM_PRE109_MUX_A_SHIFT 24 +#define CCM_PRE109_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE109_MUX_A_SHIFT))&CCM_PRE109_MUX_A_MASK) +#define CCM_PRE109_EN_A_MASK 0x10000000u +#define CCM_PRE109_EN_A_SHIFT 28 +#define CCM_PRE109_BUSY4_MASK 0x80000000u +#define CCM_PRE109_BUSY4_SHIFT 31 +/* PRE_ROOT109_SET Bit Fields */ +#define CCM_PRE_ROOT109_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT109_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT109_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT109_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT109_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT109_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT109_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT109_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT109_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_MUX_B_SHIFT))&CCM_PRE_ROOT109_SET_MUX_B_MASK) +#define CCM_PRE_ROOT109_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT109_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT109_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT109_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT109_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT109_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT109_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT109_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT109_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT109_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT109_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT109_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT109_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_SET_MUX_A_SHIFT))&CCM_PRE_ROOT109_SET_MUX_A_MASK) +#define CCM_PRE_ROOT109_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT109_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT109_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT109_SET_BUSY4_SHIFT 31 +/* PRE_ROOT109_CLR Bit Fields */ +#define CCM_PRE_ROOT109_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT109_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT109_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT109_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT109_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT109_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT109_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT109_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT109_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT109_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT109_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT109_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT109_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT109_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT109_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT109_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT109_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT109_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT109_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT109_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT109_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT109_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT109_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT109_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT109_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT109_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT109_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT109_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT109_TOG Bit Fields */ +#define CCM_PRE_ROOT109_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT109_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT109_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT109_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT109_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT109_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT109_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT109_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT109_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT109_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT109_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT109_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT109_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT109_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT109_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT109_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT109_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT109_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT109_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT109_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT109_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT109_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT109_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT109_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT109_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT109_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT109_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT109_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT109_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL109 Bit Fields */ +#define CCM_ACCESS_CTRL109_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL109_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL109_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL109_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL109_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL109_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL109_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL109_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL109_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL109_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL109_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL109_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL109_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL109_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL109_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL109_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL109_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL109_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL109_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL109_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL109_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL109_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL109_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL109_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL109_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL109_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL109_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL109_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL109_LOCK_SHIFT 31 +/* ACCESS_CTRL109_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL109_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL109_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL109_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL109_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL109_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL109_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL109_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL109_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL109_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL109_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL109_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL109_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL109_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL109_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL109_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL109_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL109_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL109_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT110 Bit Fields */ +#define CCM_TARGET_ROOT110_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT110_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT110_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_POST_PODF_MASK) +#define CCM_TARGET_ROOT110_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT110_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT110_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT110_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT110_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT110_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT110_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT110_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT110_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT110_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_PRE_PODF_MASK) +#define CCM_TARGET_ROOT110_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT110_MUX_SHIFT 24 +#define CCM_TARGET_ROOT110_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_MUX_SHIFT))&CCM_TARGET_ROOT110_MUX_MASK) +#define CCM_TARGET_ROOT110_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT110_ENABLE_SHIFT 28 +/* TARGET_ROOT110_SET Bit Fields */ +#define CCM_TARGET_ROOT110_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT110_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT110_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT110_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT110_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT110_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT110_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT110_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT110_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT110_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT110_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT110_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT110_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT110_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT110_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT110_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_SET_MUX_SHIFT))&CCM_TARGET_ROOT110_SET_MUX_MASK) +#define CCM_TARGET_ROOT110_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT110_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT110_CLR Bit Fields */ +#define CCM_TARGET_ROOT110_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT110_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT110_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT110_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT110_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT110_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT110_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT110_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT110_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT110_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT110_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT110_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT110_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_CLR_MUX_SHIFT))&CCM_TARGET_ROOT110_CLR_MUX_MASK) +#define CCM_TARGET_ROOT110_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT110_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT110_TOG Bit Fields */ +#define CCM_TARGET_ROOT110_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT110_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT110_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT110_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT110_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT110_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT110_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT110_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT110_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT110_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT110_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT110_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT110_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT110_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT110_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT110_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT110_TOG_MUX_SHIFT))&CCM_TARGET_ROOT110_TOG_MUX_MASK) +#define CCM_TARGET_ROOT110_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT110_TOG_ENABLE_SHIFT 28 +/* POST110 Bit Fields */ +#define CCM_POST110_POST_PODF_MASK 0x3Fu +#define CCM_POST110_POST_PODF_SHIFT 0 +#define CCM_POST110_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST110_POST_PODF_SHIFT))&CCM_POST110_POST_PODF_MASK) +#define CCM_POST110_BUSY1_MASK 0x80u +#define CCM_POST110_BUSY1_SHIFT 7 +#define CCM_POST110_AUTO_PODF_MASK 0x700u +#define CCM_POST110_AUTO_PODF_SHIFT 8 +#define CCM_POST110_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST110_AUTO_PODF_SHIFT))&CCM_POST110_AUTO_PODF_MASK) +#define CCM_POST110_AUTO_EN_MASK 0x1000u +#define CCM_POST110_AUTO_EN_SHIFT 12 +#define CCM_POST110_SLOW_MASK 0x8000u +#define CCM_POST110_SLOW_SHIFT 15 +#define CCM_POST110_SELECT_MASK 0x10000000u +#define CCM_POST110_SELECT_SHIFT 28 +#define CCM_POST110_BUSY2_MASK 0x80000000u +#define CCM_POST110_BUSY2_SHIFT 31 +/* POST_ROOT110_SET Bit Fields */ +#define CCM_POST_ROOT110_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT110_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT110_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_SET_POST_PODF_SHIFT))&CCM_POST_ROOT110_SET_POST_PODF_MASK) +#define CCM_POST_ROOT110_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT110_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT110_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT110_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT110_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT110_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT110_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT110_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT110_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT110_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT110_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT110_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT110_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT110_SET_BUSY2_SHIFT 31 +/* POST_ROOT110_CLR Bit Fields */ +#define CCM_POST_ROOT110_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT110_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT110_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT110_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT110_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT110_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT110_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT110_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT110_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT110_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT110_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT110_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT110_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT110_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT110_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT110_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT110_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT110_CLR_BUSY2_SHIFT 31 +/* POST_ROOT110_TOG Bit Fields */ +#define CCM_POST_ROOT110_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT110_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT110_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT110_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT110_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT110_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT110_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT110_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT110_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT110_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT110_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT110_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT110_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT110_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT110_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT110_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT110_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT110_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT110_TOG_BUSY2_SHIFT 31 +/* PRE110 Bit Fields */ +#define CCM_PRE110_PRE_PODF_B_MASK 0x7u +#define CCM_PRE110_PRE_PODF_B_SHIFT 0 +#define CCM_PRE110_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_PRE_PODF_B_SHIFT))&CCM_PRE110_PRE_PODF_B_MASK) +#define CCM_PRE110_BUSY0_MASK 0x8u +#define CCM_PRE110_BUSY0_SHIFT 3 +#define CCM_PRE110_MUX_B_MASK 0x700u +#define CCM_PRE110_MUX_B_SHIFT 8 +#define CCM_PRE110_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_MUX_B_SHIFT))&CCM_PRE110_MUX_B_MASK) +#define CCM_PRE110_EN_B_MASK 0x1000u +#define CCM_PRE110_EN_B_SHIFT 12 +#define CCM_PRE110_BUSY1_MASK 0x8000u +#define CCM_PRE110_BUSY1_SHIFT 15 +#define CCM_PRE110_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE110_PRE_PODF_A_SHIFT 16 +#define CCM_PRE110_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_PRE_PODF_A_SHIFT))&CCM_PRE110_PRE_PODF_A_MASK) +#define CCM_PRE110_BUSY3_MASK 0x80000u +#define CCM_PRE110_BUSY3_SHIFT 19 +#define CCM_PRE110_MUX_A_MASK 0x7000000u +#define CCM_PRE110_MUX_A_SHIFT 24 +#define CCM_PRE110_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE110_MUX_A_SHIFT))&CCM_PRE110_MUX_A_MASK) +#define CCM_PRE110_EN_A_MASK 0x10000000u +#define CCM_PRE110_EN_A_SHIFT 28 +#define CCM_PRE110_BUSY4_MASK 0x80000000u +#define CCM_PRE110_BUSY4_SHIFT 31 +/* PRE_ROOT110_SET Bit Fields */ +#define CCM_PRE_ROOT110_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT110_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT110_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT110_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT110_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT110_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT110_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT110_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT110_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_MUX_B_SHIFT))&CCM_PRE_ROOT110_SET_MUX_B_MASK) +#define CCM_PRE_ROOT110_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT110_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT110_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT110_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT110_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT110_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT110_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT110_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT110_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT110_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT110_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT110_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT110_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_SET_MUX_A_SHIFT))&CCM_PRE_ROOT110_SET_MUX_A_MASK) +#define CCM_PRE_ROOT110_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT110_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT110_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT110_SET_BUSY4_SHIFT 31 +/* PRE_ROOT110_CLR Bit Fields */ +#define CCM_PRE_ROOT110_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT110_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT110_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT110_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT110_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT110_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT110_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT110_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT110_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT110_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT110_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT110_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT110_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT110_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT110_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT110_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT110_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT110_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT110_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT110_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT110_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT110_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT110_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT110_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT110_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT110_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT110_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT110_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT110_TOG Bit Fields */ +#define CCM_PRE_ROOT110_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT110_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT110_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT110_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT110_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT110_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT110_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT110_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT110_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT110_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT110_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT110_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT110_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT110_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT110_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT110_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT110_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT110_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT110_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT110_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT110_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT110_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT110_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT110_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT110_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT110_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT110_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT110_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT110_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL110 Bit Fields */ +#define CCM_ACCESS_CTRL110_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL110_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL110_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL110_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL110_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL110_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL110_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL110_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL110_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL110_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL110_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL110_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL110_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL110_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL110_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL110_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL110_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL110_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL110_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL110_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL110_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL110_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL110_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL110_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL110_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL110_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL110_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL110_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL110_LOCK_SHIFT 31 +/* ACCESS_CTRL110_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL110_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL110_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL110_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL110_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL110_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL110_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL110_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL110_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL110_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL110_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL110_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL110_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL110_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL110_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL110_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL110_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL110_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL110_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT111 Bit Fields */ +#define CCM_TARGET_ROOT111_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT111_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT111_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_POST_PODF_MASK) +#define CCM_TARGET_ROOT111_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT111_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT111_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT111_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT111_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT111_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT111_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT111_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT111_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT111_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_PRE_PODF_MASK) +#define CCM_TARGET_ROOT111_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT111_MUX_SHIFT 24 +#define CCM_TARGET_ROOT111_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_MUX_SHIFT))&CCM_TARGET_ROOT111_MUX_MASK) +#define CCM_TARGET_ROOT111_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT111_ENABLE_SHIFT 28 +/* TARGET_ROOT111_SET Bit Fields */ +#define CCM_TARGET_ROOT111_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT111_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT111_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT111_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT111_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT111_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT111_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT111_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT111_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT111_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT111_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT111_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT111_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT111_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT111_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT111_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_SET_MUX_SHIFT))&CCM_TARGET_ROOT111_SET_MUX_MASK) +#define CCM_TARGET_ROOT111_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT111_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT111_CLR Bit Fields */ +#define CCM_TARGET_ROOT111_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT111_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT111_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT111_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT111_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT111_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT111_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT111_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT111_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT111_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT111_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT111_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT111_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_CLR_MUX_SHIFT))&CCM_TARGET_ROOT111_CLR_MUX_MASK) +#define CCM_TARGET_ROOT111_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT111_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT111_TOG Bit Fields */ +#define CCM_TARGET_ROOT111_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT111_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT111_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT111_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT111_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT111_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT111_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT111_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT111_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT111_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT111_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT111_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT111_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT111_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT111_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT111_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT111_TOG_MUX_SHIFT))&CCM_TARGET_ROOT111_TOG_MUX_MASK) +#define CCM_TARGET_ROOT111_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT111_TOG_ENABLE_SHIFT 28 +/* POST111 Bit Fields */ +#define CCM_POST111_POST_PODF_MASK 0x3Fu +#define CCM_POST111_POST_PODF_SHIFT 0 +#define CCM_POST111_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST111_POST_PODF_SHIFT))&CCM_POST111_POST_PODF_MASK) +#define CCM_POST111_BUSY1_MASK 0x80u +#define CCM_POST111_BUSY1_SHIFT 7 +#define CCM_POST111_AUTO_PODF_MASK 0x700u +#define CCM_POST111_AUTO_PODF_SHIFT 8 +#define CCM_POST111_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST111_AUTO_PODF_SHIFT))&CCM_POST111_AUTO_PODF_MASK) +#define CCM_POST111_AUTO_EN_MASK 0x1000u +#define CCM_POST111_AUTO_EN_SHIFT 12 +#define CCM_POST111_SLOW_MASK 0x8000u +#define CCM_POST111_SLOW_SHIFT 15 +#define CCM_POST111_SELECT_MASK 0x10000000u +#define CCM_POST111_SELECT_SHIFT 28 +#define CCM_POST111_BUSY2_MASK 0x80000000u +#define CCM_POST111_BUSY2_SHIFT 31 +/* POST_ROOT111_SET Bit Fields */ +#define CCM_POST_ROOT111_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT111_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT111_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_SET_POST_PODF_SHIFT))&CCM_POST_ROOT111_SET_POST_PODF_MASK) +#define CCM_POST_ROOT111_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT111_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT111_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT111_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT111_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT111_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT111_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT111_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT111_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT111_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT111_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT111_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT111_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT111_SET_BUSY2_SHIFT 31 +/* POST_ROOT111_CLR Bit Fields */ +#define CCM_POST_ROOT111_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT111_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT111_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT111_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT111_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT111_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT111_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT111_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT111_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT111_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT111_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT111_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT111_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT111_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT111_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT111_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT111_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT111_CLR_BUSY2_SHIFT 31 +/* POST_ROOT111_TOG Bit Fields */ +#define CCM_POST_ROOT111_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT111_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT111_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT111_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT111_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT111_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT111_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT111_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT111_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT111_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT111_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT111_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT111_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT111_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT111_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT111_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT111_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT111_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT111_TOG_BUSY2_SHIFT 31 +/* PRE111 Bit Fields */ +#define CCM_PRE111_PRE_PODF_B_MASK 0x7u +#define CCM_PRE111_PRE_PODF_B_SHIFT 0 +#define CCM_PRE111_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_PRE_PODF_B_SHIFT))&CCM_PRE111_PRE_PODF_B_MASK) +#define CCM_PRE111_BUSY0_MASK 0x8u +#define CCM_PRE111_BUSY0_SHIFT 3 +#define CCM_PRE111_MUX_B_MASK 0x700u +#define CCM_PRE111_MUX_B_SHIFT 8 +#define CCM_PRE111_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_MUX_B_SHIFT))&CCM_PRE111_MUX_B_MASK) +#define CCM_PRE111_EN_B_MASK 0x1000u +#define CCM_PRE111_EN_B_SHIFT 12 +#define CCM_PRE111_BUSY1_MASK 0x8000u +#define CCM_PRE111_BUSY1_SHIFT 15 +#define CCM_PRE111_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE111_PRE_PODF_A_SHIFT 16 +#define CCM_PRE111_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_PRE_PODF_A_SHIFT))&CCM_PRE111_PRE_PODF_A_MASK) +#define CCM_PRE111_BUSY3_MASK 0x80000u +#define CCM_PRE111_BUSY3_SHIFT 19 +#define CCM_PRE111_MUX_A_MASK 0x7000000u +#define CCM_PRE111_MUX_A_SHIFT 24 +#define CCM_PRE111_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE111_MUX_A_SHIFT))&CCM_PRE111_MUX_A_MASK) +#define CCM_PRE111_EN_A_MASK 0x10000000u +#define CCM_PRE111_EN_A_SHIFT 28 +#define CCM_PRE111_BUSY4_MASK 0x80000000u +#define CCM_PRE111_BUSY4_SHIFT 31 +/* PRE_ROOT111_SET Bit Fields */ +#define CCM_PRE_ROOT111_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT111_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT111_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT111_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT111_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT111_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT111_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT111_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT111_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_MUX_B_SHIFT))&CCM_PRE_ROOT111_SET_MUX_B_MASK) +#define CCM_PRE_ROOT111_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT111_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT111_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT111_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT111_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT111_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT111_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT111_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT111_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT111_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT111_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT111_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT111_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_SET_MUX_A_SHIFT))&CCM_PRE_ROOT111_SET_MUX_A_MASK) +#define CCM_PRE_ROOT111_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT111_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT111_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT111_SET_BUSY4_SHIFT 31 +/* PRE_ROOT111_CLR Bit Fields */ +#define CCM_PRE_ROOT111_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT111_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT111_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT111_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT111_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT111_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT111_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT111_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT111_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT111_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT111_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT111_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT111_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT111_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT111_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT111_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT111_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT111_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT111_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT111_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT111_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT111_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT111_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT111_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT111_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT111_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT111_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT111_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT111_TOG Bit Fields */ +#define CCM_PRE_ROOT111_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT111_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT111_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT111_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT111_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT111_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT111_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT111_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT111_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT111_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT111_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT111_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT111_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT111_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT111_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT111_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT111_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT111_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT111_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT111_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT111_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT111_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT111_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT111_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT111_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT111_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT111_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT111_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT111_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL111 Bit Fields */ +#define CCM_ACCESS_CTRL111_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL111_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL111_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL111_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL111_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL111_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL111_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL111_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL111_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL111_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL111_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL111_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL111_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL111_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL111_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL111_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL111_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL111_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL111_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL111_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL111_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL111_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL111_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL111_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL111_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL111_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL111_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL111_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL111_LOCK_SHIFT 31 +/* ACCESS_CTRL111_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL111_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL111_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL111_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL111_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL111_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL111_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL111_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL111_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL111_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL111_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL111_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL111_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL111_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL111_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL111_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL111_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL111_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL111_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT112 Bit Fields */ +#define CCM_TARGET_ROOT112_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT112_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT112_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_POST_PODF_MASK) +#define CCM_TARGET_ROOT112_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT112_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT112_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT112_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT112_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT112_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT112_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT112_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT112_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT112_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_PRE_PODF_MASK) +#define CCM_TARGET_ROOT112_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT112_MUX_SHIFT 24 +#define CCM_TARGET_ROOT112_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_MUX_SHIFT))&CCM_TARGET_ROOT112_MUX_MASK) +#define CCM_TARGET_ROOT112_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT112_ENABLE_SHIFT 28 +/* TARGET_ROOT112_SET Bit Fields */ +#define CCM_TARGET_ROOT112_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT112_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT112_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT112_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT112_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT112_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT112_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT112_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT112_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT112_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT112_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT112_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT112_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT112_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT112_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT112_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_SET_MUX_SHIFT))&CCM_TARGET_ROOT112_SET_MUX_MASK) +#define CCM_TARGET_ROOT112_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT112_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT112_CLR Bit Fields */ +#define CCM_TARGET_ROOT112_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT112_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT112_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT112_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT112_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT112_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT112_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT112_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT112_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT112_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT112_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT112_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT112_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_CLR_MUX_SHIFT))&CCM_TARGET_ROOT112_CLR_MUX_MASK) +#define CCM_TARGET_ROOT112_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT112_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT112_TOG Bit Fields */ +#define CCM_TARGET_ROOT112_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT112_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT112_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT112_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT112_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT112_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT112_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT112_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT112_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT112_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT112_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT112_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT112_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT112_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT112_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT112_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT112_TOG_MUX_SHIFT))&CCM_TARGET_ROOT112_TOG_MUX_MASK) +#define CCM_TARGET_ROOT112_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT112_TOG_ENABLE_SHIFT 28 +/* POST112 Bit Fields */ +#define CCM_POST112_POST_PODF_MASK 0x3Fu +#define CCM_POST112_POST_PODF_SHIFT 0 +#define CCM_POST112_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST112_POST_PODF_SHIFT))&CCM_POST112_POST_PODF_MASK) +#define CCM_POST112_BUSY1_MASK 0x80u +#define CCM_POST112_BUSY1_SHIFT 7 +#define CCM_POST112_AUTO_PODF_MASK 0x700u +#define CCM_POST112_AUTO_PODF_SHIFT 8 +#define CCM_POST112_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST112_AUTO_PODF_SHIFT))&CCM_POST112_AUTO_PODF_MASK) +#define CCM_POST112_AUTO_EN_MASK 0x1000u +#define CCM_POST112_AUTO_EN_SHIFT 12 +#define CCM_POST112_SLOW_MASK 0x8000u +#define CCM_POST112_SLOW_SHIFT 15 +#define CCM_POST112_SELECT_MASK 0x10000000u +#define CCM_POST112_SELECT_SHIFT 28 +#define CCM_POST112_BUSY2_MASK 0x80000000u +#define CCM_POST112_BUSY2_SHIFT 31 +/* POST_ROOT112_SET Bit Fields */ +#define CCM_POST_ROOT112_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT112_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT112_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_SET_POST_PODF_SHIFT))&CCM_POST_ROOT112_SET_POST_PODF_MASK) +#define CCM_POST_ROOT112_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT112_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT112_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT112_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT112_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT112_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT112_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT112_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT112_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT112_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT112_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT112_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT112_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT112_SET_BUSY2_SHIFT 31 +/* POST_ROOT112_CLR Bit Fields */ +#define CCM_POST_ROOT112_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT112_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT112_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT112_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT112_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT112_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT112_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT112_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT112_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT112_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT112_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT112_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT112_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT112_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT112_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT112_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT112_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT112_CLR_BUSY2_SHIFT 31 +/* POST_ROOT112_TOG Bit Fields */ +#define CCM_POST_ROOT112_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT112_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT112_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT112_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT112_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT112_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT112_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT112_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT112_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT112_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT112_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT112_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT112_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT112_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT112_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT112_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT112_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT112_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT112_TOG_BUSY2_SHIFT 31 +/* PRE112 Bit Fields */ +#define CCM_PRE112_PRE_PODF_B_MASK 0x7u +#define CCM_PRE112_PRE_PODF_B_SHIFT 0 +#define CCM_PRE112_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_PRE_PODF_B_SHIFT))&CCM_PRE112_PRE_PODF_B_MASK) +#define CCM_PRE112_BUSY0_MASK 0x8u +#define CCM_PRE112_BUSY0_SHIFT 3 +#define CCM_PRE112_MUX_B_MASK 0x700u +#define CCM_PRE112_MUX_B_SHIFT 8 +#define CCM_PRE112_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_MUX_B_SHIFT))&CCM_PRE112_MUX_B_MASK) +#define CCM_PRE112_EN_B_MASK 0x1000u +#define CCM_PRE112_EN_B_SHIFT 12 +#define CCM_PRE112_BUSY1_MASK 0x8000u +#define CCM_PRE112_BUSY1_SHIFT 15 +#define CCM_PRE112_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE112_PRE_PODF_A_SHIFT 16 +#define CCM_PRE112_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_PRE_PODF_A_SHIFT))&CCM_PRE112_PRE_PODF_A_MASK) +#define CCM_PRE112_BUSY3_MASK 0x80000u +#define CCM_PRE112_BUSY3_SHIFT 19 +#define CCM_PRE112_MUX_A_MASK 0x7000000u +#define CCM_PRE112_MUX_A_SHIFT 24 +#define CCM_PRE112_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE112_MUX_A_SHIFT))&CCM_PRE112_MUX_A_MASK) +#define CCM_PRE112_EN_A_MASK 0x10000000u +#define CCM_PRE112_EN_A_SHIFT 28 +#define CCM_PRE112_BUSY4_MASK 0x80000000u +#define CCM_PRE112_BUSY4_SHIFT 31 +/* PRE_ROOT112_SET Bit Fields */ +#define CCM_PRE_ROOT112_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT112_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT112_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT112_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT112_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT112_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT112_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT112_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT112_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_MUX_B_SHIFT))&CCM_PRE_ROOT112_SET_MUX_B_MASK) +#define CCM_PRE_ROOT112_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT112_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT112_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT112_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT112_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT112_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT112_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT112_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT112_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT112_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT112_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT112_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT112_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_SET_MUX_A_SHIFT))&CCM_PRE_ROOT112_SET_MUX_A_MASK) +#define CCM_PRE_ROOT112_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT112_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT112_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT112_SET_BUSY4_SHIFT 31 +/* PRE_ROOT112_CLR Bit Fields */ +#define CCM_PRE_ROOT112_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT112_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT112_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT112_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT112_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT112_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT112_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT112_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT112_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT112_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT112_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT112_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT112_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT112_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT112_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT112_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT112_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT112_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT112_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT112_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT112_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT112_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT112_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT112_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT112_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT112_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT112_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT112_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT112_TOG Bit Fields */ +#define CCM_PRE_ROOT112_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT112_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT112_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT112_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT112_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT112_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT112_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT112_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT112_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT112_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT112_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT112_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT112_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT112_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT112_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT112_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT112_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT112_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT112_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT112_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT112_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT112_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT112_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT112_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT112_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT112_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT112_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT112_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT112_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL112 Bit Fields */ +#define CCM_ACCESS_CTRL112_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL112_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL112_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL112_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL112_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL112_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL112_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL112_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL112_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL112_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL112_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL112_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL112_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL112_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL112_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL112_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL112_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL112_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL112_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL112_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL112_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL112_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL112_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL112_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL112_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL112_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL112_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL112_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL112_LOCK_SHIFT 31 +/* ACCESS_CTRL112_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL112_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL112_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL112_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL112_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL112_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL112_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL112_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL112_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL112_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL112_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL112_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL112_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL112_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL112_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL112_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL112_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL112_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL112_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT113 Bit Fields */ +#define CCM_TARGET_ROOT113_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT113_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT113_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_POST_PODF_MASK) +#define CCM_TARGET_ROOT113_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT113_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT113_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT113_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT113_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT113_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT113_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT113_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT113_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT113_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_PRE_PODF_MASK) +#define CCM_TARGET_ROOT113_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT113_MUX_SHIFT 24 +#define CCM_TARGET_ROOT113_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_MUX_SHIFT))&CCM_TARGET_ROOT113_MUX_MASK) +#define CCM_TARGET_ROOT113_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT113_ENABLE_SHIFT 28 +/* TARGET_ROOT113_SET Bit Fields */ +#define CCM_TARGET_ROOT113_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT113_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT113_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT113_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT113_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT113_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT113_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT113_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT113_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT113_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT113_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT113_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT113_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT113_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT113_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT113_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_SET_MUX_SHIFT))&CCM_TARGET_ROOT113_SET_MUX_MASK) +#define CCM_TARGET_ROOT113_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT113_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT113_CLR Bit Fields */ +#define CCM_TARGET_ROOT113_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT113_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT113_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT113_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT113_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT113_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT113_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT113_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT113_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT113_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT113_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT113_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT113_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_CLR_MUX_SHIFT))&CCM_TARGET_ROOT113_CLR_MUX_MASK) +#define CCM_TARGET_ROOT113_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT113_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT113_TOG Bit Fields */ +#define CCM_TARGET_ROOT113_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT113_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT113_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT113_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT113_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT113_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT113_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT113_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT113_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT113_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT113_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT113_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT113_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT113_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT113_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT113_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT113_TOG_MUX_SHIFT))&CCM_TARGET_ROOT113_TOG_MUX_MASK) +#define CCM_TARGET_ROOT113_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT113_TOG_ENABLE_SHIFT 28 +/* POST113 Bit Fields */ +#define CCM_POST113_POST_PODF_MASK 0x3Fu +#define CCM_POST113_POST_PODF_SHIFT 0 +#define CCM_POST113_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST113_POST_PODF_SHIFT))&CCM_POST113_POST_PODF_MASK) +#define CCM_POST113_BUSY1_MASK 0x80u +#define CCM_POST113_BUSY1_SHIFT 7 +#define CCM_POST113_AUTO_PODF_MASK 0x700u +#define CCM_POST113_AUTO_PODF_SHIFT 8 +#define CCM_POST113_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST113_AUTO_PODF_SHIFT))&CCM_POST113_AUTO_PODF_MASK) +#define CCM_POST113_AUTO_EN_MASK 0x1000u +#define CCM_POST113_AUTO_EN_SHIFT 12 +#define CCM_POST113_SLOW_MASK 0x8000u +#define CCM_POST113_SLOW_SHIFT 15 +#define CCM_POST113_SELECT_MASK 0x10000000u +#define CCM_POST113_SELECT_SHIFT 28 +#define CCM_POST113_BUSY2_MASK 0x80000000u +#define CCM_POST113_BUSY2_SHIFT 31 +/* POST_ROOT113_SET Bit Fields */ +#define CCM_POST_ROOT113_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT113_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT113_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_SET_POST_PODF_SHIFT))&CCM_POST_ROOT113_SET_POST_PODF_MASK) +#define CCM_POST_ROOT113_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT113_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT113_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT113_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT113_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT113_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT113_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT113_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT113_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT113_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT113_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT113_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT113_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT113_SET_BUSY2_SHIFT 31 +/* POST_ROOT113_CLR Bit Fields */ +#define CCM_POST_ROOT113_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT113_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT113_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT113_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT113_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT113_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT113_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT113_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT113_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT113_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT113_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT113_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT113_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT113_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT113_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT113_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT113_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT113_CLR_BUSY2_SHIFT 31 +/* POST_ROOT113_TOG Bit Fields */ +#define CCM_POST_ROOT113_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT113_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT113_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT113_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT113_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT113_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT113_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT113_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT113_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT113_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT113_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT113_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT113_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT113_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT113_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT113_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT113_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT113_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT113_TOG_BUSY2_SHIFT 31 +/* PRE113 Bit Fields */ +#define CCM_PRE113_PRE_PODF_B_MASK 0x7u +#define CCM_PRE113_PRE_PODF_B_SHIFT 0 +#define CCM_PRE113_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_PRE_PODF_B_SHIFT))&CCM_PRE113_PRE_PODF_B_MASK) +#define CCM_PRE113_BUSY0_MASK 0x8u +#define CCM_PRE113_BUSY0_SHIFT 3 +#define CCM_PRE113_MUX_B_MASK 0x700u +#define CCM_PRE113_MUX_B_SHIFT 8 +#define CCM_PRE113_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_MUX_B_SHIFT))&CCM_PRE113_MUX_B_MASK) +#define CCM_PRE113_EN_B_MASK 0x1000u +#define CCM_PRE113_EN_B_SHIFT 12 +#define CCM_PRE113_BUSY1_MASK 0x8000u +#define CCM_PRE113_BUSY1_SHIFT 15 +#define CCM_PRE113_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE113_PRE_PODF_A_SHIFT 16 +#define CCM_PRE113_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_PRE_PODF_A_SHIFT))&CCM_PRE113_PRE_PODF_A_MASK) +#define CCM_PRE113_BUSY3_MASK 0x80000u +#define CCM_PRE113_BUSY3_SHIFT 19 +#define CCM_PRE113_MUX_A_MASK 0x7000000u +#define CCM_PRE113_MUX_A_SHIFT 24 +#define CCM_PRE113_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE113_MUX_A_SHIFT))&CCM_PRE113_MUX_A_MASK) +#define CCM_PRE113_EN_A_MASK 0x10000000u +#define CCM_PRE113_EN_A_SHIFT 28 +#define CCM_PRE113_BUSY4_MASK 0x80000000u +#define CCM_PRE113_BUSY4_SHIFT 31 +/* PRE_ROOT113_SET Bit Fields */ +#define CCM_PRE_ROOT113_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT113_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT113_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT113_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT113_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT113_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT113_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT113_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT113_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_MUX_B_SHIFT))&CCM_PRE_ROOT113_SET_MUX_B_MASK) +#define CCM_PRE_ROOT113_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT113_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT113_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT113_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT113_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT113_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT113_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT113_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT113_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT113_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT113_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT113_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT113_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_SET_MUX_A_SHIFT))&CCM_PRE_ROOT113_SET_MUX_A_MASK) +#define CCM_PRE_ROOT113_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT113_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT113_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT113_SET_BUSY4_SHIFT 31 +/* PRE_ROOT113_CLR Bit Fields */ +#define CCM_PRE_ROOT113_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT113_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT113_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT113_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT113_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT113_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT113_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT113_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT113_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT113_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT113_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT113_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT113_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT113_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT113_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT113_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT113_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT113_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT113_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT113_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT113_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT113_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT113_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT113_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT113_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT113_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT113_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT113_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT113_TOG Bit Fields */ +#define CCM_PRE_ROOT113_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT113_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT113_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT113_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT113_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT113_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT113_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT113_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT113_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT113_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT113_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT113_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT113_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT113_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT113_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT113_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT113_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT113_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT113_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT113_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT113_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT113_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT113_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT113_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT113_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT113_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT113_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT113_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT113_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL113 Bit Fields */ +#define CCM_ACCESS_CTRL113_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL113_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL113_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL113_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL113_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL113_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL113_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL113_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL113_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL113_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL113_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL113_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL113_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL113_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL113_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL113_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL113_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL113_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL113_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL113_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL113_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL113_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL113_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL113_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL113_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL113_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL113_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL113_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL113_LOCK_SHIFT 31 +/* ACCESS_CTRL113_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL113_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL113_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL113_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL113_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL113_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL113_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL113_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL113_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL113_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL113_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL113_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL113_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL113_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL113_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL113_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL113_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL113_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL113_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT114 Bit Fields */ +#define CCM_TARGET_ROOT114_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT114_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT114_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_POST_PODF_MASK) +#define CCM_TARGET_ROOT114_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT114_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT114_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT114_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT114_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT114_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT114_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT114_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT114_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT114_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_PRE_PODF_MASK) +#define CCM_TARGET_ROOT114_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT114_MUX_SHIFT 24 +#define CCM_TARGET_ROOT114_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_MUX_SHIFT))&CCM_TARGET_ROOT114_MUX_MASK) +#define CCM_TARGET_ROOT114_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT114_ENABLE_SHIFT 28 +/* TARGET_ROOT114_SET Bit Fields */ +#define CCM_TARGET_ROOT114_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT114_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT114_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT114_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT114_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT114_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT114_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT114_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT114_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT114_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT114_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT114_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT114_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT114_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT114_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT114_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_SET_MUX_SHIFT))&CCM_TARGET_ROOT114_SET_MUX_MASK) +#define CCM_TARGET_ROOT114_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT114_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT114_CLR Bit Fields */ +#define CCM_TARGET_ROOT114_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT114_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT114_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT114_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT114_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT114_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT114_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT114_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT114_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT114_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT114_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT114_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT114_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_CLR_MUX_SHIFT))&CCM_TARGET_ROOT114_CLR_MUX_MASK) +#define CCM_TARGET_ROOT114_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT114_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT114_TOG Bit Fields */ +#define CCM_TARGET_ROOT114_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT114_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT114_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT114_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT114_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT114_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT114_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT114_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT114_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT114_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT114_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT114_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT114_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT114_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT114_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT114_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT114_TOG_MUX_SHIFT))&CCM_TARGET_ROOT114_TOG_MUX_MASK) +#define CCM_TARGET_ROOT114_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT114_TOG_ENABLE_SHIFT 28 +/* POST114 Bit Fields */ +#define CCM_POST114_POST_PODF_MASK 0x3Fu +#define CCM_POST114_POST_PODF_SHIFT 0 +#define CCM_POST114_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST114_POST_PODF_SHIFT))&CCM_POST114_POST_PODF_MASK) +#define CCM_POST114_BUSY1_MASK 0x80u +#define CCM_POST114_BUSY1_SHIFT 7 +#define CCM_POST114_AUTO_PODF_MASK 0x700u +#define CCM_POST114_AUTO_PODF_SHIFT 8 +#define CCM_POST114_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST114_AUTO_PODF_SHIFT))&CCM_POST114_AUTO_PODF_MASK) +#define CCM_POST114_AUTO_EN_MASK 0x1000u +#define CCM_POST114_AUTO_EN_SHIFT 12 +#define CCM_POST114_SLOW_MASK 0x8000u +#define CCM_POST114_SLOW_SHIFT 15 +#define CCM_POST114_SELECT_MASK 0x10000000u +#define CCM_POST114_SELECT_SHIFT 28 +#define CCM_POST114_BUSY2_MASK 0x80000000u +#define CCM_POST114_BUSY2_SHIFT 31 +/* POST_ROOT114_SET Bit Fields */ +#define CCM_POST_ROOT114_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT114_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT114_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_SET_POST_PODF_SHIFT))&CCM_POST_ROOT114_SET_POST_PODF_MASK) +#define CCM_POST_ROOT114_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT114_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT114_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT114_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT114_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT114_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT114_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT114_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT114_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT114_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT114_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT114_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT114_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT114_SET_BUSY2_SHIFT 31 +/* POST_ROOT114_CLR Bit Fields */ +#define CCM_POST_ROOT114_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT114_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT114_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT114_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT114_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT114_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT114_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT114_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT114_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT114_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT114_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT114_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT114_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT114_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT114_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT114_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT114_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT114_CLR_BUSY2_SHIFT 31 +/* POST_ROOT114_TOG Bit Fields */ +#define CCM_POST_ROOT114_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT114_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT114_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT114_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT114_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT114_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT114_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT114_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT114_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT114_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT114_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT114_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT114_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT114_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT114_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT114_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT114_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT114_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT114_TOG_BUSY2_SHIFT 31 +/* PRE114 Bit Fields */ +#define CCM_PRE114_PRE_PODF_B_MASK 0x7u +#define CCM_PRE114_PRE_PODF_B_SHIFT 0 +#define CCM_PRE114_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_PRE_PODF_B_SHIFT))&CCM_PRE114_PRE_PODF_B_MASK) +#define CCM_PRE114_BUSY0_MASK 0x8u +#define CCM_PRE114_BUSY0_SHIFT 3 +#define CCM_PRE114_MUX_B_MASK 0x700u +#define CCM_PRE114_MUX_B_SHIFT 8 +#define CCM_PRE114_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_MUX_B_SHIFT))&CCM_PRE114_MUX_B_MASK) +#define CCM_PRE114_EN_B_MASK 0x1000u +#define CCM_PRE114_EN_B_SHIFT 12 +#define CCM_PRE114_BUSY1_MASK 0x8000u +#define CCM_PRE114_BUSY1_SHIFT 15 +#define CCM_PRE114_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE114_PRE_PODF_A_SHIFT 16 +#define CCM_PRE114_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_PRE_PODF_A_SHIFT))&CCM_PRE114_PRE_PODF_A_MASK) +#define CCM_PRE114_BUSY3_MASK 0x80000u +#define CCM_PRE114_BUSY3_SHIFT 19 +#define CCM_PRE114_MUX_A_MASK 0x7000000u +#define CCM_PRE114_MUX_A_SHIFT 24 +#define CCM_PRE114_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE114_MUX_A_SHIFT))&CCM_PRE114_MUX_A_MASK) +#define CCM_PRE114_EN_A_MASK 0x10000000u +#define CCM_PRE114_EN_A_SHIFT 28 +#define CCM_PRE114_BUSY4_MASK 0x80000000u +#define CCM_PRE114_BUSY4_SHIFT 31 +/* PRE_ROOT114_SET Bit Fields */ +#define CCM_PRE_ROOT114_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT114_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT114_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT114_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT114_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT114_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT114_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT114_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT114_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_MUX_B_SHIFT))&CCM_PRE_ROOT114_SET_MUX_B_MASK) +#define CCM_PRE_ROOT114_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT114_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT114_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT114_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT114_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT114_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT114_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT114_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT114_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT114_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT114_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT114_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT114_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_SET_MUX_A_SHIFT))&CCM_PRE_ROOT114_SET_MUX_A_MASK) +#define CCM_PRE_ROOT114_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT114_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT114_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT114_SET_BUSY4_SHIFT 31 +/* PRE_ROOT114_CLR Bit Fields */ +#define CCM_PRE_ROOT114_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT114_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT114_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT114_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT114_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT114_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT114_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT114_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT114_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT114_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT114_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT114_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT114_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT114_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT114_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT114_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT114_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT114_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT114_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT114_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT114_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT114_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT114_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT114_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT114_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT114_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT114_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT114_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT114_TOG Bit Fields */ +#define CCM_PRE_ROOT114_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT114_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT114_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT114_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT114_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT114_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT114_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT114_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT114_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT114_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT114_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT114_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT114_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT114_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT114_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT114_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT114_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT114_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT114_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT114_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT114_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT114_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT114_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT114_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT114_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT114_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT114_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT114_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT114_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL114 Bit Fields */ +#define CCM_ACCESS_CTRL114_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL114_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL114_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL114_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL114_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL114_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL114_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL114_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL114_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL114_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL114_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL114_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL114_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL114_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL114_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL114_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL114_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL114_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL114_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL114_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL114_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL114_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL114_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL114_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL114_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL114_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL114_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL114_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL114_LOCK_SHIFT 31 +/* ACCESS_CTRL114_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL114_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL114_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL114_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL114_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL114_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL114_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL114_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL114_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL114_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL114_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL114_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL114_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL114_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL114_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL114_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL114_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL114_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL114_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT115 Bit Fields */ +#define CCM_TARGET_ROOT115_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT115_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT115_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_POST_PODF_MASK) +#define CCM_TARGET_ROOT115_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT115_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT115_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT115_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT115_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT115_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT115_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT115_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT115_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT115_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_PRE_PODF_MASK) +#define CCM_TARGET_ROOT115_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT115_MUX_SHIFT 24 +#define CCM_TARGET_ROOT115_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_MUX_SHIFT))&CCM_TARGET_ROOT115_MUX_MASK) +#define CCM_TARGET_ROOT115_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT115_ENABLE_SHIFT 28 +/* TARGET_ROOT115_SET Bit Fields */ +#define CCM_TARGET_ROOT115_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT115_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT115_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT115_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT115_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT115_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT115_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT115_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT115_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT115_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT115_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT115_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT115_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT115_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT115_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT115_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_SET_MUX_SHIFT))&CCM_TARGET_ROOT115_SET_MUX_MASK) +#define CCM_TARGET_ROOT115_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT115_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT115_CLR Bit Fields */ +#define CCM_TARGET_ROOT115_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT115_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT115_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT115_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT115_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT115_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT115_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT115_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT115_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT115_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT115_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT115_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT115_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_CLR_MUX_SHIFT))&CCM_TARGET_ROOT115_CLR_MUX_MASK) +#define CCM_TARGET_ROOT115_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT115_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT115_TOG Bit Fields */ +#define CCM_TARGET_ROOT115_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT115_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT115_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT115_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT115_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT115_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT115_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT115_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT115_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT115_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT115_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT115_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT115_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT115_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT115_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT115_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT115_TOG_MUX_SHIFT))&CCM_TARGET_ROOT115_TOG_MUX_MASK) +#define CCM_TARGET_ROOT115_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT115_TOG_ENABLE_SHIFT 28 +/* POST115 Bit Fields */ +#define CCM_POST115_POST_PODF_MASK 0x3Fu +#define CCM_POST115_POST_PODF_SHIFT 0 +#define CCM_POST115_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST115_POST_PODF_SHIFT))&CCM_POST115_POST_PODF_MASK) +#define CCM_POST115_BUSY1_MASK 0x80u +#define CCM_POST115_BUSY1_SHIFT 7 +#define CCM_POST115_AUTO_PODF_MASK 0x700u +#define CCM_POST115_AUTO_PODF_SHIFT 8 +#define CCM_POST115_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST115_AUTO_PODF_SHIFT))&CCM_POST115_AUTO_PODF_MASK) +#define CCM_POST115_AUTO_EN_MASK 0x1000u +#define CCM_POST115_AUTO_EN_SHIFT 12 +#define CCM_POST115_SLOW_MASK 0x8000u +#define CCM_POST115_SLOW_SHIFT 15 +#define CCM_POST115_SELECT_MASK 0x10000000u +#define CCM_POST115_SELECT_SHIFT 28 +#define CCM_POST115_BUSY2_MASK 0x80000000u +#define CCM_POST115_BUSY2_SHIFT 31 +/* POST_ROOT115_SET Bit Fields */ +#define CCM_POST_ROOT115_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT115_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT115_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_SET_POST_PODF_SHIFT))&CCM_POST_ROOT115_SET_POST_PODF_MASK) +#define CCM_POST_ROOT115_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT115_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT115_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT115_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT115_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT115_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT115_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT115_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT115_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT115_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT115_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT115_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT115_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT115_SET_BUSY2_SHIFT 31 +/* POST_ROOT115_CLR Bit Fields */ +#define CCM_POST_ROOT115_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT115_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT115_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT115_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT115_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT115_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT115_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT115_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT115_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT115_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT115_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT115_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT115_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT115_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT115_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT115_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT115_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT115_CLR_BUSY2_SHIFT 31 +/* POST_ROOT115_TOG Bit Fields */ +#define CCM_POST_ROOT115_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT115_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT115_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT115_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT115_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT115_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT115_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT115_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT115_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT115_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT115_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT115_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT115_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT115_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT115_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT115_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT115_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT115_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT115_TOG_BUSY2_SHIFT 31 +/* PRE115 Bit Fields */ +#define CCM_PRE115_PRE_PODF_B_MASK 0x7u +#define CCM_PRE115_PRE_PODF_B_SHIFT 0 +#define CCM_PRE115_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_PRE_PODF_B_SHIFT))&CCM_PRE115_PRE_PODF_B_MASK) +#define CCM_PRE115_BUSY0_MASK 0x8u +#define CCM_PRE115_BUSY0_SHIFT 3 +#define CCM_PRE115_MUX_B_MASK 0x700u +#define CCM_PRE115_MUX_B_SHIFT 8 +#define CCM_PRE115_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_MUX_B_SHIFT))&CCM_PRE115_MUX_B_MASK) +#define CCM_PRE115_EN_B_MASK 0x1000u +#define CCM_PRE115_EN_B_SHIFT 12 +#define CCM_PRE115_BUSY1_MASK 0x8000u +#define CCM_PRE115_BUSY1_SHIFT 15 +#define CCM_PRE115_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE115_PRE_PODF_A_SHIFT 16 +#define CCM_PRE115_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_PRE_PODF_A_SHIFT))&CCM_PRE115_PRE_PODF_A_MASK) +#define CCM_PRE115_BUSY3_MASK 0x80000u +#define CCM_PRE115_BUSY3_SHIFT 19 +#define CCM_PRE115_MUX_A_MASK 0x7000000u +#define CCM_PRE115_MUX_A_SHIFT 24 +#define CCM_PRE115_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE115_MUX_A_SHIFT))&CCM_PRE115_MUX_A_MASK) +#define CCM_PRE115_EN_A_MASK 0x10000000u +#define CCM_PRE115_EN_A_SHIFT 28 +#define CCM_PRE115_BUSY4_MASK 0x80000000u +#define CCM_PRE115_BUSY4_SHIFT 31 +/* PRE_ROOT115_SET Bit Fields */ +#define CCM_PRE_ROOT115_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT115_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT115_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT115_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT115_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT115_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT115_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT115_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT115_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_MUX_B_SHIFT))&CCM_PRE_ROOT115_SET_MUX_B_MASK) +#define CCM_PRE_ROOT115_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT115_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT115_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT115_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT115_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT115_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT115_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT115_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT115_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT115_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT115_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT115_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT115_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_SET_MUX_A_SHIFT))&CCM_PRE_ROOT115_SET_MUX_A_MASK) +#define CCM_PRE_ROOT115_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT115_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT115_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT115_SET_BUSY4_SHIFT 31 +/* PRE_ROOT115_CLR Bit Fields */ +#define CCM_PRE_ROOT115_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT115_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT115_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT115_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT115_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT115_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT115_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT115_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT115_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT115_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT115_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT115_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT115_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT115_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT115_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT115_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT115_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT115_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT115_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT115_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT115_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT115_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT115_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT115_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT115_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT115_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT115_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT115_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT115_TOG Bit Fields */ +#define CCM_PRE_ROOT115_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT115_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT115_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT115_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT115_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT115_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT115_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT115_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT115_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT115_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT115_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT115_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT115_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT115_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT115_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT115_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT115_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT115_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT115_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT115_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT115_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT115_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT115_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT115_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT115_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT115_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT115_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT115_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT115_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL115 Bit Fields */ +#define CCM_ACCESS_CTRL115_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL115_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL115_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL115_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL115_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL115_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL115_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL115_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL115_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL115_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL115_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL115_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL115_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL115_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL115_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL115_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL115_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL115_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL115_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL115_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL115_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL115_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL115_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL115_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL115_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL115_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL115_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL115_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL115_LOCK_SHIFT 31 +/* ACCESS_CTRL115_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL115_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL115_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL115_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL115_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL115_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL115_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL115_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL115_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL115_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL115_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL115_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL115_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL115_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL115_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL115_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL115_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL115_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL115_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT116 Bit Fields */ +#define CCM_TARGET_ROOT116_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT116_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT116_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_POST_PODF_MASK) +#define CCM_TARGET_ROOT116_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT116_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT116_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT116_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT116_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT116_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT116_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT116_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT116_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT116_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_PRE_PODF_MASK) +#define CCM_TARGET_ROOT116_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT116_MUX_SHIFT 24 +#define CCM_TARGET_ROOT116_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_MUX_SHIFT))&CCM_TARGET_ROOT116_MUX_MASK) +#define CCM_TARGET_ROOT116_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT116_ENABLE_SHIFT 28 +/* TARGET_ROOT116_SET Bit Fields */ +#define CCM_TARGET_ROOT116_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT116_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT116_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT116_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT116_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT116_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT116_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT116_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT116_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT116_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT116_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT116_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT116_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT116_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT116_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT116_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_SET_MUX_SHIFT))&CCM_TARGET_ROOT116_SET_MUX_MASK) +#define CCM_TARGET_ROOT116_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT116_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT116_CLR Bit Fields */ +#define CCM_TARGET_ROOT116_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT116_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT116_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT116_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT116_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT116_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT116_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT116_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT116_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT116_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT116_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT116_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT116_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_CLR_MUX_SHIFT))&CCM_TARGET_ROOT116_CLR_MUX_MASK) +#define CCM_TARGET_ROOT116_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT116_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT116_TOG Bit Fields */ +#define CCM_TARGET_ROOT116_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT116_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT116_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT116_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT116_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT116_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT116_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT116_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT116_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT116_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT116_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT116_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT116_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT116_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT116_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT116_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT116_TOG_MUX_SHIFT))&CCM_TARGET_ROOT116_TOG_MUX_MASK) +#define CCM_TARGET_ROOT116_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT116_TOG_ENABLE_SHIFT 28 +/* POST116 Bit Fields */ +#define CCM_POST116_POST_PODF_MASK 0x3Fu +#define CCM_POST116_POST_PODF_SHIFT 0 +#define CCM_POST116_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST116_POST_PODF_SHIFT))&CCM_POST116_POST_PODF_MASK) +#define CCM_POST116_BUSY1_MASK 0x80u +#define CCM_POST116_BUSY1_SHIFT 7 +#define CCM_POST116_AUTO_PODF_MASK 0x700u +#define CCM_POST116_AUTO_PODF_SHIFT 8 +#define CCM_POST116_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST116_AUTO_PODF_SHIFT))&CCM_POST116_AUTO_PODF_MASK) +#define CCM_POST116_AUTO_EN_MASK 0x1000u +#define CCM_POST116_AUTO_EN_SHIFT 12 +#define CCM_POST116_SLOW_MASK 0x8000u +#define CCM_POST116_SLOW_SHIFT 15 +#define CCM_POST116_SELECT_MASK 0x10000000u +#define CCM_POST116_SELECT_SHIFT 28 +#define CCM_POST116_BUSY2_MASK 0x80000000u +#define CCM_POST116_BUSY2_SHIFT 31 +/* POST_ROOT116_SET Bit Fields */ +#define CCM_POST_ROOT116_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT116_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT116_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_SET_POST_PODF_SHIFT))&CCM_POST_ROOT116_SET_POST_PODF_MASK) +#define CCM_POST_ROOT116_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT116_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT116_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT116_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT116_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT116_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT116_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT116_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT116_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT116_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT116_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT116_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT116_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT116_SET_BUSY2_SHIFT 31 +/* POST_ROOT116_CLR Bit Fields */ +#define CCM_POST_ROOT116_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT116_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT116_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT116_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT116_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT116_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT116_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT116_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT116_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT116_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT116_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT116_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT116_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT116_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT116_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT116_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT116_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT116_CLR_BUSY2_SHIFT 31 +/* POST_ROOT116_TOG Bit Fields */ +#define CCM_POST_ROOT116_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT116_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT116_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT116_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT116_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT116_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT116_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT116_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT116_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT116_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT116_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT116_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT116_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT116_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT116_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT116_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT116_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT116_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT116_TOG_BUSY2_SHIFT 31 +/* PRE116 Bit Fields */ +#define CCM_PRE116_PRE_PODF_B_MASK 0x7u +#define CCM_PRE116_PRE_PODF_B_SHIFT 0 +#define CCM_PRE116_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_PRE_PODF_B_SHIFT))&CCM_PRE116_PRE_PODF_B_MASK) +#define CCM_PRE116_BUSY0_MASK 0x8u +#define CCM_PRE116_BUSY0_SHIFT 3 +#define CCM_PRE116_MUX_B_MASK 0x700u +#define CCM_PRE116_MUX_B_SHIFT 8 +#define CCM_PRE116_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_MUX_B_SHIFT))&CCM_PRE116_MUX_B_MASK) +#define CCM_PRE116_EN_B_MASK 0x1000u +#define CCM_PRE116_EN_B_SHIFT 12 +#define CCM_PRE116_BUSY1_MASK 0x8000u +#define CCM_PRE116_BUSY1_SHIFT 15 +#define CCM_PRE116_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE116_PRE_PODF_A_SHIFT 16 +#define CCM_PRE116_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_PRE_PODF_A_SHIFT))&CCM_PRE116_PRE_PODF_A_MASK) +#define CCM_PRE116_BUSY3_MASK 0x80000u +#define CCM_PRE116_BUSY3_SHIFT 19 +#define CCM_PRE116_MUX_A_MASK 0x7000000u +#define CCM_PRE116_MUX_A_SHIFT 24 +#define CCM_PRE116_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE116_MUX_A_SHIFT))&CCM_PRE116_MUX_A_MASK) +#define CCM_PRE116_EN_A_MASK 0x10000000u +#define CCM_PRE116_EN_A_SHIFT 28 +#define CCM_PRE116_BUSY4_MASK 0x80000000u +#define CCM_PRE116_BUSY4_SHIFT 31 +/* PRE_ROOT116_SET Bit Fields */ +#define CCM_PRE_ROOT116_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT116_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT116_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT116_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT116_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT116_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT116_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT116_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT116_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_MUX_B_SHIFT))&CCM_PRE_ROOT116_SET_MUX_B_MASK) +#define CCM_PRE_ROOT116_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT116_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT116_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT116_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT116_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT116_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT116_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT116_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT116_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT116_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT116_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT116_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT116_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_SET_MUX_A_SHIFT))&CCM_PRE_ROOT116_SET_MUX_A_MASK) +#define CCM_PRE_ROOT116_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT116_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT116_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT116_SET_BUSY4_SHIFT 31 +/* PRE_ROOT116_CLR Bit Fields */ +#define CCM_PRE_ROOT116_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT116_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT116_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT116_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT116_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT116_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT116_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT116_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT116_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT116_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT116_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT116_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT116_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT116_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT116_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT116_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT116_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT116_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT116_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT116_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT116_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT116_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT116_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT116_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT116_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT116_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT116_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT116_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT116_TOG Bit Fields */ +#define CCM_PRE_ROOT116_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT116_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT116_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT116_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT116_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT116_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT116_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT116_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT116_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT116_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT116_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT116_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT116_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT116_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT116_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT116_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT116_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT116_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT116_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT116_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT116_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT116_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT116_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT116_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT116_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT116_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT116_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT116_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT116_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL116 Bit Fields */ +#define CCM_ACCESS_CTRL116_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL116_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL116_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL116_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL116_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL116_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL116_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL116_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL116_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL116_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL116_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL116_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL116_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL116_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL116_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL116_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL116_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL116_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL116_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL116_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL116_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL116_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL116_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL116_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL116_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL116_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL116_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL116_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL116_LOCK_SHIFT 31 +/* ACCESS_CTRL116_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL116_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL116_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL116_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL116_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL116_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL116_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL116_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL116_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL116_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL116_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL116_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL116_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL116_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL116_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL116_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL116_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL116_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL116_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT117 Bit Fields */ +#define CCM_TARGET_ROOT117_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT117_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT117_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_POST_PODF_MASK) +#define CCM_TARGET_ROOT117_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT117_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT117_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT117_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT117_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT117_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT117_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT117_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT117_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT117_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_PRE_PODF_MASK) +#define CCM_TARGET_ROOT117_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT117_MUX_SHIFT 24 +#define CCM_TARGET_ROOT117_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_MUX_SHIFT))&CCM_TARGET_ROOT117_MUX_MASK) +#define CCM_TARGET_ROOT117_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT117_ENABLE_SHIFT 28 +/* TARGET_ROOT117_SET Bit Fields */ +#define CCM_TARGET_ROOT117_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT117_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT117_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT117_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT117_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT117_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT117_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT117_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT117_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT117_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT117_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT117_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT117_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT117_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT117_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT117_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_SET_MUX_SHIFT))&CCM_TARGET_ROOT117_SET_MUX_MASK) +#define CCM_TARGET_ROOT117_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT117_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT117_CLR Bit Fields */ +#define CCM_TARGET_ROOT117_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT117_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT117_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT117_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT117_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT117_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT117_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT117_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT117_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT117_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT117_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT117_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT117_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_CLR_MUX_SHIFT))&CCM_TARGET_ROOT117_CLR_MUX_MASK) +#define CCM_TARGET_ROOT117_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT117_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT117_TOG Bit Fields */ +#define CCM_TARGET_ROOT117_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT117_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT117_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT117_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT117_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT117_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT117_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT117_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT117_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT117_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT117_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT117_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT117_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT117_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT117_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT117_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT117_TOG_MUX_SHIFT))&CCM_TARGET_ROOT117_TOG_MUX_MASK) +#define CCM_TARGET_ROOT117_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT117_TOG_ENABLE_SHIFT 28 +/* POST117 Bit Fields */ +#define CCM_POST117_POST_PODF_MASK 0x3Fu +#define CCM_POST117_POST_PODF_SHIFT 0 +#define CCM_POST117_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST117_POST_PODF_SHIFT))&CCM_POST117_POST_PODF_MASK) +#define CCM_POST117_BUSY1_MASK 0x80u +#define CCM_POST117_BUSY1_SHIFT 7 +#define CCM_POST117_AUTO_PODF_MASK 0x700u +#define CCM_POST117_AUTO_PODF_SHIFT 8 +#define CCM_POST117_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST117_AUTO_PODF_SHIFT))&CCM_POST117_AUTO_PODF_MASK) +#define CCM_POST117_AUTO_EN_MASK 0x1000u +#define CCM_POST117_AUTO_EN_SHIFT 12 +#define CCM_POST117_SLOW_MASK 0x8000u +#define CCM_POST117_SLOW_SHIFT 15 +#define CCM_POST117_SELECT_MASK 0x10000000u +#define CCM_POST117_SELECT_SHIFT 28 +#define CCM_POST117_BUSY2_MASK 0x80000000u +#define CCM_POST117_BUSY2_SHIFT 31 +/* POST_ROOT117_SET Bit Fields */ +#define CCM_POST_ROOT117_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT117_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT117_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_SET_POST_PODF_SHIFT))&CCM_POST_ROOT117_SET_POST_PODF_MASK) +#define CCM_POST_ROOT117_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT117_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT117_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT117_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT117_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT117_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT117_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT117_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT117_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT117_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT117_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT117_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT117_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT117_SET_BUSY2_SHIFT 31 +/* POST_ROOT117_CLR Bit Fields */ +#define CCM_POST_ROOT117_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT117_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT117_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT117_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT117_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT117_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT117_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT117_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT117_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT117_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT117_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT117_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT117_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT117_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT117_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT117_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT117_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT117_CLR_BUSY2_SHIFT 31 +/* POST_ROOT117_TOG Bit Fields */ +#define CCM_POST_ROOT117_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT117_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT117_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT117_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT117_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT117_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT117_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT117_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT117_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT117_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT117_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT117_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT117_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT117_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT117_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT117_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT117_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT117_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT117_TOG_BUSY2_SHIFT 31 +/* PRE117 Bit Fields */ +#define CCM_PRE117_PRE_PODF_B_MASK 0x7u +#define CCM_PRE117_PRE_PODF_B_SHIFT 0 +#define CCM_PRE117_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_PRE_PODF_B_SHIFT))&CCM_PRE117_PRE_PODF_B_MASK) +#define CCM_PRE117_BUSY0_MASK 0x8u +#define CCM_PRE117_BUSY0_SHIFT 3 +#define CCM_PRE117_MUX_B_MASK 0x700u +#define CCM_PRE117_MUX_B_SHIFT 8 +#define CCM_PRE117_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_MUX_B_SHIFT))&CCM_PRE117_MUX_B_MASK) +#define CCM_PRE117_EN_B_MASK 0x1000u +#define CCM_PRE117_EN_B_SHIFT 12 +#define CCM_PRE117_BUSY1_MASK 0x8000u +#define CCM_PRE117_BUSY1_SHIFT 15 +#define CCM_PRE117_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE117_PRE_PODF_A_SHIFT 16 +#define CCM_PRE117_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_PRE_PODF_A_SHIFT))&CCM_PRE117_PRE_PODF_A_MASK) +#define CCM_PRE117_BUSY3_MASK 0x80000u +#define CCM_PRE117_BUSY3_SHIFT 19 +#define CCM_PRE117_MUX_A_MASK 0x7000000u +#define CCM_PRE117_MUX_A_SHIFT 24 +#define CCM_PRE117_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE117_MUX_A_SHIFT))&CCM_PRE117_MUX_A_MASK) +#define CCM_PRE117_EN_A_MASK 0x10000000u +#define CCM_PRE117_EN_A_SHIFT 28 +#define CCM_PRE117_BUSY4_MASK 0x80000000u +#define CCM_PRE117_BUSY4_SHIFT 31 +/* PRE_ROOT117_SET Bit Fields */ +#define CCM_PRE_ROOT117_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT117_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT117_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT117_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT117_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT117_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT117_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT117_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT117_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_MUX_B_SHIFT))&CCM_PRE_ROOT117_SET_MUX_B_MASK) +#define CCM_PRE_ROOT117_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT117_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT117_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT117_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT117_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT117_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT117_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT117_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT117_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT117_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT117_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT117_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT117_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_SET_MUX_A_SHIFT))&CCM_PRE_ROOT117_SET_MUX_A_MASK) +#define CCM_PRE_ROOT117_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT117_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT117_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT117_SET_BUSY4_SHIFT 31 +/* PRE_ROOT117_CLR Bit Fields */ +#define CCM_PRE_ROOT117_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT117_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT117_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT117_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT117_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT117_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT117_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT117_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT117_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT117_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT117_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT117_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT117_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT117_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT117_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT117_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT117_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT117_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT117_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT117_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT117_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT117_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT117_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT117_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT117_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT117_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT117_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT117_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT117_TOG Bit Fields */ +#define CCM_PRE_ROOT117_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT117_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT117_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT117_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT117_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT117_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT117_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT117_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT117_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT117_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT117_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT117_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT117_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT117_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT117_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT117_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT117_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT117_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT117_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT117_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT117_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT117_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT117_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT117_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT117_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT117_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT117_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT117_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT117_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL117 Bit Fields */ +#define CCM_ACCESS_CTRL117_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL117_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL117_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL117_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL117_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL117_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL117_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL117_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL117_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL117_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL117_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL117_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL117_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL117_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL117_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL117_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL117_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL117_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL117_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL117_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL117_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL117_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL117_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL117_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL117_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL117_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL117_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL117_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL117_LOCK_SHIFT 31 +/* ACCESS_CTRL117_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL117_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL117_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL117_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL117_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL117_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL117_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL117_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL117_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL117_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL117_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL117_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL117_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL117_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL117_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL117_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL117_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL117_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL117_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT118 Bit Fields */ +#define CCM_TARGET_ROOT118_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT118_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT118_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_POST_PODF_MASK) +#define CCM_TARGET_ROOT118_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT118_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT118_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT118_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT118_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT118_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT118_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT118_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT118_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT118_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_PRE_PODF_MASK) +#define CCM_TARGET_ROOT118_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT118_MUX_SHIFT 24 +#define CCM_TARGET_ROOT118_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_MUX_SHIFT))&CCM_TARGET_ROOT118_MUX_MASK) +#define CCM_TARGET_ROOT118_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT118_ENABLE_SHIFT 28 +/* TARGET_ROOT118_SET Bit Fields */ +#define CCM_TARGET_ROOT118_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT118_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT118_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT118_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT118_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT118_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT118_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT118_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT118_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT118_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT118_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT118_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT118_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT118_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT118_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT118_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_SET_MUX_SHIFT))&CCM_TARGET_ROOT118_SET_MUX_MASK) +#define CCM_TARGET_ROOT118_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT118_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT118_CLR Bit Fields */ +#define CCM_TARGET_ROOT118_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT118_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT118_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT118_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT118_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT118_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT118_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT118_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT118_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT118_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT118_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT118_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT118_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_CLR_MUX_SHIFT))&CCM_TARGET_ROOT118_CLR_MUX_MASK) +#define CCM_TARGET_ROOT118_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT118_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT118_TOG Bit Fields */ +#define CCM_TARGET_ROOT118_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT118_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT118_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT118_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT118_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT118_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT118_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT118_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT118_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT118_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT118_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT118_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT118_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT118_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT118_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT118_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT118_TOG_MUX_SHIFT))&CCM_TARGET_ROOT118_TOG_MUX_MASK) +#define CCM_TARGET_ROOT118_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT118_TOG_ENABLE_SHIFT 28 +/* POST118 Bit Fields */ +#define CCM_POST118_POST_PODF_MASK 0x3Fu +#define CCM_POST118_POST_PODF_SHIFT 0 +#define CCM_POST118_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST118_POST_PODF_SHIFT))&CCM_POST118_POST_PODF_MASK) +#define CCM_POST118_BUSY1_MASK 0x80u +#define CCM_POST118_BUSY1_SHIFT 7 +#define CCM_POST118_AUTO_PODF_MASK 0x700u +#define CCM_POST118_AUTO_PODF_SHIFT 8 +#define CCM_POST118_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST118_AUTO_PODF_SHIFT))&CCM_POST118_AUTO_PODF_MASK) +#define CCM_POST118_AUTO_EN_MASK 0x1000u +#define CCM_POST118_AUTO_EN_SHIFT 12 +#define CCM_POST118_SLOW_MASK 0x8000u +#define CCM_POST118_SLOW_SHIFT 15 +#define CCM_POST118_SELECT_MASK 0x10000000u +#define CCM_POST118_SELECT_SHIFT 28 +#define CCM_POST118_BUSY2_MASK 0x80000000u +#define CCM_POST118_BUSY2_SHIFT 31 +/* POST_ROOT118_SET Bit Fields */ +#define CCM_POST_ROOT118_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT118_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT118_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_SET_POST_PODF_SHIFT))&CCM_POST_ROOT118_SET_POST_PODF_MASK) +#define CCM_POST_ROOT118_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT118_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT118_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT118_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT118_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT118_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT118_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT118_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT118_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT118_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT118_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT118_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT118_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT118_SET_BUSY2_SHIFT 31 +/* POST_ROOT118_CLR Bit Fields */ +#define CCM_POST_ROOT118_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT118_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT118_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT118_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT118_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT118_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT118_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT118_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT118_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT118_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT118_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT118_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT118_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT118_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT118_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT118_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT118_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT118_CLR_BUSY2_SHIFT 31 +/* POST_ROOT118_TOG Bit Fields */ +#define CCM_POST_ROOT118_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT118_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT118_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT118_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT118_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT118_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT118_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT118_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT118_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT118_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT118_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT118_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT118_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT118_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT118_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT118_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT118_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT118_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT118_TOG_BUSY2_SHIFT 31 +/* PRE118 Bit Fields */ +#define CCM_PRE118_PRE_PODF_B_MASK 0x7u +#define CCM_PRE118_PRE_PODF_B_SHIFT 0 +#define CCM_PRE118_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_PRE_PODF_B_SHIFT))&CCM_PRE118_PRE_PODF_B_MASK) +#define CCM_PRE118_BUSY0_MASK 0x8u +#define CCM_PRE118_BUSY0_SHIFT 3 +#define CCM_PRE118_MUX_B_MASK 0x700u +#define CCM_PRE118_MUX_B_SHIFT 8 +#define CCM_PRE118_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_MUX_B_SHIFT))&CCM_PRE118_MUX_B_MASK) +#define CCM_PRE118_EN_B_MASK 0x1000u +#define CCM_PRE118_EN_B_SHIFT 12 +#define CCM_PRE118_BUSY1_MASK 0x8000u +#define CCM_PRE118_BUSY1_SHIFT 15 +#define CCM_PRE118_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE118_PRE_PODF_A_SHIFT 16 +#define CCM_PRE118_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_PRE_PODF_A_SHIFT))&CCM_PRE118_PRE_PODF_A_MASK) +#define CCM_PRE118_BUSY3_MASK 0x80000u +#define CCM_PRE118_BUSY3_SHIFT 19 +#define CCM_PRE118_MUX_A_MASK 0x7000000u +#define CCM_PRE118_MUX_A_SHIFT 24 +#define CCM_PRE118_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE118_MUX_A_SHIFT))&CCM_PRE118_MUX_A_MASK) +#define CCM_PRE118_EN_A_MASK 0x10000000u +#define CCM_PRE118_EN_A_SHIFT 28 +#define CCM_PRE118_BUSY4_MASK 0x80000000u +#define CCM_PRE118_BUSY4_SHIFT 31 +/* PRE_ROOT118_SET Bit Fields */ +#define CCM_PRE_ROOT118_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT118_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT118_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT118_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT118_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT118_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT118_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT118_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT118_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_MUX_B_SHIFT))&CCM_PRE_ROOT118_SET_MUX_B_MASK) +#define CCM_PRE_ROOT118_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT118_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT118_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT118_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT118_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT118_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT118_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT118_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT118_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT118_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT118_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT118_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT118_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_SET_MUX_A_SHIFT))&CCM_PRE_ROOT118_SET_MUX_A_MASK) +#define CCM_PRE_ROOT118_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT118_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT118_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT118_SET_BUSY4_SHIFT 31 +/* PRE_ROOT118_CLR Bit Fields */ +#define CCM_PRE_ROOT118_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT118_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT118_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT118_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT118_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT118_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT118_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT118_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT118_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT118_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT118_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT118_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT118_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT118_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT118_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT118_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT118_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT118_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT118_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT118_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT118_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT118_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT118_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT118_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT118_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT118_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT118_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT118_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT118_TOG Bit Fields */ +#define CCM_PRE_ROOT118_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT118_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT118_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT118_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT118_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT118_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT118_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT118_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT118_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT118_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT118_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT118_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT118_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT118_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT118_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT118_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT118_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT118_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT118_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT118_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT118_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT118_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT118_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT118_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT118_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT118_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT118_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT118_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT118_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL118 Bit Fields */ +#define CCM_ACCESS_CTRL118_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL118_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL118_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL118_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL118_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL118_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL118_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL118_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL118_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL118_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL118_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL118_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL118_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL118_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL118_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL118_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL118_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL118_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL118_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL118_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL118_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL118_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL118_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL118_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL118_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL118_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL118_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL118_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL118_LOCK_SHIFT 31 +/* ACCESS_CTRL118_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL118_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL118_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL118_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL118_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL118_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL118_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL118_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL118_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL118_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL118_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL118_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL118_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL118_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL118_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL118_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL118_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL118_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL118_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT119 Bit Fields */ +#define CCM_TARGET_ROOT119_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT119_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT119_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_POST_PODF_MASK) +#define CCM_TARGET_ROOT119_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT119_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT119_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT119_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT119_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT119_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT119_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT119_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT119_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT119_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_PRE_PODF_MASK) +#define CCM_TARGET_ROOT119_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT119_MUX_SHIFT 24 +#define CCM_TARGET_ROOT119_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_MUX_SHIFT))&CCM_TARGET_ROOT119_MUX_MASK) +#define CCM_TARGET_ROOT119_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT119_ENABLE_SHIFT 28 +/* TARGET_ROOT119_SET Bit Fields */ +#define CCM_TARGET_ROOT119_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT119_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT119_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT119_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT119_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT119_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT119_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT119_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT119_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT119_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT119_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT119_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT119_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT119_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT119_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT119_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_SET_MUX_SHIFT))&CCM_TARGET_ROOT119_SET_MUX_MASK) +#define CCM_TARGET_ROOT119_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT119_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT119_CLR Bit Fields */ +#define CCM_TARGET_ROOT119_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT119_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT119_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT119_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT119_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT119_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT119_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT119_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT119_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT119_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT119_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT119_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT119_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_CLR_MUX_SHIFT))&CCM_TARGET_ROOT119_CLR_MUX_MASK) +#define CCM_TARGET_ROOT119_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT119_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT119_TOG Bit Fields */ +#define CCM_TARGET_ROOT119_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT119_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT119_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT119_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT119_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT119_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT119_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT119_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT119_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT119_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT119_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT119_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT119_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT119_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT119_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT119_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT119_TOG_MUX_SHIFT))&CCM_TARGET_ROOT119_TOG_MUX_MASK) +#define CCM_TARGET_ROOT119_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT119_TOG_ENABLE_SHIFT 28 +/* POST119 Bit Fields */ +#define CCM_POST119_POST_PODF_MASK 0x3Fu +#define CCM_POST119_POST_PODF_SHIFT 0 +#define CCM_POST119_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST119_POST_PODF_SHIFT))&CCM_POST119_POST_PODF_MASK) +#define CCM_POST119_BUSY1_MASK 0x80u +#define CCM_POST119_BUSY1_SHIFT 7 +#define CCM_POST119_AUTO_PODF_MASK 0x700u +#define CCM_POST119_AUTO_PODF_SHIFT 8 +#define CCM_POST119_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST119_AUTO_PODF_SHIFT))&CCM_POST119_AUTO_PODF_MASK) +#define CCM_POST119_AUTO_EN_MASK 0x1000u +#define CCM_POST119_AUTO_EN_SHIFT 12 +#define CCM_POST119_SLOW_MASK 0x8000u +#define CCM_POST119_SLOW_SHIFT 15 +#define CCM_POST119_SELECT_MASK 0x10000000u +#define CCM_POST119_SELECT_SHIFT 28 +#define CCM_POST119_BUSY2_MASK 0x80000000u +#define CCM_POST119_BUSY2_SHIFT 31 +/* POST_ROOT119_SET Bit Fields */ +#define CCM_POST_ROOT119_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT119_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT119_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_SET_POST_PODF_SHIFT))&CCM_POST_ROOT119_SET_POST_PODF_MASK) +#define CCM_POST_ROOT119_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT119_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT119_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT119_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT119_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT119_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT119_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT119_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT119_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT119_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT119_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT119_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT119_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT119_SET_BUSY2_SHIFT 31 +/* POST_ROOT119_CLR Bit Fields */ +#define CCM_POST_ROOT119_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT119_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT119_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT119_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT119_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT119_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT119_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT119_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT119_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT119_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT119_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT119_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT119_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT119_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT119_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT119_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT119_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT119_CLR_BUSY2_SHIFT 31 +/* POST_ROOT119_TOG Bit Fields */ +#define CCM_POST_ROOT119_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT119_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT119_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT119_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT119_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT119_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT119_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT119_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT119_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT119_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT119_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT119_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT119_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT119_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT119_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT119_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT119_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT119_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT119_TOG_BUSY2_SHIFT 31 +/* PRE119 Bit Fields */ +#define CCM_PRE119_PRE_PODF_B_MASK 0x7u +#define CCM_PRE119_PRE_PODF_B_SHIFT 0 +#define CCM_PRE119_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_PRE_PODF_B_SHIFT))&CCM_PRE119_PRE_PODF_B_MASK) +#define CCM_PRE119_BUSY0_MASK 0x8u +#define CCM_PRE119_BUSY0_SHIFT 3 +#define CCM_PRE119_MUX_B_MASK 0x700u +#define CCM_PRE119_MUX_B_SHIFT 8 +#define CCM_PRE119_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_MUX_B_SHIFT))&CCM_PRE119_MUX_B_MASK) +#define CCM_PRE119_EN_B_MASK 0x1000u +#define CCM_PRE119_EN_B_SHIFT 12 +#define CCM_PRE119_BUSY1_MASK 0x8000u +#define CCM_PRE119_BUSY1_SHIFT 15 +#define CCM_PRE119_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE119_PRE_PODF_A_SHIFT 16 +#define CCM_PRE119_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_PRE_PODF_A_SHIFT))&CCM_PRE119_PRE_PODF_A_MASK) +#define CCM_PRE119_BUSY3_MASK 0x80000u +#define CCM_PRE119_BUSY3_SHIFT 19 +#define CCM_PRE119_MUX_A_MASK 0x7000000u +#define CCM_PRE119_MUX_A_SHIFT 24 +#define CCM_PRE119_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE119_MUX_A_SHIFT))&CCM_PRE119_MUX_A_MASK) +#define CCM_PRE119_EN_A_MASK 0x10000000u +#define CCM_PRE119_EN_A_SHIFT 28 +#define CCM_PRE119_BUSY4_MASK 0x80000000u +#define CCM_PRE119_BUSY4_SHIFT 31 +/* PRE_ROOT119_SET Bit Fields */ +#define CCM_PRE_ROOT119_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT119_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT119_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT119_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT119_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT119_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT119_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT119_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT119_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_MUX_B_SHIFT))&CCM_PRE_ROOT119_SET_MUX_B_MASK) +#define CCM_PRE_ROOT119_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT119_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT119_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT119_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT119_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT119_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT119_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT119_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT119_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT119_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT119_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT119_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT119_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_SET_MUX_A_SHIFT))&CCM_PRE_ROOT119_SET_MUX_A_MASK) +#define CCM_PRE_ROOT119_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT119_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT119_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT119_SET_BUSY4_SHIFT 31 +/* PRE_ROOT119_CLR Bit Fields */ +#define CCM_PRE_ROOT119_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT119_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT119_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT119_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT119_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT119_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT119_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT119_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT119_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT119_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT119_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT119_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT119_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT119_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT119_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT119_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT119_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT119_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT119_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT119_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT119_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT119_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT119_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT119_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT119_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT119_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT119_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT119_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT119_TOG Bit Fields */ +#define CCM_PRE_ROOT119_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT119_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT119_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT119_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT119_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT119_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT119_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT119_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT119_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT119_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT119_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT119_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT119_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT119_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT119_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT119_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT119_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT119_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT119_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT119_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT119_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT119_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT119_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT119_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT119_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT119_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT119_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT119_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT119_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL119 Bit Fields */ +#define CCM_ACCESS_CTRL119_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL119_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL119_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL119_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL119_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL119_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL119_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL119_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL119_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL119_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL119_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL119_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL119_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL119_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL119_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL119_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL119_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL119_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL119_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL119_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL119_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL119_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL119_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL119_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL119_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL119_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL119_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL119_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL119_LOCK_SHIFT 31 +/* ACCESS_CTRL119_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL119_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL119_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL119_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL119_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL119_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL119_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL119_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL119_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL119_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL119_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL119_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL119_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL119_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL119_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL119_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL119_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL119_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL119_ROOT_TOG_LOCK_SHIFT 31 +/* TARGET_ROOT120 Bit Fields */ +#define CCM_TARGET_ROOT120_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT120_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT120_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_POST_PODF_MASK) +#define CCM_TARGET_ROOT120_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT120_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT120_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT120_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT120_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT120_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT120_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT120_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT120_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT120_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_PRE_PODF_MASK) +#define CCM_TARGET_ROOT120_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT120_MUX_SHIFT 24 +#define CCM_TARGET_ROOT120_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_MUX_SHIFT))&CCM_TARGET_ROOT120_MUX_MASK) +#define CCM_TARGET_ROOT120_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT120_ENABLE_SHIFT 28 +/* TARGET_ROOT120_SET Bit Fields */ +#define CCM_TARGET_ROOT120_SET_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT120_SET_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT120_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_SET_POST_PODF_MASK) +#define CCM_TARGET_ROOT120_SET_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT120_SET_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT120_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_SET_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT120_SET_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT120_SET_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT120_SET_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT120_SET_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT120_SET_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT120_SET_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT120_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_SET_PRE_PODF_MASK) +#define CCM_TARGET_ROOT120_SET_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT120_SET_MUX_SHIFT 24 +#define CCM_TARGET_ROOT120_SET_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_SET_MUX_SHIFT))&CCM_TARGET_ROOT120_SET_MUX_MASK) +#define CCM_TARGET_ROOT120_SET_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT120_SET_ENABLE_SHIFT 28 +/* TARGET_ROOT120_CLR Bit Fields */ +#define CCM_TARGET_ROOT120_CLR_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT120_CLR_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT120_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_CLR_POST_PODF_MASK) +#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT120_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_CLR_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT120_CLR_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT120_CLR_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT120_CLR_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT120_CLR_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT120_CLR_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT120_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_CLR_PRE_PODF_MASK) +#define CCM_TARGET_ROOT120_CLR_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT120_CLR_MUX_SHIFT 24 +#define CCM_TARGET_ROOT120_CLR_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_CLR_MUX_SHIFT))&CCM_TARGET_ROOT120_CLR_MUX_MASK) +#define CCM_TARGET_ROOT120_CLR_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT120_CLR_ENABLE_SHIFT 28 +/* TARGET_ROOT120_TOG Bit Fields */ +#define CCM_TARGET_ROOT120_TOG_POST_PODF_MASK 0x3Fu +#define CCM_TARGET_ROOT120_TOG_POST_PODF_SHIFT 0 +#define CCM_TARGET_ROOT120_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_POST_PODF_SHIFT))&CCM_TARGET_ROOT120_TOG_POST_PODF_MASK) +#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_MASK 0x700u +#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_SHIFT 8 +#define CCM_TARGET_ROOT120_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_AUTO_PODF_SHIFT))&CCM_TARGET_ROOT120_TOG_AUTO_PODF_MASK) +#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_EN_MASK 0x1000u +#define CCM_TARGET_ROOT120_TOG_AUTO_PODF_EN_SHIFT 12 +#define CCM_TARGET_ROOT120_TOG_SLOW_MASK 0x8000u +#define CCM_TARGET_ROOT120_TOG_SLOW_SHIFT 15 +#define CCM_TARGET_ROOT120_TOG_PRE_PODF_MASK 0x70000u +#define CCM_TARGET_ROOT120_TOG_PRE_PODF_SHIFT 16 +#define CCM_TARGET_ROOT120_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_PRE_PODF_SHIFT))&CCM_TARGET_ROOT120_TOG_PRE_PODF_MASK) +#define CCM_TARGET_ROOT120_TOG_MUX_MASK 0x7000000u +#define CCM_TARGET_ROOT120_TOG_MUX_SHIFT 24 +#define CCM_TARGET_ROOT120_TOG_MUX(x) (((uint32_t)(((uint32_t)(x))<<CCM_TARGET_ROOT120_TOG_MUX_SHIFT))&CCM_TARGET_ROOT120_TOG_MUX_MASK) +#define CCM_TARGET_ROOT120_TOG_ENABLE_MASK 0x10000000u +#define CCM_TARGET_ROOT120_TOG_ENABLE_SHIFT 28 +/* POST120 Bit Fields */ +#define CCM_POST120_POST_PODF_MASK 0x3Fu +#define CCM_POST120_POST_PODF_SHIFT 0 +#define CCM_POST120_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST120_POST_PODF_SHIFT))&CCM_POST120_POST_PODF_MASK) +#define CCM_POST120_BUSY1_MASK 0x80u +#define CCM_POST120_BUSY1_SHIFT 7 +#define CCM_POST120_AUTO_PODF_MASK 0x700u +#define CCM_POST120_AUTO_PODF_SHIFT 8 +#define CCM_POST120_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST120_AUTO_PODF_SHIFT))&CCM_POST120_AUTO_PODF_MASK) +#define CCM_POST120_AUTO_EN_MASK 0x1000u +#define CCM_POST120_AUTO_EN_SHIFT 12 +#define CCM_POST120_SLOW_MASK 0x8000u +#define CCM_POST120_SLOW_SHIFT 15 +#define CCM_POST120_SELECT_MASK 0x10000000u +#define CCM_POST120_SELECT_SHIFT 28 +#define CCM_POST120_BUSY2_MASK 0x80000000u +#define CCM_POST120_BUSY2_SHIFT 31 +/* POST_ROOT120_SET Bit Fields */ +#define CCM_POST_ROOT120_SET_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT120_SET_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT120_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_SET_POST_PODF_SHIFT))&CCM_POST_ROOT120_SET_POST_PODF_MASK) +#define CCM_POST_ROOT120_SET_BUSY1_MASK 0x80u +#define CCM_POST_ROOT120_SET_BUSY1_SHIFT 7 +#define CCM_POST_ROOT120_SET_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT120_SET_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT120_SET_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_SET_AUTO_PODF_SHIFT))&CCM_POST_ROOT120_SET_AUTO_PODF_MASK) +#define CCM_POST_ROOT120_SET_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT120_SET_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT120_SET_SLOW_MASK 0x8000u +#define CCM_POST_ROOT120_SET_SLOW_SHIFT 15 +#define CCM_POST_ROOT120_SET_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT120_SET_SELECT_SHIFT 28 +#define CCM_POST_ROOT120_SET_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT120_SET_BUSY2_SHIFT 31 +/* POST_ROOT120_CLR Bit Fields */ +#define CCM_POST_ROOT120_CLR_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT120_CLR_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT120_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_CLR_POST_PODF_SHIFT))&CCM_POST_ROOT120_CLR_POST_PODF_MASK) +#define CCM_POST_ROOT120_CLR_BUSY1_MASK 0x80u +#define CCM_POST_ROOT120_CLR_BUSY1_SHIFT 7 +#define CCM_POST_ROOT120_CLR_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT120_CLR_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT120_CLR_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_CLR_AUTO_PODF_SHIFT))&CCM_POST_ROOT120_CLR_AUTO_PODF_MASK) +#define CCM_POST_ROOT120_CLR_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT120_CLR_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT120_CLR_SLOW_MASK 0x8000u +#define CCM_POST_ROOT120_CLR_SLOW_SHIFT 15 +#define CCM_POST_ROOT120_CLR_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT120_CLR_SELECT_SHIFT 28 +#define CCM_POST_ROOT120_CLR_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT120_CLR_BUSY2_SHIFT 31 +/* POST_ROOT120_TOG Bit Fields */ +#define CCM_POST_ROOT120_TOG_POST_PODF_MASK 0x3Fu +#define CCM_POST_ROOT120_TOG_POST_PODF_SHIFT 0 +#define CCM_POST_ROOT120_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_TOG_POST_PODF_SHIFT))&CCM_POST_ROOT120_TOG_POST_PODF_MASK) +#define CCM_POST_ROOT120_TOG_BUSY1_MASK 0x80u +#define CCM_POST_ROOT120_TOG_BUSY1_SHIFT 7 +#define CCM_POST_ROOT120_TOG_AUTO_PODF_MASK 0x700u +#define CCM_POST_ROOT120_TOG_AUTO_PODF_SHIFT 8 +#define CCM_POST_ROOT120_TOG_AUTO_PODF(x) (((uint32_t)(((uint32_t)(x))<<CCM_POST_ROOT120_TOG_AUTO_PODF_SHIFT))&CCM_POST_ROOT120_TOG_AUTO_PODF_MASK) +#define CCM_POST_ROOT120_TOG_AUTO_EN_MASK 0x1000u +#define CCM_POST_ROOT120_TOG_AUTO_EN_SHIFT 12 +#define CCM_POST_ROOT120_TOG_SLOW_MASK 0x8000u +#define CCM_POST_ROOT120_TOG_SLOW_SHIFT 15 +#define CCM_POST_ROOT120_TOG_SELECT_MASK 0x10000000u +#define CCM_POST_ROOT120_TOG_SELECT_SHIFT 28 +#define CCM_POST_ROOT120_TOG_BUSY2_MASK 0x80000000u +#define CCM_POST_ROOT120_TOG_BUSY2_SHIFT 31 +/* PRE120 Bit Fields */ +#define CCM_PRE120_PRE_PODF_B_MASK 0x7u +#define CCM_PRE120_PRE_PODF_B_SHIFT 0 +#define CCM_PRE120_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_PRE_PODF_B_SHIFT))&CCM_PRE120_PRE_PODF_B_MASK) +#define CCM_PRE120_BUSY0_MASK 0x8u +#define CCM_PRE120_BUSY0_SHIFT 3 +#define CCM_PRE120_MUX_B_MASK 0x700u +#define CCM_PRE120_MUX_B_SHIFT 8 +#define CCM_PRE120_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_MUX_B_SHIFT))&CCM_PRE120_MUX_B_MASK) +#define CCM_PRE120_EN_B_MASK 0x1000u +#define CCM_PRE120_EN_B_SHIFT 12 +#define CCM_PRE120_BUSY1_MASK 0x8000u +#define CCM_PRE120_BUSY1_SHIFT 15 +#define CCM_PRE120_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE120_PRE_PODF_A_SHIFT 16 +#define CCM_PRE120_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_PRE_PODF_A_SHIFT))&CCM_PRE120_PRE_PODF_A_MASK) +#define CCM_PRE120_BUSY3_MASK 0x80000u +#define CCM_PRE120_BUSY3_SHIFT 19 +#define CCM_PRE120_MUX_A_MASK 0x7000000u +#define CCM_PRE120_MUX_A_SHIFT 24 +#define CCM_PRE120_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE120_MUX_A_SHIFT))&CCM_PRE120_MUX_A_MASK) +#define CCM_PRE120_EN_A_MASK 0x10000000u +#define CCM_PRE120_EN_A_SHIFT 28 +#define CCM_PRE120_BUSY4_MASK 0x80000000u +#define CCM_PRE120_BUSY4_SHIFT 31 +/* PRE_ROOT120_SET Bit Fields */ +#define CCM_PRE_ROOT120_SET_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT120_SET_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT120_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT120_SET_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT120_SET_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT120_SET_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT120_SET_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT120_SET_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT120_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_MUX_B_SHIFT))&CCM_PRE_ROOT120_SET_MUX_B_MASK) +#define CCM_PRE_ROOT120_SET_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT120_SET_EN_B_SHIFT 12 +#define CCM_PRE_ROOT120_SET_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT120_SET_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT120_SET_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT120_SET_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT120_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT120_SET_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT120_SET_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT120_SET_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT120_SET_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT120_SET_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT120_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_SET_MUX_A_SHIFT))&CCM_PRE_ROOT120_SET_MUX_A_MASK) +#define CCM_PRE_ROOT120_SET_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT120_SET_EN_A_SHIFT 28 +#define CCM_PRE_ROOT120_SET_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT120_SET_BUSY4_SHIFT 31 +/* PRE_ROOT120_CLR Bit Fields */ +#define CCM_PRE_ROOT120_CLR_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT120_CLR_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT120_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT120_CLR_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT120_CLR_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT120_CLR_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT120_CLR_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT120_CLR_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT120_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_MUX_B_SHIFT))&CCM_PRE_ROOT120_CLR_MUX_B_MASK) +#define CCM_PRE_ROOT120_CLR_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT120_CLR_EN_B_SHIFT 12 +#define CCM_PRE_ROOT120_CLR_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT120_CLR_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT120_CLR_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT120_CLR_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT120_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT120_CLR_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT120_CLR_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT120_CLR_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT120_CLR_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT120_CLR_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT120_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_CLR_MUX_A_SHIFT))&CCM_PRE_ROOT120_CLR_MUX_A_MASK) +#define CCM_PRE_ROOT120_CLR_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT120_CLR_EN_A_SHIFT 28 +#define CCM_PRE_ROOT120_CLR_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT120_CLR_BUSY4_SHIFT 31 +/* PRE_ROOT120_TOG Bit Fields */ +#define CCM_PRE_ROOT120_TOG_PRE_PODF_B_MASK 0x7u +#define CCM_PRE_ROOT120_TOG_PRE_PODF_B_SHIFT 0 +#define CCM_PRE_ROOT120_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_PRE_PODF_B_SHIFT))&CCM_PRE_ROOT120_TOG_PRE_PODF_B_MASK) +#define CCM_PRE_ROOT120_TOG_BUSY0_MASK 0x8u +#define CCM_PRE_ROOT120_TOG_BUSY0_SHIFT 3 +#define CCM_PRE_ROOT120_TOG_MUX_B_MASK 0x700u +#define CCM_PRE_ROOT120_TOG_MUX_B_SHIFT 8 +#define CCM_PRE_ROOT120_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_MUX_B_SHIFT))&CCM_PRE_ROOT120_TOG_MUX_B_MASK) +#define CCM_PRE_ROOT120_TOG_EN_B_MASK 0x1000u +#define CCM_PRE_ROOT120_TOG_EN_B_SHIFT 12 +#define CCM_PRE_ROOT120_TOG_BUSY1_MASK 0x8000u +#define CCM_PRE_ROOT120_TOG_BUSY1_SHIFT 15 +#define CCM_PRE_ROOT120_TOG_PRE_PODF_A_MASK 0x70000u +#define CCM_PRE_ROOT120_TOG_PRE_PODF_A_SHIFT 16 +#define CCM_PRE_ROOT120_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_PRE_PODF_A_SHIFT))&CCM_PRE_ROOT120_TOG_PRE_PODF_A_MASK) +#define CCM_PRE_ROOT120_TOG_BUSY3_MASK 0x80000u +#define CCM_PRE_ROOT120_TOG_BUSY3_SHIFT 19 +#define CCM_PRE_ROOT120_TOG_MUX_A_MASK 0x7000000u +#define CCM_PRE_ROOT120_TOG_MUX_A_SHIFT 24 +#define CCM_PRE_ROOT120_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_PRE_ROOT120_TOG_MUX_A_SHIFT))&CCM_PRE_ROOT120_TOG_MUX_A_MASK) +#define CCM_PRE_ROOT120_TOG_EN_A_MASK 0x10000000u +#define CCM_PRE_ROOT120_TOG_EN_A_SHIFT 28 +#define CCM_PRE_ROOT120_TOG_BUSY4_MASK 0x80000000u +#define CCM_PRE_ROOT120_TOG_BUSY4_SHIFT 31 +/* ACCESS_CTRL120 Bit Fields */ +#define CCM_ACCESS_CTRL120_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL120_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL120_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL120_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL120_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL120_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL120_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL120_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL120_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL120_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL120_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL120_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL120_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL120_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL120_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL120_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL120_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL120_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL120_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL120_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL120_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL120_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL120_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL120_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL120_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL120_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL120_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL120_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL120_LOCK_SHIFT 31 +/* ACCESS_CTRL120_ROOT_SET Bit Fields */ +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_ROOT_SET_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL120_ROOT_SET_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL120_ROOT_SET_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL120_ROOT_SET_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL120_ROOT_SET_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL120_ROOT_SET_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL120_ROOT_SET_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL120_ROOT_SET_LOCK_SHIFT 31 +/* ACCESS_CTRL120_ROOT_CLR Bit Fields */ +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_ROOT_CLR_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL120_ROOT_CLR_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL120_ROOT_CLR_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL120_ROOT_CLR_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL120_ROOT_CLR_LOCK_SHIFT 31 +/* ACCESS_CTRL120_ROOT_TOG Bit Fields */ +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_MASK 0xFu +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_SHIFT 0 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_MASK) +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_MASK 0xF0u +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_SHIFT 4 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_MASK) +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_MASK 0xF00u +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_SHIFT 8 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_MASK) +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_MASK 0xF000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_SHIFT 12 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_MASK) +#define CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_MASK 0x30000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_SHIFT 16 +#define CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x))<<CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_SHIFT))&CCM_ACCESS_CTRL120_ROOT_TOG_OWNER_ID_MASK) +#define CCM_ACCESS_CTRL120_ROOT_TOG_MUTEX_MASK 0x100000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_MUTEX_SHIFT 20 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_1_MASK 0x1000000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN0_1_SHIFT 24 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_1_MASK 0x2000000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN1_1_SHIFT 25 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_1_MASK 0x4000000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN2_1_SHIFT 26 +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_1_MASK 0x8000000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_DOMAIN3_1_SHIFT 27 +#define CCM_ACCESS_CTRL120_ROOT_TOG_SEMA_EN_MASK 0x10000000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_SEMA_EN_SHIFT 28 +#define CCM_ACCESS_CTRL120_ROOT_TOG_LOCK_MASK 0x80000000u +#define CCM_ACCESS_CTRL120_ROOT_TOG_LOCK_SHIFT 31 + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x30380000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +#define CCM_BASE_PTR (CCM) +/** Array initializer of CCM peripheral base adresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } + +/* ---------------------------------------------------------------------------- + -- CCM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Accessor_Macros CCM - Register accessor macros + * @{ + */ + + +/* CCM - Register instance definitions */ +/* CCM */ +#define CCM_GPR0 CCM_GPR0_REG(CCM_BASE_PTR) +#define CCM_GPR0_SET CCM_GPR0_SET_REG(CCM_BASE_PTR) +#define CCM_GPR0_CLR CCM_GPR0_CLR_REG(CCM_BASE_PTR) +#define CCM_GPR0_TOG CCM_GPR0_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR0 CCM_CCGR0_REG(CCM_BASE_PTR) +#define CCM_CCGR0_SET CCM_CCGR0_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR0_CLR CCM_CCGR0_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR0_TOG CCM_CCGR0_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR1 CCM_CCGR1_REG(CCM_BASE_PTR) +#define CCM_CCGR1_SET CCM_CCGR1_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR1_CLR CCM_CCGR1_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR1_TOG CCM_CCGR1_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR2 CCM_CCGR2_REG(CCM_BASE_PTR) +#define CCM_CCGR2_SET CCM_CCGR2_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR2_CLR CCM_CCGR2_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR2_TOG CCM_CCGR2_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR3 CCM_CCGR3_REG(CCM_BASE_PTR) +#define CCM_CCGR3_SET CCM_CCGR3_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR3_CLR CCM_CCGR3_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR3_TOG CCM_CCGR3_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR4 CCM_CCGR4_REG(CCM_BASE_PTR) +#define CCM_CCGR4_SET CCM_CCGR4_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR4_CLR CCM_CCGR4_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR4_TOG CCM_CCGR4_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR5 CCM_CCGR5_REG(CCM_BASE_PTR) +#define CCM_CCGR5_SET CCM_CCGR5_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR5_CLR CCM_CCGR5_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR5_TOG CCM_CCGR5_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR6 CCM_CCGR6_REG(CCM_BASE_PTR) +#define CCM_CCGR6_SET CCM_CCGR6_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR6_CLR CCM_CCGR6_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR6_TOG CCM_CCGR6_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR7 CCM_CCGR7_REG(CCM_BASE_PTR) +#define CCM_CCGR7_SET CCM_CCGR7_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR7_CLR CCM_CCGR7_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR7_TOG CCM_CCGR7_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR8 CCM_CCGR8_REG(CCM_BASE_PTR) +#define CCM_CCGR8_SET CCM_CCGR8_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR8_CLR CCM_CCGR8_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR8_TOG CCM_CCGR8_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR9 CCM_CCGR9_REG(CCM_BASE_PTR) +#define CCM_CCGR9_SET CCM_CCGR9_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR9_CLR CCM_CCGR9_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR9_TOG CCM_CCGR9_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR10 CCM_CCGR10_REG(CCM_BASE_PTR) +#define CCM_CCGR10_SET CCM_CCGR10_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR10_CLR CCM_CCGR10_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR10_TOG CCM_CCGR10_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR11 CCM_CCGR11_REG(CCM_BASE_PTR) +#define CCM_CCGR11_SET CCM_CCGR11_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR11_CLR CCM_CCGR11_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR11_TOG CCM_CCGR11_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR12 CCM_CCGR12_REG(CCM_BASE_PTR) +#define CCM_CCGR12_SET CCM_CCGR12_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR12_CLR CCM_CCGR12_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR12_TOG CCM_CCGR12_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR13 CCM_CCGR13_REG(CCM_BASE_PTR) +#define CCM_CCGR13_SET CCM_CCGR13_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR13_CLR CCM_CCGR13_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR13_TOG CCM_CCGR13_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR14 CCM_CCGR14_REG(CCM_BASE_PTR) +#define CCM_CCGR14_SET CCM_CCGR14_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR14_CLR CCM_CCGR14_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR14_TOG CCM_CCGR14_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR15 CCM_CCGR15_REG(CCM_BASE_PTR) +#define CCM_CCGR15_SET CCM_CCGR15_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR15_CLR CCM_CCGR15_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR15_TOG CCM_CCGR15_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR16 CCM_CCGR16_REG(CCM_BASE_PTR) +#define CCM_CCGR16_SET CCM_CCGR16_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR16_CLR CCM_CCGR16_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR16_TOG CCM_CCGR16_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR17 CCM_CCGR17_REG(CCM_BASE_PTR) +#define CCM_CCGR17_SET CCM_CCGR17_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR17_CLR CCM_CCGR17_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR17_TOG CCM_CCGR17_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR18 CCM_CCGR18_REG(CCM_BASE_PTR) +#define CCM_CCGR18_SET CCM_CCGR18_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR18_CLR CCM_CCGR18_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR18_TOG CCM_CCGR18_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR19 CCM_CCGR19_REG(CCM_BASE_PTR) +#define CCM_CCGR19_SET CCM_CCGR19_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR19_CLR CCM_CCGR19_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR19_TOG CCM_CCGR19_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR20 CCM_CCGR20_REG(CCM_BASE_PTR) +#define CCM_CCGR20_SET CCM_CCGR20_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR20_CLR CCM_CCGR20_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR20_TOG CCM_CCGR20_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR21 CCM_CCGR21_REG(CCM_BASE_PTR) +#define CCM_CCGR21_SET CCM_CCGR21_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR21_CLR CCM_CCGR21_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR21_TOG CCM_CCGR21_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR22 CCM_CCGR22_REG(CCM_BASE_PTR) +#define CCM_CCGR22_SET CCM_CCGR22_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR22_CLR CCM_CCGR22_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR22_TOG CCM_CCGR22_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR23 CCM_CCGR23_REG(CCM_BASE_PTR) +#define CCM_CCGR23_SET CCM_CCGR23_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR23_CLR CCM_CCGR23_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR23_TOG CCM_CCGR23_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR24 CCM_CCGR24_REG(CCM_BASE_PTR) +#define CCM_CCGR24_SET CCM_CCGR24_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR24_CLR CCM_CCGR24_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR24_TOG CCM_CCGR24_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR25 CCM_CCGR25_REG(CCM_BASE_PTR) +#define CCM_CCGR25_SET CCM_CCGR25_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR25_CLR CCM_CCGR25_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR25_TOG CCM_CCGR25_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR26 CCM_CCGR26_REG(CCM_BASE_PTR) +#define CCM_CCGR26_SET CCM_CCGR26_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR26_CLR CCM_CCGR26_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR26_TOG CCM_CCGR26_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR27 CCM_CCGR27_REG(CCM_BASE_PTR) +#define CCM_CCGR27_SET CCM_CCGR27_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR27_CLR CCM_CCGR27_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR27_TOG CCM_CCGR27_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR28 CCM_CCGR28_REG(CCM_BASE_PTR) +#define CCM_CCGR28_SET CCM_CCGR28_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR28_CLR CCM_CCGR28_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR28_TOG CCM_CCGR28_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR29 CCM_CCGR29_REG(CCM_BASE_PTR) +#define CCM_CCGR29_SET CCM_CCGR29_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR29_CLR CCM_CCGR29_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR29_TOG CCM_CCGR29_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR30 CCM_CCGR30_REG(CCM_BASE_PTR) +#define CCM_CCGR30_SET CCM_CCGR30_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR30_CLR CCM_CCGR30_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR30_TOG CCM_CCGR30_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR31 CCM_CCGR31_REG(CCM_BASE_PTR) +#define CCM_CCGR31_SET CCM_CCGR31_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR31_CLR CCM_CCGR31_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR31_TOG CCM_CCGR31_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR32 CCM_CCGR32_REG(CCM_BASE_PTR) +#define CCM_CCGR32_SET CCM_CCGR32_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR32_CLR CCM_CCGR32_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR32_TOG CCM_CCGR32_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR33 CCM_CCGR33_REG(CCM_BASE_PTR) +#define CCM_CCGR33_SET CCM_CCGR33_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR33_CLR CCM_CCGR33_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR33_TOG CCM_CCGR33_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR34 CCM_CCGR34_REG(CCM_BASE_PTR) +#define CCM_CCGR34_SET CCM_CCGR34_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR34_CLR CCM_CCGR34_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR34_TOG CCM_CCGR34_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR35 CCM_CCGR35_REG(CCM_BASE_PTR) +#define CCM_CCGR35_SET CCM_CCGR35_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR35_CLR CCM_CCGR35_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR35_TOG CCM_CCGR35_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR36 CCM_CCGR36_REG(CCM_BASE_PTR) +#define CCM_CCGR36_SET CCM_CCGR36_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR36_CLR CCM_CCGR36_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR36_TOG CCM_CCGR36_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR37 CCM_CCGR37_REG(CCM_BASE_PTR) +#define CCM_CCGR37_SET CCM_CCGR37_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR37_CLR CCM_CCGR37_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR37_TOG CCM_CCGR37_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR38 CCM_CCGR38_REG(CCM_BASE_PTR) +#define CCM_CCGR38_SET CCM_CCGR38_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR38_CLR CCM_CCGR38_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR38_TOG CCM_CCGR38_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR39 CCM_CCGR39_REG(CCM_BASE_PTR) +#define CCM_CCGR39_SET CCM_CCGR39_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR39_CLR CCM_CCGR39_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR39_TOG CCM_CCGR39_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR40 CCM_CCGR40_REG(CCM_BASE_PTR) +#define CCM_CCGR40_SET CCM_CCGR40_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR40_CLR CCM_CCGR40_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR40_TOG CCM_CCGR40_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR41 CCM_CCGR41_REG(CCM_BASE_PTR) +#define CCM_CCGR41_SET CCM_CCGR41_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR41_CLR CCM_CCGR41_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR41_TOG CCM_CCGR41_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR42 CCM_CCGR42_REG(CCM_BASE_PTR) +#define CCM_CCGR42_SET CCM_CCGR42_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR42_CLR CCM_CCGR42_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR42_TOG CCM_CCGR42_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR43 CCM_CCGR43_REG(CCM_BASE_PTR) +#define CCM_CCGR43_SET CCM_CCGR43_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR43_CLR CCM_CCGR43_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR43_TOG CCM_CCGR43_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR44 CCM_CCGR44_REG(CCM_BASE_PTR) +#define CCM_CCGR44_SET CCM_CCGR44_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR44_CLR CCM_CCGR44_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR44_TOG CCM_CCGR44_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR45 CCM_CCGR45_REG(CCM_BASE_PTR) +#define CCM_CCGR45_SET CCM_CCGR45_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR45_CLR CCM_CCGR45_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR45_TOG CCM_CCGR45_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR46 CCM_CCGR46_REG(CCM_BASE_PTR) +#define CCM_CCGR46_SET CCM_CCGR46_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR46_CLR CCM_CCGR46_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR46_TOG CCM_CCGR46_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR47 CCM_CCGR47_REG(CCM_BASE_PTR) +#define CCM_CCGR47_SET CCM_CCGR47_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR47_CLR CCM_CCGR47_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR47_TOG CCM_CCGR47_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR48 CCM_CCGR48_REG(CCM_BASE_PTR) +#define CCM_CCGR48_SET CCM_CCGR48_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR48_CLR CCM_CCGR48_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR48_TOG CCM_CCGR48_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR49 CCM_CCGR49_REG(CCM_BASE_PTR) +#define CCM_CCGR49_SET CCM_CCGR49_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR49_CLR CCM_CCGR49_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR49_TOG CCM_CCGR49_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR50 CCM_CCGR50_REG(CCM_BASE_PTR) +#define CCM_CCGR50_SET CCM_CCGR50_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR50_CLR CCM_CCGR50_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR50_TOG CCM_CCGR50_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR51 CCM_CCGR51_REG(CCM_BASE_PTR) +#define CCM_CCGR51_SET CCM_CCGR51_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR51_CLR CCM_CCGR51_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR51_TOG CCM_CCGR51_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR52 CCM_CCGR52_REG(CCM_BASE_PTR) +#define CCM_CCGR52_SET CCM_CCGR52_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR52_CLR CCM_CCGR52_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR52_TOG CCM_CCGR52_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR53 CCM_CCGR53_REG(CCM_BASE_PTR) +#define CCM_CCGR53_SET CCM_CCGR53_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR53_CLR CCM_CCGR53_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR53_TOG CCM_CCGR53_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR54 CCM_CCGR54_REG(CCM_BASE_PTR) +#define CCM_CCGR54_SET CCM_CCGR54_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR54_CLR CCM_CCGR54_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR54_TOG CCM_CCGR54_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR55 CCM_CCGR55_REG(CCM_BASE_PTR) +#define CCM_CCGR55_SET CCM_CCGR55_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR55_CLR CCM_CCGR55_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR55_TOG CCM_CCGR55_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR56 CCM_CCGR56_REG(CCM_BASE_PTR) +#define CCM_CCGR56_SET CCM_CCGR56_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR56_CLR CCM_CCGR56_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR56_TOG CCM_CCGR56_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR57 CCM_CCGR57_REG(CCM_BASE_PTR) +#define CCM_CCGR57_SET CCM_CCGR57_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR57_CLR CCM_CCGR57_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR57_TOG CCM_CCGR57_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR58 CCM_CCGR58_REG(CCM_BASE_PTR) +#define CCM_CCGR58_SET CCM_CCGR58_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR58_CLR CCM_CCGR58_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR58_TOG CCM_CCGR58_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR59 CCM_CCGR59_REG(CCM_BASE_PTR) +#define CCM_CCGR59_SET CCM_CCGR59_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR59_CLR CCM_CCGR59_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR59_TOG CCM_CCGR59_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR60 CCM_CCGR60_REG(CCM_BASE_PTR) +#define CCM_CCGR60_SET CCM_CCGR60_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR60_CLR CCM_CCGR60_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR60_TOG CCM_CCGR60_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR61 CCM_CCGR61_REG(CCM_BASE_PTR) +#define CCM_CCGR61_SET CCM_CCGR61_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR61_CLR CCM_CCGR61_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR61_TOG CCM_CCGR61_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR62 CCM_CCGR62_REG(CCM_BASE_PTR) +#define CCM_CCGR62_SET CCM_CCGR62_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR62_CLR CCM_CCGR62_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR62_TOG CCM_CCGR62_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR63 CCM_CCGR63_REG(CCM_BASE_PTR) +#define CCM_CCGR63_SET CCM_CCGR63_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR63_CLR CCM_CCGR63_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR63_TOG CCM_CCGR63_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR64 CCM_CCGR64_REG(CCM_BASE_PTR) +#define CCM_CCGR64_SET CCM_CCGR64_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR64_CLR CCM_CCGR64_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR64_TOG CCM_CCGR64_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR65 CCM_CCGR65_REG(CCM_BASE_PTR) +#define CCM_CCGR65_SET CCM_CCGR65_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR65_CLR CCM_CCGR65_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR65_TOG CCM_CCGR65_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR66 CCM_CCGR66_REG(CCM_BASE_PTR) +#define CCM_CCGR66_SET CCM_CCGR66_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR66_CLR CCM_CCGR66_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR66_TOG CCM_CCGR66_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR67 CCM_CCGR67_REG(CCM_BASE_PTR) +#define CCM_CCGR67_SET CCM_CCGR67_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR67_CLR CCM_CCGR67_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR67_TOG CCM_CCGR67_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR68 CCM_CCGR68_REG(CCM_BASE_PTR) +#define CCM_CCGR68_SET CCM_CCGR68_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR68_CLR CCM_CCGR68_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR68_TOG CCM_CCGR68_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR69 CCM_CCGR69_REG(CCM_BASE_PTR) +#define CCM_CCGR69_SET CCM_CCGR69_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR69_CLR CCM_CCGR69_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR69_TOG CCM_CCGR69_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR70 CCM_CCGR70_REG(CCM_BASE_PTR) +#define CCM_CCGR70_SET CCM_CCGR70_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR70_CLR CCM_CCGR70_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR70_TOG CCM_CCGR70_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR71 CCM_CCGR71_REG(CCM_BASE_PTR) +#define CCM_CCGR71_SET CCM_CCGR71_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR71_CLR CCM_CCGR71_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR71_TOG CCM_CCGR71_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR72 CCM_CCGR72_REG(CCM_BASE_PTR) +#define CCM_CCGR72_SET CCM_CCGR72_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR72_CLR CCM_CCGR72_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR72_TOG CCM_CCGR72_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR73 CCM_CCGR73_REG(CCM_BASE_PTR) +#define CCM_CCGR73_SET CCM_CCGR73_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR73_CLR CCM_CCGR73_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR73_TOG CCM_CCGR73_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR74 CCM_CCGR74_REG(CCM_BASE_PTR) +#define CCM_CCGR74_SET CCM_CCGR74_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR74_CLR CCM_CCGR74_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR74_TOG CCM_CCGR74_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR75 CCM_CCGR75_REG(CCM_BASE_PTR) +#define CCM_CCGR75_SET CCM_CCGR75_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR75_CLR CCM_CCGR75_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR75_TOG CCM_CCGR75_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR76 CCM_CCGR76_REG(CCM_BASE_PTR) +#define CCM_CCGR76_SET CCM_CCGR76_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR76_CLR CCM_CCGR76_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR76_TOG CCM_CCGR76_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR77 CCM_CCGR77_REG(CCM_BASE_PTR) +#define CCM_CCGR77_SET CCM_CCGR77_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR77_CLR CCM_CCGR77_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR77_TOG CCM_CCGR77_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR78 CCM_CCGR78_REG(CCM_BASE_PTR) +#define CCM_CCGR78_SET CCM_CCGR78_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR78_CLR CCM_CCGR78_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR78_TOG CCM_CCGR78_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR79 CCM_CCGR79_REG(CCM_BASE_PTR) +#define CCM_CCGR79_SET CCM_CCGR79_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR79_CLR CCM_CCGR79_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR79_TOG CCM_CCGR79_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR80 CCM_CCGR80_REG(CCM_BASE_PTR) +#define CCM_CCGR80_SET CCM_CCGR80_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR80_CLR CCM_CCGR80_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR80_TOG CCM_CCGR80_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR81 CCM_CCGR81_REG(CCM_BASE_PTR) +#define CCM_CCGR81_SET CCM_CCGR81_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR81_CLR CCM_CCGR81_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR81_TOG CCM_CCGR81_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR82 CCM_CCGR82_REG(CCM_BASE_PTR) +#define CCM_CCGR82_SET CCM_CCGR82_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR82_CLR CCM_CCGR82_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR82_TOG CCM_CCGR82_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR83 CCM_CCGR83_REG(CCM_BASE_PTR) +#define CCM_CCGR83_SET CCM_CCGR83_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR83_CLR CCM_CCGR83_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR83_TOG CCM_CCGR83_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR84 CCM_CCGR84_REG(CCM_BASE_PTR) +#define CCM_CCGR84_SET CCM_CCGR84_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR84_CLR CCM_CCGR84_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR84_TOG CCM_CCGR84_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR85 CCM_CCGR85_REG(CCM_BASE_PTR) +#define CCM_CCGR85_SET CCM_CCGR85_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR85_CLR CCM_CCGR85_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR85_TOG CCM_CCGR85_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR86 CCM_CCGR86_REG(CCM_BASE_PTR) +#define CCM_CCGR86_SET CCM_CCGR86_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR86_CLR CCM_CCGR86_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR86_TOG CCM_CCGR86_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR87 CCM_CCGR87_REG(CCM_BASE_PTR) +#define CCM_CCGR87_SET CCM_CCGR87_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR87_CLR CCM_CCGR87_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR87_TOG CCM_CCGR87_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR88 CCM_CCGR88_REG(CCM_BASE_PTR) +#define CCM_CCGR88_SET CCM_CCGR88_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR88_CLR CCM_CCGR88_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR88_TOG CCM_CCGR88_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR89 CCM_CCGR89_REG(CCM_BASE_PTR) +#define CCM_CCGR89_SET CCM_CCGR89_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR89_CLR CCM_CCGR89_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR89_TOG CCM_CCGR89_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR90 CCM_CCGR90_REG(CCM_BASE_PTR) +#define CCM_CCGR90_SET CCM_CCGR90_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR90_CLR CCM_CCGR90_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR90_TOG CCM_CCGR90_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR91 CCM_CCGR91_REG(CCM_BASE_PTR) +#define CCM_CCGR91_SET CCM_CCGR91_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR91_CLR CCM_CCGR91_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR91_TOG CCM_CCGR91_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR92 CCM_CCGR92_REG(CCM_BASE_PTR) +#define CCM_CCGR92_SET CCM_CCGR92_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR92_CLR CCM_CCGR92_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR92_TOG CCM_CCGR92_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR93 CCM_CCGR93_REG(CCM_BASE_PTR) +#define CCM_CCGR93_SET CCM_CCGR93_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR93_CLR CCM_CCGR93_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR93_TOG CCM_CCGR93_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR94 CCM_CCGR94_REG(CCM_BASE_PTR) +#define CCM_CCGR94_SET CCM_CCGR94_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR94_CLR CCM_CCGR94_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR94_TOG CCM_CCGR94_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR95 CCM_CCGR95_REG(CCM_BASE_PTR) +#define CCM_CCGR95_SET CCM_CCGR95_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR95_CLR CCM_CCGR95_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR95_TOG CCM_CCGR95_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR96 CCM_CCGR96_REG(CCM_BASE_PTR) +#define CCM_CCGR96_SET CCM_CCGR96_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR96_CLR CCM_CCGR96_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR96_TOG CCM_CCGR96_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR97 CCM_CCGR97_REG(CCM_BASE_PTR) +#define CCM_CCGR97_SET CCM_CCGR97_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR97_CLR CCM_CCGR97_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR97_TOG CCM_CCGR97_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR98 CCM_CCGR98_REG(CCM_BASE_PTR) +#define CCM_CCGR98_SET CCM_CCGR98_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR98_CLR CCM_CCGR98_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR98_TOG CCM_CCGR98_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR99 CCM_CCGR99_REG(CCM_BASE_PTR) +#define CCM_CCGR99_SET CCM_CCGR99_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR99_CLR CCM_CCGR99_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR99_TOG CCM_CCGR99_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR100 CCM_CCGR100_REG(CCM_BASE_PTR) +#define CCM_CCGR100_SET CCM_CCGR100_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR100_CLR CCM_CCGR100_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR100_TOG CCM_CCGR100_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR101 CCM_CCGR101_REG(CCM_BASE_PTR) +#define CCM_CCGR101_SET CCM_CCGR101_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR101_CLR CCM_CCGR101_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR101_TOG CCM_CCGR101_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR102 CCM_CCGR102_REG(CCM_BASE_PTR) +#define CCM_CCGR102_SET CCM_CCGR102_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR102_CLR CCM_CCGR102_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR102_TOG CCM_CCGR102_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR103 CCM_CCGR103_REG(CCM_BASE_PTR) +#define CCM_CCGR103_SET CCM_CCGR103_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR103_CLR CCM_CCGR103_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR103_TOG CCM_CCGR103_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR104 CCM_CCGR104_REG(CCM_BASE_PTR) +#define CCM_CCGR104_SET CCM_CCGR104_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR104_CLR CCM_CCGR104_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR104_TOG CCM_CCGR104_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR105 CCM_CCGR105_REG(CCM_BASE_PTR) +#define CCM_CCGR105_SET CCM_CCGR105_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR105_CLR CCM_CCGR105_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR105_TOG CCM_CCGR105_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR106 CCM_CCGR106_REG(CCM_BASE_PTR) +#define CCM_CCGR106_SET CCM_CCGR106_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR106_CLR CCM_CCGR106_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR106_TOG CCM_CCGR106_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR107 CCM_CCGR107_REG(CCM_BASE_PTR) +#define CCM_CCGR107_SET CCM_CCGR107_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR107_CLR CCM_CCGR107_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR107_TOG CCM_CCGR107_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR108 CCM_CCGR108_REG(CCM_BASE_PTR) +#define CCM_CCGR108_SET CCM_CCGR108_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR108_CLR CCM_CCGR108_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR108_TOG CCM_CCGR108_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR109 CCM_CCGR109_REG(CCM_BASE_PTR) +#define CCM_CCGR109_SET CCM_CCGR109_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR109_CLR CCM_CCGR109_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR109_TOG CCM_CCGR109_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR110 CCM_CCGR110_REG(CCM_BASE_PTR) +#define CCM_CCGR110_SET CCM_CCGR110_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR110_CLR CCM_CCGR110_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR110_TOG CCM_CCGR110_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR111 CCM_CCGR111_REG(CCM_BASE_PTR) +#define CCM_CCGR111_SET CCM_CCGR111_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR111_CLR CCM_CCGR111_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR111_TOG CCM_CCGR111_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR112 CCM_CCGR112_REG(CCM_BASE_PTR) +#define CCM_CCGR112_SET CCM_CCGR112_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR112_CLR CCM_CCGR112_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR112_TOG CCM_CCGR112_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR113 CCM_CCGR113_REG(CCM_BASE_PTR) +#define CCM_CCGR113_SET CCM_CCGR113_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR113_CLR CCM_CCGR113_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR113_TOG CCM_CCGR113_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR114 CCM_CCGR114_REG(CCM_BASE_PTR) +#define CCM_CCGR114_SET CCM_CCGR114_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR114_CLR CCM_CCGR114_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR114_TOG CCM_CCGR114_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR115 CCM_CCGR115_REG(CCM_BASE_PTR) +#define CCM_CCGR115_SET CCM_CCGR115_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR115_CLR CCM_CCGR115_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR115_TOG CCM_CCGR115_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR116 CCM_CCGR116_REG(CCM_BASE_PTR) +#define CCM_CCGR116_SET CCM_CCGR116_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR116_CLR CCM_CCGR116_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR116_TOG CCM_CCGR116_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR117 CCM_CCGR117_REG(CCM_BASE_PTR) +#define CCM_CCGR117_SET CCM_CCGR117_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR117_CLR CCM_CCGR117_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR117_TOG CCM_CCGR117_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR118 CCM_CCGR118_REG(CCM_BASE_PTR) +#define CCM_CCGR118_SET CCM_CCGR118_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR118_CLR CCM_CCGR118_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR118_TOG CCM_CCGR118_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR119 CCM_CCGR119_REG(CCM_BASE_PTR) +#define CCM_CCGR119_SET CCM_CCGR119_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR119_CLR CCM_CCGR119_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR119_TOG CCM_CCGR119_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR120 CCM_CCGR120_REG(CCM_BASE_PTR) +#define CCM_CCGR120_SET CCM_CCGR120_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR120_CLR CCM_CCGR120_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR120_TOG CCM_CCGR120_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR121 CCM_CCGR121_REG(CCM_BASE_PTR) +#define CCM_CCGR121_SET CCM_CCGR121_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR121_CLR CCM_CCGR121_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR121_TOG CCM_CCGR121_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR122 CCM_CCGR122_REG(CCM_BASE_PTR) +#define CCM_CCGR122_SET CCM_CCGR122_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR122_CLR CCM_CCGR122_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR122_TOG CCM_CCGR122_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR123 CCM_CCGR123_REG(CCM_BASE_PTR) +#define CCM_CCGR123_SET CCM_CCGR123_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR123_CLR CCM_CCGR123_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR123_TOG CCM_CCGR123_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR124 CCM_CCGR124_REG(CCM_BASE_PTR) +#define CCM_CCGR124_SET CCM_CCGR124_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR124_CLR CCM_CCGR124_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR124_TOG CCM_CCGR124_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR125 CCM_CCGR125_REG(CCM_BASE_PTR) +#define CCM_CCGR125_SET CCM_CCGR125_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR125_CLR CCM_CCGR125_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR125_TOG CCM_CCGR125_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR126 CCM_CCGR126_REG(CCM_BASE_PTR) +#define CCM_CCGR126_SET CCM_CCGR126_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR126_CLR CCM_CCGR126_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR126_TOG CCM_CCGR126_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR127 CCM_CCGR127_REG(CCM_BASE_PTR) +#define CCM_CCGR127_SET CCM_CCGR127_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR127_CLR CCM_CCGR127_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR127_TOG CCM_CCGR127_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR128 CCM_CCGR128_REG(CCM_BASE_PTR) +#define CCM_CCGR128_SET CCM_CCGR128_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR128_CLR CCM_CCGR128_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR128_TOG CCM_CCGR128_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR129 CCM_CCGR129_REG(CCM_BASE_PTR) +#define CCM_CCGR129_SET CCM_CCGR129_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR129_CLR CCM_CCGR129_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR129_TOG CCM_CCGR129_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR130 CCM_CCGR130_REG(CCM_BASE_PTR) +#define CCM_CCGR130_SET CCM_CCGR130_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR130_CLR CCM_CCGR130_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR130_TOG CCM_CCGR130_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR131 CCM_CCGR131_REG(CCM_BASE_PTR) +#define CCM_CCGR131_SET CCM_CCGR131_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR131_CLR CCM_CCGR131_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR131_TOG CCM_CCGR131_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR132 CCM_CCGR132_REG(CCM_BASE_PTR) +#define CCM_CCGR132_SET CCM_CCGR132_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR132_CLR CCM_CCGR132_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR132_TOG CCM_CCGR132_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR133 CCM_CCGR133_REG(CCM_BASE_PTR) +#define CCM_CCGR133_SET CCM_CCGR133_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR133_CLR CCM_CCGR133_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR133_TOG CCM_CCGR133_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR134 CCM_CCGR134_REG(CCM_BASE_PTR) +#define CCM_CCGR134_SET CCM_CCGR134_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR134_CLR CCM_CCGR134_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR134_TOG CCM_CCGR134_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR135 CCM_CCGR135_REG(CCM_BASE_PTR) +#define CCM_CCGR135_SET CCM_CCGR135_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR135_CLR CCM_CCGR135_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR135_TOG CCM_CCGR135_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR136 CCM_CCGR136_REG(CCM_BASE_PTR) +#define CCM_CCGR136_SET CCM_CCGR136_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR136_CLR CCM_CCGR136_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR136_TOG CCM_CCGR136_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR137 CCM_CCGR137_REG(CCM_BASE_PTR) +#define CCM_CCGR137_SET CCM_CCGR137_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR137_CLR CCM_CCGR137_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR137_TOG CCM_CCGR137_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR138 CCM_CCGR138_REG(CCM_BASE_PTR) +#define CCM_CCGR138_SET CCM_CCGR138_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR138_CLR CCM_CCGR138_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR138_TOG CCM_CCGR138_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR139 CCM_CCGR139_REG(CCM_BASE_PTR) +#define CCM_CCGR139_SET CCM_CCGR139_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR139_CLR CCM_CCGR139_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR139_TOG CCM_CCGR139_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR140 CCM_CCGR140_REG(CCM_BASE_PTR) +#define CCM_CCGR140_SET CCM_CCGR140_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR140_CLR CCM_CCGR140_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR140_TOG CCM_CCGR140_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR141 CCM_CCGR141_REG(CCM_BASE_PTR) +#define CCM_CCGR141_SET CCM_CCGR141_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR141_CLR CCM_CCGR141_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR141_TOG CCM_CCGR141_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR142 CCM_CCGR142_REG(CCM_BASE_PTR) +#define CCM_CCGR142_SET CCM_CCGR142_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR142_CLR CCM_CCGR142_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR142_TOG CCM_CCGR142_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR143 CCM_CCGR143_REG(CCM_BASE_PTR) +#define CCM_CCGR143_SET CCM_CCGR143_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR143_CLR CCM_CCGR143_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR143_TOG CCM_CCGR143_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR144 CCM_CCGR144_REG(CCM_BASE_PTR) +#define CCM_CCGR144_SET CCM_CCGR144_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR144_CLR CCM_CCGR144_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR144_TOG CCM_CCGR144_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR145 CCM_CCGR145_REG(CCM_BASE_PTR) +#define CCM_CCGR145_SET CCM_CCGR145_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR145_CLR CCM_CCGR145_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR145_TOG CCM_CCGR145_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR146 CCM_CCGR146_REG(CCM_BASE_PTR) +#define CCM_CCGR146_SET CCM_CCGR146_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR146_CLR CCM_CCGR146_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR146_TOG CCM_CCGR146_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR147 CCM_CCGR147_REG(CCM_BASE_PTR) +#define CCM_CCGR147_SET CCM_CCGR147_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR147_CLR CCM_CCGR147_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR147_TOG CCM_CCGR147_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR148 CCM_CCGR148_REG(CCM_BASE_PTR) +#define CCM_CCGR148_SET CCM_CCGR148_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR148_CLR CCM_CCGR148_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR148_TOG CCM_CCGR148_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR149 CCM_CCGR149_REG(CCM_BASE_PTR) +#define CCM_CCGR149_SET CCM_CCGR149_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR149_CLR CCM_CCGR149_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR149_TOG CCM_CCGR149_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR150 CCM_CCGR150_REG(CCM_BASE_PTR) +#define CCM_CCGR150_SET CCM_CCGR150_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR150_CLR CCM_CCGR150_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR150_TOG CCM_CCGR150_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR151 CCM_CCGR151_REG(CCM_BASE_PTR) +#define CCM_CCGR151_SET CCM_CCGR151_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR151_CLR CCM_CCGR151_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR151_TOG CCM_CCGR151_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR152 CCM_CCGR152_REG(CCM_BASE_PTR) +#define CCM_CCGR152_SET CCM_CCGR152_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR152_CLR CCM_CCGR152_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR152_TOG CCM_CCGR152_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR153 CCM_CCGR153_REG(CCM_BASE_PTR) +#define CCM_CCGR153_SET CCM_CCGR153_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR153_CLR CCM_CCGR153_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR153_TOG CCM_CCGR153_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR154 CCM_CCGR154_REG(CCM_BASE_PTR) +#define CCM_CCGR154_SET CCM_CCGR154_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR154_CLR CCM_CCGR154_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR154_TOG CCM_CCGR154_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR155 CCM_CCGR155_REG(CCM_BASE_PTR) +#define CCM_CCGR155_SET CCM_CCGR155_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR155_CLR CCM_CCGR155_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR155_TOG CCM_CCGR155_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR156 CCM_CCGR156_REG(CCM_BASE_PTR) +#define CCM_CCGR156_SET CCM_CCGR156_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR156_CLR CCM_CCGR156_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR156_TOG CCM_CCGR156_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR157 CCM_CCGR157_REG(CCM_BASE_PTR) +#define CCM_CCGR157_SET CCM_CCGR157_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR157_CLR CCM_CCGR157_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR157_TOG CCM_CCGR157_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR158 CCM_CCGR158_REG(CCM_BASE_PTR) +#define CCM_CCGR158_SET CCM_CCGR158_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR158_CLR CCM_CCGR158_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR158_TOG CCM_CCGR158_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR159 CCM_CCGR159_REG(CCM_BASE_PTR) +#define CCM_CCGR159_SET CCM_CCGR159_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR159_CLR CCM_CCGR159_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR159_TOG CCM_CCGR159_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR160 CCM_CCGR160_REG(CCM_BASE_PTR) +#define CCM_CCGR160_SET CCM_CCGR160_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR160_CLR CCM_CCGR160_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR160_TOG CCM_CCGR160_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR161 CCM_CCGR161_REG(CCM_BASE_PTR) +#define CCM_CCGR161_SET CCM_CCGR161_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR161_CLR CCM_CCGR161_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR161_TOG CCM_CCGR161_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR162 CCM_CCGR162_REG(CCM_BASE_PTR) +#define CCM_CCGR162_SET CCM_CCGR162_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR162_CLR CCM_CCGR162_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR162_TOG CCM_CCGR162_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR163 CCM_CCGR163_REG(CCM_BASE_PTR) +#define CCM_CCGR163_SET CCM_CCGR163_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR163_CLR CCM_CCGR163_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR163_TOG CCM_CCGR163_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR164 CCM_CCGR164_REG(CCM_BASE_PTR) +#define CCM_CCGR164_SET CCM_CCGR164_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR164_CLR CCM_CCGR164_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR164_TOG CCM_CCGR164_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR165 CCM_CCGR165_REG(CCM_BASE_PTR) +#define CCM_CCGR165_SET CCM_CCGR165_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR165_CLR CCM_CCGR165_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR165_TOG CCM_CCGR165_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR166 CCM_CCGR166_REG(CCM_BASE_PTR) +#define CCM_CCGR166_SET CCM_CCGR166_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR166_CLR CCM_CCGR166_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR166_TOG CCM_CCGR166_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR167 CCM_CCGR167_REG(CCM_BASE_PTR) +#define CCM_CCGR167_SET CCM_CCGR167_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR167_CLR CCM_CCGR167_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR167_TOG CCM_CCGR167_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR168 CCM_CCGR168_REG(CCM_BASE_PTR) +#define CCM_CCGR168_SET CCM_CCGR168_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR168_CLR CCM_CCGR168_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR168_TOG CCM_CCGR168_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR169 CCM_CCGR169_REG(CCM_BASE_PTR) +#define CCM_CCGR169_SET CCM_CCGR169_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR169_CLR CCM_CCGR169_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR169_TOG CCM_CCGR169_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR170 CCM_CCGR170_REG(CCM_BASE_PTR) +#define CCM_CCGR170_SET CCM_CCGR170_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR170_CLR CCM_CCGR170_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR170_TOG CCM_CCGR170_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR171 CCM_CCGR171_REG(CCM_BASE_PTR) +#define CCM_CCGR171_SET CCM_CCGR171_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR171_CLR CCM_CCGR171_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR171_TOG CCM_CCGR171_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR172 CCM_CCGR172_REG(CCM_BASE_PTR) +#define CCM_CCGR172_SET CCM_CCGR172_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR172_CLR CCM_CCGR172_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR172_TOG CCM_CCGR172_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR173 CCM_CCGR173_REG(CCM_BASE_PTR) +#define CCM_CCGR173_SET CCM_CCGR173_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR173_CLR CCM_CCGR173_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR173_TOG CCM_CCGR173_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR174 CCM_CCGR174_REG(CCM_BASE_PTR) +#define CCM_CCGR174_SET CCM_CCGR174_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR174_CLR CCM_CCGR174_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR174_TOG CCM_CCGR174_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR175 CCM_CCGR175_REG(CCM_BASE_PTR) +#define CCM_CCGR175_SET CCM_CCGR175_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR175_CLR CCM_CCGR175_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR175_TOG CCM_CCGR175_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR176 CCM_CCGR176_REG(CCM_BASE_PTR) +#define CCM_CCGR176_SET CCM_CCGR176_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR176_CLR CCM_CCGR176_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR176_TOG CCM_CCGR176_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR177 CCM_CCGR177_REG(CCM_BASE_PTR) +#define CCM_CCGR177_SET CCM_CCGR177_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR177_CLR CCM_CCGR177_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR177_TOG CCM_CCGR177_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR178 CCM_CCGR178_REG(CCM_BASE_PTR) +#define CCM_CCGR178_SET CCM_CCGR178_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR178_CLR CCM_CCGR178_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR178_TOG CCM_CCGR178_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR179 CCM_CCGR179_REG(CCM_BASE_PTR) +#define CCM_CCGR179_SET CCM_CCGR179_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR179_CLR CCM_CCGR179_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR179_TOG CCM_CCGR179_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR180 CCM_CCGR180_REG(CCM_BASE_PTR) +#define CCM_CCGR180_SET CCM_CCGR180_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR180_CLR CCM_CCGR180_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR180_TOG CCM_CCGR180_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR181 CCM_CCGR181_REG(CCM_BASE_PTR) +#define CCM_CCGR181_SET CCM_CCGR181_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR181_CLR CCM_CCGR181_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR181_TOG CCM_CCGR181_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR182 CCM_CCGR182_REG(CCM_BASE_PTR) +#define CCM_CCGR182_SET CCM_CCGR182_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR182_CLR CCM_CCGR182_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR182_TOG CCM_CCGR182_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR183 CCM_CCGR183_REG(CCM_BASE_PTR) +#define CCM_CCGR183_SET CCM_CCGR183_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR183_CLR CCM_CCGR183_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR183_TOG CCM_CCGR183_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR184 CCM_CCGR184_REG(CCM_BASE_PTR) +#define CCM_CCGR184_SET CCM_CCGR184_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR184_CLR CCM_CCGR184_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR184_TOG CCM_CCGR184_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR185 CCM_CCGR185_REG(CCM_BASE_PTR) +#define CCM_CCGR185_SET CCM_CCGR185_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR185_CLR CCM_CCGR185_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR185_TOG CCM_CCGR185_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR186 CCM_CCGR186_REG(CCM_BASE_PTR) +#define CCM_CCGR186_SET CCM_CCGR186_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR186_CLR CCM_CCGR186_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR186_TOG CCM_CCGR186_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR187 CCM_CCGR187_REG(CCM_BASE_PTR) +#define CCM_CCGR187_SET CCM_CCGR187_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR187_CLR CCM_CCGR187_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR187_TOG CCM_CCGR187_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR188 CCM_CCGR188_REG(CCM_BASE_PTR) +#define CCM_CCGR188_SET CCM_CCGR188_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR188_CLR CCM_CCGR188_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR188_TOG CCM_CCGR188_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR189 CCM_CCGR189_REG(CCM_BASE_PTR) +#define CCM_CCGR189_SET CCM_CCGR189_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR189_CLR CCM_CCGR189_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR189_TOG CCM_CCGR189_TOG_REG(CCM_BASE_PTR) +#define CCM_CCGR190 CCM_CCGR190_REG(CCM_BASE_PTR) +#define CCM_CCGR190_SET CCM_CCGR190_SET_REG(CCM_BASE_PTR) +#define CCM_CCGR190_CLR CCM_CCGR190_CLR_REG(CCM_BASE_PTR) +#define CCM_CCGR190_TOG CCM_CCGR190_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT0 CCM_TARGET_ROOT0_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT0_SET CCM_TARGET_ROOT0_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT0_CLR CCM_TARGET_ROOT0_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT0_TOG CCM_TARGET_ROOT0_TOG_REG(CCM_BASE_PTR) +#define CCM_POST0 CCM_POST0_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT0_SET CCM_POST_ROOT0_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT0_CLR CCM_POST_ROOT0_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT0_TOG CCM_POST_ROOT0_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE0 CCM_PRE0_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT0_SET CCM_PRE_ROOT0_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT0_CLR CCM_PRE_ROOT0_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT0_TOG CCM_PRE_ROOT0_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL0 CCM_ACCESS_CTRL0_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT0_SET CCM_ACCESS_CTRL0_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT0_CLR CCM_ACCESS_CTRL0_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT0_TOG CCM_ACCESS_CTRL0_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT1 CCM_TARGET_ROOT1_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT1_SET CCM_TARGET_ROOT1_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT1_CLR CCM_TARGET_ROOT1_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT1_TOG CCM_TARGET_ROOT1_TOG_REG(CCM_BASE_PTR) +#define CCM_POST1 CCM_POST1_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT1_SET CCM_POST_ROOT1_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT1_CLR CCM_POST_ROOT1_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT1_TOG CCM_POST_ROOT1_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE1 CCM_PRE1_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT1_SET CCM_PRE_ROOT1_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT1_CLR CCM_PRE_ROOT1_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT1_TOG CCM_PRE_ROOT1_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL1 CCM_ACCESS_CTRL1_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT1_SET CCM_ACCESS_CTRL1_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT1_CLR CCM_ACCESS_CTRL1_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT1_TOG CCM_ACCESS_CTRL1_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT2 CCM_TARGET_ROOT2_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT2_SET CCM_TARGET_ROOT2_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT2_CLR CCM_TARGET_ROOT2_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT2_TOG CCM_TARGET_ROOT2_TOG_REG(CCM_BASE_PTR) +#define CCM_POST2 CCM_POST2_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT2_SET CCM_POST_ROOT2_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT2_CLR CCM_POST_ROOT2_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT2_TOG CCM_POST_ROOT2_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE2 CCM_PRE2_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT2_SET CCM_PRE_ROOT2_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT2_CLR CCM_PRE_ROOT2_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT2_TOG CCM_PRE_ROOT2_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL2 CCM_ACCESS_CTRL2_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT2_SET CCM_ACCESS_CTRL2_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT2_CLR CCM_ACCESS_CTRL2_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT2_TOG CCM_ACCESS_CTRL2_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT3 CCM_TARGET_ROOT3_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT3_SET CCM_TARGET_ROOT3_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT3_CLR CCM_TARGET_ROOT3_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT3_TOG CCM_TARGET_ROOT3_TOG_REG(CCM_BASE_PTR) +#define CCM_POST3 CCM_POST3_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT3_SET CCM_POST_ROOT3_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT3_CLR CCM_POST_ROOT3_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT3_TOG CCM_POST_ROOT3_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE3 CCM_PRE3_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT3_SET CCM_PRE_ROOT3_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT3_CLR CCM_PRE_ROOT3_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT3_TOG CCM_PRE_ROOT3_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL3 CCM_ACCESS_CTRL3_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT3_SET CCM_ACCESS_CTRL3_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT3_CLR CCM_ACCESS_CTRL3_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT3_TOG CCM_ACCESS_CTRL3_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT4 CCM_TARGET_ROOT4_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT4_SET CCM_TARGET_ROOT4_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT4_CLR CCM_TARGET_ROOT4_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT4_TOG CCM_TARGET_ROOT4_TOG_REG(CCM_BASE_PTR) +#define CCM_POST4 CCM_POST4_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT4_SET CCM_POST_ROOT4_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT4_CLR CCM_POST_ROOT4_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT4_TOG CCM_POST_ROOT4_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE4 CCM_PRE4_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT4_SET CCM_PRE_ROOT4_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT4_CLR CCM_PRE_ROOT4_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT4_TOG CCM_PRE_ROOT4_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL4 CCM_ACCESS_CTRL4_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT4_SET CCM_ACCESS_CTRL4_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT4_CLR CCM_ACCESS_CTRL4_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT4_TOG CCM_ACCESS_CTRL4_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT5 CCM_TARGET_ROOT5_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT5_SET CCM_TARGET_ROOT5_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT5_CLR CCM_TARGET_ROOT5_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT5_TOG CCM_TARGET_ROOT5_TOG_REG(CCM_BASE_PTR) +#define CCM_POST5 CCM_POST5_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT5_SET CCM_POST_ROOT5_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT5_CLR CCM_POST_ROOT5_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT5_TOG CCM_POST_ROOT5_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE5 CCM_PRE5_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT5_SET CCM_PRE_ROOT5_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT5_CLR CCM_PRE_ROOT5_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT5_TOG CCM_PRE_ROOT5_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL5 CCM_ACCESS_CTRL5_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT5_SET CCM_ACCESS_CTRL5_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT5_CLR CCM_ACCESS_CTRL5_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT5_TOG CCM_ACCESS_CTRL5_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT6 CCM_TARGET_ROOT6_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT6_SET CCM_TARGET_ROOT6_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT6_CLR CCM_TARGET_ROOT6_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT6_TOG CCM_TARGET_ROOT6_TOG_REG(CCM_BASE_PTR) +#define CCM_POST6 CCM_POST6_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT6_SET CCM_POST_ROOT6_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT6_CLR CCM_POST_ROOT6_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT6_TOG CCM_POST_ROOT6_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE6 CCM_PRE6_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT6_SET CCM_PRE_ROOT6_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT6_CLR CCM_PRE_ROOT6_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT6_TOG CCM_PRE_ROOT6_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL6 CCM_ACCESS_CTRL6_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT6_SET CCM_ACCESS_CTRL6_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT6_CLR CCM_ACCESS_CTRL6_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT6_TOG CCM_ACCESS_CTRL6_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT7 CCM_TARGET_ROOT7_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT7_SET CCM_TARGET_ROOT7_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT7_CLR CCM_TARGET_ROOT7_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT7_TOG CCM_TARGET_ROOT7_TOG_REG(CCM_BASE_PTR) +#define CCM_POST7 CCM_POST7_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT7_SET CCM_POST_ROOT7_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT7_CLR CCM_POST_ROOT7_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT7_TOG CCM_POST_ROOT7_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE7 CCM_PRE7_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT7_SET CCM_PRE_ROOT7_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT7_CLR CCM_PRE_ROOT7_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT7_TOG CCM_PRE_ROOT7_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL7 CCM_ACCESS_CTRL7_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT7_SET CCM_ACCESS_CTRL7_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT7_CLR CCM_ACCESS_CTRL7_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT7_TOG CCM_ACCESS_CTRL7_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT8 CCM_TARGET_ROOT8_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT8_SET CCM_TARGET_ROOT8_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT8_CLR CCM_TARGET_ROOT8_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT8_TOG CCM_TARGET_ROOT8_TOG_REG(CCM_BASE_PTR) +#define CCM_POST8 CCM_POST8_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT8_SET CCM_POST_ROOT8_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT8_CLR CCM_POST_ROOT8_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT8_TOG CCM_POST_ROOT8_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE8 CCM_PRE8_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT8_SET CCM_PRE_ROOT8_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT8_CLR CCM_PRE_ROOT8_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT8_TOG CCM_PRE_ROOT8_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL8 CCM_ACCESS_CTRL8_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT8_SET CCM_ACCESS_CTRL8_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT8_CLR CCM_ACCESS_CTRL8_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT8_TOG CCM_ACCESS_CTRL8_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT9 CCM_TARGET_ROOT9_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT9_SET CCM_TARGET_ROOT9_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT9_CLR CCM_TARGET_ROOT9_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT9_TOG CCM_TARGET_ROOT9_TOG_REG(CCM_BASE_PTR) +#define CCM_POST9 CCM_POST9_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT9_SET CCM_POST_ROOT9_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT9_CLR CCM_POST_ROOT9_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT9_TOG CCM_POST_ROOT9_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE9 CCM_PRE9_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT9_SET CCM_PRE_ROOT9_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT9_CLR CCM_PRE_ROOT9_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT9_TOG CCM_PRE_ROOT9_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL9 CCM_ACCESS_CTRL9_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT9_SET CCM_ACCESS_CTRL9_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT9_CLR CCM_ACCESS_CTRL9_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT9_TOG CCM_ACCESS_CTRL9_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT10 CCM_TARGET_ROOT10_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT10_SET CCM_TARGET_ROOT10_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT10_CLR CCM_TARGET_ROOT10_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT10_TOG CCM_TARGET_ROOT10_TOG_REG(CCM_BASE_PTR) +#define CCM_POST10 CCM_POST10_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT10_SET CCM_POST_ROOT10_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT10_CLR CCM_POST_ROOT10_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT10_TOG CCM_POST_ROOT10_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE10 CCM_PRE10_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT10_SET CCM_PRE_ROOT10_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT10_CLR CCM_PRE_ROOT10_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT10_TOG CCM_PRE_ROOT10_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL10 CCM_ACCESS_CTRL10_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT10_SET CCM_ACCESS_CTRL10_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT10_CLR CCM_ACCESS_CTRL10_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT10_TOG CCM_ACCESS_CTRL10_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT11 CCM_TARGET_ROOT11_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT11_SET CCM_TARGET_ROOT11_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT11_CLR CCM_TARGET_ROOT11_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT11_TOG CCM_TARGET_ROOT11_TOG_REG(CCM_BASE_PTR) +#define CCM_POST11 CCM_POST11_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT11_SET CCM_POST_ROOT11_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT11_CLR CCM_POST_ROOT11_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT11_TOG CCM_POST_ROOT11_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE11 CCM_PRE11_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT11_SET CCM_PRE_ROOT11_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT11_CLR CCM_PRE_ROOT11_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT11_TOG CCM_PRE_ROOT11_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL11 CCM_ACCESS_CTRL11_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT11_SET CCM_ACCESS_CTRL11_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT11_CLR CCM_ACCESS_CTRL11_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT11_TOG CCM_ACCESS_CTRL11_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT12 CCM_TARGET_ROOT12_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT12_SET CCM_TARGET_ROOT12_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT12_CLR CCM_TARGET_ROOT12_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT12_TOG CCM_TARGET_ROOT12_TOG_REG(CCM_BASE_PTR) +#define CCM_POST12 CCM_POST12_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT12_SET CCM_POST_ROOT12_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT12_CLR CCM_POST_ROOT12_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT12_TOG CCM_POST_ROOT12_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE12 CCM_PRE12_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT12_SET CCM_PRE_ROOT12_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT12_CLR CCM_PRE_ROOT12_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT12_TOG CCM_PRE_ROOT12_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL12 CCM_ACCESS_CTRL12_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT12_SET CCM_ACCESS_CTRL12_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT12_CLR CCM_ACCESS_CTRL12_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT12_TOG CCM_ACCESS_CTRL12_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT13 CCM_TARGET_ROOT13_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT13_SET CCM_TARGET_ROOT13_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT13_CLR CCM_TARGET_ROOT13_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT13_TOG CCM_TARGET_ROOT13_TOG_REG(CCM_BASE_PTR) +#define CCM_POST13 CCM_POST13_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT13_SET CCM_POST_ROOT13_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT13_CLR CCM_POST_ROOT13_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT13_TOG CCM_POST_ROOT13_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE13 CCM_PRE13_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT13_SET CCM_PRE_ROOT13_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT13_CLR CCM_PRE_ROOT13_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT13_TOG CCM_PRE_ROOT13_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL13 CCM_ACCESS_CTRL13_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT13_SET CCM_ACCESS_CTRL13_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT13_CLR CCM_ACCESS_CTRL13_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT13_TOG CCM_ACCESS_CTRL13_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT14 CCM_TARGET_ROOT14_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT14_SET CCM_TARGET_ROOT14_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT14_CLR CCM_TARGET_ROOT14_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT14_TOG CCM_TARGET_ROOT14_TOG_REG(CCM_BASE_PTR) +#define CCM_POST14 CCM_POST14_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT14_SET CCM_POST_ROOT14_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT14_CLR CCM_POST_ROOT14_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT14_TOG CCM_POST_ROOT14_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE14 CCM_PRE14_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT14_SET CCM_PRE_ROOT14_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT14_CLR CCM_PRE_ROOT14_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT14_TOG CCM_PRE_ROOT14_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL14 CCM_ACCESS_CTRL14_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT14_SET CCM_ACCESS_CTRL14_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT14_CLR CCM_ACCESS_CTRL14_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT14_TOG CCM_ACCESS_CTRL14_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT15 CCM_TARGET_ROOT15_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT15_SET CCM_TARGET_ROOT15_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT15_CLR CCM_TARGET_ROOT15_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT15_TOG CCM_TARGET_ROOT15_TOG_REG(CCM_BASE_PTR) +#define CCM_POST15 CCM_POST15_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT15_SET CCM_POST_ROOT15_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT15_CLR CCM_POST_ROOT15_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT15_TOG CCM_POST_ROOT15_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE15 CCM_PRE15_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT15_SET CCM_PRE_ROOT15_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT15_CLR CCM_PRE_ROOT15_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT15_TOG CCM_PRE_ROOT15_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL15 CCM_ACCESS_CTRL15_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT15_SET CCM_ACCESS_CTRL15_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT15_CLR CCM_ACCESS_CTRL15_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT15_TOG CCM_ACCESS_CTRL15_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT16 CCM_TARGET_ROOT16_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT16_SET CCM_TARGET_ROOT16_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT16_CLR CCM_TARGET_ROOT16_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT16_TOG CCM_TARGET_ROOT16_TOG_REG(CCM_BASE_PTR) +#define CCM_POST16 CCM_POST16_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT16_SET CCM_POST_ROOT16_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT16_CLR CCM_POST_ROOT16_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT16_TOG CCM_POST_ROOT16_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE16 CCM_PRE16_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT16_SET CCM_PRE_ROOT16_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT16_CLR CCM_PRE_ROOT16_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT16_TOG CCM_PRE_ROOT16_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL16 CCM_ACCESS_CTRL16_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT16_SET CCM_ACCESS_CTRL16_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT16_CLR CCM_ACCESS_CTRL16_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT16_TOG CCM_ACCESS_CTRL16_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT17 CCM_TARGET_ROOT17_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT17_SET CCM_TARGET_ROOT17_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT17_CLR CCM_TARGET_ROOT17_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT17_TOG CCM_TARGET_ROOT17_TOG_REG(CCM_BASE_PTR) +#define CCM_POST17 CCM_POST17_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT17_SET CCM_POST_ROOT17_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT17_CLR CCM_POST_ROOT17_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT17_TOG CCM_POST_ROOT17_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE17 CCM_PRE17_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT17_SET CCM_PRE_ROOT17_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT17_CLR CCM_PRE_ROOT17_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT17_TOG CCM_PRE_ROOT17_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL17 CCM_ACCESS_CTRL17_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT17_SET CCM_ACCESS_CTRL17_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT17_CLR CCM_ACCESS_CTRL17_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT17_TOG CCM_ACCESS_CTRL17_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT18 CCM_TARGET_ROOT18_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT18_SET CCM_TARGET_ROOT18_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT18_CLR CCM_TARGET_ROOT18_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT18_TOG CCM_TARGET_ROOT18_TOG_REG(CCM_BASE_PTR) +#define CCM_POST18 CCM_POST18_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT18_SET CCM_POST_ROOT18_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT18_CLR CCM_POST_ROOT18_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT18_TOG CCM_POST_ROOT18_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE18 CCM_PRE18_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT18_SET CCM_PRE_ROOT18_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT18_CLR CCM_PRE_ROOT18_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT18_TOG CCM_PRE_ROOT18_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL18 CCM_ACCESS_CTRL18_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT18_SET CCM_ACCESS_CTRL18_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT18_CLR CCM_ACCESS_CTRL18_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT18_TOG CCM_ACCESS_CTRL18_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT19 CCM_TARGET_ROOT19_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT19_SET CCM_TARGET_ROOT19_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT19_CLR CCM_TARGET_ROOT19_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT19_TOG CCM_TARGET_ROOT19_TOG_REG(CCM_BASE_PTR) +#define CCM_POST19 CCM_POST19_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT19_SET CCM_POST_ROOT19_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT19_CLR CCM_POST_ROOT19_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT19_TOG CCM_POST_ROOT19_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE19 CCM_PRE19_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT19_SET CCM_PRE_ROOT19_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT19_CLR CCM_PRE_ROOT19_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT19_TOG CCM_PRE_ROOT19_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL19 CCM_ACCESS_CTRL19_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT19_SET CCM_ACCESS_CTRL19_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT19_CLR CCM_ACCESS_CTRL19_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT19_TOG CCM_ACCESS_CTRL19_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT20 CCM_TARGET_ROOT20_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT20_SET CCM_TARGET_ROOT20_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT20_CLR CCM_TARGET_ROOT20_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT20_TOG CCM_TARGET_ROOT20_TOG_REG(CCM_BASE_PTR) +#define CCM_POST20 CCM_POST20_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT20_SET CCM_POST_ROOT20_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT20_CLR CCM_POST_ROOT20_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT20_TOG CCM_POST_ROOT20_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE20 CCM_PRE20_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT20_SET CCM_PRE_ROOT20_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT20_CLR CCM_PRE_ROOT20_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT20_TOG CCM_PRE_ROOT20_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL20 CCM_ACCESS_CTRL20_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT20_SET CCM_ACCESS_CTRL20_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT20_CLR CCM_ACCESS_CTRL20_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT20_TOG CCM_ACCESS_CTRL20_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT21 CCM_TARGET_ROOT21_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT21_SET CCM_TARGET_ROOT21_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT21_CLR CCM_TARGET_ROOT21_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT21_TOG CCM_TARGET_ROOT21_TOG_REG(CCM_BASE_PTR) +#define CCM_POST21 CCM_POST21_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT21_SET CCM_POST_ROOT21_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT21_CLR CCM_POST_ROOT21_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT21_TOG CCM_POST_ROOT21_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE21 CCM_PRE21_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT21_SET CCM_PRE_ROOT21_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT21_CLR CCM_PRE_ROOT21_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT21_TOG CCM_PRE_ROOT21_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL21 CCM_ACCESS_CTRL21_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT21_SET CCM_ACCESS_CTRL21_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT21_CLR CCM_ACCESS_CTRL21_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT21_TOG CCM_ACCESS_CTRL21_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT22 CCM_TARGET_ROOT22_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT22_SET CCM_TARGET_ROOT22_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT22_CLR CCM_TARGET_ROOT22_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT22_TOG CCM_TARGET_ROOT22_TOG_REG(CCM_BASE_PTR) +#define CCM_POST22 CCM_POST22_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT22_SET CCM_POST_ROOT22_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT22_CLR CCM_POST_ROOT22_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT22_TOG CCM_POST_ROOT22_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE22 CCM_PRE22_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT22_SET CCM_PRE_ROOT22_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT22_CLR CCM_PRE_ROOT22_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT22_TOG CCM_PRE_ROOT22_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL22 CCM_ACCESS_CTRL22_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT22_SET CCM_ACCESS_CTRL22_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT22_CLR CCM_ACCESS_CTRL22_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT22_TOG CCM_ACCESS_CTRL22_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT23 CCM_TARGET_ROOT23_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT23_SET CCM_TARGET_ROOT23_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT23_CLR CCM_TARGET_ROOT23_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT23_TOG CCM_TARGET_ROOT23_TOG_REG(CCM_BASE_PTR) +#define CCM_POST23 CCM_POST23_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT23_SET CCM_POST_ROOT23_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT23_CLR CCM_POST_ROOT23_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT23_TOG CCM_POST_ROOT23_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE23 CCM_PRE23_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT23_SET CCM_PRE_ROOT23_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT23_CLR CCM_PRE_ROOT23_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT23_TOG CCM_PRE_ROOT23_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL23 CCM_ACCESS_CTRL23_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT23_SET CCM_ACCESS_CTRL23_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT23_CLR CCM_ACCESS_CTRL23_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT23_TOG CCM_ACCESS_CTRL23_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT24 CCM_TARGET_ROOT24_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT24_SET CCM_TARGET_ROOT24_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT24_CLR CCM_TARGET_ROOT24_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT24_TOG CCM_TARGET_ROOT24_TOG_REG(CCM_BASE_PTR) +#define CCM_POST24 CCM_POST24_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT24_SET CCM_POST_ROOT24_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT24_CLR CCM_POST_ROOT24_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT24_TOG CCM_POST_ROOT24_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE24 CCM_PRE24_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT24_SET CCM_PRE_ROOT24_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT24_CLR CCM_PRE_ROOT24_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT24_TOG CCM_PRE_ROOT24_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL24 CCM_ACCESS_CTRL24_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT24_SET CCM_ACCESS_CTRL24_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT24_CLR CCM_ACCESS_CTRL24_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT24_TOG CCM_ACCESS_CTRL24_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT25 CCM_TARGET_ROOT25_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT25_SET CCM_TARGET_ROOT25_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT25_CLR CCM_TARGET_ROOT25_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT25_TOG CCM_TARGET_ROOT25_TOG_REG(CCM_BASE_PTR) +#define CCM_POST25 CCM_POST25_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT25_SET CCM_POST_ROOT25_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT25_CLR CCM_POST_ROOT25_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT25_TOG CCM_POST_ROOT25_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE25 CCM_PRE25_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT25_SET CCM_PRE_ROOT25_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT25_CLR CCM_PRE_ROOT25_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT25_TOG CCM_PRE_ROOT25_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL25 CCM_ACCESS_CTRL25_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT25_SET CCM_ACCESS_CTRL25_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT25_CLR CCM_ACCESS_CTRL25_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT25_TOG CCM_ACCESS_CTRL25_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT26 CCM_TARGET_ROOT26_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT26_SET CCM_TARGET_ROOT26_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT26_CLR CCM_TARGET_ROOT26_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT26_TOG CCM_TARGET_ROOT26_TOG_REG(CCM_BASE_PTR) +#define CCM_POST26 CCM_POST26_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT26_SET CCM_POST_ROOT26_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT26_CLR CCM_POST_ROOT26_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT26_TOG CCM_POST_ROOT26_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE26 CCM_PRE26_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT26_SET CCM_PRE_ROOT26_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT26_CLR CCM_PRE_ROOT26_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT26_TOG CCM_PRE_ROOT26_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL26 CCM_ACCESS_CTRL26_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT26_SET CCM_ACCESS_CTRL26_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT26_CLR CCM_ACCESS_CTRL26_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT26_TOG CCM_ACCESS_CTRL26_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT27 CCM_TARGET_ROOT27_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT27_SET CCM_TARGET_ROOT27_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT27_CLR CCM_TARGET_ROOT27_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT27_TOG CCM_TARGET_ROOT27_TOG_REG(CCM_BASE_PTR) +#define CCM_POST27 CCM_POST27_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT27_SET CCM_POST_ROOT27_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT27_CLR CCM_POST_ROOT27_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT27_TOG CCM_POST_ROOT27_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE27 CCM_PRE27_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT27_SET CCM_PRE_ROOT27_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT27_CLR CCM_PRE_ROOT27_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT27_TOG CCM_PRE_ROOT27_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL27 CCM_ACCESS_CTRL27_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT27_SET CCM_ACCESS_CTRL27_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT27_CLR CCM_ACCESS_CTRL27_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT27_TOG CCM_ACCESS_CTRL27_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT28 CCM_TARGET_ROOT28_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT28_SET CCM_TARGET_ROOT28_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT28_CLR CCM_TARGET_ROOT28_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT28_TOG CCM_TARGET_ROOT28_TOG_REG(CCM_BASE_PTR) +#define CCM_POST28 CCM_POST28_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT28_SET CCM_POST_ROOT28_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT28_CLR CCM_POST_ROOT28_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT28_TOG CCM_POST_ROOT28_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE28 CCM_PRE28_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT28_SET CCM_PRE_ROOT28_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT28_CLR CCM_PRE_ROOT28_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT28_TOG CCM_PRE_ROOT28_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL28 CCM_ACCESS_CTRL28_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT28_SET CCM_ACCESS_CTRL28_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT28_CLR CCM_ACCESS_CTRL28_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT28_TOG CCM_ACCESS_CTRL28_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT29 CCM_TARGET_ROOT29_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT29_SET CCM_TARGET_ROOT29_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT29_CLR CCM_TARGET_ROOT29_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT29_TOG CCM_TARGET_ROOT29_TOG_REG(CCM_BASE_PTR) +#define CCM_POST29 CCM_POST29_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT29_SET CCM_POST_ROOT29_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT29_CLR CCM_POST_ROOT29_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT29_TOG CCM_POST_ROOT29_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE29 CCM_PRE29_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT29_SET CCM_PRE_ROOT29_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT29_CLR CCM_PRE_ROOT29_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT29_TOG CCM_PRE_ROOT29_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL29 CCM_ACCESS_CTRL29_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT29_SET CCM_ACCESS_CTRL29_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT29_CLR CCM_ACCESS_CTRL29_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT29_TOG CCM_ACCESS_CTRL29_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT30 CCM_TARGET_ROOT30_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT30_SET CCM_TARGET_ROOT30_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT30_CLR CCM_TARGET_ROOT30_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT30_TOG CCM_TARGET_ROOT30_TOG_REG(CCM_BASE_PTR) +#define CCM_POST30 CCM_POST30_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT30_SET CCM_POST_ROOT30_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT30_CLR CCM_POST_ROOT30_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT30_TOG CCM_POST_ROOT30_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE30 CCM_PRE30_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT30_SET CCM_PRE_ROOT30_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT30_CLR CCM_PRE_ROOT30_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT30_TOG CCM_PRE_ROOT30_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL30 CCM_ACCESS_CTRL30_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT30_SET CCM_ACCESS_CTRL30_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT30_CLR CCM_ACCESS_CTRL30_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT30_TOG CCM_ACCESS_CTRL30_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT31 CCM_TARGET_ROOT31_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT31_SET CCM_TARGET_ROOT31_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT31_CLR CCM_TARGET_ROOT31_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT31_TOG CCM_TARGET_ROOT31_TOG_REG(CCM_BASE_PTR) +#define CCM_POST31 CCM_POST31_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT31_SET CCM_POST_ROOT31_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT31_CLR CCM_POST_ROOT31_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT31_TOG CCM_POST_ROOT31_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE31 CCM_PRE31_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT31_SET CCM_PRE_ROOT31_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT31_CLR CCM_PRE_ROOT31_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT31_TOG CCM_PRE_ROOT31_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL31 CCM_ACCESS_CTRL31_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT31_SET CCM_ACCESS_CTRL31_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT31_CLR CCM_ACCESS_CTRL31_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT31_TOG CCM_ACCESS_CTRL31_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT32 CCM_TARGET_ROOT32_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT32_SET CCM_TARGET_ROOT32_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT32_CLR CCM_TARGET_ROOT32_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT32_TOG CCM_TARGET_ROOT32_TOG_REG(CCM_BASE_PTR) +#define CCM_POST32 CCM_POST32_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT32_SET CCM_POST_ROOT32_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT32_CLR CCM_POST_ROOT32_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT32_TOG CCM_POST_ROOT32_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE32 CCM_PRE32_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT32_SET CCM_PRE_ROOT32_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT32_CLR CCM_PRE_ROOT32_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT32_TOG CCM_PRE_ROOT32_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL32 CCM_ACCESS_CTRL32_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT32_SET CCM_ACCESS_CTRL32_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT32_CLR CCM_ACCESS_CTRL32_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT32_TOG CCM_ACCESS_CTRL32_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT33 CCM_TARGET_ROOT33_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT33_SET CCM_TARGET_ROOT33_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT33_CLR CCM_TARGET_ROOT33_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT33_TOG CCM_TARGET_ROOT33_TOG_REG(CCM_BASE_PTR) +#define CCM_POST33 CCM_POST33_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT33_SET CCM_POST_ROOT33_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT33_CLR CCM_POST_ROOT33_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT33_TOG CCM_POST_ROOT33_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE33 CCM_PRE33_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT33_SET CCM_PRE_ROOT33_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT33_CLR CCM_PRE_ROOT33_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT33_TOG CCM_PRE_ROOT33_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL33 CCM_ACCESS_CTRL33_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT33_SET CCM_ACCESS_CTRL33_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT33_CLR CCM_ACCESS_CTRL33_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT33_TOG CCM_ACCESS_CTRL33_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT34 CCM_TARGET_ROOT34_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT34_SET CCM_TARGET_ROOT34_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT34_CLR CCM_TARGET_ROOT34_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT34_TOG CCM_TARGET_ROOT34_TOG_REG(CCM_BASE_PTR) +#define CCM_POST34 CCM_POST34_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT34_SET CCM_POST_ROOT34_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT34_CLR CCM_POST_ROOT34_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT34_TOG CCM_POST_ROOT34_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE34 CCM_PRE34_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT34_SET CCM_PRE_ROOT34_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT34_CLR CCM_PRE_ROOT34_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT34_TOG CCM_PRE_ROOT34_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL34 CCM_ACCESS_CTRL34_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT34_SET CCM_ACCESS_CTRL34_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT34_CLR CCM_ACCESS_CTRL34_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT34_TOG CCM_ACCESS_CTRL34_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT35 CCM_TARGET_ROOT35_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT35_SET CCM_TARGET_ROOT35_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT35_CLR CCM_TARGET_ROOT35_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT35_TOG CCM_TARGET_ROOT35_TOG_REG(CCM_BASE_PTR) +#define CCM_POST35 CCM_POST35_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT35_SET CCM_POST_ROOT35_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT35_CLR CCM_POST_ROOT35_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT35_TOG CCM_POST_ROOT35_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE35 CCM_PRE35_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT35_SET CCM_PRE_ROOT35_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT35_CLR CCM_PRE_ROOT35_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT35_TOG CCM_PRE_ROOT35_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL35 CCM_ACCESS_CTRL35_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT35_SET CCM_ACCESS_CTRL35_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT35_CLR CCM_ACCESS_CTRL35_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT35_TOG CCM_ACCESS_CTRL35_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT36 CCM_TARGET_ROOT36_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT36_SET CCM_TARGET_ROOT36_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT36_CLR CCM_TARGET_ROOT36_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT36_TOG CCM_TARGET_ROOT36_TOG_REG(CCM_BASE_PTR) +#define CCM_POST36 CCM_POST36_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT36_SET CCM_POST_ROOT36_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT36_CLR CCM_POST_ROOT36_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT36_TOG CCM_POST_ROOT36_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE36 CCM_PRE36_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT36_SET CCM_PRE_ROOT36_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT36_CLR CCM_PRE_ROOT36_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT36_TOG CCM_PRE_ROOT36_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL36 CCM_ACCESS_CTRL36_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT36_SET CCM_ACCESS_CTRL36_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT36_CLR CCM_ACCESS_CTRL36_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT36_TOG CCM_ACCESS_CTRL36_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT37 CCM_TARGET_ROOT37_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT37_SET CCM_TARGET_ROOT37_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT37_CLR CCM_TARGET_ROOT37_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT37_TOG CCM_TARGET_ROOT37_TOG_REG(CCM_BASE_PTR) +#define CCM_POST37 CCM_POST37_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT37_SET CCM_POST_ROOT37_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT37_CLR CCM_POST_ROOT37_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT37_TOG CCM_POST_ROOT37_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE37 CCM_PRE37_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT37_SET CCM_PRE_ROOT37_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT37_CLR CCM_PRE_ROOT37_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT37_TOG CCM_PRE_ROOT37_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL37 CCM_ACCESS_CTRL37_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT37_SET CCM_ACCESS_CTRL37_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT37_CLR CCM_ACCESS_CTRL37_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT37_TOG CCM_ACCESS_CTRL37_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT38 CCM_TARGET_ROOT38_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT38_SET CCM_TARGET_ROOT38_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT38_CLR CCM_TARGET_ROOT38_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT38_TOG CCM_TARGET_ROOT38_TOG_REG(CCM_BASE_PTR) +#define CCM_POST38 CCM_POST38_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT38_SET CCM_POST_ROOT38_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT38_CLR CCM_POST_ROOT38_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT38_TOG CCM_POST_ROOT38_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE38 CCM_PRE38_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT38_SET CCM_PRE_ROOT38_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT38_CLR CCM_PRE_ROOT38_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT38_TOG CCM_PRE_ROOT38_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL38 CCM_ACCESS_CTRL38_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT38_SET CCM_ACCESS_CTRL38_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT38_CLR CCM_ACCESS_CTRL38_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT38_TOG CCM_ACCESS_CTRL38_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT39 CCM_TARGET_ROOT39_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT39_SET CCM_TARGET_ROOT39_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT39_CLR CCM_TARGET_ROOT39_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT39_TOG CCM_TARGET_ROOT39_TOG_REG(CCM_BASE_PTR) +#define CCM_POST39 CCM_POST39_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT39_SET CCM_POST_ROOT39_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT39_CLR CCM_POST_ROOT39_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT39_TOG CCM_POST_ROOT39_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE39 CCM_PRE39_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT39_SET CCM_PRE_ROOT39_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT39_CLR CCM_PRE_ROOT39_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT39_TOG CCM_PRE_ROOT39_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL39 CCM_ACCESS_CTRL39_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT39_SET CCM_ACCESS_CTRL39_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT39_CLR CCM_ACCESS_CTRL39_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT39_TOG CCM_ACCESS_CTRL39_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT40 CCM_TARGET_ROOT40_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT40_SET CCM_TARGET_ROOT40_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT40_CLR CCM_TARGET_ROOT40_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT40_TOG CCM_TARGET_ROOT40_TOG_REG(CCM_BASE_PTR) +#define CCM_POST40 CCM_POST40_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT40_SET CCM_POST_ROOT40_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT40_CLR CCM_POST_ROOT40_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT40_TOG CCM_POST_ROOT40_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE40 CCM_PRE40_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT40_SET CCM_PRE_ROOT40_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT40_CLR CCM_PRE_ROOT40_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT40_TOG CCM_PRE_ROOT40_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL40 CCM_ACCESS_CTRL40_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT40_SET CCM_ACCESS_CTRL40_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT40_CLR CCM_ACCESS_CTRL40_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT40_TOG CCM_ACCESS_CTRL40_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT41 CCM_TARGET_ROOT41_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT41_SET CCM_TARGET_ROOT41_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT41_CLR CCM_TARGET_ROOT41_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT41_TOG CCM_TARGET_ROOT41_TOG_REG(CCM_BASE_PTR) +#define CCM_POST41 CCM_POST41_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT41_SET CCM_POST_ROOT41_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT41_CLR CCM_POST_ROOT41_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT41_TOG CCM_POST_ROOT41_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE41 CCM_PRE41_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT41_SET CCM_PRE_ROOT41_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT41_CLR CCM_PRE_ROOT41_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT41_TOG CCM_PRE_ROOT41_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL41 CCM_ACCESS_CTRL41_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT41_SET CCM_ACCESS_CTRL41_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT41_CLR CCM_ACCESS_CTRL41_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT41_TOG CCM_ACCESS_CTRL41_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT42 CCM_TARGET_ROOT42_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT42_SET CCM_TARGET_ROOT42_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT42_CLR CCM_TARGET_ROOT42_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT42_TOG CCM_TARGET_ROOT42_TOG_REG(CCM_BASE_PTR) +#define CCM_POST42 CCM_POST42_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT42_SET CCM_POST_ROOT42_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT42_CLR CCM_POST_ROOT42_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT42_TOG CCM_POST_ROOT42_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE42 CCM_PRE42_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT42_SET CCM_PRE_ROOT42_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT42_CLR CCM_PRE_ROOT42_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT42_TOG CCM_PRE_ROOT42_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL42 CCM_ACCESS_CTRL42_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT42_SET CCM_ACCESS_CTRL42_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT42_CLR CCM_ACCESS_CTRL42_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT42_TOG CCM_ACCESS_CTRL42_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT43 CCM_TARGET_ROOT43_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT43_SET CCM_TARGET_ROOT43_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT43_CLR CCM_TARGET_ROOT43_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT43_TOG CCM_TARGET_ROOT43_TOG_REG(CCM_BASE_PTR) +#define CCM_POST43 CCM_POST43_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT43_SET CCM_POST_ROOT43_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT43_CLR CCM_POST_ROOT43_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT43_TOG CCM_POST_ROOT43_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE43 CCM_PRE43_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT43_SET CCM_PRE_ROOT43_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT43_CLR CCM_PRE_ROOT43_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT43_TOG CCM_PRE_ROOT43_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL43 CCM_ACCESS_CTRL43_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT43_SET CCM_ACCESS_CTRL43_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT43_CLR CCM_ACCESS_CTRL43_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT43_TOG CCM_ACCESS_CTRL43_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT44 CCM_TARGET_ROOT44_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT44_SET CCM_TARGET_ROOT44_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT44_CLR CCM_TARGET_ROOT44_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT44_TOG CCM_TARGET_ROOT44_TOG_REG(CCM_BASE_PTR) +#define CCM_POST44 CCM_POST44_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT44_SET CCM_POST_ROOT44_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT44_CLR CCM_POST_ROOT44_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT44_TOG CCM_POST_ROOT44_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE44 CCM_PRE44_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT44_SET CCM_PRE_ROOT44_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT44_CLR CCM_PRE_ROOT44_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT44_TOG CCM_PRE_ROOT44_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL44 CCM_ACCESS_CTRL44_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT44_SET CCM_ACCESS_CTRL44_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT44_CLR CCM_ACCESS_CTRL44_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT44_TOG CCM_ACCESS_CTRL44_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT45 CCM_TARGET_ROOT45_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT45_SET CCM_TARGET_ROOT45_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT45_CLR CCM_TARGET_ROOT45_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT45_TOG CCM_TARGET_ROOT45_TOG_REG(CCM_BASE_PTR) +#define CCM_POST45 CCM_POST45_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT45_SET CCM_POST_ROOT45_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT45_CLR CCM_POST_ROOT45_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT45_TOG CCM_POST_ROOT45_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE45 CCM_PRE45_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT45_SET CCM_PRE_ROOT45_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT45_CLR CCM_PRE_ROOT45_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT45_TOG CCM_PRE_ROOT45_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL45 CCM_ACCESS_CTRL45_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT45_SET CCM_ACCESS_CTRL45_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT45_CLR CCM_ACCESS_CTRL45_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT45_TOG CCM_ACCESS_CTRL45_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT46 CCM_TARGET_ROOT46_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT46_SET CCM_TARGET_ROOT46_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT46_CLR CCM_TARGET_ROOT46_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT46_TOG CCM_TARGET_ROOT46_TOG_REG(CCM_BASE_PTR) +#define CCM_POST46 CCM_POST46_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT46_SET CCM_POST_ROOT46_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT46_CLR CCM_POST_ROOT46_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT46_TOG CCM_POST_ROOT46_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE46 CCM_PRE46_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT46_SET CCM_PRE_ROOT46_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT46_CLR CCM_PRE_ROOT46_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT46_TOG CCM_PRE_ROOT46_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL46 CCM_ACCESS_CTRL46_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT46_SET CCM_ACCESS_CTRL46_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT46_CLR CCM_ACCESS_CTRL46_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT46_TOG CCM_ACCESS_CTRL46_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT47 CCM_TARGET_ROOT47_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT47_SET CCM_TARGET_ROOT47_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT47_CLR CCM_TARGET_ROOT47_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT47_TOG CCM_TARGET_ROOT47_TOG_REG(CCM_BASE_PTR) +#define CCM_POST47 CCM_POST47_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT47_SET CCM_POST_ROOT47_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT47_CLR CCM_POST_ROOT47_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT47_TOG CCM_POST_ROOT47_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE47 CCM_PRE47_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT47_SET CCM_PRE_ROOT47_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT47_CLR CCM_PRE_ROOT47_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT47_TOG CCM_PRE_ROOT47_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL47 CCM_ACCESS_CTRL47_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT47_SET CCM_ACCESS_CTRL47_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT47_CLR CCM_ACCESS_CTRL47_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT47_TOG CCM_ACCESS_CTRL47_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT48 CCM_TARGET_ROOT48_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT48_SET CCM_TARGET_ROOT48_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT48_CLR CCM_TARGET_ROOT48_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT48_TOG CCM_TARGET_ROOT48_TOG_REG(CCM_BASE_PTR) +#define CCM_POST48 CCM_POST48_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT48_SET CCM_POST_ROOT48_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT48_CLR CCM_POST_ROOT48_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT48_TOG CCM_POST_ROOT48_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE48 CCM_PRE48_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT48_SET CCM_PRE_ROOT48_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT48_CLR CCM_PRE_ROOT48_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT48_TOG CCM_PRE_ROOT48_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL48 CCM_ACCESS_CTRL48_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT48_SET CCM_ACCESS_CTRL48_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT48_CLR CCM_ACCESS_CTRL48_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT48_TOG CCM_ACCESS_CTRL48_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT49 CCM_TARGET_ROOT49_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT49_SET CCM_TARGET_ROOT49_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT49_CLR CCM_TARGET_ROOT49_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT49_TOG CCM_TARGET_ROOT49_TOG_REG(CCM_BASE_PTR) +#define CCM_POST49 CCM_POST49_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT49_SET CCM_POST_ROOT49_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT49_CLR CCM_POST_ROOT49_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT49_TOG CCM_POST_ROOT49_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE49 CCM_PRE49_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT49_SET CCM_PRE_ROOT49_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT49_CLR CCM_PRE_ROOT49_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT49_TOG CCM_PRE_ROOT49_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL49 CCM_ACCESS_CTRL49_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT49_SET CCM_ACCESS_CTRL49_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT49_CLR CCM_ACCESS_CTRL49_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT49_TOG CCM_ACCESS_CTRL49_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT50 CCM_TARGET_ROOT50_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT50_SET CCM_TARGET_ROOT50_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT50_CLR CCM_TARGET_ROOT50_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT50_TOG CCM_TARGET_ROOT50_TOG_REG(CCM_BASE_PTR) +#define CCM_POST50 CCM_POST50_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT50_SET CCM_POST_ROOT50_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT50_CLR CCM_POST_ROOT50_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT50_TOG CCM_POST_ROOT50_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE50 CCM_PRE50_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT50_SET CCM_PRE_ROOT50_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT50_CLR CCM_PRE_ROOT50_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT50_TOG CCM_PRE_ROOT50_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL50 CCM_ACCESS_CTRL50_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT50_SET CCM_ACCESS_CTRL50_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT50_CLR CCM_ACCESS_CTRL50_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT50_TOG CCM_ACCESS_CTRL50_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT51 CCM_TARGET_ROOT51_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT51_SET CCM_TARGET_ROOT51_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT51_CLR CCM_TARGET_ROOT51_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT51_TOG CCM_TARGET_ROOT51_TOG_REG(CCM_BASE_PTR) +#define CCM_POST51 CCM_POST51_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT51_SET CCM_POST_ROOT51_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT51_CLR CCM_POST_ROOT51_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT51_TOG CCM_POST_ROOT51_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE51 CCM_PRE51_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT51_SET CCM_PRE_ROOT51_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT51_CLR CCM_PRE_ROOT51_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT51_TOG CCM_PRE_ROOT51_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL51 CCM_ACCESS_CTRL51_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT51_SET CCM_ACCESS_CTRL51_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT51_CLR CCM_ACCESS_CTRL51_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT51_TOG CCM_ACCESS_CTRL51_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT52 CCM_TARGET_ROOT52_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT52_SET CCM_TARGET_ROOT52_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT52_CLR CCM_TARGET_ROOT52_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT52_TOG CCM_TARGET_ROOT52_TOG_REG(CCM_BASE_PTR) +#define CCM_POST52 CCM_POST52_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT52_SET CCM_POST_ROOT52_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT52_CLR CCM_POST_ROOT52_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT52_TOG CCM_POST_ROOT52_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE52 CCM_PRE52_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT52_SET CCM_PRE_ROOT52_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT52_CLR CCM_PRE_ROOT52_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT52_TOG CCM_PRE_ROOT52_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL52 CCM_ACCESS_CTRL52_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT52_SET CCM_ACCESS_CTRL52_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT52_CLR CCM_ACCESS_CTRL52_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT52_TOG CCM_ACCESS_CTRL52_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT53 CCM_TARGET_ROOT53_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT53_SET CCM_TARGET_ROOT53_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT53_CLR CCM_TARGET_ROOT53_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT53_TOG CCM_TARGET_ROOT53_TOG_REG(CCM_BASE_PTR) +#define CCM_POST53 CCM_POST53_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT53_SET CCM_POST_ROOT53_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT53_CLR CCM_POST_ROOT53_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT53_TOG CCM_POST_ROOT53_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE53 CCM_PRE53_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT53_SET CCM_PRE_ROOT53_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT53_CLR CCM_PRE_ROOT53_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT53_TOG CCM_PRE_ROOT53_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL53 CCM_ACCESS_CTRL53_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT53_SET CCM_ACCESS_CTRL53_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT53_CLR CCM_ACCESS_CTRL53_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT53_TOG CCM_ACCESS_CTRL53_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT54 CCM_TARGET_ROOT54_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT54_SET CCM_TARGET_ROOT54_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT54_CLR CCM_TARGET_ROOT54_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT54_TOG CCM_TARGET_ROOT54_TOG_REG(CCM_BASE_PTR) +#define CCM_POST54 CCM_POST54_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT54_SET CCM_POST_ROOT54_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT54_CLR CCM_POST_ROOT54_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT54_TOG CCM_POST_ROOT54_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE54 CCM_PRE54_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT54_SET CCM_PRE_ROOT54_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT54_CLR CCM_PRE_ROOT54_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT54_TOG CCM_PRE_ROOT54_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL54 CCM_ACCESS_CTRL54_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT54_SET CCM_ACCESS_CTRL54_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT54_CLR CCM_ACCESS_CTRL54_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT54_TOG CCM_ACCESS_CTRL54_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT55 CCM_TARGET_ROOT55_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT55_SET CCM_TARGET_ROOT55_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT55_CLR CCM_TARGET_ROOT55_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT55_TOG CCM_TARGET_ROOT55_TOG_REG(CCM_BASE_PTR) +#define CCM_POST55 CCM_POST55_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT55_SET CCM_POST_ROOT55_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT55_CLR CCM_POST_ROOT55_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT55_TOG CCM_POST_ROOT55_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE55 CCM_PRE55_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT55_SET CCM_PRE_ROOT55_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT55_CLR CCM_PRE_ROOT55_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT55_TOG CCM_PRE_ROOT55_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL55 CCM_ACCESS_CTRL55_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT55_SET CCM_ACCESS_CTRL55_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT55_CLR CCM_ACCESS_CTRL55_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT55_TOG CCM_ACCESS_CTRL55_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT56 CCM_TARGET_ROOT56_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT56_SET CCM_TARGET_ROOT56_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT56_CLR CCM_TARGET_ROOT56_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT56_TOG CCM_TARGET_ROOT56_TOG_REG(CCM_BASE_PTR) +#define CCM_POST56 CCM_POST56_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT56_SET CCM_POST_ROOT56_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT56_CLR CCM_POST_ROOT56_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT56_TOG CCM_POST_ROOT56_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE56 CCM_PRE56_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT56_SET CCM_PRE_ROOT56_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT56_CLR CCM_PRE_ROOT56_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT56_TOG CCM_PRE_ROOT56_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL56 CCM_ACCESS_CTRL56_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT56_SET CCM_ACCESS_CTRL56_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT56_CLR CCM_ACCESS_CTRL56_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT56_TOG CCM_ACCESS_CTRL56_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT57 CCM_TARGET_ROOT57_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT57_SET CCM_TARGET_ROOT57_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT57_CLR CCM_TARGET_ROOT57_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT57_TOG CCM_TARGET_ROOT57_TOG_REG(CCM_BASE_PTR) +#define CCM_POST57 CCM_POST57_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT57_SET CCM_POST_ROOT57_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT57_CLR CCM_POST_ROOT57_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT57_TOG CCM_POST_ROOT57_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE57 CCM_PRE57_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT57_SET CCM_PRE_ROOT57_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT57_CLR CCM_PRE_ROOT57_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT57_TOG CCM_PRE_ROOT57_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL57 CCM_ACCESS_CTRL57_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT57_SET CCM_ACCESS_CTRL57_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT57_CLR CCM_ACCESS_CTRL57_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT57_TOG CCM_ACCESS_CTRL57_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT58 CCM_TARGET_ROOT58_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT58_SET CCM_TARGET_ROOT58_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT58_CLR CCM_TARGET_ROOT58_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT58_TOG CCM_TARGET_ROOT58_TOG_REG(CCM_BASE_PTR) +#define CCM_POST58 CCM_POST58_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT58_SET CCM_POST_ROOT58_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT58_CLR CCM_POST_ROOT58_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT58_TOG CCM_POST_ROOT58_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE58 CCM_PRE58_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT58_SET CCM_PRE_ROOT58_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT58_CLR CCM_PRE_ROOT58_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT58_TOG CCM_PRE_ROOT58_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL58 CCM_ACCESS_CTRL58_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT58_SET CCM_ACCESS_CTRL58_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT58_CLR CCM_ACCESS_CTRL58_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT58_TOG CCM_ACCESS_CTRL58_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT59 CCM_TARGET_ROOT59_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT59_SET CCM_TARGET_ROOT59_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT59_CLR CCM_TARGET_ROOT59_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT59_TOG CCM_TARGET_ROOT59_TOG_REG(CCM_BASE_PTR) +#define CCM_POST59 CCM_POST59_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT59_SET CCM_POST_ROOT59_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT59_CLR CCM_POST_ROOT59_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT59_TOG CCM_POST_ROOT59_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE59 CCM_PRE59_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT59_SET CCM_PRE_ROOT59_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT59_CLR CCM_PRE_ROOT59_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT59_TOG CCM_PRE_ROOT59_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL59 CCM_ACCESS_CTRL59_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT59_SET CCM_ACCESS_CTRL59_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT59_CLR CCM_ACCESS_CTRL59_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT59_TOG CCM_ACCESS_CTRL59_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT60 CCM_TARGET_ROOT60_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT60_SET CCM_TARGET_ROOT60_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT60_CLR CCM_TARGET_ROOT60_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT60_TOG CCM_TARGET_ROOT60_TOG_REG(CCM_BASE_PTR) +#define CCM_POST60 CCM_POST60_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT60_SET CCM_POST_ROOT60_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT60_CLR CCM_POST_ROOT60_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT60_TOG CCM_POST_ROOT60_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE60 CCM_PRE60_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT60_SET CCM_PRE_ROOT60_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT60_CLR CCM_PRE_ROOT60_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT60_TOG CCM_PRE_ROOT60_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL60 CCM_ACCESS_CTRL60_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT60_SET CCM_ACCESS_CTRL60_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT60_CLR CCM_ACCESS_CTRL60_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT60_TOG CCM_ACCESS_CTRL60_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT61 CCM_TARGET_ROOT61_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT61_SET CCM_TARGET_ROOT61_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT61_CLR CCM_TARGET_ROOT61_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT61_TOG CCM_TARGET_ROOT61_TOG_REG(CCM_BASE_PTR) +#define CCM_POST61 CCM_POST61_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT61_SET CCM_POST_ROOT61_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT61_CLR CCM_POST_ROOT61_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT61_TOG CCM_POST_ROOT61_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE61 CCM_PRE61_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT61_SET CCM_PRE_ROOT61_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT61_CLR CCM_PRE_ROOT61_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT61_TOG CCM_PRE_ROOT61_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL61 CCM_ACCESS_CTRL61_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT61_SET CCM_ACCESS_CTRL61_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT61_CLR CCM_ACCESS_CTRL61_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT61_TOG CCM_ACCESS_CTRL61_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT62 CCM_TARGET_ROOT62_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT62_SET CCM_TARGET_ROOT62_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT62_CLR CCM_TARGET_ROOT62_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT62_TOG CCM_TARGET_ROOT62_TOG_REG(CCM_BASE_PTR) +#define CCM_POST62 CCM_POST62_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT62_SET CCM_POST_ROOT62_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT62_CLR CCM_POST_ROOT62_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT62_TOG CCM_POST_ROOT62_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE62 CCM_PRE62_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT62_SET CCM_PRE_ROOT62_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT62_CLR CCM_PRE_ROOT62_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT62_TOG CCM_PRE_ROOT62_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL62 CCM_ACCESS_CTRL62_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT62_SET CCM_ACCESS_CTRL62_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT62_CLR CCM_ACCESS_CTRL62_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT62_TOG CCM_ACCESS_CTRL62_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT63 CCM_TARGET_ROOT63_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT63_SET CCM_TARGET_ROOT63_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT63_CLR CCM_TARGET_ROOT63_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT63_TOG CCM_TARGET_ROOT63_TOG_REG(CCM_BASE_PTR) +#define CCM_POST63 CCM_POST63_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT63_SET CCM_POST_ROOT63_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT63_CLR CCM_POST_ROOT63_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT63_TOG CCM_POST_ROOT63_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE63 CCM_PRE63_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT63_SET CCM_PRE_ROOT63_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT63_CLR CCM_PRE_ROOT63_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT63_TOG CCM_PRE_ROOT63_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL63 CCM_ACCESS_CTRL63_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT63_SET CCM_ACCESS_CTRL63_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT63_CLR CCM_ACCESS_CTRL63_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT63_TOG CCM_ACCESS_CTRL63_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT64 CCM_TARGET_ROOT64_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT64_SET CCM_TARGET_ROOT64_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT64_CLR CCM_TARGET_ROOT64_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT64_TOG CCM_TARGET_ROOT64_TOG_REG(CCM_BASE_PTR) +#define CCM_POST64 CCM_POST64_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT64_SET CCM_POST_ROOT64_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT64_CLR CCM_POST_ROOT64_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT64_TOG CCM_POST_ROOT64_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE64 CCM_PRE64_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT64_SET CCM_PRE_ROOT64_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT64_CLR CCM_PRE_ROOT64_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT64_TOG CCM_PRE_ROOT64_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL64 CCM_ACCESS_CTRL64_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT64_SET CCM_ACCESS_CTRL64_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT64_CLR CCM_ACCESS_CTRL64_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT64_TOG CCM_ACCESS_CTRL64_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT65 CCM_TARGET_ROOT65_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT65_SET CCM_TARGET_ROOT65_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT65_CLR CCM_TARGET_ROOT65_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT65_TOG CCM_TARGET_ROOT65_TOG_REG(CCM_BASE_PTR) +#define CCM_POST65 CCM_POST65_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT65_SET CCM_POST_ROOT65_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT65_CLR CCM_POST_ROOT65_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT65_TOG CCM_POST_ROOT65_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE65 CCM_PRE65_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT65_SET CCM_PRE_ROOT65_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT65_CLR CCM_PRE_ROOT65_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT65_TOG CCM_PRE_ROOT65_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL65 CCM_ACCESS_CTRL65_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT65_SET CCM_ACCESS_CTRL65_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT65_CLR CCM_ACCESS_CTRL65_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT65_TOG CCM_ACCESS_CTRL65_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT66 CCM_TARGET_ROOT66_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT66_SET CCM_TARGET_ROOT66_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT66_CLR CCM_TARGET_ROOT66_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT66_TOG CCM_TARGET_ROOT66_TOG_REG(CCM_BASE_PTR) +#define CCM_POST66 CCM_POST66_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT66_SET CCM_POST_ROOT66_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT66_CLR CCM_POST_ROOT66_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT66_TOG CCM_POST_ROOT66_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE66 CCM_PRE66_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT66_SET CCM_PRE_ROOT66_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT66_CLR CCM_PRE_ROOT66_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT66_TOG CCM_PRE_ROOT66_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL66 CCM_ACCESS_CTRL66_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT66_SET CCM_ACCESS_CTRL66_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT66_CLR CCM_ACCESS_CTRL66_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT66_TOG CCM_ACCESS_CTRL66_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT67 CCM_TARGET_ROOT67_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT67_SET CCM_TARGET_ROOT67_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT67_CLR CCM_TARGET_ROOT67_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT67_TOG CCM_TARGET_ROOT67_TOG_REG(CCM_BASE_PTR) +#define CCM_POST67 CCM_POST67_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT67_SET CCM_POST_ROOT67_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT67_CLR CCM_POST_ROOT67_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT67_TOG CCM_POST_ROOT67_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE67 CCM_PRE67_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT67_SET CCM_PRE_ROOT67_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT67_CLR CCM_PRE_ROOT67_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT67_TOG CCM_PRE_ROOT67_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL67 CCM_ACCESS_CTRL67_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT67_SET CCM_ACCESS_CTRL67_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT67_CLR CCM_ACCESS_CTRL67_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT67_TOG CCM_ACCESS_CTRL67_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT68 CCM_TARGET_ROOT68_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT68_SET CCM_TARGET_ROOT68_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT68_CLR CCM_TARGET_ROOT68_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT68_TOG CCM_TARGET_ROOT68_TOG_REG(CCM_BASE_PTR) +#define CCM_POST68 CCM_POST68_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT68_SET CCM_POST_ROOT68_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT68_CLR CCM_POST_ROOT68_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT68_TOG CCM_POST_ROOT68_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE68 CCM_PRE68_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT68_SET CCM_PRE_ROOT68_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT68_CLR CCM_PRE_ROOT68_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT68_TOG CCM_PRE_ROOT68_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL68 CCM_ACCESS_CTRL68_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT68_SET CCM_ACCESS_CTRL68_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT68_CLR CCM_ACCESS_CTRL68_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT68_TOG CCM_ACCESS_CTRL68_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT69 CCM_TARGET_ROOT69_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT69_SET CCM_TARGET_ROOT69_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT69_CLR CCM_TARGET_ROOT69_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT69_TOG CCM_TARGET_ROOT69_TOG_REG(CCM_BASE_PTR) +#define CCM_POST69 CCM_POST69_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT69_SET CCM_POST_ROOT69_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT69_CLR CCM_POST_ROOT69_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT69_TOG CCM_POST_ROOT69_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE69 CCM_PRE69_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT69_SET CCM_PRE_ROOT69_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT69_CLR CCM_PRE_ROOT69_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT69_TOG CCM_PRE_ROOT69_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL69 CCM_ACCESS_CTRL69_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT69_SET CCM_ACCESS_CTRL69_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT69_CLR CCM_ACCESS_CTRL69_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT69_TOG CCM_ACCESS_CTRL69_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT70 CCM_TARGET_ROOT70_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT70_SET CCM_TARGET_ROOT70_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT70_CLR CCM_TARGET_ROOT70_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT70_TOG CCM_TARGET_ROOT70_TOG_REG(CCM_BASE_PTR) +#define CCM_POST70 CCM_POST70_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT70_SET CCM_POST_ROOT70_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT70_CLR CCM_POST_ROOT70_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT70_TOG CCM_POST_ROOT70_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE70 CCM_PRE70_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT70_SET CCM_PRE_ROOT70_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT70_CLR CCM_PRE_ROOT70_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT70_TOG CCM_PRE_ROOT70_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL70 CCM_ACCESS_CTRL70_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT70_SET CCM_ACCESS_CTRL70_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT70_CLR CCM_ACCESS_CTRL70_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT70_TOG CCM_ACCESS_CTRL70_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT71 CCM_TARGET_ROOT71_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT71_SET CCM_TARGET_ROOT71_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT71_CLR CCM_TARGET_ROOT71_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT71_TOG CCM_TARGET_ROOT71_TOG_REG(CCM_BASE_PTR) +#define CCM_POST71 CCM_POST71_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT71_SET CCM_POST_ROOT71_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT71_CLR CCM_POST_ROOT71_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT71_TOG CCM_POST_ROOT71_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE71 CCM_PRE71_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT71_SET CCM_PRE_ROOT71_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT71_CLR CCM_PRE_ROOT71_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT71_TOG CCM_PRE_ROOT71_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL71 CCM_ACCESS_CTRL71_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT71_SET CCM_ACCESS_CTRL71_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT71_CLR CCM_ACCESS_CTRL71_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT71_TOG CCM_ACCESS_CTRL71_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT72 CCM_TARGET_ROOT72_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT72_SET CCM_TARGET_ROOT72_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT72_CLR CCM_TARGET_ROOT72_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT72_TOG CCM_TARGET_ROOT72_TOG_REG(CCM_BASE_PTR) +#define CCM_POST72 CCM_POST72_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT72_SET CCM_POST_ROOT72_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT72_CLR CCM_POST_ROOT72_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT72_TOG CCM_POST_ROOT72_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE72 CCM_PRE72_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT72_SET CCM_PRE_ROOT72_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT72_CLR CCM_PRE_ROOT72_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT72_TOG CCM_PRE_ROOT72_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL72 CCM_ACCESS_CTRL72_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT72_SET CCM_ACCESS_CTRL72_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT72_CLR CCM_ACCESS_CTRL72_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT72_TOG CCM_ACCESS_CTRL72_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT73 CCM_TARGET_ROOT73_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT73_SET CCM_TARGET_ROOT73_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT73_CLR CCM_TARGET_ROOT73_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT73_TOG CCM_TARGET_ROOT73_TOG_REG(CCM_BASE_PTR) +#define CCM_POST73 CCM_POST73_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT73_SET CCM_POST_ROOT73_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT73_CLR CCM_POST_ROOT73_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT73_TOG CCM_POST_ROOT73_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE73 CCM_PRE73_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT73_SET CCM_PRE_ROOT73_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT73_CLR CCM_PRE_ROOT73_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT73_TOG CCM_PRE_ROOT73_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL73 CCM_ACCESS_CTRL73_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT73_SET CCM_ACCESS_CTRL73_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT73_CLR CCM_ACCESS_CTRL73_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT73_TOG CCM_ACCESS_CTRL73_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT74 CCM_TARGET_ROOT74_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT74_SET CCM_TARGET_ROOT74_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT74_CLR CCM_TARGET_ROOT74_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT74_TOG CCM_TARGET_ROOT74_TOG_REG(CCM_BASE_PTR) +#define CCM_POST74 CCM_POST74_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT74_SET CCM_POST_ROOT74_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT74_CLR CCM_POST_ROOT74_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT74_TOG CCM_POST_ROOT74_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE74 CCM_PRE74_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT74_SET CCM_PRE_ROOT74_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT74_CLR CCM_PRE_ROOT74_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT74_TOG CCM_PRE_ROOT74_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL74 CCM_ACCESS_CTRL74_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT74_SET CCM_ACCESS_CTRL74_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT74_CLR CCM_ACCESS_CTRL74_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT74_TOG CCM_ACCESS_CTRL74_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT75 CCM_TARGET_ROOT75_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT75_SET CCM_TARGET_ROOT75_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT75_CLR CCM_TARGET_ROOT75_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT75_TOG CCM_TARGET_ROOT75_TOG_REG(CCM_BASE_PTR) +#define CCM_POST75 CCM_POST75_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT75_SET CCM_POST_ROOT75_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT75_CLR CCM_POST_ROOT75_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT75_TOG CCM_POST_ROOT75_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE75 CCM_PRE75_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT75_SET CCM_PRE_ROOT75_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT75_CLR CCM_PRE_ROOT75_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT75_TOG CCM_PRE_ROOT75_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL75 CCM_ACCESS_CTRL75_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT75_SET CCM_ACCESS_CTRL75_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT75_CLR CCM_ACCESS_CTRL75_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT75_TOG CCM_ACCESS_CTRL75_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT76 CCM_TARGET_ROOT76_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT76_SET CCM_TARGET_ROOT76_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT76_CLR CCM_TARGET_ROOT76_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT76_TOG CCM_TARGET_ROOT76_TOG_REG(CCM_BASE_PTR) +#define CCM_POST76 CCM_POST76_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT76_SET CCM_POST_ROOT76_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT76_CLR CCM_POST_ROOT76_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT76_TOG CCM_POST_ROOT76_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE76 CCM_PRE76_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT76_SET CCM_PRE_ROOT76_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT76_CLR CCM_PRE_ROOT76_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT76_TOG CCM_PRE_ROOT76_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL76 CCM_ACCESS_CTRL76_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT76_SET CCM_ACCESS_CTRL76_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT76_CLR CCM_ACCESS_CTRL76_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT76_TOG CCM_ACCESS_CTRL76_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT77 CCM_TARGET_ROOT77_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT77_SET CCM_TARGET_ROOT77_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT77_CLR CCM_TARGET_ROOT77_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT77_TOG CCM_TARGET_ROOT77_TOG_REG(CCM_BASE_PTR) +#define CCM_POST77 CCM_POST77_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT77_SET CCM_POST_ROOT77_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT77_CLR CCM_POST_ROOT77_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT77_TOG CCM_POST_ROOT77_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE77 CCM_PRE77_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT77_SET CCM_PRE_ROOT77_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT77_CLR CCM_PRE_ROOT77_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT77_TOG CCM_PRE_ROOT77_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL77 CCM_ACCESS_CTRL77_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT77_SET CCM_ACCESS_CTRL77_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT77_CLR CCM_ACCESS_CTRL77_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT77_TOG CCM_ACCESS_CTRL77_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT78 CCM_TARGET_ROOT78_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT78_SET CCM_TARGET_ROOT78_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT78_CLR CCM_TARGET_ROOT78_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT78_TOG CCM_TARGET_ROOT78_TOG_REG(CCM_BASE_PTR) +#define CCM_POST78 CCM_POST78_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT78_SET CCM_POST_ROOT78_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT78_CLR CCM_POST_ROOT78_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT78_TOG CCM_POST_ROOT78_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE78 CCM_PRE78_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT78_SET CCM_PRE_ROOT78_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT78_CLR CCM_PRE_ROOT78_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT78_TOG CCM_PRE_ROOT78_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL78 CCM_ACCESS_CTRL78_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT78_SET CCM_ACCESS_CTRL78_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT78_CLR CCM_ACCESS_CTRL78_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT78_TOG CCM_ACCESS_CTRL78_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT79 CCM_TARGET_ROOT79_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT79_SET CCM_TARGET_ROOT79_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT79_CLR CCM_TARGET_ROOT79_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT79_TOG CCM_TARGET_ROOT79_TOG_REG(CCM_BASE_PTR) +#define CCM_POST79 CCM_POST79_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT79_SET CCM_POST_ROOT79_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT79_CLR CCM_POST_ROOT79_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT79_TOG CCM_POST_ROOT79_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE79 CCM_PRE79_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT79_SET CCM_PRE_ROOT79_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT79_CLR CCM_PRE_ROOT79_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT79_TOG CCM_PRE_ROOT79_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL79 CCM_ACCESS_CTRL79_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT79_SET CCM_ACCESS_CTRL79_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT79_CLR CCM_ACCESS_CTRL79_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT79_TOG CCM_ACCESS_CTRL79_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT80 CCM_TARGET_ROOT80_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT80_SET CCM_TARGET_ROOT80_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT80_CLR CCM_TARGET_ROOT80_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT80_TOG CCM_TARGET_ROOT80_TOG_REG(CCM_BASE_PTR) +#define CCM_POST80 CCM_POST80_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT80_SET CCM_POST_ROOT80_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT80_CLR CCM_POST_ROOT80_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT80_TOG CCM_POST_ROOT80_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE80 CCM_PRE80_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT80_SET CCM_PRE_ROOT80_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT80_CLR CCM_PRE_ROOT80_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT80_TOG CCM_PRE_ROOT80_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL80 CCM_ACCESS_CTRL80_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT80_SET CCM_ACCESS_CTRL80_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT80_CLR CCM_ACCESS_CTRL80_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT80_TOG CCM_ACCESS_CTRL80_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT81 CCM_TARGET_ROOT81_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT81_SET CCM_TARGET_ROOT81_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT81_CLR CCM_TARGET_ROOT81_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT81_TOG CCM_TARGET_ROOT81_TOG_REG(CCM_BASE_PTR) +#define CCM_POST81 CCM_POST81_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT81_SET CCM_POST_ROOT81_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT81_CLR CCM_POST_ROOT81_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT81_TOG CCM_POST_ROOT81_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE81 CCM_PRE81_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT81_SET CCM_PRE_ROOT81_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT81_CLR CCM_PRE_ROOT81_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT81_TOG CCM_PRE_ROOT81_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL81 CCM_ACCESS_CTRL81_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT81_SET CCM_ACCESS_CTRL81_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT81_CLR CCM_ACCESS_CTRL81_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT81_TOG CCM_ACCESS_CTRL81_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT82 CCM_TARGET_ROOT82_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT82_SET CCM_TARGET_ROOT82_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT82_CLR CCM_TARGET_ROOT82_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT82_TOG CCM_TARGET_ROOT82_TOG_REG(CCM_BASE_PTR) +#define CCM_POST82 CCM_POST82_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT82_SET CCM_POST_ROOT82_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT82_CLR CCM_POST_ROOT82_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT82_TOG CCM_POST_ROOT82_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE82 CCM_PRE82_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT82_SET CCM_PRE_ROOT82_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT82_CLR CCM_PRE_ROOT82_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT82_TOG CCM_PRE_ROOT82_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL82 CCM_ACCESS_CTRL82_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT82_SET CCM_ACCESS_CTRL82_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT82_CLR CCM_ACCESS_CTRL82_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT82_TOG CCM_ACCESS_CTRL82_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT83 CCM_TARGET_ROOT83_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT83_SET CCM_TARGET_ROOT83_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT83_CLR CCM_TARGET_ROOT83_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT83_TOG CCM_TARGET_ROOT83_TOG_REG(CCM_BASE_PTR) +#define CCM_POST83 CCM_POST83_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT83_SET CCM_POST_ROOT83_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT83_CLR CCM_POST_ROOT83_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT83_TOG CCM_POST_ROOT83_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE83 CCM_PRE83_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT83_SET CCM_PRE_ROOT83_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT83_CLR CCM_PRE_ROOT83_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT83_TOG CCM_PRE_ROOT83_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL83 CCM_ACCESS_CTRL83_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT83_SET CCM_ACCESS_CTRL83_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT83_CLR CCM_ACCESS_CTRL83_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT83_TOG CCM_ACCESS_CTRL83_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT84 CCM_TARGET_ROOT84_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT84_SET CCM_TARGET_ROOT84_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT84_CLR CCM_TARGET_ROOT84_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT84_TOG CCM_TARGET_ROOT84_TOG_REG(CCM_BASE_PTR) +#define CCM_POST84 CCM_POST84_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT84_SET CCM_POST_ROOT84_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT84_CLR CCM_POST_ROOT84_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT84_TOG CCM_POST_ROOT84_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE84 CCM_PRE84_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT84_SET CCM_PRE_ROOT84_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT84_CLR CCM_PRE_ROOT84_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT84_TOG CCM_PRE_ROOT84_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL84 CCM_ACCESS_CTRL84_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT84_SET CCM_ACCESS_CTRL84_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT84_CLR CCM_ACCESS_CTRL84_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT84_TOG CCM_ACCESS_CTRL84_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT85 CCM_TARGET_ROOT85_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT85_SET CCM_TARGET_ROOT85_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT85_CLR CCM_TARGET_ROOT85_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT85_TOG CCM_TARGET_ROOT85_TOG_REG(CCM_BASE_PTR) +#define CCM_POST85 CCM_POST85_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT85_SET CCM_POST_ROOT85_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT85_CLR CCM_POST_ROOT85_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT85_TOG CCM_POST_ROOT85_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE85 CCM_PRE85_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT85_SET CCM_PRE_ROOT85_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT85_CLR CCM_PRE_ROOT85_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT85_TOG CCM_PRE_ROOT85_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL85 CCM_ACCESS_CTRL85_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT85_SET CCM_ACCESS_CTRL85_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT85_CLR CCM_ACCESS_CTRL85_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT85_TOG CCM_ACCESS_CTRL85_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT86 CCM_TARGET_ROOT86_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT86_SET CCM_TARGET_ROOT86_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT86_CLR CCM_TARGET_ROOT86_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT86_TOG CCM_TARGET_ROOT86_TOG_REG(CCM_BASE_PTR) +#define CCM_POST86 CCM_POST86_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT86_SET CCM_POST_ROOT86_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT86_CLR CCM_POST_ROOT86_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT86_TOG CCM_POST_ROOT86_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE86 CCM_PRE86_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT86_SET CCM_PRE_ROOT86_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT86_CLR CCM_PRE_ROOT86_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT86_TOG CCM_PRE_ROOT86_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL86 CCM_ACCESS_CTRL86_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT86_SET CCM_ACCESS_CTRL86_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT86_CLR CCM_ACCESS_CTRL86_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT86_TOG CCM_ACCESS_CTRL86_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT87 CCM_TARGET_ROOT87_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT87_SET CCM_TARGET_ROOT87_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT87_CLR CCM_TARGET_ROOT87_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT87_TOG CCM_TARGET_ROOT87_TOG_REG(CCM_BASE_PTR) +#define CCM_POST87 CCM_POST87_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT87_SET CCM_POST_ROOT87_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT87_CLR CCM_POST_ROOT87_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT87_TOG CCM_POST_ROOT87_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE87 CCM_PRE87_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT87_SET CCM_PRE_ROOT87_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT87_CLR CCM_PRE_ROOT87_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT87_TOG CCM_PRE_ROOT87_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL87 CCM_ACCESS_CTRL87_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT87_SET CCM_ACCESS_CTRL87_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT87_CLR CCM_ACCESS_CTRL87_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT87_TOG CCM_ACCESS_CTRL87_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT88 CCM_TARGET_ROOT88_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT88_SET CCM_TARGET_ROOT88_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT88_CLR CCM_TARGET_ROOT88_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT88_TOG CCM_TARGET_ROOT88_TOG_REG(CCM_BASE_PTR) +#define CCM_POST88 CCM_POST88_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT88_SET CCM_POST_ROOT88_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT88_CLR CCM_POST_ROOT88_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT88_TOG CCM_POST_ROOT88_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE88 CCM_PRE88_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT88_SET CCM_PRE_ROOT88_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT88_CLR CCM_PRE_ROOT88_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT88_TOG CCM_PRE_ROOT88_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL88 CCM_ACCESS_CTRL88_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT88_SET CCM_ACCESS_CTRL88_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT88_CLR CCM_ACCESS_CTRL88_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT88_TOG CCM_ACCESS_CTRL88_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT89 CCM_TARGET_ROOT89_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT89_SET CCM_TARGET_ROOT89_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT89_CLR CCM_TARGET_ROOT89_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT89_TOG CCM_TARGET_ROOT89_TOG_REG(CCM_BASE_PTR) +#define CCM_POST89 CCM_POST89_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT89_SET CCM_POST_ROOT89_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT89_CLR CCM_POST_ROOT89_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT89_TOG CCM_POST_ROOT89_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE89 CCM_PRE89_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT89_SET CCM_PRE_ROOT89_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT89_CLR CCM_PRE_ROOT89_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT89_TOG CCM_PRE_ROOT89_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL89 CCM_ACCESS_CTRL89_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT89_SET CCM_ACCESS_CTRL89_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT89_CLR CCM_ACCESS_CTRL89_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT89_TOG CCM_ACCESS_CTRL89_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT90 CCM_TARGET_ROOT90_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT90_SET CCM_TARGET_ROOT90_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT90_CLR CCM_TARGET_ROOT90_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT90_TOG CCM_TARGET_ROOT90_TOG_REG(CCM_BASE_PTR) +#define CCM_POST90 CCM_POST90_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT90_SET CCM_POST_ROOT90_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT90_CLR CCM_POST_ROOT90_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT90_TOG CCM_POST_ROOT90_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE90 CCM_PRE90_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT90_SET CCM_PRE_ROOT90_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT90_CLR CCM_PRE_ROOT90_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT90_TOG CCM_PRE_ROOT90_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL90 CCM_ACCESS_CTRL90_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT90_SET CCM_ACCESS_CTRL90_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT90_CLR CCM_ACCESS_CTRL90_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT90_TOG CCM_ACCESS_CTRL90_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT91 CCM_TARGET_ROOT91_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT91_SET CCM_TARGET_ROOT91_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT91_CLR CCM_TARGET_ROOT91_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT91_TOG CCM_TARGET_ROOT91_TOG_REG(CCM_BASE_PTR) +#define CCM_POST91 CCM_POST91_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT91_SET CCM_POST_ROOT91_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT91_CLR CCM_POST_ROOT91_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT91_TOG CCM_POST_ROOT91_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE91 CCM_PRE91_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT91_SET CCM_PRE_ROOT91_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT91_CLR CCM_PRE_ROOT91_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT91_TOG CCM_PRE_ROOT91_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL91 CCM_ACCESS_CTRL91_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT91_SET CCM_ACCESS_CTRL91_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT91_CLR CCM_ACCESS_CTRL91_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT91_TOG CCM_ACCESS_CTRL91_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT92 CCM_TARGET_ROOT92_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT92_SET CCM_TARGET_ROOT92_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT92_CLR CCM_TARGET_ROOT92_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT92_TOG CCM_TARGET_ROOT92_TOG_REG(CCM_BASE_PTR) +#define CCM_POST92 CCM_POST92_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT92_SET CCM_POST_ROOT92_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT92_CLR CCM_POST_ROOT92_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT92_TOG CCM_POST_ROOT92_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE92 CCM_PRE92_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT92_SET CCM_PRE_ROOT92_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT92_CLR CCM_PRE_ROOT92_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT92_TOG CCM_PRE_ROOT92_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL92 CCM_ACCESS_CTRL92_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT92_SET CCM_ACCESS_CTRL92_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT92_CLR CCM_ACCESS_CTRL92_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT92_TOG CCM_ACCESS_CTRL92_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT93 CCM_TARGET_ROOT93_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT93_SET CCM_TARGET_ROOT93_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT93_CLR CCM_TARGET_ROOT93_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT93_TOG CCM_TARGET_ROOT93_TOG_REG(CCM_BASE_PTR) +#define CCM_POST93 CCM_POST93_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT93_SET CCM_POST_ROOT93_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT93_CLR CCM_POST_ROOT93_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT93_TOG CCM_POST_ROOT93_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE93 CCM_PRE93_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT93_SET CCM_PRE_ROOT93_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT93_CLR CCM_PRE_ROOT93_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT93_TOG CCM_PRE_ROOT93_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL93 CCM_ACCESS_CTRL93_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT93_SET CCM_ACCESS_CTRL93_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT93_CLR CCM_ACCESS_CTRL93_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT93_TOG CCM_ACCESS_CTRL93_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT94 CCM_TARGET_ROOT94_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT94_SET CCM_TARGET_ROOT94_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT94_CLR CCM_TARGET_ROOT94_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT94_TOG CCM_TARGET_ROOT94_TOG_REG(CCM_BASE_PTR) +#define CCM_POST94 CCM_POST94_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT94_SET CCM_POST_ROOT94_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT94_CLR CCM_POST_ROOT94_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT94_TOG CCM_POST_ROOT94_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE94 CCM_PRE94_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT94_SET CCM_PRE_ROOT94_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT94_CLR CCM_PRE_ROOT94_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT94_TOG CCM_PRE_ROOT94_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL94 CCM_ACCESS_CTRL94_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT94_SET CCM_ACCESS_CTRL94_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT94_CLR CCM_ACCESS_CTRL94_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT94_TOG CCM_ACCESS_CTRL94_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT95 CCM_TARGET_ROOT95_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT95_SET CCM_TARGET_ROOT95_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT95_CLR CCM_TARGET_ROOT95_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT95_TOG CCM_TARGET_ROOT95_TOG_REG(CCM_BASE_PTR) +#define CCM_POST95 CCM_POST95_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT95_SET CCM_POST_ROOT95_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT95_CLR CCM_POST_ROOT95_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT95_TOG CCM_POST_ROOT95_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE95 CCM_PRE95_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT95_SET CCM_PRE_ROOT95_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT95_CLR CCM_PRE_ROOT95_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT95_TOG CCM_PRE_ROOT95_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL95 CCM_ACCESS_CTRL95_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT95_SET CCM_ACCESS_CTRL95_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT95_CLR CCM_ACCESS_CTRL95_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT95_TOG CCM_ACCESS_CTRL95_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT96 CCM_TARGET_ROOT96_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT96_SET CCM_TARGET_ROOT96_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT96_CLR CCM_TARGET_ROOT96_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT96_TOG CCM_TARGET_ROOT96_TOG_REG(CCM_BASE_PTR) +#define CCM_POST96 CCM_POST96_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT96_SET CCM_POST_ROOT96_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT96_CLR CCM_POST_ROOT96_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT96_TOG CCM_POST_ROOT96_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE96 CCM_PRE96_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT96_SET CCM_PRE_ROOT96_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT96_CLR CCM_PRE_ROOT96_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT96_TOG CCM_PRE_ROOT96_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL96 CCM_ACCESS_CTRL96_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT96_SET CCM_ACCESS_CTRL96_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT96_CLR CCM_ACCESS_CTRL96_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT96_TOG CCM_ACCESS_CTRL96_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT97 CCM_TARGET_ROOT97_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT97_SET CCM_TARGET_ROOT97_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT97_CLR CCM_TARGET_ROOT97_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT97_TOG CCM_TARGET_ROOT97_TOG_REG(CCM_BASE_PTR) +#define CCM_POST97 CCM_POST97_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT97_SET CCM_POST_ROOT97_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT97_CLR CCM_POST_ROOT97_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT97_TOG CCM_POST_ROOT97_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE97 CCM_PRE97_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT97_SET CCM_PRE_ROOT97_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT97_CLR CCM_PRE_ROOT97_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT97_TOG CCM_PRE_ROOT97_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL97 CCM_ACCESS_CTRL97_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT97_SET CCM_ACCESS_CTRL97_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT97_CLR CCM_ACCESS_CTRL97_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT97_TOG CCM_ACCESS_CTRL97_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT98 CCM_TARGET_ROOT98_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT98_SET CCM_TARGET_ROOT98_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT98_CLR CCM_TARGET_ROOT98_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT98_TOG CCM_TARGET_ROOT98_TOG_REG(CCM_BASE_PTR) +#define CCM_POST98 CCM_POST98_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT98_SET CCM_POST_ROOT98_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT98_CLR CCM_POST_ROOT98_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT98_TOG CCM_POST_ROOT98_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE98 CCM_PRE98_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT98_SET CCM_PRE_ROOT98_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT98_CLR CCM_PRE_ROOT98_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT98_TOG CCM_PRE_ROOT98_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL98 CCM_ACCESS_CTRL98_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT98_SET CCM_ACCESS_CTRL98_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT98_CLR CCM_ACCESS_CTRL98_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT98_TOG CCM_ACCESS_CTRL98_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT99 CCM_TARGET_ROOT99_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT99_SET CCM_TARGET_ROOT99_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT99_CLR CCM_TARGET_ROOT99_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT99_TOG CCM_TARGET_ROOT99_TOG_REG(CCM_BASE_PTR) +#define CCM_POST99 CCM_POST99_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT99_SET CCM_POST_ROOT99_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT99_CLR CCM_POST_ROOT99_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT99_TOG CCM_POST_ROOT99_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE99 CCM_PRE99_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT99_SET CCM_PRE_ROOT99_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT99_CLR CCM_PRE_ROOT99_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT99_TOG CCM_PRE_ROOT99_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL99 CCM_ACCESS_CTRL99_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT99_SET CCM_ACCESS_CTRL99_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT99_CLR CCM_ACCESS_CTRL99_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT99_TOG CCM_ACCESS_CTRL99_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT100 CCM_TARGET_ROOT100_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT100_SET CCM_TARGET_ROOT100_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT100_CLR CCM_TARGET_ROOT100_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT100_TOG CCM_TARGET_ROOT100_TOG_REG(CCM_BASE_PTR) +#define CCM_POST100 CCM_POST100_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT100_SET CCM_POST_ROOT100_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT100_CLR CCM_POST_ROOT100_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT100_TOG CCM_POST_ROOT100_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE100 CCM_PRE100_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT100_SET CCM_PRE_ROOT100_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT100_CLR CCM_PRE_ROOT100_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT100_TOG CCM_PRE_ROOT100_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL100 CCM_ACCESS_CTRL100_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT100_SET CCM_ACCESS_CTRL100_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT100_CLR CCM_ACCESS_CTRL100_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT100_TOG CCM_ACCESS_CTRL100_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT101 CCM_TARGET_ROOT101_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT101_SET CCM_TARGET_ROOT101_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT101_CLR CCM_TARGET_ROOT101_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT101_TOG CCM_TARGET_ROOT101_TOG_REG(CCM_BASE_PTR) +#define CCM_POST101 CCM_POST101_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT101_SET CCM_POST_ROOT101_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT101_CLR CCM_POST_ROOT101_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT101_TOG CCM_POST_ROOT101_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE101 CCM_PRE101_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT101_SET CCM_PRE_ROOT101_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT101_CLR CCM_PRE_ROOT101_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT101_TOG CCM_PRE_ROOT101_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL101 CCM_ACCESS_CTRL101_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT101_SET CCM_ACCESS_CTRL101_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT101_CLR CCM_ACCESS_CTRL101_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT101_TOG CCM_ACCESS_CTRL101_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT102 CCM_TARGET_ROOT102_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT102_SET CCM_TARGET_ROOT102_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT102_CLR CCM_TARGET_ROOT102_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT102_TOG CCM_TARGET_ROOT102_TOG_REG(CCM_BASE_PTR) +#define CCM_POST102 CCM_POST102_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT102_SET CCM_POST_ROOT102_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT102_CLR CCM_POST_ROOT102_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT102_TOG CCM_POST_ROOT102_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE102 CCM_PRE102_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT102_SET CCM_PRE_ROOT102_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT102_CLR CCM_PRE_ROOT102_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT102_TOG CCM_PRE_ROOT102_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL102 CCM_ACCESS_CTRL102_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT102_SET CCM_ACCESS_CTRL102_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT102_CLR CCM_ACCESS_CTRL102_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT102_TOG CCM_ACCESS_CTRL102_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT103 CCM_TARGET_ROOT103_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT103_SET CCM_TARGET_ROOT103_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT103_CLR CCM_TARGET_ROOT103_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT103_TOG CCM_TARGET_ROOT103_TOG_REG(CCM_BASE_PTR) +#define CCM_POST103 CCM_POST103_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT103_SET CCM_POST_ROOT103_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT103_CLR CCM_POST_ROOT103_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT103_TOG CCM_POST_ROOT103_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE103 CCM_PRE103_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT103_SET CCM_PRE_ROOT103_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT103_CLR CCM_PRE_ROOT103_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT103_TOG CCM_PRE_ROOT103_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL103 CCM_ACCESS_CTRL103_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT103_SET CCM_ACCESS_CTRL103_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT103_CLR CCM_ACCESS_CTRL103_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT103_TOG CCM_ACCESS_CTRL103_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT104 CCM_TARGET_ROOT104_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT104_SET CCM_TARGET_ROOT104_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT104_CLR CCM_TARGET_ROOT104_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT104_TOG CCM_TARGET_ROOT104_TOG_REG(CCM_BASE_PTR) +#define CCM_POST104 CCM_POST104_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT104_SET CCM_POST_ROOT104_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT104_CLR CCM_POST_ROOT104_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT104_TOG CCM_POST_ROOT104_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE104 CCM_PRE104_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT104_SET CCM_PRE_ROOT104_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT104_CLR CCM_PRE_ROOT104_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT104_TOG CCM_PRE_ROOT104_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL104 CCM_ACCESS_CTRL104_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT104_SET CCM_ACCESS_CTRL104_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT104_CLR CCM_ACCESS_CTRL104_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT104_TOG CCM_ACCESS_CTRL104_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT105 CCM_TARGET_ROOT105_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT105_SET CCM_TARGET_ROOT105_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT105_CLR CCM_TARGET_ROOT105_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT105_TOG CCM_TARGET_ROOT105_TOG_REG(CCM_BASE_PTR) +#define CCM_POST105 CCM_POST105_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT105_SET CCM_POST_ROOT105_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT105_CLR CCM_POST_ROOT105_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT105_TOG CCM_POST_ROOT105_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE105 CCM_PRE105_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT105_SET CCM_PRE_ROOT105_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT105_CLR CCM_PRE_ROOT105_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT105_TOG CCM_PRE_ROOT105_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL105 CCM_ACCESS_CTRL105_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT105_SET CCM_ACCESS_CTRL105_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT105_CLR CCM_ACCESS_CTRL105_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT105_TOG CCM_ACCESS_CTRL105_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT106 CCM_TARGET_ROOT106_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT106_SET CCM_TARGET_ROOT106_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT106_CLR CCM_TARGET_ROOT106_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT106_TOG CCM_TARGET_ROOT106_TOG_REG(CCM_BASE_PTR) +#define CCM_POST106 CCM_POST106_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT106_SET CCM_POST_ROOT106_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT106_CLR CCM_POST_ROOT106_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT106_TOG CCM_POST_ROOT106_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE106 CCM_PRE106_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT106_SET CCM_PRE_ROOT106_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT106_CLR CCM_PRE_ROOT106_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT106_TOG CCM_PRE_ROOT106_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL106 CCM_ACCESS_CTRL106_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT106_SET CCM_ACCESS_CTRL106_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT106_CLR CCM_ACCESS_CTRL106_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT106_TOG CCM_ACCESS_CTRL106_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT107 CCM_TARGET_ROOT107_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT107_SET CCM_TARGET_ROOT107_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT107_CLR CCM_TARGET_ROOT107_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT107_TOG CCM_TARGET_ROOT107_TOG_REG(CCM_BASE_PTR) +#define CCM_POST107 CCM_POST107_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT107_SET CCM_POST_ROOT107_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT107_CLR CCM_POST_ROOT107_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT107_TOG CCM_POST_ROOT107_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE107 CCM_PRE107_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT107_SET CCM_PRE_ROOT107_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT107_CLR CCM_PRE_ROOT107_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT107_TOG CCM_PRE_ROOT107_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL107 CCM_ACCESS_CTRL107_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT107_SET CCM_ACCESS_CTRL107_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT107_CLR CCM_ACCESS_CTRL107_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT107_TOG CCM_ACCESS_CTRL107_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT108 CCM_TARGET_ROOT108_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT108_SET CCM_TARGET_ROOT108_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT108_CLR CCM_TARGET_ROOT108_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT108_TOG CCM_TARGET_ROOT108_TOG_REG(CCM_BASE_PTR) +#define CCM_POST108 CCM_POST108_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT108_SET CCM_POST_ROOT108_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT108_CLR CCM_POST_ROOT108_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT108_TOG CCM_POST_ROOT108_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE108 CCM_PRE108_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT108_SET CCM_PRE_ROOT108_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT108_CLR CCM_PRE_ROOT108_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT108_TOG CCM_PRE_ROOT108_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL108 CCM_ACCESS_CTRL108_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT108_SET CCM_ACCESS_CTRL108_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT108_CLR CCM_ACCESS_CTRL108_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT108_TOG CCM_ACCESS_CTRL108_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT109 CCM_TARGET_ROOT109_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT109_SET CCM_TARGET_ROOT109_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT109_CLR CCM_TARGET_ROOT109_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT109_TOG CCM_TARGET_ROOT109_TOG_REG(CCM_BASE_PTR) +#define CCM_POST109 CCM_POST109_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT109_SET CCM_POST_ROOT109_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT109_CLR CCM_POST_ROOT109_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT109_TOG CCM_POST_ROOT109_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE109 CCM_PRE109_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT109_SET CCM_PRE_ROOT109_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT109_CLR CCM_PRE_ROOT109_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT109_TOG CCM_PRE_ROOT109_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL109 CCM_ACCESS_CTRL109_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT109_SET CCM_ACCESS_CTRL109_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT109_CLR CCM_ACCESS_CTRL109_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT109_TOG CCM_ACCESS_CTRL109_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT110 CCM_TARGET_ROOT110_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT110_SET CCM_TARGET_ROOT110_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT110_CLR CCM_TARGET_ROOT110_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT110_TOG CCM_TARGET_ROOT110_TOG_REG(CCM_BASE_PTR) +#define CCM_POST110 CCM_POST110_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT110_SET CCM_POST_ROOT110_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT110_CLR CCM_POST_ROOT110_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT110_TOG CCM_POST_ROOT110_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE110 CCM_PRE110_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT110_SET CCM_PRE_ROOT110_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT110_CLR CCM_PRE_ROOT110_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT110_TOG CCM_PRE_ROOT110_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL110 CCM_ACCESS_CTRL110_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT110_SET CCM_ACCESS_CTRL110_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT110_CLR CCM_ACCESS_CTRL110_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT110_TOG CCM_ACCESS_CTRL110_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT111 CCM_TARGET_ROOT111_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT111_SET CCM_TARGET_ROOT111_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT111_CLR CCM_TARGET_ROOT111_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT111_TOG CCM_TARGET_ROOT111_TOG_REG(CCM_BASE_PTR) +#define CCM_POST111 CCM_POST111_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT111_SET CCM_POST_ROOT111_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT111_CLR CCM_POST_ROOT111_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT111_TOG CCM_POST_ROOT111_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE111 CCM_PRE111_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT111_SET CCM_PRE_ROOT111_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT111_CLR CCM_PRE_ROOT111_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT111_TOG CCM_PRE_ROOT111_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL111 CCM_ACCESS_CTRL111_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT111_SET CCM_ACCESS_CTRL111_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT111_CLR CCM_ACCESS_CTRL111_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT111_TOG CCM_ACCESS_CTRL111_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT112 CCM_TARGET_ROOT112_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT112_SET CCM_TARGET_ROOT112_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT112_CLR CCM_TARGET_ROOT112_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT112_TOG CCM_TARGET_ROOT112_TOG_REG(CCM_BASE_PTR) +#define CCM_POST112 CCM_POST112_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT112_SET CCM_POST_ROOT112_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT112_CLR CCM_POST_ROOT112_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT112_TOG CCM_POST_ROOT112_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE112 CCM_PRE112_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT112_SET CCM_PRE_ROOT112_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT112_CLR CCM_PRE_ROOT112_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT112_TOG CCM_PRE_ROOT112_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL112 CCM_ACCESS_CTRL112_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT112_SET CCM_ACCESS_CTRL112_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT112_CLR CCM_ACCESS_CTRL112_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT112_TOG CCM_ACCESS_CTRL112_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT113 CCM_TARGET_ROOT113_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT113_SET CCM_TARGET_ROOT113_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT113_CLR CCM_TARGET_ROOT113_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT113_TOG CCM_TARGET_ROOT113_TOG_REG(CCM_BASE_PTR) +#define CCM_POST113 CCM_POST113_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT113_SET CCM_POST_ROOT113_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT113_CLR CCM_POST_ROOT113_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT113_TOG CCM_POST_ROOT113_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE113 CCM_PRE113_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT113_SET CCM_PRE_ROOT113_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT113_CLR CCM_PRE_ROOT113_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT113_TOG CCM_PRE_ROOT113_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL113 CCM_ACCESS_CTRL113_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT113_SET CCM_ACCESS_CTRL113_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT113_CLR CCM_ACCESS_CTRL113_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT113_TOG CCM_ACCESS_CTRL113_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT114 CCM_TARGET_ROOT114_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT114_SET CCM_TARGET_ROOT114_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT114_CLR CCM_TARGET_ROOT114_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT114_TOG CCM_TARGET_ROOT114_TOG_REG(CCM_BASE_PTR) +#define CCM_POST114 CCM_POST114_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT114_SET CCM_POST_ROOT114_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT114_CLR CCM_POST_ROOT114_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT114_TOG CCM_POST_ROOT114_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE114 CCM_PRE114_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT114_SET CCM_PRE_ROOT114_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT114_CLR CCM_PRE_ROOT114_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT114_TOG CCM_PRE_ROOT114_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL114 CCM_ACCESS_CTRL114_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT114_SET CCM_ACCESS_CTRL114_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT114_CLR CCM_ACCESS_CTRL114_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT114_TOG CCM_ACCESS_CTRL114_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT115 CCM_TARGET_ROOT115_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT115_SET CCM_TARGET_ROOT115_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT115_CLR CCM_TARGET_ROOT115_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT115_TOG CCM_TARGET_ROOT115_TOG_REG(CCM_BASE_PTR) +#define CCM_POST115 CCM_POST115_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT115_SET CCM_POST_ROOT115_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT115_CLR CCM_POST_ROOT115_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT115_TOG CCM_POST_ROOT115_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE115 CCM_PRE115_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT115_SET CCM_PRE_ROOT115_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT115_CLR CCM_PRE_ROOT115_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT115_TOG CCM_PRE_ROOT115_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL115 CCM_ACCESS_CTRL115_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT115_SET CCM_ACCESS_CTRL115_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT115_CLR CCM_ACCESS_CTRL115_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT115_TOG CCM_ACCESS_CTRL115_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT116 CCM_TARGET_ROOT116_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT116_SET CCM_TARGET_ROOT116_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT116_CLR CCM_TARGET_ROOT116_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT116_TOG CCM_TARGET_ROOT116_TOG_REG(CCM_BASE_PTR) +#define CCM_POST116 CCM_POST116_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT116_SET CCM_POST_ROOT116_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT116_CLR CCM_POST_ROOT116_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT116_TOG CCM_POST_ROOT116_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE116 CCM_PRE116_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT116_SET CCM_PRE_ROOT116_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT116_CLR CCM_PRE_ROOT116_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT116_TOG CCM_PRE_ROOT116_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL116 CCM_ACCESS_CTRL116_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT116_SET CCM_ACCESS_CTRL116_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT116_CLR CCM_ACCESS_CTRL116_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT116_TOG CCM_ACCESS_CTRL116_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT117 CCM_TARGET_ROOT117_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT117_SET CCM_TARGET_ROOT117_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT117_CLR CCM_TARGET_ROOT117_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT117_TOG CCM_TARGET_ROOT117_TOG_REG(CCM_BASE_PTR) +#define CCM_POST117 CCM_POST117_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT117_SET CCM_POST_ROOT117_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT117_CLR CCM_POST_ROOT117_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT117_TOG CCM_POST_ROOT117_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE117 CCM_PRE117_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT117_SET CCM_PRE_ROOT117_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT117_CLR CCM_PRE_ROOT117_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT117_TOG CCM_PRE_ROOT117_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL117 CCM_ACCESS_CTRL117_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT117_SET CCM_ACCESS_CTRL117_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT117_CLR CCM_ACCESS_CTRL117_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT117_TOG CCM_ACCESS_CTRL117_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT118 CCM_TARGET_ROOT118_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT118_SET CCM_TARGET_ROOT118_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT118_CLR CCM_TARGET_ROOT118_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT118_TOG CCM_TARGET_ROOT118_TOG_REG(CCM_BASE_PTR) +#define CCM_POST118 CCM_POST118_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT118_SET CCM_POST_ROOT118_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT118_CLR CCM_POST_ROOT118_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT118_TOG CCM_POST_ROOT118_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE118 CCM_PRE118_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT118_SET CCM_PRE_ROOT118_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT118_CLR CCM_PRE_ROOT118_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT118_TOG CCM_PRE_ROOT118_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL118 CCM_ACCESS_CTRL118_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT118_SET CCM_ACCESS_CTRL118_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT118_CLR CCM_ACCESS_CTRL118_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT118_TOG CCM_ACCESS_CTRL118_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT119 CCM_TARGET_ROOT119_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT119_SET CCM_TARGET_ROOT119_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT119_CLR CCM_TARGET_ROOT119_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT119_TOG CCM_TARGET_ROOT119_TOG_REG(CCM_BASE_PTR) +#define CCM_POST119 CCM_POST119_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT119_SET CCM_POST_ROOT119_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT119_CLR CCM_POST_ROOT119_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT119_TOG CCM_POST_ROOT119_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE119 CCM_PRE119_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT119_SET CCM_PRE_ROOT119_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT119_CLR CCM_PRE_ROOT119_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT119_TOG CCM_PRE_ROOT119_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL119 CCM_ACCESS_CTRL119_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT119_SET CCM_ACCESS_CTRL119_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT119_CLR CCM_ACCESS_CTRL119_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT119_TOG CCM_ACCESS_CTRL119_ROOT_TOG_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT120 CCM_TARGET_ROOT120_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT120_SET CCM_TARGET_ROOT120_SET_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT120_CLR CCM_TARGET_ROOT120_CLR_REG(CCM_BASE_PTR) +#define CCM_TARGET_ROOT120_TOG CCM_TARGET_ROOT120_TOG_REG(CCM_BASE_PTR) +#define CCM_POST120 CCM_POST120_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT120_SET CCM_POST_ROOT120_SET_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT120_CLR CCM_POST_ROOT120_CLR_REG(CCM_BASE_PTR) +#define CCM_POST_ROOT120_TOG CCM_POST_ROOT120_TOG_REG(CCM_BASE_PTR) +#define CCM_PRE120 CCM_PRE120_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT120_SET CCM_PRE_ROOT120_SET_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT120_CLR CCM_PRE_ROOT120_CLR_REG(CCM_BASE_PTR) +#define CCM_PRE_ROOT120_TOG CCM_PRE_ROOT120_TOG_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL120 CCM_ACCESS_CTRL120_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT120_SET CCM_ACCESS_CTRL120_ROOT_SET_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT120_CLR CCM_ACCESS_CTRL120_ROOT_CLR_REG(CCM_BASE_PTR) +#define CCM_ACCESS_CTRL_ROOT120_TOG CCM_ACCESS_CTRL120_ROOT_TOG_REG(CCM_BASE_PTR) + +/*! + * @} + */ /* end of group CCM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group CCM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[96]; + __IO uint32_t PLL_ARM; /**< Anadig ARM PLL control Register, offset: 0x60 */ + __IO uint32_t PLL_ARM_SET; /**< Anadig ARM PLL control Register, offset: 0x64 */ + __IO uint32_t PLL_ARM_CLR; /**< Anadig ARM PLL control Register, offset: 0x68 */ + __IO uint32_t PLL_ARM_TOG; /**< Anadig ARM PLL control Register, offset: 0x6C */ + __IO uint32_t PLL_DDR; /**< Anadig DDR PLL Control Register, offset: 0x70 */ + __IO uint32_t PLL_DDR_SET; /**< Anadig DDR PLL Control Register, offset: 0x74 */ + __IO uint32_t PLL_DDR_CLR; /**< Anadig DDR PLL Control Register, offset: 0x78 */ + __IO uint32_t PLL_DDR_TOG; /**< Anadig DDR PLL Control Register, offset: 0x7C */ + __IO uint32_t PLL_DDR_SS; /**< DDR PLL Spread Spectrum Register., offset: 0x80 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_DDR_NUM; /**< Numerator of DDR PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_DDR_DENOM; /**< Denominator of DDR PLL Fractional Loop Divider Register, offset: 0xA0 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_480; /**< Anadig 480MHz PLL Control Register, offset: 0xB0 */ + __IO uint32_t PLL_480_SET; /**< Anadig 480MHz PLL Control Register, offset: 0xB4 */ + __IO uint32_t PLL_480_CLR; /**< Anadig 480MHz PLL Control Register, offset: 0xB8 */ + __IO uint32_t PLL_480_TOG; /**< Anadig 480MHz PLL Control Register, offset: 0xBC */ + __IO uint32_t PFD_480A; /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xC0 */ + __IO uint32_t PFD_480A_SET; /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xC4 */ + __IO uint32_t PFD_480A_CLR; /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xC8 */ + __IO uint32_t PFD_480A_TOG; /**< 480MHz Clock Phase Fractional Divider Control Register A, offset: 0xCC */ + __IO uint32_t PFD_480B; /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xD0 */ + __IO uint32_t PFD_480B_SET; /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xD4 */ + __IO uint32_t PFD_480B_CLR; /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xD8 */ + __IO uint32_t PFD_480B_TOG; /**< 480MHz Clock Phase Fractional Divider Control Register B, offset: 0xDC */ + __IO uint32_t PLL_ENET; /**< Anadig ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Anadig ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Anadig ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Anadig ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PLL_AUDIO; /**< Anadig Audio PLL control Register, offset: 0xF0 */ + __IO uint32_t PLL_AUDIO_SET; /**< Anadig Audio PLL control Register, offset: 0xF4 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Anadig Audio PLL control Register, offset: 0xF8 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Anadig Audio PLL control Register, offset: 0xFC */ + __IO uint32_t PLL_AUDIO_SS; /**< Audio PLL Spread Spectrum Register., offset: 0x100 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x110 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x120 */ + uint8_t RESERVED_6[12]; + __IO uint32_t PLL_VIDEO; /**< Anadig Video PLL control Register, offset: 0x130 */ + __IO uint32_t PLL_VIDEO_SET; /**< Anadig Video PLL control Register, offset: 0x134 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Anadig Video PLL control Register, offset: 0x138 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Anadig Video PLL control Register, offset: 0x13C */ + __IO uint32_t PLL_VIDEO_SS; /**< Video PLL Spread Spectrum Register., offset: 0x140 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0x150 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0x160 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CLK_MISC0; /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x170 */ + __IO uint32_t CLK_MISC0_SET; /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x174 */ + __IO uint32_t CLK_MISC0_CLR; /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x178 */ + __IO uint32_t CLK_MISC0_TOG; /**< Miscellaneous0 Analog Clock Control and Status Register, offset: 0x17C */ +} CCM_ANALOG_Type, *CCM_ANALOG_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros + * @{ + */ + + +/* CCM_ANALOG - Register accessors */ +#define CCM_ANALOG_PLL_ARM_REG(base) ((base)->PLL_ARM) +#define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) +#define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) +#define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) +#define CCM_ANALOG_PLL_DDR_REG(base) ((base)->PLL_DDR) +#define CCM_ANALOG_PLL_DDR_SET_REG(base) ((base)->PLL_DDR_SET) +#define CCM_ANALOG_PLL_DDR_CLR_REG(base) ((base)->PLL_DDR_CLR) +#define CCM_ANALOG_PLL_DDR_TOG_REG(base) ((base)->PLL_DDR_TOG) +#define CCM_ANALOG_PLL_DDR_SS_REG(base) ((base)->PLL_DDR_SS) +#define CCM_ANALOG_PLL_DDR_NUM_REG(base) ((base)->PLL_DDR_NUM) +#define CCM_ANALOG_PLL_DDR_DENOM_REG(base) ((base)->PLL_DDR_DENOM) +#define CCM_ANALOG_PLL_480_REG(base) ((base)->PLL_480) +#define CCM_ANALOG_PLL_480_SET_REG(base) ((base)->PLL_480_SET) +#define CCM_ANALOG_PLL_480_CLR_REG(base) ((base)->PLL_480_CLR) +#define CCM_ANALOG_PLL_480_TOG_REG(base) ((base)->PLL_480_TOG) +#define CCM_ANALOG_PFD_480A_REG(base) ((base)->PFD_480A) +#define CCM_ANALOG_PFD_480A_SET_REG(base) ((base)->PFD_480A_SET) +#define CCM_ANALOG_PFD_480A_CLR_REG(base) ((base)->PFD_480A_CLR) +#define CCM_ANALOG_PFD_480A_TOG_REG(base) ((base)->PFD_480A_TOG) +#define CCM_ANALOG_PFD_480B_REG(base) ((base)->PFD_480B) +#define CCM_ANALOG_PFD_480B_SET_REG(base) ((base)->PFD_480B_SET) +#define CCM_ANALOG_PFD_480B_CLR_REG(base) ((base)->PFD_480B_CLR) +#define CCM_ANALOG_PFD_480B_TOG_REG(base) ((base)->PFD_480B_TOG) +#define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) +#define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) +#define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) +#define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) +#define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) +#define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) +#define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) +#define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) +#define CCM_ANALOG_PLL_AUDIO_SS_REG(base) ((base)->PLL_AUDIO_SS) +#define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) +#define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) +#define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) +#define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) +#define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) +#define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) +#define CCM_ANALOG_PLL_VIDEO_SS_REG(base) ((base)->PLL_VIDEO_SS) +#define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) +#define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) +#define CCM_ANALOG_CLK_MISC0_REG(base) ((base)->CLK_MISC0) +#define CCM_ANALOG_CLK_MISC0_SET_REG(base) ((base)->CLK_MISC0_SET) +#define CCM_ANALOG_CLK_MISC0_CLR_REG(base) ((base)->CLK_MISC0_CLR) +#define CCM_ANALOG_CLK_MISC0_TOG_REG(base) ((base)->CLK_MISC0_TOG) + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000u +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000u +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000u +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000u +#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_ARM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_RSVD0_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 +/* PLL_ARM_SET Bit Fields */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_ARM_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_ARM_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_ARM_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_ARM_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_ARM_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_ARM_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_ARM_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_ARM_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_ARM_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_MASK 0x20000u +#define CCM_ANALOG_PLL_ARM_SET_LVDS_SEL_SHIFT 17 +#define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_MASK 0x40000u +#define CCM_ANALOG_PLL_ARM_SET_LVDS_24MHZ_SEL_SHIFT 18 +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK 0x80000u +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT 19 +#define CCM_ANALOG_PLL_ARM_SET_PLL_ARM_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_ARM_SET_PLL_ARM_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_ARM_SET_RSVD0_MASK 0x7FE00000u +#define CCM_ANALOG_PLL_ARM_SET_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_ARM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_SET_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_SET_RSVD0_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT 31 +/* PLL_ARM_CLR Bit Fields */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_ARM_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_ARM_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_ARM_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_ARM_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_ARM_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_ARM_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_MASK 0x20000u +#define CCM_ANALOG_PLL_ARM_CLR_LVDS_SEL_SHIFT 17 +#define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_MASK 0x40000u +#define CCM_ANALOG_PLL_ARM_CLR_LVDS_24MHZ_SEL_SHIFT 18 +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK 0x80000u +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT 19 +#define CCM_ANALOG_PLL_ARM_CLR_PLL_ARM_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_ARM_CLR_PLL_ARM_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_ARM_CLR_RSVD0_MASK 0x7FE00000u +#define CCM_ANALOG_PLL_ARM_CLR_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_ARM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_CLR_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_CLR_RSVD0_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT 31 +/* PLL_ARM_TOG Bit Fields */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_ARM_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_ARM_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_ARM_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_ARM_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_ARM_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_ARM_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_MASK 0x20000u +#define CCM_ANALOG_PLL_ARM_TOG_LVDS_SEL_SHIFT 17 +#define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_MASK 0x40000u +#define CCM_ANALOG_PLL_ARM_TOG_LVDS_24MHZ_SEL_SHIFT 18 +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK 0x80000u +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT 19 +#define CCM_ANALOG_PLL_ARM_TOG_PLL_ARM_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_ARM_TOG_PLL_ARM_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_ARM_TOG_RSVD0_MASK 0x7FE00000u +#define CCM_ANALOG_PLL_ARM_TOG_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_ARM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ARM_TOG_RSVD0_SHIFT))&CCM_ANALOG_PLL_ARM_TOG_RSVD0_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT 31 +/* PLL_DDR Bit Fields */ +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000u +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000u +#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000u +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000u +#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 +#define CCM_ANALOG_PLL_DDR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_RSVD1_MASK) +#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 +/* PLL_DDR_SET Bit Fields */ +#define CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_DDR_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_DDR_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_DDR_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_DDR_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_DDR_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_DDR_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_DDR_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_DDR_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_DDR_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_DDR_SET_DIV2_ENABLE_CLK_MASK 0x1000u +#define CCM_ANALOG_PLL_DDR_SET_DIV2_ENABLE_CLK_SHIFT 12 +#define CCM_ANALOG_PLL_DDR_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_DDR_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_DDR_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_DDR_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_DDR_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_DDR_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_DDR_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_DDR_SET_PLL_DDR_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_DDR_SET_PLL_DDR_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_DDR_SET_POWERDOWN_MASK 0x100000u +#define CCM_ANALOG_PLL_DDR_SET_POWERDOWN_SHIFT 20 +#define CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_MASK 0x600000u +#define CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_SHIFT 21 +#define CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_SET_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_SET_RSVD1_MASK 0x7F800000u +#define CCM_ANALOG_PLL_DDR_SET_RSVD1_SHIFT 23 +#define CCM_ANALOG_PLL_DDR_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_DDR_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_DDR_SET_LOCK_SHIFT 31 +/* PLL_DDR_CLR Bit Fields */ +#define CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_DDR_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_DDR_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_DDR_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_DDR_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_DDR_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_DDR_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_DDR_CLR_DIV2_ENABLE_CLK_MASK 0x1000u +#define CCM_ANALOG_PLL_DDR_CLR_DIV2_ENABLE_CLK_SHIFT 12 +#define CCM_ANALOG_PLL_DDR_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_DDR_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_DDR_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_DDR_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_DDR_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_DDR_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_DDR_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_DDR_CLR_PLL_DDR_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_DDR_CLR_PLL_DDR_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_DDR_CLR_POWERDOWN_MASK 0x100000u +#define CCM_ANALOG_PLL_DDR_CLR_POWERDOWN_SHIFT 20 +#define CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_MASK 0x600000u +#define CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_SHIFT 21 +#define CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_CLR_RSVD1_MASK 0x7F800000u +#define CCM_ANALOG_PLL_DDR_CLR_RSVD1_SHIFT 23 +#define CCM_ANALOG_PLL_DDR_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_DDR_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_DDR_CLR_LOCK_SHIFT 31 +/* PLL_DDR_TOG Bit Fields */ +#define CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_DDR_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_DDR_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_DDR_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_DDR_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_DDR_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_DDR_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_DDR_TOG_DIV2_ENABLE_CLK_MASK 0x1000u +#define CCM_ANALOG_PLL_DDR_TOG_DIV2_ENABLE_CLK_SHIFT 12 +#define CCM_ANALOG_PLL_DDR_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_DDR_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_DDR_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_DDR_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_DDR_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_DDR_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_DDR_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_DDR_TOG_PLL_DDR_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_DDR_TOG_PLL_DDR_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_DDR_TOG_POWERDOWN_MASK 0x100000u +#define CCM_ANALOG_PLL_DDR_TOG_POWERDOWN_SHIFT 20 +#define CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_MASK 0x600000u +#define CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_SHIFT 21 +#define CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_DDR_TOG_RSVD1_MASK 0x7F800000u +#define CCM_ANALOG_PLL_DDR_TOG_RSVD1_SHIFT 23 +#define CCM_ANALOG_PLL_DDR_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_DDR_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_DDR_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_DDR_TOG_LOCK_SHIFT 31 +/* PLL_DDR_SS Bit Fields */ +#define CCM_ANALOG_PLL_DDR_SS_STEP_MASK 0x7FFFu +#define CCM_ANALOG_PLL_DDR_SS_STEP_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SS_STEP_SHIFT))&CCM_ANALOG_PLL_DDR_SS_STEP_MASK) +#define CCM_ANALOG_PLL_DDR_SS_ENABLE_MASK 0x8000u +#define CCM_ANALOG_PLL_DDR_SS_ENABLE_SHIFT 15 +#define CCM_ANALOG_PLL_DDR_SS_STOP_MASK 0xFFFF0000u +#define CCM_ANALOG_PLL_DDR_SS_STOP_SHIFT 16 +#define CCM_ANALOG_PLL_DDR_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_SS_STOP_SHIFT))&CCM_ANALOG_PLL_DDR_SS_STOP_MASK) +/* PLL_DDR_NUM Bit Fields */ +#define CCM_ANALOG_PLL_DDR_NUM_A_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_DDR_NUM_A_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_NUM_A_SHIFT))&CCM_ANALOG_PLL_DDR_NUM_A_MASK) +#define CCM_ANALOG_PLL_DDR_NUM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_DDR_NUM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_DDR_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_DDR_NUM_RSVD0_MASK) +/* PLL_DDR_DENOM Bit Fields */ +#define CCM_ANALOG_PLL_DDR_DENOM_B_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_DDR_DENOM_B_SHIFT 0 +#define CCM_ANALOG_PLL_DDR_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_DENOM_B_SHIFT))&CCM_ANALOG_PLL_DDR_DENOM_B_MASK) +#define CCM_ANALOG_PLL_DDR_DENOM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_DDR_DENOM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_DDR_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_DDR_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_DDR_DENOM_RSVD0_MASK) +/* PLL_480 Bit Fields */ +#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1u +#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xEu +#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 +#define CCM_ANALOG_PLL_480_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_RSVD0_MASK) +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10u +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20u +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40u +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 +#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000u +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000u +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000u +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000u +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000u +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000u +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000u +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000u +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000u +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 +#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000u +#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 +#define CCM_ANALOG_PLL_480_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_RSVD1_MASK) +#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 +/* PLL_480_SET Bit Fields */ +#define CCM_ANALOG_PLL_480_SET_DIV_SELECT_MASK 0x1u +#define CCM_ANALOG_PLL_480_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_480_SET_RSVD0_MASK 0xEu +#define CCM_ANALOG_PLL_480_SET_RSVD0_SHIFT 1 +#define CCM_ANALOG_PLL_480_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_SET_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_SET_RSVD0_MASK) +#define CCM_ANALOG_PLL_480_SET_MAIN_DIV1_CLKGATE_MASK 0x10u +#define CCM_ANALOG_PLL_480_SET_MAIN_DIV1_CLKGATE_SHIFT 4 +#define CCM_ANALOG_PLL_480_SET_MAIN_DIV2_CLKGATE_MASK 0x20u +#define CCM_ANALOG_PLL_480_SET_MAIN_DIV2_CLKGATE_SHIFT 5 +#define CCM_ANALOG_PLL_480_SET_MAIN_DIV4_CLKGATE_MASK 0x40u +#define CCM_ANALOG_PLL_480_SET_MAIN_DIV4_CLKGATE_SHIFT 6 +#define CCM_ANALOG_PLL_480_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_480_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_480_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_480_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_480_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_480_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_480_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_480_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_480_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_480_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_480_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_480_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_480_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_480_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_480_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_480_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_480_SET_PLL_480_OVERRIDE_MASK 0x20000u +#define CCM_ANALOG_PLL_480_SET_PLL_480_OVERRIDE_SHIFT 17 +#define CCM_ANALOG_PLL_480_SET_PFD0_OVERRIDE_MASK 0x40000u +#define CCM_ANALOG_PLL_480_SET_PFD0_OVERRIDE_SHIFT 18 +#define CCM_ANALOG_PLL_480_SET_PFD1_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_480_SET_PFD1_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_480_SET_PFD2_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_480_SET_PFD2_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_480_SET_PFD3_OVERRIDE_MASK 0x200000u +#define CCM_ANALOG_PLL_480_SET_PFD3_OVERRIDE_SHIFT 21 +#define CCM_ANALOG_PLL_480_SET_PFD4_OVERRIDE_MASK 0x400000u +#define CCM_ANALOG_PLL_480_SET_PFD4_OVERRIDE_SHIFT 22 +#define CCM_ANALOG_PLL_480_SET_PFD5_OVERRIDE_MASK 0x800000u +#define CCM_ANALOG_PLL_480_SET_PFD5_OVERRIDE_SHIFT 23 +#define CCM_ANALOG_PLL_480_SET_PFD6_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_480_SET_PFD6_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_480_SET_PFD7_OVERRIDE_MASK 0x2000000u +#define CCM_ANALOG_PLL_480_SET_PFD7_OVERRIDE_SHIFT 25 +#define CCM_ANALOG_PLL_480_SET_PFD0_DIV2_CLKGATE_MASK 0x4000000u +#define CCM_ANALOG_PLL_480_SET_PFD0_DIV2_CLKGATE_SHIFT 26 +#define CCM_ANALOG_PLL_480_SET_PFD1_DIV2_CLKGATE_MASK 0x8000000u +#define CCM_ANALOG_PLL_480_SET_PFD1_DIV2_CLKGATE_SHIFT 27 +#define CCM_ANALOG_PLL_480_SET_PFD2_DIV2_CLKGATE_MASK 0x10000000u +#define CCM_ANALOG_PLL_480_SET_PFD2_DIV2_CLKGATE_SHIFT 28 +#define CCM_ANALOG_PLL_480_SET_RSVD1_MASK 0x60000000u +#define CCM_ANALOG_PLL_480_SET_RSVD1_SHIFT 29 +#define CCM_ANALOG_PLL_480_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_480_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_480_SET_LOCK_SHIFT 31 +/* PLL_480_CLR Bit Fields */ +#define CCM_ANALOG_PLL_480_CLR_DIV_SELECT_MASK 0x1u +#define CCM_ANALOG_PLL_480_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_480_CLR_RSVD0_MASK 0xEu +#define CCM_ANALOG_PLL_480_CLR_RSVD0_SHIFT 1 +#define CCM_ANALOG_PLL_480_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_CLR_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_CLR_RSVD0_MASK) +#define CCM_ANALOG_PLL_480_CLR_MAIN_DIV1_CLKGATE_MASK 0x10u +#define CCM_ANALOG_PLL_480_CLR_MAIN_DIV1_CLKGATE_SHIFT 4 +#define CCM_ANALOG_PLL_480_CLR_MAIN_DIV2_CLKGATE_MASK 0x20u +#define CCM_ANALOG_PLL_480_CLR_MAIN_DIV2_CLKGATE_SHIFT 5 +#define CCM_ANALOG_PLL_480_CLR_MAIN_DIV4_CLKGATE_MASK 0x40u +#define CCM_ANALOG_PLL_480_CLR_MAIN_DIV4_CLKGATE_SHIFT 6 +#define CCM_ANALOG_PLL_480_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_480_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_480_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_480_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_480_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_480_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_480_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_480_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_480_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_480_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_480_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_480_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_480_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_480_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_480_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_480_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_480_CLR_PLL_480_OVERRIDE_MASK 0x20000u +#define CCM_ANALOG_PLL_480_CLR_PLL_480_OVERRIDE_SHIFT 17 +#define CCM_ANALOG_PLL_480_CLR_PFD0_OVERRIDE_MASK 0x40000u +#define CCM_ANALOG_PLL_480_CLR_PFD0_OVERRIDE_SHIFT 18 +#define CCM_ANALOG_PLL_480_CLR_PFD1_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_480_CLR_PFD1_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_480_CLR_PFD2_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_480_CLR_PFD2_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_480_CLR_PFD3_OVERRIDE_MASK 0x200000u +#define CCM_ANALOG_PLL_480_CLR_PFD3_OVERRIDE_SHIFT 21 +#define CCM_ANALOG_PLL_480_CLR_PFD4_OVERRIDE_MASK 0x400000u +#define CCM_ANALOG_PLL_480_CLR_PFD4_OVERRIDE_SHIFT 22 +#define CCM_ANALOG_PLL_480_CLR_PFD5_OVERRIDE_MASK 0x800000u +#define CCM_ANALOG_PLL_480_CLR_PFD5_OVERRIDE_SHIFT 23 +#define CCM_ANALOG_PLL_480_CLR_PFD6_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_480_CLR_PFD6_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_480_CLR_PFD7_OVERRIDE_MASK 0x2000000u +#define CCM_ANALOG_PLL_480_CLR_PFD7_OVERRIDE_SHIFT 25 +#define CCM_ANALOG_PLL_480_CLR_PFD0_DIV2_CLKGATE_MASK 0x4000000u +#define CCM_ANALOG_PLL_480_CLR_PFD0_DIV2_CLKGATE_SHIFT 26 +#define CCM_ANALOG_PLL_480_CLR_PFD1_DIV2_CLKGATE_MASK 0x8000000u +#define CCM_ANALOG_PLL_480_CLR_PFD1_DIV2_CLKGATE_SHIFT 27 +#define CCM_ANALOG_PLL_480_CLR_PFD2_DIV2_CLKGATE_MASK 0x10000000u +#define CCM_ANALOG_PLL_480_CLR_PFD2_DIV2_CLKGATE_SHIFT 28 +#define CCM_ANALOG_PLL_480_CLR_RSVD1_MASK 0x60000000u +#define CCM_ANALOG_PLL_480_CLR_RSVD1_SHIFT 29 +#define CCM_ANALOG_PLL_480_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_480_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_480_CLR_LOCK_SHIFT 31 +/* PLL_480_TOG Bit Fields */ +#define CCM_ANALOG_PLL_480_TOG_DIV_SELECT_MASK 0x1u +#define CCM_ANALOG_PLL_480_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_480_TOG_RSVD0_MASK 0xEu +#define CCM_ANALOG_PLL_480_TOG_RSVD0_SHIFT 1 +#define CCM_ANALOG_PLL_480_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_TOG_RSVD0_SHIFT))&CCM_ANALOG_PLL_480_TOG_RSVD0_MASK) +#define CCM_ANALOG_PLL_480_TOG_MAIN_DIV1_CLKGATE_MASK 0x10u +#define CCM_ANALOG_PLL_480_TOG_MAIN_DIV1_CLKGATE_SHIFT 4 +#define CCM_ANALOG_PLL_480_TOG_MAIN_DIV2_CLKGATE_MASK 0x20u +#define CCM_ANALOG_PLL_480_TOG_MAIN_DIV2_CLKGATE_SHIFT 5 +#define CCM_ANALOG_PLL_480_TOG_MAIN_DIV4_CLKGATE_MASK 0x40u +#define CCM_ANALOG_PLL_480_TOG_MAIN_DIV4_CLKGATE_SHIFT 6 +#define CCM_ANALOG_PLL_480_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_480_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_480_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_480_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_480_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_480_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_480_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_480_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_480_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_480_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_480_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_480_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_480_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_480_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_480_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_480_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_480_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_480_TOG_PLL_480_OVERRIDE_MASK 0x20000u +#define CCM_ANALOG_PLL_480_TOG_PLL_480_OVERRIDE_SHIFT 17 +#define CCM_ANALOG_PLL_480_TOG_PFD0_OVERRIDE_MASK 0x40000u +#define CCM_ANALOG_PLL_480_TOG_PFD0_OVERRIDE_SHIFT 18 +#define CCM_ANALOG_PLL_480_TOG_PFD1_OVERRIDE_MASK 0x80000u +#define CCM_ANALOG_PLL_480_TOG_PFD1_OVERRIDE_SHIFT 19 +#define CCM_ANALOG_PLL_480_TOG_PFD2_OVERRIDE_MASK 0x100000u +#define CCM_ANALOG_PLL_480_TOG_PFD2_OVERRIDE_SHIFT 20 +#define CCM_ANALOG_PLL_480_TOG_PFD3_OVERRIDE_MASK 0x200000u +#define CCM_ANALOG_PLL_480_TOG_PFD3_OVERRIDE_SHIFT 21 +#define CCM_ANALOG_PLL_480_TOG_PFD4_OVERRIDE_MASK 0x400000u +#define CCM_ANALOG_PLL_480_TOG_PFD4_OVERRIDE_SHIFT 22 +#define CCM_ANALOG_PLL_480_TOG_PFD5_OVERRIDE_MASK 0x800000u +#define CCM_ANALOG_PLL_480_TOG_PFD5_OVERRIDE_SHIFT 23 +#define CCM_ANALOG_PLL_480_TOG_PFD6_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_480_TOG_PFD6_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_480_TOG_PFD7_OVERRIDE_MASK 0x2000000u +#define CCM_ANALOG_PLL_480_TOG_PFD7_OVERRIDE_SHIFT 25 +#define CCM_ANALOG_PLL_480_TOG_PFD0_DIV2_CLKGATE_MASK 0x4000000u +#define CCM_ANALOG_PLL_480_TOG_PFD0_DIV2_CLKGATE_SHIFT 26 +#define CCM_ANALOG_PLL_480_TOG_PFD1_DIV2_CLKGATE_MASK 0x8000000u +#define CCM_ANALOG_PLL_480_TOG_PFD1_DIV2_CLKGATE_SHIFT 27 +#define CCM_ANALOG_PLL_480_TOG_PFD2_DIV2_CLKGATE_MASK 0x10000000u +#define CCM_ANALOG_PLL_480_TOG_PFD2_DIV2_CLKGATE_SHIFT 28 +#define CCM_ANALOG_PLL_480_TOG_RSVD1_MASK 0x60000000u +#define CCM_ANALOG_PLL_480_TOG_RSVD1_SHIFT 29 +#define CCM_ANALOG_PLL_480_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_480_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_480_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_480_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_480_TOG_LOCK_SHIFT 31 +/* PFD_480A Bit Fields */ +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480A_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480A_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480A_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480A_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 +/* PFD_480A_SET Bit Fields */ +#define CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480A_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_SET_PFD0_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480A_SET_PFD0_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480A_SET_PFD0_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480A_SET_PFD0_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480A_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_SET_PFD1_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480A_SET_PFD1_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480A_SET_PFD1_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480A_SET_PFD1_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480A_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_SET_PFD2_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480A_SET_PFD2_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480A_SET_PFD2_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480A_SET_PFD2_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480A_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_SET_PFD3_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480A_SET_PFD3_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480A_SET_PFD3_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480A_SET_PFD3_DIV1_CLKGATE_SHIFT 31 +/* PFD_480A_CLR Bit Fields */ +#define CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_CLR_PFD0_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480A_CLR_PFD0_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480A_CLR_PFD0_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480A_CLR_PFD0_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_CLR_PFD1_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480A_CLR_PFD1_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480A_CLR_PFD1_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480A_CLR_PFD1_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_CLR_PFD2_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480A_CLR_PFD2_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480A_CLR_PFD2_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480A_CLR_PFD2_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_CLR_PFD3_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480A_CLR_PFD3_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480A_CLR_PFD3_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480A_CLR_PFD3_DIV1_CLKGATE_SHIFT 31 +/* PFD_480A_TOG Bit Fields */ +#define CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_TOG_PFD0_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480A_TOG_PFD0_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480A_TOG_PFD0_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480A_TOG_PFD0_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_TOG_PFD1_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480A_TOG_PFD1_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480A_TOG_PFD1_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480A_TOG_PFD1_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_TOG_PFD2_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480A_TOG_PFD2_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480A_TOG_PFD2_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480A_TOG_PFD2_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_SHIFT))&CCM_ANALOG_PFD_480A_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480A_TOG_PFD3_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480A_TOG_PFD3_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480A_TOG_PFD3_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480A_TOG_PFD3_DIV1_CLKGATE_SHIFT 31 +/* PFD_480B Bit Fields */ +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480B_PFD4_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480B_PFD5_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480B_PFD6_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480B_PFD7_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 +/* PFD_480B_SET Bit Fields */ +#define CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480B_SET_PFD4_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD4_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_SET_PFD4_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480B_SET_PFD4_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480B_SET_PFD4_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480B_SET_PFD4_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480B_SET_PFD5_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD5_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_SET_PFD5_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480B_SET_PFD5_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480B_SET_PFD5_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480B_SET_PFD5_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480B_SET_PFD6_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD6_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_SET_PFD6_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480B_SET_PFD6_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480B_SET_PFD6_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480B_SET_PFD6_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480B_SET_PFD7_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_SET_PFD7_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_SET_PFD7_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480B_SET_PFD7_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480B_SET_PFD7_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480B_SET_PFD7_DIV1_CLKGATE_SHIFT 31 +/* PFD_480B_CLR Bit Fields */ +#define CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD4_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_CLR_PFD4_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480B_CLR_PFD4_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480B_CLR_PFD4_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480B_CLR_PFD4_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD5_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_CLR_PFD5_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480B_CLR_PFD5_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480B_CLR_PFD5_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480B_CLR_PFD5_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD6_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_CLR_PFD6_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480B_CLR_PFD6_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480B_CLR_PFD6_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480B_CLR_PFD6_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_CLR_PFD7_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_CLR_PFD7_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480B_CLR_PFD7_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480B_CLR_PFD7_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480B_CLR_PFD7_DIV1_CLKGATE_SHIFT 31 +/* PFD_480B_TOG Bit Fields */ +#define CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_MASK 0x3Fu +#define CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_SHIFT 0 +#define CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD4_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_TOG_PFD4_STABLE_MASK 0x40u +#define CCM_ANALOG_PFD_480B_TOG_PFD4_STABLE_SHIFT 6 +#define CCM_ANALOG_PFD_480B_TOG_PFD4_DIV1_CLKGATE_MASK 0x80u +#define CCM_ANALOG_PFD_480B_TOG_PFD4_DIV1_CLKGATE_SHIFT 7 +#define CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_MASK 0x3F00u +#define CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_SHIFT 8 +#define CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD5_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_TOG_PFD5_STABLE_MASK 0x4000u +#define CCM_ANALOG_PFD_480B_TOG_PFD5_STABLE_SHIFT 14 +#define CCM_ANALOG_PFD_480B_TOG_PFD5_DIV1_CLKGATE_MASK 0x8000u +#define CCM_ANALOG_PFD_480B_TOG_PFD5_DIV1_CLKGATE_SHIFT 15 +#define CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_MASK 0x3F0000u +#define CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_SHIFT 16 +#define CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD6_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_TOG_PFD6_STABLE_MASK 0x400000u +#define CCM_ANALOG_PFD_480B_TOG_PFD6_STABLE_SHIFT 22 +#define CCM_ANALOG_PFD_480B_TOG_PFD6_DIV1_CLKGATE_MASK 0x800000u +#define CCM_ANALOG_PFD_480B_TOG_PFD6_DIV1_CLKGATE_SHIFT 23 +#define CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_MASK 0x3F000000u +#define CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_SHIFT 24 +#define CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_SHIFT))&CCM_ANALOG_PFD_480B_TOG_PFD7_FRAC_MASK) +#define CCM_ANALOG_PFD_480B_TOG_PFD7_STABLE_MASK 0x40000000u +#define CCM_ANALOG_PFD_480B_TOG_PFD7_STABLE_SHIFT 30 +#define CCM_ANALOG_PFD_480B_TOG_PFD7_DIV1_CLKGATE_MASK 0x80000000u +#define CCM_ANALOG_PFD_480B_TOG_PFD7_DIV1_CLKGATE_SHIFT 31 +/* PLL_ENET Bit Fields */ +#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1u +#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2u +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 +#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4u +#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8u +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10u +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20u +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40u +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80u +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100u +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200u +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400u +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800u +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000u +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000u +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000u +#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 +#define CCM_ANALOG_PLL_ENET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_RSVD1_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 +/* PLL_ENET_SET Bit Fields */ +#define CCM_ANALOG_PLL_ENET_SET_HALF_LF_MASK 0x1u +#define CCM_ANALOG_PLL_ENET_SET_HALF_LF_SHIFT 0 +#define CCM_ANALOG_PLL_ENET_SET_DOUBLE_LF_MASK 0x2u +#define CCM_ANALOG_PLL_ENET_SET_DOUBLE_LF_SHIFT 1 +#define CCM_ANALOG_PLL_ENET_SET_HALF_CP_MASK 0x4u +#define CCM_ANALOG_PLL_ENET_SET_HALF_CP_SHIFT 2 +#define CCM_ANALOG_PLL_ENET_SET_DOUBLE_CP_MASK 0x8u +#define CCM_ANALOG_PLL_ENET_SET_DOUBLE_CP_SHIFT 3 +#define CCM_ANALOG_PLL_ENET_SET_HOLD_RING_OFF_MASK 0x10u +#define CCM_ANALOG_PLL_ENET_SET_HOLD_RING_OFF_SHIFT 4 +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK 0x20u +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT 5 +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_25MHZ_MASK 0x40u +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_25MHZ_SHIFT 6 +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_40MHZ_MASK 0x80u +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_40MHZ_SHIFT 7 +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_50MHZ_MASK 0x100u +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_50MHZ_SHIFT 8 +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_100MHZ_MASK 0x200u +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_100MHZ_SHIFT 9 +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_125MHZ_MASK 0x400u +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_125MHZ_SHIFT 10 +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_250MHZ_MASK 0x800u +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_250MHZ_SHIFT 11 +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_500MHZ_MASK 0x1000u +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_CLK_500MHZ_SHIFT 12 +#define CCM_ANALOG_PLL_ENET_SET_PLL_ENET_OVERRIDE_MASK 0x2000u +#define CCM_ANALOG_PLL_ENET_SET_PLL_ENET_OVERRIDE_SHIFT 13 +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ENET_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_ENET_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_ENET_SET_RSVD1_MASK 0x7FF80000u +#define CCM_ANALOG_PLL_ENET_SET_RSVD1_SHIFT 19 +#define CCM_ANALOG_PLL_ENET_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT 31 +/* PLL_ENET_CLR Bit Fields */ +#define CCM_ANALOG_PLL_ENET_CLR_HALF_LF_MASK 0x1u +#define CCM_ANALOG_PLL_ENET_CLR_HALF_LF_SHIFT 0 +#define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_LF_MASK 0x2u +#define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_LF_SHIFT 1 +#define CCM_ANALOG_PLL_ENET_CLR_HALF_CP_MASK 0x4u +#define CCM_ANALOG_PLL_ENET_CLR_HALF_CP_SHIFT 2 +#define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_CP_MASK 0x8u +#define CCM_ANALOG_PLL_ENET_CLR_DOUBLE_CP_SHIFT 3 +#define CCM_ANALOG_PLL_ENET_CLR_HOLD_RING_OFF_MASK 0x10u +#define CCM_ANALOG_PLL_ENET_CLR_HOLD_RING_OFF_SHIFT 4 +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK 0x20u +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT 5 +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_25MHZ_MASK 0x40u +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_25MHZ_SHIFT 6 +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_40MHZ_MASK 0x80u +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_40MHZ_SHIFT 7 +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_50MHZ_MASK 0x100u +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_50MHZ_SHIFT 8 +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_100MHZ_MASK 0x200u +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_100MHZ_SHIFT 9 +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_125MHZ_MASK 0x400u +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_125MHZ_SHIFT 10 +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_250MHZ_MASK 0x800u +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_250MHZ_SHIFT 11 +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_500MHZ_MASK 0x1000u +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_CLK_500MHZ_SHIFT 12 +#define CCM_ANALOG_PLL_ENET_CLR_PLL_ENET_OVERRIDE_MASK 0x2000u +#define CCM_ANALOG_PLL_ENET_CLR_PLL_ENET_OVERRIDE_SHIFT 13 +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ENET_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_ENET_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_ENET_CLR_RSVD1_MASK 0x7FF80000u +#define CCM_ANALOG_PLL_ENET_CLR_RSVD1_SHIFT 19 +#define CCM_ANALOG_PLL_ENET_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT 31 +/* PLL_ENET_TOG Bit Fields */ +#define CCM_ANALOG_PLL_ENET_TOG_HALF_LF_MASK 0x1u +#define CCM_ANALOG_PLL_ENET_TOG_HALF_LF_SHIFT 0 +#define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_LF_MASK 0x2u +#define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_LF_SHIFT 1 +#define CCM_ANALOG_PLL_ENET_TOG_HALF_CP_MASK 0x4u +#define CCM_ANALOG_PLL_ENET_TOG_HALF_CP_SHIFT 2 +#define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_CP_MASK 0x8u +#define CCM_ANALOG_PLL_ENET_TOG_DOUBLE_CP_SHIFT 3 +#define CCM_ANALOG_PLL_ENET_TOG_HOLD_RING_OFF_MASK 0x10u +#define CCM_ANALOG_PLL_ENET_TOG_HOLD_RING_OFF_SHIFT 4 +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK 0x20u +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT 5 +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_25MHZ_MASK 0x40u +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_25MHZ_SHIFT 6 +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_40MHZ_MASK 0x80u +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_40MHZ_SHIFT 7 +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_50MHZ_MASK 0x100u +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_50MHZ_SHIFT 8 +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_100MHZ_MASK 0x200u +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_100MHZ_SHIFT 9 +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_125MHZ_MASK 0x400u +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_125MHZ_SHIFT 10 +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_250MHZ_MASK 0x800u +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_250MHZ_SHIFT 11 +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_500MHZ_MASK 0x1000u +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_CLK_500MHZ_SHIFT 12 +#define CCM_ANALOG_PLL_ENET_TOG_PLL_ENET_OVERRIDE_MASK 0x2000u +#define CCM_ANALOG_PLL_ENET_TOG_PLL_ENET_OVERRIDE_SHIFT 13 +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_ENET_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_ENET_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_ENET_TOG_RSVD1_MASK 0x7FF80000u +#define CCM_ANALOG_PLL_ENET_TOG_RSVD1_SHIFT 19 +#define CCM_ANALOG_PLL_ENET_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_ENET_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_ENET_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT 31 +/* PLL_AUDIO Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 +/* PLL_AUDIO_SET Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 +/* PLL_AUDIO_CLR Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 +/* PLL_AUDIO_TOG Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 +/* PLL_AUDIO_SS Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK) +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15 +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16 +#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK) +/* PLL_AUDIO_NUM Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK) +/* PLL_AUDIO_DENOM Bit Fields */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK) +/* PLL_VIDEO Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 +/* PLL_VIDEO_SET Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 +/* PLL_VIDEO_CLR Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 +/* PLL_VIDEO_TOG Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7 +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8 +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9 +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10 +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11 +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13 +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17 +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19 +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21 +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22 +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24 +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25 +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 +/* PLL_VIDEO_SS Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK) +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15 +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16 +#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK) +/* PLL_VIDEO_NUM Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK) +/* PLL_VIDEO_DENOM Bit Fields */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30 +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK) +/* CLK_MISC0 Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK) +/* CLK_MISC0_SET Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK) +/* CLK_MISC0_CLR Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK) +/* CLK_MISC0_TOG Bit Fields */ +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0 +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5 +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6 +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7 +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8 +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK) + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x30360000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +#define CCM_ANALOG_BASE_PTR (CCM_ANALOG) +/** Array initializer of CCM_ANALOG peripheral base adresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Accessor_Macros CCM_ANALOG - Register accessor macros + * @{ + */ + + +/* CCM_ANALOG - Register instance definitions */ +/* CCM_ANALOG */ +#define CCM_ANALOG_PLL_ARM CCM_ANALOG_PLL_ARM_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_ARM_SET CCM_ANALOG_PLL_ARM_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_ARM_CLR CCM_ANALOG_PLL_ARM_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_ARM_TOG CCM_ANALOG_PLL_ARM_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_DDR CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_DDR_SET CCM_ANALOG_PLL_DDR_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_DDR_CLR CCM_ANALOG_PLL_DDR_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_DDR_TOG CCM_ANALOG_PLL_DDR_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_DDR_SS CCM_ANALOG_PLL_DDR_SS_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_DDR_NUM CCM_ANALOG_PLL_DDR_NUM_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_DDR_DENOM CCM_ANALOG_PLL_DDR_DENOM_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_480 CCM_ANALOG_PLL_480_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_480_SET CCM_ANALOG_PLL_480_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_480_CLR CCM_ANALOG_PLL_480_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_480_TOG CCM_ANALOG_PLL_480_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480A CCM_ANALOG_PFD_480A_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480A_SET CCM_ANALOG_PFD_480A_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480A_CLR CCM_ANALOG_PFD_480A_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480A_TOG CCM_ANALOG_PFD_480A_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480B CCM_ANALOG_PFD_480B_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480B_SET CCM_ANALOG_PFD_480B_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480B_CLR CCM_ANALOG_PFD_480B_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PFD_480B_TOG CCM_ANALOG_PFD_480B_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_ENET CCM_ANALOG_PLL_ENET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_ENET_SET CCM_ANALOG_PLL_ENET_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_ENET_CLR CCM_ANALOG_PLL_ENET_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_ENET_TOG CCM_ANALOG_PLL_ENET_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_AUDIO CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_AUDIO_SET CCM_ANALOG_PLL_AUDIO_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_AUDIO_CLR CCM_ANALOG_PLL_AUDIO_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_AUDIO_TOG CCM_ANALOG_PLL_AUDIO_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_AUDIO_SS CCM_ANALOG_PLL_AUDIO_SS_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_AUDIO_NUM CCM_ANALOG_PLL_AUDIO_NUM_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_AUDIO_DENOM CCM_ANALOG_PLL_AUDIO_DENOM_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_VIDEO CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_VIDEO_SET CCM_ANALOG_PLL_VIDEO_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_VIDEO_CLR CCM_ANALOG_PLL_VIDEO_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_VIDEO_TOG CCM_ANALOG_PLL_VIDEO_TOG_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_VIDEO_SS CCM_ANALOG_PLL_VIDEO_SS_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_VIDEO_NUM CCM_ANALOG_PLL_VIDEO_NUM_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_PLL_VIDEO_DENOM CCM_ANALOG_PLL_VIDEO_DENOM_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_CLK_MISC0 CCM_ANALOG_CLK_MISC0_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_CLK_MISC0_SET CCM_ANALOG_CLK_MISC0_SET_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_CLK_MISC0_CLR CCM_ANALOG_CLK_MISC0_CLR_REG(CCM_ANALOG_BASE_PTR) +#define CCM_ANALOG_CLK_MISC0_TOG CCM_ANALOG_CLK_MISC0_TOG_REG(CCM_ANALOG_BASE_PTR) + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type, *CSI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- CSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros + * @{ + */ + + +/* CSI - Register accessors */ +#define CSI_CSICR1_REG(base) ((base)->CSICR1) +#define CSI_CSICR2_REG(base) ((base)->CSICR2) +#define CSI_CSICR3_REG(base) ((base)->CSICR3) +#define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) +#define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) +#define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) +#define CSI_CSISR_REG(base) ((base)->CSISR) +#define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) +#define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) +#define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) +#define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) +#define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) +#define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) +#define CSI_CSICR18_REG(base) ((base)->CSICR18) +#define CSI_CSICR19_REG(base) ((base)->CSICR19) + +/*! + * @} + */ /* end of group CSI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/* CSICR1 Bit Fields */ +#define CSI_CSICR1_PIXEL_BIT_MASK 0x1u +#define CSI_CSICR1_PIXEL_BIT_SHIFT 0 +#define CSI_CSICR1_REDGE_MASK 0x2u +#define CSI_CSICR1_REDGE_SHIFT 1 +#define CSI_CSICR1_INV_PCLK_MASK 0x4u +#define CSI_CSICR1_INV_PCLK_SHIFT 2 +#define CSI_CSICR1_INV_DATA_MASK 0x8u +#define CSI_CSICR1_INV_DATA_SHIFT 3 +#define CSI_CSICR1_GCLK_MODE_MASK 0x10u +#define CSI_CSICR1_GCLK_MODE_SHIFT 4 +#define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u +#define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 +#define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u +#define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 +#define CSI_CSICR1_PACK_DIR_MASK 0x80u +#define CSI_CSICR1_PACK_DIR_SHIFT 7 +#define CSI_CSICR1_FCC_MASK 0x100u +#define CSI_CSICR1_FCC_SHIFT 8 +#define CSI_CSICR1_CCIR_EN_MASK 0x400u +#define CSI_CSICR1_CCIR_EN_SHIFT 10 +#define CSI_CSICR1_HSYNC_POL_MASK 0x800u +#define CSI_CSICR1_HSYNC_POL_SHIFT 11 +#define CSI_CSICR1_SOF_INTEN_MASK 0x10000u +#define CSI_CSICR1_SOF_INTEN_SHIFT 16 +#define CSI_CSICR1_SOF_POL_MASK 0x20000u +#define CSI_CSICR1_SOF_POL_SHIFT 17 +#define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u +#define CSI_CSICR1_RXFF_INTEN_SHIFT 18 +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 +#define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u +#define CSI_CSICR1_STATFF_INTEN_SHIFT 21 +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 +#define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u +#define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 +#define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u +#define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 +#define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u +#define CSI_CSICR1_COF_INT_EN_SHIFT 26 +#define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u +#define CSI_CSICR1_VIDEO_MODE_SHIFT 27 +#define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u +#define CSI_CSICR1_PrP_IF_EN_SHIFT 28 +#define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u +#define CSI_CSICR1_EOF_INT_EN_SHIFT 29 +#define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u +#define CSI_CSICR1_EXT_VSYNC_SHIFT 30 +#define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u +#define CSI_CSICR1_SWAP16_EN_SHIFT 31 +/* CSICR2 Bit Fields */ +#define CSI_CSICR2_HSC_MASK 0xFFu +#define CSI_CSICR2_HSC_SHIFT 0 +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_HSC_SHIFT))&CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK 0xFF00u +#define CSI_CSICR2_VSC_SHIFT 8 +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_VSC_SHIFT))&CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK 0x70000u +#define CSI_CSICR2_LVRM_SHIFT 16 +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_LVRM_SHIFT))&CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK 0x180000u +#define CSI_CSICR2_BTS_SHIFT 19 +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_BTS_SHIFT))&CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK 0x800000u +#define CSI_CSICR2_SCE_SHIFT 23 +#define CSI_CSICR2_AFS_MASK 0x3000000u +#define CSI_CSICR2_AFS_SHIFT 24 +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_AFS_SHIFT))&CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK 0x4000000u +#define CSI_CSICR2_DRM_SHIFT 26 +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK 0x30000000u +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT 28 +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK 0xC0000000u +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT 30 +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT))&CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) +/* CSICR3 Bit Fields */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK 0x1u +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT 0 +#define CSI_CSICR3_ECC_INT_EN_MASK 0x2u +#define CSI_CSICR3_ECC_INT_EN_SHIFT 1 +#define CSI_CSICR3_ZERO_PACK_EN_MASK 0x4u +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT 2 +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK 0x8u +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT 3 +#define CSI_CSICR3_RxFF_LEVEL_MASK 0x70u +#define CSI_CSICR3_RxFF_LEVEL_SHIFT 4 +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_RxFF_LEVEL_SHIFT))&CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK 0x80u +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT 7 +#define CSI_CSICR3_STATFF_LEVEL_MASK 0x700u +#define CSI_CSICR3_STATFF_LEVEL_SHIFT 8 +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_STATFF_LEVEL_SHIFT))&CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK 0x800u +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT 11 +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK 0x1000u +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT 12 +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK 0x2000u +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT 13 +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK 0x4000u +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT 14 +#define CSI_CSICR3_FRMCNT_RST_MASK 0x8000u +#define CSI_CSICR3_FRMCNT_RST_SHIFT 15 +#define CSI_CSICR3_FRMCNT_MASK 0xFFFF0000u +#define CSI_CSICR3_FRMCNT_SHIFT 16 +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR3_FRMCNT_SHIFT))&CSI_CSICR3_FRMCNT_MASK) +/* CSISTATFIFO Bit Fields */ +#define CSI_CSISTATFIFO_STAT_MASK 0xFFFFFFFFu +#define CSI_CSISTATFIFO_STAT_SHIFT 0 +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSISTATFIFO_STAT_SHIFT))&CSI_CSISTATFIFO_STAT_MASK) +/* CSIRFIFO Bit Fields */ +#define CSI_CSIRFIFO_IMAGE_MASK 0xFFFFFFFFu +#define CSI_CSIRFIFO_IMAGE_SHIFT 0 +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIRFIFO_IMAGE_SHIFT))&CSI_CSIRFIFO_IMAGE_MASK) +/* CSIRXCNT Bit Fields */ +#define CSI_CSIRXCNT_RXCNT_MASK 0x3FFFFFu +#define CSI_CSIRXCNT_RXCNT_SHIFT 0 +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIRXCNT_RXCNT_SHIFT))&CSI_CSIRXCNT_RXCNT_MASK) +/* CSISR Bit Fields */ +#define CSI_CSISR_DRDY_MASK 0x1u +#define CSI_CSISR_DRDY_SHIFT 0 +#define CSI_CSISR_ECC_INT_MASK 0x2u +#define CSI_CSISR_ECC_INT_SHIFT 1 +#define CSI_CSISR_HRESP_ERR_INT_MASK 0x80u +#define CSI_CSISR_HRESP_ERR_INT_SHIFT 7 +#define CSI_CSISR_COF_INT_MASK 0x2000u +#define CSI_CSISR_COF_INT_SHIFT 13 +#define CSI_CSISR_F1_INT_MASK 0x4000u +#define CSI_CSISR_F1_INT_SHIFT 14 +#define CSI_CSISR_F2_INT_MASK 0x8000u +#define CSI_CSISR_F2_INT_SHIFT 15 +#define CSI_CSISR_SOF_INT_MASK 0x10000u +#define CSI_CSISR_SOF_INT_SHIFT 16 +#define CSI_CSISR_EOF_INT_MASK 0x20000u +#define CSI_CSISR_EOF_INT_SHIFT 17 +#define CSI_CSISR_RxFF_INT_MASK 0x40000u +#define CSI_CSISR_RxFF_INT_SHIFT 18 +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK 0x80000u +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT 19 +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK 0x100000u +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT 20 +#define CSI_CSISR_STATFF_INT_MASK 0x200000u +#define CSI_CSISR_STATFF_INT_SHIFT 21 +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK 0x400000u +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT 22 +#define CSI_CSISR_RF_OR_INT_MASK 0x1000000u +#define CSI_CSISR_RF_OR_INT_SHIFT 24 +#define CSI_CSISR_SF_OR_INT_MASK 0x2000000u +#define CSI_CSISR_SF_OR_INT_SHIFT 25 +#define CSI_CSISR_DMA_FIELD1_DONE_MASK 0x4000000u +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT 26 +#define CSI_CSISR_DMA_FIELD0_DONE_MASK 0x8000000u +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT 27 +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK 0x10000000u +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT 28 +/* CSIDMASA_STATFIFO Bit Fields */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK 0xFFFFFFFCu +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT 2 +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT))&CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +/* CSIDMATS_STATFIFO Bit Fields */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK 0xFFFFFFFFu +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT 0 +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT))&CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) +/* CSIDMASA_FB1 Bit Fields */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK 0xFFFFFFFCu +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT 2 +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT))&CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) +/* CSIDMASA_FB2 Bit Fields */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK 0xFFFFFFFCu +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT 2 +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT))&CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) +/* CSIFBUF_PARA Bit Fields */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK 0xFFFFu +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT 0 +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT))&CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +/* CSIIMAG_PARA Bit Fields */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK 0xFFFFu +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT 0 +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK 0xFFFF0000u +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT 16 +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT))&CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) +/* CSICR18 Bit Fields */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK 0x4u +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT 2 +#define CSI_CSICR18_PARALLEL24_EN_MASK 0x8u +#define CSI_CSICR18_PARALLEL24_EN_SHIFT 3 +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK 0x10u +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT 4 +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK 0x20u +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT 5 +#define CSI_CSICR18_FIELD0_DONE_IE_MASK 0x40u +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT 6 +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK 0x80u +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT 7 +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK 0x100u +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT 8 +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK 0x200u +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT 9 +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK 0x400u +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT 10 +#define CSI_CSICR18_AHB_HPROT_MASK 0xF000u +#define CSI_CSICR18_AHB_HPROT_SHIFT 12 +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_AHB_HPROT_SHIFT))&CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK 0x30000u +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT 16 +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT))&CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK 0xC0000u +#define CSI_CSICR18_MASK_OPTION_SHIFT 18 +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_MASK_OPTION_SHIFT))&CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK 0x100000u +#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT 20 +#define CSI_CSICR18_MIPI_YU_SWAP_MASK 0x200000u +#define CSI_CSICR18_MIPI_YU_SWAP_SHIFT 21 +#define CSI_CSICR18_DATA_FROM_MIPI_MASK 0x400000u +#define CSI_CSICR18_DATA_FROM_MIPI_SHIFT 22 +#define CSI_CSICR18_LINE_STRIDE_EN_MASK 0x1000000u +#define CSI_CSICR18_LINE_STRIDE_EN_SHIFT 24 +#define CSI_CSICR18_MIPI_DATA_FORMAT_MASK 0x7E000000u +#define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT 25 +#define CSI_CSICR18_MIPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT))&CSI_CSICR18_MIPI_DATA_FORMAT_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK 0x80000000u +#define CSI_CSICR18_CSI_ENABLE_SHIFT 31 +/* CSICR19 Bit Fields */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK 0xFFu +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT 0 +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT))&CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI1 base address */ +#define CSI1_BASE (0x30710000u) +/** Peripheral CSI1 base pointer */ +#define CSI1 ((CSI_Type *)CSI1_BASE) +#define CSI1_BASE_PTR (CSI1) +/** Peripheral CSI2 base address */ +#define CSI2_BASE (0x30718000u) +/** Peripheral CSI2 base pointer */ +#define CSI2 ((CSI_Type *)CSI2_BASE) +#define CSI2_BASE_PTR (CSI2) +/** Array initializer of CSI peripheral base adresses */ +#define CSI_BASE_ADDRS { CSI1_BASE, CSI2_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI1, CSI2 } + +/* ---------------------------------------------------------------------------- + -- CSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Accessor_Macros CSI - Register accessor macros + * @{ + */ + + +/* CSI - Register instance definitions */ +/* CSI1 */ +#define CSI1_CSICR1 CSI_CSICR1_REG(CSI1_BASE_PTR) +#define CSI1_CSICR2 CSI_CSICR2_REG(CSI1_BASE_PTR) +#define CSI1_CSICR3 CSI_CSICR3_REG(CSI1_BASE_PTR) +#define CSI1_CSISTATFIFO CSI_CSISTATFIFO_REG(CSI1_BASE_PTR) +#define CSI1_CSIRFIFO CSI_CSIRFIFO_REG(CSI1_BASE_PTR) +#define CSI1_CSIRXCNT CSI_CSIRXCNT_REG(CSI1_BASE_PTR) +#define CSI1_CSISR CSI_CSISR_REG(CSI1_BASE_PTR) +#define CSI1_CSIDMASA_STATFIFO CSI_CSIDMASA_STATFIFO_REG(CSI1_BASE_PTR) +#define CSI1_CSIDMATS_STATFIFO CSI_CSIDMATS_STATFIFO_REG(CSI1_BASE_PTR) +#define CSI1_CSIDMASA_FB1 CSI_CSIDMASA_FB1_REG(CSI1_BASE_PTR) +#define CSI1_CSIDMASA_FB2 CSI_CSIDMASA_FB2_REG(CSI1_BASE_PTR) +#define CSI1_CSIFBUF_PARA CSI_CSIFBUF_PARA_REG(CSI1_BASE_PTR) +#define CSI1_CSIIMAG_PARA CSI_CSIIMAG_PARA_REG(CSI1_BASE_PTR) +#define CSI1_CSICR18 CSI_CSICR18_REG(CSI1_BASE_PTR) +#define CSI1_CSICR19 CSI_CSICR19_REG(CSI1_BASE_PTR) +/* CSI2 */ +#define CSI2_CSICR1 CSI_CSICR1_REG(CSI2_BASE_PTR) +#define CSI2_CSICR2 CSI_CSICR2_REG(CSI2_BASE_PTR) +#define CSI2_CSICR3 CSI_CSICR3_REG(CSI2_BASE_PTR) +#define CSI2_CSISTATFIFO CSI_CSISTATFIFO_REG(CSI2_BASE_PTR) +#define CSI2_CSIRFIFO CSI_CSIRFIFO_REG(CSI2_BASE_PTR) +#define CSI2_CSIRXCNT CSI_CSIRXCNT_REG(CSI2_BASE_PTR) +#define CSI2_CSISR CSI_CSISR_REG(CSI2_BASE_PTR) +#define CSI2_CSIDMASA_STATFIFO CSI_CSIDMASA_STATFIFO_REG(CSI2_BASE_PTR) +#define CSI2_CSIDMATS_STATFIFO CSI_CSIDMATS_STATFIFO_REG(CSI2_BASE_PTR) +#define CSI2_CSIDMASA_FB1 CSI_CSIDMASA_FB1_REG(CSI2_BASE_PTR) +#define CSI2_CSIDMASA_FB2 CSI_CSIDMASA_FB2_REG(CSI2_BASE_PTR) +#define CSI2_CSIFBUF_PARA CSI_CSIFBUF_PARA_REG(CSI2_BASE_PTR) +#define CSI2_CSIIMAG_PARA CSI_CSIIMAG_PARA_REG(CSI2_BASE_PTR) +#define CSI2_CSICR18 CSI_CSICR18_REG(CSI2_BASE_PTR) +#define CSI2_CSICR19 CSI_CSICR19_REG(CSI2_BASE_PTR) + +/*! + * @} + */ /* end of group CSI_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group CSI_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- DDRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer + * @{ + */ + +/** DDRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MSTR; /**< Master Register, offset: 0x0 */ + __IO uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MRCTRL0; /**< Mode Register Read / Write Control Register 0, offset: 0x10 */ + __IO uint32_t MRCTRL1; /**< Mode Register Read / Write Control Register 1, offset: 0x14 */ + __I uint32_t MRSTAT; /**< Mode Register Read / Write Status Register, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */ + __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */ + __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */ + __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */ + uint8_t RESERVED_3[20]; + __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */ + __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */ + uint8_t RESERVED_4[8]; + __IO uint32_t RFSHCTL3; /**< Refresh Control Register 0, offset: 0x60 */ + __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */ + uint8_t RESERVED_5[104]; + __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */ + __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */ + __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */ + __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */ + __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */ + __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */ + uint8_t RESERVED_6[24]; + __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */ + __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */ + __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */ + __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */ + __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */ + __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register5, offset: 0x114 */ + __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */ + __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */ + __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */ + uint8_t RESERVED_7[92]; + __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */ + __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */ + __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */ + __IO uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */ + __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */ + __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */ + __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */ + uint8_t RESERVED_8[4]; + __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */ + __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */ + __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */ + __IO uint32_t DFIUPD3; /**< DFI Update Register 3, offset: 0x1AC */ + __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */ + uint8_t RESERVED_9[76]; + __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */ + __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */ + __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */ + __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */ + __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */ + __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */ + __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */ + uint8_t RESERVED_10[36]; + __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */ + __IO uint32_t ODTMAP; /**< ODT / Rank Map Register, offset: 0x244 */ + uint8_t RESERVED_11[8]; + __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */ + __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */ + uint8_t RESERVED_12[4]; + __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */ + uint8_t RESERVED_13[4]; + __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */ + uint8_t RESERVED_14[4]; + __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */ + uint8_t RESERVED_15[4]; + __IO uint32_t PERFVPR1; /**< Variable Priority Read CAM Register 1, offset: 0x274 */ + __IO uint32_t PERFVPW1; /**< Variable Priority Write CAM Register 1, offset: 0x278 */ + uint8_t RESERVED_16[132]; + __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */ + __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */ + __IO uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */ + __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */ + __IO uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */ + uint8_t RESERVED_17[12]; + __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */ + __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */ +} DDRC_Type, *DDRC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- DDRC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Accessor_Macros DDRC - Register accessor macros + * @{ + */ + + +/* DDRC - Register accessors */ +#define DDRC_MSTR_REG(base) ((base)->MSTR) +#define DDRC_STAT_REG(base) ((base)->STAT) +#define DDRC_MRCTRL0_REG(base) ((base)->MRCTRL0) +#define DDRC_MRCTRL1_REG(base) ((base)->MRCTRL1) +#define DDRC_MRSTAT_REG(base) ((base)->MRSTAT) +#define DDRC_DERATEEN_REG(base) ((base)->DERATEEN) +#define DDRC_DERATEINT_REG(base) ((base)->DERATEINT) +#define DDRC_PWRCTL_REG(base) ((base)->PWRCTL) +#define DDRC_PWRTMG_REG(base) ((base)->PWRTMG) +#define DDRC_HWLPCTL_REG(base) ((base)->HWLPCTL) +#define DDRC_RFSHCTL0_REG(base) ((base)->RFSHCTL0) +#define DDRC_RFSHCTL1_REG(base) ((base)->RFSHCTL1) +#define DDRC_RFSHCTL3_REG(base) ((base)->RFSHCTL3) +#define DDRC_RFSHTMG_REG(base) ((base)->RFSHTMG) +#define DDRC_INIT0_REG(base) ((base)->INIT0) +#define DDRC_INIT1_REG(base) ((base)->INIT1) +#define DDRC_INIT2_REG(base) ((base)->INIT2) +#define DDRC_INIT3_REG(base) ((base)->INIT3) +#define DDRC_INIT4_REG(base) ((base)->INIT4) +#define DDRC_INIT5_REG(base) ((base)->INIT5) +#define DDRC_DRAMTMG0_REG(base) ((base)->DRAMTMG0) +#define DDRC_DRAMTMG1_REG(base) ((base)->DRAMTMG1) +#define DDRC_DRAMTMG2_REG(base) ((base)->DRAMTMG2) +#define DDRC_DRAMTMG3_REG(base) ((base)->DRAMTMG3) +#define DDRC_DRAMTMG4_REG(base) ((base)->DRAMTMG4) +#define DDRC_DRAMTMG5_REG(base) ((base)->DRAMTMG5) +#define DDRC_DRAMTMG6_REG(base) ((base)->DRAMTMG6) +#define DDRC_DRAMTMG7_REG(base) ((base)->DRAMTMG7) +#define DDRC_DRAMTMG8_REG(base) ((base)->DRAMTMG8) +#define DDRC_ZQCTL0_REG(base) ((base)->ZQCTL0) +#define DDRC_ZQCTL1_REG(base) ((base)->ZQCTL1) +#define DDRC_ZQCTL2_REG(base) ((base)->ZQCTL2) +#define DDRC_ZQSTAT_REG(base) ((base)->ZQSTAT) +#define DDRC_DFITMG0_REG(base) ((base)->DFITMG0) +#define DDRC_DFITMG1_REG(base) ((base)->DFITMG1) +#define DDRC_DFILPCFG0_REG(base) ((base)->DFILPCFG0) +#define DDRC_DFIUPD0_REG(base) ((base)->DFIUPD0) +#define DDRC_DFIUPD1_REG(base) ((base)->DFIUPD1) +#define DDRC_DFIUPD2_REG(base) ((base)->DFIUPD2) +#define DDRC_DFIUPD3_REG(base) ((base)->DFIUPD3) +#define DDRC_DFIMISC_REG(base) ((base)->DFIMISC) +#define DDRC_ADDRMAP0_REG(base) ((base)->ADDRMAP0) +#define DDRC_ADDRMAP1_REG(base) ((base)->ADDRMAP1) +#define DDRC_ADDRMAP2_REG(base) ((base)->ADDRMAP2) +#define DDRC_ADDRMAP3_REG(base) ((base)->ADDRMAP3) +#define DDRC_ADDRMAP4_REG(base) ((base)->ADDRMAP4) +#define DDRC_ADDRMAP5_REG(base) ((base)->ADDRMAP5) +#define DDRC_ADDRMAP6_REG(base) ((base)->ADDRMAP6) +#define DDRC_ODTCFG_REG(base) ((base)->ODTCFG) +#define DDRC_ODTMAP_REG(base) ((base)->ODTMAP) +#define DDRC_SCHED_REG(base) ((base)->SCHED) +#define DDRC_SCHED1_REG(base) ((base)->SCHED1) +#define DDRC_PERFHPR1_REG(base) ((base)->PERFHPR1) +#define DDRC_PERFLPR1_REG(base) ((base)->PERFLPR1) +#define DDRC_PERFWR1_REG(base) ((base)->PERFWR1) +#define DDRC_PERFVPR1_REG(base) ((base)->PERFVPR1) +#define DDRC_PERFVPW1_REG(base) ((base)->PERFVPW1) +#define DDRC_DBG0_REG(base) ((base)->DBG0) +#define DDRC_DBG1_REG(base) ((base)->DBG1) +#define DDRC_DBGCAM_REG(base) ((base)->DBGCAM) +#define DDRC_DBGCMD_REG(base) ((base)->DBGCMD) +#define DDRC_DBGSTAT_REG(base) ((base)->DBGSTAT) +#define DDRC_SWCTL_REG(base) ((base)->SWCTL) +#define DDRC_SWSTAT_REG(base) ((base)->SWSTAT) + +/*! + * @} + */ /* end of group DDRC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DDRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Masks DDRC Register Masks + * @{ + */ + +/* MSTR Bit Fields */ +#define DDRC_MSTR_DDR3_MASK 0x1u +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_LPDDR2_MASK 0x4u +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR3_MASK 0x8u +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_BURST_MODE_MASK 0x100u +#define DDRC_MSTR_BURST_MODE_SHIFT 8 +#define DDRC_MSTR_BURSTCHOP_MASK 0x200u +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x3000u +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MSTR_DATA_BUS_WIDTH_SHIFT))&DDRC_MSTR_DATA_BUS_WIDTH_MASK) +#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x8000u +#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 +#define DDRC_MSTR_BURST_RDWR_MASK 0xF0000u +#define DDRC_MSTR_BURST_RDWR_SHIFT 16 +#define DDRC_MSTR_BURST_RDWR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MSTR_BURST_RDWR_SHIFT))&DDRC_MSTR_BURST_RDWR_MASK) +#define DDRC_MSTR_ACTIVE_RANKS_MASK 0xF000000u +#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 +#define DDRC_MSTR_ACTIVE_RANKS(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MSTR_ACTIVE_RANKS_SHIFT))&DDRC_MSTR_ACTIVE_RANKS_MASK) +/* STAT Bit Fields */ +#define DDRC_STAT_OPERATING_MODE_MASK 0x7u +#define DDRC_STAT_OPERATING_MODE_SHIFT 0 +#define DDRC_STAT_OPERATING_MODE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_STAT_OPERATING_MODE_SHIFT))&DDRC_STAT_OPERATING_MODE_MASK) +#define DDRC_STAT_SELFREF_TYPE_MASK 0x30u +#define DDRC_STAT_SELFREF_TYPE_SHIFT 4 +#define DDRC_STAT_SELFREF_TYPE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_STAT_SELFREF_TYPE_SHIFT))&DDRC_STAT_SELFREF_TYPE_MASK) +/* MRCTRL0 Bit Fields */ +#define DDRC_MRCTRL0_MR_TYPE_MASK 0x1u +#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 +#define DDRC_MRCTRL0_MR_RANK_MASK 0xF0u +#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRC_MRCTRL0_MR_RANK(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MRCTRL0_MR_RANK_SHIFT))&DDRC_MRCTRL0_MR_RANK_MASK) +#define DDRC_MRCTRL0_MR_ADDR_MASK 0xF000u +#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRC_MRCTRL0_MR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MRCTRL0_MR_ADDR_SHIFT))&DDRC_MRCTRL0_MR_ADDR_MASK) +#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000u +#define DDRC_MRCTRL0_MR_WR_SHIFT 31 +/* MRCTRL1 Bit Fields */ +#define DDRC_MRCTRL1_MR_DATA_MASK 0x3FFFFu +#define DDRC_MRCTRL1_MR_DATA_SHIFT 0 +#define DDRC_MRCTRL1_MR_DATA(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MRCTRL1_MR_DATA_SHIFT))&DDRC_MRCTRL1_MR_DATA_MASK) +/* MRSTAT Bit Fields */ +#define DDRC_MRSTAT_MR_WR_BUSY_MASK 0x1u +#define DDRC_MRSTAT_MR_WR_BUSY_SHIFT 0 +/* DERATEEN Bit Fields */ +#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x1u +#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 +#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x2u +#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +/* DERATEINT Bit Fields */ +#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFu +#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 +#define DDRC_DERATEINT_MR4_READ_INTERVAL(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT))&DDRC_DERATEINT_MR4_READ_INTERVAL_MASK) +/* PWRCTL Bit Fields */ +#define DDRC_PWRCTL_SELFREF_EN_MASK 0x1u +#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 +#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x2u +#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x4u +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x8u +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 +#define DDRC_PWRCTL_SELFREF_SW_MASK 0x20u +#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 +/* PWRTMG Bit Fields */ +#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x1Fu +#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 +#define DDRC_PWRTMG_POWERDOWN_TO_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT))&DDRC_PWRTMG_POWERDOWN_TO_X32_MASK) +#define DDRC_PWRTMG_T_DPD_X4096_MASK 0xFF00u +#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 +#define DDRC_PWRTMG_T_DPD_X4096(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PWRTMG_T_DPD_X4096_SHIFT))&DDRC_PWRTMG_T_DPD_X4096_MASK) +#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0xFF0000u +#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 +#define DDRC_PWRTMG_SELFREF_TO_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PWRTMG_SELFREF_TO_X32_SHIFT))&DDRC_PWRTMG_SELFREF_TO_X32_MASK) +/* HWLPCTL Bit Fields */ +#define DDRC_HWLPCTL_HW_LP_EN_MASK 0x1u +#define DDRC_HWLPCTL_HW_LP_EN_SHIFT 0 +#define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK 0x2u +#define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT 1 +#define DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK 0xFFF0000u +#define DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT 16 +#define DDRC_HWLPCTL_HW_LP_IDLE_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT))&DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK) +/* RFSHCTL0 Bit Fields */ +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x4u +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 +#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x1F0u +#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 +#define DDRC_RFSHCTL0_REFRESH_BURST(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL0_REFRESH_BURST_SHIFT))&DDRC_RFSHCTL0_REFRESH_BURST_MASK) +#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x1F000u +#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 +#define DDRC_RFSHCTL0_REFRESH_TO_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT))&DDRC_RFSHCTL0_REFRESH_TO_X32_MASK) +#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0xF00000u +#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 +#define DDRC_RFSHCTL0_REFRESH_MARGIN(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT))&DDRC_RFSHCTL0_REFRESH_MARGIN_MASK) +/* RFSHCTL1 Bit Fields */ +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0xFFFu +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT))&DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK) +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0xFFF0000u +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT))&DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK) +/* RFSHCTL3 Bit Fields */ +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x1u +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x2u +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 +/* RFSHTMG Bit Fields */ +#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x3FFu +#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 +#define DDRC_RFSHTMG_T_RFC_MIN(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHTMG_T_RFC_MIN_SHIFT))&DDRC_RFSHTMG_T_RFC_MIN_MASK) +#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0xFFF0000u +#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 +#define DDRC_RFSHTMG_T_RFC_NOM_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT))&DDRC_RFSHTMG_T_RFC_NOM_X32_MASK) +/* INIT0 Bit Fields */ +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x3FFu +#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 +#define DDRC_INIT0_PRE_CKE_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT0_PRE_CKE_X1024_SHIFT))&DDRC_INIT0_PRE_CKE_X1024_MASK) +#define DDRC_INIT0_POST_CKE_X1024_MASK 0x3FF0000u +#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 +#define DDRC_INIT0_POST_CKE_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT0_POST_CKE_X1024_SHIFT))&DDRC_INIT0_POST_CKE_X1024_MASK) +#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000u +#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 +#define DDRC_INIT0_SKIP_DRAM_INIT(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT0_SKIP_DRAM_INIT_SHIFT))&DDRC_INIT0_SKIP_DRAM_INIT_MASK) +/* INIT1 Bit Fields */ +#define DDRC_INIT1_PRE_OCD_X32_MASK 0xFu +#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 +#define DDRC_INIT1_PRE_OCD_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT1_PRE_OCD_X32_SHIFT))&DDRC_INIT1_PRE_OCD_X32_MASK) +#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x7F00u +#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 +#define DDRC_INIT1_FINAL_WAIT_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT1_FINAL_WAIT_X32_SHIFT))&DDRC_INIT1_FINAL_WAIT_X32_MASK) +#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0xFF0000u +#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 +#define DDRC_INIT1_DRAM_RSTN_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT1_DRAM_RSTN_X1024_SHIFT))&DDRC_INIT1_DRAM_RSTN_X1024_MASK) +/* INIT2 Bit Fields */ +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0xFu +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT))&DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK) +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0xFF00u +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT))&DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK) +/* INIT3 Bit Fields */ +#define DDRC_INIT3_EMR_MASK 0xFFFFu +#define DDRC_INIT3_EMR_SHIFT 0 +#define DDRC_INIT3_EMR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT3_EMR_SHIFT))&DDRC_INIT3_EMR_MASK) +#define DDRC_INIT3_MR_MASK 0xFFFF0000u +#define DDRC_INIT3_MR_SHIFT 16 +#define DDRC_INIT3_MR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT3_MR_SHIFT))&DDRC_INIT3_MR_MASK) +/* INIT4 Bit Fields */ +#define DDRC_INIT4_EMR3_MASK 0xFFFFu +#define DDRC_INIT4_EMR3_SHIFT 0 +#define DDRC_INIT4_EMR3(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT4_EMR3_SHIFT))&DDRC_INIT4_EMR3_MASK) +#define DDRC_INIT4_EMR2_MASK 0xFFFF0000u +#define DDRC_INIT4_EMR2_SHIFT 16 +#define DDRC_INIT4_EMR2(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT4_EMR2_SHIFT))&DDRC_INIT4_EMR2_MASK) +/* INIT5 Bit Fields */ +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x3FFu +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT))&DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK) +#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0xFF0000u +#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 +#define DDRC_INIT5_DEV_ZQINIT_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_INIT5_DEV_ZQINIT_X32_SHIFT))&DDRC_INIT5_DEV_ZQINIT_X32_MASK) +/* DRAMTMG0 Bit Fields */ +#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x3Fu +#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 +#define DDRC_DRAMTMG0_T_RAS_MIN(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_T_RAS_MIN_SHIFT))&DDRC_DRAMTMG0_T_RAS_MIN_MASK) +#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x7F00u +#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 +#define DDRC_DRAMTMG0_T_RAS_MAX(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_T_RAS_MAX_SHIFT))&DDRC_DRAMTMG0_T_RAS_MAX_MASK) +#define DDRC_DRAMTMG0_T_FAW_MASK 0x3F0000u +#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 +#define DDRC_DRAMTMG0_T_FAW(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_T_FAW_SHIFT))&DDRC_DRAMTMG0_T_FAW_MASK) +#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000u +#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 +#define DDRC_DRAMTMG0_WR2PRE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG0_WR2PRE_SHIFT))&DDRC_DRAMTMG0_WR2PRE_MASK) +/* DRAMTMG1 Bit Fields */ +#define DDRC_DRAMTMG1_T_RC_MASK 0x7Fu +#define DDRC_DRAMTMG1_T_RC_SHIFT 0 +#define DDRC_DRAMTMG1_T_RC(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG1_T_RC_SHIFT))&DDRC_DRAMTMG1_T_RC_MASK) +#define DDRC_DRAMTMG1_RD2PRE_MASK 0x1F00u +#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 +#define DDRC_DRAMTMG1_RD2PRE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG1_RD2PRE_SHIFT))&DDRC_DRAMTMG1_RD2PRE_MASK) +#define DDRC_DRAMTMG1_T_XP_MASK 0x1F0000u +#define DDRC_DRAMTMG1_T_XP_SHIFT 16 +#define DDRC_DRAMTMG1_T_XP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG1_T_XP_SHIFT))&DDRC_DRAMTMG1_T_XP_MASK) +/* DRAMTMG2 Bit Fields */ +#define DDRC_DRAMTMG2_WR2RD_MASK 0x3Fu +#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 +#define DDRC_DRAMTMG2_WR2RD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_WR2RD_SHIFT))&DDRC_DRAMTMG2_WR2RD_MASK) +#define DDRC_DRAMTMG2_RD2WR_MASK 0x1F00u +#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 +#define DDRC_DRAMTMG2_RD2WR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_RD2WR_SHIFT))&DDRC_DRAMTMG2_RD2WR_MASK) +#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x3F0000u +#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 +#define DDRC_DRAMTMG2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_READ_LATENCY_SHIFT))&DDRC_DRAMTMG2_READ_LATENCY_MASK) +#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000u +#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 +#define DDRC_DRAMTMG2_WRITE_LATENCY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT))&DDRC_DRAMTMG2_WRITE_LATENCY_MASK) +/* DRAMTMG3 Bit Fields */ +#define DDRC_DRAMTMG3_T_MOD_MASK 0x3FFu +#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 +#define DDRC_DRAMTMG3_T_MOD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG3_T_MOD_SHIFT))&DDRC_DRAMTMG3_T_MOD_MASK) +#define DDRC_DRAMTMG3_T_MRD_MASK 0x3F000u +#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 +#define DDRC_DRAMTMG3_T_MRD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG3_T_MRD_SHIFT))&DDRC_DRAMTMG3_T_MRD_MASK) +#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000u +#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 +#define DDRC_DRAMTMG3_T_MRW(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG3_T_MRW_SHIFT))&DDRC_DRAMTMG3_T_MRW_MASK) +/* DRAMTMG4 Bit Fields */ +#define DDRC_DRAMTMG4_T_RP_MASK 0x1Fu +#define DDRC_DRAMTMG4_T_RP_SHIFT 0 +#define DDRC_DRAMTMG4_T_RP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_RP_SHIFT))&DDRC_DRAMTMG4_T_RP_MASK) +#define DDRC_DRAMTMG4_T_RRD_MASK 0xF00u +#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 +#define DDRC_DRAMTMG4_T_RRD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_RRD_SHIFT))&DDRC_DRAMTMG4_T_RRD_MASK) +#define DDRC_DRAMTMG4_T_CCD_MASK 0x70000u +#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 +#define DDRC_DRAMTMG4_T_CCD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_CCD_SHIFT))&DDRC_DRAMTMG4_T_CCD_MASK) +#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000u +#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 +#define DDRC_DRAMTMG4_T_RCD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG4_T_RCD_SHIFT))&DDRC_DRAMTMG4_T_RCD_MASK) +/* DRAMTMG5 Bit Fields */ +#define DDRC_DRAMTMG5_T_CKE_MASK 0x1Fu +#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 +#define DDRC_DRAMTMG5_T_CKE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKE_SHIFT))&DDRC_DRAMTMG5_T_CKE_MASK) +#define DDRC_DRAMTMG5_T_CKESR_MASK 0x3F00u +#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 +#define DDRC_DRAMTMG5_T_CKESR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKESR_SHIFT))&DDRC_DRAMTMG5_T_CKESR_MASK) +#define DDRC_DRAMTMG5_T_CKSRE_MASK 0xF0000u +#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 +#define DDRC_DRAMTMG5_T_CKSRE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKSRE_SHIFT))&DDRC_DRAMTMG5_T_CKSRE_MASK) +#define DDRC_DRAMTMG5_T_CKSRX_MASK 0xF000000u +#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 +#define DDRC_DRAMTMG5_T_CKSRX(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG5_T_CKSRX_SHIFT))&DDRC_DRAMTMG5_T_CKSRX_MASK) +/* DRAMTMG6 Bit Fields */ +#define DDRC_DRAMTMG6_T_CKCSX_MASK 0xFu +#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 +#define DDRC_DRAMTMG6_T_CKCSX(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG6_T_CKCSX_SHIFT))&DDRC_DRAMTMG6_T_CKCSX_MASK) +#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0xF0000u +#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 +#define DDRC_DRAMTMG6_T_CKDPDX(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG6_T_CKDPDX_SHIFT))&DDRC_DRAMTMG6_T_CKDPDX_MASK) +#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0xF000000u +#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 +#define DDRC_DRAMTMG6_T_CKDPDE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG6_T_CKDPDE_SHIFT))&DDRC_DRAMTMG6_T_CKDPDE_MASK) +/* DRAMTMG7 Bit Fields */ +#define DDRC_DRAMTMG7_T_CKPDX_MASK 0xFu +#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 +#define DDRC_DRAMTMG7_T_CKPDX(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG7_T_CKPDX_SHIFT))&DDRC_DRAMTMG7_T_CKPDX_MASK) +#define DDRC_DRAMTMG7_T_CKPDE_MASK 0xF00u +#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 +#define DDRC_DRAMTMG7_T_CKPDE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG7_T_CKPDE_SHIFT))&DDRC_DRAMTMG7_T_CKPDE_MASK) +/* DRAMTMG8 Bit Fields */ +#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x7Fu +#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 +#define DDRC_DRAMTMG8_T_XS_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG8_T_XS_X32_SHIFT))&DDRC_DRAMTMG8_T_XS_X32_MASK) +#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x7F00u +#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 +#define DDRC_DRAMTMG8_T_XS_DLL_X32(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT))&DDRC_DRAMTMG8_T_XS_DLL_X32_MASK) +/* ZQCTL0 Bit Fields */ +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x3FFu +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT))&DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK) +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x3FF0000u +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT))&DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK) +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000u +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000u +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000u +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 +/* ZQCTL1 Bit Fields */ +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0xFFFFFu +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT))&DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK) +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000u +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT))&DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK) +/* ZQCTL2 Bit Fields */ +#define DDRC_ZQCTL2_ZQ_RESET_MASK 0x1u +#define DDRC_ZQCTL2_ZQ_RESET_SHIFT 0 +/* ZQSTAT Bit Fields */ +#define DDRC_ZQSTAT_ZQ_RESET_BUSY_MASK 0x1u +#define DDRC_ZQSTAT_ZQ_RESET_BUSY_SHIFT 0 +/* DFITMG0 Bit Fields */ +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x3Fu +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT))&DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK) +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x3F00u +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT))&DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK) +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x8000u +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x3F0000u +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT))&DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK) +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x800000u +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000u +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT))&DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK) +/* DFITMG1 Bit Fields */ +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0xFu +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT))&DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK) +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0xF00u +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT))&DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK) +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x1F0000u +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT))&DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK) +/* DFILPCFG0 Bit Fields */ +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x1u +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0xF0u +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT))&DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK) +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x100u +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0xF000u +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT))&DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK) +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x10000u +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0xF00000u +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT))&DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK) +#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0xF000000u +#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 +#define DDRC_DFILPCFG0_DFI_TLP_RESP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT))&DDRC_DFILPCFG0_DFI_TLP_RESP_MASK) +/* DFIUPD0 Bit Fields */ +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x3FFu +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT))&DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK) +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x3FF0000u +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT))&DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK) +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000u +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000u +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31 +/* DFIUPD1 Bit Fields */ +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0xFFu +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT))&DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK) +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0xFF0000u +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT))&DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK) +/* DFIUPD2 Bit Fields */ +#define DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_MASK 0xFFFu +#define DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT 0 +#define DDRC_DFIUPD2_DFI_PHYUPD_TYPE0(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT))&DDRC_DFIUPD2_DFI_PHYUPD_TYPE0_MASK) +#define DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_MASK 0xFFF0000u +#define DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT 16 +#define DDRC_DFIUPD2_DFI_PHYUPD_TYPE1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT))&DDRC_DFIUPD2_DFI_PHYUPD_TYPE1_MASK) +#define DDRC_DFIUPD2_DFI_PHYUPD_EN_MASK 0x80000000u +#define DDRC_DFIUPD2_DFI_PHYUPD_EN_SHIFT 31 +/* DFIUPD3 Bit Fields */ +#define DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_MASK 0xFFFu +#define DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT 0 +#define DDRC_DFIUPD3_DFI_PHYUPD_TYPE2(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT))&DDRC_DFIUPD3_DFI_PHYUPD_TYPE2_MASK) +#define DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_MASK 0xFFF0000u +#define DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT 16 +#define DDRC_DFIUPD3_DFI_PHYUPD_TYPE3(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT))&DDRC_DFIUPD3_DFI_PHYUPD_TYPE3_MASK) +/* DFIMISC Bit Fields */ +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x1u +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 +/* ADDRMAP0 Bit Fields */ +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x1Fu +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT))&DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK) +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_MASK 0x1F00u +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_SHIFT 8 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_SHIFT))&DDRC_ADDRMAP0_ADDRMAP_CS_BIT1_MASK) +/* ADDRMAP1 Bit Fields */ +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x1Fu +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT))&DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK) +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x1F00u +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT))&DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK) +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x1F0000u +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT))&DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK) +/* ADDRMAP2 Bit Fields */ +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0xFu +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK) +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0xF00u +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK) +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0xF0000u +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK) +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0xF000000u +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT))&DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK) +/* ADDRMAP3 Bit Fields */ +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0xFu +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK) +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0xF00u +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK) +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0xF0000u +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK) +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0xF000000u +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT))&DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK) +/* ADDRMAP4 Bit Fields */ +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0xFu +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT))&DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK) +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0xF00u +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT))&DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK) +/* ADDRMAP5 Bit Fields */ +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0xFu +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK) +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0xF00u +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK) +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0xF0000u +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK) +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0xF000000u +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT))&DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK) +/* ADDRMAP6 Bit Fields */ +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0xFu +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK) +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0xF00u +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK) +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0xF0000u +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK) +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0xF000000u +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT))&DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK) +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000u +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 +/* ODTCFG Bit Fields */ +#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x7Cu +#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 +#define DDRC_ODTCFG_RD_ODT_DELAY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_RD_ODT_DELAY_SHIFT))&DDRC_ODTCFG_RD_ODT_DELAY_MASK) +#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0xF00u +#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 +#define DDRC_ODTCFG_RD_ODT_HOLD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_RD_ODT_HOLD_SHIFT))&DDRC_ODTCFG_RD_ODT_HOLD_MASK) +#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x1F0000u +#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 +#define DDRC_ODTCFG_WR_ODT_DELAY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_WR_ODT_DELAY_SHIFT))&DDRC_ODTCFG_WR_ODT_DELAY_MASK) +#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0xF000000u +#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 +#define DDRC_ODTCFG_WR_ODT_HOLD(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTCFG_WR_ODT_HOLD_SHIFT))&DDRC_ODTCFG_WR_ODT_HOLD_MASK) +/* ODTMAP Bit Fields */ +#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0xFu +#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 +#define DDRC_ODTMAP_RANK0_WR_ODT(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK0_WR_ODT_SHIFT))&DDRC_ODTMAP_RANK0_WR_ODT_MASK) +#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0xF0u +#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 +#define DDRC_ODTMAP_RANK0_RD_ODT(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK0_RD_ODT_SHIFT))&DDRC_ODTMAP_RANK0_RD_ODT_MASK) +#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0xF00u +#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 +#define DDRC_ODTMAP_RANK1_WR_ODT(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK1_WR_ODT_SHIFT))&DDRC_ODTMAP_RANK1_WR_ODT_MASK) +#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0xF000u +#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 +#define DDRC_ODTMAP_RANK1_RD_ODT(x) (((uint32_t)(((uint32_t)(x))<<DDRC_ODTMAP_RANK1_RD_ODT_SHIFT))&DDRC_ODTMAP_RANK1_RD_ODT_MASK) +/* SCHED Bit Fields */ +#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x1u +#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 +#define DDRC_SCHED_PREFER_WRITE_MASK 0x2u +#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 +#define DDRC_SCHED_PAGECLOSE_MASK 0x4u +#define DDRC_SCHED_PAGECLOSE_SHIFT 2 +#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x3F00u +#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 +#define DDRC_SCHED_LPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x))<<DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT))&DDRC_SCHED_LPR_NUM_ENTRIES_MASK) +#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000u +#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 +#define DDRC_SCHED_RDWR_IDLE_GAP(x) (((uint32_t)(((uint32_t)(x))<<DDRC_SCHED_RDWR_IDLE_GAP_SHIFT))&DDRC_SCHED_RDWR_IDLE_GAP_MASK) +/* SCHED1 Bit Fields */ +#define DDRC_SCHED1_PAGECLOSE_TIMER_MASK 0xFFu +#define DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT 0 +#define DDRC_SCHED1_PAGECLOSE_TIMER(x) (((uint32_t)(((uint32_t)(x))<<DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT))&DDRC_SCHED1_PAGECLOSE_TIMER_MASK) +/* PERFHPR1 Bit Fields */ +#define DDRC_PERFHPR1_HPR_MAX_STARVE_MASK 0xFFFFu +#define DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFHPR1_HPR_MAX_STARVE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT))&DDRC_PERFHPR1_HPR_MAX_STARVE_MASK) +#define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK 0xFF000000u +#define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT))&DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK) +/* PERFLPR1 Bit Fields */ +#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0xFFFFu +#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFLPR1_LPR_MAX_STARVE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT))&DDRC_PERFLPR1_LPR_MAX_STARVE_MASK) +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000u +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT))&DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK) +/* PERFWR1 Bit Fields */ +#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0xFFFFu +#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 +#define DDRC_PERFWR1_W_MAX_STARVE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFWR1_W_MAX_STARVE_SHIFT))&DDRC_PERFWR1_W_MAX_STARVE_MASK) +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000u +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT))&DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK) +/* PERFVPR1 Bit Fields */ +#define DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_MASK 0x7FFu +#define DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT 0 +#define DDRC_PERFVPR1_VPR_TIMEOUT_RANGE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT))&DDRC_PERFVPR1_VPR_TIMEOUT_RANGE_MASK) +/* PERFVPW1 Bit Fields */ +#define DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_MASK 0x7FFu +#define DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT 0 +#define DDRC_PERFVPW1_VPW_TIMEOUT_RANGE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT))&DDRC_PERFVPW1_VPW_TIMEOUT_RANGE_MASK) +/* DBG0 Bit Fields */ +#define DDRC_DBG0_DIS_WC_MASK 0x1u +#define DDRC_DBG0_DIS_WC_SHIFT 0 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x10u +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 +/* DBG1 Bit Fields */ +#define DDRC_DBG1_DIS_DQ_MASK 0x1u +#define DDRC_DBG1_DIS_DQ_SHIFT 0 +#define DDRC_DBG1_DIS_HIF_MASK 0x2u +#define DDRC_DBG1_DIS_HIF_SHIFT 1 +/* DBGCAM Bit Fields */ +#define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK 0x7Fu +#define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT 0 +#define DDRC_DBGCAM_DBG_HPR_Q_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT))&DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK) +#define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK 0x7F00u +#define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT 8 +#define DDRC_DBGCAM_DBG_LPR_Q_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT))&DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK) +#define DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK 0x7F0000u +#define DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT 16 +#define DDRC_DBGCAM_DBG_W_Q_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT))&DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK) +#define DDRC_DBGCAM_DBG_STALL_MASK 0x1000000u +#define DDRC_DBGCAM_DBG_STALL_SHIFT 24 +#define DDRC_DBGCAM_DBG_RD_Q_EMPTY_MASK 0x2000000u +#define DDRC_DBGCAM_DBG_RD_Q_EMPTY_SHIFT 25 +#define DDRC_DBGCAM_DBG_WR_Q_EMPTY_MASK 0x4000000u +#define DDRC_DBGCAM_DBG_WR_Q_EMPTY_SHIFT 26 +#define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK 0x10000000u +#define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT 28 +#define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK 0x20000000u +#define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT 29 +#define DDRC_DBGCAM_DBG_STALL_WR_MASK 0x40000000u +#define DDRC_DBGCAM_DBG_STALL_WR_SHIFT 30 +#define DDRC_DBGCAM_DBG_STALL_RD_MASK 0x80000000u +#define DDRC_DBGCAM_DBG_STALL_RD_SHIFT 31 +/* DBGCMD Bit Fields */ +#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x1u +#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 +#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x2u +#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x10u +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 +#define DDRC_DBGCMD_CTRLUPD_MASK 0x20u +#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 +/* DBGSTAT Bit Fields */ +#define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_MASK 0x1u +#define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT 0 +#define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_MASK 0x2u +#define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT 1 +#define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK 0x10u +#define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT 4 +#define DDRC_DBGSTAT_CTRLUPD_BUSY_MASK 0x20u +#define DDRC_DBGSTAT_CTRLUPD_BUSY_SHIFT 5 +/* SWCTL Bit Fields */ +#define DDRC_SWCTL_SW_DONE_MASK 0x1u +#define DDRC_SWCTL_SW_DONE_SHIFT 0 +/* SWSTAT Bit Fields */ +#define DDRC_SWSTAT_SW_DONE_ACK_MASK 0x1u +#define DDRC_SWSTAT_SW_DONE_ACK_SHIFT 0 + +/*! + * @} + */ /* end of group DDRC_Register_Masks */ + + +/* DDRC - Peripheral instance base addresses */ +/** Peripheral DDRC base address */ +#define DDRC_BASE (0x307A0000u) +/** Peripheral DDRC base pointer */ +#define DDRC ((DDRC_Type *)DDRC_BASE) +#define DDRC_BASE_PTR (DDRC) +/** Array initializer of DDRC peripheral base adresses */ +#define DDRC_BASE_ADDRS { DDRC_BASE } +/** Array initializer of DDRC peripheral base pointers */ +#define DDRC_BASE_PTRS { DDRC } + +/* ---------------------------------------------------------------------------- + -- DDRC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Accessor_Macros DDRC - Register accessor macros + * @{ + */ + + +/* DDRC - Register instance definitions */ +/* DDRC */ +#define DDRC_MSTR DDRC_MSTR_REG(DDRC_BASE_PTR) +#define DDRC_STAT DDRC_STAT_REG(DDRC_BASE_PTR) +#define DDRC_MRCTRL0 DDRC_MRCTRL0_REG(DDRC_BASE_PTR) +#define DDRC_MRCTRL1 DDRC_MRCTRL1_REG(DDRC_BASE_PTR) +#define DDRC_MRSTAT DDRC_MRSTAT_REG(DDRC_BASE_PTR) +#define DDRC_DERATEEN DDRC_DERATEEN_REG(DDRC_BASE_PTR) +#define DDRC_DERATEINT DDRC_DERATEINT_REG(DDRC_BASE_PTR) +#define DDRC_PWRCTL DDRC_PWRCTL_REG(DDRC_BASE_PTR) +#define DDRC_PWRTMG DDRC_PWRTMG_REG(DDRC_BASE_PTR) +#define DDRC_HWLPCTL DDRC_HWLPCTL_REG(DDRC_BASE_PTR) +#define DDRC_RFSHCTL0 DDRC_RFSHCTL0_REG(DDRC_BASE_PTR) +#define DDRC_RFSHCTL1 DDRC_RFSHCTL1_REG(DDRC_BASE_PTR) +#define DDRC_RFSHCTL3 DDRC_RFSHCTL3_REG(DDRC_BASE_PTR) +#define DDRC_RFSHTMG DDRC_RFSHTMG_REG(DDRC_BASE_PTR) +#define DDRC_INIT0 DDRC_INIT0_REG(DDRC_BASE_PTR) +#define DDRC_INIT1 DDRC_INIT1_REG(DDRC_BASE_PTR) +#define DDRC_INIT2 DDRC_INIT2_REG(DDRC_BASE_PTR) +#define DDRC_INIT3 DDRC_INIT3_REG(DDRC_BASE_PTR) +#define DDRC_INIT4 DDRC_INIT4_REG(DDRC_BASE_PTR) +#define DDRC_INIT5 DDRC_INIT5_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG0 DDRC_DRAMTMG0_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG1 DDRC_DRAMTMG1_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG2 DDRC_DRAMTMG2_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG3 DDRC_DRAMTMG3_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG4 DDRC_DRAMTMG4_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG5 DDRC_DRAMTMG5_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG6 DDRC_DRAMTMG6_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG7 DDRC_DRAMTMG7_REG(DDRC_BASE_PTR) +#define DDRC_DRAMTMG8 DDRC_DRAMTMG8_REG(DDRC_BASE_PTR) +#define DDRC_ZQCTL0 DDRC_ZQCTL0_REG(DDRC_BASE_PTR) +#define DDRC_ZQCTL1 DDRC_ZQCTL1_REG(DDRC_BASE_PTR) +#define DDRC_ZQCTL2 DDRC_ZQCTL2_REG(DDRC_BASE_PTR) +#define DDRC_ZQSTAT DDRC_ZQSTAT_REG(DDRC_BASE_PTR) +#define DDRC_DFITMG0 DDRC_DFITMG0_REG(DDRC_BASE_PTR) +#define DDRC_DFITMG1 DDRC_DFITMG1_REG(DDRC_BASE_PTR) +#define DDRC_DFILPCFG0 DDRC_DFILPCFG0_REG(DDRC_BASE_PTR) +#define DDRC_DFIUPD0 DDRC_DFIUPD0_REG(DDRC_BASE_PTR) +#define DDRC_DFIUPD1 DDRC_DFIUPD1_REG(DDRC_BASE_PTR) +#define DDRC_DFIUPD2 DDRC_DFIUPD2_REG(DDRC_BASE_PTR) +#define DDRC_DFIUPD3 DDRC_DFIUPD3_REG(DDRC_BASE_PTR) +#define DDRC_DFIMISC DDRC_DFIMISC_REG(DDRC_BASE_PTR) +#define DDRC_ADDRMAP0 DDRC_ADDRMAP0_REG(DDRC_BASE_PTR) +#define DDRC_ADDRMAP1 DDRC_ADDRMAP1_REG(DDRC_BASE_PTR) +#define DDRC_ADDRMAP2 DDRC_ADDRMAP2_REG(DDRC_BASE_PTR) +#define DDRC_ADDRMAP3 DDRC_ADDRMAP3_REG(DDRC_BASE_PTR) +#define DDRC_ADDRMAP4 DDRC_ADDRMAP4_REG(DDRC_BASE_PTR) +#define DDRC_ADDRMAP5 DDRC_ADDRMAP5_REG(DDRC_BASE_PTR) +#define DDRC_ADDRMAP6 DDRC_ADDRMAP6_REG(DDRC_BASE_PTR) +#define DDRC_ODTCFG DDRC_ODTCFG_REG(DDRC_BASE_PTR) +#define DDRC_ODTMAP DDRC_ODTMAP_REG(DDRC_BASE_PTR) +#define DDRC_SCHED DDRC_SCHED_REG(DDRC_BASE_PTR) +#define DDRC_SCHED1 DDRC_SCHED1_REG(DDRC_BASE_PTR) +#define DDRC_PERFHPR1 DDRC_PERFHPR1_REG(DDRC_BASE_PTR) +#define DDRC_PERFLPR1 DDRC_PERFLPR1_REG(DDRC_BASE_PTR) +#define DDRC_PERFWR1 DDRC_PERFWR1_REG(DDRC_BASE_PTR) +#define DDRC_PERFVPR1 DDRC_PERFVPR1_REG(DDRC_BASE_PTR) +#define DDRC_PERFVPW1 DDRC_PERFVPW1_REG(DDRC_BASE_PTR) +#define DDRC_DBG0 DDRC_DBG0_REG(DDRC_BASE_PTR) +#define DDRC_DBG1 DDRC_DBG1_REG(DDRC_BASE_PTR) +#define DDRC_DBGCAM DDRC_DBGCAM_REG(DDRC_BASE_PTR) +#define DDRC_DBGCMD DDRC_DBGCMD_REG(DDRC_BASE_PTR) +#define DDRC_DBGSTAT DDRC_DBGSTAT_REG(DDRC_BASE_PTR) +#define DDRC_SWCTL DDRC_SWCTL_REG(DDRC_BASE_PTR) +#define DDRC_SWSTAT DDRC_SWSTAT_REG(DDRC_BASE_PTR) + +/*! + * @} + */ /* end of group DDRC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group DDRC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- DDRC_MP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_MP_Peripheral_Access_Layer DDRC_MP Peripheral Access Layer + * @{ + */ + +/** DDRC_MP - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1020]; + __IO uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */ + __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */ + __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */ + __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */ + uint8_t RESERVED_1[4]; + struct { /* offset: 0x410, array step: 0x8 */ + __IO uint32_t PCFGIDMASKCH_0; /**< Port n Channel m Configuration ID Mask Register, array offset: 0x410, array step: 0x8 */ + __IO uint32_t PCFGIDVALUECH_0; /**< Port n Channel m Configuration ID Value Register, array offset: 0x414, array step: 0x8 */ + } PCFGID[16]; + __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */ + __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */ + __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */ + __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */ + __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */ + uint8_t RESERVED_2[2656]; + struct { /* offset: 0xF04, array step: 0x8 */ + __IO uint32_t SARBASE; /**< SAR Base Address Register n, array offset: 0xF04, array step: 0x8 */ + __IO uint32_t SARSIZE; /**< SAR Size Register n, array offset: 0xF08, array step: 0x8 */ + } SAR[4]; +} DDRC_MP_Type, *DDRC_MP_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- DDRC_MP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_MP_Register_Accessor_Macros DDRC_MP - Register accessor macros + * @{ + */ + + +/* DDRC_MP - Register accessors */ +#define DDRC_MP_PSTAT_REG(base) ((base)->PSTAT) +#define DDRC_MP_PCCFG_REG(base) ((base)->PCCFG) +#define DDRC_MP_PCFGR_0_REG(base) ((base)->PCFGR_0) +#define DDRC_MP_PCFGW_0_REG(base) ((base)->PCFGW_0) +#define DDRC_MP_PCFGIDMASKCH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDMASKCH_0) +#define DDRC_MP_PCFGIDVALUECH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDVALUECH_0) +#define DDRC_MP_PCTRL_0_REG(base) ((base)->PCTRL_0) +#define DDRC_MP_PCFGQOS0_0_REG(base) ((base)->PCFGQOS0_0) +#define DDRC_MP_PCFGQOS1_0_REG(base) ((base)->PCFGQOS1_0) +#define DDRC_MP_PCFGWQOS0_0_REG(base) ((base)->PCFGWQOS0_0) +#define DDRC_MP_PCFGWQOS1_0_REG(base) ((base)->PCFGWQOS1_0) +#define DDRC_MP_SARBASE_REG(base,index) ((base)->SAR[index].SARBASE) +#define DDRC_MP_SARSIZE_REG(base,index) ((base)->SAR[index].SARSIZE) + +/*! + * @} + */ /* end of group DDRC_MP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DDRC_MP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_MP_Register_Masks DDRC_MP Register Masks + * @{ + */ + +/* PSTAT Bit Fields */ +#define DDRC_MP_PSTAT_RD_PORT_BUSY_0_MASK 0x1u +#define DDRC_MP_PSTAT_RD_PORT_BUSY_0_SHIFT 0 +/* PCCFG Bit Fields */ +#define DDRC_MP_PCCFG_GO2CRITICAL_EN_MASK 0x1u +#define DDRC_MP_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_MASK 0x10u +#define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +/* PCFGR_0 Bit Fields */ +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_MASK 0x3FFu +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_SHIFT))&DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_MASK) +#define DDRC_MP_PCFGR_0_READ_REORDER_BYPASS_EN_MASK 0x800u +#define DDRC_MP_PCFGR_0_READ_REORDER_BYPASS_EN_SHIFT 11 +#define DDRC_MP_PCFGR_0_RD_PORT_AGING_EN_MASK 0x1000u +#define DDRC_MP_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_MP_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x2000u +#define DDRC_MP_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_MP_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x4000u +#define DDRC_MP_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_MP_PCFGR_0_RDWR_ORDERED_EN_MASK 0x10000u +#define DDRC_MP_PCFGR_0_RDWR_ORDERED_EN_SHIFT 16 +/* PCFGW_0 Bit Fields */ +#define DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_MASK 0x3FFu +#define DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_MP_PCFGW_0_WR_PORT_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_SHIFT))&DDRC_MP_PCFGW_0_WR_PORT_PRIORITY_MASK) +#define DDRC_MP_PCFGW_0_WR_PORT_AGING_EN_MASK 0x1000u +#define DDRC_MP_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_MP_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x2000u +#define DDRC_MP_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_MP_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x4000u +#define DDRC_MP_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 +/* PCFGIDMASKCH_0 Bit Fields */ +#define DDRC_MP_PCFGIDMASKCH_0_ID_MASK_MASK 0xFFFFFFFFu +#define DDRC_MP_PCFGIDMASKCH_0_ID_MASK_SHIFT 0 +#define DDRC_MP_PCFGIDMASKCH_0_ID_MASK(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGIDMASKCH_0_ID_MASK_SHIFT))&DDRC_MP_PCFGIDMASKCH_0_ID_MASK_MASK) +/* PCFGIDVALUECH_0 Bit Fields */ +#define DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_MASK 0xFFFFFFFFu +#define DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_SHIFT 0 +#define DDRC_MP_PCFGIDVALUECH_0_ID_VALUE(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_SHIFT))&DDRC_MP_PCFGIDVALUECH_0_ID_VALUE_MASK) +/* PCTRL_0 Bit Fields */ +#define DDRC_MP_PCTRL_0_PORT_EN_MASK 0x1u +#define DDRC_MP_PCTRL_0_PORT_EN_SHIFT 0 +/* PCFGQOS0_0 Bit Fields */ +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0xFu +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK) +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_MASK 0xF00u +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_LEVEL2_MASK) +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x30000u +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION0_MASK) +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x300000u +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION1_MASK) +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_MASK 0x3000000u +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_SHIFT))&DDRC_MP_PCFGQOS0_0_RQOS_MAP_REGION2_MASK) +/* PCFGQOS1_0 Bit Fields */ +#define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x7FFu +#define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT))&DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK) +#define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x7FF0000u +#define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT))&DDRC_MP_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK) +/* PCFGWQOS0_0 Bit Fields */ +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK 0xFu +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT))&DDRC_MP_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK) +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK 0x30000u +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT))&DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK) +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK 0x300000u +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT))&DDRC_MP_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK) +/* PCFGWQOS1_0 Bit Fields */ +#define DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK 0x7FFu +#define DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT))&DDRC_MP_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK) +/* SARBASE Bit Fields */ +#define DDRC_MP_SARBASE_BASE_ADDR_MASK 0xFFFFFFFFu +#define DDRC_MP_SARBASE_BASE_ADDR_SHIFT 0 +#define DDRC_MP_SARBASE_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_SARBASE_BASE_ADDR_SHIFT))&DDRC_MP_SARBASE_BASE_ADDR_MASK) +/* SARSIZE Bit Fields */ +#define DDRC_MP_SARSIZE_NBLOCKS_MASK 0xFFu +#define DDRC_MP_SARSIZE_NBLOCKS_SHIFT 0 +#define DDRC_MP_SARSIZE_NBLOCKS(x) (((uint32_t)(((uint32_t)(x))<<DDRC_MP_SARSIZE_NBLOCKS_SHIFT))&DDRC_MP_SARSIZE_NBLOCKS_MASK) + +/*! + * @} + */ /* end of group DDRC_MP_Register_Masks */ + + +/* DDRC_MP - Peripheral instance base addresses */ +/** Peripheral DDRC_MP base address */ +#define DDRC_MP_BASE (0x307A0000u) +/** Peripheral DDRC_MP base pointer */ +#define DDRC_MP ((DDRC_MP_Type *)DDRC_MP_BASE) +#define DDRC_MP_BASE_PTR (DDRC_MP) +/** Array initializer of DDRC_MP peripheral base adresses */ +#define DDRC_MP_BASE_ADDRS { DDRC_MP_BASE } +/** Array initializer of DDRC_MP peripheral base pointers */ +#define DDRC_MP_BASE_PTRS { DDRC_MP } + +/* ---------------------------------------------------------------------------- + -- DDRC_MP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_MP_Register_Accessor_Macros DDRC_MP - Register accessor macros + * @{ + */ + + +/* DDRC_MP - Register instance definitions */ +/* DDRC_MP */ +#define DDRC_MP_PSTAT DDRC_MP_PSTAT_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCCFG DDRC_MP_PCCFG_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCFGR_0 DDRC_MP_PCFGR_0_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCFGW_0 DDRC_MP_PCFGW_0_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCFGIDMASKCH_00 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,0) +#define DDRC_MP_PCFGIDVALUECH_00 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,0) +#define DDRC_MP_PCFGIDMASKCH_10 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,1) +#define DDRC_MP_PCFGIDVALUECH_10 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,1) +#define DDRC_MP_PCFGIDMASKCH_20 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,2) +#define DDRC_MP_PCFGIDVALUECH_20 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,2) +#define DDRC_MP_PCFGIDMASKCH_30 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,3) +#define DDRC_MP_PCFGIDVALUECH_30 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,3) +#define DDRC_MP_PCFGIDMASKCH_40 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,4) +#define DDRC_MP_PCFGIDVALUECH_40 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,4) +#define DDRC_MP_PCFGIDMASKCH_50 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,5) +#define DDRC_MP_PCFGIDVALUECH_50 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,5) +#define DDRC_MP_PCFGIDMASKCH_60 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,6) +#define DDRC_MP_PCFGIDVALUECH_60 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,6) +#define DDRC_MP_PCFGIDMASKCH_70 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,7) +#define DDRC_MP_PCFGIDVALUECH_70 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,7) +#define DDRC_MP_PCFGIDMASKCH_80 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,8) +#define DDRC_MP_PCFGIDVALUECH_80 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,8) +#define DDRC_MP_PCFGIDMASKCH_90 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,9) +#define DDRC_MP_PCFGIDVALUECH_90 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,9) +#define DDRC_MP_PCFGIDMASKCH_100 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,10) +#define DDRC_MP_PCFGIDVALUECH_100 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,10) +#define DDRC_MP_PCFGIDMASKCH_110 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,11) +#define DDRC_MP_PCFGIDVALUECH_110 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,11) +#define DDRC_MP_PCFGIDMASKCH_120 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,12) +#define DDRC_MP_PCFGIDVALUECH_120 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,12) +#define DDRC_MP_PCFGIDMASKCH_130 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,13) +#define DDRC_MP_PCFGIDVALUECH_130 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,13) +#define DDRC_MP_PCFGIDMASKCH_140 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,14) +#define DDRC_MP_PCFGIDVALUECH_140 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,14) +#define DDRC_MP_PCFGIDMASKCH_150 DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,15) +#define DDRC_MP_PCFGIDVALUECH_150 DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,15) +#define DDRC_MP_PCTRL_0 DDRC_MP_PCTRL_0_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCFGQOS0_0 DDRC_MP_PCFGQOS0_0_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCFGQOS1_0 DDRC_MP_PCFGQOS1_0_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCFGWQOS0_0 DDRC_MP_PCFGWQOS0_0_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_PCFGWQOS1_0 DDRC_MP_PCFGWQOS1_0_REG(DDRC_MP_BASE_PTR) +#define DDRC_MP_SARBASE0 DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,0) +#define DDRC_MP_SARSIZE0 DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,0) +#define DDRC_MP_SARBASE1 DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,1) +#define DDRC_MP_SARSIZE1 DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,1) +#define DDRC_MP_SARBASE2 DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,2) +#define DDRC_MP_SARSIZE2 DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,2) +#define DDRC_MP_SARBASE3 DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,3) +#define DDRC_MP_SARSIZE3 DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,3) + +/* DDRC_MP - Register array accessors */ +#define DDRC_MP_PCFGIDMASKCH_0(index) DDRC_MP_PCFGIDMASKCH_0_REG(DDRC_MP_BASE_PTR,index) +#define DDRC_MP_PCFGIDVALUECH_0(index) DDRC_MP_PCFGIDVALUECH_0_REG(DDRC_MP_BASE_PTR,index) +#define DDRC_MP_SARBASE(index) DDRC_MP_SARBASE_REG(DDRC_MP_BASE_PTR,index) +#define DDRC_MP_SARSIZE(index) DDRC_MP_SARSIZE_REG(DDRC_MP_BASE_PTR,index) + +/*! + * @} + */ /* end of group DDRC_MP_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group DDRC_MP_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- DDR_PHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDR_PHY_Peripheral_Access_Layer DDR_PHY Peripheral Access Layer + * @{ + */ + +/** DDR_PHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PHY_CON0; /**< , offset: 0x0 */ + __IO uint32_t PHY_CON1; /**< , offset: 0x4 */ + __IO uint32_t PHY_CON2; /**< , offset: 0x8 */ + __IO uint32_t PHY_CON3; /**< , offset: 0xC */ + __IO uint32_t CON4; /**< , offset: 0x10 */ + __IO uint32_t PHY_CON5; /**< , offset: 0x14 */ + union { /* offset: 0x18 */ + __IO uint32_t LP_CON0; /**< , offset: 0x18 */ + __IO uint32_t RODT_CON0; /**< , offset: 0x18 */ + }; + uint8_t RESERVED_0[4]; + __IO uint32_t OFFSET_RD_CON0; /**< , offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OFFSET_WR_CON0; /**< , offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t GATE_CODE_CON0; /**< , offset: 0x40 */ + uint8_t RESERVED_3[8]; + __IO uint32_t SHIFTC_CON0; /**< , offset: 0x4C */ + __IO uint32_t CMD_SDLL_CON0; /**< , offset: 0x50 */ + uint8_t RESERVED_4[24]; + __IO uint32_t LVL_CON0; /**< , offset: 0x6C */ + uint8_t RESERVED_5[8]; + __IO uint32_t LVL_CON3; /**< , offset: 0x78 */ + __IO uint32_t CMD_DESKEW_CON0; /**< , offset: 0x7C */ + __IO uint32_t CMD_DESKEW_CON1; /**< , offset: 0x80 */ + __IO uint32_t CMD_DESKEW_CON2; /**< , offset: 0x84 */ + __IO uint32_t CMD_DESKEW_CON3; /**< , offset: 0x88 */ + uint8_t RESERVED_6[8]; + __IO uint32_t CMD_DESKEW_CON4; /**< , offset: 0x94 */ + uint8_t RESERVED_7[4]; + __IO uint32_t DRVDS_CON0; /**< , offset: 0x9C */ + uint8_t RESERVED_8[16]; + __IO uint32_t MDLL_CON0; /**< , offset: 0xB0 */ + __IO uint32_t MDLL_CON1; /**< , offset: 0xB4 */ + uint8_t RESERVED_9[8]; + __IO uint32_t ZQ_CON0; /**< , offset: 0xC0 */ + __IO uint32_t ZQ_CON1; /**< , offset: 0xC4 */ + __IO uint32_t ZQ_CON2; /**< , offset: 0xC8 */ + uint8_t RESERVED_10[196]; + __IO uint32_t RD_DESKEW_CON0; /**< , offset: 0x190 */ + uint8_t RESERVED_11[8]; + __IO uint32_t RD_DESKEW_CON3; /**< , offset: 0x19C */ + uint8_t RESERVED_12[8]; + __IO uint32_t RD_DESKEW_CON6; /**< , offset: 0x1A8 */ + uint8_t RESERVED_13[8]; + __IO uint32_t RD_DESKEW_CON9; /**< , offset: 0x1B4 */ + uint8_t RESERVED_14[8]; + __IO uint32_t RD_DESKEW_CON12; /**< , offset: 0x1C0 */ + uint8_t RESERVED_15[8]; + __IO uint32_t RD_DESKEW_CON15; /**< , offset: 0x1CC */ + uint8_t RESERVED_16[8]; + __IO uint32_t RD_DESKEW_CON18; /**< , offset: 0x1D8 */ + uint8_t RESERVED_17[8]; + __IO uint32_t RD_DESKEW_CON21; /**< , offset: 0x1E4 */ + uint8_t RESERVED_18[8]; + __IO uint32_t WR_DESKEW_CON0; /**< , offset: 0x1F0 */ + uint8_t RESERVED_19[8]; + __IO uint32_t WR_DESKEW_CON3; /**< , offset: 0x1FC */ + uint8_t RESERVED_20[8]; + __IO uint32_t WR_DESKEW_CON6; /**< , offset: 0x208 */ + uint8_t RESERVED_21[8]; + __IO uint32_t WR_DESKEW_CON9; /**< , offset: 0x214 */ + uint8_t RESERVED_22[8]; + __IO uint32_t WR_DESKEW_CON12; /**< , offset: 0x220 */ + uint8_t RESERVED_23[8]; + __IO uint32_t WR_DESKEW_CON15; /**< , offset: 0x22C */ + uint8_t RESERVED_24[8]; + __IO uint32_t WR_DESKEW_CON18; /**< , offset: 0x238 */ + uint8_t RESERVED_25[8]; + __IO uint32_t WR_DESKEW_CON21; /**< , offset: 0x244 */ + uint8_t RESERVED_26[8]; + __IO uint32_t DM_DESKEW_CON; /**< , offset: 0x250 */ + uint8_t RESERVED_27[332]; + __IO uint32_t RDATA0; /**< , offset: 0x3A0 */ + uint8_t RESERVED_28[8]; + __IO uint32_t STAT0; /**< , offset: 0x3AC */ +} DDR_PHY_Type, *DDR_PHY_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- DDR_PHY - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDR_PHY_Register_Accessor_Macros DDR_PHY - Register accessor macros + * @{ + */ + + +/* DDR_PHY - Register accessors */ +#define DDR_PHY_PHY_CON0_REG(base) ((base)->PHY_CON0) +#define DDR_PHY_PHY_CON1_REG(base) ((base)->PHY_CON1) +#define DDR_PHY_PHY_CON2_REG(base) ((base)->PHY_CON2) +#define DDR_PHY_PHY_CON3_REG(base) ((base)->PHY_CON3) +#define DDR_PHY_CON4_REG(base) ((base)->CON4) +#define DDR_PHY_PHY_CON5_REG(base) ((base)->PHY_CON5) +#define DDR_PHY_LP_CON0_REG(base) ((base)->LP_CON0) +#define DDR_PHY_RODT_CON0_REG(base) ((base)->RODT_CON0) +#define DDR_PHY_OFFSET_RD_CON0_REG(base) ((base)->OFFSET_RD_CON0) +#define DDR_PHY_OFFSET_WR_CON0_REG(base) ((base)->OFFSET_WR_CON0) +#define DDR_PHY_GATE_CODE_CON0_REG(base) ((base)->GATE_CODE_CON0) +#define DDR_PHY_SHIFTC_CON0_REG(base) ((base)->SHIFTC_CON0) +#define DDR_PHY_CMD_SDLL_CON0_REG(base) ((base)->CMD_SDLL_CON0) +#define DDR_PHY_LVL_CON0_REG(base) ((base)->LVL_CON0) +#define DDR_PHY_LVL_CON3_REG(base) ((base)->LVL_CON3) +#define DDR_PHY_CMD_DESKEW_CON0_REG(base) ((base)->CMD_DESKEW_CON0) +#define DDR_PHY_CMD_DESKEW_CON1_REG(base) ((base)->CMD_DESKEW_CON1) +#define DDR_PHY_CMD_DESKEW_CON2_REG(base) ((base)->CMD_DESKEW_CON2) +#define DDR_PHY_CMD_DESKEW_CON3_REG(base) ((base)->CMD_DESKEW_CON3) +#define DDR_PHY_CMD_DESKEW_CON4_REG(base) ((base)->CMD_DESKEW_CON4) +#define DDR_PHY_DRVDS_CON0_REG(base) ((base)->DRVDS_CON0) +#define DDR_PHY_MDLL_CON0_REG(base) ((base)->MDLL_CON0) +#define DDR_PHY_MDLL_CON1_REG(base) ((base)->MDLL_CON1) +#define DDR_PHY_ZQ_CON0_REG(base) ((base)->ZQ_CON0) +#define DDR_PHY_ZQ_CON1_REG(base) ((base)->ZQ_CON1) +#define DDR_PHY_ZQ_CON2_REG(base) ((base)->ZQ_CON2) +#define DDR_PHY_RD_DESKEW_CON0_REG(base) ((base)->RD_DESKEW_CON0) +#define DDR_PHY_RD_DESKEW_CON3_REG(base) ((base)->RD_DESKEW_CON3) +#define DDR_PHY_RD_DESKEW_CON6_REG(base) ((base)->RD_DESKEW_CON6) +#define DDR_PHY_RD_DESKEW_CON9_REG(base) ((base)->RD_DESKEW_CON9) +#define DDR_PHY_RD_DESKEW_CON12_REG(base) ((base)->RD_DESKEW_CON12) +#define DDR_PHY_RD_DESKEW_CON15_REG(base) ((base)->RD_DESKEW_CON15) +#define DDR_PHY_RD_DESKEW_CON18_REG(base) ((base)->RD_DESKEW_CON18) +#define DDR_PHY_RD_DESKEW_CON21_REG(base) ((base)->RD_DESKEW_CON21) +#define DDR_PHY_WR_DESKEW_CON0_REG(base) ((base)->WR_DESKEW_CON0) +#define DDR_PHY_WR_DESKEW_CON3_REG(base) ((base)->WR_DESKEW_CON3) +#define DDR_PHY_WR_DESKEW_CON6_REG(base) ((base)->WR_DESKEW_CON6) +#define DDR_PHY_WR_DESKEW_CON9_REG(base) ((base)->WR_DESKEW_CON9) +#define DDR_PHY_WR_DESKEW_CON12_REG(base) ((base)->WR_DESKEW_CON12) +#define DDR_PHY_WR_DESKEW_CON15_REG(base) ((base)->WR_DESKEW_CON15) +#define DDR_PHY_WR_DESKEW_CON18_REG(base) ((base)->WR_DESKEW_CON18) +#define DDR_PHY_WR_DESKEW_CON21_REG(base) ((base)->WR_DESKEW_CON21) +#define DDR_PHY_DM_DESKEW_CON_REG(base) ((base)->DM_DESKEW_CON) +#define DDR_PHY_RDATA0_REG(base) ((base)->RDATA0) +#define DDR_PHY_STAT0_REG(base) ((base)->STAT0) + +/*! + * @} + */ /* end of group DDR_PHY_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- DDR_PHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDR_PHY_Register_Masks DDR_PHY Register Masks + * @{ + */ + +/* PHY_CON0 Bit Fields */ +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB_MASK 0x7u +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB_SHIFT 0 +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_FNC_FB_SHIFT))&DDR_PHY_PHY_CON0_CTRL_FNC_FB_MASK) +#define DDR_PHY_PHY_CON0_CTRL_TWPRE_MASK 0x8u +#define DDR_PHY_PHY_CON0_CTRL_TWPRE_SHIFT 3 +#define DDR_PHY_PHY_CON0_CTRL_CMOSRCV_MASK 0x10u +#define DDR_PHY_PHY_CON0_CTRL_CMOSRCV_SHIFT 4 +#define DDR_PHY_PHY_CON0_CTRL_ATGATE_MASK 0x40u +#define DDR_PHY_PHY_CON0_CTRL_ATGATE_SHIFT 6 +#define DDR_PHY_PHY_CON0_CTRL_SHGATE_MASK 0x100u +#define DDR_PHY_PHY_CON0_CTRL_SHGATE_SHIFT 8 +#define DDR_PHY_PHY_CON0_CTRL_DFDQS_MASK 0x200u +#define DDR_PHY_PHY_CON0_CTRL_DFDQS_SHIFT 9 +#define DDR_PHY_PHY_CON0_CTRL_DDR_MODE_MASK 0x1800u +#define DDR_PHY_PHY_CON0_CTRL_DDR_MODE_SHIFT 11 +#define DDR_PHY_PHY_CON0_CTRL_DDR_MODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_DDR_MODE_SHIFT))&DDR_PHY_PHY_CON0_CTRL_DDR_MODE_MASK) +#define DDR_PHY_PHY_CON0_WRLVL_MODE_MASK 0x10000u +#define DDR_PHY_PHY_CON0_WRLVL_MODE_SHIFT 16 +#define DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_MASK 0x300000u +#define DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_SHIFT 20 +#define DDR_PHY_PHY_CON0_CTRL_UPD_RANGE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_SHIFT))&DDR_PHY_PHY_CON0_CTRL_UPD_RANGE_MASK) +#define DDR_PHY_PHY_CON0_CTRL_UPD_MODE_MASK 0xC00000u +#define DDR_PHY_PHY_CON0_CTRL_UPD_MODE_SHIFT 22 +#define DDR_PHY_PHY_CON0_CTRL_UPD_MODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON0_CTRL_UPD_MODE_SHIFT))&DDR_PHY_PHY_CON0_CTRL_UPD_MODE_MASK) +/* PHY_CON1 Bit Fields */ +#define DDR_PHY_PHY_CON1_ctrl_gateduradj_MASK 0xF00000u +#define DDR_PHY_PHY_CON1_ctrl_gateduradj_SHIFT 20 +#define DDR_PHY_PHY_CON1_ctrl_gateduradj(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON1_ctrl_gateduradj_SHIFT))&DDR_PHY_PHY_CON1_ctrl_gateduradj_MASK) +#define DDR_PHY_PHY_CON1_CTRL_GATEADJ_MASK 0xF0000000u +#define DDR_PHY_PHY_CON1_CTRL_GATEADJ_SHIFT 28 +#define DDR_PHY_PHY_CON1_CTRL_GATEADJ(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON1_CTRL_GATEADJ_SHIFT))&DDR_PHY_PHY_CON1_CTRL_GATEADJ_MASK) +/* PHY_CON2 Bit Fields */ +#define DDR_PHY_PHY_CON2_RDDESKEW_CLEAR_MASK 0x2000u +#define DDR_PHY_PHY_CON2_RDDESKEW_CLEAR_SHIFT 13 +#define DDR_PHY_PHY_CON2_WRDESKEW_CLEAR_MASK 0x4000u +#define DDR_PHY_PHY_CON2_WRDESKEW_CLEAR_SHIFT 14 +#define DDR_PHY_PHY_CON2_CA_CAL_MODE_MASK 0x800000u +#define DDR_PHY_PHY_CON2_CA_CAL_MODE_SHIFT 23 +#define DDR_PHY_PHY_CON2_GATE_CAL_MODE_MASK 0x1000000u +#define DDR_PHY_PHY_CON2_GATE_CAL_MODE_SHIFT 24 +/* PHY_CON3 Bit Fields */ +#define DDR_PHY_PHY_CON3_REG_MODE_MASK 0xFFu +#define DDR_PHY_PHY_CON3_REG_MODE_SHIFT 0 +#define DDR_PHY_PHY_CON3_REG_MODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON3_REG_MODE_SHIFT))&DDR_PHY_PHY_CON3_REG_MODE_MASK) +#define DDR_PHY_PHY_CON3_WRLVL_START_MASK 0x10000u +#define DDR_PHY_PHY_CON3_WRLVL_START_SHIFT 16 +#define DDR_PHY_PHY_CON3_WL_CAL_MODE_MASK 0x100000u +#define DDR_PHY_PHY_CON3_WL_CAL_MODE_SHIFT 20 +#define DDR_PHY_PHY_CON3_WL_CAL_START_MASK 0x200000u +#define DDR_PHY_PHY_CON3_WL_CAL_START_SHIFT 21 +#define DDR_PHY_PHY_CON3_WRLVL_RESP_MASK 0x1000000u +#define DDR_PHY_PHY_CON3_WRLVL_RESP_SHIFT 24 +#define DDR_PHY_PHY_CON3_WL_CAL_RESP_MASK 0x8000000u +#define DDR_PHY_PHY_CON3_WL_CAL_RESP_SHIFT 27 +/* CON4 Bit Fields */ +#define DDR_PHY_CON4_CTRL_RDLAT_MASK 0x1Fu +#define DDR_PHY_CON4_CTRL_RDLAT_SHIFT 0 +#define DDR_PHY_CON4_CTRL_RDLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CON4_CTRL_RDLAT_SHIFT))&DDR_PHY_CON4_CTRL_RDLAT_MASK) +#define DDR_PHY_CON4_CTRL_BSTLEN_MASK 0x1F00u +#define DDR_PHY_CON4_CTRL_BSTLEN_SHIFT 8 +#define DDR_PHY_CON4_CTRL_BSTLEN(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CON4_CTRL_BSTLEN_SHIFT))&DDR_PHY_CON4_CTRL_BSTLEN_MASK) +#define DDR_PHY_CON4_CTRL_WRLAT_MASK 0x1F0000u +#define DDR_PHY_CON4_CTRL_WRLAT_SHIFT 16 +#define DDR_PHY_CON4_CTRL_WRLAT(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CON4_CTRL_WRLAT_SHIFT))&DDR_PHY_CON4_CTRL_WRLAT_MASK) +/* PHY_CON5 Bit Fields */ +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_MASK 0x7u +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_SHIFT 0 +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_0_MASK) +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_MASK 0x38u +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_SHIFT 3 +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS1_1_MASK) +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_MASK 0x1C0u +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_SHIFT 6 +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS2_MASK) +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_MASK 0xE00u +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_SHIFT 9 +#define DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_SHIFT))&DDR_PHY_PHY_CON5_CTRL_WRLAT_PLUS3_MASK) +/* LP_CON0 Bit Fields */ +#define DDR_PHY_LP_CON0_CTRL_PULLD_DQS_MASK 0x1FFu +#define DDR_PHY_LP_CON0_CTRL_PULLD_DQS_SHIFT 0 +#define DDR_PHY_LP_CON0_CTRL_PULLD_DQS(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LP_CON0_CTRL_PULLD_DQS_SHIFT))&DDR_PHY_LP_CON0_CTRL_PULLD_DQS_MASK) +#define DDR_PHY_LP_CON0_CTRL_PULLD_DQ_MASK 0x1FF0000u +#define DDR_PHY_LP_CON0_CTRL_PULLD_DQ_SHIFT 16 +#define DDR_PHY_LP_CON0_CTRL_PULLD_DQ(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LP_CON0_CTRL_PULLD_DQ_SHIFT))&DDR_PHY_LP_CON0_CTRL_PULLD_DQ_MASK) +/* RODT_CON0 Bit Fields */ +#define DDR_PHY_RODT_CON0_CTRL_READ_DIS_MASK 0x10000u +#define DDR_PHY_RODT_CON0_CTRL_READ_DIS_SHIFT 16 +/* OFFSET_RD_CON0 Bit Fields */ +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_MASK 0xFFu +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_SHIFT 0 +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR0_MASK) +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_MASK 0xFF00u +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_SHIFT 8 +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR1_MASK) +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_MASK 0xFF0000u +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_SHIFT 16 +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR2_MASK) +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_MASK 0xFF000000u +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_SHIFT 24 +#define DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_SHIFT))&DDR_PHY_OFFSET_RD_CON0_CTRL_OFFSETR3_MASK) +/* OFFSET_WR_CON0 Bit Fields */ +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_MASK 0xFFu +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_SHIFT 0 +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW0_MASK) +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_MASK 0xFF00u +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_SHIFT 8 +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW1_MASK) +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_MASK 0xFF0000u +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_SHIFT 16 +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW2_MASK) +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_MASK 0xFF000000u +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_SHIFT 24 +#define DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_SHIFT))&DDR_PHY_OFFSET_WR_CON0_CTRL_OFFSETW3_MASK) +/* GATE_CODE_CON0 Bit Fields */ +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_MASK 0xFFu +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_SHIFT 0 +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC0_MASK) +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_MASK 0xFF00u +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_SHIFT 8 +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC1_MASK) +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_MASK 0xFF0000u +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_SHIFT 16 +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC2_MASK) +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_MASK 0xFF000000u +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_SHIFT 24 +#define DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_SHIFT))&DDR_PHY_GATE_CODE_CON0_CTRL_OFFSETC3_MASK) +/* SHIFTC_CON0 Bit Fields */ +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_MASK 0x7u +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_SHIFT 0 +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC0_MASK) +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_MASK 0x38u +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_SHIFT 3 +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC1_MASK) +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_MASK 0x1C0u +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_SHIFT 6 +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC2_MASK) +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_MASK 0xE00u +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_SHIFT 9 +#define DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_SHIFT))&DDR_PHY_SHIFTC_CON0_CTRL_SHIFTC3_MASK) +/* CMD_SDLL_CON0 Bit Fields */ +#define DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_MASK 0xFFu +#define DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_SHIFT 0 +#define DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_SHIFT))&DDR_PHY_CMD_SDLL_CON0_CTRL_OFFSETD_MASK) +#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK 0x1000000u +#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_SHIFT 24 +#define DDR_PHY_CMD_SDLL_CON0_UPD_MODE_MASK 0x10000000u +#define DDR_PHY_CMD_SDLL_CON0_UPD_MODE_SHIFT 28 +/* LVL_CON0 Bit Fields */ +#define DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_MASK 0xFFu +#define DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_SHIFT 0 +#define DDR_PHY_LVL_CON0_ctrl_wrlvl0_code(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl0_code_MASK) +#define DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_MASK 0xFF00u +#define DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_SHIFT 8 +#define DDR_PHY_LVL_CON0_ctrl_wrlvl1_code(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl1_code_MASK) +#define DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_MASK 0xFF0000u +#define DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_SHIFT 16 +#define DDR_PHY_LVL_CON0_ctrl_wrlvl2_code(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl2_code_MASK) +#define DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_MASK 0xFF000000u +#define DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_SHIFT 24 +#define DDR_PHY_LVL_CON0_ctrl_wrlvl3_code(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_SHIFT))&DDR_PHY_LVL_CON0_ctrl_wrlvl3_code_MASK) +/* LVL_CON3 Bit Fields */ +#define DDR_PHY_LVL_CON3_CTRL_WRLVL_RESYNC_MASK 0x1u +#define DDR_PHY_LVL_CON3_CTRL_WRLVL_RESYNC_SHIFT 0 +/* CMD_DESKEW_CON0 Bit Fields */ +#define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_MASK 0xFFu +#define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_SHIFT 0 +#define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_0_MASK) +#define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_MASK 0xFF00u +#define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_SHIFT 8 +#define DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA1DESKEWCODE_1_MASK) +#define DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_MASK 0xFF0000u +#define DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_SHIFT 16 +#define DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA2DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_MASK 0xFF000000u +#define DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_SHIFT 24 +#define DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON0_CA3DESKEWCODE_MASK) +/* CMD_DESKEW_CON1 Bit Fields */ +#define DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_MASK 0xFFu +#define DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_SHIFT 0 +#define DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA4DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_MASK 0xFF00u +#define DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_SHIFT 8 +#define DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA5DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_MASK 0xFF0000u +#define DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_SHIFT 16 +#define DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA6DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_MASK 0xFF000000u +#define DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_SHIFT 24 +#define DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON1_CA7DESKEWCODE_MASK) +/* CMD_DESKEW_CON2 Bit Fields */ +#define DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_MASK 0xFFu +#define DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_SHIFT 0 +#define DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CA8DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_MASK 0xFF00u +#define DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_SHIFT 8 +#define DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CA9DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_MASK 0xFF0000u +#define DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_SHIFT 16 +#define DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CKDESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_MASK 0xFF000000u +#define DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_SHIFT 24 +#define DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON2_CS0DESKEWCODE_MASK) +/* CMD_DESKEW_CON3 Bit Fields */ +#define DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_MASK 0xFFu +#define DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_SHIFT 0 +#define DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON3_CS1DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_MASK 0xFF00u +#define DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_SHIFT 8 +#define DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON3_CKE0DESKEWCODE_MASK) +#define DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_MASK 0xFF0000u +#define DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_SHIFT 16 +#define DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON3_CKE1DESKEWCODE_MASK) +/* CMD_DESKEW_CON4 Bit Fields */ +#define DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_MASK 0xFFu +#define DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_SHIFT 0 +#define DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_SHIFT))&DDR_PHY_CMD_DESKEW_CON4_RSTDESKEWCODE_MASK) +/* DRVDS_CON0 Bit Fields */ +#define DDR_PHY_DRVDS_CON0_CAADRDRVRDS_MASK 0x7u +#define DDR_PHY_DRVDS_CON0_CAADRDRVRDS_SHIFT 0 +#define DDR_PHY_DRVDS_CON0_CAADRDRVRDS(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CAADRDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CAADRDRVRDS_MASK) +#define DDR_PHY_DRVDS_CON0_CACSDRVRDS_MASK 0x38u +#define DDR_PHY_DRVDS_CON0_CACSDRVRDS_SHIFT 3 +#define DDR_PHY_DRVDS_CON0_CACSDRVRDS(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CACSDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CACSDRVRDS_MASK) +#define DDR_PHY_DRVDS_CON0_CACKEDRVRDS_MASK 0x1C0u +#define DDR_PHY_DRVDS_CON0_CACKEDRVRDS_SHIFT 6 +#define DDR_PHY_DRVDS_CON0_CACKEDRVRDS(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CACKEDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CACKEDRVRDS_MASK) +#define DDR_PHY_DRVDS_CON0_CACKDRVRDS_MASK 0xE00u +#define DDR_PHY_DRVDS_CON0_CACKDRVRDS_SHIFT 9 +#define DDR_PHY_DRVDS_CON0_CACKDRVRDS(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DRVDS_CON0_CACKDRVRDS_SHIFT))&DDR_PHY_DRVDS_CON0_CACKDRVRDS_MASK) +/* MDLL_CON0 Bit Fields */ +#define DDR_PHY_MDLL_CON0_CTRL_REF_MASK 0x1Eu +#define DDR_PHY_MDLL_CON0_CTRL_REF_SHIFT 1 +#define DDR_PHY_MDLL_CON0_CTRL_REF(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_REF_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_REF_MASK) +#define DDR_PHY_MDLL_CON0_CTRL_DLL_ON_MASK 0x20u +#define DDR_PHY_MDLL_CON0_CTRL_DLL_ON_SHIFT 5 +#define DDR_PHY_MDLL_CON0_CTRL_START_MASK 0x40u +#define DDR_PHY_MDLL_CON0_CTRL_START_SHIFT 6 +#define DDR_PHY_MDLL_CON0_CTRL_FORCE_MASK 0xFF80u +#define DDR_PHY_MDLL_CON0_CTRL_FORCE_SHIFT 7 +#define DDR_PHY_MDLL_CON0_CTRL_FORCE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_FORCE_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_FORCE_MASK) +#define DDR_PHY_MDLL_CON0_CTRL_INC_MASK 0x7F0000u +#define DDR_PHY_MDLL_CON0_CTRL_INC_SHIFT 16 +#define DDR_PHY_MDLL_CON0_CTRL_INC(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_INC_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_INC_MASK) +#define DDR_PHY_MDLL_CON0_CTRL_START_POINT_MASK 0x7F000000u +#define DDR_PHY_MDLL_CON0_CTRL_START_POINT_SHIFT 24 +#define DDR_PHY_MDLL_CON0_CTRL_START_POINT(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON0_CTRL_START_POINT_SHIFT))&DDR_PHY_MDLL_CON0_CTRL_START_POINT_MASK) +/* MDLL_CON1 Bit Fields */ +#define DDR_PHY_MDLL_CON1_CTRL_LOCKED_MASK 0x1u +#define DDR_PHY_MDLL_CON1_CTRL_LOCKED_SHIFT 0 +#define DDR_PHY_MDLL_CON1_CTRL_FLOCK_MASK 0x2u +#define DDR_PHY_MDLL_CON1_CTRL_FLOCK_SHIFT 1 +#define DDR_PHY_MDLL_CON1_CTRL_CLOCK_MASK 0x4u +#define DDR_PHY_MDLL_CON1_CTRL_CLOCK_SHIFT 2 +#define DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_MASK 0x1FF00u +#define DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_SHIFT 8 +#define DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_SHIFT))&DDR_PHY_MDLL_CON1_CTRL_LOCK_VALUE_MASK) +/* ZQ_CON0 Bit Fields */ +#define DDR_PHY_ZQ_CON0_ZQ_AUTO_EN_MASK 0x1u +#define DDR_PHY_ZQ_CON0_ZQ_AUTO_EN_SHIFT 0 +#define DDR_PHY_ZQ_CON0_ZQ_MANUAL_STR_MASK 0x2u +#define DDR_PHY_ZQ_CON0_ZQ_MANUAL_STR_SHIFT 1 +#define DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_MASK 0xCu +#define DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_SHIFT 2 +#define DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_MANUAL_MODE_MASK) +#define DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_MASK 0xFF0u +#define DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_SHIFT 4 +#define DDR_PHY_ZQ_CON0_ZQ_UDT_DLY(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_UDT_DLY_MASK) +#define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_MASK 0x7000u +#define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_SHIFT 12 +#define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPP_MASK) +#define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_MASK 0x38000u +#define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_SHIFT 15 +#define DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_FORCE_IMPN_MASK) +#define DDR_PHY_ZQ_CON0_ZQ_CLK_DIV_EN_MASK 0x40000u +#define DDR_PHY_ZQ_CON0_ZQ_CLK_DIV_EN_SHIFT 18 +#define DDR_PHY_ZQ_CON0_ZQ_MODE_NOTERM_MASK 0x80000u +#define DDR_PHY_ZQ_CON0_ZQ_MODE_NOTERM_SHIFT 19 +#define DDR_PHY_ZQ_CON0_ZQ_RGDDR3_MASK 0x100000u +#define DDR_PHY_ZQ_CON0_ZQ_RGDDR3_SHIFT 20 +#define DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_MASK 0xE00000u +#define DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_SHIFT 21 +#define DDR_PHY_ZQ_CON0_ZQ_MODE_TERM(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_MODE_TERM_MASK) +#define DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_MASK 0x7000000u +#define DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_SHIFT 24 +#define DDR_PHY_ZQ_CON0_ZQ_MODE_DDS(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_SHIFT))&DDR_PHY_ZQ_CON0_ZQ_MODE_DDS_MASK) +#define DDR_PHY_ZQ_CON0_ZQ_CLK_EN_MASK 0x8000000u +#define DDR_PHY_ZQ_CON0_ZQ_CLK_EN_SHIFT 27 +/* ZQ_CON1 Bit Fields */ +#define DDR_PHY_ZQ_CON1_ZQ_DONE_MASK 0x1u +#define DDR_PHY_ZQ_CON1_ZQ_DONE_SHIFT 0 +#define DDR_PHY_ZQ_CON1_ZQ_PENDING_MASK 0x2u +#define DDR_PHY_ZQ_CON1_ZQ_PENDING_SHIFT 1 +#define DDR_PHY_ZQ_CON1_ZQ_ERROR_MASK 0x4u +#define DDR_PHY_ZQ_CON1_ZQ_ERROR_SHIFT 2 +#define DDR_PHY_ZQ_CON1_ZQ_NMON_MASK 0x38u +#define DDR_PHY_ZQ_CON1_ZQ_NMON_SHIFT 3 +#define DDR_PHY_ZQ_CON1_ZQ_NMON(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON1_ZQ_NMON_SHIFT))&DDR_PHY_ZQ_CON1_ZQ_NMON_MASK) +#define DDR_PHY_ZQ_CON1_ZQ_PMON_MASK 0x1C0u +#define DDR_PHY_ZQ_CON1_ZQ_PMON_SHIFT 6 +#define DDR_PHY_ZQ_CON1_ZQ_PMON(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON1_ZQ_PMON_SHIFT))&DDR_PHY_ZQ_CON1_ZQ_PMON_MASK) +/* ZQ_CON2 Bit Fields */ +#define DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_MASK 0xFFFFu +#define DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_SHIFT 0 +#define DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_SHIFT))&DDR_PHY_ZQ_CON2_CTRL_ZQ_CLK_DIV_MASK) +/* RD_DESKEW_CON0 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON0_RD0DESKEW3_MASK) +/* RD_DESKEW_CON3 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON3_RD1DESKEW3_MASK) +/* RD_DESKEW_CON6 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON6_RD2DESKEW3_MASK) +/* RD_DESKEW_CON9 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON9_RD3DESKEW3_MASK) +/* RD_DESKEW_CON12 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON12_RD4DESKEW3_MASK) +/* RD_DESKEW_CON15 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON15_RD5DESKEW3_MASK) +/* RD_DESKEW_CON18 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON18_RD6DESKEW3_MASK) +/* RD_DESKEW_CON21 Bit Fields */ +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_MASK 0xFFu +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_SHIFT 0 +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW0_MASK) +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_MASK 0xFF00u +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_SHIFT 8 +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW1_MASK) +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_MASK 0xFF0000u +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_SHIFT 16 +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW2_MASK) +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_MASK 0xFF000000u +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_SHIFT 24 +#define DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_SHIFT))&DDR_PHY_RD_DESKEW_CON21_RD7DESKEW3_MASK) +/* WR_DESKEW_CON0 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON0_WR0DESKEW3_MASK) +/* WR_DESKEW_CON3 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON3_WR1DESKEW3_MASK) +/* WR_DESKEW_CON6 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON6_WR2DESKEW3_MASK) +/* WR_DESKEW_CON9 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON9_WR3DESKEW3_MASK) +/* WR_DESKEW_CON12 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON12_WR4DESKEW3_MASK) +/* WR_DESKEW_CON15 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON15_WR5DESKEW3_MASK) +/* WR_DESKEW_CON18 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON18_RD6DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON18_WR6DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON18_WR6DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON18_WR6DESKEW3_MASK) +/* WR_DESKEW_CON21 Bit Fields */ +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_MASK 0xFFu +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_SHIFT 0 +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW0_MASK) +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_MASK 0xFF00u +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_SHIFT 8 +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW1_MASK) +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_MASK 0xFF0000u +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_SHIFT 16 +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW2_MASK) +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_MASK 0xFF000000u +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_SHIFT 24 +#define DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_SHIFT))&DDR_PHY_WR_DESKEW_CON21_WR7DESKEW3_MASK) +/* DM_DESKEW_CON Bit Fields */ +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW0_MASK 0xFFu +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW0_SHIFT 0 +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW0_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW0_MASK) +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW1_MASK 0xFF00u +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW1_SHIFT 8 +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW1_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW1_MASK) +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW2_MASK 0xFF0000u +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW2_SHIFT 16 +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW2_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW2_MASK) +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW3_MASK 0xFF000000u +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW3_SHIFT 24 +#define DDR_PHY_DM_DESKEW_CON_DMDESKEW3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_DM_DESKEW_CON_DMDESKEW3_SHIFT))&DDR_PHY_DM_DESKEW_CON_DMDESKEW3_MASK) +/* RDATA0 Bit Fields */ +#define DDR_PHY_RDATA0_DQ_IO_RD0_MASK 0xFFu +#define DDR_PHY_RDATA0_DQ_IO_RD0_SHIFT 0 +#define DDR_PHY_RDATA0_DQ_IO_RD0(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD0_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD0_MASK) +#define DDR_PHY_RDATA0_DQ_IO_RD1_MASK 0xFF00u +#define DDR_PHY_RDATA0_DQ_IO_RD1_SHIFT 8 +#define DDR_PHY_RDATA0_DQ_IO_RD1(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD1_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD1_MASK) +#define DDR_PHY_RDATA0_DQ_IO_RD2_MASK 0xFF0000u +#define DDR_PHY_RDATA0_DQ_IO_RD2_SHIFT 16 +#define DDR_PHY_RDATA0_DQ_IO_RD2(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD2_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD2_MASK) +#define DDR_PHY_RDATA0_DQ_IO_RD3_MASK 0xFF000000u +#define DDR_PHY_RDATA0_DQ_IO_RD3_SHIFT 24 +#define DDR_PHY_RDATA0_DQ_IO_RD3(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_RDATA0_DQ_IO_RD3_SHIFT))&DDR_PHY_RDATA0_DQ_IO_RD3_MASK) +/* STAT0 Bit Fields */ +#define DDR_PHY_STAT0_VERSION_INFO_MASK 0xFFFFFFFFu +#define DDR_PHY_STAT0_VERSION_INFO_SHIFT 0 +#define DDR_PHY_STAT0_VERSION_INFO(x) (((uint32_t)(((uint32_t)(x))<<DDR_PHY_STAT0_VERSION_INFO_SHIFT))&DDR_PHY_STAT0_VERSION_INFO_MASK) + +/*! + * @} + */ /* end of group DDR_PHY_Register_Masks */ + + +/* DDR_PHY - Peripheral instance base addresses */ +/** Peripheral DDR_PHY base address */ +#define DDR_PHY_BASE (0x30790000u) +/** Peripheral DDR_PHY base pointer */ +#define DDR_PHY ((DDR_PHY_Type *)DDR_PHY_BASE) +#define DDR_PHY_BASE_PTR (DDR_PHY) +/** Array initializer of DDR_PHY peripheral base adresses */ +#define DDR_PHY_BASE_ADDRS { DDR_PHY_BASE } +/** Array initializer of DDR_PHY peripheral base pointers */ +#define DDR_PHY_BASE_PTRS { DDR_PHY } + +/* ---------------------------------------------------------------------------- + -- DDR_PHY - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDR_PHY_Register_Accessor_Macros DDR_PHY - Register accessor macros + * @{ + */ + + +/* DDR_PHY - Register instance definitions */ +/* DDR_PHY */ +#define DDR_PHY_PHY_CON0 DDR_PHY_PHY_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_PHY_CON1 DDR_PHY_PHY_CON1_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_PHY_CON2 DDR_PHY_PHY_CON2_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_PHY_CON3 DDR_PHY_PHY_CON3_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_CON4 DDR_PHY_CON4_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_PHY_CON5 DDR_PHY_PHY_CON5_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_LP_CON0 DDR_PHY_LP_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RODT_CON0 DDR_PHY_RODT_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_OFFSET_RD_CON0 DDR_PHY_OFFSET_RD_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_OFFSET_WR_CON0 DDR_PHY_OFFSET_WR_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_GATE_CODE_CON0 DDR_PHY_GATE_CODE_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_SHIFTC_CON0 DDR_PHY_SHIFTC_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_CMD_SDLL_CON0 DDR_PHY_CMD_SDLL_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_LVL_CON0 DDR_PHY_LVL_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_LVL_CON3 DDR_PHY_LVL_CON3_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_CMD_DESKEW_CON0 DDR_PHY_CMD_DESKEW_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_CMD_DESKEW_CON1 DDR_PHY_CMD_DESKEW_CON1_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_CMD_DESKEW_CON2 DDR_PHY_CMD_DESKEW_CON2_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_CMD_DESKEW_CON3 DDR_PHY_CMD_DESKEW_CON3_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_CMD_DESKEW_CON4 DDR_PHY_CMD_DESKEW_CON4_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_DRVDS_CON0 DDR_PHY_DRVDS_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_MDLL_CON0 DDR_PHY_MDLL_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_MDLL_CON1 DDR_PHY_MDLL_CON1_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_ZQ_CON0 DDR_PHY_ZQ_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_ZQ_CON1 DDR_PHY_ZQ_CON1_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_ZQ_CON2 DDR_PHY_ZQ_CON2_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON0 DDR_PHY_RD_DESKEW_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON3 DDR_PHY_RD_DESKEW_CON3_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON6 DDR_PHY_RD_DESKEW_CON6_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON9 DDR_PHY_RD_DESKEW_CON9_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON12 DDR_PHY_RD_DESKEW_CON12_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON15 DDR_PHY_RD_DESKEW_CON15_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON18 DDR_PHY_RD_DESKEW_CON18_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RD_DESKEW_CON21 DDR_PHY_RD_DESKEW_CON21_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON0 DDR_PHY_WR_DESKEW_CON0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON3 DDR_PHY_WR_DESKEW_CON3_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON6 DDR_PHY_WR_DESKEW_CON6_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON9 DDR_PHY_WR_DESKEW_CON9_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON12 DDR_PHY_WR_DESKEW_CON12_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON15 DDR_PHY_WR_DESKEW_CON15_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON18 DDR_PHY_WR_DESKEW_CON18_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_WR_DESKEW_CON21 DDR_PHY_WR_DESKEW_CON21_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_DM_DESKEW_CON DDR_PHY_DM_DESKEW_CON_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_RDATA0 DDR_PHY_RDATA0_REG(DDR_PHY_BASE_PTR) +#define DDR_PHY_STAT0 DDR_PHY_STAT0_REG(DDR_PHY_BASE_PTR) + +/*! + * @} + */ /* end of group DDR_PHY_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group DDR_PHY_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ECSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer + * @{ + */ + +/** ECSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ + __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ + __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ + __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ + __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ + __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ + __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ + __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ + uint8_t RESERVED_0[28]; + __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ +} ECSPI_Type, *ECSPI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ECSPI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros + * @{ + */ + + +/* ECSPI - Register accessors */ +#define ECSPI_RXDATA_REG(base) ((base)->RXDATA) +#define ECSPI_TXDATA_REG(base) ((base)->TXDATA) +#define ECSPI_CONREG_REG(base) ((base)->CONREG) +#define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) +#define ECSPI_INTREG_REG(base) ((base)->INTREG) +#define ECSPI_DMAREG_REG(base) ((base)->DMAREG) +#define ECSPI_STATREG_REG(base) ((base)->STATREG) +#define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) +#define ECSPI_TESTREG_REG(base) ((base)->TESTREG) +#define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) + +/*! + * @} + */ /* end of group ECSPI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/* RXDATA Bit Fields */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_RXDATA_ECSPI_RXDATA_SHIFT))&ECSPI_RXDATA_ECSPI_RXDATA_MASK) +/* TXDATA Bit Fields */ +#define ECSPI_TXDATA_ECSPI_TXDATA_MASK 0xFFFFFFFFu +#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT 0 +#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_TXDATA_ECSPI_TXDATA_SHIFT))&ECSPI_TXDATA_ECSPI_TXDATA_MASK) +/* CONREG Bit Fields */ +#define ECSPI_CONREG_EN_MASK 0x1u +#define ECSPI_CONREG_EN_SHIFT 0 +#define ECSPI_CONREG_HT_MASK 0x2u +#define ECSPI_CONREG_HT_SHIFT 1 +#define ECSPI_CONREG_XCH_MASK 0x4u +#define ECSPI_CONREG_XCH_SHIFT 2 +#define ECSPI_CONREG_SMC_MASK 0x8u +#define ECSPI_CONREG_SMC_SHIFT 3 +#define ECSPI_CONREG_CHANNEL_MODE_MASK 0xF0u +#define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4 +#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_MODE_SHIFT))&ECSPI_CONREG_CHANNEL_MODE_MASK) +#define ECSPI_CONREG_POST_DIVIDER_MASK 0xF00u +#define ECSPI_CONREG_POST_DIVIDER_SHIFT 8 +#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_POST_DIVIDER_SHIFT))&ECSPI_CONREG_POST_DIVIDER_MASK) +#define ECSPI_CONREG_PRE_DIVIDER_MASK 0xF000u +#define ECSPI_CONREG_PRE_DIVIDER_SHIFT 12 +#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_PRE_DIVIDER_SHIFT))&ECSPI_CONREG_PRE_DIVIDER_MASK) +#define ECSPI_CONREG_DRCTL_MASK 0x30000u +#define ECSPI_CONREG_DRCTL_SHIFT 16 +#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_DRCTL_SHIFT))&ECSPI_CONREG_DRCTL_MASK) +#define ECSPI_CONREG_CHANNEL_SELECT_MASK 0xC0000u +#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18 +#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_CHANNEL_SELECT_SHIFT))&ECSPI_CONREG_CHANNEL_SELECT_MASK) +#define ECSPI_CONREG_BURST_LENGTH_MASK 0xFFF00000u +#define ECSPI_CONREG_BURST_LENGTH_SHIFT 20 +#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONREG_BURST_LENGTH_SHIFT))&ECSPI_CONREG_BURST_LENGTH_MASK) +/* CONFIGREG Bit Fields */ +#define ECSPI_CONFIGREG_SCLK_PHA_MASK 0xFu +#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT 0 +#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_PHA_SHIFT))&ECSPI_CONFIGREG_SCLK_PHA_MASK) +#define ECSPI_CONFIGREG_SCLK_POL_MASK 0xF0u +#define ECSPI_CONFIGREG_SCLK_POL_SHIFT 4 +#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_POL_SHIFT))&ECSPI_CONFIGREG_SCLK_POL_MASK) +#define ECSPI_CONFIGREG_SS_CTL_MASK 0xF00u +#define ECSPI_CONFIGREG_SS_CTL_SHIFT 8 +#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_CTL_SHIFT))&ECSPI_CONFIGREG_SS_CTL_MASK) +#define ECSPI_CONFIGREG_SS_POL_MASK 0xF000u +#define ECSPI_CONFIGREG_SS_POL_SHIFT 12 +#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SS_POL_SHIFT))&ECSPI_CONFIGREG_SS_POL_MASK) +#define ECSPI_CONFIGREG_DATA_CTL_MASK 0xF0000u +#define ECSPI_CONFIGREG_DATA_CTL_SHIFT 16 +#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_DATA_CTL_SHIFT))&ECSPI_CONFIGREG_DATA_CTL_MASK) +#define ECSPI_CONFIGREG_SCLK_CTL_MASK 0xF00000u +#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT 20 +#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_SCLK_CTL_SHIFT))&ECSPI_CONFIGREG_SCLK_CTL_MASK) +#define ECSPI_CONFIGREG_HT_LENGTH_MASK 0x1F000000u +#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT 24 +#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_CONFIGREG_HT_LENGTH_SHIFT))&ECSPI_CONFIGREG_HT_LENGTH_MASK) +/* INTREG Bit Fields */ +#define ECSPI_INTREG_TEEN_MASK 0x1u +#define ECSPI_INTREG_TEEN_SHIFT 0 +#define ECSPI_INTREG_TDREN_MASK 0x2u +#define ECSPI_INTREG_TDREN_SHIFT 1 +#define ECSPI_INTREG_TFEN_MASK 0x4u +#define ECSPI_INTREG_TFEN_SHIFT 2 +#define ECSPI_INTREG_RREN_MASK 0x8u +#define ECSPI_INTREG_RREN_SHIFT 3 +#define ECSPI_INTREG_RDREN_MASK 0x10u +#define ECSPI_INTREG_RDREN_SHIFT 4 +#define ECSPI_INTREG_RFEN_MASK 0x20u +#define ECSPI_INTREG_RFEN_SHIFT 5 +#define ECSPI_INTREG_ROEN_MASK 0x40u +#define ECSPI_INTREG_ROEN_SHIFT 6 +#define ECSPI_INTREG_TCEN_MASK 0x80u +#define ECSPI_INTREG_TCEN_SHIFT 7 +/* DMAREG Bit Fields */ +#define ECSPI_DMAREG_TX_THRESHOLD_MASK 0x3Fu +#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT 0 +#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_TX_THRESHOLD_SHIFT))&ECSPI_DMAREG_TX_THRESHOLD_MASK) +#define ECSPI_DMAREG_TEDEN_MASK 0x80u +#define ECSPI_DMAREG_TEDEN_SHIFT 7 +#define ECSPI_DMAREG_RX_THRESHOLD_MASK 0x3F0000u +#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16 +#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_THRESHOLD_SHIFT))&ECSPI_DMAREG_RX_THRESHOLD_MASK) +#define ECSPI_DMAREG_RXDEN_MASK 0x800000u +#define ECSPI_DMAREG_RXDEN_SHIFT 23 +#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK 0x3F000000u +#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT 24 +#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT))&ECSPI_DMAREG_RX_DMA_LENGTH_MASK) +#define ECSPI_DMAREG_RXTDEN_MASK 0x80000000u +#define ECSPI_DMAREG_RXTDEN_SHIFT 31 +/* STATREG Bit Fields */ +#define ECSPI_STATREG_TE_MASK 0x1u +#define ECSPI_STATREG_TE_SHIFT 0 +#define ECSPI_STATREG_TDR_MASK 0x2u +#define ECSPI_STATREG_TDR_SHIFT 1 +#define ECSPI_STATREG_TF_MASK 0x4u +#define ECSPI_STATREG_TF_SHIFT 2 +#define ECSPI_STATREG_RR_MASK 0x8u +#define ECSPI_STATREG_RR_SHIFT 3 +#define ECSPI_STATREG_RDR_MASK 0x10u +#define ECSPI_STATREG_RDR_SHIFT 4 +#define ECSPI_STATREG_RF_MASK 0x20u +#define ECSPI_STATREG_RF_SHIFT 5 +#define ECSPI_STATREG_RO_MASK 0x40u +#define ECSPI_STATREG_RO_SHIFT 6 +#define ECSPI_STATREG_TC_MASK 0x80u +#define ECSPI_STATREG_TC_SHIFT 7 +/* PERIODREG Bit Fields */ +#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK 0x7FFFu +#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT 0 +#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT))&ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) +#define ECSPI_PERIODREG_CSRC_MASK 0x8000u +#define ECSPI_PERIODREG_CSRC_SHIFT 15 +#define ECSPI_PERIODREG_CSD_CTL_MASK 0x3F0000u +#define ECSPI_PERIODREG_CSD_CTL_SHIFT 16 +#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_PERIODREG_CSD_CTL_SHIFT))&ECSPI_PERIODREG_CSD_CTL_MASK) +/* TESTREG Bit Fields */ +#define ECSPI_TESTREG_TXCNT_MASK 0x7Fu +#define ECSPI_TESTREG_TXCNT_SHIFT 0 +#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_TXCNT_SHIFT))&ECSPI_TESTREG_TXCNT_MASK) +#define ECSPI_TESTREG_RXCNT_MASK 0x7F00u +#define ECSPI_TESTREG_RXCNT_SHIFT 8 +#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_TESTREG_RXCNT_SHIFT))&ECSPI_TESTREG_RXCNT_MASK) +#define ECSPI_TESTREG_LBC_MASK 0x80000000u +#define ECSPI_TESTREG_LBC_SHIFT 31 +/* MSGDATA Bit Fields */ +#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK 0xFFFFFFFFu +#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT 0 +#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x))<<ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT))&ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) + +/*! + * @} + */ /* end of group ECSPI_Register_Masks */ + + +/* ECSPI - Peripheral instance base addresses */ +/** Peripheral ECSPI1 base address */ +#define ECSPI1_BASE (0x30820000u) +/** Peripheral ECSPI1 base pointer */ +#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) +#define ECSPI1_BASE_PTR (ECSPI1) +/** Peripheral ECSPI2 base address */ +#define ECSPI2_BASE (0x30830000u) +/** Peripheral ECSPI2 base pointer */ +#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) +#define ECSPI2_BASE_PTR (ECSPI2) +/** Peripheral ECSPI3 base address */ +#define ECSPI3_BASE (0x30840000u) +/** Peripheral ECSPI3 base pointer */ +#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) +#define ECSPI3_BASE_PTR (ECSPI3) +/** Peripheral ECSPI4 base address */ +#define ECSPI4_BASE (0x30630000u) +/** Peripheral ECSPI4 base pointer */ +#define ECSPI4 ((ECSPI_Type *)ECSPI4_BASE) +#define ECSPI4_BASE_PTR (ECSPI4) +/** Array initializer of ECSPI peripheral base adresses */ +#define ECSPI_BASE_ADDRS { ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE } +/** Array initializer of ECSPI peripheral base pointers */ +#define ECSPI_BASE_PTRS { ECSPI1, ECSPI2, ECSPI3, ECSPI4 } + +/* ---------------------------------------------------------------------------- + -- ECSPI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Accessor_Macros ECSPI - Register accessor macros + * @{ + */ + + +/* ECSPI - Register instance definitions */ +/* ECSPI1 */ +#define ECSPI1_RXDATA ECSPI_RXDATA_REG(ECSPI1_BASE_PTR) +#define ECSPI1_TXDATA ECSPI_TXDATA_REG(ECSPI1_BASE_PTR) +#define ECSPI1_CONREG ECSPI_CONREG_REG(ECSPI1_BASE_PTR) +#define ECSPI1_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI1_BASE_PTR) +#define ECSPI1_INTREG ECSPI_INTREG_REG(ECSPI1_BASE_PTR) +#define ECSPI1_DMAREG ECSPI_DMAREG_REG(ECSPI1_BASE_PTR) +#define ECSPI1_STATREG ECSPI_STATREG_REG(ECSPI1_BASE_PTR) +#define ECSPI1_PERIODREG ECSPI_PERIODREG_REG(ECSPI1_BASE_PTR) +#define ECSPI1_TESTREG ECSPI_TESTREG_REG(ECSPI1_BASE_PTR) +#define ECSPI1_MSGDATA ECSPI_MSGDATA_REG(ECSPI1_BASE_PTR) +/* ECSPI2 */ +#define ECSPI2_RXDATA ECSPI_RXDATA_REG(ECSPI2_BASE_PTR) +#define ECSPI2_TXDATA ECSPI_TXDATA_REG(ECSPI2_BASE_PTR) +#define ECSPI2_CONREG ECSPI_CONREG_REG(ECSPI2_BASE_PTR) +#define ECSPI2_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI2_BASE_PTR) +#define ECSPI2_INTREG ECSPI_INTREG_REG(ECSPI2_BASE_PTR) +#define ECSPI2_DMAREG ECSPI_DMAREG_REG(ECSPI2_BASE_PTR) +#define ECSPI2_STATREG ECSPI_STATREG_REG(ECSPI2_BASE_PTR) +#define ECSPI2_PERIODREG ECSPI_PERIODREG_REG(ECSPI2_BASE_PTR) +#define ECSPI2_TESTREG ECSPI_TESTREG_REG(ECSPI2_BASE_PTR) +#define ECSPI2_MSGDATA ECSPI_MSGDATA_REG(ECSPI2_BASE_PTR) +/* ECSPI3 */ +#define ECSPI3_RXDATA ECSPI_RXDATA_REG(ECSPI3_BASE_PTR) +#define ECSPI3_TXDATA ECSPI_TXDATA_REG(ECSPI3_BASE_PTR) +#define ECSPI3_CONREG ECSPI_CONREG_REG(ECSPI3_BASE_PTR) +#define ECSPI3_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI3_BASE_PTR) +#define ECSPI3_INTREG ECSPI_INTREG_REG(ECSPI3_BASE_PTR) +#define ECSPI3_DMAREG ECSPI_DMAREG_REG(ECSPI3_BASE_PTR) +#define ECSPI3_STATREG ECSPI_STATREG_REG(ECSPI3_BASE_PTR) +#define ECSPI3_PERIODREG ECSPI_PERIODREG_REG(ECSPI3_BASE_PTR) +#define ECSPI3_TESTREG ECSPI_TESTREG_REG(ECSPI3_BASE_PTR) +#define ECSPI3_MSGDATA ECSPI_MSGDATA_REG(ECSPI3_BASE_PTR) +/* ECSPI4 */ +#define ECSPI4_RXDATA ECSPI_RXDATA_REG(ECSPI4_BASE_PTR) +#define ECSPI4_TXDATA ECSPI_TXDATA_REG(ECSPI4_BASE_PTR) +#define ECSPI4_CONREG ECSPI_CONREG_REG(ECSPI4_BASE_PTR) +#define ECSPI4_CONFIGREG ECSPI_CONFIGREG_REG(ECSPI4_BASE_PTR) +#define ECSPI4_INTREG ECSPI_INTREG_REG(ECSPI4_BASE_PTR) +#define ECSPI4_DMAREG ECSPI_DMAREG_REG(ECSPI4_BASE_PTR) +#define ECSPI4_STATREG ECSPI_STATREG_REG(ECSPI4_BASE_PTR) +#define ECSPI4_PERIODREG ECSPI_PERIODREG_REG(ECSPI4_BASE_PTR) +#define ECSPI4_TESTREG ECSPI_TESTREG_REG(ECSPI4_BASE_PTR) +#define ECSPI4_MSGDATA ECSPI_MSGDATA_REG(ECSPI4_BASE_PTR) + +/*! + * @} + */ /* end of group ECSPI_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group ECSPI_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x18 */ + __IO uint32_t CSGCR1; /**< Chip Select n General Configuration Register 1, array offset: 0x0, array step: 0x18 */ + __IO uint32_t CSGCR2; /**< Chip Select n General Configuration Register 2, array offset: 0x4, array step: 0x18 */ + __IO uint32_t CSRCR1; /**< Chip Select n Read Configuration Register 1, array offset: 0x8, array step: 0x18 */ + __IO uint32_t CSRCR2; /**< Chip Select n Read Configuration Register 2, array offset: 0xC, array step: 0x18 */ + __IO uint32_t CSWCR1; /**< Chip Select n Write Configuration Register 1, array offset: 0x10, array step: 0x18 */ + __IO uint32_t CSWCR2; /**< Chip Select n Write Configuration Register 2, array offset: 0x14, array step: 0x18 */ + } CSCR[6]; + __IO uint32_t WCR; /**< EIM Configuration Register, offset: 0x90 */ + __IO uint32_t DCR; /**< DLL Control Register, offset: 0x94 */ + __I uint32_t DSR; /**< DLL Status Register, offset: 0x98 */ + __IO uint32_t WIAR; /**< EIM IP Access Register, offset: 0x9C */ + __IO uint32_t EAR; /**< Error Address Register, offset: 0xA0 */ +} EIM_Type, *EIM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- EIM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros + * @{ + */ + + +/* EIM - Register accessors */ +#define EIM_CSGCR1_REG(base,index) ((base)->CSCR[index].CSGCR1) +#define EIM_CSGCR2_REG(base,index) ((base)->CSCR[index].CSGCR2) +#define EIM_CSRCR1_REG(base,index) ((base)->CSCR[index].CSRCR1) +#define EIM_CSRCR2_REG(base,index) ((base)->CSCR[index].CSRCR2) +#define EIM_CSWCR1_REG(base,index) ((base)->CSCR[index].CSWCR1) +#define EIM_CSWCR2_REG(base,index) ((base)->CSCR[index].CSWCR2) +#define EIM_WCR_REG(base) ((base)->WCR) +#define EIM_DCR_REG(base) ((base)->DCR) +#define EIM_DSR_REG(base) ((base)->DSR) +#define EIM_WIAR_REG(base) ((base)->WIAR) +#define EIM_EAR_REG(base) ((base)->EAR) + +/*! + * @} + */ /* end of group EIM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/* CSGCR1 Bit Fields */ +#define EIM_CSGCR1_CSEN_MASK 0x1u +#define EIM_CSGCR1_CSEN_SHIFT 0 +#define EIM_CSGCR1_SWR_MASK 0x2u +#define EIM_CSGCR1_SWR_SHIFT 1 +#define EIM_CSGCR1_SRD_MASK 0x4u +#define EIM_CSGCR1_SRD_SHIFT 2 +#define EIM_CSGCR1_MUM_MASK 0x8u +#define EIM_CSGCR1_MUM_SHIFT 3 +#define EIM_CSGCR1_WFL_MASK 0x10u +#define EIM_CSGCR1_WFL_SHIFT 4 +#define EIM_CSGCR1_RFL_MASK 0x20u +#define EIM_CSGCR1_RFL_SHIFT 5 +#define EIM_CSGCR1_CRE_MASK 0x40u +#define EIM_CSGCR1_CRE_SHIFT 6 +#define EIM_CSGCR1_CREP_MASK 0x80u +#define EIM_CSGCR1_CREP_SHIFT 7 +#define EIM_CSGCR1_BL_MASK 0x700u +#define EIM_CSGCR1_BL_SHIFT 8 +#define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BL_SHIFT))&EIM_CSGCR1_BL_MASK) +#define EIM_CSGCR1_WC_MASK 0x800u +#define EIM_CSGCR1_WC_SHIFT 11 +#define EIM_CSGCR1_BCD_MASK 0x3000u +#define EIM_CSGCR1_BCD_SHIFT 12 +#define EIM_CSGCR1_BCD(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCD_SHIFT))&EIM_CSGCR1_BCD_MASK) +#define EIM_CSGCR1_BCS_MASK 0xC000u +#define EIM_CSGCR1_BCS_SHIFT 14 +#define EIM_CSGCR1_BCS(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_BCS_SHIFT))&EIM_CSGCR1_BCS_MASK) +#define EIM_CSGCR1_DSZ_MASK 0x70000u +#define EIM_CSGCR1_DSZ_SHIFT 16 +#define EIM_CSGCR1_DSZ(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_DSZ_SHIFT))&EIM_CSGCR1_DSZ_MASK) +#define EIM_CSGCR1_SP_MASK 0x80000u +#define EIM_CSGCR1_SP_SHIFT 19 +#define EIM_CSGCR1_CSREC_MASK 0x700000u +#define EIM_CSGCR1_CSREC_SHIFT 20 +#define EIM_CSGCR1_CSREC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_CSREC_SHIFT))&EIM_CSGCR1_CSREC_MASK) +#define EIM_CSGCR1_AUS_MASK 0x800000u +#define EIM_CSGCR1_AUS_SHIFT 23 +#define EIM_CSGCR1_GBC_MASK 0x7000000u +#define EIM_CSGCR1_GBC_SHIFT 24 +#define EIM_CSGCR1_GBC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_GBC_SHIFT))&EIM_CSGCR1_GBC_MASK) +#define EIM_CSGCR1_WP_MASK 0x8000000u +#define EIM_CSGCR1_WP_SHIFT 27 +#define EIM_CSGCR1_PSZ_MASK 0xF0000000u +#define EIM_CSGCR1_PSZ_SHIFT 28 +#define EIM_CSGCR1_PSZ(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR1_PSZ_SHIFT))&EIM_CSGCR1_PSZ_MASK) +/* CSGCR2 Bit Fields */ +#define EIM_CSGCR2_ADH_MASK 0x3u +#define EIM_CSGCR2_ADH_SHIFT 0 +#define EIM_CSGCR2_ADH(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_ADH_SHIFT))&EIM_CSGCR2_ADH_MASK) +#define EIM_CSGCR2_DAPS_MASK 0xF0u +#define EIM_CSGCR2_DAPS_SHIFT 4 +#define EIM_CSGCR2_DAPS(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSGCR2_DAPS_SHIFT))&EIM_CSGCR2_DAPS_MASK) +#define EIM_CSGCR2_DAE_MASK 0x100u +#define EIM_CSGCR2_DAE_SHIFT 8 +#define EIM_CSGCR2_DAP_MASK 0x200u +#define EIM_CSGCR2_DAP_SHIFT 9 +#define EIM_CSGCR2_MUX16_BYP_GRANT_MASK 0x1000u +#define EIM_CSGCR2_MUX16_BYP_GRANT_SHIFT 12 +/* CSRCR1 Bit Fields */ +#define EIM_CSRCR1_RCSN_MASK 0x7u +#define EIM_CSRCR1_RCSN_SHIFT 0 +#define EIM_CSRCR1_RCSN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSN_SHIFT))&EIM_CSRCR1_RCSN_MASK) +#define EIM_CSRCR1_RCSA_MASK 0x70u +#define EIM_CSRCR1_RCSA_SHIFT 4 +#define EIM_CSRCR1_RCSA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RCSA_SHIFT))&EIM_CSRCR1_RCSA_MASK) +#define EIM_CSRCR1_OEN_MASK 0x700u +#define EIM_CSRCR1_OEN_SHIFT 8 +#define EIM_CSRCR1_OEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEN_SHIFT))&EIM_CSRCR1_OEN_MASK) +#define EIM_CSRCR1_OEA_MASK 0x7000u +#define EIM_CSRCR1_OEA_SHIFT 12 +#define EIM_CSRCR1_OEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_OEA_SHIFT))&EIM_CSRCR1_OEA_MASK) +#define EIM_CSRCR1_RADVN_MASK 0x70000u +#define EIM_CSRCR1_RADVN_SHIFT 16 +#define EIM_CSRCR1_RADVN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVN_SHIFT))&EIM_CSRCR1_RADVN_MASK) +#define EIM_CSRCR1_RAL_MASK 0x80000u +#define EIM_CSRCR1_RAL_SHIFT 19 +#define EIM_CSRCR1_RADVA_MASK 0x700000u +#define EIM_CSRCR1_RADVA_SHIFT 20 +#define EIM_CSRCR1_RADVA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RADVA_SHIFT))&EIM_CSRCR1_RADVA_MASK) +#define EIM_CSRCR1_RWSC_MASK 0x3F000000u +#define EIM_CSRCR1_RWSC_SHIFT 24 +#define EIM_CSRCR1_RWSC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR1_RWSC_SHIFT))&EIM_CSRCR1_RWSC_MASK) +/* CSRCR2 Bit Fields */ +#define EIM_CSRCR2_RBEN_MASK 0x7u +#define EIM_CSRCR2_RBEN_SHIFT 0 +#define EIM_CSRCR2_RBEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEN_SHIFT))&EIM_CSRCR2_RBEN_MASK) +#define EIM_CSRCR2_RBE_MASK 0x8u +#define EIM_CSRCR2_RBE_SHIFT 3 +#define EIM_CSRCR2_RBEA_MASK 0x70u +#define EIM_CSRCR2_RBEA_SHIFT 4 +#define EIM_CSRCR2_RBEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RBEA_SHIFT))&EIM_CSRCR2_RBEA_MASK) +#define EIM_CSRCR2_RL_MASK 0x300u +#define EIM_CSRCR2_RL_SHIFT 8 +#define EIM_CSRCR2_RL(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_RL_SHIFT))&EIM_CSRCR2_RL_MASK) +#define EIM_CSRCR2_PAT_MASK 0x7000u +#define EIM_CSRCR2_PAT_SHIFT 12 +#define EIM_CSRCR2_PAT(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSRCR2_PAT_SHIFT))&EIM_CSRCR2_PAT_MASK) +#define EIM_CSRCR2_APR_MASK 0x8000u +#define EIM_CSRCR2_APR_SHIFT 15 +/* CSWCR1 Bit Fields */ +#define EIM_CSWCR1_WCSN_MASK 0x7u +#define EIM_CSWCR1_WCSN_SHIFT 0 +#define EIM_CSWCR1_WCSN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSN_SHIFT))&EIM_CSWCR1_WCSN_MASK) +#define EIM_CSWCR1_WCSA_MASK 0x38u +#define EIM_CSWCR1_WCSA_SHIFT 3 +#define EIM_CSWCR1_WCSA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WCSA_SHIFT))&EIM_CSWCR1_WCSA_MASK) +#define EIM_CSWCR1_WEN_MASK 0x1C0u +#define EIM_CSWCR1_WEN_SHIFT 6 +#define EIM_CSWCR1_WEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEN_SHIFT))&EIM_CSWCR1_WEN_MASK) +#define EIM_CSWCR1_WEA_MASK 0xE00u +#define EIM_CSWCR1_WEA_SHIFT 9 +#define EIM_CSWCR1_WEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WEA_SHIFT))&EIM_CSWCR1_WEA_MASK) +#define EIM_CSWCR1_WBEN_MASK 0x7000u +#define EIM_CSWCR1_WBEN_SHIFT 12 +#define EIM_CSWCR1_WBEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEN_SHIFT))&EIM_CSWCR1_WBEN_MASK) +#define EIM_CSWCR1_WBEA_MASK 0x38000u +#define EIM_CSWCR1_WBEA_SHIFT 15 +#define EIM_CSWCR1_WBEA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WBEA_SHIFT))&EIM_CSWCR1_WBEA_MASK) +#define EIM_CSWCR1_WADVN_MASK 0x1C0000u +#define EIM_CSWCR1_WADVN_SHIFT 18 +#define EIM_CSWCR1_WADVN(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVN_SHIFT))&EIM_CSWCR1_WADVN_MASK) +#define EIM_CSWCR1_WADVA_MASK 0xE00000u +#define EIM_CSWCR1_WADVA_SHIFT 21 +#define EIM_CSWCR1_WADVA(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WADVA_SHIFT))&EIM_CSWCR1_WADVA_MASK) +#define EIM_CSWCR1_WWSC_MASK 0x3F000000u +#define EIM_CSWCR1_WWSC_SHIFT 24 +#define EIM_CSWCR1_WWSC(x) (((uint32_t)(((uint32_t)(x))<<EIM_CSWCR1_WWSC_SHIFT))&EIM_CSWCR1_WWSC_MASK) +#define EIM_CSWCR1_WBED_MASK 0x40000000u +#define EIM_CSWCR1_WBED_SHIFT 30 +#define EIM_CSWCR1_WAL_MASK 0x80000000u +#define EIM_CSWCR1_WAL_SHIFT 31 +/* CSWCR2 Bit Fields */ +#define EIM_CSWCR2_WBCDD_MASK 0x1u +#define EIM_CSWCR2_WBCDD_SHIFT 0 +/* WCR Bit Fields */ +#define EIM_WCR_BCM_MASK 0x1u +#define EIM_WCR_BCM_SHIFT 0 +#define EIM_WCR_GBCD_MASK 0x6u +#define EIM_WCR_GBCD_SHIFT 1 +#define EIM_WCR_GBCD(x) (((uint32_t)(((uint32_t)(x))<<EIM_WCR_GBCD_SHIFT))&EIM_WCR_GBCD_MASK) +#define EIM_WCR_CONT_BCLK_SEL_MASK 0x8u +#define EIM_WCR_CONT_BCLK_SEL_SHIFT 3 +#define EIM_WCR_INTEN_MASK 0x10u +#define EIM_WCR_INTEN_SHIFT 4 +#define EIM_WCR_INTPOL_MASK 0x20u +#define EIM_WCR_INTPOL_SHIFT 5 +#define EIM_WCR_WDOG_EN_MASK 0x100u +#define EIM_WCR_WDOG_EN_SHIFT 8 +#define EIM_WCR_WDOG_LIMIT_MASK 0x600u +#define EIM_WCR_WDOG_LIMIT_SHIFT 9 +#define EIM_WCR_WDOG_LIMIT(x) (((uint32_t)(((uint32_t)(x))<<EIM_WCR_WDOG_LIMIT_SHIFT))&EIM_WCR_WDOG_LIMIT_MASK) +#define EIM_WCR_FRUN_ACLK_EN_MASK 0x800u +#define EIM_WCR_FRUN_ACLK_EN_SHIFT 11 +/* DCR Bit Fields */ +#define EIM_DCR_DLL_CTRL_ENABLE_MASK 0x1u +#define EIM_DCR_DLL_CTRL_ENABLE_SHIFT 0 +#define EIM_DCR_DLL_CTRL_RESET_MASK 0x2u +#define EIM_DCR_DLL_CTRL_RESET_SHIFT 1 +#define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u +#define EIM_DCR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 +#define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_MASK 0x8u +#define EIM_DCR_DLL_CTRL_SLV_OFFSET_DEC_SHIFT 3 +#define EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK 0x70u +#define EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT 4 +#define EIM_DCR_DLL_CTRL_SLV_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OFFSET_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OFFSET_MASK) +#define EIM_DCR_DLL_CTRL_GATE_UPDATE_MASK 0x80u +#define EIM_DCR_DLL_CTRL_GATE_UPDATE_SHIFT 7 +#define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u +#define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_SHIFT 8 +#define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u +#define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9 +#define EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&EIM_DCR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK 0x7F0000u +#define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT 16 +#define EIM_DCR_DLL_CTRL_REF_INITIAL_VAL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_SHIFT))&EIM_DCR_DLL_CTRL_REF_INITIAL_VAL_MASK) +#define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xF800000u +#define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 23 +#define EIM_DCR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u +#define EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 +#define EIM_DCR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<EIM_DCR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&EIM_DCR_DLL_CTRL_REF_UPDATE_INT_MASK) +/* DSR Bit Fields */ +#define EIM_DSR_DLL_STS_SLV_LOCK_MASK 0x1u +#define EIM_DSR_DLL_STS_SLV_LOCK_SHIFT 0 +#define EIM_DSR_DLL_STS_REF_LOCK_MASK 0x2u +#define EIM_DSR_DLL_STS_REF_LOCK_SHIFT 1 +#define EIM_DSR_DLL_STS_SLV_SEL_MASK 0x1FCu +#define EIM_DSR_DLL_STS_SLV_SEL_SHIFT 2 +#define EIM_DSR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_SLV_SEL_SHIFT))&EIM_DSR_DLL_STS_SLV_SEL_MASK) +#define EIM_DSR_DLL_STS_REF_SEL_MASK 0xFE00u +#define EIM_DSR_DLL_STS_REF_SEL_SHIFT 9 +#define EIM_DSR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<EIM_DSR_DLL_STS_REF_SEL_SHIFT))&EIM_DSR_DLL_STS_REF_SEL_MASK) +/* WIAR Bit Fields */ +#define EIM_WIAR_IPS_REQ_MASK 0x1u +#define EIM_WIAR_IPS_REQ_SHIFT 0 +#define EIM_WIAR_IPS_ACK_MASK 0x2u +#define EIM_WIAR_IPS_ACK_SHIFT 1 +#define EIM_WIAR_INT_MASK 0x4u +#define EIM_WIAR_INT_SHIFT 2 +#define EIM_WIAR_ERRST_MASK 0x8u +#define EIM_WIAR_ERRST_SHIFT 3 +#define EIM_WIAR_ACLK_EN_MASK 0x10u +#define EIM_WIAR_ACLK_EN_SHIFT 4 +/* EAR Bit Fields */ +#define EIM_EAR_Error_ADDR_MASK 0xFFFFFFFFu +#define EIM_EAR_Error_ADDR_SHIFT 0 +#define EIM_EAR_Error_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EIM_EAR_Error_ADDR_SHIFT))&EIM_EAR_Error_ADDR_MASK) + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM base address */ +#define EIM_BASE (0x30BC0000u) +/** Peripheral EIM base pointer */ +#define EIM ((EIM_Type *)EIM_BASE) +#define EIM_BASE_PTR (EIM) +/** Array initializer of EIM peripheral base adresses */ +#define EIM_BASE_ADDRS { EIM_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM } + +/* ---------------------------------------------------------------------------- + -- EIM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Accessor_Macros EIM - Register accessor macros + * @{ + */ + + +/* EIM - Register instance definitions */ +/* EIM */ +#define EIM_CS0GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,0) +#define EIM_CS0GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,0) +#define EIM_CS0RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,0) +#define EIM_CS0RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,0) +#define EIM_CS0WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,0) +#define EIM_CS0WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,0) +#define EIM_CS1GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,1) +#define EIM_CS1GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,1) +#define EIM_CS1RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,1) +#define EIM_CS1RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,1) +#define EIM_CS1WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,1) +#define EIM_CS1WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,1) +#define EIM_CS2GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,2) +#define EIM_CS2GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,2) +#define EIM_CS2RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,2) +#define EIM_CS2RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,2) +#define EIM_CS2WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,2) +#define EIM_CS2WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,2) +#define EIM_CS3GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,3) +#define EIM_CS3GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,3) +#define EIM_CS3RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,3) +#define EIM_CS3RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,3) +#define EIM_CS3WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,3) +#define EIM_CS3WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,3) +#define EIM_CS4GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,4) +#define EIM_CS4GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,4) +#define EIM_CS4RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,4) +#define EIM_CS4RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,4) +#define EIM_CS4WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,4) +#define EIM_CS4WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,4) +#define EIM_CS5GCR1 EIM_CSGCR1_REG(EIM_BASE_PTR,5) +#define EIM_CS5GCR2 EIM_CSGCR2_REG(EIM_BASE_PTR,5) +#define EIM_CS5RCR1 EIM_CSRCR1_REG(EIM_BASE_PTR,5) +#define EIM_CS5RCR2 EIM_CSRCR2_REG(EIM_BASE_PTR,5) +#define EIM_CS5WCR1 EIM_CSWCR1_REG(EIM_BASE_PTR,5) +#define EIM_CS5WCR2 EIM_CSWCR2_REG(EIM_BASE_PTR,5) +#define EIM_WCR EIM_WCR_REG(EIM_BASE_PTR) +#define EIM_DCR EIM_DCR_REG(EIM_BASE_PTR) +#define EIM_DSR EIM_DSR_REG(EIM_BASE_PTR) +#define EIM_WIAR EIM_WIAR_REG(EIM_BASE_PTR) +#define EIM_EAR EIM_EAR_REG(EIM_BASE_PTR) + +/* EIM - Register array accessors */ +#define EIM_CSGCR1(index) EIM_CSGCR1_REG(EIM_BASE_PTR,index) +#define EIM_CSGCR2(index) EIM_CSGCR2_REG(EIM_BASE_PTR,index) +#define EIM_CSRCR1(index) EIM_CSRCR1_REG(EIM_BASE_PTR,index) +#define EIM_CSRCR2(index) EIM_CSRCR2_REG(EIM_BASE_PTR,index) +#define EIM_CSWCR1(index) EIM_CSWCR1_REG(EIM_BASE_PTR,index) +#define EIM_CSWCR2(index) EIM_CSWCR2_REG(EIM_BASE_PTR,index) + +/*! + * @} + */ /* end of group EIM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group EIM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- EMVSIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer + * @{ + */ + +/** EMVSIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */ + __IO uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */ + __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */ + __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ + __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ + __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ + __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */ + __I uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ + __I uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */ + __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */ + __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ + __O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ + __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */ + __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */ + __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */ + __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */ + __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */ + __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ +} EMVSIM_Type, *EMVSIM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- EMVSIM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EMVSIM_Register_Accessor_Macros EMVSIM - Register accessor macros + * @{ + */ + + +/* EMVSIM - Register accessors */ +#define EMVSIM_VER_ID_REG(base) ((base)->VER_ID) +#define EMVSIM_PARAM_REG(base) ((base)->PARAM) +#define EMVSIM_CLKCFG_REG(base) ((base)->CLKCFG) +#define EMVSIM_DIVISOR_REG(base) ((base)->DIVISOR) +#define EMVSIM_CTRL_REG(base) ((base)->CTRL) +#define EMVSIM_INT_MASK_REG(base) ((base)->INT_MASK) +#define EMVSIM_RX_THD_REG(base) ((base)->RX_THD) +#define EMVSIM_TX_THD_REG(base) ((base)->TX_THD) +#define EMVSIM_RX_STATUS_REG(base) ((base)->RX_STATUS) +#define EMVSIM_TX_STATUS_REG(base) ((base)->TX_STATUS) +#define EMVSIM_PCSR_REG(base) ((base)->PCSR) +#define EMVSIM_RX_BUF_REG(base) ((base)->RX_BUF) +#define EMVSIM_TX_BUF_REG(base) ((base)->TX_BUF) +#define EMVSIM_TX_GETU_REG(base) ((base)->TX_GETU) +#define EMVSIM_CWT_VAL_REG(base) ((base)->CWT_VAL) +#define EMVSIM_BWT_VAL_REG(base) ((base)->BWT_VAL) +#define EMVSIM_BGT_VAL_REG(base) ((base)->BGT_VAL) +#define EMVSIM_GPCNT0_VAL_REG(base) ((base)->GPCNT0_VAL) +#define EMVSIM_GPCNT1_VAL_REG(base) ((base)->GPCNT1_VAL) + +/*! + * @} + */ /* end of group EMVSIM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- EMVSIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks + * @{ + */ + +/* VER_ID Bit Fields */ +#define EMVSIM_VER_ID_VER_MASK 0xFFFFFFFFu +#define EMVSIM_VER_ID_VER_SHIFT 0 +#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_VER_ID_VER_SHIFT))&EMVSIM_VER_ID_VER_MASK) +/* PARAM Bit Fields */ +#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK 0xFFu +#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT 0 +#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT))&EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) +#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK 0xFF00u +#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT 8 +#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT))&EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) +/* CLKCFG Bit Fields */ +#define EMVSIM_CLKCFG_CLK_PRSC_MASK 0xFFu +#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT 0 +#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_CLK_PRSC_SHIFT))&EMVSIM_CLKCFG_CLK_PRSC_MASK) +#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK 0x300u +#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT 8 +#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT))&EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) +#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK 0xC00u +#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT 10 +#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT))&EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) +/* DIVISOR Bit Fields */ +#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK 0x1FFu +#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT 0 +#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT))&EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) +/* CTRL Bit Fields */ +#define EMVSIM_CTRL_IC_MASK 0x1u +#define EMVSIM_CTRL_IC_SHIFT 0 +#define EMVSIM_CTRL_ICM_MASK 0x2u +#define EMVSIM_CTRL_ICM_SHIFT 1 +#define EMVSIM_CTRL_ANACK_MASK 0x4u +#define EMVSIM_CTRL_ANACK_SHIFT 2 +#define EMVSIM_CTRL_ONACK_MASK 0x8u +#define EMVSIM_CTRL_ONACK_SHIFT 3 +#define EMVSIM_CTRL_FLSH_RX_MASK 0x100u +#define EMVSIM_CTRL_FLSH_RX_SHIFT 8 +#define EMVSIM_CTRL_FLSH_TX_MASK 0x200u +#define EMVSIM_CTRL_FLSH_TX_SHIFT 9 +#define EMVSIM_CTRL_SW_RST_MASK 0x400u +#define EMVSIM_CTRL_SW_RST_SHIFT 10 +#define EMVSIM_CTRL_KILL_CLOCKS_MASK 0x800u +#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT 11 +#define EMVSIM_CTRL_DOZE_EN_MASK 0x1000u +#define EMVSIM_CTRL_DOZE_EN_SHIFT 12 +#define EMVSIM_CTRL_STOP_EN_MASK 0x2000u +#define EMVSIM_CTRL_STOP_EN_SHIFT 13 +#define EMVSIM_CTRL_RCV_EN_MASK 0x10000u +#define EMVSIM_CTRL_RCV_EN_SHIFT 16 +#define EMVSIM_CTRL_XMT_EN_MASK 0x20000u +#define EMVSIM_CTRL_XMT_EN_SHIFT 17 +#define EMVSIM_CTRL_RCVR_11_MASK 0x40000u +#define EMVSIM_CTRL_RCVR_11_SHIFT 18 +#define EMVSIM_CTRL_RX_DMA_EN_MASK 0x80000u +#define EMVSIM_CTRL_RX_DMA_EN_SHIFT 19 +#define EMVSIM_CTRL_TX_DMA_EN_MASK 0x100000u +#define EMVSIM_CTRL_TX_DMA_EN_SHIFT 20 +#define EMVSIM_CTRL_INV_CRC_VAL_MASK 0x1000000u +#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT 24 +#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK 0x2000000u +#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT 25 +#define EMVSIM_CTRL_CRC_IN_FLIP_MASK 0x4000000u +#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT 26 +#define EMVSIM_CTRL_CWT_EN_MASK 0x8000000u +#define EMVSIM_CTRL_CWT_EN_SHIFT 27 +#define EMVSIM_CTRL_LRC_EN_MASK 0x10000000u +#define EMVSIM_CTRL_LRC_EN_SHIFT 28 +#define EMVSIM_CTRL_CRC_EN_MASK 0x20000000u +#define EMVSIM_CTRL_CRC_EN_SHIFT 29 +#define EMVSIM_CTRL_XMT_CRC_LRC_MASK 0x40000000u +#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT 30 +#define EMVSIM_CTRL_BWT_EN_MASK 0x80000000u +#define EMVSIM_CTRL_BWT_EN_SHIFT 31 +/* INT_MASK Bit Fields */ +#define EMVSIM_INT_MASK_RDT_IM_MASK 0x1u +#define EMVSIM_INT_MASK_RDT_IM_SHIFT 0 +#define EMVSIM_INT_MASK_TC_IM_MASK 0x2u +#define EMVSIM_INT_MASK_TC_IM_SHIFT 1 +#define EMVSIM_INT_MASK_RFO_IM_MASK 0x4u +#define EMVSIM_INT_MASK_RFO_IM_SHIFT 2 +#define EMVSIM_INT_MASK_ETC_IM_MASK 0x8u +#define EMVSIM_INT_MASK_ETC_IM_SHIFT 3 +#define EMVSIM_INT_MASK_TFE_IM_MASK 0x10u +#define EMVSIM_INT_MASK_TFE_IM_SHIFT 4 +#define EMVSIM_INT_MASK_TNACK_IM_MASK 0x20u +#define EMVSIM_INT_MASK_TNACK_IM_SHIFT 5 +#define EMVSIM_INT_MASK_TFF_IM_MASK 0x40u +#define EMVSIM_INT_MASK_TFF_IM_SHIFT 6 +#define EMVSIM_INT_MASK_TDT_IM_MASK 0x80u +#define EMVSIM_INT_MASK_TDT_IM_SHIFT 7 +#define EMVSIM_INT_MASK_GPCNT0_IM_MASK 0x100u +#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT 8 +#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK 0x200u +#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT 9 +#define EMVSIM_INT_MASK_RNACK_IM_MASK 0x400u +#define EMVSIM_INT_MASK_RNACK_IM_SHIFT 10 +#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK 0x800u +#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT 11 +#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK 0x1000u +#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT 12 +#define EMVSIM_INT_MASK_GPCNT1_IM_MASK 0x2000u +#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT 13 +#define EMVSIM_INT_MASK_RX_DATA_IM_MASK 0x4000u +#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT 14 +/* RX_THD Bit Fields */ +#define EMVSIM_RX_THD_RDT_MASK 0xFu +#define EMVSIM_RX_THD_RDT_SHIFT 0 +#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_THD_RDT_SHIFT))&EMVSIM_RX_THD_RDT_MASK) +#define EMVSIM_RX_THD_RNCK_THD_MASK 0xF00u +#define EMVSIM_RX_THD_RNCK_THD_SHIFT 8 +#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_THD_RNCK_THD_SHIFT))&EMVSIM_RX_THD_RNCK_THD_MASK) +/* TX_THD Bit Fields */ +#define EMVSIM_TX_THD_TDT_MASK 0xFu +#define EMVSIM_TX_THD_TDT_SHIFT 0 +#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_THD_TDT_SHIFT))&EMVSIM_TX_THD_TDT_MASK) +#define EMVSIM_TX_THD_TNCK_THD_MASK 0xF00u +#define EMVSIM_TX_THD_TNCK_THD_SHIFT 8 +#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_THD_TNCK_THD_SHIFT))&EMVSIM_TX_THD_TNCK_THD_MASK) +/* RX_STATUS Bit Fields */ +#define EMVSIM_RX_STATUS_RFO_MASK 0x1u +#define EMVSIM_RX_STATUS_RFO_SHIFT 0 +#define EMVSIM_RX_STATUS_RX_DATA_MASK 0x10u +#define EMVSIM_RX_STATUS_RX_DATA_SHIFT 4 +#define EMVSIM_RX_STATUS_RDTF_MASK 0x20u +#define EMVSIM_RX_STATUS_RDTF_SHIFT 5 +#define EMVSIM_RX_STATUS_LRC_OK_MASK 0x40u +#define EMVSIM_RX_STATUS_LRC_OK_SHIFT 6 +#define EMVSIM_RX_STATUS_CRC_OK_MASK 0x80u +#define EMVSIM_RX_STATUS_CRC_OK_SHIFT 7 +#define EMVSIM_RX_STATUS_CWT_ERR_MASK 0x100u +#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT 8 +#define EMVSIM_RX_STATUS_RTE_MASK 0x200u +#define EMVSIM_RX_STATUS_RTE_SHIFT 9 +#define EMVSIM_RX_STATUS_BWT_ERR_MASK 0x400u +#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT 10 +#define EMVSIM_RX_STATUS_BGT_ERR_MASK 0x800u +#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT 11 +#define EMVSIM_RX_STATUS_PEF_MASK 0x1000u +#define EMVSIM_RX_STATUS_PEF_SHIFT 12 +#define EMVSIM_RX_STATUS_FEF_MASK 0x2000u +#define EMVSIM_RX_STATUS_FEF_SHIFT 13 +#define EMVSIM_RX_STATUS_RX_WPTR_MASK 0xF0000u +#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT 16 +#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RX_WPTR_SHIFT))&EMVSIM_RX_STATUS_RX_WPTR_MASK) +#define EMVSIM_RX_STATUS_RX_CNT_MASK 0x1F000000u +#define EMVSIM_RX_STATUS_RX_CNT_SHIFT 24 +#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_STATUS_RX_CNT_SHIFT))&EMVSIM_RX_STATUS_RX_CNT_MASK) +/* TX_STATUS Bit Fields */ +#define EMVSIM_TX_STATUS_TNTE_MASK 0x1u +#define EMVSIM_TX_STATUS_TNTE_SHIFT 0 +#define EMVSIM_TX_STATUS_TFE_MASK 0x8u +#define EMVSIM_TX_STATUS_TFE_SHIFT 3 +#define EMVSIM_TX_STATUS_ETCF_MASK 0x10u +#define EMVSIM_TX_STATUS_ETCF_SHIFT 4 +#define EMVSIM_TX_STATUS_TCF_MASK 0x20u +#define EMVSIM_TX_STATUS_TCF_SHIFT 5 +#define EMVSIM_TX_STATUS_TFF_MASK 0x40u +#define EMVSIM_TX_STATUS_TFF_SHIFT 6 +#define EMVSIM_TX_STATUS_TDTF_MASK 0x80u +#define EMVSIM_TX_STATUS_TDTF_SHIFT 7 +#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK 0x100u +#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT 8 +#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK 0x200u +#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT 9 +#define EMVSIM_TX_STATUS_TX_RPTR_MASK 0xF0000u +#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT 16 +#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TX_RPTR_SHIFT))&EMVSIM_TX_STATUS_TX_RPTR_MASK) +#define EMVSIM_TX_STATUS_TX_CNT_MASK 0x1F000000u +#define EMVSIM_TX_STATUS_TX_CNT_SHIFT 24 +#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_STATUS_TX_CNT_SHIFT))&EMVSIM_TX_STATUS_TX_CNT_MASK) +/* PCSR Bit Fields */ +#define EMVSIM_PCSR_SAPD_MASK 0x1u +#define EMVSIM_PCSR_SAPD_SHIFT 0 +#define EMVSIM_PCSR_SVCC_EN_MASK 0x2u +#define EMVSIM_PCSR_SVCC_EN_SHIFT 1 +#define EMVSIM_PCSR_VCCENP_MASK 0x4u +#define EMVSIM_PCSR_VCCENP_SHIFT 2 +#define EMVSIM_PCSR_SRST_MASK 0x8u +#define EMVSIM_PCSR_SRST_SHIFT 3 +#define EMVSIM_PCSR_SCEN_MASK 0x10u +#define EMVSIM_PCSR_SCEN_SHIFT 4 +#define EMVSIM_PCSR_SCSP_MASK 0x20u +#define EMVSIM_PCSR_SCSP_SHIFT 5 +#define EMVSIM_PCSR_SPD_MASK 0x80u +#define EMVSIM_PCSR_SPD_SHIFT 7 +#define EMVSIM_PCSR_SPDIM_MASK 0x1000000u +#define EMVSIM_PCSR_SPDIM_SHIFT 24 +#define EMVSIM_PCSR_SPDIF_MASK 0x2000000u +#define EMVSIM_PCSR_SPDIF_SHIFT 25 +#define EMVSIM_PCSR_SPDP_MASK 0x4000000u +#define EMVSIM_PCSR_SPDP_SHIFT 26 +#define EMVSIM_PCSR_SPDES_MASK 0x8000000u +#define EMVSIM_PCSR_SPDES_SHIFT 27 +/* RX_BUF Bit Fields */ +#define EMVSIM_RX_BUF_RX_BYTE_MASK 0xFFu +#define EMVSIM_RX_BUF_RX_BYTE_SHIFT 0 +#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_RX_BUF_RX_BYTE_SHIFT))&EMVSIM_RX_BUF_RX_BYTE_MASK) +/* TX_BUF Bit Fields */ +#define EMVSIM_TX_BUF_TX_BYTE_MASK 0xFFu +#define EMVSIM_TX_BUF_TX_BYTE_SHIFT 0 +#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_BUF_TX_BYTE_SHIFT))&EMVSIM_TX_BUF_TX_BYTE_MASK) +/* TX_GETU Bit Fields */ +#define EMVSIM_TX_GETU_GETU_MASK 0xFFu +#define EMVSIM_TX_GETU_GETU_SHIFT 0 +#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_TX_GETU_GETU_SHIFT))&EMVSIM_TX_GETU_GETU_MASK) +/* CWT_VAL Bit Fields */ +#define EMVSIM_CWT_VAL_CWT_MASK 0xFFFFu +#define EMVSIM_CWT_VAL_CWT_SHIFT 0 +#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_CWT_VAL_CWT_SHIFT))&EMVSIM_CWT_VAL_CWT_MASK) +/* BWT_VAL Bit Fields */ +#define EMVSIM_BWT_VAL_BWT_MASK 0xFFFFFFFFu +#define EMVSIM_BWT_VAL_BWT_SHIFT 0 +#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_BWT_VAL_BWT_SHIFT))&EMVSIM_BWT_VAL_BWT_MASK) +/* BGT_VAL Bit Fields */ +#define EMVSIM_BGT_VAL_BGT_MASK 0xFFFFu +#define EMVSIM_BGT_VAL_BGT_SHIFT 0 +#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_BGT_VAL_BGT_SHIFT))&EMVSIM_BGT_VAL_BGT_MASK) +/* GPCNT0_VAL Bit Fields */ +#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK 0xFFFFu +#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT 0 +#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT))&EMVSIM_GPCNT0_VAL_GPCNT0_MASK) +/* GPCNT1_VAL Bit Fields */ +#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK 0xFFFFu +#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT 0 +#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x))<<EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT))&EMVSIM_GPCNT1_VAL_GPCNT1_MASK) + +/*! + * @} + */ /* end of group EMVSIM_Register_Masks */ + + +/* EMVSIM - Peripheral instance base addresses */ +/** Peripheral EMVSIM1 base address */ +#define EMVSIM1_BASE (0x30B90000u) +/** Peripheral EMVSIM1 base pointer */ +#define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) +#define EMVSIM1_BASE_PTR (EMVSIM1) +/** Peripheral EMVSIM2 base address */ +#define EMVSIM2_BASE (0x30BA0000u) +/** Peripheral EMVSIM2 base pointer */ +#define EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE) +#define EMVSIM2_BASE_PTR (EMVSIM2) +/** Array initializer of EMVSIM peripheral base adresses */ +#define EMVSIM_BASE_ADDRS { EMVSIM1_BASE, EMVSIM2_BASE } +/** Array initializer of EMVSIM peripheral base pointers */ +#define EMVSIM_BASE_PTRS { EMVSIM1, EMVSIM2 } + +/* ---------------------------------------------------------------------------- + -- EMVSIM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EMVSIM_Register_Accessor_Macros EMVSIM - Register accessor macros + * @{ + */ + + +/* EMVSIM - Register instance definitions */ +/* EMVSIM1 */ +#define EMVSIM1_VER_ID EMVSIM_VER_ID_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_PARAM EMVSIM_PARAM_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_CLKCFG EMVSIM_CLKCFG_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_DIVISOR EMVSIM_DIVISOR_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_CTRL EMVSIM_CTRL_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_INT_MASK EMVSIM_INT_MASK_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_RX_THD EMVSIM_RX_THD_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_TX_THD EMVSIM_TX_THD_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_RX_STATUS EMVSIM_RX_STATUS_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_TX_STATUS EMVSIM_TX_STATUS_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_PCSR EMVSIM_PCSR_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_RX_BUF EMVSIM_RX_BUF_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_TX_BUF EMVSIM_TX_BUF_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_TX_GETU EMVSIM_TX_GETU_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_CWT_VAL EMVSIM_CWT_VAL_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_BWT_VAL EMVSIM_BWT_VAL_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_BGT_VAL EMVSIM_BGT_VAL_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_GPCNT0_VAL EMVSIM_GPCNT0_VAL_REG(EMVSIM1_BASE_PTR) +#define EMVSIM1_GPCNT1_VAL EMVSIM_GPCNT1_VAL_REG(EMVSIM1_BASE_PTR) +/* EMVSIM2 */ +#define EMVSIM2_VER_ID EMVSIM_VER_ID_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_PARAM EMVSIM_PARAM_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_CLKCFG EMVSIM_CLKCFG_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_DIVISOR EMVSIM_DIVISOR_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_CTRL EMVSIM_CTRL_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_INT_MASK EMVSIM_INT_MASK_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_RX_THD EMVSIM_RX_THD_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_TX_THD EMVSIM_TX_THD_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_RX_STATUS EMVSIM_RX_STATUS_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_TX_STATUS EMVSIM_TX_STATUS_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_PCSR EMVSIM_PCSR_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_RX_BUF EMVSIM_RX_BUF_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_TX_BUF EMVSIM_TX_BUF_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_TX_GETU EMVSIM_TX_GETU_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_CWT_VAL EMVSIM_CWT_VAL_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_BWT_VAL EMVSIM_BWT_VAL_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_BGT_VAL EMVSIM_BGT_VAL_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_GPCNT0_VAL EMVSIM_GPCNT0_VAL_REG(EMVSIM2_BASE_PTR) +#define EMVSIM2_GPCNT1_VAL EMVSIM_GPCNT1_VAL_REG(EMVSIM2_BASE_PTR) + +/*! + * @} + */ /* end of group EMVSIM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group EMVSIM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */ + uint8_t RESERVED_8[4]; + __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_9[12]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[24]; + __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */ + __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */ + __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */ + __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */ + __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */ + __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */ + uint8_t RESERVED_12[8]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */ + uint8_t RESERVED_13[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */ + uint8_t RESERVED_15[8]; + __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */ + __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */ + __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */ + __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ + __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ + __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ + uint8_t RESERVED_16[12]; + __I uint32_t RMON_T_DROP; /**< Incorrectly Counted Frames Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + __I uint32_t IEEE_T_DROP; /**< IEEE_T_DROP Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< , offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_17[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + __I uint32_t RMON_R_RESVD_0; /**< RMON Reserved Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_18[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_19[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type, *ENET_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ENET - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros + * @{ + */ + + +/* ENET - Register accessors */ +#define ENET_EIR_REG(base) ((base)->EIR) +#define ENET_EIMR_REG(base) ((base)->EIMR) +#define ENET_RDAR_REG(base) ((base)->RDAR) +#define ENET_TDAR_REG(base) ((base)->TDAR) +#define ENET_ECR_REG(base) ((base)->ECR) +#define ENET_MMFR_REG(base) ((base)->MMFR) +#define ENET_MSCR_REG(base) ((base)->MSCR) +#define ENET_MIBC_REG(base) ((base)->MIBC) +#define ENET_RCR_REG(base) ((base)->RCR) +#define ENET_TCR_REG(base) ((base)->TCR) +#define ENET_PALR_REG(base) ((base)->PALR) +#define ENET_PAUR_REG(base) ((base)->PAUR) +#define ENET_OPD_REG(base) ((base)->OPD) +#define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) +#define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) +#define ENET_IAUR_REG(base) ((base)->IAUR) +#define ENET_IALR_REG(base) ((base)->IALR) +#define ENET_GAUR_REG(base) ((base)->GAUR) +#define ENET_GALR_REG(base) ((base)->GALR) +#define ENET_TFWR_REG(base) ((base)->TFWR) +#define ENET_RDSR1_REG(base) ((base)->RDSR1) +#define ENET_TDSR1_REG(base) ((base)->TDSR1) +#define ENET_MRBR1_REG(base) ((base)->MRBR1) +#define ENET_RDSR2_REG(base) ((base)->RDSR2) +#define ENET_TDSR2_REG(base) ((base)->TDSR2) +#define ENET_MRBR2_REG(base) ((base)->MRBR2) +#define ENET_RDSR_REG(base) ((base)->RDSR) +#define ENET_TDSR_REG(base) ((base)->TDSR) +#define ENET_MRBR_REG(base) ((base)->MRBR) +#define ENET_RSFL_REG(base) ((base)->RSFL) +#define ENET_RSEM_REG(base) ((base)->RSEM) +#define ENET_RAEM_REG(base) ((base)->RAEM) +#define ENET_RAFL_REG(base) ((base)->RAFL) +#define ENET_TSEM_REG(base) ((base)->TSEM) +#define ENET_TAEM_REG(base) ((base)->TAEM) +#define ENET_TAFL_REG(base) ((base)->TAFL) +#define ENET_TIPG_REG(base) ((base)->TIPG) +#define ENET_FTRL_REG(base) ((base)->FTRL) +#define ENET_TACC_REG(base) ((base)->TACC) +#define ENET_RACC_REG(base) ((base)->RACC) +#define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) +#define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) +#define ENET_RDAR1_REG(base) ((base)->RDAR1) +#define ENET_TDAR1_REG(base) ((base)->TDAR1) +#define ENET_RDAR2_REG(base) ((base)->RDAR2) +#define ENET_TDAR2_REG(base) ((base)->TDAR2) +#define ENET_QOS_REG(base) ((base)->QOS) +#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) +#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) +#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) +#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) +#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) +#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) +#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) +#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) +#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) +#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) +#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) +#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) +#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) +#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) +#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) +#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) +#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) +#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) +#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) +#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) +#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) +#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) +#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) +#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) +#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) +#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) +#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) +#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) +#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) +#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) +#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) +#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) +#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) +#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) +#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) +#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) +#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) +#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) +#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) +#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) +#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) +#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) +#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) +#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) +#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) +#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) +#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) +#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) +#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) +#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) +#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) +#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) +#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) +#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) +#define ENET_ATCR_REG(base) ((base)->ATCR) +#define ENET_ATVR_REG(base) ((base)->ATVR) +#define ENET_ATOFF_REG(base) ((base)->ATOFF) +#define ENET_ATPER_REG(base) ((base)->ATPER) +#define ENET_ATCOR_REG(base) ((base)->ATCOR) +#define ENET_ATINC_REG(base) ((base)->ATINC) +#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) +#define ENET_TGSR_REG(base) ((base)->TGSR) +#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) +#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) + +/*! + * @} + */ /* end of group ENET_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/* EIR Bit Fields */ +#define ENET_EIR_RXB1_MASK 0x1u +#define ENET_EIR_RXB1_SHIFT 0 +#define ENET_EIR_RXF1_MASK 0x2u +#define ENET_EIR_RXF1_SHIFT 1 +#define ENET_EIR_TXB1_MASK 0x4u +#define ENET_EIR_TXB1_SHIFT 2 +#define ENET_EIR_TXF1_MASK 0x8u +#define ENET_EIR_TXF1_SHIFT 3 +#define ENET_EIR_RXB2_MASK 0x10u +#define ENET_EIR_RXB2_SHIFT 4 +#define ENET_EIR_RXF2_MASK 0x20u +#define ENET_EIR_RXF2_SHIFT 5 +#define ENET_EIR_TXB2_MASK 0x40u +#define ENET_EIR_TXB2_SHIFT 6 +#define ENET_EIR_TXF2_MASK 0x80u +#define ENET_EIR_TXF2_SHIFT 7 +#define ENET_EIR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIR_RXFLUSH_0_SHIFT 12 +#define ENET_EIR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIR_RXFLUSH_1_SHIFT 13 +#define ENET_EIR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIR_RXFLUSH_2_SHIFT 14 +#define ENET_EIR_TS_TIMER_MASK 0x8000u +#define ENET_EIR_TS_TIMER_SHIFT 15 +#define ENET_EIR_TS_AVAIL_MASK 0x10000u +#define ENET_EIR_TS_AVAIL_SHIFT 16 +#define ENET_EIR_WAKEUP_MASK 0x20000u +#define ENET_EIR_WAKEUP_SHIFT 17 +#define ENET_EIR_PLR_MASK 0x40000u +#define ENET_EIR_PLR_SHIFT 18 +#define ENET_EIR_UN_MASK 0x80000u +#define ENET_EIR_UN_SHIFT 19 +#define ENET_EIR_RL_MASK 0x100000u +#define ENET_EIR_RL_SHIFT 20 +#define ENET_EIR_LC_MASK 0x200000u +#define ENET_EIR_LC_SHIFT 21 +#define ENET_EIR_EBERR_MASK 0x400000u +#define ENET_EIR_EBERR_SHIFT 22 +#define ENET_EIR_MII_MASK 0x800000u +#define ENET_EIR_MII_SHIFT 23 +#define ENET_EIR_RXB_MASK 0x1000000u +#define ENET_EIR_RXB_SHIFT 24 +#define ENET_EIR_RXF_MASK 0x2000000u +#define ENET_EIR_RXF_SHIFT 25 +#define ENET_EIR_TXB_MASK 0x4000000u +#define ENET_EIR_TXB_SHIFT 26 +#define ENET_EIR_TXF_MASK 0x8000000u +#define ENET_EIR_TXF_SHIFT 27 +#define ENET_EIR_GRA_MASK 0x10000000u +#define ENET_EIR_GRA_SHIFT 28 +#define ENET_EIR_BABT_MASK 0x20000000u +#define ENET_EIR_BABT_SHIFT 29 +#define ENET_EIR_BABR_MASK 0x40000000u +#define ENET_EIR_BABR_SHIFT 30 +/* EIMR Bit Fields */ +#define ENET_EIMR_RXB1_MASK 0x1u +#define ENET_EIMR_RXB1_SHIFT 0 +#define ENET_EIMR_RXF1_MASK 0x2u +#define ENET_EIMR_RXF1_SHIFT 1 +#define ENET_EIMR_TXB1_MASK 0x4u +#define ENET_EIMR_TXB1_SHIFT 2 +#define ENET_EIMR_TXF1_MASK 0x8u +#define ENET_EIMR_TXF1_SHIFT 3 +#define ENET_EIMR_RXB2_MASK 0x10u +#define ENET_EIMR_RXB2_SHIFT 4 +#define ENET_EIMR_RXF2_MASK 0x20u +#define ENET_EIMR_RXF2_SHIFT 5 +#define ENET_EIMR_TXB2_MASK 0x40u +#define ENET_EIMR_TXB2_SHIFT 6 +#define ENET_EIMR_TXF2_MASK 0x80u +#define ENET_EIMR_TXF2_SHIFT 7 +#define ENET_EIMR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIMR_RXFLUSH_0_SHIFT 12 +#define ENET_EIMR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIMR_RXFLUSH_1_SHIFT 13 +#define ENET_EIMR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIMR_RXFLUSH_2_SHIFT 14 +#define ENET_EIMR_TS_TIMER_MASK 0x8000u +#define ENET_EIMR_TS_TIMER_SHIFT 15 +#define ENET_EIMR_TS_AVAIL_MASK 0x10000u +#define ENET_EIMR_TS_AVAIL_SHIFT 16 +#define ENET_EIMR_WAKEUP_MASK 0x20000u +#define ENET_EIMR_WAKEUP_SHIFT 17 +#define ENET_EIMR_PLR_MASK 0x40000u +#define ENET_EIMR_PLR_SHIFT 18 +#define ENET_EIMR_UN_MASK 0x80000u +#define ENET_EIMR_UN_SHIFT 19 +#define ENET_EIMR_RL_MASK 0x100000u +#define ENET_EIMR_RL_SHIFT 20 +#define ENET_EIMR_LC_MASK 0x200000u +#define ENET_EIMR_LC_SHIFT 21 +#define ENET_EIMR_EBERR_MASK 0x400000u +#define ENET_EIMR_EBERR_SHIFT 22 +#define ENET_EIMR_MII_MASK 0x800000u +#define ENET_EIMR_MII_SHIFT 23 +#define ENET_EIMR_RXB_MASK 0x1000000u +#define ENET_EIMR_RXB_SHIFT 24 +#define ENET_EIMR_RXF_MASK 0x2000000u +#define ENET_EIMR_RXF_SHIFT 25 +#define ENET_EIMR_TXB_MASK 0x4000000u +#define ENET_EIMR_TXB_SHIFT 26 +#define ENET_EIMR_TXF_MASK 0x8000000u +#define ENET_EIMR_TXF_SHIFT 27 +#define ENET_EIMR_GRA_MASK 0x10000000u +#define ENET_EIMR_GRA_SHIFT 28 +#define ENET_EIMR_BABT_MASK 0x20000000u +#define ENET_EIMR_BABT_SHIFT 29 +#define ENET_EIMR_BABR_MASK 0x40000000u +#define ENET_EIMR_BABR_SHIFT 30 +/* RDAR Bit Fields */ +#define ENET_RDAR_RDAR_MASK 0x1000000u +#define ENET_RDAR_RDAR_SHIFT 24 +/* TDAR Bit Fields */ +#define ENET_TDAR_TDAR_MASK 0x1000000u +#define ENET_TDAR_TDAR_SHIFT 24 +/* ECR Bit Fields */ +#define ENET_ECR_RESET_MASK 0x1u +#define ENET_ECR_RESET_SHIFT 0 +#define ENET_ECR_ETHEREN_MASK 0x2u +#define ENET_ECR_ETHEREN_SHIFT 1 +#define ENET_ECR_MAGICEN_MASK 0x4u +#define ENET_ECR_MAGICEN_SHIFT 2 +#define ENET_ECR_SLEEP_MASK 0x8u +#define ENET_ECR_SLEEP_SHIFT 3 +#define ENET_ECR_EN1588_MASK 0x10u +#define ENET_ECR_EN1588_SHIFT 4 +#define ENET_ECR_SPEED_MASK 0x20u +#define ENET_ECR_SPEED_SHIFT 5 +#define ENET_ECR_DBGEN_MASK 0x40u +#define ENET_ECR_DBGEN_SHIFT 6 +#define ENET_ECR_DBSWP_MASK 0x100u +#define ENET_ECR_DBSWP_SHIFT 8 +#define ENET_ECR_SVLANEN_MASK 0x200u +#define ENET_ECR_SVLANEN_SHIFT 9 +#define ENET_ECR_VLANUSE2ND_MASK 0x400u +#define ENET_ECR_VLANUSE2ND_SHIFT 10 +#define ENET_ECR_SVLANDBL_MASK 0x800u +#define ENET_ECR_SVLANDBL_SHIFT 11 +/* MMFR Bit Fields */ +#define ENET_MMFR_DATA_MASK 0xFFFFu +#define ENET_MMFR_DATA_SHIFT 0 +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK 0x30000u +#define ENET_MMFR_TA_SHIFT 16 +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK 0x7C0000u +#define ENET_MMFR_RA_SHIFT 18 +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK 0xF800000u +#define ENET_MMFR_PA_SHIFT 23 +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK 0x30000000u +#define ENET_MMFR_OP_SHIFT 28 +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK 0xC0000000u +#define ENET_MMFR_ST_SHIFT 30 +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK) +/* MSCR Bit Fields */ +#define ENET_MSCR_MII_SPEED_MASK 0x7Eu +#define ENET_MSCR_MII_SPEED_SHIFT 1 +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK 0x80u +#define ENET_MSCR_DIS_PRE_SHIFT 7 +#define ENET_MSCR_HOLDTIME_MASK 0x700u +#define ENET_MSCR_HOLDTIME_SHIFT 8 +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK) +/* MIBC Bit Fields */ +#define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u +#define ENET_MIBC_MIB_CLEAR_SHIFT 29 +#define ENET_MIBC_MIB_IDLE_MASK 0x40000000u +#define ENET_MIBC_MIB_IDLE_SHIFT 30 +#define ENET_MIBC_MIB_DIS_MASK 0x80000000u +#define ENET_MIBC_MIB_DIS_SHIFT 31 +/* RCR Bit Fields */ +#define ENET_RCR_LOOP_MASK 0x1u +#define ENET_RCR_LOOP_SHIFT 0 +#define ENET_RCR_DRT_MASK 0x2u +#define ENET_RCR_DRT_SHIFT 1 +#define ENET_RCR_MII_MODE_MASK 0x4u +#define ENET_RCR_MII_MODE_SHIFT 2 +#define ENET_RCR_PROM_MASK 0x8u +#define ENET_RCR_PROM_SHIFT 3 +#define ENET_RCR_BC_REJ_MASK 0x10u +#define ENET_RCR_BC_REJ_SHIFT 4 +#define ENET_RCR_FCE_MASK 0x20u +#define ENET_RCR_FCE_SHIFT 5 +#define ENET_RCR_RGMII_EN_MASK 0x40u +#define ENET_RCR_RGMII_EN_SHIFT 6 +#define ENET_RCR_RMII_MODE_MASK 0x100u +#define ENET_RCR_RMII_MODE_SHIFT 8 +#define ENET_RCR_RMII_10T_MASK 0x200u +#define ENET_RCR_RMII_10T_SHIFT 9 +#define ENET_RCR_PADEN_MASK 0x1000u +#define ENET_RCR_PADEN_SHIFT 12 +#define ENET_RCR_PAUFWD_MASK 0x2000u +#define ENET_RCR_PAUFWD_SHIFT 13 +#define ENET_RCR_CRCFWD_MASK 0x4000u +#define ENET_RCR_CRCFWD_SHIFT 14 +#define ENET_RCR_CFEN_MASK 0x8000u +#define ENET_RCR_CFEN_SHIFT 15 +#define ENET_RCR_MAX_FL_MASK 0x3FFF0000u +#define ENET_RCR_MAX_FL_SHIFT 16 +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK 0x40000000u +#define ENET_RCR_NLC_SHIFT 30 +#define ENET_RCR_GRS_MASK 0x80000000u +#define ENET_RCR_GRS_SHIFT 31 +/* TCR Bit Fields */ +#define ENET_TCR_GTS_MASK 0x1u +#define ENET_TCR_GTS_SHIFT 0 +#define ENET_TCR_FDEN_MASK 0x4u +#define ENET_TCR_FDEN_SHIFT 2 +#define ENET_TCR_TFC_PAUSE_MASK 0x8u +#define ENET_TCR_TFC_PAUSE_SHIFT 3 +#define ENET_TCR_RFC_PAUSE_MASK 0x10u +#define ENET_TCR_RFC_PAUSE_SHIFT 4 +#define ENET_TCR_ADDSEL_MASK 0xE0u +#define ENET_TCR_ADDSEL_SHIFT 5 +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK 0x100u +#define ENET_TCR_ADDINS_SHIFT 8 +#define ENET_TCR_CRCFWD_MASK 0x200u +#define ENET_TCR_CRCFWD_SHIFT 9 +/* PALR Bit Fields */ +#define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu +#define ENET_PALR_PADDR1_SHIFT 0 +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK) +/* PAUR Bit Fields */ +#define ENET_PAUR_TYPE_MASK 0xFFFFu +#define ENET_PAUR_TYPE_SHIFT 0 +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK 0xFFFF0000u +#define ENET_PAUR_PADDR2_SHIFT 16 +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK) +/* OPD Bit Fields */ +#define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu +#define ENET_OPD_PAUSE_DUR_SHIFT 0 +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK 0xFFFF0000u +#define ENET_OPD_OPCODE_SHIFT 16 +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK) +/* TXIC Bit Fields */ +#define ENET_TXIC_ICTT_MASK 0xFFFFu +#define ENET_TXIC_ICTT_SHIFT 0 +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICTT_SHIFT))&ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK 0xFF00000u +#define ENET_TXIC_ICFT_SHIFT 20 +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x))<<ENET_TXIC_ICFT_SHIFT))&ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK 0x40000000u +#define ENET_TXIC_ICCS_SHIFT 30 +#define ENET_TXIC_ICEN_MASK 0x80000000u +#define ENET_TXIC_ICEN_SHIFT 31 +/* RXIC Bit Fields */ +#define ENET_RXIC_ICTT_MASK 0xFFFFu +#define ENET_RXIC_ICTT_SHIFT 0 +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICTT_SHIFT))&ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK 0xFF00000u +#define ENET_RXIC_ICFT_SHIFT 20 +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RXIC_ICFT_SHIFT))&ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK 0x40000000u +#define ENET_RXIC_ICCS_SHIFT 30 +#define ENET_RXIC_ICEN_MASK 0x80000000u +#define ENET_RXIC_ICEN_SHIFT 31 +/* IAUR Bit Fields */ +#define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu +#define ENET_IAUR_IADDR1_SHIFT 0 +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK) +/* IALR Bit Fields */ +#define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu +#define ENET_IALR_IADDR2_SHIFT 0 +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK) +/* GAUR Bit Fields */ +#define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu +#define ENET_GAUR_GADDR1_SHIFT 0 +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK) +/* GALR Bit Fields */ +#define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu +#define ENET_GALR_GADDR2_SHIFT 0 +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK) +/* TFWR Bit Fields */ +#define ENET_TFWR_TFWR_MASK 0x3Fu +#define ENET_TFWR_TFWR_SHIFT 0 +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK 0x100u +#define ENET_TFWR_STRFWD_SHIFT 8 +/* RDSR1 Bit Fields */ +#define ENET_RDSR1_R_DES_START_MASK 0xFFFFFFF8u +#define ENET_RDSR1_R_DES_START_SHIFT 3 +#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR1_R_DES_START_SHIFT))&ENET_RDSR1_R_DES_START_MASK) +/* TDSR1 Bit Fields */ +#define ENET_TDSR1_X_DES_START_MASK 0xFFFFFFF8u +#define ENET_TDSR1_X_DES_START_SHIFT 3 +#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR1_X_DES_START_SHIFT))&ENET_TDSR1_X_DES_START_MASK) +/* MRBR1 Bit Fields */ +#define ENET_MRBR1_R_BUF_SIZE_MASK 0x3FF0u +#define ENET_MRBR1_R_BUF_SIZE_SHIFT 4 +#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR1_R_BUF_SIZE_SHIFT))&ENET_MRBR1_R_BUF_SIZE_MASK) +/* RDSR2 Bit Fields */ +#define ENET_RDSR2_R_DES_START_MASK 0xFFFFFFF8u +#define ENET_RDSR2_R_DES_START_SHIFT 3 +#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR2_R_DES_START_SHIFT))&ENET_RDSR2_R_DES_START_MASK) +/* TDSR2 Bit Fields */ +#define ENET_TDSR2_X_DES_START_MASK 0xFFFFFFF8u +#define ENET_TDSR2_X_DES_START_SHIFT 3 +#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR2_X_DES_START_SHIFT))&ENET_TDSR2_X_DES_START_MASK) +/* MRBR2 Bit Fields */ +#define ENET_MRBR2_R_BUF_SIZE_MASK 0x3FF0u +#define ENET_MRBR2_R_BUF_SIZE_SHIFT 4 +#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR2_R_BUF_SIZE_SHIFT))&ENET_MRBR2_R_BUF_SIZE_MASK) +/* RDSR Bit Fields */ +#define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u +#define ENET_RDSR_R_DES_START_SHIFT 3 +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK) +/* TDSR Bit Fields */ +#define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u +#define ENET_TDSR_X_DES_START_SHIFT 3 +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK) +/* MRBR Bit Fields */ +#define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u +#define ENET_MRBR_R_BUF_SIZE_SHIFT 4 +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK) +/* RSFL Bit Fields */ +#define ENET_RSFL_RX_SECTION_FULL_MASK 0x3FFu +#define ENET_RSFL_RX_SECTION_FULL_SHIFT 0 +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK) +/* RSEM Bit Fields */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK 0x3FFu +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0 +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16 +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/* RAEM Bit Fields */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0x3FFu +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0 +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/* RAFL Bit Fields */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK 0x3FFu +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0 +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK) +/* TSEM Bit Fields */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK 0x3FFu +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0 +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK) +/* TAEM Bit Fields */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0x3FFu +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0 +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/* TAFL Bit Fields */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK 0x3FFu +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0 +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK) +/* TIPG Bit Fields */ +#define ENET_TIPG_IPG_MASK 0x1Fu +#define ENET_TIPG_IPG_SHIFT 0 +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK) +/* FTRL Bit Fields */ +#define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu +#define ENET_FTRL_TRUNC_FL_SHIFT 0 +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK) +/* TACC Bit Fields */ +#define ENET_TACC_SHIFT16_MASK 0x1u +#define ENET_TACC_SHIFT16_SHIFT 0 +#define ENET_TACC_IPCHK_MASK 0x8u +#define ENET_TACC_IPCHK_SHIFT 3 +#define ENET_TACC_PROCHK_MASK 0x10u +#define ENET_TACC_PROCHK_SHIFT 4 +/* RACC Bit Fields */ +#define ENET_RACC_PADREM_MASK 0x1u +#define ENET_RACC_PADREM_SHIFT 0 +#define ENET_RACC_IPDIS_MASK 0x2u +#define ENET_RACC_IPDIS_SHIFT 1 +#define ENET_RACC_PRODIS_MASK 0x4u +#define ENET_RACC_PRODIS_SHIFT 2 +#define ENET_RACC_LINEDIS_MASK 0x40u +#define ENET_RACC_LINEDIS_SHIFT 6 +#define ENET_RACC_SHIFT16_MASK 0x80u +#define ENET_RACC_SHIFT16_SHIFT 7 +/* RCMR Bit Fields */ +#define ENET_RCMR_CMP0_MASK 0x7u +#define ENET_RCMR_CMP0_SHIFT 0 +#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP0_SHIFT))&ENET_RCMR_CMP0_MASK) +#define ENET_RCMR_CMP1_MASK 0x70u +#define ENET_RCMR_CMP1_SHIFT 4 +#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP1_SHIFT))&ENET_RCMR_CMP1_MASK) +#define ENET_RCMR_CMP2_MASK 0x700u +#define ENET_RCMR_CMP2_SHIFT 8 +#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP2_SHIFT))&ENET_RCMR_CMP2_MASK) +#define ENET_RCMR_CMP3_MASK 0x7000u +#define ENET_RCMR_CMP3_SHIFT 12 +#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCMR_CMP3_SHIFT))&ENET_RCMR_CMP3_MASK) +#define ENET_RCMR_MATCHEN_MASK 0x10000u +#define ENET_RCMR_MATCHEN_SHIFT 16 +/* DMACFG Bit Fields */ +#define ENET_DMACFG_IDLE_SLOPE_MASK 0xFFFFu +#define ENET_DMACFG_IDLE_SLOPE_SHIFT 0 +#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_DMACFG_IDLE_SLOPE_SHIFT))&ENET_DMACFG_IDLE_SLOPE_MASK) +#define ENET_DMACFG_DMA_CLASS_EN_MASK 0x10000u +#define ENET_DMACFG_DMA_CLASS_EN_SHIFT 16 +#define ENET_DMACFG_CALC_NOIPG_MASK 0x20000u +#define ENET_DMACFG_CALC_NOIPG_SHIFT 17 +/* RDAR1 Bit Fields */ +#define ENET_RDAR1_RDAR_MASK 0x1000000u +#define ENET_RDAR1_RDAR_SHIFT 24 +/* TDAR1 Bit Fields */ +#define ENET_TDAR1_TDAR_MASK 0x1000000u +#define ENET_TDAR1_TDAR_SHIFT 24 +/* RDAR2 Bit Fields */ +#define ENET_RDAR2_RDAR_MASK 0x1000000u +#define ENET_RDAR2_RDAR_SHIFT 24 +/* TDAR2 Bit Fields */ +#define ENET_TDAR2_TDAR_MASK 0x1000000u +#define ENET_TDAR2_TDAR_SHIFT 24 +/* QOS Bit Fields */ +#define ENET_QOS_TX_SCHEME_MASK 0x7u +#define ENET_QOS_TX_SCHEME_SHIFT 0 +#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x))<<ENET_QOS_TX_SCHEME_SHIFT))&ENET_QOS_TX_SCHEME_MASK) +#define ENET_QOS_RX_FLUSH0_MASK 0x8u +#define ENET_QOS_RX_FLUSH0_SHIFT 3 +#define ENET_QOS_RX_FLUSH1_MASK 0x10u +#define ENET_QOS_RX_FLUSH1_SHIFT 4 +#define ENET_QOS_RX_FLUSH2_MASK 0x20u +#define ENET_QOS_RX_FLUSH2_SHIFT 5 +/* RMON_T_DROP Bit Fields */ +#define ENET_RMON_T_DROP_INCCNTF_MASK 0xFFFFu +#define ENET_RMON_T_DROP_INCCNTF_SHIFT 0 +#define ENET_RMON_T_DROP_INCCNTF(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_DROP_INCCNTF_SHIFT))&ENET_RMON_T_DROP_INCCNTF_MASK) +/* RMON_T_PACKETS Bit Fields */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0 +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK) +/* RMON_T_BC_PKT Bit Fields */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0 +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/* RMON_T_MC_PKT Bit Fields */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0 +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/* RMON_T_CRC_ALIGN Bit Fields */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0 +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/* RMON_T_UNDERSIZE Bit Fields */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0 +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/* RMON_T_OVERSIZE Bit Fields */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0 +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/* RMON_T_FRAG Bit Fields */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0 +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK) +/* RMON_T_JAB Bit Fields */ +#define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_JAB_TXPKTS_SHIFT 0 +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK) +/* RMON_T_COL Bit Fields */ +#define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_COL_TXPKTS_SHIFT 0 +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK) +/* RMON_T_P64 Bit Fields */ +#define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_P64_TXPKTS_SHIFT 0 +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK) +/* RMON_T_P65TO127 Bit Fields */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0 +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK) +/* RMON_T_P128TO255 Bit Fields */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0 +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK) +/* RMON_T_P256TO511 Bit Fields */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0 +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK) +/* RMON_T_P512TO1023 Bit Fields */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0 +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/* RMON_T_P1024TO2047 Bit Fields */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0 +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/* RMON_T_P_GTE2048 Bit Fields */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0 +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/* RMON_T_OCTETS Bit Fields */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0 +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK) +/* IEEE_T_DROP Bit Fields */ +#define ENET_IEEE_T_DROP_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_DROP_COUNT_SHIFT 0 +#define ENET_IEEE_T_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DROP_COUNT_SHIFT))&ENET_IEEE_T_DROP_COUNT_MASK) +/* IEEE_T_FRAME_OK Bit Fields */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0 +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/* IEEE_T_1COL Bit Fields */ +#define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_1COL_COUNT_SHIFT 0 +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK) +/* IEEE_T_MCOL Bit Fields */ +#define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_MCOL_COUNT_SHIFT 0 +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK) +/* IEEE_T_DEF Bit Fields */ +#define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_DEF_COUNT_SHIFT 0 +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK) +/* IEEE_T_LCOL Bit Fields */ +#define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_LCOL_COUNT_SHIFT 0 +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK) +/* IEEE_T_EXCOL Bit Fields */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0 +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK) +/* IEEE_T_MACERR Bit Fields */ +#define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_MACERR_COUNT_SHIFT 0 +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK) +/* IEEE_T_CSERR Bit Fields */ +#define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_CSERR_COUNT_SHIFT 0 +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK) +/* IEEE_T_SQE Bit Fields */ +#define ENET_IEEE_T_SQE_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_SQE_COUNT_SHIFT 0 +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_SQE_COUNT_SHIFT))&ENET_IEEE_T_SQE_COUNT_MASK) +/* IEEE_T_FDXFC Bit Fields */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0 +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK) +/* IEEE_T_OCTETS_OK Bit Fields */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0 +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/* RMON_R_PACKETS Bit Fields */ +#define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_PACKETS_COUNT_SHIFT 0 +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK) +/* RMON_R_BC_PKT Bit Fields */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0 +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK) +/* RMON_R_MC_PKT Bit Fields */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0 +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK) +/* RMON_R_CRC_ALIGN Bit Fields */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0 +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/* RMON_R_UNDERSIZE Bit Fields */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0 +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/* RMON_R_OVERSIZE Bit Fields */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0 +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK) +/* RMON_R_FRAG Bit Fields */ +#define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_FRAG_COUNT_SHIFT 0 +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK) +/* RMON_R_JAB Bit Fields */ +#define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_JAB_COUNT_SHIFT 0 +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK) +/* RMON_R_P64 Bit Fields */ +#define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_P64_COUNT_SHIFT 0 +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK) +/* RMON_R_P65TO127 Bit Fields */ +#define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_P65TO127_COUNT_SHIFT 0 +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK) +/* RMON_R_P128TO255 Bit Fields */ +#define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_P128TO255_COUNT_SHIFT 0 +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK) +/* RMON_R_P256TO511 Bit Fields */ +#define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_P256TO511_COUNT_SHIFT 0 +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK) +/* RMON_R_P512TO1023 Bit Fields */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0 +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK) +/* RMON_R_P1024TO2047 Bit Fields */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0 +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK) +/* RMON_R_P_GTE2048 Bit Fields */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0 +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK) +/* RMON_R_OCTETS Bit Fields */ +#define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu +#define ENET_RMON_R_OCTETS_COUNT_SHIFT 0 +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK) +/* IEEE_R_DROP Bit Fields */ +#define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu +#define ENET_IEEE_R_DROP_COUNT_SHIFT 0 +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK) +/* IEEE_R_FRAME_OK Bit Fields */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0 +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/* IEEE_R_CRC Bit Fields */ +#define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu +#define ENET_IEEE_R_CRC_COUNT_SHIFT 0 +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK) +/* IEEE_R_ALIGN Bit Fields */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0 +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK) +/* IEEE_R_MACERR Bit Fields */ +#define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu +#define ENET_IEEE_R_MACERR_COUNT_SHIFT 0 +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK) +/* IEEE_R_FDXFC Bit Fields */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0 +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK) +/* IEEE_R_OCTETS_OK Bit Fields */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0 +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/* ATCR Bit Fields */ +#define ENET_ATCR_EN_MASK 0x1u +#define ENET_ATCR_EN_SHIFT 0 +#define ENET_ATCR_OFFEN_MASK 0x4u +#define ENET_ATCR_OFFEN_SHIFT 2 +#define ENET_ATCR_OFFRST_MASK 0x8u +#define ENET_ATCR_OFFRST_SHIFT 3 +#define ENET_ATCR_PEREN_MASK 0x10u +#define ENET_ATCR_PEREN_SHIFT 4 +#define ENET_ATCR_PINPER_MASK 0x80u +#define ENET_ATCR_PINPER_SHIFT 7 +#define ENET_ATCR_RESTART_MASK 0x200u +#define ENET_ATCR_RESTART_SHIFT 9 +#define ENET_ATCR_CAPTURE_MASK 0x800u +#define ENET_ATCR_CAPTURE_SHIFT 11 +#define ENET_ATCR_SLAVE_MASK 0x2000u +#define ENET_ATCR_SLAVE_SHIFT 13 +/* ATVR Bit Fields */ +#define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu +#define ENET_ATVR_ATIME_SHIFT 0 +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK) +/* ATOFF Bit Fields */ +#define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu +#define ENET_ATOFF_OFFSET_SHIFT 0 +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK) +/* ATPER Bit Fields */ +#define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu +#define ENET_ATPER_PERIOD_SHIFT 0 +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK) +/* ATCOR Bit Fields */ +#define ENET_ATCOR_COR_MASK 0x7FFFFFFFu +#define ENET_ATCOR_COR_SHIFT 0 +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK) +/* ATINC Bit Fields */ +#define ENET_ATINC_INC_MASK 0x7Fu +#define ENET_ATINC_INC_SHIFT 0 +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK 0x7F00u +#define ENET_ATINC_INC_CORR_SHIFT 8 +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK) +/* ATSTMP Bit Fields */ +#define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu +#define ENET_ATSTMP_TIMESTAMP_SHIFT 0 +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK) +/* TGSR Bit Fields */ +#define ENET_TGSR_TF0_MASK 0x1u +#define ENET_TGSR_TF0_SHIFT 0 +#define ENET_TGSR_TF1_MASK 0x2u +#define ENET_TGSR_TF1_SHIFT 1 +#define ENET_TGSR_TF2_MASK 0x4u +#define ENET_TGSR_TF2_SHIFT 2 +#define ENET_TGSR_TF3_MASK 0x8u +#define ENET_TGSR_TF3_SHIFT 3 +/* TCSR Bit Fields */ +#define ENET_TCSR_TDRE_MASK 0x1u +#define ENET_TCSR_TDRE_SHIFT 0 +#define ENET_TCSR_TMODE_MASK 0x3Cu +#define ENET_TCSR_TMODE_SHIFT 2 +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK 0x40u +#define ENET_TCSR_TIE_SHIFT 6 +#define ENET_TCSR_TF_MASK 0x80u +#define ENET_TCSR_TF_SHIFT 7 +/* TCCR Bit Fields */ +#define ENET_TCCR_TCC_MASK 0xFFFFFFFFu +#define ENET_TCCR_TCC_SHIFT 0 +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK) + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET1 base address */ +#define ENET1_BASE (0x30BE0000u) +/** Peripheral ENET1 base pointer */ +#define ENET1 ((ENET_Type *)ENET1_BASE) +#define ENET1_BASE_PTR (ENET1) +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x30BF0000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +#define ENET2_BASE_PTR (ENET2) +/** Array initializer of ENET peripheral base adresses */ +#define ENET_BASE_ADDRS { ENET1_BASE, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET1, ENET2 } + +/* ---------------------------------------------------------------------------- + -- ENET - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros + * @{ + */ + + +/* ENET - Register instance definitions */ +/* ENET1 */ +#define ENET1_EIR ENET_EIR_REG(ENET1_BASE_PTR) +#define ENET1_EIMR ENET_EIMR_REG(ENET1_BASE_PTR) +#define ENET1_RDAR ENET_RDAR_REG(ENET1_BASE_PTR) +#define ENET1_TDAR ENET_TDAR_REG(ENET1_BASE_PTR) +#define ENET1_ECR ENET_ECR_REG(ENET1_BASE_PTR) +#define ENET1_MMFR ENET_MMFR_REG(ENET1_BASE_PTR) +#define ENET1_MSCR ENET_MSCR_REG(ENET1_BASE_PTR) +#define ENET1_MIBC ENET_MIBC_REG(ENET1_BASE_PTR) +#define ENET1_RCR ENET_RCR_REG(ENET1_BASE_PTR) +#define ENET1_TCR ENET_TCR_REG(ENET1_BASE_PTR) +#define ENET1_PALR ENET_PALR_REG(ENET1_BASE_PTR) +#define ENET1_PAUR ENET_PAUR_REG(ENET1_BASE_PTR) +#define ENET1_OPD ENET_OPD_REG(ENET1_BASE_PTR) +#define ENET1_TXIC0 ENET_TXIC_REG(ENET1_BASE_PTR,0) +#define ENET1_TXIC1 ENET_TXIC_REG(ENET1_BASE_PTR,1) +#define ENET1_TXIC2 ENET_TXIC_REG(ENET1_BASE_PTR,2) +#define ENET1_RXIC0 ENET_RXIC_REG(ENET1_BASE_PTR,0) +#define ENET1_RXIC1 ENET_RXIC_REG(ENET1_BASE_PTR,1) +#define ENET1_RXIC2 ENET_RXIC_REG(ENET1_BASE_PTR,2) +#define ENET1_IAUR ENET_IAUR_REG(ENET1_BASE_PTR) +#define ENET1_IALR ENET_IALR_REG(ENET1_BASE_PTR) +#define ENET1_GAUR ENET_GAUR_REG(ENET1_BASE_PTR) +#define ENET1_GALR ENET_GALR_REG(ENET1_BASE_PTR) +#define ENET1_TFWR ENET_TFWR_REG(ENET1_BASE_PTR) +#define ENET1_RDSR1 ENET_RDSR1_REG(ENET1_BASE_PTR) +#define ENET1_TDSR1 ENET_TDSR1_REG(ENET1_BASE_PTR) +#define ENET1_MRBR1 ENET_MRBR1_REG(ENET1_BASE_PTR) +#define ENET1_RDSR2 ENET_RDSR2_REG(ENET1_BASE_PTR) +#define ENET1_TDSR2 ENET_TDSR2_REG(ENET1_BASE_PTR) +#define ENET1_MRBR2 ENET_MRBR2_REG(ENET1_BASE_PTR) +#define ENET1_RDSR ENET_RDSR_REG(ENET1_BASE_PTR) +#define ENET1_TDSR ENET_TDSR_REG(ENET1_BASE_PTR) +#define ENET1_MRBR ENET_MRBR_REG(ENET1_BASE_PTR) +#define ENET1_RSFL ENET_RSFL_REG(ENET1_BASE_PTR) +#define ENET1_RSEM ENET_RSEM_REG(ENET1_BASE_PTR) +#define ENET1_RAEM ENET_RAEM_REG(ENET1_BASE_PTR) +#define ENET1_RAFL ENET_RAFL_REG(ENET1_BASE_PTR) +#define ENET1_TSEM ENET_TSEM_REG(ENET1_BASE_PTR) +#define ENET1_TAEM ENET_TAEM_REG(ENET1_BASE_PTR) +#define ENET1_TAFL ENET_TAFL_REG(ENET1_BASE_PTR) +#define ENET1_TIPG ENET_TIPG_REG(ENET1_BASE_PTR) +#define ENET1_FTRL ENET_FTRL_REG(ENET1_BASE_PTR) +#define ENET1_TACC ENET_TACC_REG(ENET1_BASE_PTR) +#define ENET1_RACC ENET_RACC_REG(ENET1_BASE_PTR) +#define ENET1_RCMR1 ENET_RCMR_REG(ENET1_BASE_PTR,0) +#define ENET1_RCMR2 ENET_RCMR_REG(ENET1_BASE_PTR,1) +#define ENET1_DMA1CFG ENET_DMACFG_REG(ENET1_BASE_PTR,0) +#define ENET1_DMA2CFG ENET_DMACFG_REG(ENET1_BASE_PTR,1) +#define ENET1_RDAR1 ENET_RDAR1_REG(ENET1_BASE_PTR) +#define ENET1_TDAR1 ENET_TDAR1_REG(ENET1_BASE_PTR) +#define ENET1_RDAR2 ENET_RDAR2_REG(ENET1_BASE_PTR) +#define ENET1_TDAR2 ENET_TDAR2_REG(ENET1_BASE_PTR) +#define ENET1_QOS ENET_QOS_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_COL ENET_RMON_T_COL_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_P64 ENET_RMON_T_P64_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET1_BASE_PTR) +#define ENET1_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_P64 ENET_RMON_R_P64_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET1_BASE_PTR) +#define ENET1_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET1_BASE_PTR) +#define ENET1_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET1_BASE_PTR) +#define ENET1_ATCR ENET_ATCR_REG(ENET1_BASE_PTR) +#define ENET1_ATVR ENET_ATVR_REG(ENET1_BASE_PTR) +#define ENET1_ATOFF ENET_ATOFF_REG(ENET1_BASE_PTR) +#define ENET1_ATPER ENET_ATPER_REG(ENET1_BASE_PTR) +#define ENET1_ATCOR ENET_ATCOR_REG(ENET1_BASE_PTR) +#define ENET1_ATINC ENET_ATINC_REG(ENET1_BASE_PTR) +#define ENET1_ATSTMP ENET_ATSTMP_REG(ENET1_BASE_PTR) +#define ENET1_TGSR ENET_TGSR_REG(ENET1_BASE_PTR) +#define ENET1_TCSR0 ENET_TCSR_REG(ENET1_BASE_PTR,0) +#define ENET1_TCCR0 ENET_TCCR_REG(ENET1_BASE_PTR,0) +#define ENET1_TCSR1 ENET_TCSR_REG(ENET1_BASE_PTR,1) +#define ENET1_TCCR1 ENET_TCCR_REG(ENET1_BASE_PTR,1) +#define ENET1_TCSR2 ENET_TCSR_REG(ENET1_BASE_PTR,2) +#define ENET1_TCCR2 ENET_TCCR_REG(ENET1_BASE_PTR,2) +#define ENET1_TCSR3 ENET_TCSR_REG(ENET1_BASE_PTR,3) +#define ENET1_TCCR3 ENET_TCCR_REG(ENET1_BASE_PTR,3) +/* ENET2 */ +#define ENET2_EIR ENET_EIR_REG(ENET2_BASE_PTR) +#define ENET2_EIMR ENET_EIMR_REG(ENET2_BASE_PTR) +#define ENET2_RDAR ENET_RDAR_REG(ENET2_BASE_PTR) +#define ENET2_TDAR ENET_TDAR_REG(ENET2_BASE_PTR) +#define ENET2_ECR ENET_ECR_REG(ENET2_BASE_PTR) +#define ENET2_MMFR ENET_MMFR_REG(ENET2_BASE_PTR) +#define ENET2_MSCR ENET_MSCR_REG(ENET2_BASE_PTR) +#define ENET2_MIBC ENET_MIBC_REG(ENET2_BASE_PTR) +#define ENET2_RCR ENET_RCR_REG(ENET2_BASE_PTR) +#define ENET2_TCR ENET_TCR_REG(ENET2_BASE_PTR) +#define ENET2_PALR ENET_PALR_REG(ENET2_BASE_PTR) +#define ENET2_PAUR ENET_PAUR_REG(ENET2_BASE_PTR) +#define ENET2_OPD ENET_OPD_REG(ENET2_BASE_PTR) +#define ENET2_TXIC0 ENET_TXIC_REG(ENET2_BASE_PTR,0) +#define ENET2_TXIC1 ENET_TXIC_REG(ENET2_BASE_PTR,1) +#define ENET2_TXIC2 ENET_TXIC_REG(ENET2_BASE_PTR,2) +#define ENET2_RXIC0 ENET_RXIC_REG(ENET2_BASE_PTR,0) +#define ENET2_RXIC1 ENET_RXIC_REG(ENET2_BASE_PTR,1) +#define ENET2_RXIC2 ENET_RXIC_REG(ENET2_BASE_PTR,2) +#define ENET2_IAUR ENET_IAUR_REG(ENET2_BASE_PTR) +#define ENET2_IALR ENET_IALR_REG(ENET2_BASE_PTR) +#define ENET2_GAUR ENET_GAUR_REG(ENET2_BASE_PTR) +#define ENET2_GALR ENET_GALR_REG(ENET2_BASE_PTR) +#define ENET2_TFWR ENET_TFWR_REG(ENET2_BASE_PTR) +#define ENET2_RDSR1 ENET_RDSR1_REG(ENET2_BASE_PTR) +#define ENET2_TDSR1 ENET_TDSR1_REG(ENET2_BASE_PTR) +#define ENET2_MRBR1 ENET_MRBR1_REG(ENET2_BASE_PTR) +#define ENET2_RDSR2 ENET_RDSR2_REG(ENET2_BASE_PTR) +#define ENET2_TDSR2 ENET_TDSR2_REG(ENET2_BASE_PTR) +#define ENET2_MRBR2 ENET_MRBR2_REG(ENET2_BASE_PTR) +#define ENET2_RDSR ENET_RDSR_REG(ENET2_BASE_PTR) +#define ENET2_TDSR ENET_TDSR_REG(ENET2_BASE_PTR) +#define ENET2_MRBR ENET_MRBR_REG(ENET2_BASE_PTR) +#define ENET2_RSFL ENET_RSFL_REG(ENET2_BASE_PTR) +#define ENET2_RSEM ENET_RSEM_REG(ENET2_BASE_PTR) +#define ENET2_RAEM ENET_RAEM_REG(ENET2_BASE_PTR) +#define ENET2_RAFL ENET_RAFL_REG(ENET2_BASE_PTR) +#define ENET2_TSEM ENET_TSEM_REG(ENET2_BASE_PTR) +#define ENET2_TAEM ENET_TAEM_REG(ENET2_BASE_PTR) +#define ENET2_TAFL ENET_TAFL_REG(ENET2_BASE_PTR) +#define ENET2_TIPG ENET_TIPG_REG(ENET2_BASE_PTR) +#define ENET2_FTRL ENET_FTRL_REG(ENET2_BASE_PTR) +#define ENET2_TACC ENET_TACC_REG(ENET2_BASE_PTR) +#define ENET2_RACC ENET_RACC_REG(ENET2_BASE_PTR) +#define ENET2_RCMR1 ENET_RCMR_REG(ENET2_BASE_PTR,0) +#define ENET2_RCMR2 ENET_RCMR_REG(ENET2_BASE_PTR,1) +#define ENET2_DMA1CFG ENET_DMACFG_REG(ENET2_BASE_PTR,0) +#define ENET2_DMA2CFG ENET_DMACFG_REG(ENET2_BASE_PTR,1) +#define ENET2_RDAR1 ENET_RDAR1_REG(ENET2_BASE_PTR) +#define ENET2_TDAR1 ENET_TDAR1_REG(ENET2_BASE_PTR) +#define ENET2_RDAR2 ENET_RDAR2_REG(ENET2_BASE_PTR) +#define ENET2_TDAR2 ENET_TDAR2_REG(ENET2_BASE_PTR) +#define ENET2_QOS ENET_QOS_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_COL ENET_RMON_T_COL_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_P64 ENET_RMON_T_P64_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET2_BASE_PTR) +#define ENET2_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_P64 ENET_RMON_R_P64_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET2_BASE_PTR) +#define ENET2_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET2_BASE_PTR) +#define ENET2_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET2_BASE_PTR) +#define ENET2_ATCR ENET_ATCR_REG(ENET2_BASE_PTR) +#define ENET2_ATVR ENET_ATVR_REG(ENET2_BASE_PTR) +#define ENET2_ATOFF ENET_ATOFF_REG(ENET2_BASE_PTR) +#define ENET2_ATPER ENET_ATPER_REG(ENET2_BASE_PTR) +#define ENET2_ATCOR ENET_ATCOR_REG(ENET2_BASE_PTR) +#define ENET2_ATINC ENET_ATINC_REG(ENET2_BASE_PTR) +#define ENET2_ATSTMP ENET_ATSTMP_REG(ENET2_BASE_PTR) +#define ENET2_TGSR ENET_TGSR_REG(ENET2_BASE_PTR) +#define ENET2_TCSR0 ENET_TCSR_REG(ENET2_BASE_PTR,0) +#define ENET2_TCCR0 ENET_TCCR_REG(ENET2_BASE_PTR,0) +#define ENET2_TCSR1 ENET_TCSR_REG(ENET2_BASE_PTR,1) +#define ENET2_TCCR1 ENET_TCCR_REG(ENET2_BASE_PTR,1) +#define ENET2_TCSR2 ENET_TCSR_REG(ENET2_BASE_PTR,2) +#define ENET2_TCCR2 ENET_TCCR_REG(ENET2_BASE_PTR,2) +#define ENET2_TCSR3 ENET_TCSR_REG(ENET2_BASE_PTR,3) +#define ENET2_TCCR3 ENET_TCCR_REG(ENET2_BASE_PTR,3) + +/* ENET - Register array accessors */ +#define ENET1_TXIC(index) ENET_TXIC_REG(ENET1_BASE_PTR,index) +#define ENET2_TXIC(index) ENET_TXIC_REG(ENET2_BASE_PTR,index) +#define ENET1_RXIC(index) ENET_RXIC_REG(ENET1_BASE_PTR,index) +#define ENET2_RXIC(index) ENET_RXIC_REG(ENET2_BASE_PTR,index) +#define ENET1_RCMR(index) ENET_RCMR_REG(ENET1_BASE_PTR,index) +#define ENET2_RCMR(index) ENET_RCMR_REG(ENET2_BASE_PTR,index) +#define ENET1_DMACFG(index) ENET_DMACFG_REG(ENET1_BASE_PTR,index) +#define ENET2_DMACFG(index) ENET_DMACFG_REG(ENET2_BASE_PTR,index) +#define ENET1_TCSR(index) ENET_TCSR_REG(ENET1_BASE_PTR,index) +#define ENET2_TCSR(index) ENET_TCSR_REG(ENET2_BASE_PTR,index) +#define ENET1_TCCR(index) ENET_TCCR_REG(ENET1_BASE_PTR,index) +#define ENET2_TCCR(index) ENET_TCCR_REG(ENET2_BASE_PTR,index) + +/*! + * @} + */ /* end of group ENET_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group ENET_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- EPDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPDC_Peripheral_Access_Layer EPDC Peripheral Access Layer + * @{ + */ + +/** EPDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< EPDC Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< EPDC Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< EPDC Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< EPDC Control Register, offset: 0xC */ + uint8_t RESERVED_0[16]; + __IO uint32_t WVADDR; /**< EPDC Waveform Address Pointer, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t WB_ADDR; /**< EPDC Working Buffer Address, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t RES; /**< EPDC Screen Resolution, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FORMAT; /**< EPDC Format Control Register, offset: 0x50 */ + __IO uint32_t FORMAT_SET; /**< EPDC Format Control Register, offset: 0x54 */ + __IO uint32_t FORMAT_CLR; /**< EPDC Format Control Register, offset: 0x58 */ + __IO uint32_t FORMAT_TOG; /**< EPDC Format Control Register, offset: 0x5C */ + uint8_t RESERVED_4[64]; + __IO uint32_t FIFOCTRL; /**< EPDC FIFO control register, offset: 0xA0 */ + __IO uint32_t FIFOCTRL_SET; /**< EPDC FIFO control register, offset: 0xA4 */ + __IO uint32_t FIFOCTRL_CLR; /**< EPDC FIFO control register, offset: 0xA8 */ + __IO uint32_t FIFOCTRL_TOG; /**< EPDC FIFO control register, offset: 0xAC */ + uint8_t RESERVED_5[80]; + __IO uint32_t UPD_ADDR; /**< EPDC Update Region Address, offset: 0x100 */ + uint8_t RESERVED_6[12]; + __IO uint32_t UPD_STRIDE; /**< EPDC Update Region Stride, offset: 0x110 */ + uint8_t RESERVED_7[12]; + __IO uint32_t UPD_CORD; /**< EPDC Update Command Co-ordinate, offset: 0x120 */ + uint8_t RESERVED_8[28]; + __IO uint32_t UPD_SIZE; /**< EPDC Update Command Size, offset: 0x140 */ + uint8_t RESERVED_9[28]; + __IO uint32_t UPD_CTRL; /**< EPDC Update Command Control, offset: 0x160 */ + __IO uint32_t UPD_CTRL_SET; /**< EPDC Update Command Control, offset: 0x164 */ + __IO uint32_t UPD_CTRL_CLR; /**< EPDC Update Command Control, offset: 0x168 */ + __IO uint32_t UPD_CTRL_TOG; /**< EPDC Update Command Control, offset: 0x16C */ + uint8_t RESERVED_10[16]; + __IO uint32_t UPD_FIXED; /**< EPDC Update Fixed Pixel Control, offset: 0x180 */ + __IO uint32_t UPD_FIXED_SET; /**< EPDC Update Fixed Pixel Control, offset: 0x184 */ + __IO uint32_t UPD_FIXED_CLR; /**< EPDC Update Fixed Pixel Control, offset: 0x188 */ + __IO uint32_t UPD_FIXED_TOG; /**< EPDC Update Fixed Pixel Control, offset: 0x18C */ + uint8_t RESERVED_11[16]; + __IO uint32_t TEMP; /**< EPDC Temperature Register, offset: 0x1A0 */ + uint8_t RESERVED_12[28]; + __IO uint32_t AUTOWV_LUT; /**< Waveform Mode Lookup Table Control Register., offset: 0x1C0 */ + uint8_t RESERVED_13[60]; + __IO uint32_t TCE_CTRL; /**< EPDC Timing Control Engine Control Register, offset: 0x200 */ + __IO uint32_t TCE_CTRL_SET; /**< EPDC Timing Control Engine Control Register, offset: 0x204 */ + __IO uint32_t TCE_CTRL_CLR; /**< EPDC Timing Control Engine Control Register, offset: 0x208 */ + __IO uint32_t TCE_CTRL_TOG; /**< EPDC Timing Control Engine Control Register, offset: 0x20C */ + uint8_t RESERVED_14[16]; + __IO uint32_t TCE_SDCFG; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x220 */ + __IO uint32_t TCE_SDCFG_SET; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x224 */ + __IO uint32_t TCE_SDCFG_CLR; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x228 */ + __IO uint32_t TCE_SDCFG_TOG; /**< EPDC Timing Control Engine Source-Driver Config Register, offset: 0x22C */ + uint8_t RESERVED_15[16]; + __IO uint32_t TCE_GDCFG; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x240 */ + __IO uint32_t TCE_GDCFG_SET; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x244 */ + __IO uint32_t TCE_GDCFG_CLR; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x248 */ + __IO uint32_t TCE_GDCFG_TOG; /**< EPDC Timing Control Engine Gate-Driver Config Register, offset: 0x24C */ + uint8_t RESERVED_16[16]; + __IO uint32_t TCE_HSCAN1; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x260 */ + __IO uint32_t TCE_HSCAN1_SET; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x264 */ + __IO uint32_t TCE_HSCAN1_CLR; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x268 */ + __IO uint32_t TCE_HSCAN1_TOG; /**< EPDC Timing Control Engine Horizontal Timing Register 1, offset: 0x26C */ + uint8_t RESERVED_17[16]; + __IO uint32_t TCE_HSCAN2; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x280 */ + __IO uint32_t TCE_HSCAN2_SET; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x284 */ + __IO uint32_t TCE_HSCAN2_CLR; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x288 */ + __IO uint32_t TCE_HSCAN2_TOG; /**< EPDC Timing Control Engine Horizontal Timing Register 2, offset: 0x28C */ + uint8_t RESERVED_18[16]; + __IO uint32_t TCE_VSCAN; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A0 */ + __IO uint32_t TCE_VSCAN_SET; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A4 */ + __IO uint32_t TCE_VSCAN_CLR; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2A8 */ + __IO uint32_t TCE_VSCAN_TOG; /**< EPDC Timing Control Engine Vertical Timing Register, offset: 0x2AC */ + uint8_t RESERVED_19[16]; + __IO uint32_t TCE_OE; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C0 */ + __IO uint32_t TCE_OE_SET; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C4 */ + __IO uint32_t TCE_OE_CLR; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2C8 */ + __IO uint32_t TCE_OE_TOG; /**< EPDC Timing Control Engine OE timing control Register, offset: 0x2CC */ + uint8_t RESERVED_20[16]; + __IO uint32_t TCE_POLARITY; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E0 */ + __IO uint32_t TCE_POLARITY_SET; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E4 */ + __IO uint32_t TCE_POLARITY_CLR; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2E8 */ + __IO uint32_t TCE_POLARITY_TOG; /**< EPDC Timing Control Engine Driver Polarity Register, offset: 0x2EC */ + uint8_t RESERVED_21[16]; + __IO uint32_t TCE_TIMING1; /**< EPDC Timing Control Engine Timing Register 1, offset: 0x300 */ + __IO uint32_t TCE_TIMING1_SET; /**< EPDC Timing Control Engine Timing Register 1, offset: 0x304 */ + __IO uint32_t TCE_TIMING1_CLR; /**< EPDC Timing Control Engine Timing Register 1, offset: 0x308 */ + __IO uint32_t TCE_TIMING1_TOG; /**< EPDC Timing Control Engine Timing Register 1, offset: 0x30C */ + __IO uint32_t TCE_TIMING2; /**< EPDC Timing Control Engine Timing Register 2, offset: 0x310 */ + __IO uint32_t TCE_TIMING2_SET; /**< EPDC Timing Control Engine Timing Register 2, offset: 0x314 */ + __IO uint32_t TCE_TIMING2_CLR; /**< EPDC Timing Control Engine Timing Register 2, offset: 0x318 */ + __IO uint32_t TCE_TIMING2_TOG; /**< EPDC Timing Control Engine Timing Register 2, offset: 0x31C */ + __IO uint32_t TCE_TIMING3; /**< EPDC Timing Control Engine Timing Register 3, offset: 0x320 */ + __IO uint32_t TCE_TIMING3_SET; /**< EPDC Timing Control Engine Timing Register 3, offset: 0x324 */ + __IO uint32_t TCE_TIMING3_CLR; /**< EPDC Timing Control Engine Timing Register 3, offset: 0x328 */ + __IO uint32_t TCE_TIMING3_TOG; /**< EPDC Timing Control Engine Timing Register 3, offset: 0x32C */ + uint8_t RESERVED_22[80]; + __IO uint32_t PIGEON_CTRL0; /**< EPDC Pigeon Mode Control Register 0, offset: 0x380 */ + __IO uint32_t PIGEON_CTRL0_SET; /**< EPDC Pigeon Mode Control Register 0, offset: 0x384 */ + __IO uint32_t PIGEON_CTRL0_CLR; /**< EPDC Pigeon Mode Control Register 0, offset: 0x388 */ + __IO uint32_t PIGEON_CTRL0_TOG; /**< EPDC Pigeon Mode Control Register 0, offset: 0x38C */ + __IO uint32_t PIGEON_CTRL1; /**< EPDC Pigeon Mode Control Register 1, offset: 0x390 */ + __IO uint32_t PIGEON_CTRL1_SET; /**< EPDC Pigeon Mode Control Register 1, offset: 0x394 */ + __IO uint32_t PIGEON_CTRL1_CLR; /**< EPDC Pigeon Mode Control Register 1, offset: 0x398 */ + __IO uint32_t PIGEON_CTRL1_TOG; /**< EPDC Pigeon Mode Control Register 1, offset: 0x39C */ + uint8_t RESERVED_23[32]; + __IO uint32_t IRQ_MASK1; /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C0 */ + __IO uint32_t IRQ_MASK1_SET; /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C4 */ + __IO uint32_t IRQ_MASK1_CLR; /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3C8 */ + __IO uint32_t IRQ_MASK1_TOG; /**< EPDC IRQ Mask Register for LUT 0~31, offset: 0x3CC */ + __IO uint32_t IRQ_MASK2; /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3D0 */ + __IO uint32_t IRQ_MASK2_SET; /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3D4 */ + __IO uint32_t IRQ_MASK2_CLR; /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3D8 */ + __IO uint32_t IRQ_MASK2_TOG; /**< EPDC IRQ Mask Register for LUT 32~63, offset: 0x3DC */ + __IO uint32_t IRQ1; /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3E0 */ + __IO uint32_t IRQ1_SET; /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3E4 */ + __IO uint32_t IRQ1_CLR; /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3E8 */ + __IO uint32_t IRQ1_TOG; /**< EPDC Interrupt Register for LUT 0~31, offset: 0x3EC */ + __IO uint32_t IRQ2; /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3F0 */ + __IO uint32_t IRQ2_SET; /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3F4 */ + __IO uint32_t IRQ2_CLR; /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3F8 */ + __IO uint32_t IRQ2_TOG; /**< EPDC Interrupt Registerr for LUT 32~63, offset: 0x3FC */ + __IO uint32_t IRQ_MASK; /**< EPDC IRQ Mask Register, offset: 0x400 */ + __IO uint32_t IRQ_MASK_SET; /**< EPDC IRQ Mask Register, offset: 0x404 */ + __IO uint32_t IRQ_MASK_CLR; /**< EPDC IRQ Mask Register, offset: 0x408 */ + __IO uint32_t IRQ_MASK_TOG; /**< EPDC IRQ Mask Register, offset: 0x40C */ + uint8_t RESERVED_24[16]; + __IO uint32_t IRQ; /**< EPDC Interrupt Register, offset: 0x420 */ + __IO uint32_t IRQ_SET; /**< EPDC Interrupt Register, offset: 0x424 */ + __IO uint32_t IRQ_CLR; /**< EPDC Interrupt Register, offset: 0x428 */ + __IO uint32_t IRQ_TOG; /**< EPDC Interrupt Register, offset: 0x42C */ + uint8_t RESERVED_25[16]; + __IO uint32_t STATUS_LUTS1; /**< EPDC Status Register - LUTs, offset: 0x440 */ + __IO uint32_t STATUS_LUTS1_SET; /**< EPDC Status Register - LUTs, offset: 0x444 */ + __IO uint32_t STATUS_LUTS1_CLR; /**< EPDC Status Register - LUTs, offset: 0x448 */ + __IO uint32_t STATUS_LUTS1_TOG; /**< EPDC Status Register - LUTs, offset: 0x44C */ + __IO uint32_t STATUS_LUTS2; /**< EPDC Status Register - LUTs, offset: 0x450 */ + __IO uint32_t STATUS_LUTS2_SET; /**< EPDC Status Register - LUTs, offset: 0x454 */ + __IO uint32_t STATUS_LUTS2_CLR; /**< EPDC Status Register - LUTs, offset: 0x458 */ + __IO uint32_t STATUS_LUTS2_TOG; /**< EPDC Status Register - LUTs, offset: 0x45C */ + __IO uint32_t STATUS_NEXTLUT; /**< EPDC Status Register - Next Available LUT, offset: 0x460 */ + uint8_t RESERVED_26[28]; + __IO uint32_t STATUS_COL1; /**< EPDC LUT Collision Status, offset: 0x480 */ + __IO uint32_t STATUS_COL1_SET; /**< EPDC LUT Collision Status, offset: 0x484 */ + __IO uint32_t STATUS_COL1_CLR; /**< EPDC LUT Collision Status, offset: 0x488 */ + __IO uint32_t STATUS_COL1_TOG; /**< EPDC LUT Collision Status, offset: 0x48C */ + __IO uint32_t STATUS_COL2; /**< EPDC LUT Collision Status, offset: 0x490 */ + __IO uint32_t STATUS_COL2_SET; /**< EPDC LUT Collision Status, offset: 0x494 */ + __IO uint32_t STATUS_COL2_CLR; /**< EPDC LUT Collision Status, offset: 0x498 */ + __IO uint32_t STATUS_COL2_TOG; /**< EPDC LUT Collision Status, offset: 0x49C */ + __IO uint32_t STATUS; /**< EPDC General Status Register, offset: 0x4A0 */ + __IO uint32_t STATUS_SET; /**< EPDC General Status Register, offset: 0x4A4 */ + __IO uint32_t STATUS_CLR; /**< EPDC General Status Register, offset: 0x4A8 */ + __IO uint32_t STATUS_TOG; /**< EPDC General Status Register, offset: 0x4AC */ + uint8_t RESERVED_27[16]; + __IO uint32_t UPD_COL_CORD; /**< EPDC Collision Region Co-ordinate, offset: 0x4C0 */ + uint8_t RESERVED_28[28]; + __IO uint32_t UPD_COL_SIZE; /**< EPDC Collision Region Size, offset: 0x4E0 */ + uint8_t RESERVED_29[284]; + __IO uint32_t HIST1_PARAM; /**< 1-level Histogram Parameter Register., offset: 0x600 */ + uint8_t RESERVED_30[12]; + __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x610 */ + uint8_t RESERVED_31[12]; + __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x620 */ + uint8_t RESERVED_32[12]; + __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x630 */ + uint8_t RESERVED_33[12]; + __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x640 */ + uint8_t RESERVED_34[12]; + __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x650 */ + uint8_t RESERVED_35[12]; + __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter Register., offset: 0x660 */ + uint8_t RESERVED_36[12]; + __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter Register., offset: 0x670 */ + uint8_t RESERVED_37[12]; + __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter Register., offset: 0x680 */ + uint8_t RESERVED_38[124]; + __IO uint32_t GPIO; /**< EPDC General Purpose I/O Debug register, offset: 0x700 */ + __IO uint32_t GPIO_SET; /**< EPDC General Purpose I/O Debug register, offset: 0x704 */ + __IO uint32_t GPIO_CLR; /**< EPDC General Purpose I/O Debug register, offset: 0x708 */ + __IO uint32_t GPIO_TOG; /**< EPDC General Purpose I/O Debug register, offset: 0x70C */ + uint8_t RESERVED_39[224]; + __IO uint32_t VERSION; /**< EPDC Version Register, offset: 0x7F0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t PIGEON_0_0; /**< Panel Interface Signal Generator Register 0_0, offset: 0x800 */ + uint8_t RESERVED_41[12]; + __IO uint32_t PIGEON_0_1; /**< Panel Interface Signal Generator Register 0_1, offset: 0x810 */ + uint8_t RESERVED_42[12]; + __IO uint32_t PIGEON_0_2; /**< Panel Interface Signal Generator Register 0_1, offset: 0x820 */ + uint8_t RESERVED_43[28]; + __IO uint32_t PIGEON_1_0; /**< Panel Interface Signal Generator Register 1_0, offset: 0x840 */ + uint8_t RESERVED_44[12]; + __IO uint32_t PIGEON_1_1; /**< Panel Interface Signal Generator Register 1_1, offset: 0x850 */ + uint8_t RESERVED_45[12]; + __IO uint32_t PIGEON_1_2; /**< Panel Interface Signal Generator Register 1_1, offset: 0x860 */ + uint8_t RESERVED_46[28]; + __IO uint32_t PIGEON_2_0; /**< Panel Interface Signal Generator Register 2_0, offset: 0x880 */ + uint8_t RESERVED_47[12]; + __IO uint32_t PIGEON_2_1; /**< Panel Interface Signal Generator Register 2_1, offset: 0x890 */ + uint8_t RESERVED_48[12]; + __IO uint32_t PIGEON_2_2; /**< Panel Interface Signal Generator Register 2_1, offset: 0x8A0 */ + uint8_t RESERVED_49[28]; + __IO uint32_t PIGEON_3_0; /**< Panel Interface Signal Generator Register 3_0, offset: 0x8C0 */ + uint8_t RESERVED_50[12]; + __IO uint32_t PIGEON_3_1; /**< Panel Interface Signal Generator Register 3_1, offset: 0x8D0 */ + uint8_t RESERVED_51[12]; + __IO uint32_t PIGEON_3_2; /**< Panel Interface Signal Generator Register 3_1, offset: 0x8E0 */ + uint8_t RESERVED_52[28]; + __IO uint32_t PIGEON_4_0; /**< Panel Interface Signal Generator Register 4_0, offset: 0x900 */ + uint8_t RESERVED_53[12]; + __IO uint32_t PIGEON_4_1; /**< Panel Interface Signal Generator Register 4_1, offset: 0x910 */ + uint8_t RESERVED_54[12]; + __IO uint32_t PIGEON_4_2; /**< Panel Interface Signal Generator Register 4_1, offset: 0x920 */ + uint8_t RESERVED_55[28]; + __IO uint32_t PIGEON_5_0; /**< Panel Interface Signal Generator Register 5_0, offset: 0x940 */ + uint8_t RESERVED_56[12]; + __IO uint32_t PIGEON_5_1; /**< Panel Interface Signal Generator Register 5_1, offset: 0x950 */ + uint8_t RESERVED_57[12]; + __IO uint32_t PIGEON_5_2; /**< Panel Interface Signal Generator Register 5_1, offset: 0x960 */ + uint8_t RESERVED_58[28]; + __IO uint32_t PIGEON_6_0; /**< Panel Interface Signal Generator Register 6_0, offset: 0x980 */ + uint8_t RESERVED_59[12]; + __IO uint32_t PIGEON_6_1; /**< Panel Interface Signal Generator Register 6_1, offset: 0x990 */ + uint8_t RESERVED_60[12]; + __IO uint32_t PIGEON_6_2; /**< Panel Interface Signal Generator Register 6_1, offset: 0x9A0 */ + uint8_t RESERVED_61[28]; + __IO uint32_t PIGEON_7_0; /**< Panel Interface Signal Generator Register 7_0, offset: 0x9C0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t PIGEON_7_1; /**< Panel Interface Signal Generator Register 7_1, offset: 0x9D0 */ + uint8_t RESERVED_63[12]; + __IO uint32_t PIGEON_7_2; /**< Panel Interface Signal Generator Register 7_1, offset: 0x9E0 */ + uint8_t RESERVED_64[28]; + __IO uint32_t PIGEON_8_0; /**< Panel Interface Signal Generator Register 8_0, offset: 0xA00 */ + uint8_t RESERVED_65[12]; + __IO uint32_t PIGEON_8_1; /**< Panel Interface Signal Generator Register 8_1, offset: 0xA10 */ + uint8_t RESERVED_66[12]; + __IO uint32_t PIGEON_8_2; /**< Panel Interface Signal Generator Register 8_1, offset: 0xA20 */ + uint8_t RESERVED_67[28]; + __IO uint32_t PIGEON_9_0; /**< Panel Interface Signal Generator Register 9_0, offset: 0xA40 */ + uint8_t RESERVED_68[12]; + __IO uint32_t PIGEON_9_1; /**< Panel Interface Signal Generator Register 9_1, offset: 0xA50 */ + uint8_t RESERVED_69[12]; + __IO uint32_t PIGEON_9_2; /**< Panel Interface Signal Generator Register 9_1, offset: 0xA60 */ + uint8_t RESERVED_70[28]; + __IO uint32_t PIGEON_10_0; /**< Panel Interface Signal Generator Register 10_0, offset: 0xA80 */ + uint8_t RESERVED_71[12]; + __IO uint32_t PIGEON_10_1; /**< Panel Interface Signal Generator Register 10_1, offset: 0xA90 */ + uint8_t RESERVED_72[12]; + __IO uint32_t PIGEON_10_2; /**< Panel Interface Signal Generator Register 10_1, offset: 0xAA0 */ + uint8_t RESERVED_73[28]; + __IO uint32_t PIGEON_11_0; /**< Panel Interface Signal Generator Register 11_0, offset: 0xAC0 */ + uint8_t RESERVED_74[12]; + __IO uint32_t PIGEON_11_1; /**< Panel Interface Signal Generator Register 11_1, offset: 0xAD0 */ + uint8_t RESERVED_75[12]; + __IO uint32_t PIGEON_11_2; /**< Panel Interface Signal Generator Register 11_1, offset: 0xAE0 */ + uint8_t RESERVED_76[28]; + __IO uint32_t PIGEON_12_0; /**< Panel Interface Signal Generator Register 12_0, offset: 0xB00 */ + uint8_t RESERVED_77[12]; + __IO uint32_t PIGEON_12_1; /**< Panel Interface Signal Generator Register 12_1, offset: 0xB10 */ + uint8_t RESERVED_78[12]; + __IO uint32_t PIGEON_12_2; /**< Panel Interface Signal Generator Register 12_1, offset: 0xB20 */ + uint8_t RESERVED_79[28]; + __IO uint32_t PIGEON_13_0; /**< Panel Interface Signal Generator Register 13_0, offset: 0xB40 */ + uint8_t RESERVED_80[12]; + __IO uint32_t PIGEON_13_1; /**< Panel Interface Signal Generator Register 13_1, offset: 0xB50 */ + uint8_t RESERVED_81[12]; + __IO uint32_t PIGEON_13_2; /**< Panel Interface Signal Generator Register 13_1, offset: 0xB60 */ + uint8_t RESERVED_82[28]; + __IO uint32_t PIGEON_14_0; /**< Panel Interface Signal Generator Register 14_0, offset: 0xB80 */ + uint8_t RESERVED_83[12]; + __IO uint32_t PIGEON_14_1; /**< Panel Interface Signal Generator Register 14_1, offset: 0xB90 */ + uint8_t RESERVED_84[12]; + __IO uint32_t PIGEON_14_2; /**< Panel Interface Signal Generator Register 14_1, offset: 0xBA0 */ + uint8_t RESERVED_85[28]; + __IO uint32_t PIGEON_15_0; /**< Panel Interface Signal Generator Register 15_0, offset: 0xBC0 */ + uint8_t RESERVED_86[12]; + __IO uint32_t PIGEON_15_1; /**< Panel Interface Signal Generator Register 15_1, offset: 0xBD0 */ + uint8_t RESERVED_87[12]; + __IO uint32_t PIGEON_15_2; /**< Panel Interface Signal Generator Register 15_1, offset: 0xBE0 */ + uint8_t RESERVED_88[28]; + __IO uint32_t PIGEON_16_0; /**< Panel Interface Signal Generator Register 16_0, offset: 0xC00 */ + uint8_t RESERVED_89[12]; + union { /* offset: 0xC10 */ + __IO uint32_t PIGEON_16_1; /**< Panel Interface Signal Generator Register 16_1, offset: 0xC10 */ + __IO uint32_t WB_ADDR_TCE; /**< EPDC Working Buffer Address for TCE, offset: 0xC10 */ + }; + uint8_t RESERVED_90[12]; + __IO uint32_t PIGEON_16_2; /**< Panel Interface Signal Generator Register 16_1, offset: 0xC20 */ +} EPDC_Type, *EPDC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- EPDC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPDC_Register_Accessor_Macros EPDC - Register accessor macros + * @{ + */ + + +/* EPDC - Register accessors */ +#define EPDC_CTRL_REG(base) ((base)->CTRL) +#define EPDC_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define EPDC_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define EPDC_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define EPDC_WVADDR_REG(base) ((base)->WVADDR) +#define EPDC_WB_ADDR_REG(base) ((base)->WB_ADDR) +#define EPDC_RES_REG(base) ((base)->RES) +#define EPDC_FORMAT_REG(base) ((base)->FORMAT) +#define EPDC_FORMAT_SET_REG(base) ((base)->FORMAT_SET) +#define EPDC_FORMAT_CLR_REG(base) ((base)->FORMAT_CLR) +#define EPDC_FORMAT_TOG_REG(base) ((base)->FORMAT_TOG) +#define EPDC_FIFOCTRL_REG(base) ((base)->FIFOCTRL) +#define EPDC_FIFOCTRL_SET_REG(base) ((base)->FIFOCTRL_SET) +#define EPDC_FIFOCTRL_CLR_REG(base) ((base)->FIFOCTRL_CLR) +#define EPDC_FIFOCTRL_TOG_REG(base) ((base)->FIFOCTRL_TOG) +#define EPDC_UPD_ADDR_REG(base) ((base)->UPD_ADDR) +#define EPDC_UPD_STRIDE_REG(base) ((base)->UPD_STRIDE) +#define EPDC_UPD_CORD_REG(base) ((base)->UPD_CORD) +#define EPDC_UPD_SIZE_REG(base) ((base)->UPD_SIZE) +#define EPDC_UPD_CTRL_REG(base) ((base)->UPD_CTRL) +#define EPDC_UPD_CTRL_SET_REG(base) ((base)->UPD_CTRL_SET) +#define EPDC_UPD_CTRL_CLR_REG(base) ((base)->UPD_CTRL_CLR) +#define EPDC_UPD_CTRL_TOG_REG(base) ((base)->UPD_CTRL_TOG) +#define EPDC_UPD_FIXED_REG(base) ((base)->UPD_FIXED) +#define EPDC_UPD_FIXED_SET_REG(base) ((base)->UPD_FIXED_SET) +#define EPDC_UPD_FIXED_CLR_REG(base) ((base)->UPD_FIXED_CLR) +#define EPDC_UPD_FIXED_TOG_REG(base) ((base)->UPD_FIXED_TOG) +#define EPDC_TEMP_REG(base) ((base)->TEMP) +#define EPDC_AUTOWV_LUT_REG(base) ((base)->AUTOWV_LUT) +#define EPDC_TCE_CTRL_REG(base) ((base)->TCE_CTRL) +#define EPDC_TCE_CTRL_SET_REG(base) ((base)->TCE_CTRL_SET) +#define EPDC_TCE_CTRL_CLR_REG(base) ((base)->TCE_CTRL_CLR) +#define EPDC_TCE_CTRL_TOG_REG(base) ((base)->TCE_CTRL_TOG) +#define EPDC_TCE_SDCFG_REG(base) ((base)->TCE_SDCFG) +#define EPDC_TCE_SDCFG_SET_REG(base) ((base)->TCE_SDCFG_SET) +#define EPDC_TCE_SDCFG_CLR_REG(base) ((base)->TCE_SDCFG_CLR) +#define EPDC_TCE_SDCFG_TOG_REG(base) ((base)->TCE_SDCFG_TOG) +#define EPDC_TCE_GDCFG_REG(base) ((base)->TCE_GDCFG) +#define EPDC_TCE_GDCFG_SET_REG(base) ((base)->TCE_GDCFG_SET) +#define EPDC_TCE_GDCFG_CLR_REG(base) ((base)->TCE_GDCFG_CLR) +#define EPDC_TCE_GDCFG_TOG_REG(base) ((base)->TCE_GDCFG_TOG) +#define EPDC_TCE_HSCAN1_REG(base) ((base)->TCE_HSCAN1) +#define EPDC_TCE_HSCAN1_SET_REG(base) ((base)->TCE_HSCAN1_SET) +#define EPDC_TCE_HSCAN1_CLR_REG(base) ((base)->TCE_HSCAN1_CLR) +#define EPDC_TCE_HSCAN1_TOG_REG(base) ((base)->TCE_HSCAN1_TOG) +#define EPDC_TCE_HSCAN2_REG(base) ((base)->TCE_HSCAN2) +#define EPDC_TCE_HSCAN2_SET_REG(base) ((base)->TCE_HSCAN2_SET) +#define EPDC_TCE_HSCAN2_CLR_REG(base) ((base)->TCE_HSCAN2_CLR) +#define EPDC_TCE_HSCAN2_TOG_REG(base) ((base)->TCE_HSCAN2_TOG) +#define EPDC_TCE_VSCAN_REG(base) ((base)->TCE_VSCAN) +#define EPDC_TCE_VSCAN_SET_REG(base) ((base)->TCE_VSCAN_SET) +#define EPDC_TCE_VSCAN_CLR_REG(base) ((base)->TCE_VSCAN_CLR) +#define EPDC_TCE_VSCAN_TOG_REG(base) ((base)->TCE_VSCAN_TOG) +#define EPDC_TCE_OE_REG(base) ((base)->TCE_OE) +#define EPDC_TCE_OE_SET_REG(base) ((base)->TCE_OE_SET) +#define EPDC_TCE_OE_CLR_REG(base) ((base)->TCE_OE_CLR) +#define EPDC_TCE_OE_TOG_REG(base) ((base)->TCE_OE_TOG) +#define EPDC_TCE_POLARITY_REG(base) ((base)->TCE_POLARITY) +#define EPDC_TCE_POLARITY_SET_REG(base) ((base)->TCE_POLARITY_SET) +#define EPDC_TCE_POLARITY_CLR_REG(base) ((base)->TCE_POLARITY_CLR) +#define EPDC_TCE_POLARITY_TOG_REG(base) ((base)->TCE_POLARITY_TOG) +#define EPDC_TCE_TIMING1_REG(base) ((base)->TCE_TIMING1) +#define EPDC_TCE_TIMING1_SET_REG(base) ((base)->TCE_TIMING1_SET) +#define EPDC_TCE_TIMING1_CLR_REG(base) ((base)->TCE_TIMING1_CLR) +#define EPDC_TCE_TIMING1_TOG_REG(base) ((base)->TCE_TIMING1_TOG) +#define EPDC_TCE_TIMING2_REG(base) ((base)->TCE_TIMING2) +#define EPDC_TCE_TIMING2_SET_REG(base) ((base)->TCE_TIMING2_SET) +#define EPDC_TCE_TIMING2_CLR_REG(base) ((base)->TCE_TIMING2_CLR) +#define EPDC_TCE_TIMING2_TOG_REG(base) ((base)->TCE_TIMING2_TOG) +#define EPDC_TCE_TIMING3_REG(base) ((base)->TCE_TIMING3) +#define EPDC_TCE_TIMING3_SET_REG(base) ((base)->TCE_TIMING3_SET) +#define EPDC_TCE_TIMING3_CLR_REG(base) ((base)->TCE_TIMING3_CLR) +#define EPDC_TCE_TIMING3_TOG_REG(base) ((base)->TCE_TIMING3_TOG) +#define EPDC_PIGEON_CTRL0_REG(base) ((base)->PIGEON_CTRL0) +#define EPDC_PIGEON_CTRL0_SET_REG(base) ((base)->PIGEON_CTRL0_SET) +#define EPDC_PIGEON_CTRL0_CLR_REG(base) ((base)->PIGEON_CTRL0_CLR) +#define EPDC_PIGEON_CTRL0_TOG_REG(base) ((base)->PIGEON_CTRL0_TOG) +#define EPDC_PIGEON_CTRL1_REG(base) ((base)->PIGEON_CTRL1) +#define EPDC_PIGEON_CTRL1_SET_REG(base) ((base)->PIGEON_CTRL1_SET) +#define EPDC_PIGEON_CTRL1_CLR_REG(base) ((base)->PIGEON_CTRL1_CLR) +#define EPDC_PIGEON_CTRL1_TOG_REG(base) ((base)->PIGEON_CTRL1_TOG) +#define EPDC_IRQ_MASK1_REG(base) ((base)->IRQ_MASK1) +#define EPDC_IRQ_MASK1_SET_REG(base) ((base)->IRQ_MASK1_SET) +#define EPDC_IRQ_MASK1_CLR_REG(base) ((base)->IRQ_MASK1_CLR) +#define EPDC_IRQ_MASK1_TOG_REG(base) ((base)->IRQ_MASK1_TOG) +#define EPDC_IRQ_MASK2_REG(base) ((base)->IRQ_MASK2) +#define EPDC_IRQ_MASK2_SET_REG(base) ((base)->IRQ_MASK2_SET) +#define EPDC_IRQ_MASK2_CLR_REG(base) ((base)->IRQ_MASK2_CLR) +#define EPDC_IRQ_MASK2_TOG_REG(base) ((base)->IRQ_MASK2_TOG) +#define EPDC_IRQ1_REG(base) ((base)->IRQ1) +#define EPDC_IRQ1_SET_REG(base) ((base)->IRQ1_SET) +#define EPDC_IRQ1_CLR_REG(base) ((base)->IRQ1_CLR) +#define EPDC_IRQ1_TOG_REG(base) ((base)->IRQ1_TOG) +#define EPDC_IRQ2_REG(base) ((base)->IRQ2) +#define EPDC_IRQ2_SET_REG(base) ((base)->IRQ2_SET) +#define EPDC_IRQ2_CLR_REG(base) ((base)->IRQ2_CLR) +#define EPDC_IRQ2_TOG_REG(base) ((base)->IRQ2_TOG) +#define EPDC_IRQ_MASK_REG(base) ((base)->IRQ_MASK) +#define EPDC_IRQ_MASK_SET_REG(base) ((base)->IRQ_MASK_SET) +#define EPDC_IRQ_MASK_CLR_REG(base) ((base)->IRQ_MASK_CLR) +#define EPDC_IRQ_MASK_TOG_REG(base) ((base)->IRQ_MASK_TOG) +#define EPDC_IRQ_REG(base) ((base)->IRQ) +#define EPDC_IRQ_SET_REG(base) ((base)->IRQ_SET) +#define EPDC_IRQ_CLR_REG(base) ((base)->IRQ_CLR) +#define EPDC_IRQ_TOG_REG(base) ((base)->IRQ_TOG) +#define EPDC_STATUS_LUTS1_REG(base) ((base)->STATUS_LUTS1) +#define EPDC_STATUS_LUTS1_SET_REG(base) ((base)->STATUS_LUTS1_SET) +#define EPDC_STATUS_LUTS1_CLR_REG(base) ((base)->STATUS_LUTS1_CLR) +#define EPDC_STATUS_LUTS1_TOG_REG(base) ((base)->STATUS_LUTS1_TOG) +#define EPDC_STATUS_LUTS2_REG(base) ((base)->STATUS_LUTS2) +#define EPDC_STATUS_LUTS2_SET_REG(base) ((base)->STATUS_LUTS2_SET) +#define EPDC_STATUS_LUTS2_CLR_REG(base) ((base)->STATUS_LUTS2_CLR) +#define EPDC_STATUS_LUTS2_TOG_REG(base) ((base)->STATUS_LUTS2_TOG) +#define EPDC_STATUS_NEXTLUT_REG(base) ((base)->STATUS_NEXTLUT) +#define EPDC_STATUS_COL1_REG(base) ((base)->STATUS_COL1) +#define EPDC_STATUS_COL1_SET_REG(base) ((base)->STATUS_COL1_SET) +#define EPDC_STATUS_COL1_CLR_REG(base) ((base)->STATUS_COL1_CLR) +#define EPDC_STATUS_COL1_TOG_REG(base) ((base)->STATUS_COL1_TOG) +#define EPDC_STATUS_COL2_REG(base) ((base)->STATUS_COL2) +#define EPDC_STATUS_COL2_SET_REG(base) ((base)->STATUS_COL2_SET) +#define EPDC_STATUS_COL2_CLR_REG(base) ((base)->STATUS_COL2_CLR) +#define EPDC_STATUS_COL2_TOG_REG(base) ((base)->STATUS_COL2_TOG) +#define EPDC_STATUS_REG(base) ((base)->STATUS) +#define EPDC_STATUS_SET_REG(base) ((base)->STATUS_SET) +#define EPDC_STATUS_CLR_REG(base) ((base)->STATUS_CLR) +#define EPDC_STATUS_TOG_REG(base) ((base)->STATUS_TOG) +#define EPDC_UPD_COL_CORD_REG(base) ((base)->UPD_COL_CORD) +#define EPDC_UPD_COL_SIZE_REG(base) ((base)->UPD_COL_SIZE) +#define EPDC_HIST1_PARAM_REG(base) ((base)->HIST1_PARAM) +#define EPDC_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) +#define EPDC_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) +#define EPDC_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) +#define EPDC_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) +#define EPDC_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) +#define EPDC_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) +#define EPDC_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) +#define EPDC_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) +#define EPDC_GPIO_REG(base) ((base)->GPIO) +#define EPDC_GPIO_SET_REG(base) ((base)->GPIO_SET) +#define EPDC_GPIO_CLR_REG(base) ((base)->GPIO_CLR) +#define EPDC_GPIO_TOG_REG(base) ((base)->GPIO_TOG) +#define EPDC_VERSION_REG(base) ((base)->VERSION) +#define EPDC_PIGEON_0_0_REG(base) ((base)->PIGEON_0_0) +#define EPDC_PIGEON_0_1_REG(base) ((base)->PIGEON_0_1) +#define EPDC_PIGEON_0_2_REG(base) ((base)->PIGEON_0_2) +#define EPDC_PIGEON_1_0_REG(base) ((base)->PIGEON_1_0) +#define EPDC_PIGEON_1_1_REG(base) ((base)->PIGEON_1_1) +#define EPDC_PIGEON_1_2_REG(base) ((base)->PIGEON_1_2) +#define EPDC_PIGEON_2_0_REG(base) ((base)->PIGEON_2_0) +#define EPDC_PIGEON_2_1_REG(base) ((base)->PIGEON_2_1) +#define EPDC_PIGEON_2_2_REG(base) ((base)->PIGEON_2_2) +#define EPDC_PIGEON_3_0_REG(base) ((base)->PIGEON_3_0) +#define EPDC_PIGEON_3_1_REG(base) ((base)->PIGEON_3_1) +#define EPDC_PIGEON_3_2_REG(base) ((base)->PIGEON_3_2) +#define EPDC_PIGEON_4_0_REG(base) ((base)->PIGEON_4_0) +#define EPDC_PIGEON_4_1_REG(base) ((base)->PIGEON_4_1) +#define EPDC_PIGEON_4_2_REG(base) ((base)->PIGEON_4_2) +#define EPDC_PIGEON_5_0_REG(base) ((base)->PIGEON_5_0) +#define EPDC_PIGEON_5_1_REG(base) ((base)->PIGEON_5_1) +#define EPDC_PIGEON_5_2_REG(base) ((base)->PIGEON_5_2) +#define EPDC_PIGEON_6_0_REG(base) ((base)->PIGEON_6_0) +#define EPDC_PIGEON_6_1_REG(base) ((base)->PIGEON_6_1) +#define EPDC_PIGEON_6_2_REG(base) ((base)->PIGEON_6_2) +#define EPDC_PIGEON_7_0_REG(base) ((base)->PIGEON_7_0) +#define EPDC_PIGEON_7_1_REG(base) ((base)->PIGEON_7_1) +#define EPDC_PIGEON_7_2_REG(base) ((base)->PIGEON_7_2) +#define EPDC_PIGEON_8_0_REG(base) ((base)->PIGEON_8_0) +#define EPDC_PIGEON_8_1_REG(base) ((base)->PIGEON_8_1) +#define EPDC_PIGEON_8_2_REG(base) ((base)->PIGEON_8_2) +#define EPDC_PIGEON_9_0_REG(base) ((base)->PIGEON_9_0) +#define EPDC_PIGEON_9_1_REG(base) ((base)->PIGEON_9_1) +#define EPDC_PIGEON_9_2_REG(base) ((base)->PIGEON_9_2) +#define EPDC_PIGEON_10_0_REG(base) ((base)->PIGEON_10_0) +#define EPDC_PIGEON_10_1_REG(base) ((base)->PIGEON_10_1) +#define EPDC_PIGEON_10_2_REG(base) ((base)->PIGEON_10_2) +#define EPDC_PIGEON_11_0_REG(base) ((base)->PIGEON_11_0) +#define EPDC_PIGEON_11_1_REG(base) ((base)->PIGEON_11_1) +#define EPDC_PIGEON_11_2_REG(base) ((base)->PIGEON_11_2) +#define EPDC_PIGEON_12_0_REG(base) ((base)->PIGEON_12_0) +#define EPDC_PIGEON_12_1_REG(base) ((base)->PIGEON_12_1) +#define EPDC_PIGEON_12_2_REG(base) ((base)->PIGEON_12_2) +#define EPDC_PIGEON_13_0_REG(base) ((base)->PIGEON_13_0) +#define EPDC_PIGEON_13_1_REG(base) ((base)->PIGEON_13_1) +#define EPDC_PIGEON_13_2_REG(base) ((base)->PIGEON_13_2) +#define EPDC_PIGEON_14_0_REG(base) ((base)->PIGEON_14_0) +#define EPDC_PIGEON_14_1_REG(base) ((base)->PIGEON_14_1) +#define EPDC_PIGEON_14_2_REG(base) ((base)->PIGEON_14_2) +#define EPDC_PIGEON_15_0_REG(base) ((base)->PIGEON_15_0) +#define EPDC_PIGEON_15_1_REG(base) ((base)->PIGEON_15_1) +#define EPDC_PIGEON_15_2_REG(base) ((base)->PIGEON_15_2) +#define EPDC_PIGEON_16_0_REG(base) ((base)->PIGEON_16_0) +#define EPDC_PIGEON_16_1_REG(base) ((base)->PIGEON_16_1) +#define EPDC_WB_ADDR_TCE_REG(base) ((base)->WB_ADDR_TCE) +#define EPDC_PIGEON_16_2_REG(base) ((base)->PIGEON_16_2) + +/*! + * @} + */ /* end of group EPDC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- EPDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPDC_Register_Masks EPDC Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EPDC_CTRL_BURST_LEN_8_MASK 0x1u +#define EPDC_CTRL_BURST_LEN_8_SHIFT 0 +#define EPDC_CTRL_LUT_DATA_SWIZZLE_MASK 0x30u +#define EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT 4 +#define EPDC_CTRL_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_LUT_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_UPD_DATA_SWIZZLE_MASK 0xC0u +#define EPDC_CTRL_UPD_DATA_SWIZZLE_SHIFT 6 +#define EPDC_CTRL_UPD_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_UPD_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_CLKGATE_MASK 0x40000000u +#define EPDC_CTRL_CLKGATE_SHIFT 30 +#define EPDC_CTRL_SFTRST_MASK 0x80000000u +#define EPDC_CTRL_SFTRST_SHIFT 31 +/* CTRL_SET Bit Fields */ +#define EPDC_CTRL_SET_BURST_LEN_8_MASK 0x1u +#define EPDC_CTRL_SET_BURST_LEN_8_SHIFT 0 +#define EPDC_CTRL_SET_LUT_DATA_SWIZZLE_MASK 0x30u +#define EPDC_CTRL_SET_LUT_DATA_SWIZZLE_SHIFT 4 +#define EPDC_CTRL_SET_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_SET_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_SET_LUT_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_SET_UPD_DATA_SWIZZLE_MASK 0xC0u +#define EPDC_CTRL_SET_UPD_DATA_SWIZZLE_SHIFT 6 +#define EPDC_CTRL_SET_UPD_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_SET_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_SET_UPD_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_SET_CLKGATE_MASK 0x40000000u +#define EPDC_CTRL_SET_CLKGATE_SHIFT 30 +#define EPDC_CTRL_SET_SFTRST_MASK 0x80000000u +#define EPDC_CTRL_SET_SFTRST_SHIFT 31 +/* CTRL_CLR Bit Fields */ +#define EPDC_CTRL_CLR_BURST_LEN_8_MASK 0x1u +#define EPDC_CTRL_CLR_BURST_LEN_8_SHIFT 0 +#define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_MASK 0x30u +#define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_SHIFT 4 +#define EPDC_CTRL_CLR_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_CLR_LUT_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_MASK 0xC0u +#define EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_SHIFT 6 +#define EPDC_CTRL_CLR_UPD_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_CLR_UPD_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_CLR_CLKGATE_MASK 0x40000000u +#define EPDC_CTRL_CLR_CLKGATE_SHIFT 30 +#define EPDC_CTRL_CLR_SFTRST_MASK 0x80000000u +#define EPDC_CTRL_CLR_SFTRST_SHIFT 31 +/* CTRL_TOG Bit Fields */ +#define EPDC_CTRL_TOG_BURST_LEN_8_MASK 0x1u +#define EPDC_CTRL_TOG_BURST_LEN_8_SHIFT 0 +#define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_MASK 0x30u +#define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_SHIFT 4 +#define EPDC_CTRL_TOG_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_TOG_LUT_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_MASK 0xC0u +#define EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_SHIFT 6 +#define EPDC_CTRL_TOG_UPD_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_SHIFT))&EPDC_CTRL_TOG_UPD_DATA_SWIZZLE_MASK) +#define EPDC_CTRL_TOG_CLKGATE_MASK 0x40000000u +#define EPDC_CTRL_TOG_CLKGATE_SHIFT 30 +#define EPDC_CTRL_TOG_SFTRST_MASK 0x80000000u +#define EPDC_CTRL_TOG_SFTRST_SHIFT 31 +/* WVADDR Bit Fields */ +#define EPDC_WVADDR_ADDR_MASK 0xFFFFFFFFu +#define EPDC_WVADDR_ADDR_SHIFT 0 +#define EPDC_WVADDR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WVADDR_ADDR_SHIFT))&EPDC_WVADDR_ADDR_MASK) +/* WB_ADDR Bit Fields */ +#define EPDC_WB_ADDR_ADDR_MASK 0xFFFFFFFFu +#define EPDC_WB_ADDR_ADDR_SHIFT 0 +#define EPDC_WB_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_ADDR_ADDR_SHIFT))&EPDC_WB_ADDR_ADDR_MASK) +/* RES Bit Fields */ +#define EPDC_RES_HORIZONTAL_MASK 0x1FFFu +#define EPDC_RES_HORIZONTAL_SHIFT 0 +#define EPDC_RES_HORIZONTAL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_RES_HORIZONTAL_SHIFT))&EPDC_RES_HORIZONTAL_MASK) +#define EPDC_RES_VERTICAL_MASK 0x1FFF0000u +#define EPDC_RES_VERTICAL_SHIFT 16 +#define EPDC_RES_VERTICAL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_RES_VERTICAL_SHIFT))&EPDC_RES_VERTICAL_MASK) +/* FORMAT Bit Fields */ +#define EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK 0x3u +#define EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT 0 +#define EPDC_FORMAT_TFT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_TFT_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK 0x700u +#define EPDC_FORMAT_BUF_PIXEL_FORMAT_SHIFT 8 +#define EPDC_FORMAT_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK 0xFF0000u +#define EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT 16 +#define EPDC_FORMAT_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK) +#define EPDC_FORMAT_BUF_PIXEL_SCALE_MASK 0x1000000u +#define EPDC_FORMAT_BUF_PIXEL_SCALE_SHIFT 24 +/* FORMAT_SET Bit Fields */ +#define EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_MASK 0x3u +#define EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_SHIFT 0 +#define EPDC_FORMAT_SET_TFT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_SET_TFT_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_MASK 0x700u +#define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_SHIFT 8 +#define EPDC_FORMAT_SET_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_SET_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_MASK 0xFF0000u +#define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_SHIFT 16 +#define EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_SET_DEFAULT_TFT_PIXEL_MASK) +#define EPDC_FORMAT_SET_BUF_PIXEL_SCALE_MASK 0x1000000u +#define EPDC_FORMAT_SET_BUF_PIXEL_SCALE_SHIFT 24 +/* FORMAT_CLR Bit Fields */ +#define EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_MASK 0x3u +#define EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_SHIFT 0 +#define EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_CLR_TFT_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_MASK 0x700u +#define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_SHIFT 8 +#define EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_CLR_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_MASK 0xFF0000u +#define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_SHIFT 16 +#define EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_CLR_DEFAULT_TFT_PIXEL_MASK) +#define EPDC_FORMAT_CLR_BUF_PIXEL_SCALE_MASK 0x1000000u +#define EPDC_FORMAT_CLR_BUF_PIXEL_SCALE_SHIFT 24 +/* FORMAT_TOG Bit Fields */ +#define EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_MASK 0x3u +#define EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_SHIFT 0 +#define EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_TOG_TFT_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_MASK 0x700u +#define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_SHIFT 8 +#define EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_SHIFT))&EPDC_FORMAT_TOG_BUF_PIXEL_FORMAT_MASK) +#define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_MASK 0xFF0000u +#define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_SHIFT 16 +#define EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_SHIFT))&EPDC_FORMAT_TOG_DEFAULT_TFT_PIXEL_MASK) +#define EPDC_FORMAT_TOG_BUF_PIXEL_SCALE_MASK 0x1000000u +#define EPDC_FORMAT_TOG_BUF_PIXEL_SCALE_SHIFT 24 +/* FIFOCTRL Bit Fields */ +#define EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK 0xFFu +#define EPDC_FIFOCTRL_FIFO_L_LEVEL_SHIFT 0 +#define EPDC_FIFOCTRL_FIFO_L_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK) +#define EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK 0xFF00u +#define EPDC_FIFOCTRL_FIFO_H_LEVEL_SHIFT 8 +#define EPDC_FIFOCTRL_FIFO_H_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK) +#define EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK 0xFF0000u +#define EPDC_FIFOCTRL_FIFO_INIT_LEVEL_SHIFT 16 +#define EPDC_FIFOCTRL_FIFO_INIT_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK) +#define EPDC_FIFOCTRL_ENABLE_PRIORITY_MASK 0x80000000u +#define EPDC_FIFOCTRL_ENABLE_PRIORITY_SHIFT 31 +/* FIFOCTRL_SET Bit Fields */ +#define EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_MASK 0xFFu +#define EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_SHIFT 0 +#define EPDC_FIFOCTRL_SET_FIFO_L_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_SET_FIFO_L_LEVEL_MASK) +#define EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_MASK 0xFF00u +#define EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_SHIFT 8 +#define EPDC_FIFOCTRL_SET_FIFO_H_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_SET_FIFO_H_LEVEL_MASK) +#define EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_MASK 0xFF0000u +#define EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_SHIFT 16 +#define EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_SET_FIFO_INIT_LEVEL_MASK) +#define EPDC_FIFOCTRL_SET_ENABLE_PRIORITY_MASK 0x80000000u +#define EPDC_FIFOCTRL_SET_ENABLE_PRIORITY_SHIFT 31 +/* FIFOCTRL_CLR Bit Fields */ +#define EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_MASK 0xFFu +#define EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_SHIFT 0 +#define EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_CLR_FIFO_L_LEVEL_MASK) +#define EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_MASK 0xFF00u +#define EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_SHIFT 8 +#define EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_CLR_FIFO_H_LEVEL_MASK) +#define EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_MASK 0xFF0000u +#define EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_SHIFT 16 +#define EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_CLR_FIFO_INIT_LEVEL_MASK) +#define EPDC_FIFOCTRL_CLR_ENABLE_PRIORITY_MASK 0x80000000u +#define EPDC_FIFOCTRL_CLR_ENABLE_PRIORITY_SHIFT 31 +/* FIFOCTRL_TOG Bit Fields */ +#define EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_MASK 0xFFu +#define EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_SHIFT 0 +#define EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_SHIFT))&EPDC_FIFOCTRL_TOG_FIFO_L_LEVEL_MASK) +#define EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_MASK 0xFF00u +#define EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_SHIFT 8 +#define EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_SHIFT))&EPDC_FIFOCTRL_TOG_FIFO_H_LEVEL_MASK) +#define EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_MASK 0xFF0000u +#define EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_SHIFT 16 +#define EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_SHIFT))&EPDC_FIFOCTRL_TOG_FIFO_INIT_LEVEL_MASK) +#define EPDC_FIFOCTRL_TOG_ENABLE_PRIORITY_MASK 0x80000000u +#define EPDC_FIFOCTRL_TOG_ENABLE_PRIORITY_SHIFT 31 +/* UPD_ADDR Bit Fields */ +#define EPDC_UPD_ADDR_ADDR_MASK 0xFFFFFFFFu +#define EPDC_UPD_ADDR_ADDR_SHIFT 0 +#define EPDC_UPD_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_ADDR_ADDR_SHIFT))&EPDC_UPD_ADDR_ADDR_MASK) +/* UPD_STRIDE Bit Fields */ +#define EPDC_UPD_STRIDE_STRIDE_MASK 0xFFFFFFFFu +#define EPDC_UPD_STRIDE_STRIDE_SHIFT 0 +#define EPDC_UPD_STRIDE_STRIDE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_STRIDE_STRIDE_SHIFT))&EPDC_UPD_STRIDE_STRIDE_MASK) +/* UPD_CORD Bit Fields */ +#define EPDC_UPD_CORD_XCORD_MASK 0x1FFFu +#define EPDC_UPD_CORD_XCORD_SHIFT 0 +#define EPDC_UPD_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CORD_XCORD_SHIFT))&EPDC_UPD_CORD_XCORD_MASK) +#define EPDC_UPD_CORD_YCORD_MASK 0x1FFF0000u +#define EPDC_UPD_CORD_YCORD_SHIFT 16 +#define EPDC_UPD_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CORD_YCORD_SHIFT))&EPDC_UPD_CORD_YCORD_MASK) +/* UPD_SIZE Bit Fields */ +#define EPDC_UPD_SIZE_WIDTH_MASK 0x1FFFu +#define EPDC_UPD_SIZE_WIDTH_SHIFT 0 +#define EPDC_UPD_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_SIZE_WIDTH_SHIFT))&EPDC_UPD_SIZE_WIDTH_MASK) +#define EPDC_UPD_SIZE_HEIGHT_MASK 0x1FFF0000u +#define EPDC_UPD_SIZE_HEIGHT_SHIFT 16 +#define EPDC_UPD_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_SIZE_HEIGHT_SHIFT))&EPDC_UPD_SIZE_HEIGHT_MASK) +/* UPD_CTRL Bit Fields */ +#define EPDC_UPD_CTRL_UPDATE_MODE_MASK 0x1u +#define EPDC_UPD_CTRL_UPDATE_MODE_SHIFT 0 +#define EPDC_UPD_CTRL_DRY_RUN_MASK 0x2u +#define EPDC_UPD_CTRL_DRY_RUN_SHIFT 1 +#define EPDC_UPD_CTRL_AUTOWV_MASK 0x4u +#define EPDC_UPD_CTRL_AUTOWV_SHIFT 2 +#define EPDC_UPD_CTRL_AUTOWV_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_NO_LUT_CANCEL_MASK 0x10u +#define EPDC_UPD_CTRL_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_WAVEFORM_MODE_MASK 0xFF00u +#define EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT 8 +#define EPDC_UPD_CTRL_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) +#define EPDC_UPD_CTRL_LUT_SEL_MASK 0x3F0000u +#define EPDC_UPD_CTRL_LUT_SEL_SHIFT 16 +#define EPDC_UPD_CTRL_LUT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_LUT_SEL_MASK) +#define EPDC_UPD_CTRL_USE_FIXED_MASK 0x80000000u +#define EPDC_UPD_CTRL_USE_FIXED_SHIFT 31 +/* UPD_CTRL_SET Bit Fields */ +#define EPDC_UPD_CTRL_SET_UPDATE_MODE_MASK 0x1u +#define EPDC_UPD_CTRL_SET_UPDATE_MODE_SHIFT 0 +#define EPDC_UPD_CTRL_SET_DRY_RUN_MASK 0x2u +#define EPDC_UPD_CTRL_SET_DRY_RUN_SHIFT 1 +#define EPDC_UPD_CTRL_SET_AUTOWV_MASK 0x4u +#define EPDC_UPD_CTRL_SET_AUTOWV_SHIFT 2 +#define EPDC_UPD_CTRL_SET_AUTOWV_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_SET_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_SET_NO_LUT_CANCEL_MASK 0x10u +#define EPDC_UPD_CTRL_SET_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_SET_WAVEFORM_MODE_MASK 0xFF00u +#define EPDC_UPD_CTRL_SET_WAVEFORM_MODE_SHIFT 8 +#define EPDC_UPD_CTRL_SET_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_SET_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_SET_WAVEFORM_MODE_MASK) +#define EPDC_UPD_CTRL_SET_LUT_SEL_MASK 0x3F0000u +#define EPDC_UPD_CTRL_SET_LUT_SEL_SHIFT 16 +#define EPDC_UPD_CTRL_SET_LUT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_SET_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_SET_LUT_SEL_MASK) +#define EPDC_UPD_CTRL_SET_USE_FIXED_MASK 0x80000000u +#define EPDC_UPD_CTRL_SET_USE_FIXED_SHIFT 31 +/* UPD_CTRL_CLR Bit Fields */ +#define EPDC_UPD_CTRL_CLR_UPDATE_MODE_MASK 0x1u +#define EPDC_UPD_CTRL_CLR_UPDATE_MODE_SHIFT 0 +#define EPDC_UPD_CTRL_CLR_DRY_RUN_MASK 0x2u +#define EPDC_UPD_CTRL_CLR_DRY_RUN_SHIFT 1 +#define EPDC_UPD_CTRL_CLR_AUTOWV_MASK 0x4u +#define EPDC_UPD_CTRL_CLR_AUTOWV_SHIFT 2 +#define EPDC_UPD_CTRL_CLR_AUTOWV_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_CLR_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_CLR_NO_LUT_CANCEL_MASK 0x10u +#define EPDC_UPD_CTRL_CLR_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_MASK 0xFF00u +#define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_SHIFT 8 +#define EPDC_UPD_CTRL_CLR_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_CLR_WAVEFORM_MODE_MASK) +#define EPDC_UPD_CTRL_CLR_LUT_SEL_MASK 0x3F0000u +#define EPDC_UPD_CTRL_CLR_LUT_SEL_SHIFT 16 +#define EPDC_UPD_CTRL_CLR_LUT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_CLR_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_CLR_LUT_SEL_MASK) +#define EPDC_UPD_CTRL_CLR_USE_FIXED_MASK 0x80000000u +#define EPDC_UPD_CTRL_CLR_USE_FIXED_SHIFT 31 +/* UPD_CTRL_TOG Bit Fields */ +#define EPDC_UPD_CTRL_TOG_UPDATE_MODE_MASK 0x1u +#define EPDC_UPD_CTRL_TOG_UPDATE_MODE_SHIFT 0 +#define EPDC_UPD_CTRL_TOG_DRY_RUN_MASK 0x2u +#define EPDC_UPD_CTRL_TOG_DRY_RUN_SHIFT 1 +#define EPDC_UPD_CTRL_TOG_AUTOWV_MASK 0x4u +#define EPDC_UPD_CTRL_TOG_AUTOWV_SHIFT 2 +#define EPDC_UPD_CTRL_TOG_AUTOWV_PAUSE_MASK 0x8u +#define EPDC_UPD_CTRL_TOG_AUTOWV_PAUSE_SHIFT 3 +#define EPDC_UPD_CTRL_TOG_NO_LUT_CANCEL_MASK 0x10u +#define EPDC_UPD_CTRL_TOG_NO_LUT_CANCEL_SHIFT 4 +#define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_MASK 0xFF00u +#define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_SHIFT 8 +#define EPDC_UPD_CTRL_TOG_WAVEFORM_MODE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_SHIFT))&EPDC_UPD_CTRL_TOG_WAVEFORM_MODE_MASK) +#define EPDC_UPD_CTRL_TOG_LUT_SEL_MASK 0x3F0000u +#define EPDC_UPD_CTRL_TOG_LUT_SEL_SHIFT 16 +#define EPDC_UPD_CTRL_TOG_LUT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_CTRL_TOG_LUT_SEL_SHIFT))&EPDC_UPD_CTRL_TOG_LUT_SEL_MASK) +#define EPDC_UPD_CTRL_TOG_USE_FIXED_MASK 0x80000000u +#define EPDC_UPD_CTRL_TOG_USE_FIXED_SHIFT 31 +/* UPD_FIXED Bit Fields */ +#define EPDC_UPD_FIXED_FIXCP_MASK 0xFFu +#define EPDC_UPD_FIXED_FIXCP_SHIFT 0 +#define EPDC_UPD_FIXED_FIXCP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_FIXCP_SHIFT))&EPDC_UPD_FIXED_FIXCP_MASK) +#define EPDC_UPD_FIXED_FIXNP_MASK 0xFF00u +#define EPDC_UPD_FIXED_FIXNP_SHIFT 8 +#define EPDC_UPD_FIXED_FIXNP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_FIXNP_SHIFT))&EPDC_UPD_FIXED_FIXNP_MASK) +#define EPDC_UPD_FIXED_FIXCP_EN_MASK 0x40000000u +#define EPDC_UPD_FIXED_FIXCP_EN_SHIFT 30 +#define EPDC_UPD_FIXED_FIXNP_EN_MASK 0x80000000u +#define EPDC_UPD_FIXED_FIXNP_EN_SHIFT 31 +/* UPD_FIXED_SET Bit Fields */ +#define EPDC_UPD_FIXED_SET_FIXCP_MASK 0xFFu +#define EPDC_UPD_FIXED_SET_FIXCP_SHIFT 0 +#define EPDC_UPD_FIXED_SET_FIXCP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_SET_FIXCP_SHIFT))&EPDC_UPD_FIXED_SET_FIXCP_MASK) +#define EPDC_UPD_FIXED_SET_FIXNP_MASK 0xFF00u +#define EPDC_UPD_FIXED_SET_FIXNP_SHIFT 8 +#define EPDC_UPD_FIXED_SET_FIXNP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_SET_FIXNP_SHIFT))&EPDC_UPD_FIXED_SET_FIXNP_MASK) +#define EPDC_UPD_FIXED_SET_FIXCP_EN_MASK 0x40000000u +#define EPDC_UPD_FIXED_SET_FIXCP_EN_SHIFT 30 +#define EPDC_UPD_FIXED_SET_FIXNP_EN_MASK 0x80000000u +#define EPDC_UPD_FIXED_SET_FIXNP_EN_SHIFT 31 +/* UPD_FIXED_CLR Bit Fields */ +#define EPDC_UPD_FIXED_CLR_FIXCP_MASK 0xFFu +#define EPDC_UPD_FIXED_CLR_FIXCP_SHIFT 0 +#define EPDC_UPD_FIXED_CLR_FIXCP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_CLR_FIXCP_SHIFT))&EPDC_UPD_FIXED_CLR_FIXCP_MASK) +#define EPDC_UPD_FIXED_CLR_FIXNP_MASK 0xFF00u +#define EPDC_UPD_FIXED_CLR_FIXNP_SHIFT 8 +#define EPDC_UPD_FIXED_CLR_FIXNP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_CLR_FIXNP_SHIFT))&EPDC_UPD_FIXED_CLR_FIXNP_MASK) +#define EPDC_UPD_FIXED_CLR_FIXCP_EN_MASK 0x40000000u +#define EPDC_UPD_FIXED_CLR_FIXCP_EN_SHIFT 30 +#define EPDC_UPD_FIXED_CLR_FIXNP_EN_MASK 0x80000000u +#define EPDC_UPD_FIXED_CLR_FIXNP_EN_SHIFT 31 +/* UPD_FIXED_TOG Bit Fields */ +#define EPDC_UPD_FIXED_TOG_FIXCP_MASK 0xFFu +#define EPDC_UPD_FIXED_TOG_FIXCP_SHIFT 0 +#define EPDC_UPD_FIXED_TOG_FIXCP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_TOG_FIXCP_SHIFT))&EPDC_UPD_FIXED_TOG_FIXCP_MASK) +#define EPDC_UPD_FIXED_TOG_FIXNP_MASK 0xFF00u +#define EPDC_UPD_FIXED_TOG_FIXNP_SHIFT 8 +#define EPDC_UPD_FIXED_TOG_FIXNP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_FIXED_TOG_FIXNP_SHIFT))&EPDC_UPD_FIXED_TOG_FIXNP_MASK) +#define EPDC_UPD_FIXED_TOG_FIXCP_EN_MASK 0x40000000u +#define EPDC_UPD_FIXED_TOG_FIXCP_EN_SHIFT 30 +#define EPDC_UPD_FIXED_TOG_FIXNP_EN_MASK 0x80000000u +#define EPDC_UPD_FIXED_TOG_FIXNP_EN_SHIFT 31 +/* TEMP Bit Fields */ +#define EPDC_TEMP_TEMPERATURE_MASK 0xFFFFFFFFu +#define EPDC_TEMP_TEMPERATURE_SHIFT 0 +#define EPDC_TEMP_TEMPERATURE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TEMP_TEMPERATURE_SHIFT))&EPDC_TEMP_TEMPERATURE_MASK) +/* AUTOWV_LUT Bit Fields */ +#define EPDC_AUTOWV_LUT_ADDR_MASK 0x7u +#define EPDC_AUTOWV_LUT_ADDR_SHIFT 0 +#define EPDC_AUTOWV_LUT_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_AUTOWV_LUT_ADDR_SHIFT))&EPDC_AUTOWV_LUT_ADDR_MASK) +#define EPDC_AUTOWV_LUT_DATA_MASK 0xFF0000u +#define EPDC_AUTOWV_LUT_DATA_SHIFT 16 +#define EPDC_AUTOWV_LUT_DATA(x) (((uint32_t)(((uint32_t)(x))<<EPDC_AUTOWV_LUT_DATA_SHIFT))&EPDC_AUTOWV_LUT_DATA_MASK) +/* TCE_CTRL Bit Fields */ +#define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK 0x3u +#define EPDC_TCE_CTRL_PIXELS_PER_SDCLK_SHIFT 0 +#define EPDC_TCE_CTRL_PIXELS_PER_SDCLK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_PIXELS_PER_SDCLK_MASK) +#define EPDC_TCE_CTRL_SDDO_WIDTH_MASK 0x4u +#define EPDC_TCE_CTRL_SDDO_WIDTH_SHIFT 2 +#define EPDC_TCE_CTRL_DUAL_SCAN_MASK 0x8u +#define EPDC_TCE_CTRL_DUAL_SCAN_SHIFT 3 +#define EPDC_TCE_CTRL_SCAN_DIR_0_MASK 0x10u +#define EPDC_TCE_CTRL_SCAN_DIR_0_SHIFT 4 +#define EPDC_TCE_CTRL_SCAN_DIR_1_MASK 0x20u +#define EPDC_TCE_CTRL_SCAN_DIR_1_SHIFT 5 +#define EPDC_TCE_CTRL_LVDS_MODE_MASK 0x40u +#define EPDC_TCE_CTRL_LVDS_MODE_SHIFT 6 +#define EPDC_TCE_CTRL_LVDS_MODE_CE_MASK 0x80u +#define EPDC_TCE_CTRL_LVDS_MODE_CE_SHIFT 7 +#define EPDC_TCE_CTRL_DDR_MODE_MASK 0x100u +#define EPDC_TCE_CTRL_DDR_MODE_SHIFT 8 +#define EPDC_TCE_CTRL_VCOM_MODE_MASK 0x200u +#define EPDC_TCE_CTRL_VCOM_MODE_SHIFT 9 +#define EPDC_TCE_CTRL_VCOM_VAL_MASK 0xC00u +#define EPDC_TCE_CTRL_VCOM_VAL_SHIFT 10 +#define EPDC_TCE_CTRL_VCOM_VAL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_VCOM_VAL_MASK) +#define EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK 0x1FF0000u +#define EPDC_TCE_CTRL_VSCAN_HOLDOFF_SHIFT 16 +#define EPDC_TCE_CTRL_VSCAN_HOLDOFF(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK) +/* TCE_CTRL_SET Bit Fields */ +#define EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_MASK 0x3u +#define EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_SHIFT 0 +#define EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_SET_PIXELS_PER_SDCLK_MASK) +#define EPDC_TCE_CTRL_SET_SDDO_WIDTH_MASK 0x4u +#define EPDC_TCE_CTRL_SET_SDDO_WIDTH_SHIFT 2 +#define EPDC_TCE_CTRL_SET_DUAL_SCAN_MASK 0x8u +#define EPDC_TCE_CTRL_SET_DUAL_SCAN_SHIFT 3 +#define EPDC_TCE_CTRL_SET_SCAN_DIR_0_MASK 0x10u +#define EPDC_TCE_CTRL_SET_SCAN_DIR_0_SHIFT 4 +#define EPDC_TCE_CTRL_SET_SCAN_DIR_1_MASK 0x20u +#define EPDC_TCE_CTRL_SET_SCAN_DIR_1_SHIFT 5 +#define EPDC_TCE_CTRL_SET_LVDS_MODE_MASK 0x40u +#define EPDC_TCE_CTRL_SET_LVDS_MODE_SHIFT 6 +#define EPDC_TCE_CTRL_SET_LVDS_MODE_CE_MASK 0x80u +#define EPDC_TCE_CTRL_SET_LVDS_MODE_CE_SHIFT 7 +#define EPDC_TCE_CTRL_SET_DDR_MODE_MASK 0x100u +#define EPDC_TCE_CTRL_SET_DDR_MODE_SHIFT 8 +#define EPDC_TCE_CTRL_SET_VCOM_MODE_MASK 0x200u +#define EPDC_TCE_CTRL_SET_VCOM_MODE_SHIFT 9 +#define EPDC_TCE_CTRL_SET_VCOM_VAL_MASK 0xC00u +#define EPDC_TCE_CTRL_SET_VCOM_VAL_SHIFT 10 +#define EPDC_TCE_CTRL_SET_VCOM_VAL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_SET_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_SET_VCOM_VAL_MASK) +#define EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_MASK 0x1FF0000u +#define EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_SHIFT 16 +#define EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_SET_VSCAN_HOLDOFF_MASK) +/* TCE_CTRL_CLR Bit Fields */ +#define EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_MASK 0x3u +#define EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_SHIFT 0 +#define EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_CLR_PIXELS_PER_SDCLK_MASK) +#define EPDC_TCE_CTRL_CLR_SDDO_WIDTH_MASK 0x4u +#define EPDC_TCE_CTRL_CLR_SDDO_WIDTH_SHIFT 2 +#define EPDC_TCE_CTRL_CLR_DUAL_SCAN_MASK 0x8u +#define EPDC_TCE_CTRL_CLR_DUAL_SCAN_SHIFT 3 +#define EPDC_TCE_CTRL_CLR_SCAN_DIR_0_MASK 0x10u +#define EPDC_TCE_CTRL_CLR_SCAN_DIR_0_SHIFT 4 +#define EPDC_TCE_CTRL_CLR_SCAN_DIR_1_MASK 0x20u +#define EPDC_TCE_CTRL_CLR_SCAN_DIR_1_SHIFT 5 +#define EPDC_TCE_CTRL_CLR_LVDS_MODE_MASK 0x40u +#define EPDC_TCE_CTRL_CLR_LVDS_MODE_SHIFT 6 +#define EPDC_TCE_CTRL_CLR_LVDS_MODE_CE_MASK 0x80u +#define EPDC_TCE_CTRL_CLR_LVDS_MODE_CE_SHIFT 7 +#define EPDC_TCE_CTRL_CLR_DDR_MODE_MASK 0x100u +#define EPDC_TCE_CTRL_CLR_DDR_MODE_SHIFT 8 +#define EPDC_TCE_CTRL_CLR_VCOM_MODE_MASK 0x200u +#define EPDC_TCE_CTRL_CLR_VCOM_MODE_SHIFT 9 +#define EPDC_TCE_CTRL_CLR_VCOM_VAL_MASK 0xC00u +#define EPDC_TCE_CTRL_CLR_VCOM_VAL_SHIFT 10 +#define EPDC_TCE_CTRL_CLR_VCOM_VAL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_CLR_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_CLR_VCOM_VAL_MASK) +#define EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_MASK 0x1FF0000u +#define EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_SHIFT 16 +#define EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_CLR_VSCAN_HOLDOFF_MASK) +/* TCE_CTRL_TOG Bit Fields */ +#define EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_MASK 0x3u +#define EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_SHIFT 0 +#define EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_SHIFT))&EPDC_TCE_CTRL_TOG_PIXELS_PER_SDCLK_MASK) +#define EPDC_TCE_CTRL_TOG_SDDO_WIDTH_MASK 0x4u +#define EPDC_TCE_CTRL_TOG_SDDO_WIDTH_SHIFT 2 +#define EPDC_TCE_CTRL_TOG_DUAL_SCAN_MASK 0x8u +#define EPDC_TCE_CTRL_TOG_DUAL_SCAN_SHIFT 3 +#define EPDC_TCE_CTRL_TOG_SCAN_DIR_0_MASK 0x10u +#define EPDC_TCE_CTRL_TOG_SCAN_DIR_0_SHIFT 4 +#define EPDC_TCE_CTRL_TOG_SCAN_DIR_1_MASK 0x20u +#define EPDC_TCE_CTRL_TOG_SCAN_DIR_1_SHIFT 5 +#define EPDC_TCE_CTRL_TOG_LVDS_MODE_MASK 0x40u +#define EPDC_TCE_CTRL_TOG_LVDS_MODE_SHIFT 6 +#define EPDC_TCE_CTRL_TOG_LVDS_MODE_CE_MASK 0x80u +#define EPDC_TCE_CTRL_TOG_LVDS_MODE_CE_SHIFT 7 +#define EPDC_TCE_CTRL_TOG_DDR_MODE_MASK 0x100u +#define EPDC_TCE_CTRL_TOG_DDR_MODE_SHIFT 8 +#define EPDC_TCE_CTRL_TOG_VCOM_MODE_MASK 0x200u +#define EPDC_TCE_CTRL_TOG_VCOM_MODE_SHIFT 9 +#define EPDC_TCE_CTRL_TOG_VCOM_VAL_MASK 0xC00u +#define EPDC_TCE_CTRL_TOG_VCOM_VAL_SHIFT 10 +#define EPDC_TCE_CTRL_TOG_VCOM_VAL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_TOG_VCOM_VAL_SHIFT))&EPDC_TCE_CTRL_TOG_VCOM_VAL_MASK) +#define EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_MASK 0x1FF0000u +#define EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_SHIFT 16 +#define EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_SHIFT))&EPDC_TCE_CTRL_TOG_VSCAN_HOLDOFF_MASK) +/* TCE_SDCFG Bit Fields */ +#define EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK 0x1FFFu +#define EPDC_TCE_SDCFG_PIXELS_PER_CE_SHIFT 0 +#define EPDC_TCE_SDCFG_PIXELS_PER_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK) +#define EPDC_TCE_SDCFG_SDDO_INVERT_MASK 0x2000u +#define EPDC_TCE_SDCFG_SDDO_INVERT_SHIFT 13 +#define EPDC_TCE_SDCFG_SDDO_REFORMAT_MASK 0xC000u +#define EPDC_TCE_SDCFG_SDDO_REFORMAT_SHIFT 14 +#define EPDC_TCE_SDCFG_SDDO_REFORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_SDDO_REFORMAT_MASK) +#define EPDC_TCE_SDCFG_NUM_CE_MASK 0xF0000u +#define EPDC_TCE_SDCFG_NUM_CE_SHIFT 16 +#define EPDC_TCE_SDCFG_NUM_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_NUM_CE_MASK) +#define EPDC_TCE_SDCFG_SDSHR_MASK 0x100000u +#define EPDC_TCE_SDCFG_SDSHR_SHIFT 20 +#define EPDC_TCE_SDCFG_SDCLK_HOLD_MASK 0x200000u +#define EPDC_TCE_SDCFG_SDCLK_HOLD_SHIFT 21 +/* TCE_SDCFG_SET Bit Fields */ +#define EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_MASK 0x1FFFu +#define EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_SHIFT 0 +#define EPDC_TCE_SDCFG_SET_PIXELS_PER_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_SET_PIXELS_PER_CE_MASK) +#define EPDC_TCE_SDCFG_SET_SDDO_INVERT_MASK 0x2000u +#define EPDC_TCE_SDCFG_SET_SDDO_INVERT_SHIFT 13 +#define EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_MASK 0xC000u +#define EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_SHIFT 14 +#define EPDC_TCE_SDCFG_SET_SDDO_REFORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_SET_SDDO_REFORMAT_MASK) +#define EPDC_TCE_SDCFG_SET_NUM_CE_MASK 0xF0000u +#define EPDC_TCE_SDCFG_SET_NUM_CE_SHIFT 16 +#define EPDC_TCE_SDCFG_SET_NUM_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_SET_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_SET_NUM_CE_MASK) +#define EPDC_TCE_SDCFG_SET_SDSHR_MASK 0x100000u +#define EPDC_TCE_SDCFG_SET_SDSHR_SHIFT 20 +#define EPDC_TCE_SDCFG_SET_SDCLK_HOLD_MASK 0x200000u +#define EPDC_TCE_SDCFG_SET_SDCLK_HOLD_SHIFT 21 +/* TCE_SDCFG_CLR Bit Fields */ +#define EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_MASK 0x1FFFu +#define EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_SHIFT 0 +#define EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_CLR_PIXELS_PER_CE_MASK) +#define EPDC_TCE_SDCFG_CLR_SDDO_INVERT_MASK 0x2000u +#define EPDC_TCE_SDCFG_CLR_SDDO_INVERT_SHIFT 13 +#define EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_MASK 0xC000u +#define EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_SHIFT 14 +#define EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_CLR_SDDO_REFORMAT_MASK) +#define EPDC_TCE_SDCFG_CLR_NUM_CE_MASK 0xF0000u +#define EPDC_TCE_SDCFG_CLR_NUM_CE_SHIFT 16 +#define EPDC_TCE_SDCFG_CLR_NUM_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_CLR_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_CLR_NUM_CE_MASK) +#define EPDC_TCE_SDCFG_CLR_SDSHR_MASK 0x100000u +#define EPDC_TCE_SDCFG_CLR_SDSHR_SHIFT 20 +#define EPDC_TCE_SDCFG_CLR_SDCLK_HOLD_MASK 0x200000u +#define EPDC_TCE_SDCFG_CLR_SDCLK_HOLD_SHIFT 21 +/* TCE_SDCFG_TOG Bit Fields */ +#define EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_MASK 0x1FFFu +#define EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_SHIFT 0 +#define EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_SHIFT))&EPDC_TCE_SDCFG_TOG_PIXELS_PER_CE_MASK) +#define EPDC_TCE_SDCFG_TOG_SDDO_INVERT_MASK 0x2000u +#define EPDC_TCE_SDCFG_TOG_SDDO_INVERT_SHIFT 13 +#define EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_MASK 0xC000u +#define EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_SHIFT 14 +#define EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_SHIFT))&EPDC_TCE_SDCFG_TOG_SDDO_REFORMAT_MASK) +#define EPDC_TCE_SDCFG_TOG_NUM_CE_MASK 0xF0000u +#define EPDC_TCE_SDCFG_TOG_NUM_CE_SHIFT 16 +#define EPDC_TCE_SDCFG_TOG_NUM_CE(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_SDCFG_TOG_NUM_CE_SHIFT))&EPDC_TCE_SDCFG_TOG_NUM_CE_MASK) +#define EPDC_TCE_SDCFG_TOG_SDSHR_MASK 0x100000u +#define EPDC_TCE_SDCFG_TOG_SDSHR_SHIFT 20 +#define EPDC_TCE_SDCFG_TOG_SDCLK_HOLD_MASK 0x200000u +#define EPDC_TCE_SDCFG_TOG_SDCLK_HOLD_SHIFT 21 +/* TCE_GDCFG Bit Fields */ +#define EPDC_TCE_GDCFG_GDSP_MODE_MASK 0x1u +#define EPDC_TCE_GDCFG_GDSP_MODE_SHIFT 0 +#define EPDC_TCE_GDCFG_GDOE_MODE_MASK 0x2u +#define EPDC_TCE_GDCFG_GDOE_MODE_SHIFT 1 +#define EPDC_TCE_GDCFG_GDRL_MASK 0x10u +#define EPDC_TCE_GDCFG_GDRL_SHIFT 4 +#define EPDC_TCE_GDCFG_PERIOD_VSCAN_MASK 0xFFFF0000u +#define EPDC_TCE_GDCFG_PERIOD_VSCAN_SHIFT 16 +#define EPDC_TCE_GDCFG_PERIOD_VSCAN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_PERIOD_VSCAN_MASK) +/* TCE_GDCFG_SET Bit Fields */ +#define EPDC_TCE_GDCFG_SET_GDSP_MODE_MASK 0x1u +#define EPDC_TCE_GDCFG_SET_GDSP_MODE_SHIFT 0 +#define EPDC_TCE_GDCFG_SET_GDOE_MODE_MASK 0x2u +#define EPDC_TCE_GDCFG_SET_GDOE_MODE_SHIFT 1 +#define EPDC_TCE_GDCFG_SET_GDRL_MASK 0x10u +#define EPDC_TCE_GDCFG_SET_GDRL_SHIFT 4 +#define EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_MASK 0xFFFF0000u +#define EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_SHIFT 16 +#define EPDC_TCE_GDCFG_SET_PERIOD_VSCAN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_SET_PERIOD_VSCAN_MASK) +/* TCE_GDCFG_CLR Bit Fields */ +#define EPDC_TCE_GDCFG_CLR_GDSP_MODE_MASK 0x1u +#define EPDC_TCE_GDCFG_CLR_GDSP_MODE_SHIFT 0 +#define EPDC_TCE_GDCFG_CLR_GDOE_MODE_MASK 0x2u +#define EPDC_TCE_GDCFG_CLR_GDOE_MODE_SHIFT 1 +#define EPDC_TCE_GDCFG_CLR_GDRL_MASK 0x10u +#define EPDC_TCE_GDCFG_CLR_GDRL_SHIFT 4 +#define EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_MASK 0xFFFF0000u +#define EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_SHIFT 16 +#define EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_CLR_PERIOD_VSCAN_MASK) +/* TCE_GDCFG_TOG Bit Fields */ +#define EPDC_TCE_GDCFG_TOG_GDSP_MODE_MASK 0x1u +#define EPDC_TCE_GDCFG_TOG_GDSP_MODE_SHIFT 0 +#define EPDC_TCE_GDCFG_TOG_GDOE_MODE_MASK 0x2u +#define EPDC_TCE_GDCFG_TOG_GDOE_MODE_SHIFT 1 +#define EPDC_TCE_GDCFG_TOG_GDRL_MASK 0x10u +#define EPDC_TCE_GDCFG_TOG_GDRL_SHIFT 4 +#define EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_MASK 0xFFFF0000u +#define EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_SHIFT 16 +#define EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_SHIFT))&EPDC_TCE_GDCFG_TOG_PERIOD_VSCAN_MASK) +/* TCE_HSCAN1 Bit Fields */ +#define EPDC_TCE_HSCAN1_LINE_SYNC_MASK 0xFFFu +#define EPDC_TCE_HSCAN1_LINE_SYNC_SHIFT 0 +#define EPDC_TCE_HSCAN1_LINE_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_LINE_SYNC_MASK) +#define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_SHIFT 16 +#define EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK) +/* TCE_HSCAN1_SET Bit Fields */ +#define EPDC_TCE_HSCAN1_SET_LINE_SYNC_MASK 0xFFFu +#define EPDC_TCE_HSCAN1_SET_LINE_SYNC_SHIFT 0 +#define EPDC_TCE_HSCAN1_SET_LINE_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_SET_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_SET_LINE_SYNC_MASK) +#define EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_SHIFT 16 +#define EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_SET_LINE_SYNC_WIDTH_MASK) +/* TCE_HSCAN1_CLR Bit Fields */ +#define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_MASK 0xFFFu +#define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_SHIFT 0 +#define EPDC_TCE_HSCAN1_CLR_LINE_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_CLR_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_CLR_LINE_SYNC_MASK) +#define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_SHIFT 16 +#define EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_CLR_LINE_SYNC_WIDTH_MASK) +/* TCE_HSCAN1_TOG Bit Fields */ +#define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_MASK 0xFFFu +#define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_SHIFT 0 +#define EPDC_TCE_HSCAN1_TOG_LINE_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_TOG_LINE_SYNC_SHIFT))&EPDC_TCE_HSCAN1_TOG_LINE_SYNC_MASK) +#define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_SHIFT 16 +#define EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_SHIFT))&EPDC_TCE_HSCAN1_TOG_LINE_SYNC_WIDTH_MASK) +/* TCE_HSCAN2 Bit Fields */ +#define EPDC_TCE_HSCAN2_LINE_BEGIN_MASK 0xFFFu +#define EPDC_TCE_HSCAN2_LINE_BEGIN_SHIFT 0 +#define EPDC_TCE_HSCAN2_LINE_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_LINE_BEGIN_MASK) +#define EPDC_TCE_HSCAN2_LINE_END_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN2_LINE_END_SHIFT 16 +#define EPDC_TCE_HSCAN2_LINE_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_LINE_END_MASK) +/* TCE_HSCAN2_SET Bit Fields */ +#define EPDC_TCE_HSCAN2_SET_LINE_BEGIN_MASK 0xFFFu +#define EPDC_TCE_HSCAN2_SET_LINE_BEGIN_SHIFT 0 +#define EPDC_TCE_HSCAN2_SET_LINE_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_SET_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_SET_LINE_BEGIN_MASK) +#define EPDC_TCE_HSCAN2_SET_LINE_END_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN2_SET_LINE_END_SHIFT 16 +#define EPDC_TCE_HSCAN2_SET_LINE_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_SET_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_SET_LINE_END_MASK) +/* TCE_HSCAN2_CLR Bit Fields */ +#define EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_MASK 0xFFFu +#define EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_SHIFT 0 +#define EPDC_TCE_HSCAN2_CLR_LINE_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_CLR_LINE_BEGIN_MASK) +#define EPDC_TCE_HSCAN2_CLR_LINE_END_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN2_CLR_LINE_END_SHIFT 16 +#define EPDC_TCE_HSCAN2_CLR_LINE_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_CLR_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_CLR_LINE_END_MASK) +/* TCE_HSCAN2_TOG Bit Fields */ +#define EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_MASK 0xFFFu +#define EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_SHIFT 0 +#define EPDC_TCE_HSCAN2_TOG_LINE_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_SHIFT))&EPDC_TCE_HSCAN2_TOG_LINE_BEGIN_MASK) +#define EPDC_TCE_HSCAN2_TOG_LINE_END_MASK 0xFFF0000u +#define EPDC_TCE_HSCAN2_TOG_LINE_END_SHIFT 16 +#define EPDC_TCE_HSCAN2_TOG_LINE_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_HSCAN2_TOG_LINE_END_SHIFT))&EPDC_TCE_HSCAN2_TOG_LINE_END_MASK) +/* TCE_VSCAN Bit Fields */ +#define EPDC_TCE_VSCAN_FRAME_SYNC_MASK 0xFFu +#define EPDC_TCE_VSCAN_FRAME_SYNC_SHIFT 0 +#define EPDC_TCE_VSCAN_FRAME_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_FRAME_SYNC_MASK) +#define EPDC_TCE_VSCAN_FRAME_BEGIN_MASK 0xFF00u +#define EPDC_TCE_VSCAN_FRAME_BEGIN_SHIFT 8 +#define EPDC_TCE_VSCAN_FRAME_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_FRAME_BEGIN_MASK) +#define EPDC_TCE_VSCAN_FRAME_END_MASK 0xFF0000u +#define EPDC_TCE_VSCAN_FRAME_END_SHIFT 16 +#define EPDC_TCE_VSCAN_FRAME_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_FRAME_END_MASK) +/* TCE_VSCAN_SET Bit Fields */ +#define EPDC_TCE_VSCAN_SET_FRAME_SYNC_MASK 0xFFu +#define EPDC_TCE_VSCAN_SET_FRAME_SYNC_SHIFT 0 +#define EPDC_TCE_VSCAN_SET_FRAME_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_SET_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_SET_FRAME_SYNC_MASK) +#define EPDC_TCE_VSCAN_SET_FRAME_BEGIN_MASK 0xFF00u +#define EPDC_TCE_VSCAN_SET_FRAME_BEGIN_SHIFT 8 +#define EPDC_TCE_VSCAN_SET_FRAME_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_SET_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_SET_FRAME_BEGIN_MASK) +#define EPDC_TCE_VSCAN_SET_FRAME_END_MASK 0xFF0000u +#define EPDC_TCE_VSCAN_SET_FRAME_END_SHIFT 16 +#define EPDC_TCE_VSCAN_SET_FRAME_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_SET_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_SET_FRAME_END_MASK) +/* TCE_VSCAN_CLR Bit Fields */ +#define EPDC_TCE_VSCAN_CLR_FRAME_SYNC_MASK 0xFFu +#define EPDC_TCE_VSCAN_CLR_FRAME_SYNC_SHIFT 0 +#define EPDC_TCE_VSCAN_CLR_FRAME_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_CLR_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_CLR_FRAME_SYNC_MASK) +#define EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_MASK 0xFF00u +#define EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_SHIFT 8 +#define EPDC_TCE_VSCAN_CLR_FRAME_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_CLR_FRAME_BEGIN_MASK) +#define EPDC_TCE_VSCAN_CLR_FRAME_END_MASK 0xFF0000u +#define EPDC_TCE_VSCAN_CLR_FRAME_END_SHIFT 16 +#define EPDC_TCE_VSCAN_CLR_FRAME_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_CLR_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_CLR_FRAME_END_MASK) +/* TCE_VSCAN_TOG Bit Fields */ +#define EPDC_TCE_VSCAN_TOG_FRAME_SYNC_MASK 0xFFu +#define EPDC_TCE_VSCAN_TOG_FRAME_SYNC_SHIFT 0 +#define EPDC_TCE_VSCAN_TOG_FRAME_SYNC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_TOG_FRAME_SYNC_SHIFT))&EPDC_TCE_VSCAN_TOG_FRAME_SYNC_MASK) +#define EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_MASK 0xFF00u +#define EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_SHIFT 8 +#define EPDC_TCE_VSCAN_TOG_FRAME_BEGIN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_SHIFT))&EPDC_TCE_VSCAN_TOG_FRAME_BEGIN_MASK) +#define EPDC_TCE_VSCAN_TOG_FRAME_END_MASK 0xFF0000u +#define EPDC_TCE_VSCAN_TOG_FRAME_END_SHIFT 16 +#define EPDC_TCE_VSCAN_TOG_FRAME_END(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_VSCAN_TOG_FRAME_END_SHIFT))&EPDC_TCE_VSCAN_TOG_FRAME_END_MASK) +/* TCE_OE Bit Fields */ +#define EPDC_TCE_OE_SDOEZ_DLY_MASK 0xFFu +#define EPDC_TCE_OE_SDOEZ_DLY_SHIFT 0 +#define EPDC_TCE_OE_SDOEZ_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_SDOEZ_DLY_MASK) +#define EPDC_TCE_OE_SDOEZ_WIDTH_MASK 0xFF00u +#define EPDC_TCE_OE_SDOEZ_WIDTH_SHIFT 8 +#define EPDC_TCE_OE_SDOEZ_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_SDOEZ_WIDTH_MASK) +#define EPDC_TCE_OE_SDOED_DLY_MASK 0xFF0000u +#define EPDC_TCE_OE_SDOED_DLY_SHIFT 16 +#define EPDC_TCE_OE_SDOED_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOED_DLY_SHIFT))&EPDC_TCE_OE_SDOED_DLY_MASK) +#define EPDC_TCE_OE_SDOED_WIDTH_MASK 0xFF000000u +#define EPDC_TCE_OE_SDOED_WIDTH_SHIFT 24 +#define EPDC_TCE_OE_SDOED_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_SDOED_WIDTH_MASK) +/* TCE_OE_SET Bit Fields */ +#define EPDC_TCE_OE_SET_SDOEZ_DLY_MASK 0xFFu +#define EPDC_TCE_OE_SET_SDOEZ_DLY_SHIFT 0 +#define EPDC_TCE_OE_SET_SDOEZ_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_SET_SDOEZ_DLY_MASK) +#define EPDC_TCE_OE_SET_SDOEZ_WIDTH_MASK 0xFF00u +#define EPDC_TCE_OE_SET_SDOEZ_WIDTH_SHIFT 8 +#define EPDC_TCE_OE_SET_SDOEZ_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_SET_SDOEZ_WIDTH_MASK) +#define EPDC_TCE_OE_SET_SDOED_DLY_MASK 0xFF0000u +#define EPDC_TCE_OE_SET_SDOED_DLY_SHIFT 16 +#define EPDC_TCE_OE_SET_SDOED_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOED_DLY_SHIFT))&EPDC_TCE_OE_SET_SDOED_DLY_MASK) +#define EPDC_TCE_OE_SET_SDOED_WIDTH_MASK 0xFF000000u +#define EPDC_TCE_OE_SET_SDOED_WIDTH_SHIFT 24 +#define EPDC_TCE_OE_SET_SDOED_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_SET_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_SET_SDOED_WIDTH_MASK) +/* TCE_OE_CLR Bit Fields */ +#define EPDC_TCE_OE_CLR_SDOEZ_DLY_MASK 0xFFu +#define EPDC_TCE_OE_CLR_SDOEZ_DLY_SHIFT 0 +#define EPDC_TCE_OE_CLR_SDOEZ_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_CLR_SDOEZ_DLY_MASK) +#define EPDC_TCE_OE_CLR_SDOEZ_WIDTH_MASK 0xFF00u +#define EPDC_TCE_OE_CLR_SDOEZ_WIDTH_SHIFT 8 +#define EPDC_TCE_OE_CLR_SDOEZ_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_CLR_SDOEZ_WIDTH_MASK) +#define EPDC_TCE_OE_CLR_SDOED_DLY_MASK 0xFF0000u +#define EPDC_TCE_OE_CLR_SDOED_DLY_SHIFT 16 +#define EPDC_TCE_OE_CLR_SDOED_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOED_DLY_SHIFT))&EPDC_TCE_OE_CLR_SDOED_DLY_MASK) +#define EPDC_TCE_OE_CLR_SDOED_WIDTH_MASK 0xFF000000u +#define EPDC_TCE_OE_CLR_SDOED_WIDTH_SHIFT 24 +#define EPDC_TCE_OE_CLR_SDOED_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_CLR_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_CLR_SDOED_WIDTH_MASK) +/* TCE_OE_TOG Bit Fields */ +#define EPDC_TCE_OE_TOG_SDOEZ_DLY_MASK 0xFFu +#define EPDC_TCE_OE_TOG_SDOEZ_DLY_SHIFT 0 +#define EPDC_TCE_OE_TOG_SDOEZ_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOEZ_DLY_SHIFT))&EPDC_TCE_OE_TOG_SDOEZ_DLY_MASK) +#define EPDC_TCE_OE_TOG_SDOEZ_WIDTH_MASK 0xFF00u +#define EPDC_TCE_OE_TOG_SDOEZ_WIDTH_SHIFT 8 +#define EPDC_TCE_OE_TOG_SDOEZ_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOEZ_WIDTH_SHIFT))&EPDC_TCE_OE_TOG_SDOEZ_WIDTH_MASK) +#define EPDC_TCE_OE_TOG_SDOED_DLY_MASK 0xFF0000u +#define EPDC_TCE_OE_TOG_SDOED_DLY_SHIFT 16 +#define EPDC_TCE_OE_TOG_SDOED_DLY(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOED_DLY_SHIFT))&EPDC_TCE_OE_TOG_SDOED_DLY_MASK) +#define EPDC_TCE_OE_TOG_SDOED_WIDTH_MASK 0xFF000000u +#define EPDC_TCE_OE_TOG_SDOED_WIDTH_SHIFT 24 +#define EPDC_TCE_OE_TOG_SDOED_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_OE_TOG_SDOED_WIDTH_SHIFT))&EPDC_TCE_OE_TOG_SDOED_WIDTH_MASK) +/* TCE_POLARITY Bit Fields */ +#define EPDC_TCE_POLARITY_SDCE_POL_MASK 0x1u +#define EPDC_TCE_POLARITY_SDCE_POL_SHIFT 0 +#define EPDC_TCE_POLARITY_SDLE_POL_MASK 0x2u +#define EPDC_TCE_POLARITY_SDLE_POL_SHIFT 1 +#define EPDC_TCE_POLARITY_SDOE_POL_MASK 0x4u +#define EPDC_TCE_POLARITY_SDOE_POL_SHIFT 2 +#define EPDC_TCE_POLARITY_GDOE_POL_MASK 0x8u +#define EPDC_TCE_POLARITY_GDOE_POL_SHIFT 3 +#define EPDC_TCE_POLARITY_GDSP_POL_MASK 0x10u +#define EPDC_TCE_POLARITY_GDSP_POL_SHIFT 4 +/* TCE_POLARITY_SET Bit Fields */ +#define EPDC_TCE_POLARITY_SET_SDCE_POL_MASK 0x1u +#define EPDC_TCE_POLARITY_SET_SDCE_POL_SHIFT 0 +#define EPDC_TCE_POLARITY_SET_SDLE_POL_MASK 0x2u +#define EPDC_TCE_POLARITY_SET_SDLE_POL_SHIFT 1 +#define EPDC_TCE_POLARITY_SET_SDOE_POL_MASK 0x4u +#define EPDC_TCE_POLARITY_SET_SDOE_POL_SHIFT 2 +#define EPDC_TCE_POLARITY_SET_GDOE_POL_MASK 0x8u +#define EPDC_TCE_POLARITY_SET_GDOE_POL_SHIFT 3 +#define EPDC_TCE_POLARITY_SET_GDSP_POL_MASK 0x10u +#define EPDC_TCE_POLARITY_SET_GDSP_POL_SHIFT 4 +/* TCE_POLARITY_CLR Bit Fields */ +#define EPDC_TCE_POLARITY_CLR_SDCE_POL_MASK 0x1u +#define EPDC_TCE_POLARITY_CLR_SDCE_POL_SHIFT 0 +#define EPDC_TCE_POLARITY_CLR_SDLE_POL_MASK 0x2u +#define EPDC_TCE_POLARITY_CLR_SDLE_POL_SHIFT 1 +#define EPDC_TCE_POLARITY_CLR_SDOE_POL_MASK 0x4u +#define EPDC_TCE_POLARITY_CLR_SDOE_POL_SHIFT 2 +#define EPDC_TCE_POLARITY_CLR_GDOE_POL_MASK 0x8u +#define EPDC_TCE_POLARITY_CLR_GDOE_POL_SHIFT 3 +#define EPDC_TCE_POLARITY_CLR_GDSP_POL_MASK 0x10u +#define EPDC_TCE_POLARITY_CLR_GDSP_POL_SHIFT 4 +/* TCE_POLARITY_TOG Bit Fields */ +#define EPDC_TCE_POLARITY_TOG_SDCE_POL_MASK 0x1u +#define EPDC_TCE_POLARITY_TOG_SDCE_POL_SHIFT 0 +#define EPDC_TCE_POLARITY_TOG_SDLE_POL_MASK 0x2u +#define EPDC_TCE_POLARITY_TOG_SDLE_POL_SHIFT 1 +#define EPDC_TCE_POLARITY_TOG_SDOE_POL_MASK 0x4u +#define EPDC_TCE_POLARITY_TOG_SDOE_POL_SHIFT 2 +#define EPDC_TCE_POLARITY_TOG_GDOE_POL_MASK 0x8u +#define EPDC_TCE_POLARITY_TOG_GDOE_POL_SHIFT 3 +#define EPDC_TCE_POLARITY_TOG_GDSP_POL_MASK 0x10u +#define EPDC_TCE_POLARITY_TOG_GDSP_POL_SHIFT 4 +/* TCE_TIMING1 Bit Fields */ +#define EPDC_TCE_TIMING1_SDCLK_SHIFT_MASK 0x3u +#define EPDC_TCE_TIMING1_SDCLK_SHIFT_SHIFT 0 +#define EPDC_TCE_TIMING1_SDCLK_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SDCLK_SHIFT_MASK) +#define EPDC_TCE_TIMING1_SDCLK_INVERT_MASK 0x8u +#define EPDC_TCE_TIMING1_SDCLK_INVERT_SHIFT 3 +#define EPDC_TCE_TIMING1_SDLE_SHIFT_MASK 0x30u +#define EPDC_TCE_TIMING1_SDLE_SHIFT_SHIFT 4 +#define EPDC_TCE_TIMING1_SDLE_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SDLE_SHIFT_MASK) +/* TCE_TIMING1_SET Bit Fields */ +#define EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_MASK 0x3u +#define EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_SHIFT 0 +#define EPDC_TCE_TIMING1_SET_SDCLK_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SET_SDCLK_SHIFT_MASK) +#define EPDC_TCE_TIMING1_SET_SDCLK_INVERT_MASK 0x8u +#define EPDC_TCE_TIMING1_SET_SDCLK_INVERT_SHIFT 3 +#define EPDC_TCE_TIMING1_SET_SDLE_SHIFT_MASK 0x30u +#define EPDC_TCE_TIMING1_SET_SDLE_SHIFT_SHIFT 4 +#define EPDC_TCE_TIMING1_SET_SDLE_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_SET_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_SET_SDLE_SHIFT_MASK) +/* TCE_TIMING1_CLR Bit Fields */ +#define EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_MASK 0x3u +#define EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_SHIFT 0 +#define EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_CLR_SDCLK_SHIFT_MASK) +#define EPDC_TCE_TIMING1_CLR_SDCLK_INVERT_MASK 0x8u +#define EPDC_TCE_TIMING1_CLR_SDCLK_INVERT_SHIFT 3 +#define EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_MASK 0x30u +#define EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_SHIFT 4 +#define EPDC_TCE_TIMING1_CLR_SDLE_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_CLR_SDLE_SHIFT_MASK) +/* TCE_TIMING1_TOG Bit Fields */ +#define EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_MASK 0x3u +#define EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_SHIFT 0 +#define EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_SHIFT))&EPDC_TCE_TIMING1_TOG_SDCLK_SHIFT_MASK) +#define EPDC_TCE_TIMING1_TOG_SDCLK_INVERT_MASK 0x8u +#define EPDC_TCE_TIMING1_TOG_SDCLK_INVERT_SHIFT 3 +#define EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_MASK 0x30u +#define EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_SHIFT 4 +#define EPDC_TCE_TIMING1_TOG_SDLE_SHIFT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_SHIFT))&EPDC_TCE_TIMING1_TOG_SDLE_SHIFT_MASK) +/* TCE_TIMING2 Bit Fields */ +#define EPDC_TCE_TIMING2_GDSP_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING2_GDSP_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING2_GDSP_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_GDSP_OFFSET_MASK) +#define EPDC_TCE_TIMING2_GDCLK_HP_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING2_GDCLK_HP_SHIFT 16 +#define EPDC_TCE_TIMING2_GDCLK_HP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_GDCLK_HP_MASK) +/* TCE_TIMING2_SET Bit Fields */ +#define EPDC_TCE_TIMING2_SET_GDSP_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING2_SET_GDSP_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING2_SET_GDSP_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_SET_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_SET_GDSP_OFFSET_MASK) +#define EPDC_TCE_TIMING2_SET_GDCLK_HP_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING2_SET_GDCLK_HP_SHIFT 16 +#define EPDC_TCE_TIMING2_SET_GDCLK_HP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_SET_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_SET_GDCLK_HP_MASK) +/* TCE_TIMING2_CLR Bit Fields */ +#define EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING2_CLR_GDSP_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_CLR_GDSP_OFFSET_MASK) +#define EPDC_TCE_TIMING2_CLR_GDCLK_HP_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING2_CLR_GDCLK_HP_SHIFT 16 +#define EPDC_TCE_TIMING2_CLR_GDCLK_HP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_CLR_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_CLR_GDCLK_HP_MASK) +/* TCE_TIMING2_TOG Bit Fields */ +#define EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING2_TOG_GDSP_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_SHIFT))&EPDC_TCE_TIMING2_TOG_GDSP_OFFSET_MASK) +#define EPDC_TCE_TIMING2_TOG_GDCLK_HP_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING2_TOG_GDCLK_HP_SHIFT 16 +#define EPDC_TCE_TIMING2_TOG_GDCLK_HP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING2_TOG_GDCLK_HP_SHIFT))&EPDC_TCE_TIMING2_TOG_GDCLK_HP_MASK) +/* TCE_TIMING3 Bit Fields */ +#define EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING3_GDCLK_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING3_GDCLK_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK) +#define EPDC_TCE_TIMING3_GDOE_OFFSET_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING3_GDOE_OFFSET_SHIFT 16 +#define EPDC_TCE_TIMING3_GDOE_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_GDOE_OFFSET_MASK) +/* TCE_TIMING3_SET Bit Fields */ +#define EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING3_SET_GDCLK_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_SET_GDCLK_OFFSET_MASK) +#define EPDC_TCE_TIMING3_SET_GDOE_OFFSET_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING3_SET_GDOE_OFFSET_SHIFT 16 +#define EPDC_TCE_TIMING3_SET_GDOE_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_SET_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_SET_GDOE_OFFSET_MASK) +/* TCE_TIMING3_CLR Bit Fields */ +#define EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_CLR_GDCLK_OFFSET_MASK) +#define EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_SHIFT 16 +#define EPDC_TCE_TIMING3_CLR_GDOE_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_CLR_GDOE_OFFSET_MASK) +/* TCE_TIMING3_TOG Bit Fields */ +#define EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_MASK 0xFFFFu +#define EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_SHIFT 0 +#define EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_SHIFT))&EPDC_TCE_TIMING3_TOG_GDCLK_OFFSET_MASK) +#define EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_MASK 0xFFFF0000u +#define EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_SHIFT 16 +#define EPDC_TCE_TIMING3_TOG_GDOE_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_SHIFT))&EPDC_TCE_TIMING3_TOG_GDOE_OFFSET_MASK) +/* PIGEON_CTRL0 Bit Fields */ +#define EPDC_PIGEON_CTRL0_FD_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL0_FD_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_FD_PERIOD_MASK) +#define EPDC_PIGEON_CTRL0_LD_PERIOD_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL0_LD_PERIOD_SHIFT 16 +#define EPDC_PIGEON_CTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_LD_PERIOD_MASK) +/* PIGEON_CTRL0_SET Bit Fields */ +#define EPDC_PIGEON_CTRL0_SET_FD_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL0_SET_FD_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_SET_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_SET_FD_PERIOD_MASK) +#define EPDC_PIGEON_CTRL0_SET_LD_PERIOD_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL0_SET_LD_PERIOD_SHIFT 16 +#define EPDC_PIGEON_CTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_SET_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_SET_LD_PERIOD_MASK) +/* PIGEON_CTRL0_CLR Bit Fields */ +#define EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_CLR_FD_PERIOD_MASK) +#define EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_SHIFT 16 +#define EPDC_PIGEON_CTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_CLR_LD_PERIOD_MASK) +/* PIGEON_CTRL0_TOG Bit Fields */ +#define EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_TOG_FD_PERIOD_MASK) +#define EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_SHIFT 16 +#define EPDC_PIGEON_CTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_SHIFT))&EPDC_PIGEON_CTRL0_TOG_LD_PERIOD_MASK) +/* PIGEON_CTRL1 Bit Fields */ +#define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_FRAME_CNT_PERIOD_MASK) +#define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_SHIFT 16 +#define EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_FRAME_CNT_CYCLES_MASK) +/* PIGEON_CTRL1_SET Bit Fields */ +#define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_SET_FRAME_CNT_PERIOD_MASK) +#define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_SHIFT 16 +#define EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_SET_FRAME_CNT_CYCLES_MASK) +/* PIGEON_CTRL1_CLR Bit Fields */ +#define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_PERIOD_MASK) +#define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_SHIFT 16 +#define EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_CLR_FRAME_CNT_CYCLES_MASK) +/* PIGEON_CTRL1_TOG Bit Fields */ +#define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_MASK 0xFFFu +#define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_SHIFT 0 +#define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_SHIFT))&EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_PERIOD_MASK) +#define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_MASK 0xFFF0000u +#define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_SHIFT 16 +#define EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_SHIFT))&EPDC_PIGEON_CTRL1_TOG_FRAME_CNT_CYCLES_MASK) +/* IRQ_MASK1 Bit Fields */ +#define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ_MASK1_SET Bit Fields */ +#define EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_SET_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ_MASK1_CLR Bit Fields */ +#define EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_CLR_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ_MASK1_TOG Bit Fields */ +#define EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK1_TOG_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ_MASK2 Bit Fields */ +#define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ_MASK2_SET Bit Fields */ +#define EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_SET_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ_MASK2_CLR Bit Fields */ +#define EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_CLR_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ_MASK2_TOG Bit Fields */ +#define EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_MASK 0xFFFFFFFFu +#define EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_SHIFT 0 +#define EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_SHIFT))&EPDC_IRQ_MASK2_TOG_LUTN_CMPLT_IRQ_EN_MASK) +/* IRQ1 Bit Fields */ +#define EPDC_IRQ1_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ1_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ1_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_LUTN_CMPLT_IRQ_MASK) +/* IRQ1_SET Bit Fields */ +#define EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ1_SET_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_SET_LUTN_CMPLT_IRQ_MASK) +/* IRQ1_CLR Bit Fields */ +#define EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_CLR_LUTN_CMPLT_IRQ_MASK) +/* IRQ1_TOG Bit Fields */ +#define EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ1_TOG_LUTN_CMPLT_IRQ_MASK) +/* IRQ2 Bit Fields */ +#define EPDC_IRQ2_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ2_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ2_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_LUTN_CMPLT_IRQ_MASK) +/* IRQ2_SET Bit Fields */ +#define EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ2_SET_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_SET_LUTN_CMPLT_IRQ_MASK) +/* IRQ2_CLR Bit Fields */ +#define EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_CLR_LUTN_CMPLT_IRQ_MASK) +/* IRQ2_TOG Bit Fields */ +#define EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_MASK 0xFFFFFFFFu +#define EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_SHIFT 0 +#define EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x))<<EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_SHIFT))&EPDC_IRQ2_TOG_LUTN_CMPLT_IRQ_MASK) +/* IRQ_MASK Bit Fields */ +#define EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_MASK 0x10000u +#define EPDC_IRQ_MASK_WB_CMPLT_IRQ_EN_SHIFT 16 +#define EPDC_IRQ_MASK_COL_IRQ_EN_MASK 0x20000u +#define EPDC_IRQ_MASK_COL_IRQ_EN_SHIFT 17 +#define EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_MASK 0x40000u +#define EPDC_IRQ_MASK_TCE_UNDERRUN_IRQ_EN_SHIFT 18 +#define EPDC_IRQ_MASK_FRAME_END_IRQ_EN_MASK 0x80000u +#define EPDC_IRQ_MASK_FRAME_END_IRQ_EN_SHIFT 19 +#define EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_MASK 0x100000u +#define EPDC_IRQ_MASK_BUS_ERROR_IRQ_EN_SHIFT 20 +#define EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_MASK 0x200000u +#define EPDC_IRQ_MASK_TCE_IDLE_IRQ_EN_SHIFT 21 +#define EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_MASK 0x400000u +#define EPDC_IRQ_MASK_UPD_DONE_IRQ_EN_SHIFT 22 +#define EPDC_IRQ_MASK_PWR_IRQ_EN_MASK 0x800000u +#define EPDC_IRQ_MASK_PWR_IRQ_EN_SHIFT 23 +/* IRQ_MASK_SET Bit Fields */ +#define EPDC_IRQ_MASK_SET_WB_CMPLT_IRQ_EN_MASK 0x10000u +#define EPDC_IRQ_MASK_SET_WB_CMPLT_IRQ_EN_SHIFT 16 +#define EPDC_IRQ_MASK_SET_COL_IRQ_EN_MASK 0x20000u +#define EPDC_IRQ_MASK_SET_COL_IRQ_EN_SHIFT 17 +#define EPDC_IRQ_MASK_SET_TCE_UNDERRUN_IRQ_EN_MASK 0x40000u +#define EPDC_IRQ_MASK_SET_TCE_UNDERRUN_IRQ_EN_SHIFT 18 +#define EPDC_IRQ_MASK_SET_FRAME_END_IRQ_EN_MASK 0x80000u +#define EPDC_IRQ_MASK_SET_FRAME_END_IRQ_EN_SHIFT 19 +#define EPDC_IRQ_MASK_SET_BUS_ERROR_IRQ_EN_MASK 0x100000u +#define EPDC_IRQ_MASK_SET_BUS_ERROR_IRQ_EN_SHIFT 20 +#define EPDC_IRQ_MASK_SET_TCE_IDLE_IRQ_EN_MASK 0x200000u +#define EPDC_IRQ_MASK_SET_TCE_IDLE_IRQ_EN_SHIFT 21 +#define EPDC_IRQ_MASK_SET_UPD_DONE_IRQ_EN_MASK 0x400000u +#define EPDC_IRQ_MASK_SET_UPD_DONE_IRQ_EN_SHIFT 22 +#define EPDC_IRQ_MASK_SET_PWR_IRQ_EN_MASK 0x800000u +#define EPDC_IRQ_MASK_SET_PWR_IRQ_EN_SHIFT 23 +/* IRQ_MASK_CLR Bit Fields */ +#define EPDC_IRQ_MASK_CLR_WB_CMPLT_IRQ_EN_MASK 0x10000u +#define EPDC_IRQ_MASK_CLR_WB_CMPLT_IRQ_EN_SHIFT 16 +#define EPDC_IRQ_MASK_CLR_COL_IRQ_EN_MASK 0x20000u +#define EPDC_IRQ_MASK_CLR_COL_IRQ_EN_SHIFT 17 +#define EPDC_IRQ_MASK_CLR_TCE_UNDERRUN_IRQ_EN_MASK 0x40000u +#define EPDC_IRQ_MASK_CLR_TCE_UNDERRUN_IRQ_EN_SHIFT 18 +#define EPDC_IRQ_MASK_CLR_FRAME_END_IRQ_EN_MASK 0x80000u +#define EPDC_IRQ_MASK_CLR_FRAME_END_IRQ_EN_SHIFT 19 +#define EPDC_IRQ_MASK_CLR_BUS_ERROR_IRQ_EN_MASK 0x100000u +#define EPDC_IRQ_MASK_CLR_BUS_ERROR_IRQ_EN_SHIFT 20 +#define EPDC_IRQ_MASK_CLR_TCE_IDLE_IRQ_EN_MASK 0x200000u +#define EPDC_IRQ_MASK_CLR_TCE_IDLE_IRQ_EN_SHIFT 21 +#define EPDC_IRQ_MASK_CLR_UPD_DONE_IRQ_EN_MASK 0x400000u +#define EPDC_IRQ_MASK_CLR_UPD_DONE_IRQ_EN_SHIFT 22 +#define EPDC_IRQ_MASK_CLR_PWR_IRQ_EN_MASK 0x800000u +#define EPDC_IRQ_MASK_CLR_PWR_IRQ_EN_SHIFT 23 +/* IRQ_MASK_TOG Bit Fields */ +#define EPDC_IRQ_MASK_TOG_WB_CMPLT_IRQ_EN_MASK 0x10000u +#define EPDC_IRQ_MASK_TOG_WB_CMPLT_IRQ_EN_SHIFT 16 +#define EPDC_IRQ_MASK_TOG_COL_IRQ_EN_MASK 0x20000u +#define EPDC_IRQ_MASK_TOG_COL_IRQ_EN_SHIFT 17 +#define EPDC_IRQ_MASK_TOG_TCE_UNDERRUN_IRQ_EN_MASK 0x40000u +#define EPDC_IRQ_MASK_TOG_TCE_UNDERRUN_IRQ_EN_SHIFT 18 +#define EPDC_IRQ_MASK_TOG_FRAME_END_IRQ_EN_MASK 0x80000u +#define EPDC_IRQ_MASK_TOG_FRAME_END_IRQ_EN_SHIFT 19 +#define EPDC_IRQ_MASK_TOG_BUS_ERROR_IRQ_EN_MASK 0x100000u +#define EPDC_IRQ_MASK_TOG_BUS_ERROR_IRQ_EN_SHIFT 20 +#define EPDC_IRQ_MASK_TOG_TCE_IDLE_IRQ_EN_MASK 0x200000u +#define EPDC_IRQ_MASK_TOG_TCE_IDLE_IRQ_EN_SHIFT 21 +#define EPDC_IRQ_MASK_TOG_UPD_DONE_IRQ_EN_MASK 0x400000u +#define EPDC_IRQ_MASK_TOG_UPD_DONE_IRQ_EN_SHIFT 22 +#define EPDC_IRQ_MASK_TOG_PWR_IRQ_EN_MASK 0x800000u +#define EPDC_IRQ_MASK_TOG_PWR_IRQ_EN_SHIFT 23 +/* IRQ Bit Fields */ +#define EPDC_IRQ_WB_CMPLT_IRQ_MASK 0x10000u +#define EPDC_IRQ_WB_CMPLT_IRQ_SHIFT 16 +#define EPDC_IRQ_LUT_COL_IRQ_MASK 0x20000u +#define EPDC_IRQ_LUT_COL_IRQ_SHIFT 17 +#define EPDC_IRQ_TCE_UNDERRUN_IRQ_MASK 0x40000u +#define EPDC_IRQ_TCE_UNDERRUN_IRQ_SHIFT 18 +#define EPDC_IRQ_FRAME_END_IRQ_MASK 0x80000u +#define EPDC_IRQ_FRAME_END_IRQ_SHIFT 19 +#define EPDC_IRQ_BUS_ERROR_IRQ_MASK 0x100000u +#define EPDC_IRQ_BUS_ERROR_IRQ_SHIFT 20 +#define EPDC_IRQ_TCE_IDLE_IRQ_MASK 0x200000u +#define EPDC_IRQ_TCE_IDLE_IRQ_SHIFT 21 +#define EPDC_IRQ_UPD_DONE_IRQ_MASK 0x400000u +#define EPDC_IRQ_UPD_DONE_IRQ_SHIFT 22 +#define EPDC_IRQ_PWR_IRQ_MASK 0x800000u +#define EPDC_IRQ_PWR_IRQ_SHIFT 23 +/* IRQ_SET Bit Fields */ +#define EPDC_IRQ_SET_WB_CMPLT_IRQ_MASK 0x10000u +#define EPDC_IRQ_SET_WB_CMPLT_IRQ_SHIFT 16 +#define EPDC_IRQ_SET_LUT_COL_IRQ_MASK 0x20000u +#define EPDC_IRQ_SET_LUT_COL_IRQ_SHIFT 17 +#define EPDC_IRQ_SET_TCE_UNDERRUN_IRQ_MASK 0x40000u +#define EPDC_IRQ_SET_TCE_UNDERRUN_IRQ_SHIFT 18 +#define EPDC_IRQ_SET_FRAME_END_IRQ_MASK 0x80000u +#define EPDC_IRQ_SET_FRAME_END_IRQ_SHIFT 19 +#define EPDC_IRQ_SET_BUS_ERROR_IRQ_MASK 0x100000u +#define EPDC_IRQ_SET_BUS_ERROR_IRQ_SHIFT 20 +#define EPDC_IRQ_SET_TCE_IDLE_IRQ_MASK 0x200000u +#define EPDC_IRQ_SET_TCE_IDLE_IRQ_SHIFT 21 +#define EPDC_IRQ_SET_UPD_DONE_IRQ_MASK 0x400000u +#define EPDC_IRQ_SET_UPD_DONE_IRQ_SHIFT 22 +#define EPDC_IRQ_SET_PWR_IRQ_MASK 0x800000u +#define EPDC_IRQ_SET_PWR_IRQ_SHIFT 23 +/* IRQ_CLR Bit Fields */ +#define EPDC_IRQ_CLR_WB_CMPLT_IRQ_MASK 0x10000u +#define EPDC_IRQ_CLR_WB_CMPLT_IRQ_SHIFT 16 +#define EPDC_IRQ_CLR_LUT_COL_IRQ_MASK 0x20000u +#define EPDC_IRQ_CLR_LUT_COL_IRQ_SHIFT 17 +#define EPDC_IRQ_CLR_TCE_UNDERRUN_IRQ_MASK 0x40000u +#define EPDC_IRQ_CLR_TCE_UNDERRUN_IRQ_SHIFT 18 +#define EPDC_IRQ_CLR_FRAME_END_IRQ_MASK 0x80000u +#define EPDC_IRQ_CLR_FRAME_END_IRQ_SHIFT 19 +#define EPDC_IRQ_CLR_BUS_ERROR_IRQ_MASK 0x100000u +#define EPDC_IRQ_CLR_BUS_ERROR_IRQ_SHIFT 20 +#define EPDC_IRQ_CLR_TCE_IDLE_IRQ_MASK 0x200000u +#define EPDC_IRQ_CLR_TCE_IDLE_IRQ_SHIFT 21 +#define EPDC_IRQ_CLR_UPD_DONE_IRQ_MASK 0x400000u +#define EPDC_IRQ_CLR_UPD_DONE_IRQ_SHIFT 22 +#define EPDC_IRQ_CLR_PWR_IRQ_MASK 0x800000u +#define EPDC_IRQ_CLR_PWR_IRQ_SHIFT 23 +/* IRQ_TOG Bit Fields */ +#define EPDC_IRQ_TOG_WB_CMPLT_IRQ_MASK 0x10000u +#define EPDC_IRQ_TOG_WB_CMPLT_IRQ_SHIFT 16 +#define EPDC_IRQ_TOG_LUT_COL_IRQ_MASK 0x20000u +#define EPDC_IRQ_TOG_LUT_COL_IRQ_SHIFT 17 +#define EPDC_IRQ_TOG_TCE_UNDERRUN_IRQ_MASK 0x40000u +#define EPDC_IRQ_TOG_TCE_UNDERRUN_IRQ_SHIFT 18 +#define EPDC_IRQ_TOG_FRAME_END_IRQ_MASK 0x80000u +#define EPDC_IRQ_TOG_FRAME_END_IRQ_SHIFT 19 +#define EPDC_IRQ_TOG_BUS_ERROR_IRQ_MASK 0x100000u +#define EPDC_IRQ_TOG_BUS_ERROR_IRQ_SHIFT 20 +#define EPDC_IRQ_TOG_TCE_IDLE_IRQ_MASK 0x200000u +#define EPDC_IRQ_TOG_TCE_IDLE_IRQ_SHIFT 21 +#define EPDC_IRQ_TOG_UPD_DONE_IRQ_MASK 0x400000u +#define EPDC_IRQ_TOG_UPD_DONE_IRQ_SHIFT 22 +#define EPDC_IRQ_TOG_PWR_IRQ_MASK 0x800000u +#define EPDC_IRQ_TOG_PWR_IRQ_SHIFT 23 +/* STATUS_LUTS1 Bit Fields */ +#define EPDC_STATUS_LUTS1_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS1_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS1_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_LUTN_STS_MASK) +/* STATUS_LUTS1_SET Bit Fields */ +#define EPDC_STATUS_LUTS1_SET_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS1_SET_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS1_SET_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_SET_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_SET_LUTN_STS_MASK) +/* STATUS_LUTS1_CLR Bit Fields */ +#define EPDC_STATUS_LUTS1_CLR_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS1_CLR_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS1_CLR_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_CLR_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_CLR_LUTN_STS_MASK) +/* STATUS_LUTS1_TOG Bit Fields */ +#define EPDC_STATUS_LUTS1_TOG_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS1_TOG_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS1_TOG_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS1_TOG_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS1_TOG_LUTN_STS_MASK) +/* STATUS_LUTS2 Bit Fields */ +#define EPDC_STATUS_LUTS2_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS2_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS2_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_LUTN_STS_MASK) +/* STATUS_LUTS2_SET Bit Fields */ +#define EPDC_STATUS_LUTS2_SET_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS2_SET_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS2_SET_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_SET_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_SET_LUTN_STS_MASK) +/* STATUS_LUTS2_CLR Bit Fields */ +#define EPDC_STATUS_LUTS2_CLR_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS2_CLR_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS2_CLR_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_CLR_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_CLR_LUTN_STS_MASK) +/* STATUS_LUTS2_TOG Bit Fields */ +#define EPDC_STATUS_LUTS2_TOG_LUTN_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_LUTS2_TOG_LUTN_STS_SHIFT 0 +#define EPDC_STATUS_LUTS2_TOG_LUTN_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_LUTS2_TOG_LUTN_STS_SHIFT))&EPDC_STATUS_LUTS2_TOG_LUTN_STS_MASK) +/* STATUS_NEXTLUT Bit Fields */ +#define EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK 0x3Fu +#define EPDC_STATUS_NEXTLUT_NEXT_LUT_SHIFT 0 +#define EPDC_STATUS_NEXTLUT_NEXT_LUT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_NEXTLUT_NEXT_LUT_SHIFT))&EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK) +#define EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_MASK 0x100u +#define EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID_SHIFT 8 +/* STATUS_COL1 Bit Fields */ +#define EPDC_STATUS_COL1_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL1_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL1_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_LUTN_COL_STS_MASK) +/* STATUS_COL1_SET Bit Fields */ +#define EPDC_STATUS_COL1_SET_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL1_SET_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL1_SET_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_SET_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_SET_LUTN_COL_STS_MASK) +/* STATUS_COL1_CLR Bit Fields */ +#define EPDC_STATUS_COL1_CLR_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL1_CLR_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL1_CLR_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_CLR_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_CLR_LUTN_COL_STS_MASK) +/* STATUS_COL1_TOG Bit Fields */ +#define EPDC_STATUS_COL1_TOG_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL1_TOG_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL1_TOG_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL1_TOG_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL1_TOG_LUTN_COL_STS_MASK) +/* STATUS_COL2 Bit Fields */ +#define EPDC_STATUS_COL2_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL2_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL2_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_LUTN_COL_STS_MASK) +/* STATUS_COL2_SET Bit Fields */ +#define EPDC_STATUS_COL2_SET_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL2_SET_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL2_SET_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_SET_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_SET_LUTN_COL_STS_MASK) +/* STATUS_COL2_CLR Bit Fields */ +#define EPDC_STATUS_COL2_CLR_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL2_CLR_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL2_CLR_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_CLR_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_CLR_LUTN_COL_STS_MASK) +/* STATUS_COL2_TOG Bit Fields */ +#define EPDC_STATUS_COL2_TOG_LUTN_COL_STS_MASK 0xFFFFFFFFu +#define EPDC_STATUS_COL2_TOG_LUTN_COL_STS_SHIFT 0 +#define EPDC_STATUS_COL2_TOG_LUTN_COL_STS(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_COL2_TOG_LUTN_COL_STS_SHIFT))&EPDC_STATUS_COL2_TOG_LUTN_COL_STS_MASK) +/* STATUS Bit Fields */ +#define EPDC_STATUS_WB_BUSY_MASK 0x1u +#define EPDC_STATUS_WB_BUSY_SHIFT 0 +#define EPDC_STATUS_LUTS_BUSY_MASK 0x2u +#define EPDC_STATUS_LUTS_BUSY_SHIFT 1 +#define EPDC_STATUS_LUTS_UNDERRUN_MASK 0x4u +#define EPDC_STATUS_LUTS_UNDERRUN_SHIFT 2 +#define EPDC_STATUS_UPD_VOID_MASK 0x8u +#define EPDC_STATUS_UPD_VOID_SHIFT 3 +#define EPDC_STATUS_HISTOGRAM_NP_MASK 0x1F00u +#define EPDC_STATUS_HISTOGRAM_NP_SHIFT 8 +#define EPDC_STATUS_HISTOGRAM_NP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_HISTOGRAM_NP_MASK) +#define EPDC_STATUS_HISTOGRAM_CP_MASK 0x1F0000u +#define EPDC_STATUS_HISTOGRAM_CP_SHIFT 16 +#define EPDC_STATUS_HISTOGRAM_CP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_HISTOGRAM_CP_MASK) +/* STATUS_SET Bit Fields */ +#define EPDC_STATUS_SET_WB_BUSY_MASK 0x1u +#define EPDC_STATUS_SET_WB_BUSY_SHIFT 0 +#define EPDC_STATUS_SET_LUTS_BUSY_MASK 0x2u +#define EPDC_STATUS_SET_LUTS_BUSY_SHIFT 1 +#define EPDC_STATUS_SET_LUTS_UNDERRUN_MASK 0x4u +#define EPDC_STATUS_SET_LUTS_UNDERRUN_SHIFT 2 +#define EPDC_STATUS_SET_UPD_VOID_MASK 0x8u +#define EPDC_STATUS_SET_UPD_VOID_SHIFT 3 +#define EPDC_STATUS_SET_HISTOGRAM_NP_MASK 0x1F00u +#define EPDC_STATUS_SET_HISTOGRAM_NP_SHIFT 8 +#define EPDC_STATUS_SET_HISTOGRAM_NP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_SET_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_SET_HISTOGRAM_NP_MASK) +#define EPDC_STATUS_SET_HISTOGRAM_CP_MASK 0x1F0000u +#define EPDC_STATUS_SET_HISTOGRAM_CP_SHIFT 16 +#define EPDC_STATUS_SET_HISTOGRAM_CP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_SET_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_SET_HISTOGRAM_CP_MASK) +/* STATUS_CLR Bit Fields */ +#define EPDC_STATUS_CLR_WB_BUSY_MASK 0x1u +#define EPDC_STATUS_CLR_WB_BUSY_SHIFT 0 +#define EPDC_STATUS_CLR_LUTS_BUSY_MASK 0x2u +#define EPDC_STATUS_CLR_LUTS_BUSY_SHIFT 1 +#define EPDC_STATUS_CLR_LUTS_UNDERRUN_MASK 0x4u +#define EPDC_STATUS_CLR_LUTS_UNDERRUN_SHIFT 2 +#define EPDC_STATUS_CLR_UPD_VOID_MASK 0x8u +#define EPDC_STATUS_CLR_UPD_VOID_SHIFT 3 +#define EPDC_STATUS_CLR_HISTOGRAM_NP_MASK 0x1F00u +#define EPDC_STATUS_CLR_HISTOGRAM_NP_SHIFT 8 +#define EPDC_STATUS_CLR_HISTOGRAM_NP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_CLR_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_CLR_HISTOGRAM_NP_MASK) +#define EPDC_STATUS_CLR_HISTOGRAM_CP_MASK 0x1F0000u +#define EPDC_STATUS_CLR_HISTOGRAM_CP_SHIFT 16 +#define EPDC_STATUS_CLR_HISTOGRAM_CP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_CLR_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_CLR_HISTOGRAM_CP_MASK) +/* STATUS_TOG Bit Fields */ +#define EPDC_STATUS_TOG_WB_BUSY_MASK 0x1u +#define EPDC_STATUS_TOG_WB_BUSY_SHIFT 0 +#define EPDC_STATUS_TOG_LUTS_BUSY_MASK 0x2u +#define EPDC_STATUS_TOG_LUTS_BUSY_SHIFT 1 +#define EPDC_STATUS_TOG_LUTS_UNDERRUN_MASK 0x4u +#define EPDC_STATUS_TOG_LUTS_UNDERRUN_SHIFT 2 +#define EPDC_STATUS_TOG_UPD_VOID_MASK 0x8u +#define EPDC_STATUS_TOG_UPD_VOID_SHIFT 3 +#define EPDC_STATUS_TOG_HISTOGRAM_NP_MASK 0x1F00u +#define EPDC_STATUS_TOG_HISTOGRAM_NP_SHIFT 8 +#define EPDC_STATUS_TOG_HISTOGRAM_NP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_TOG_HISTOGRAM_NP_SHIFT))&EPDC_STATUS_TOG_HISTOGRAM_NP_MASK) +#define EPDC_STATUS_TOG_HISTOGRAM_CP_MASK 0x1F0000u +#define EPDC_STATUS_TOG_HISTOGRAM_CP_SHIFT 16 +#define EPDC_STATUS_TOG_HISTOGRAM_CP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_STATUS_TOG_HISTOGRAM_CP_SHIFT))&EPDC_STATUS_TOG_HISTOGRAM_CP_MASK) +/* UPD_COL_CORD Bit Fields */ +#define EPDC_UPD_COL_CORD_XCORD_MASK 0x1FFFu +#define EPDC_UPD_COL_CORD_XCORD_SHIFT 0 +#define EPDC_UPD_COL_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_CORD_XCORD_SHIFT))&EPDC_UPD_COL_CORD_XCORD_MASK) +#define EPDC_UPD_COL_CORD_YCORD_MASK 0x1FFF0000u +#define EPDC_UPD_COL_CORD_YCORD_SHIFT 16 +#define EPDC_UPD_COL_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_CORD_YCORD_SHIFT))&EPDC_UPD_COL_CORD_YCORD_MASK) +/* UPD_COL_SIZE Bit Fields */ +#define EPDC_UPD_COL_SIZE_WIDTH_MASK 0x1FFFu +#define EPDC_UPD_COL_SIZE_WIDTH_SHIFT 0 +#define EPDC_UPD_COL_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_SIZE_WIDTH_SHIFT))&EPDC_UPD_COL_SIZE_WIDTH_MASK) +#define EPDC_UPD_COL_SIZE_HEIGHT_MASK 0x1FFF0000u +#define EPDC_UPD_COL_SIZE_HEIGHT_SHIFT 16 +#define EPDC_UPD_COL_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_UPD_COL_SIZE_HEIGHT_SHIFT))&EPDC_UPD_COL_SIZE_HEIGHT_MASK) +/* HIST1_PARAM Bit Fields */ +#define EPDC_HIST1_PARAM_VALUE0_MASK 0x1Fu +#define EPDC_HIST1_PARAM_VALUE0_SHIFT 0 +#define EPDC_HIST1_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST1_PARAM_VALUE0_SHIFT))&EPDC_HIST1_PARAM_VALUE0_MASK) +#define EPDC_HIST1_PARAM_RSVD_MASK 0xFFFFFFE0u +#define EPDC_HIST1_PARAM_RSVD_SHIFT 5 +#define EPDC_HIST1_PARAM_RSVD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST1_PARAM_RSVD_SHIFT))&EPDC_HIST1_PARAM_RSVD_MASK) +/* HIST2_PARAM Bit Fields */ +#define EPDC_HIST2_PARAM_VALUE0_MASK 0x1Fu +#define EPDC_HIST2_PARAM_VALUE0_SHIFT 0 +#define EPDC_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST2_PARAM_VALUE0_SHIFT))&EPDC_HIST2_PARAM_VALUE0_MASK) +#define EPDC_HIST2_PARAM_VALUE1_MASK 0x1F00u +#define EPDC_HIST2_PARAM_VALUE1_SHIFT 8 +#define EPDC_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST2_PARAM_VALUE1_SHIFT))&EPDC_HIST2_PARAM_VALUE1_MASK) +#define EPDC_HIST2_PARAM_RSVD_MASK 0xFFFF0000u +#define EPDC_HIST2_PARAM_RSVD_SHIFT 16 +#define EPDC_HIST2_PARAM_RSVD(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST2_PARAM_RSVD_SHIFT))&EPDC_HIST2_PARAM_RSVD_MASK) +/* HIST4_PARAM Bit Fields */ +#define EPDC_HIST4_PARAM_VALUE0_MASK 0x1Fu +#define EPDC_HIST4_PARAM_VALUE0_SHIFT 0 +#define EPDC_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE0_SHIFT))&EPDC_HIST4_PARAM_VALUE0_MASK) +#define EPDC_HIST4_PARAM_VALUE1_MASK 0x1F00u +#define EPDC_HIST4_PARAM_VALUE1_SHIFT 8 +#define EPDC_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE1_SHIFT))&EPDC_HIST4_PARAM_VALUE1_MASK) +#define EPDC_HIST4_PARAM_VALUE2_MASK 0x1F0000u +#define EPDC_HIST4_PARAM_VALUE2_SHIFT 16 +#define EPDC_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE2_SHIFT))&EPDC_HIST4_PARAM_VALUE2_MASK) +#define EPDC_HIST4_PARAM_VALUE3_MASK 0x1F000000u +#define EPDC_HIST4_PARAM_VALUE3_SHIFT 24 +#define EPDC_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST4_PARAM_VALUE3_SHIFT))&EPDC_HIST4_PARAM_VALUE3_MASK) +/* HIST8_PARAM0 Bit Fields */ +#define EPDC_HIST8_PARAM0_VALUE0_MASK 0x1Fu +#define EPDC_HIST8_PARAM0_VALUE0_SHIFT 0 +#define EPDC_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE0_SHIFT))&EPDC_HIST8_PARAM0_VALUE0_MASK) +#define EPDC_HIST8_PARAM0_VALUE1_MASK 0x1F00u +#define EPDC_HIST8_PARAM0_VALUE1_SHIFT 8 +#define EPDC_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE1_SHIFT))&EPDC_HIST8_PARAM0_VALUE1_MASK) +#define EPDC_HIST8_PARAM0_VALUE2_MASK 0x1F0000u +#define EPDC_HIST8_PARAM0_VALUE2_SHIFT 16 +#define EPDC_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE2_SHIFT))&EPDC_HIST8_PARAM0_VALUE2_MASK) +#define EPDC_HIST8_PARAM0_VALUE3_MASK 0x1F000000u +#define EPDC_HIST8_PARAM0_VALUE3_SHIFT 24 +#define EPDC_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM0_VALUE3_SHIFT))&EPDC_HIST8_PARAM0_VALUE3_MASK) +/* HIST8_PARAM1 Bit Fields */ +#define EPDC_HIST8_PARAM1_VALUE4_MASK 0x1Fu +#define EPDC_HIST8_PARAM1_VALUE4_SHIFT 0 +#define EPDC_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE4_SHIFT))&EPDC_HIST8_PARAM1_VALUE4_MASK) +#define EPDC_HIST8_PARAM1_VALUE5_MASK 0x1F00u +#define EPDC_HIST8_PARAM1_VALUE5_SHIFT 8 +#define EPDC_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE5_SHIFT))&EPDC_HIST8_PARAM1_VALUE5_MASK) +#define EPDC_HIST8_PARAM1_VALUE6_MASK 0x1F0000u +#define EPDC_HIST8_PARAM1_VALUE6_SHIFT 16 +#define EPDC_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE6_SHIFT))&EPDC_HIST8_PARAM1_VALUE6_MASK) +#define EPDC_HIST8_PARAM1_VALUE7_MASK 0x1F000000u +#define EPDC_HIST8_PARAM1_VALUE7_SHIFT 24 +#define EPDC_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST8_PARAM1_VALUE7_SHIFT))&EPDC_HIST8_PARAM1_VALUE7_MASK) +/* HIST16_PARAM0 Bit Fields */ +#define EPDC_HIST16_PARAM0_VALUE0_MASK 0x1Fu +#define EPDC_HIST16_PARAM0_VALUE0_SHIFT 0 +#define EPDC_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE0_SHIFT))&EPDC_HIST16_PARAM0_VALUE0_MASK) +#define EPDC_HIST16_PARAM0_VALUE1_MASK 0x1F00u +#define EPDC_HIST16_PARAM0_VALUE1_SHIFT 8 +#define EPDC_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE1_SHIFT))&EPDC_HIST16_PARAM0_VALUE1_MASK) +#define EPDC_HIST16_PARAM0_VALUE2_MASK 0x1F0000u +#define EPDC_HIST16_PARAM0_VALUE2_SHIFT 16 +#define EPDC_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE2_SHIFT))&EPDC_HIST16_PARAM0_VALUE2_MASK) +#define EPDC_HIST16_PARAM0_VALUE3_MASK 0x1F000000u +#define EPDC_HIST16_PARAM0_VALUE3_SHIFT 24 +#define EPDC_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM0_VALUE3_SHIFT))&EPDC_HIST16_PARAM0_VALUE3_MASK) +/* HIST16_PARAM1 Bit Fields */ +#define EPDC_HIST16_PARAM1_VALUE4_MASK 0x1Fu +#define EPDC_HIST16_PARAM1_VALUE4_SHIFT 0 +#define EPDC_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE4_SHIFT))&EPDC_HIST16_PARAM1_VALUE4_MASK) +#define EPDC_HIST16_PARAM1_VALUE5_MASK 0x1F00u +#define EPDC_HIST16_PARAM1_VALUE5_SHIFT 8 +#define EPDC_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE5_SHIFT))&EPDC_HIST16_PARAM1_VALUE5_MASK) +#define EPDC_HIST16_PARAM1_VALUE6_MASK 0x1F0000u +#define EPDC_HIST16_PARAM1_VALUE6_SHIFT 16 +#define EPDC_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE6_SHIFT))&EPDC_HIST16_PARAM1_VALUE6_MASK) +#define EPDC_HIST16_PARAM1_VALUE7_MASK 0x1F000000u +#define EPDC_HIST16_PARAM1_VALUE7_SHIFT 24 +#define EPDC_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM1_VALUE7_SHIFT))&EPDC_HIST16_PARAM1_VALUE7_MASK) +/* HIST16_PARAM2 Bit Fields */ +#define EPDC_HIST16_PARAM2_VALUE8_MASK 0x1Fu +#define EPDC_HIST16_PARAM2_VALUE8_SHIFT 0 +#define EPDC_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE8_SHIFT))&EPDC_HIST16_PARAM2_VALUE8_MASK) +#define EPDC_HIST16_PARAM2_VALUE9_MASK 0x1F00u +#define EPDC_HIST16_PARAM2_VALUE9_SHIFT 8 +#define EPDC_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE9_SHIFT))&EPDC_HIST16_PARAM2_VALUE9_MASK) +#define EPDC_HIST16_PARAM2_VALUE10_MASK 0x1F0000u +#define EPDC_HIST16_PARAM2_VALUE10_SHIFT 16 +#define EPDC_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE10_SHIFT))&EPDC_HIST16_PARAM2_VALUE10_MASK) +#define EPDC_HIST16_PARAM2_VALUE11_MASK 0x1F000000u +#define EPDC_HIST16_PARAM2_VALUE11_SHIFT 24 +#define EPDC_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM2_VALUE11_SHIFT))&EPDC_HIST16_PARAM2_VALUE11_MASK) +/* HIST16_PARAM3 Bit Fields */ +#define EPDC_HIST16_PARAM3_VALUE12_MASK 0x1Fu +#define EPDC_HIST16_PARAM3_VALUE12_SHIFT 0 +#define EPDC_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE12_SHIFT))&EPDC_HIST16_PARAM3_VALUE12_MASK) +#define EPDC_HIST16_PARAM3_VALUE13_MASK 0x1F00u +#define EPDC_HIST16_PARAM3_VALUE13_SHIFT 8 +#define EPDC_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE13_SHIFT))&EPDC_HIST16_PARAM3_VALUE13_MASK) +#define EPDC_HIST16_PARAM3_VALUE14_MASK 0x1F0000u +#define EPDC_HIST16_PARAM3_VALUE14_SHIFT 16 +#define EPDC_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE14_SHIFT))&EPDC_HIST16_PARAM3_VALUE14_MASK) +#define EPDC_HIST16_PARAM3_VALUE15_MASK 0x1F000000u +#define EPDC_HIST16_PARAM3_VALUE15_SHIFT 24 +#define EPDC_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x))<<EPDC_HIST16_PARAM3_VALUE15_SHIFT))&EPDC_HIST16_PARAM3_VALUE15_MASK) +/* GPIO Bit Fields */ +#define EPDC_GPIO_BDR_MASK 0x3u +#define EPDC_GPIO_BDR_SHIFT 0 +#define EPDC_GPIO_BDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_BDR_SHIFT))&EPDC_GPIO_BDR_MASK) +#define EPDC_GPIO_PWRCTRL_MASK 0x3Cu +#define EPDC_GPIO_PWRCTRL_SHIFT 2 +#define EPDC_GPIO_PWRCTRL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_PWRCTRL_SHIFT))&EPDC_GPIO_PWRCTRL_MASK) +#define EPDC_GPIO_PWRCOM_MASK 0x40u +#define EPDC_GPIO_PWRCOM_SHIFT 6 +#define EPDC_GPIO_PWRWAKE_MASK 0x80u +#define EPDC_GPIO_PWRWAKE_SHIFT 7 +#define EPDC_GPIO_PWRSTAT_MASK 0x100u +#define EPDC_GPIO_PWRSTAT_SHIFT 8 +/* GPIO_SET Bit Fields */ +#define EPDC_GPIO_SET_BDR_MASK 0x3u +#define EPDC_GPIO_SET_BDR_SHIFT 0 +#define EPDC_GPIO_SET_BDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_SET_BDR_SHIFT))&EPDC_GPIO_SET_BDR_MASK) +#define EPDC_GPIO_SET_PWRCTRL_MASK 0x3Cu +#define EPDC_GPIO_SET_PWRCTRL_SHIFT 2 +#define EPDC_GPIO_SET_PWRCTRL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_SET_PWRCTRL_SHIFT))&EPDC_GPIO_SET_PWRCTRL_MASK) +#define EPDC_GPIO_SET_PWRCOM_MASK 0x40u +#define EPDC_GPIO_SET_PWRCOM_SHIFT 6 +#define EPDC_GPIO_SET_PWRWAKE_MASK 0x80u +#define EPDC_GPIO_SET_PWRWAKE_SHIFT 7 +#define EPDC_GPIO_SET_PWRSTAT_MASK 0x100u +#define EPDC_GPIO_SET_PWRSTAT_SHIFT 8 +/* GPIO_CLR Bit Fields */ +#define EPDC_GPIO_CLR_BDR_MASK 0x3u +#define EPDC_GPIO_CLR_BDR_SHIFT 0 +#define EPDC_GPIO_CLR_BDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_CLR_BDR_SHIFT))&EPDC_GPIO_CLR_BDR_MASK) +#define EPDC_GPIO_CLR_PWRCTRL_MASK 0x3Cu +#define EPDC_GPIO_CLR_PWRCTRL_SHIFT 2 +#define EPDC_GPIO_CLR_PWRCTRL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_CLR_PWRCTRL_SHIFT))&EPDC_GPIO_CLR_PWRCTRL_MASK) +#define EPDC_GPIO_CLR_PWRCOM_MASK 0x40u +#define EPDC_GPIO_CLR_PWRCOM_SHIFT 6 +#define EPDC_GPIO_CLR_PWRWAKE_MASK 0x80u +#define EPDC_GPIO_CLR_PWRWAKE_SHIFT 7 +#define EPDC_GPIO_CLR_PWRSTAT_MASK 0x100u +#define EPDC_GPIO_CLR_PWRSTAT_SHIFT 8 +/* GPIO_TOG Bit Fields */ +#define EPDC_GPIO_TOG_BDR_MASK 0x3u +#define EPDC_GPIO_TOG_BDR_SHIFT 0 +#define EPDC_GPIO_TOG_BDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_TOG_BDR_SHIFT))&EPDC_GPIO_TOG_BDR_MASK) +#define EPDC_GPIO_TOG_PWRCTRL_MASK 0x3Cu +#define EPDC_GPIO_TOG_PWRCTRL_SHIFT 2 +#define EPDC_GPIO_TOG_PWRCTRL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_GPIO_TOG_PWRCTRL_SHIFT))&EPDC_GPIO_TOG_PWRCTRL_MASK) +#define EPDC_GPIO_TOG_PWRCOM_MASK 0x40u +#define EPDC_GPIO_TOG_PWRCOM_SHIFT 6 +#define EPDC_GPIO_TOG_PWRWAKE_MASK 0x80u +#define EPDC_GPIO_TOG_PWRWAKE_SHIFT 7 +#define EPDC_GPIO_TOG_PWRSTAT_MASK 0x100u +#define EPDC_GPIO_TOG_PWRSTAT_SHIFT 8 +/* VERSION Bit Fields */ +#define EPDC_VERSION_STEP_MASK 0xFFFFu +#define EPDC_VERSION_STEP_SHIFT 0 +#define EPDC_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<EPDC_VERSION_STEP_SHIFT))&EPDC_VERSION_STEP_MASK) +#define EPDC_VERSION_MINOR_MASK 0xFF0000u +#define EPDC_VERSION_MINOR_SHIFT 16 +#define EPDC_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_VERSION_MINOR_SHIFT))&EPDC_VERSION_MINOR_MASK) +#define EPDC_VERSION_MAJOR_MASK 0xFF000000u +#define EPDC_VERSION_MAJOR_SHIFT 24 +#define EPDC_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_VERSION_MAJOR_SHIFT))&EPDC_VERSION_MAJOR_MASK) +/* PIGEON_0_0 Bit Fields */ +#define EPDC_PIGEON_0_0_EN_MASK 0x1u +#define EPDC_PIGEON_0_0_EN_SHIFT 0 +#define EPDC_PIGEON_0_0_POL_MASK 0x2u +#define EPDC_PIGEON_0_0_POL_SHIFT 1 +#define EPDC_PIGEON_0_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_0_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_0_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_INC_SEL_SHIFT))&EPDC_PIGEON_0_0_INC_SEL_MASK) +#define EPDC_PIGEON_0_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_0_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_0_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_OFFSET_SHIFT))&EPDC_PIGEON_0_0_OFFSET_MASK) +#define EPDC_PIGEON_0_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_0_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_0_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_0_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_0_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_0_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_0_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_MASK_CNT_SHIFT))&EPDC_PIGEON_0_0_MASK_CNT_MASK) +#define EPDC_PIGEON_0_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_0_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_0_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_0_STATE_MASK_SHIFT))&EPDC_PIGEON_0_0_STATE_MASK_MASK) +/* PIGEON_0_1 Bit Fields */ +#define EPDC_PIGEON_0_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_0_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_0_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_1_SET_CNT_SHIFT))&EPDC_PIGEON_0_1_SET_CNT_MASK) +#define EPDC_PIGEON_0_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_0_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_0_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_1_CLR_CNT_SHIFT))&EPDC_PIGEON_0_1_CLR_CNT_MASK) +/* PIGEON_0_2 Bit Fields */ +#define EPDC_PIGEON_0_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_0_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_0_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_0_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_0_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_0_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_0_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_0_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_0_2_SIG_ANOTHER_MASK) +/* PIGEON_1_0 Bit Fields */ +#define EPDC_PIGEON_1_0_EN_MASK 0x1u +#define EPDC_PIGEON_1_0_EN_SHIFT 0 +#define EPDC_PIGEON_1_0_POL_MASK 0x2u +#define EPDC_PIGEON_1_0_POL_SHIFT 1 +#define EPDC_PIGEON_1_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_1_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_1_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_INC_SEL_SHIFT))&EPDC_PIGEON_1_0_INC_SEL_MASK) +#define EPDC_PIGEON_1_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_1_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_1_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_OFFSET_SHIFT))&EPDC_PIGEON_1_0_OFFSET_MASK) +#define EPDC_PIGEON_1_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_1_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_1_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_1_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_1_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_1_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_1_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_MASK_CNT_SHIFT))&EPDC_PIGEON_1_0_MASK_CNT_MASK) +#define EPDC_PIGEON_1_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_1_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_1_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_0_STATE_MASK_SHIFT))&EPDC_PIGEON_1_0_STATE_MASK_MASK) +/* PIGEON_1_1 Bit Fields */ +#define EPDC_PIGEON_1_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_1_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_1_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_1_SET_CNT_SHIFT))&EPDC_PIGEON_1_1_SET_CNT_MASK) +#define EPDC_PIGEON_1_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_1_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_1_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_1_CLR_CNT_SHIFT))&EPDC_PIGEON_1_1_CLR_CNT_MASK) +/* PIGEON_1_2 Bit Fields */ +#define EPDC_PIGEON_1_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_1_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_1_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_1_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_1_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_1_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_1_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_1_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_1_2_SIG_ANOTHER_MASK) +/* PIGEON_2_0 Bit Fields */ +#define EPDC_PIGEON_2_0_EN_MASK 0x1u +#define EPDC_PIGEON_2_0_EN_SHIFT 0 +#define EPDC_PIGEON_2_0_POL_MASK 0x2u +#define EPDC_PIGEON_2_0_POL_SHIFT 1 +#define EPDC_PIGEON_2_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_2_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_2_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_INC_SEL_SHIFT))&EPDC_PIGEON_2_0_INC_SEL_MASK) +#define EPDC_PIGEON_2_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_2_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_2_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_OFFSET_SHIFT))&EPDC_PIGEON_2_0_OFFSET_MASK) +#define EPDC_PIGEON_2_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_2_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_2_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_2_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_2_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_2_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_2_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_MASK_CNT_SHIFT))&EPDC_PIGEON_2_0_MASK_CNT_MASK) +#define EPDC_PIGEON_2_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_2_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_2_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_0_STATE_MASK_SHIFT))&EPDC_PIGEON_2_0_STATE_MASK_MASK) +/* PIGEON_2_1 Bit Fields */ +#define EPDC_PIGEON_2_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_2_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_2_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_1_SET_CNT_SHIFT))&EPDC_PIGEON_2_1_SET_CNT_MASK) +#define EPDC_PIGEON_2_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_2_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_2_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_1_CLR_CNT_SHIFT))&EPDC_PIGEON_2_1_CLR_CNT_MASK) +/* PIGEON_2_2 Bit Fields */ +#define EPDC_PIGEON_2_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_2_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_2_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_2_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_2_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_2_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_2_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_2_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_2_2_SIG_ANOTHER_MASK) +/* PIGEON_3_0 Bit Fields */ +#define EPDC_PIGEON_3_0_EN_MASK 0x1u +#define EPDC_PIGEON_3_0_EN_SHIFT 0 +#define EPDC_PIGEON_3_0_POL_MASK 0x2u +#define EPDC_PIGEON_3_0_POL_SHIFT 1 +#define EPDC_PIGEON_3_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_3_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_3_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_INC_SEL_SHIFT))&EPDC_PIGEON_3_0_INC_SEL_MASK) +#define EPDC_PIGEON_3_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_3_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_3_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_OFFSET_SHIFT))&EPDC_PIGEON_3_0_OFFSET_MASK) +#define EPDC_PIGEON_3_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_3_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_3_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_3_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_3_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_3_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_3_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_MASK_CNT_SHIFT))&EPDC_PIGEON_3_0_MASK_CNT_MASK) +#define EPDC_PIGEON_3_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_3_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_3_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_0_STATE_MASK_SHIFT))&EPDC_PIGEON_3_0_STATE_MASK_MASK) +/* PIGEON_3_1 Bit Fields */ +#define EPDC_PIGEON_3_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_3_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_3_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_1_SET_CNT_SHIFT))&EPDC_PIGEON_3_1_SET_CNT_MASK) +#define EPDC_PIGEON_3_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_3_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_3_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_1_CLR_CNT_SHIFT))&EPDC_PIGEON_3_1_CLR_CNT_MASK) +/* PIGEON_3_2 Bit Fields */ +#define EPDC_PIGEON_3_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_3_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_3_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_3_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_3_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_3_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_3_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_3_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_3_2_SIG_ANOTHER_MASK) +/* PIGEON_4_0 Bit Fields */ +#define EPDC_PIGEON_4_0_EN_MASK 0x1u +#define EPDC_PIGEON_4_0_EN_SHIFT 0 +#define EPDC_PIGEON_4_0_POL_MASK 0x2u +#define EPDC_PIGEON_4_0_POL_SHIFT 1 +#define EPDC_PIGEON_4_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_4_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_4_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_INC_SEL_SHIFT))&EPDC_PIGEON_4_0_INC_SEL_MASK) +#define EPDC_PIGEON_4_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_4_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_4_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_OFFSET_SHIFT))&EPDC_PIGEON_4_0_OFFSET_MASK) +#define EPDC_PIGEON_4_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_4_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_4_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_4_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_4_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_4_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_4_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_MASK_CNT_SHIFT))&EPDC_PIGEON_4_0_MASK_CNT_MASK) +#define EPDC_PIGEON_4_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_4_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_4_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_0_STATE_MASK_SHIFT))&EPDC_PIGEON_4_0_STATE_MASK_MASK) +/* PIGEON_4_1 Bit Fields */ +#define EPDC_PIGEON_4_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_4_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_4_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_1_SET_CNT_SHIFT))&EPDC_PIGEON_4_1_SET_CNT_MASK) +#define EPDC_PIGEON_4_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_4_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_4_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_1_CLR_CNT_SHIFT))&EPDC_PIGEON_4_1_CLR_CNT_MASK) +/* PIGEON_4_2 Bit Fields */ +#define EPDC_PIGEON_4_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_4_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_4_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_4_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_4_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_4_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_4_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_4_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_4_2_SIG_ANOTHER_MASK) +/* PIGEON_5_0 Bit Fields */ +#define EPDC_PIGEON_5_0_EN_MASK 0x1u +#define EPDC_PIGEON_5_0_EN_SHIFT 0 +#define EPDC_PIGEON_5_0_POL_MASK 0x2u +#define EPDC_PIGEON_5_0_POL_SHIFT 1 +#define EPDC_PIGEON_5_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_5_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_5_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_INC_SEL_SHIFT))&EPDC_PIGEON_5_0_INC_SEL_MASK) +#define EPDC_PIGEON_5_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_5_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_5_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_OFFSET_SHIFT))&EPDC_PIGEON_5_0_OFFSET_MASK) +#define EPDC_PIGEON_5_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_5_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_5_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_5_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_5_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_5_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_5_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_MASK_CNT_SHIFT))&EPDC_PIGEON_5_0_MASK_CNT_MASK) +#define EPDC_PIGEON_5_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_5_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_5_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_0_STATE_MASK_SHIFT))&EPDC_PIGEON_5_0_STATE_MASK_MASK) +/* PIGEON_5_1 Bit Fields */ +#define EPDC_PIGEON_5_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_5_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_5_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_1_SET_CNT_SHIFT))&EPDC_PIGEON_5_1_SET_CNT_MASK) +#define EPDC_PIGEON_5_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_5_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_5_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_1_CLR_CNT_SHIFT))&EPDC_PIGEON_5_1_CLR_CNT_MASK) +/* PIGEON_5_2 Bit Fields */ +#define EPDC_PIGEON_5_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_5_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_5_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_5_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_5_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_5_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_5_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_5_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_5_2_SIG_ANOTHER_MASK) +/* PIGEON_6_0 Bit Fields */ +#define EPDC_PIGEON_6_0_EN_MASK 0x1u +#define EPDC_PIGEON_6_0_EN_SHIFT 0 +#define EPDC_PIGEON_6_0_POL_MASK 0x2u +#define EPDC_PIGEON_6_0_POL_SHIFT 1 +#define EPDC_PIGEON_6_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_6_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_6_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_INC_SEL_SHIFT))&EPDC_PIGEON_6_0_INC_SEL_MASK) +#define EPDC_PIGEON_6_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_6_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_6_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_OFFSET_SHIFT))&EPDC_PIGEON_6_0_OFFSET_MASK) +#define EPDC_PIGEON_6_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_6_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_6_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_6_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_6_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_6_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_6_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_MASK_CNT_SHIFT))&EPDC_PIGEON_6_0_MASK_CNT_MASK) +#define EPDC_PIGEON_6_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_6_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_6_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_0_STATE_MASK_SHIFT))&EPDC_PIGEON_6_0_STATE_MASK_MASK) +/* PIGEON_6_1 Bit Fields */ +#define EPDC_PIGEON_6_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_6_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_6_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_1_SET_CNT_SHIFT))&EPDC_PIGEON_6_1_SET_CNT_MASK) +#define EPDC_PIGEON_6_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_6_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_6_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_1_CLR_CNT_SHIFT))&EPDC_PIGEON_6_1_CLR_CNT_MASK) +/* PIGEON_6_2 Bit Fields */ +#define EPDC_PIGEON_6_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_6_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_6_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_6_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_6_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_6_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_6_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_6_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_6_2_SIG_ANOTHER_MASK) +/* PIGEON_7_0 Bit Fields */ +#define EPDC_PIGEON_7_0_EN_MASK 0x1u +#define EPDC_PIGEON_7_0_EN_SHIFT 0 +#define EPDC_PIGEON_7_0_POL_MASK 0x2u +#define EPDC_PIGEON_7_0_POL_SHIFT 1 +#define EPDC_PIGEON_7_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_7_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_7_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_INC_SEL_SHIFT))&EPDC_PIGEON_7_0_INC_SEL_MASK) +#define EPDC_PIGEON_7_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_7_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_7_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_OFFSET_SHIFT))&EPDC_PIGEON_7_0_OFFSET_MASK) +#define EPDC_PIGEON_7_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_7_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_7_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_7_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_7_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_7_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_7_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_MASK_CNT_SHIFT))&EPDC_PIGEON_7_0_MASK_CNT_MASK) +#define EPDC_PIGEON_7_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_7_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_7_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_0_STATE_MASK_SHIFT))&EPDC_PIGEON_7_0_STATE_MASK_MASK) +/* PIGEON_7_1 Bit Fields */ +#define EPDC_PIGEON_7_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_7_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_7_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_1_SET_CNT_SHIFT))&EPDC_PIGEON_7_1_SET_CNT_MASK) +#define EPDC_PIGEON_7_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_7_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_7_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_1_CLR_CNT_SHIFT))&EPDC_PIGEON_7_1_CLR_CNT_MASK) +/* PIGEON_7_2 Bit Fields */ +#define EPDC_PIGEON_7_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_7_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_7_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_7_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_7_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_7_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_7_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_7_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_7_2_SIG_ANOTHER_MASK) +/* PIGEON_8_0 Bit Fields */ +#define EPDC_PIGEON_8_0_EN_MASK 0x1u +#define EPDC_PIGEON_8_0_EN_SHIFT 0 +#define EPDC_PIGEON_8_0_POL_MASK 0x2u +#define EPDC_PIGEON_8_0_POL_SHIFT 1 +#define EPDC_PIGEON_8_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_8_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_8_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_INC_SEL_SHIFT))&EPDC_PIGEON_8_0_INC_SEL_MASK) +#define EPDC_PIGEON_8_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_8_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_8_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_OFFSET_SHIFT))&EPDC_PIGEON_8_0_OFFSET_MASK) +#define EPDC_PIGEON_8_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_8_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_8_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_8_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_8_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_8_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_8_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_MASK_CNT_SHIFT))&EPDC_PIGEON_8_0_MASK_CNT_MASK) +#define EPDC_PIGEON_8_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_8_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_8_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_0_STATE_MASK_SHIFT))&EPDC_PIGEON_8_0_STATE_MASK_MASK) +/* PIGEON_8_1 Bit Fields */ +#define EPDC_PIGEON_8_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_8_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_8_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_1_SET_CNT_SHIFT))&EPDC_PIGEON_8_1_SET_CNT_MASK) +#define EPDC_PIGEON_8_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_8_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_8_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_1_CLR_CNT_SHIFT))&EPDC_PIGEON_8_1_CLR_CNT_MASK) +/* PIGEON_8_2 Bit Fields */ +#define EPDC_PIGEON_8_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_8_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_8_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_8_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_8_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_8_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_8_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_8_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_8_2_SIG_ANOTHER_MASK) +/* PIGEON_9_0 Bit Fields */ +#define EPDC_PIGEON_9_0_EN_MASK 0x1u +#define EPDC_PIGEON_9_0_EN_SHIFT 0 +#define EPDC_PIGEON_9_0_POL_MASK 0x2u +#define EPDC_PIGEON_9_0_POL_SHIFT 1 +#define EPDC_PIGEON_9_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_9_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_9_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_INC_SEL_SHIFT))&EPDC_PIGEON_9_0_INC_SEL_MASK) +#define EPDC_PIGEON_9_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_9_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_9_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_OFFSET_SHIFT))&EPDC_PIGEON_9_0_OFFSET_MASK) +#define EPDC_PIGEON_9_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_9_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_9_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_9_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_9_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_9_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_9_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_MASK_CNT_SHIFT))&EPDC_PIGEON_9_0_MASK_CNT_MASK) +#define EPDC_PIGEON_9_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_9_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_9_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_0_STATE_MASK_SHIFT))&EPDC_PIGEON_9_0_STATE_MASK_MASK) +/* PIGEON_9_1 Bit Fields */ +#define EPDC_PIGEON_9_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_9_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_9_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_1_SET_CNT_SHIFT))&EPDC_PIGEON_9_1_SET_CNT_MASK) +#define EPDC_PIGEON_9_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_9_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_9_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_1_CLR_CNT_SHIFT))&EPDC_PIGEON_9_1_CLR_CNT_MASK) +/* PIGEON_9_2 Bit Fields */ +#define EPDC_PIGEON_9_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_9_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_9_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_9_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_9_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_9_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_9_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_9_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_9_2_SIG_ANOTHER_MASK) +/* PIGEON_10_0 Bit Fields */ +#define EPDC_PIGEON_10_0_EN_MASK 0x1u +#define EPDC_PIGEON_10_0_EN_SHIFT 0 +#define EPDC_PIGEON_10_0_POL_MASK 0x2u +#define EPDC_PIGEON_10_0_POL_SHIFT 1 +#define EPDC_PIGEON_10_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_10_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_10_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_INC_SEL_SHIFT))&EPDC_PIGEON_10_0_INC_SEL_MASK) +#define EPDC_PIGEON_10_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_10_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_10_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_OFFSET_SHIFT))&EPDC_PIGEON_10_0_OFFSET_MASK) +#define EPDC_PIGEON_10_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_10_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_10_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_10_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_10_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_10_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_10_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_MASK_CNT_SHIFT))&EPDC_PIGEON_10_0_MASK_CNT_MASK) +#define EPDC_PIGEON_10_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_10_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_10_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_0_STATE_MASK_SHIFT))&EPDC_PIGEON_10_0_STATE_MASK_MASK) +/* PIGEON_10_1 Bit Fields */ +#define EPDC_PIGEON_10_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_10_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_10_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_1_SET_CNT_SHIFT))&EPDC_PIGEON_10_1_SET_CNT_MASK) +#define EPDC_PIGEON_10_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_10_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_10_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_1_CLR_CNT_SHIFT))&EPDC_PIGEON_10_1_CLR_CNT_MASK) +/* PIGEON_10_2 Bit Fields */ +#define EPDC_PIGEON_10_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_10_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_10_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_10_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_10_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_10_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_10_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_10_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_10_2_SIG_ANOTHER_MASK) +/* PIGEON_11_0 Bit Fields */ +#define EPDC_PIGEON_11_0_EN_MASK 0x1u +#define EPDC_PIGEON_11_0_EN_SHIFT 0 +#define EPDC_PIGEON_11_0_POL_MASK 0x2u +#define EPDC_PIGEON_11_0_POL_SHIFT 1 +#define EPDC_PIGEON_11_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_11_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_11_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_INC_SEL_SHIFT))&EPDC_PIGEON_11_0_INC_SEL_MASK) +#define EPDC_PIGEON_11_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_11_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_11_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_OFFSET_SHIFT))&EPDC_PIGEON_11_0_OFFSET_MASK) +#define EPDC_PIGEON_11_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_11_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_11_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_11_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_11_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_11_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_11_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_MASK_CNT_SHIFT))&EPDC_PIGEON_11_0_MASK_CNT_MASK) +#define EPDC_PIGEON_11_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_11_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_11_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_0_STATE_MASK_SHIFT))&EPDC_PIGEON_11_0_STATE_MASK_MASK) +/* PIGEON_11_1 Bit Fields */ +#define EPDC_PIGEON_11_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_11_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_11_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_1_SET_CNT_SHIFT))&EPDC_PIGEON_11_1_SET_CNT_MASK) +#define EPDC_PIGEON_11_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_11_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_11_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_1_CLR_CNT_SHIFT))&EPDC_PIGEON_11_1_CLR_CNT_MASK) +/* PIGEON_11_2 Bit Fields */ +#define EPDC_PIGEON_11_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_11_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_11_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_11_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_11_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_11_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_11_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_11_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_11_2_SIG_ANOTHER_MASK) +/* PIGEON_12_0 Bit Fields */ +#define EPDC_PIGEON_12_0_EN_MASK 0x1u +#define EPDC_PIGEON_12_0_EN_SHIFT 0 +#define EPDC_PIGEON_12_0_POL_MASK 0x2u +#define EPDC_PIGEON_12_0_POL_SHIFT 1 +#define EPDC_PIGEON_12_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_12_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_12_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_INC_SEL_SHIFT))&EPDC_PIGEON_12_0_INC_SEL_MASK) +#define EPDC_PIGEON_12_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_12_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_12_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_OFFSET_SHIFT))&EPDC_PIGEON_12_0_OFFSET_MASK) +#define EPDC_PIGEON_12_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_12_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_12_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_12_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_12_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_12_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_12_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_MASK_CNT_SHIFT))&EPDC_PIGEON_12_0_MASK_CNT_MASK) +#define EPDC_PIGEON_12_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_12_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_12_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_0_STATE_MASK_SHIFT))&EPDC_PIGEON_12_0_STATE_MASK_MASK) +/* PIGEON_12_1 Bit Fields */ +#define EPDC_PIGEON_12_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_12_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_12_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_1_SET_CNT_SHIFT))&EPDC_PIGEON_12_1_SET_CNT_MASK) +#define EPDC_PIGEON_12_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_12_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_12_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_1_CLR_CNT_SHIFT))&EPDC_PIGEON_12_1_CLR_CNT_MASK) +/* PIGEON_12_2 Bit Fields */ +#define EPDC_PIGEON_12_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_12_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_12_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_12_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_12_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_12_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_12_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_12_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_12_2_SIG_ANOTHER_MASK) +/* PIGEON_13_0 Bit Fields */ +#define EPDC_PIGEON_13_0_EN_MASK 0x1u +#define EPDC_PIGEON_13_0_EN_SHIFT 0 +#define EPDC_PIGEON_13_0_POL_MASK 0x2u +#define EPDC_PIGEON_13_0_POL_SHIFT 1 +#define EPDC_PIGEON_13_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_13_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_13_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_INC_SEL_SHIFT))&EPDC_PIGEON_13_0_INC_SEL_MASK) +#define EPDC_PIGEON_13_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_13_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_13_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_OFFSET_SHIFT))&EPDC_PIGEON_13_0_OFFSET_MASK) +#define EPDC_PIGEON_13_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_13_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_13_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_13_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_13_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_13_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_13_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_MASK_CNT_SHIFT))&EPDC_PIGEON_13_0_MASK_CNT_MASK) +#define EPDC_PIGEON_13_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_13_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_13_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_0_STATE_MASK_SHIFT))&EPDC_PIGEON_13_0_STATE_MASK_MASK) +/* PIGEON_13_1 Bit Fields */ +#define EPDC_PIGEON_13_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_13_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_13_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_1_SET_CNT_SHIFT))&EPDC_PIGEON_13_1_SET_CNT_MASK) +#define EPDC_PIGEON_13_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_13_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_13_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_1_CLR_CNT_SHIFT))&EPDC_PIGEON_13_1_CLR_CNT_MASK) +/* PIGEON_13_2 Bit Fields */ +#define EPDC_PIGEON_13_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_13_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_13_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_13_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_13_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_13_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_13_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_13_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_13_2_SIG_ANOTHER_MASK) +/* PIGEON_14_0 Bit Fields */ +#define EPDC_PIGEON_14_0_EN_MASK 0x1u +#define EPDC_PIGEON_14_0_EN_SHIFT 0 +#define EPDC_PIGEON_14_0_POL_MASK 0x2u +#define EPDC_PIGEON_14_0_POL_SHIFT 1 +#define EPDC_PIGEON_14_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_14_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_14_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_INC_SEL_SHIFT))&EPDC_PIGEON_14_0_INC_SEL_MASK) +#define EPDC_PIGEON_14_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_14_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_14_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_OFFSET_SHIFT))&EPDC_PIGEON_14_0_OFFSET_MASK) +#define EPDC_PIGEON_14_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_14_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_14_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_14_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_14_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_14_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_14_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_MASK_CNT_SHIFT))&EPDC_PIGEON_14_0_MASK_CNT_MASK) +#define EPDC_PIGEON_14_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_14_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_14_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_0_STATE_MASK_SHIFT))&EPDC_PIGEON_14_0_STATE_MASK_MASK) +/* PIGEON_14_1 Bit Fields */ +#define EPDC_PIGEON_14_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_14_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_14_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_1_SET_CNT_SHIFT))&EPDC_PIGEON_14_1_SET_CNT_MASK) +#define EPDC_PIGEON_14_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_14_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_14_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_1_CLR_CNT_SHIFT))&EPDC_PIGEON_14_1_CLR_CNT_MASK) +/* PIGEON_14_2 Bit Fields */ +#define EPDC_PIGEON_14_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_14_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_14_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_14_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_14_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_14_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_14_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_14_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_14_2_SIG_ANOTHER_MASK) +/* PIGEON_15_0 Bit Fields */ +#define EPDC_PIGEON_15_0_EN_MASK 0x1u +#define EPDC_PIGEON_15_0_EN_SHIFT 0 +#define EPDC_PIGEON_15_0_POL_MASK 0x2u +#define EPDC_PIGEON_15_0_POL_SHIFT 1 +#define EPDC_PIGEON_15_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_15_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_15_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_INC_SEL_SHIFT))&EPDC_PIGEON_15_0_INC_SEL_MASK) +#define EPDC_PIGEON_15_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_15_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_15_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_OFFSET_SHIFT))&EPDC_PIGEON_15_0_OFFSET_MASK) +#define EPDC_PIGEON_15_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_15_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_15_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_15_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_15_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_15_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_15_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_MASK_CNT_SHIFT))&EPDC_PIGEON_15_0_MASK_CNT_MASK) +#define EPDC_PIGEON_15_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_15_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_15_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_0_STATE_MASK_SHIFT))&EPDC_PIGEON_15_0_STATE_MASK_MASK) +/* PIGEON_15_1 Bit Fields */ +#define EPDC_PIGEON_15_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_15_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_15_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_1_SET_CNT_SHIFT))&EPDC_PIGEON_15_1_SET_CNT_MASK) +#define EPDC_PIGEON_15_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_15_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_15_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_1_CLR_CNT_SHIFT))&EPDC_PIGEON_15_1_CLR_CNT_MASK) +/* PIGEON_15_2 Bit Fields */ +#define EPDC_PIGEON_15_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_15_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_15_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_15_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_15_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_15_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_15_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_15_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_15_2_SIG_ANOTHER_MASK) +/* PIGEON_16_0 Bit Fields */ +#define EPDC_PIGEON_16_0_EN_MASK 0x1u +#define EPDC_PIGEON_16_0_EN_SHIFT 0 +#define EPDC_PIGEON_16_0_POL_MASK 0x2u +#define EPDC_PIGEON_16_0_POL_SHIFT 1 +#define EPDC_PIGEON_16_0_INC_SEL_MASK 0xCu +#define EPDC_PIGEON_16_0_INC_SEL_SHIFT 2 +#define EPDC_PIGEON_16_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_INC_SEL_SHIFT))&EPDC_PIGEON_16_0_INC_SEL_MASK) +#define EPDC_PIGEON_16_0_OFFSET_MASK 0xF0u +#define EPDC_PIGEON_16_0_OFFSET_SHIFT 4 +#define EPDC_PIGEON_16_0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_OFFSET_SHIFT))&EPDC_PIGEON_16_0_OFFSET_MASK) +#define EPDC_PIGEON_16_0_MASK_CNT_SEL_MASK 0xF00u +#define EPDC_PIGEON_16_0_MASK_CNT_SEL_SHIFT 8 +#define EPDC_PIGEON_16_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_MASK_CNT_SEL_SHIFT))&EPDC_PIGEON_16_0_MASK_CNT_SEL_MASK) +#define EPDC_PIGEON_16_0_MASK_CNT_MASK 0xFFF000u +#define EPDC_PIGEON_16_0_MASK_CNT_SHIFT 12 +#define EPDC_PIGEON_16_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_MASK_CNT_SHIFT))&EPDC_PIGEON_16_0_MASK_CNT_MASK) +#define EPDC_PIGEON_16_0_STATE_MASK_MASK 0xFF000000u +#define EPDC_PIGEON_16_0_STATE_MASK_SHIFT 24 +#define EPDC_PIGEON_16_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_0_STATE_MASK_SHIFT))&EPDC_PIGEON_16_0_STATE_MASK_MASK) +/* PIGEON_16_1 Bit Fields */ +#define EPDC_PIGEON_16_1_SET_CNT_MASK 0xFFFFu +#define EPDC_PIGEON_16_1_SET_CNT_SHIFT 0 +#define EPDC_PIGEON_16_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_1_SET_CNT_SHIFT))&EPDC_PIGEON_16_1_SET_CNT_MASK) +#define EPDC_PIGEON_16_1_CLR_CNT_MASK 0xFFFF0000u +#define EPDC_PIGEON_16_1_CLR_CNT_SHIFT 16 +#define EPDC_PIGEON_16_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_1_CLR_CNT_SHIFT))&EPDC_PIGEON_16_1_CLR_CNT_MASK) +/* WB_ADDR_TCE Bit Fields */ +#define EPDC_WB_ADDR_TCE_ADDR_MASK 0xFFFFFFFFu +#define EPDC_WB_ADDR_TCE_ADDR_SHIFT 0 +#define EPDC_WB_ADDR_TCE_ADDR(x) (((uint32_t)(((uint32_t)(x))<<EPDC_WB_ADDR_TCE_ADDR_SHIFT))&EPDC_WB_ADDR_TCE_ADDR_MASK) +/* PIGEON_16_2 Bit Fields */ +#define EPDC_PIGEON_16_2_SIG_LOGIC_MASK 0xFu +#define EPDC_PIGEON_16_2_SIG_LOGIC_SHIFT 0 +#define EPDC_PIGEON_16_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_2_SIG_LOGIC_SHIFT))&EPDC_PIGEON_16_2_SIG_LOGIC_MASK) +#define EPDC_PIGEON_16_2_SIG_ANOTHER_MASK 0x1F0u +#define EPDC_PIGEON_16_2_SIG_ANOTHER_SHIFT 4 +#define EPDC_PIGEON_16_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x))<<EPDC_PIGEON_16_2_SIG_ANOTHER_SHIFT))&EPDC_PIGEON_16_2_SIG_ANOTHER_MASK) + +/*! + * @} + */ /* end of group EPDC_Register_Masks */ + + +/* EPDC - Peripheral instance base addresses */ +/** Peripheral EPDC base address */ +#define EPDC_BASE (0x306F0000u) +/** Peripheral EPDC base pointer */ +#define EPDC ((EPDC_Type *)EPDC_BASE) +#define EPDC_BASE_PTR (EPDC) +/** Array initializer of EPDC peripheral base adresses */ +#define EPDC_BASE_ADDRS { EPDC_BASE } +/** Array initializer of EPDC peripheral base pointers */ +#define EPDC_BASE_PTRS { EPDC } + +/* ---------------------------------------------------------------------------- + -- EPDC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPDC_Register_Accessor_Macros EPDC - Register accessor macros + * @{ + */ + + +/* EPDC - Register instance definitions */ +/* EPDC */ +#define EPDC_CTRL EPDC_CTRL_REG(EPDC_BASE_PTR) +#define EPDC_CTRL_SET EPDC_CTRL_SET_REG(EPDC_BASE_PTR) +#define EPDC_CTRL_CLR EPDC_CTRL_CLR_REG(EPDC_BASE_PTR) +#define EPDC_CTRL_TOG EPDC_CTRL_TOG_REG(EPDC_BASE_PTR) +#define EPDC_WVADDR EPDC_WVADDR_REG(EPDC_BASE_PTR) +#define EPDC_WB_ADDR EPDC_WB_ADDR_REG(EPDC_BASE_PTR) +#define EPDC_RES EPDC_RES_REG(EPDC_BASE_PTR) +#define EPDC_FORMAT EPDC_FORMAT_REG(EPDC_BASE_PTR) +#define EPDC_FORMAT_SET EPDC_FORMAT_SET_REG(EPDC_BASE_PTR) +#define EPDC_FORMAT_CLR EPDC_FORMAT_CLR_REG(EPDC_BASE_PTR) +#define EPDC_FORMAT_TOG EPDC_FORMAT_TOG_REG(EPDC_BASE_PTR) +#define EPDC_FIFOCTRL EPDC_FIFOCTRL_REG(EPDC_BASE_PTR) +#define EPDC_FIFOCTRL_SET EPDC_FIFOCTRL_SET_REG(EPDC_BASE_PTR) +#define EPDC_FIFOCTRL_CLR EPDC_FIFOCTRL_CLR_REG(EPDC_BASE_PTR) +#define EPDC_FIFOCTRL_TOG EPDC_FIFOCTRL_TOG_REG(EPDC_BASE_PTR) +#define EPDC_UPD_ADDR EPDC_UPD_ADDR_REG(EPDC_BASE_PTR) +#define EPDC_UPD_STRIDE EPDC_UPD_STRIDE_REG(EPDC_BASE_PTR) +#define EPDC_UPD_CORD EPDC_UPD_CORD_REG(EPDC_BASE_PTR) +#define EPDC_UPD_SIZE EPDC_UPD_SIZE_REG(EPDC_BASE_PTR) +#define EPDC_UPD_CTRL EPDC_UPD_CTRL_REG(EPDC_BASE_PTR) +#define EPDC_UPD_CTRL_SET EPDC_UPD_CTRL_SET_REG(EPDC_BASE_PTR) +#define EPDC_UPD_CTRL_CLR EPDC_UPD_CTRL_CLR_REG(EPDC_BASE_PTR) +#define EPDC_UPD_CTRL_TOG EPDC_UPD_CTRL_TOG_REG(EPDC_BASE_PTR) +#define EPDC_UPD_FIXED EPDC_UPD_FIXED_REG(EPDC_BASE_PTR) +#define EPDC_UPD_FIXED_SET EPDC_UPD_FIXED_SET_REG(EPDC_BASE_PTR) +#define EPDC_UPD_FIXED_CLR EPDC_UPD_FIXED_CLR_REG(EPDC_BASE_PTR) +#define EPDC_UPD_FIXED_TOG EPDC_UPD_FIXED_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TEMP EPDC_TEMP_REG(EPDC_BASE_PTR) +#define EPDC_AUTOWV_LUT EPDC_AUTOWV_LUT_REG(EPDC_BASE_PTR) +#define EPDC_TCE_CTRL EPDC_TCE_CTRL_REG(EPDC_BASE_PTR) +#define EPDC_TCE_CTRL_SET EPDC_TCE_CTRL_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_CTRL_CLR EPDC_TCE_CTRL_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_CTRL_TOG EPDC_TCE_CTRL_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_SDCFG EPDC_TCE_SDCFG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_SDCFG_SET EPDC_TCE_SDCFG_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_SDCFG_CLR EPDC_TCE_SDCFG_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_SDCFG_TOG EPDC_TCE_SDCFG_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_GDCFG EPDC_TCE_GDCFG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_GDCFG_SET EPDC_TCE_GDCFG_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_GDCFG_CLR EPDC_TCE_GDCFG_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_GDCFG_TOG EPDC_TCE_GDCFG_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN1 EPDC_TCE_HSCAN1_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN1_SET EPDC_TCE_HSCAN1_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN1_CLR EPDC_TCE_HSCAN1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN1_TOG EPDC_TCE_HSCAN1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN2 EPDC_TCE_HSCAN2_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN2_SET EPDC_TCE_HSCAN2_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN2_CLR EPDC_TCE_HSCAN2_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_HSCAN2_TOG EPDC_TCE_HSCAN2_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_VSCAN EPDC_TCE_VSCAN_REG(EPDC_BASE_PTR) +#define EPDC_TCE_VSCAN_SET EPDC_TCE_VSCAN_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_VSCAN_CLR EPDC_TCE_VSCAN_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_VSCAN_TOG EPDC_TCE_VSCAN_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_OE EPDC_TCE_OE_REG(EPDC_BASE_PTR) +#define EPDC_TCE_OE_SET EPDC_TCE_OE_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_OE_CLR EPDC_TCE_OE_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_OE_TOG EPDC_TCE_OE_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_POLARITY EPDC_TCE_POLARITY_REG(EPDC_BASE_PTR) +#define EPDC_TCE_POLARITY_SET EPDC_TCE_POLARITY_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_POLARITY_CLR EPDC_TCE_POLARITY_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_POLARITY_TOG EPDC_TCE_POLARITY_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING1 EPDC_TCE_TIMING1_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING1_SET EPDC_TCE_TIMING1_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING1_CLR EPDC_TCE_TIMING1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING1_TOG EPDC_TCE_TIMING1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING2 EPDC_TCE_TIMING2_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING2_SET EPDC_TCE_TIMING2_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING2_CLR EPDC_TCE_TIMING2_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING2_TOG EPDC_TCE_TIMING2_TOG_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING3 EPDC_TCE_TIMING3_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING3_SET EPDC_TCE_TIMING3_SET_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING3_CLR EPDC_TCE_TIMING3_CLR_REG(EPDC_BASE_PTR) +#define EPDC_TCE_TIMING3_TOG EPDC_TCE_TIMING3_TOG_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL0 EPDC_PIGEON_CTRL0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL0_SET EPDC_PIGEON_CTRL0_SET_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL0_CLR EPDC_PIGEON_CTRL0_CLR_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL0_TOG EPDC_PIGEON_CTRL0_TOG_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL1 EPDC_PIGEON_CTRL1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL1_SET EPDC_PIGEON_CTRL1_SET_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL1_CLR EPDC_PIGEON_CTRL1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_CTRL1_TOG EPDC_PIGEON_CTRL1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK1 EPDC_IRQ_MASK1_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK1_SET EPDC_IRQ_MASK1_SET_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK1_CLR EPDC_IRQ_MASK1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK1_TOG EPDC_IRQ_MASK1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK2 EPDC_IRQ_MASK2_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK2_SET EPDC_IRQ_MASK2_SET_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK2_CLR EPDC_IRQ_MASK2_CLR_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK2_TOG EPDC_IRQ_MASK2_TOG_REG(EPDC_BASE_PTR) +#define EPDC_IRQ1 EPDC_IRQ1_REG(EPDC_BASE_PTR) +#define EPDC_IRQ1_SET EPDC_IRQ1_SET_REG(EPDC_BASE_PTR) +#define EPDC_IRQ1_CLR EPDC_IRQ1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_IRQ1_TOG EPDC_IRQ1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_IRQ2 EPDC_IRQ2_REG(EPDC_BASE_PTR) +#define EPDC_IRQ2_SET EPDC_IRQ2_SET_REG(EPDC_BASE_PTR) +#define EPDC_IRQ2_CLR EPDC_IRQ2_CLR_REG(EPDC_BASE_PTR) +#define EPDC_IRQ2_TOG EPDC_IRQ2_TOG_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK EPDC_IRQ_MASK_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK_SET EPDC_IRQ_MASK_SET_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK_CLR EPDC_IRQ_MASK_CLR_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_MASK_TOG EPDC_IRQ_MASK_TOG_REG(EPDC_BASE_PTR) +#define EPDC_IRQ EPDC_IRQ_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_SET EPDC_IRQ_SET_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_CLR EPDC_IRQ_CLR_REG(EPDC_BASE_PTR) +#define EPDC_IRQ_TOG EPDC_IRQ_TOG_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS1 EPDC_STATUS_LUTS1_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS1_SET EPDC_STATUS_LUTS1_SET_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS1_CLR EPDC_STATUS_LUTS1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS1_TOG EPDC_STATUS_LUTS1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS2 EPDC_STATUS_LUTS2_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS2_SET EPDC_STATUS_LUTS2_SET_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS2_CLR EPDC_STATUS_LUTS2_CLR_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_LUTS2_TOG EPDC_STATUS_LUTS2_TOG_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_NEXTLUT EPDC_STATUS_NEXTLUT_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL1 EPDC_STATUS_COL1_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL1_SET EPDC_STATUS_COL1_SET_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL1_CLR EPDC_STATUS_COL1_CLR_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL1_TOG EPDC_STATUS_COL1_TOG_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL2 EPDC_STATUS_COL2_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL2_SET EPDC_STATUS_COL2_SET_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL2_CLR EPDC_STATUS_COL2_CLR_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_COL2_TOG EPDC_STATUS_COL2_TOG_REG(EPDC_BASE_PTR) +#define EPDC_STATUS EPDC_STATUS_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_SET EPDC_STATUS_SET_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_CLR EPDC_STATUS_CLR_REG(EPDC_BASE_PTR) +#define EPDC_STATUS_TOG EPDC_STATUS_TOG_REG(EPDC_BASE_PTR) +#define EPDC_UPD_COL_CORD EPDC_UPD_COL_CORD_REG(EPDC_BASE_PTR) +#define EPDC_UPD_COL_SIZE EPDC_UPD_COL_SIZE_REG(EPDC_BASE_PTR) +#define EPDC_HIST1_PARAM EPDC_HIST1_PARAM_REG(EPDC_BASE_PTR) +#define EPDC_HIST2_PARAM EPDC_HIST2_PARAM_REG(EPDC_BASE_PTR) +#define EPDC_HIST4_PARAM EPDC_HIST4_PARAM_REG(EPDC_BASE_PTR) +#define EPDC_HIST8_PARAM0 EPDC_HIST8_PARAM0_REG(EPDC_BASE_PTR) +#define EPDC_HIST8_PARAM1 EPDC_HIST8_PARAM1_REG(EPDC_BASE_PTR) +#define EPDC_HIST16_PARAM0 EPDC_HIST16_PARAM0_REG(EPDC_BASE_PTR) +#define EPDC_HIST16_PARAM1 EPDC_HIST16_PARAM1_REG(EPDC_BASE_PTR) +#define EPDC_HIST16_PARAM2 EPDC_HIST16_PARAM2_REG(EPDC_BASE_PTR) +#define EPDC_HIST16_PARAM3 EPDC_HIST16_PARAM3_REG(EPDC_BASE_PTR) +#define EPDC_GPIO EPDC_GPIO_REG(EPDC_BASE_PTR) +#define EPDC_GPIO_SET EPDC_GPIO_SET_REG(EPDC_BASE_PTR) +#define EPDC_GPIO_CLR EPDC_GPIO_CLR_REG(EPDC_BASE_PTR) +#define EPDC_GPIO_TOG EPDC_GPIO_TOG_REG(EPDC_BASE_PTR) +#define EPDC_VERSION EPDC_VERSION_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_0_0 EPDC_PIGEON_0_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_0_1 EPDC_PIGEON_0_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_0_2 EPDC_PIGEON_0_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_1_0 EPDC_PIGEON_1_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_1_1 EPDC_PIGEON_1_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_1_2 EPDC_PIGEON_1_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_2_0 EPDC_PIGEON_2_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_2_1 EPDC_PIGEON_2_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_2_2 EPDC_PIGEON_2_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_3_0 EPDC_PIGEON_3_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_3_1 EPDC_PIGEON_3_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_3_2 EPDC_PIGEON_3_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_4_0 EPDC_PIGEON_4_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_4_1 EPDC_PIGEON_4_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_4_2 EPDC_PIGEON_4_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_5_0 EPDC_PIGEON_5_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_5_1 EPDC_PIGEON_5_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_5_2 EPDC_PIGEON_5_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_6_0 EPDC_PIGEON_6_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_6_1 EPDC_PIGEON_6_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_6_2 EPDC_PIGEON_6_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_7_0 EPDC_PIGEON_7_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_7_1 EPDC_PIGEON_7_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_7_2 EPDC_PIGEON_7_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_8_0 EPDC_PIGEON_8_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_8_1 EPDC_PIGEON_8_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_8_2 EPDC_PIGEON_8_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_9_0 EPDC_PIGEON_9_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_9_1 EPDC_PIGEON_9_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_9_2 EPDC_PIGEON_9_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_10_0 EPDC_PIGEON_10_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_10_1 EPDC_PIGEON_10_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_10_2 EPDC_PIGEON_10_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_11_0 EPDC_PIGEON_11_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_11_1 EPDC_PIGEON_11_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_11_2 EPDC_PIGEON_11_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_12_0 EPDC_PIGEON_12_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_12_1 EPDC_PIGEON_12_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_12_2 EPDC_PIGEON_12_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_13_0 EPDC_PIGEON_13_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_13_1 EPDC_PIGEON_13_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_13_2 EPDC_PIGEON_13_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_14_0 EPDC_PIGEON_14_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_14_1 EPDC_PIGEON_14_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_14_2 EPDC_PIGEON_14_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_15_0 EPDC_PIGEON_15_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_15_1 EPDC_PIGEON_15_1_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_15_2 EPDC_PIGEON_15_2_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_16_0 EPDC_PIGEON_16_0_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_16_1 EPDC_PIGEON_16_1_REG(EPDC_BASE_PTR) +#define EPDC_WB_ADDR_TCE EPDC_WB_ADDR_TCE_REG(EPDC_BASE_PTR) +#define EPDC_PIGEON_16_2 EPDC_PIGEON_16_2_REG(EPDC_BASE_PTR) + +/*! + * @} + */ /* end of group EPDC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group EPDC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- FTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer + * @{ + */ + +/** FTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ + __IO uint32_t CNT; /**< Counter, offset: 0x4 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ + struct { /* offset: 0xC, array step: 0x8 */ + __IO uint32_t CSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ + __IO uint32_t CV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ + } C[8]; + __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ + __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ + __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ + __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ + __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ + __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ + __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ + __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ + __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ + __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ + __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ + __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ + __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ + __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ + __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ + __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ + __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ +} FTM_Type, *FTM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- FTM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros + * @{ + */ + + +/* FTM - Register accessors */ +#define FTM_SC_REG(base) ((base)->SC) +#define FTM_CNT_REG(base) ((base)->CNT) +#define FTM_MOD_REG(base) ((base)->MOD) +#define FTM_CSC_REG(base,index) ((base)->C[index].CSC) +#define FTM_CV_REG(base,index) ((base)->C[index].CV) +#define FTM_CNTIN_REG(base) ((base)->CNTIN) +#define FTM_STATUS_REG(base) ((base)->STATUS) +#define FTM_MODE_REG(base) ((base)->MODE) +#define FTM_SYNC_REG(base) ((base)->SYNC) +#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) +#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) +#define FTM_COMBINE_REG(base) ((base)->COMBINE) +#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) +#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) +#define FTM_POL_REG(base) ((base)->POL) +#define FTM_FMS_REG(base) ((base)->FMS) +#define FTM_FILTER_REG(base) ((base)->FILTER) +#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) +#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) +#define FTM_CONF_REG(base) ((base)->CONF) +#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) +#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) +#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) +#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) +#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) + +/*! + * @} + */ /* end of group FTM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK 0x18u +#define FTM_SC_CLKS_SHIFT 3 +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS_MASK 0x20u +#define FTM_SC_CPWMS_SHIFT 5 +#define FTM_SC_TOIE_MASK 0x40u +#define FTM_SC_TOIE_SHIFT 6 +#define FTM_SC_TOF_MASK 0x80u +#define FTM_SC_TOF_SHIFT 7 +/* CNT Bit Fields */ +#define FTM_CNT_COUNT_MASK 0xFFFFu +#define FTM_CNT_COUNT_SHIFT 0 +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK) +/* MOD Bit Fields */ +#define FTM_MOD_MOD_MASK 0xFFFFu +#define FTM_MOD_MOD_SHIFT 0 +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK) +/* CSC Bit Fields */ +#define FTM_CSC_DMA_MASK 0x1u +#define FTM_CSC_DMA_SHIFT 0 +#define FTM_CSC_ELSA_MASK 0x4u +#define FTM_CSC_ELSA_SHIFT 2 +#define FTM_CSC_ELSB_MASK 0x8u +#define FTM_CSC_ELSB_SHIFT 3 +#define FTM_CSC_MSA_MASK 0x10u +#define FTM_CSC_MSA_SHIFT 4 +#define FTM_CSC_MSB_MASK 0x20u +#define FTM_CSC_MSB_SHIFT 5 +#define FTM_CSC_CHIE_MASK 0x40u +#define FTM_CSC_CHIE_SHIFT 6 +#define FTM_CSC_CHF_MASK 0x80u +#define FTM_CSC_CHF_SHIFT 7 +/* CV Bit Fields */ +#define FTM_CV_VAL_MASK 0xFFFFu +#define FTM_CV_VAL_SHIFT 0 +#define FTM_CV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_VAL_SHIFT))&FTM_CV_VAL_MASK) +/* CNTIN Bit Fields */ +#define FTM_CNTIN_INIT_MASK 0xFFFFu +#define FTM_CNTIN_INIT_SHIFT 0 +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK) +/* STATUS Bit Fields */ +#define FTM_STATUS_CH0F_MASK 0x1u +#define FTM_STATUS_CH0F_SHIFT 0 +#define FTM_STATUS_CH1F_MASK 0x2u +#define FTM_STATUS_CH1F_SHIFT 1 +#define FTM_STATUS_CH2F_MASK 0x4u +#define FTM_STATUS_CH2F_SHIFT 2 +#define FTM_STATUS_CH3F_MASK 0x8u +#define FTM_STATUS_CH3F_SHIFT 3 +#define FTM_STATUS_CH4F_MASK 0x10u +#define FTM_STATUS_CH4F_SHIFT 4 +#define FTM_STATUS_CH5F_MASK 0x20u +#define FTM_STATUS_CH5F_SHIFT 5 +#define FTM_STATUS_CH6F_MASK 0x40u +#define FTM_STATUS_CH6F_SHIFT 6 +#define FTM_STATUS_CH7F_MASK 0x80u +#define FTM_STATUS_CH7F_SHIFT 7 +/* MODE Bit Fields */ +#define FTM_MODE_FTMEN_MASK 0x1u +#define FTM_MODE_FTMEN_SHIFT 0 +#define FTM_MODE_INIT_MASK 0x2u +#define FTM_MODE_INIT_SHIFT 1 +#define FTM_MODE_WPDIS_MASK 0x4u +#define FTM_MODE_WPDIS_SHIFT 2 +#define FTM_MODE_PWMSYNC_MASK 0x8u +#define FTM_MODE_PWMSYNC_SHIFT 3 +#define FTM_MODE_CAPTEST_MASK 0x10u +#define FTM_MODE_CAPTEST_SHIFT 4 +#define FTM_MODE_FAULTM_MASK 0x60u +#define FTM_MODE_FAULTM_SHIFT 5 +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK 0x80u +#define FTM_MODE_FAULTIE_SHIFT 7 +/* SYNC Bit Fields */ +#define FTM_SYNC_CNTMIN_MASK 0x1u +#define FTM_SYNC_CNTMIN_SHIFT 0 +#define FTM_SYNC_CNTMAX_MASK 0x2u +#define FTM_SYNC_CNTMAX_SHIFT 1 +#define FTM_SYNC_REINIT_MASK 0x4u +#define FTM_SYNC_REINIT_SHIFT 2 +#define FTM_SYNC_SYNCHOM_MASK 0x8u +#define FTM_SYNC_SYNCHOM_SHIFT 3 +#define FTM_SYNC_TRIG0_MASK 0x10u +#define FTM_SYNC_TRIG0_SHIFT 4 +#define FTM_SYNC_TRIG1_MASK 0x20u +#define FTM_SYNC_TRIG1_SHIFT 5 +#define FTM_SYNC_TRIG2_MASK 0x40u +#define FTM_SYNC_TRIG2_SHIFT 6 +#define FTM_SYNC_SWSYNC_MASK 0x80u +#define FTM_SYNC_SWSYNC_SHIFT 7 +/* OUTINIT Bit Fields */ +#define FTM_OUTINIT_CH0OI_MASK 0x1u +#define FTM_OUTINIT_CH0OI_SHIFT 0 +#define FTM_OUTINIT_CH1OI_MASK 0x2u +#define FTM_OUTINIT_CH1OI_SHIFT 1 +#define FTM_OUTINIT_CH2OI_MASK 0x4u +#define FTM_OUTINIT_CH2OI_SHIFT 2 +#define FTM_OUTINIT_CH3OI_MASK 0x8u +#define FTM_OUTINIT_CH3OI_SHIFT 3 +#define FTM_OUTINIT_CH4OI_MASK 0x10u +#define FTM_OUTINIT_CH4OI_SHIFT 4 +#define FTM_OUTINIT_CH5OI_MASK 0x20u +#define FTM_OUTINIT_CH5OI_SHIFT 5 +#define FTM_OUTINIT_CH6OI_MASK 0x40u +#define FTM_OUTINIT_CH6OI_SHIFT 6 +#define FTM_OUTINIT_CH7OI_MASK 0x80u +#define FTM_OUTINIT_CH7OI_SHIFT 7 +/* OUTMASK Bit Fields */ +#define FTM_OUTMASK_CH0OM_MASK 0x1u +#define FTM_OUTMASK_CH0OM_SHIFT 0 +#define FTM_OUTMASK_CH1OM_MASK 0x2u +#define FTM_OUTMASK_CH1OM_SHIFT 1 +#define FTM_OUTMASK_CH2OM_MASK 0x4u +#define FTM_OUTMASK_CH2OM_SHIFT 2 +#define FTM_OUTMASK_CH3OM_MASK 0x8u +#define FTM_OUTMASK_CH3OM_SHIFT 3 +#define FTM_OUTMASK_CH4OM_MASK 0x10u +#define FTM_OUTMASK_CH4OM_SHIFT 4 +#define FTM_OUTMASK_CH5OM_MASK 0x20u +#define FTM_OUTMASK_CH5OM_SHIFT 5 +#define FTM_OUTMASK_CH6OM_MASK 0x40u +#define FTM_OUTMASK_CH6OM_SHIFT 6 +#define FTM_OUTMASK_CH7OM_MASK 0x80u +#define FTM_OUTMASK_CH7OM_SHIFT 7 +/* COMBINE Bit Fields */ +#define FTM_COMBINE_COMBINE0_MASK 0x1u +#define FTM_COMBINE_COMBINE0_SHIFT 0 +#define FTM_COMBINE_COMP0_MASK 0x2u +#define FTM_COMBINE_COMP0_SHIFT 1 +#define FTM_COMBINE_DECAPEN0_MASK 0x4u +#define FTM_COMBINE_DECAPEN0_SHIFT 2 +#define FTM_COMBINE_DECAP0_MASK 0x8u +#define FTM_COMBINE_DECAP0_SHIFT 3 +#define FTM_COMBINE_DTEN0_MASK 0x10u +#define FTM_COMBINE_DTEN0_SHIFT 4 +#define FTM_COMBINE_SYNCEN0_MASK 0x20u +#define FTM_COMBINE_SYNCEN0_SHIFT 5 +#define FTM_COMBINE_FAULTEN0_MASK 0x40u +#define FTM_COMBINE_FAULTEN0_SHIFT 6 +#define FTM_COMBINE_COMBINE1_MASK 0x100u +#define FTM_COMBINE_COMBINE1_SHIFT 8 +#define FTM_COMBINE_COMP1_MASK 0x200u +#define FTM_COMBINE_COMP1_SHIFT 9 +#define FTM_COMBINE_DECAPEN1_MASK 0x400u +#define FTM_COMBINE_DECAPEN1_SHIFT 10 +#define FTM_COMBINE_DECAP1_MASK 0x800u +#define FTM_COMBINE_DECAP1_SHIFT 11 +#define FTM_COMBINE_DTEN1_MASK 0x1000u +#define FTM_COMBINE_DTEN1_SHIFT 12 +#define FTM_COMBINE_SYNCEN1_MASK 0x2000u +#define FTM_COMBINE_SYNCEN1_SHIFT 13 +#define FTM_COMBINE_FAULTEN1_MASK 0x4000u +#define FTM_COMBINE_FAULTEN1_SHIFT 14 +#define FTM_COMBINE_COMBINE2_MASK 0x10000u +#define FTM_COMBINE_COMBINE2_SHIFT 16 +#define FTM_COMBINE_COMP2_MASK 0x20000u +#define FTM_COMBINE_COMP2_SHIFT 17 +#define FTM_COMBINE_DECAPEN2_MASK 0x40000u +#define FTM_COMBINE_DECAPEN2_SHIFT 18 +#define FTM_COMBINE_DECAP2_MASK 0x80000u +#define FTM_COMBINE_DECAP2_SHIFT 19 +#define FTM_COMBINE_DTEN2_MASK 0x100000u +#define FTM_COMBINE_DTEN2_SHIFT 20 +#define FTM_COMBINE_SYNCEN2_MASK 0x200000u +#define FTM_COMBINE_SYNCEN2_SHIFT 21 +#define FTM_COMBINE_FAULTEN2_MASK 0x400000u +#define FTM_COMBINE_FAULTEN2_SHIFT 22 +#define FTM_COMBINE_COMBINE3_MASK 0x1000000u +#define FTM_COMBINE_COMBINE3_SHIFT 24 +#define FTM_COMBINE_COMP3_MASK 0x2000000u +#define FTM_COMBINE_COMP3_SHIFT 25 +#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u +#define FTM_COMBINE_DECAPEN3_SHIFT 26 +#define FTM_COMBINE_DECAP3_MASK 0x8000000u +#define FTM_COMBINE_DECAP3_SHIFT 27 +#define FTM_COMBINE_DTEN3_MASK 0x10000000u +#define FTM_COMBINE_DTEN3_SHIFT 28 +#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u +#define FTM_COMBINE_SYNCEN3_SHIFT 29 +#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u +#define FTM_COMBINE_FAULTEN3_SHIFT 30 +/* DEADTIME Bit Fields */ +#define FTM_DEADTIME_DTVAL_MASK 0x3Fu +#define FTM_DEADTIME_DTVAL_SHIFT 0 +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK 0xC0u +#define FTM_DEADTIME_DTPS_SHIFT 6 +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK) +/* EXTTRIG Bit Fields */ +#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u +#define FTM_EXTTRIG_CH2TRIG_SHIFT 0 +#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u +#define FTM_EXTTRIG_CH3TRIG_SHIFT 1 +#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u +#define FTM_EXTTRIG_CH4TRIG_SHIFT 2 +#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u +#define FTM_EXTTRIG_CH5TRIG_SHIFT 3 +#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u +#define FTM_EXTTRIG_CH0TRIG_SHIFT 4 +#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u +#define FTM_EXTTRIG_CH1TRIG_SHIFT 5 +#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u +#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6 +#define FTM_EXTTRIG_TRIGF_MASK 0x80u +#define FTM_EXTTRIG_TRIGF_SHIFT 7 +/* POL Bit Fields */ +#define FTM_POL_POL0_MASK 0x1u +#define FTM_POL_POL0_SHIFT 0 +#define FTM_POL_POL1_MASK 0x2u +#define FTM_POL_POL1_SHIFT 1 +#define FTM_POL_POL2_MASK 0x4u +#define FTM_POL_POL2_SHIFT 2 +#define FTM_POL_POL3_MASK 0x8u +#define FTM_POL_POL3_SHIFT 3 +#define FTM_POL_POL4_MASK 0x10u +#define FTM_POL_POL4_SHIFT 4 +#define FTM_POL_POL5_MASK 0x20u +#define FTM_POL_POL5_SHIFT 5 +#define FTM_POL_POL6_MASK 0x40u +#define FTM_POL_POL6_SHIFT 6 +#define FTM_POL_POL7_MASK 0x80u +#define FTM_POL_POL7_SHIFT 7 +/* FMS Bit Fields */ +#define FTM_FMS_FAULTF0_MASK 0x1u +#define FTM_FMS_FAULTF0_SHIFT 0 +#define FTM_FMS_FAULTF1_MASK 0x2u +#define FTM_FMS_FAULTF1_SHIFT 1 +#define FTM_FMS_FAULTF2_MASK 0x4u +#define FTM_FMS_FAULTF2_SHIFT 2 +#define FTM_FMS_FAULTF3_MASK 0x8u +#define FTM_FMS_FAULTF3_SHIFT 3 +#define FTM_FMS_FAULTIN_MASK 0x20u +#define FTM_FMS_FAULTIN_SHIFT 5 +#define FTM_FMS_WPEN_MASK 0x40u +#define FTM_FMS_WPEN_SHIFT 6 +#define FTM_FMS_FAULTF_MASK 0x80u +#define FTM_FMS_FAULTF_SHIFT 7 +/* FILTER Bit Fields */ +#define FTM_FILTER_CH0FVAL_MASK 0xFu +#define FTM_FILTER_CH0FVAL_SHIFT 0 +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK 0xF0u +#define FTM_FILTER_CH1FVAL_SHIFT 4 +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK 0xF00u +#define FTM_FILTER_CH2FVAL_SHIFT 8 +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK 0xF000u +#define FTM_FILTER_CH3FVAL_SHIFT 12 +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK) +/* FLTCTRL Bit Fields */ +#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u +#define FTM_FLTCTRL_FAULT0EN_SHIFT 0 +#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u +#define FTM_FLTCTRL_FAULT1EN_SHIFT 1 +#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u +#define FTM_FLTCTRL_FAULT2EN_SHIFT 2 +#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u +#define FTM_FLTCTRL_FAULT3EN_SHIFT 3 +#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u +#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4 +#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u +#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5 +#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u +#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6 +#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u +#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7 +#define FTM_FLTCTRL_FFVAL_MASK 0xF00u +#define FTM_FLTCTRL_FFVAL_SHIFT 8 +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK) +/* QDCTRL Bit Fields */ +#define FTM_QDCTRL_QUADEN_MASK 0x1u +#define FTM_QDCTRL_QUADEN_SHIFT 0 +#define FTM_QDCTRL_TOFDIR_MASK 0x2u +#define FTM_QDCTRL_TOFDIR_SHIFT 1 +#define FTM_QDCTRL_QUADIR_MASK 0x4u +#define FTM_QDCTRL_QUADIR_SHIFT 2 +#define FTM_QDCTRL_QUADMODE_MASK 0x8u +#define FTM_QDCTRL_QUADMODE_SHIFT 3 +#define FTM_QDCTRL_PHBPOL_MASK 0x10u +#define FTM_QDCTRL_PHBPOL_SHIFT 4 +#define FTM_QDCTRL_PHAPOL_MASK 0x20u +#define FTM_QDCTRL_PHAPOL_SHIFT 5 +#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u +#define FTM_QDCTRL_PHBFLTREN_SHIFT 6 +#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u +#define FTM_QDCTRL_PHAFLTREN_SHIFT 7 +/* CONF Bit Fields */ +#define FTM_CONF_NUMTOF_MASK 0x1Fu +#define FTM_CONF_NUMTOF_SHIFT 0 +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK 0xC0u +#define FTM_CONF_BDMMODE_SHIFT 6 +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK 0x200u +#define FTM_CONF_GTBEEN_SHIFT 9 +#define FTM_CONF_GTBEOUT_MASK 0x400u +#define FTM_CONF_GTBEOUT_SHIFT 10 +/* FLTPOL Bit Fields */ +#define FTM_FLTPOL_FLT0POL_MASK 0x1u +#define FTM_FLTPOL_FLT0POL_SHIFT 0 +#define FTM_FLTPOL_FLT1POL_MASK 0x2u +#define FTM_FLTPOL_FLT1POL_SHIFT 1 +#define FTM_FLTPOL_FLT2POL_MASK 0x4u +#define FTM_FLTPOL_FLT2POL_SHIFT 2 +#define FTM_FLTPOL_FLT3POL_MASK 0x8u +#define FTM_FLTPOL_FLT3POL_SHIFT 3 +/* SYNCONF Bit Fields */ +#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u +#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0 +#define FTM_SYNCONF_CNTINC_MASK 0x4u +#define FTM_SYNCONF_CNTINC_SHIFT 2 +#define FTM_SYNCONF_INVC_MASK 0x10u +#define FTM_SYNCONF_INVC_SHIFT 4 +#define FTM_SYNCONF_SWOC_MASK 0x20u +#define FTM_SYNCONF_SWOC_SHIFT 5 +#define FTM_SYNCONF_SYNCMODE_MASK 0x80u +#define FTM_SYNCONF_SYNCMODE_SHIFT 7 +#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u +#define FTM_SYNCONF_SWRSTCNT_SHIFT 8 +#define FTM_SYNCONF_SWWRBUF_MASK 0x200u +#define FTM_SYNCONF_SWWRBUF_SHIFT 9 +#define FTM_SYNCONF_SWOM_MASK 0x400u +#define FTM_SYNCONF_SWOM_SHIFT 10 +#define FTM_SYNCONF_SWINVC_MASK 0x800u +#define FTM_SYNCONF_SWINVC_SHIFT 11 +#define FTM_SYNCONF_SWSOC_MASK 0x1000u +#define FTM_SYNCONF_SWSOC_SHIFT 12 +#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u +#define FTM_SYNCONF_HWRSTCNT_SHIFT 16 +#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u +#define FTM_SYNCONF_HWWRBUF_SHIFT 17 +#define FTM_SYNCONF_HWOM_MASK 0x40000u +#define FTM_SYNCONF_HWOM_SHIFT 18 +#define FTM_SYNCONF_HWINVC_MASK 0x80000u +#define FTM_SYNCONF_HWINVC_SHIFT 19 +#define FTM_SYNCONF_HWSOC_MASK 0x100000u +#define FTM_SYNCONF_HWSOC_SHIFT 20 +/* INVCTRL Bit Fields */ +#define FTM_INVCTRL_INV0EN_MASK 0x1u +#define FTM_INVCTRL_INV0EN_SHIFT 0 +#define FTM_INVCTRL_INV1EN_MASK 0x2u +#define FTM_INVCTRL_INV1EN_SHIFT 1 +#define FTM_INVCTRL_INV2EN_MASK 0x4u +#define FTM_INVCTRL_INV2EN_SHIFT 2 +#define FTM_INVCTRL_INV3EN_MASK 0x8u +#define FTM_INVCTRL_INV3EN_SHIFT 3 +/* SWOCTRL Bit Fields */ +#define FTM_SWOCTRL_CH0OC_MASK 0x1u +#define FTM_SWOCTRL_CH0OC_SHIFT 0 +#define FTM_SWOCTRL_CH1OC_MASK 0x2u +#define FTM_SWOCTRL_CH1OC_SHIFT 1 +#define FTM_SWOCTRL_CH2OC_MASK 0x4u +#define FTM_SWOCTRL_CH2OC_SHIFT 2 +#define FTM_SWOCTRL_CH3OC_MASK 0x8u +#define FTM_SWOCTRL_CH3OC_SHIFT 3 +#define FTM_SWOCTRL_CH4OC_MASK 0x10u +#define FTM_SWOCTRL_CH4OC_SHIFT 4 +#define FTM_SWOCTRL_CH5OC_MASK 0x20u +#define FTM_SWOCTRL_CH5OC_SHIFT 5 +#define FTM_SWOCTRL_CH6OC_MASK 0x40u +#define FTM_SWOCTRL_CH6OC_SHIFT 6 +#define FTM_SWOCTRL_CH7OC_MASK 0x80u +#define FTM_SWOCTRL_CH7OC_SHIFT 7 +#define FTM_SWOCTRL_CH0OCV_MASK 0x100u +#define FTM_SWOCTRL_CH0OCV_SHIFT 8 +#define FTM_SWOCTRL_CH1OCV_MASK 0x200u +#define FTM_SWOCTRL_CH1OCV_SHIFT 9 +#define FTM_SWOCTRL_CH2OCV_MASK 0x400u +#define FTM_SWOCTRL_CH2OCV_SHIFT 10 +#define FTM_SWOCTRL_CH3OCV_MASK 0x800u +#define FTM_SWOCTRL_CH3OCV_SHIFT 11 +#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u +#define FTM_SWOCTRL_CH4OCV_SHIFT 12 +#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u +#define FTM_SWOCTRL_CH5OCV_SHIFT 13 +#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u +#define FTM_SWOCTRL_CH6OCV_SHIFT 14 +#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u +#define FTM_SWOCTRL_CH7OCV_SHIFT 15 +/* PWMLOAD Bit Fields */ +#define FTM_PWMLOAD_CH0SEL_MASK 0x1u +#define FTM_PWMLOAD_CH0SEL_SHIFT 0 +#define FTM_PWMLOAD_CH1SEL_MASK 0x2u +#define FTM_PWMLOAD_CH1SEL_SHIFT 1 +#define FTM_PWMLOAD_CH2SEL_MASK 0x4u +#define FTM_PWMLOAD_CH2SEL_SHIFT 2 +#define FTM_PWMLOAD_CH3SEL_MASK 0x8u +#define FTM_PWMLOAD_CH3SEL_SHIFT 3 +#define FTM_PWMLOAD_CH4SEL_MASK 0x10u +#define FTM_PWMLOAD_CH4SEL_SHIFT 4 +#define FTM_PWMLOAD_CH5SEL_MASK 0x20u +#define FTM_PWMLOAD_CH5SEL_SHIFT 5 +#define FTM_PWMLOAD_CH6SEL_MASK 0x40u +#define FTM_PWMLOAD_CH6SEL_SHIFT 6 +#define FTM_PWMLOAD_CH7SEL_MASK 0x80u +#define FTM_PWMLOAD_CH7SEL_SHIFT 7 +#define FTM_PWMLOAD_LDOK_MASK 0x200u +#define FTM_PWMLOAD_LDOK_SHIFT 9 + +/*! + * @} + */ /* end of group FTM_Register_Masks */ + + +/* FTM - Peripheral instance base addresses */ +/** Peripheral FTM base address */ +/* TODO: FTM1, FTM2 */ +#define FTM_BASE (0x30640000u) +/** Peripheral FTM base pointer */ +#define FTM ((FTM_Type *)FTM_BASE) +#define FTM_BASE_PTR (FTM) +/** Array initializer of FTM peripheral base adresses */ +#define FTM_BASE_ADDRS { FTM_BASE } +/** Array initializer of FTM peripheral base pointers */ +#define FTM_BASE_PTRS { FTM } + +/* ---------------------------------------------------------------------------- + -- FTM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros + * @{ + */ + + +/* FTM - Register instance definitions */ +/* FTM */ +#define FTM_SC FTM_SC_REG(FTM_BASE_PTR) +#define FTM_CNT FTM_CNT_REG(FTM_BASE_PTR) +#define FTM_MOD FTM_MOD_REG(FTM_BASE_PTR) +#define FTM_C0SC FTM_CSC_REG(FTM_BASE_PTR,0) +#define FTM_C0V FTM_CV_REG(FTM_BASE_PTR,0) +#define FTM_C1SC FTM_CSC_REG(FTM_BASE_PTR,1) +#define FTM_C1V FTM_CV_REG(FTM_BASE_PTR,1) +#define FTM_C2SC FTM_CSC_REG(FTM_BASE_PTR,2) +#define FTM_C2V FTM_CV_REG(FTM_BASE_PTR,2) +#define FTM_C3SC FTM_CSC_REG(FTM_BASE_PTR,3) +#define FTM_C3V FTM_CV_REG(FTM_BASE_PTR,3) +#define FTM_C4SC FTM_CSC_REG(FTM_BASE_PTR,4) +#define FTM_C4V FTM_CV_REG(FTM_BASE_PTR,4) +#define FTM_C5SC FTM_CSC_REG(FTM_BASE_PTR,5) +#define FTM_C5V FTM_CV_REG(FTM_BASE_PTR,5) +#define FTM_C6SC FTM_CSC_REG(FTM_BASE_PTR,6) +#define FTM_C6V FTM_CV_REG(FTM_BASE_PTR,6) +#define FTM_C7SC FTM_CSC_REG(FTM_BASE_PTR,7) +#define FTM_C7V FTM_CV_REG(FTM_BASE_PTR,7) +#define FTM_CNTIN FTM_CNTIN_REG(FTM_BASE_PTR) +#define FTM_STATUS FTM_STATUS_REG(FTM_BASE_PTR) +#define FTM_MODE FTM_MODE_REG(FTM_BASE_PTR) +#define FTM_SYNC FTM_SYNC_REG(FTM_BASE_PTR) +#define FTM_OUTINIT FTM_OUTINIT_REG(FTM_BASE_PTR) +#define FTM_OUTMASK FTM_OUTMASK_REG(FTM_BASE_PTR) +#define FTM_COMBINE FTM_COMBINE_REG(FTM_BASE_PTR) +#define FTM_DEADTIME FTM_DEADTIME_REG(FTM_BASE_PTR) +#define FTM_EXTTRIG FTM_EXTTRIG_REG(FTM_BASE_PTR) +#define FTM_POL FTM_POL_REG(FTM_BASE_PTR) +#define FTM_FMS FTM_FMS_REG(FTM_BASE_PTR) +#define FTM_FILTER FTM_FILTER_REG(FTM_BASE_PTR) +#define FTM_FLTCTRL FTM_FLTCTRL_REG(FTM_BASE_PTR) +#define FTM_QDCTRL FTM_QDCTRL_REG(FTM_BASE_PTR) +#define FTM_CONF FTM_CONF_REG(FTM_BASE_PTR) +#define FTM_FLTPOL FTM_FLTPOL_REG(FTM_BASE_PTR) +#define FTM_SYNCONF FTM_SYNCONF_REG(FTM_BASE_PTR) +#define FTM_INVCTRL FTM_INVCTRL_REG(FTM_BASE_PTR) +#define FTM_SWOCTRL FTM_SWOCTRL_REG(FTM_BASE_PTR) +#define FTM_PWMLOAD FTM_PWMLOAD_REG(FTM_BASE_PTR) + +/* FTM - Register array accessors */ +#define FTM_CSC(index) FTM_CSC_REG(FTM_BASE_PTR,index) +#define FTM_CV(index) FTM_CV_REG(FTM_BASE_PTR,index) + +/*! + * @} + */ /* end of group FTM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group FTM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + __IO uint32_t PGR; /**< GPC Power Gating Register, offset: 0x4 */ + __IO uint32_t IMR1; /**< IRQ masking register 1, offset: 0x8 */ + __IO uint32_t IMR2; /**< IRQ masking register 2, offset: 0xC */ + __IO uint32_t IMR3; /**< IRQ masking register 3, offset: 0x10 */ + __IO uint32_t IMR4; /**< IRQ masking register 4, offset: 0x14 */ + __I uint32_t ISR1; /**< IRQ status resister 1, offset: 0x18 */ + __I uint32_t ISR2; /**< IRQ status resister 2, offset: 0x1C */ + __I uint32_t ISR3; /**< IRQ status resister 3, offset: 0x20 */ + __I uint32_t ISR4; /**< IRQ status resister 4, offset: 0x24 */ + __IO uint32_t A9_LPSR; /**< A9 Low Power Status Register, offset: 0x28 */ + __IO uint32_t M4_LPSR; /**< M4 Low Power Status Register, offset: 0x2C */ + __I uint32_t DR; /**< GPC Debug Register, offset: 0x30 */ +} GPC_Type, *GPC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- GPC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros + * @{ + */ + + +/* GPC - Register accessors */ +#define GPC_CNTR_REG(base) ((base)->CNTR) +#define GPC_PGR_REG(base) ((base)->PGR) +#define GPC_IMR1_REG(base) ((base)->IMR1) +#define GPC_IMR2_REG(base) ((base)->IMR2) +#define GPC_IMR3_REG(base) ((base)->IMR3) +#define GPC_IMR4_REG(base) ((base)->IMR4) +#define GPC_ISR1_REG(base) ((base)->ISR1) +#define GPC_ISR2_REG(base) ((base)->ISR2) +#define GPC_ISR3_REG(base) ((base)->ISR3) +#define GPC_ISR4_REG(base) ((base)->ISR4) +#define GPC_A9_LPSR_REG(base) ((base)->A9_LPSR) +#define GPC_M4_LPSR_REG(base) ((base)->M4_LPSR) +#define GPC_DR_REG(base) ((base)->DR) + +/*! + * @} + */ /* end of group GPC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/* CNTR Bit Fields */ +#define GPC_CNTR_gpu_vpu_pdn_req_MASK 0x1u +#define GPC_CNTR_gpu_vpu_pdn_req_SHIFT 0 +#define GPC_CNTR_gpu_vpu_pup_req_MASK 0x2u +#define GPC_CNTR_gpu_vpu_pup_req_SHIFT 1 +#define GPC_CNTR_MEGA_PDN_REQ_MASK 0x4u +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT 2 +#define GPC_CNTR_MEGA_PUP_REQ_MASK 0x8u +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT 3 +#define GPC_CNTR_DISPLAY_PDN_REQ_MASK 0x10u +#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT 4 +#define GPC_CNTR_DISPLAY_PUP_REQ_MASK 0x20u +#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT 5 +#define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK 0x40u +#define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT 6 +#define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK 0x80u +#define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT 7 +#define GPC_CNTR_DVFS0CR_MASK 0x10000u +#define GPC_CNTR_DVFS0CR_SHIFT 16 +#define GPC_CNTR_VADC_ANALOG_OFF_MASK 0x20000u +#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT 17 +#define GPC_CNTR_VADC_EXT_PWD_N_MASK 0x40000u +#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT 18 +#define GPC_CNTR_GPCIRQM_MASK 0x200000u +#define GPC_CNTR_GPCIRQM_SHIFT 21 +#define GPC_CNTR_L2_PGE_MASK 0x400000u +#define GPC_CNTR_L2_PGE_SHIFT 22 +/* PGR Bit Fields */ +#define GPC_PGR_DRCIC_MASK 0x60000000u +#define GPC_PGR_DRCIC_SHIFT 29 +#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x))<<GPC_PGR_DRCIC_SHIFT))&GPC_PGR_DRCIC_MASK) +/* IMR1 Bit Fields */ +#define GPC_IMR1_IMR1_MASK 0xFFFFFFFFu +#define GPC_IMR1_IMR1_SHIFT 0 +#define GPC_IMR1_IMR1(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR1_IMR1_SHIFT))&GPC_IMR1_IMR1_MASK) +/* IMR2 Bit Fields */ +#define GPC_IMR2_IMR2_MASK 0xFFFFFFFFu +#define GPC_IMR2_IMR2_SHIFT 0 +#define GPC_IMR2_IMR2(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR2_IMR2_SHIFT))&GPC_IMR2_IMR2_MASK) +/* IMR3 Bit Fields */ +#define GPC_IMR3_IMR3_MASK 0xFFFFFFFFu +#define GPC_IMR3_IMR3_SHIFT 0 +#define GPC_IMR3_IMR3(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR3_IMR3_SHIFT))&GPC_IMR3_IMR3_MASK) +/* IMR4 Bit Fields */ +#define GPC_IMR4_IMR4_MASK 0xFFFFFFFFu +#define GPC_IMR4_IMR4_SHIFT 0 +#define GPC_IMR4_IMR4(x) (((uint32_t)(((uint32_t)(x))<<GPC_IMR4_IMR4_SHIFT))&GPC_IMR4_IMR4_MASK) +/* ISR1 Bit Fields */ +#define GPC_ISR1_ISR1_MASK 0xFFFFFFFFu +#define GPC_ISR1_ISR1_SHIFT 0 +#define GPC_ISR1_ISR1(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR1_ISR1_SHIFT))&GPC_ISR1_ISR1_MASK) +/* ISR2 Bit Fields */ +#define GPC_ISR2_ISR2_MASK 0xFFFFFFFFu +#define GPC_ISR2_ISR2_SHIFT 0 +#define GPC_ISR2_ISR2(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR2_ISR2_SHIFT))&GPC_ISR2_ISR2_MASK) +/* ISR3 Bit Fields */ +#define GPC_ISR3_ISR3_MASK 0xFFFFFFFFu +#define GPC_ISR3_ISR3_SHIFT 0 +#define GPC_ISR3_ISR3(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR3_ISR3_SHIFT))&GPC_ISR3_ISR3_MASK) +/* ISR4 Bit Fields */ +#define GPC_ISR4_ISR4_MASK 0xFFFFFFFFu +#define GPC_ISR4_ISR4_SHIFT 0 +#define GPC_ISR4_ISR4(x) (((uint32_t)(((uint32_t)(x))<<GPC_ISR4_ISR4_SHIFT))&GPC_ISR4_ISR4_MASK) +/* A9_LPSR Bit Fields */ +#define GPC_A9_LPSR_A9_STANDBY_WFI_MASK 0x1u +#define GPC_A9_LPSR_A9_STANDBY_WFI_SHIFT 0 +#define GPC_A9_LPSR_A9_SCU_IDLE_MASK 0x10u +#define GPC_A9_LPSR_A9_SCU_IDLE_SHIFT 4 +#define GPC_A9_LPSR_A9_L2CC_IDLE_MASK 0x20u +#define GPC_A9_LPSR_A9_L2CC_IDLE_SHIFT 5 +#define GPC_A9_LPSR_A9_CLK_ENABLE_MASK 0x40u +#define GPC_A9_LPSR_A9_CLK_ENABLE_SHIFT 6 +#define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_MASK 0x80u +#define GPC_A9_LPSR_SYSTEM_IN_WAIT_MODE_SHIFT 7 +#define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_MASK 0x100u +#define GPC_A9_LPSR_SYSTEM_IN_STOP_MODE_SHIFT 8 +#define GPC_A9_LPSR_A9_DBG_ACK_MASK 0x200u +#define GPC_A9_LPSR_A9_DBG_ACK_SHIFT 9 +#define GPC_A9_LPSR_A9_RST_MASK 0x400u +#define GPC_A9_LPSR_A9_RST_SHIFT 10 +/* M4_LPSR Bit Fields */ +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_MASK 0x1u +#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_B_SHIFT 0 +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_MASK 0x2u +#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_B_SHIFT 1 +#define GPC_M4_LPSR_M4_GATE_HCLK_MASK 0x4u +#define GPC_M4_LPSR_M4_GATE_HCLK_SHIFT 2 +#define GPC_M4_LPSR_M4_SLEEP_DEEP_MASK 0x8u +#define GPC_M4_LPSR_M4_SLEEP_DEEP_SHIFT 3 +#define GPC_M4_LPSR_M4_SLEEPING_MASK 0x10u +#define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4 +#define GPC_M4_LPSR_M4_LOCKUP_MASK 0x20u +#define GPC_M4_LPSR_M4_LOCKUP_SHIFT 5 +#define GPC_M4_LPSR_M4_HALTED_MASK 0x40u +#define GPC_M4_LPSR_M4_HALTED_SHIFT 6 +#define GPC_M4_LPSR_M4_PLATFORM_RESET_B_MASK 0x80u +#define GPC_M4_LPSR_M4_PLATFORM_RESET_B_SHIFT 7 +#define GPC_M4_LPSR_M4_CORE_RESET_B_MASK 0x100u +#define GPC_M4_LPSR_M4_CORE_RESET_B_SHIFT 8 +/* DR Bit Fields */ +#define GPC_DR_PCIE_PHY_RESET_B_MASK 0x1u +#define GPC_DR_PCIE_PHY_RESET_B_SHIFT 0 +#define GPC_DR_PCIE_PHY_ISO_MASK 0x2u +#define GPC_DR_PCIE_PHY_ISO_SHIFT 1 +#define GPC_DR_MEGA_RESET_B_MASK 0x4u +#define GPC_DR_MEGA_RESET_B_SHIFT 2 +#define GPC_DR_MEGA_SWITCH_B_MASK 0x8u +#define GPC_DR_MEGA_SWITCH_B_SHIFT 3 +#define GPC_DR_MEGA_ISO_MASK 0x10u +#define GPC_DR_MEGA_ISO_SHIFT 4 +#define GPC_DR_GPC_PUP_ACK_MASK 0x20u +#define GPC_DR_GPC_PUP_ACK_SHIFT 5 +#define GPC_DR_GPC_PDN_ACK_MASK 0x40u +#define GPC_DR_GPC_PDN_ACK_SHIFT 6 +#define GPC_DR_GPC_DISP_RESET_B_MASK 0x80u +#define GPC_DR_GPC_DISP_RESET_B_SHIFT 7 +#define GPC_DR_GPC_DISP_SWITCH_B_MASK 0x100u +#define GPC_DR_GPC_DISP_SWITCH_B_SHIFT 8 +#define GPC_DR_GPC_DISP_ISO_MASK 0x200u +#define GPC_DR_GPC_DISP_ISO_SHIFT 9 +#define GPC_DR_GPC_GPU_RESET_B_MASK 0x400u +#define GPC_DR_GPC_GPU_RESET_B_SHIFT 10 +#define GPC_DR_GPC_GPU_SWITCH_B_MASK 0x800u +#define GPC_DR_GPC_GPU_SWITCH_B_SHIFT 11 +#define GPC_DR_GPC_GPU_ISO_MASK 0x1000u +#define GPC_DR_GPC_GPU_ISO_SHIFT 12 +#define GPC_DR_GPC_L2SOC_ISO_MASK 0x2000u +#define GPC_DR_GPC_L2SOC_ISO_SHIFT 13 +#define GPC_DR_GPC_L2CPU_ISO_MASK 0x4000u +#define GPC_DR_GPC_L2CPU_ISO_SHIFT 14 +#define GPC_DR_GPC_L2_SWITCH_B_MASK 0x8000u +#define GPC_DR_GPC_L2_SWITCH_B_SHIFT 15 +#define GPC_DR_GPC_CPU_RESET_B_MASK 0x10000u +#define GPC_DR_GPC_CPU_RESET_B_SHIFT 16 +#define GPC_DR_GPC_CPU_SWITCH_B_MASK 0x20000u +#define GPC_DR_GPC_CPU_SWITCH_B_SHIFT 17 +#define GPC_DR_GPC_CPU_ISO_MASK 0x40000u +#define GPC_DR_GPC_CPU_ISO_SHIFT 18 +#define GPC_DR_IPG_STOP_MASK 0x80000u +#define GPC_DR_IPG_STOP_SHIFT 19 +#define GPC_DR_IPG_WAIT_MASK 0x100000u +#define GPC_DR_IPG_WAIT_SHIFT 20 + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x303A0000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +#define GPC_BASE_PTR (GPC) +/** Array initializer of GPC peripheral base adresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } + +/* ---------------------------------------------------------------------------- + -- GPC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Accessor_Macros GPC - Register accessor macros + * @{ + */ + + +/* GPC - Register instance definitions */ +/* GPC */ +#define GPC_CNTR GPC_CNTR_REG(GPC_BASE_PTR) +#define GPC_PGR GPC_PGR_REG(GPC_BASE_PTR) +#define GPC_IMR1 GPC_IMR1_REG(GPC_BASE_PTR) +#define GPC_IMR2 GPC_IMR2_REG(GPC_BASE_PTR) +#define GPC_IMR3 GPC_IMR3_REG(GPC_BASE_PTR) +#define GPC_IMR4 GPC_IMR4_REG(GPC_BASE_PTR) +#define GPC_ISR1 GPC_ISR1_REG(GPC_BASE_PTR) +#define GPC_ISR2 GPC_ISR2_REG(GPC_BASE_PTR) +#define GPC_ISR3 GPC_ISR3_REG(GPC_BASE_PTR) +#define GPC_ISR4 GPC_ISR4_REG(GPC_BASE_PTR) +#define GPC_A9_LPSR GPC_A9_LPSR_REG(GPC_BASE_PTR) +#define GPC_M4_LPSR GPC_M4_LPSR_REG(GPC_BASE_PTR) +#define GPC_DR GPC_DR_REG(GPC_BASE_PTR) + +/*! + * @} + */ /* end of group GPC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group GPC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ +} GPIO_Type, *GPIO_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- GPIO - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros + * @{ + */ + + +/* GPIO - Register accessors */ +#define GPIO_DR_REG(base) ((base)->DR) +#define GPIO_GDIR_REG(base) ((base)->GDIR) +#define GPIO_PSR_REG(base) ((base)->PSR) +#define GPIO_ICR1_REG(base) ((base)->ICR1) +#define GPIO_ICR2_REG(base) ((base)->ICR2) +#define GPIO_IMR_REG(base) ((base)->IMR) +#define GPIO_ISR_REG(base) ((base)->ISR) +#define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) + +/*! + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* DR Bit Fields */ +#define GPIO_DR_DR_MASK 0xFFFFFFFFu +#define GPIO_DR_DR_SHIFT 0 +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_DR_DR_SHIFT))&GPIO_DR_DR_MASK) +/* GDIR Bit Fields */ +#define GPIO_GDIR_GDIR_MASK 0xFFFFFFFFu +#define GPIO_GDIR_GDIR_SHIFT 0 +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_GDIR_GDIR_SHIFT))&GPIO_GDIR_GDIR_MASK) +/* PSR Bit Fields */ +#define GPIO_PSR_PSR_MASK 0xFFFFFFFFu +#define GPIO_PSR_PSR_SHIFT 0 +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSR_PSR_SHIFT))&GPIO_PSR_PSR_MASK) +/* ICR1 Bit Fields */ +#define GPIO_ICR1_ICR0_MASK 0x3u +#define GPIO_ICR1_ICR0_SHIFT 0 +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR0_SHIFT))&GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK 0xCu +#define GPIO_ICR1_ICR1_SHIFT 2 +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR1_SHIFT))&GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK 0x30u +#define GPIO_ICR1_ICR2_SHIFT 4 +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR2_SHIFT))&GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK 0xC0u +#define GPIO_ICR1_ICR3_SHIFT 6 +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR3_SHIFT))&GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK 0x300u +#define GPIO_ICR1_ICR4_SHIFT 8 +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR4_SHIFT))&GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK 0xC00u +#define GPIO_ICR1_ICR5_SHIFT 10 +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR5_SHIFT))&GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK 0x3000u +#define GPIO_ICR1_ICR6_SHIFT 12 +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR6_SHIFT))&GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK 0xC000u +#define GPIO_ICR1_ICR7_SHIFT 14 +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR7_SHIFT))&GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK 0x30000u +#define GPIO_ICR1_ICR8_SHIFT 16 +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR8_SHIFT))&GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK 0xC0000u +#define GPIO_ICR1_ICR9_SHIFT 18 +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR9_SHIFT))&GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK 0x300000u +#define GPIO_ICR1_ICR10_SHIFT 20 +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR10_SHIFT))&GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK 0xC00000u +#define GPIO_ICR1_ICR11_SHIFT 22 +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR11_SHIFT))&GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK 0x3000000u +#define GPIO_ICR1_ICR12_SHIFT 24 +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR12_SHIFT))&GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK 0xC000000u +#define GPIO_ICR1_ICR13_SHIFT 26 +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR13_SHIFT))&GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK 0x30000000u +#define GPIO_ICR1_ICR14_SHIFT 28 +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR14_SHIFT))&GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK 0xC0000000u +#define GPIO_ICR1_ICR15_SHIFT 30 +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR15_SHIFT))&GPIO_ICR1_ICR15_MASK) +/* ICR2 Bit Fields */ +#define GPIO_ICR2_ICR16_MASK 0x3u +#define GPIO_ICR2_ICR16_SHIFT 0 +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR16_SHIFT))&GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK 0xCu +#define GPIO_ICR2_ICR17_SHIFT 2 +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR17_SHIFT))&GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK 0x30u +#define GPIO_ICR2_ICR18_SHIFT 4 +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR18_SHIFT))&GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK 0xC0u +#define GPIO_ICR2_ICR19_SHIFT 6 +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR19_SHIFT))&GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK 0x300u +#define GPIO_ICR2_ICR20_SHIFT 8 +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR20_SHIFT))&GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK 0xC00u +#define GPIO_ICR2_ICR21_SHIFT 10 +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR21_SHIFT))&GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK 0x3000u +#define GPIO_ICR2_ICR22_SHIFT 12 +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR22_SHIFT))&GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK 0xC000u +#define GPIO_ICR2_ICR23_SHIFT 14 +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR23_SHIFT))&GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK 0x30000u +#define GPIO_ICR2_ICR24_SHIFT 16 +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR24_SHIFT))&GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK 0xC0000u +#define GPIO_ICR2_ICR25_SHIFT 18 +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR25_SHIFT))&GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK 0x300000u +#define GPIO_ICR2_ICR26_SHIFT 20 +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR26_SHIFT))&GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK 0xC00000u +#define GPIO_ICR2_ICR27_SHIFT 22 +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR27_SHIFT))&GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK 0x3000000u +#define GPIO_ICR2_ICR28_SHIFT 24 +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR28_SHIFT))&GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK 0xC000000u +#define GPIO_ICR2_ICR29_SHIFT 26 +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR29_SHIFT))&GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK 0x30000000u +#define GPIO_ICR2_ICR30_SHIFT 28 +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR30_SHIFT))&GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK 0xC0000000u +#define GPIO_ICR2_ICR31_SHIFT 30 +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR2_ICR31_SHIFT))&GPIO_ICR2_ICR31_MASK) +/* IMR Bit Fields */ +#define GPIO_IMR_IMR_MASK 0xFFFFFFFFu +#define GPIO_IMR_IMR_SHIFT 0 +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_IMR_IMR_SHIFT))&GPIO_IMR_IMR_MASK) +/* ISR Bit Fields */ +#define GPIO_ISR_ISR_MASK 0xFFFFFFFFu +#define GPIO_ISR_ISR_SHIFT 0 +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x))<<GPIO_ISR_ISR_SHIFT))&GPIO_ISR_ISR_MASK) +/* EDGE_SEL Bit Fields */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK 0xFFFFFFFFu +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT 0 +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT))&GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x30200000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +#define GPIO1_BASE_PTR (GPIO1) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x30210000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +#define GPIO2_BASE_PTR (GPIO2) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x30220000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +#define GPIO3_BASE_PTR (GPIO3) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x30230000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +#define GPIO4_BASE_PTR (GPIO4) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x30240000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +#define GPIO5_BASE_PTR (GPIO5) +/** Peripheral GPIO6 base address */ +#define GPIO6_BASE (0x30250000u) +/** Peripheral GPIO6 base pointer */ +#define GPIO6 ((GPIO_Type *)GPIO6_BASE) +#define GPIO6_BASE_PTR (GPIO6) +/** Peripheral GPIO7 base address */ +#define GPIO7_BASE (0x30260000u) +/** Peripheral GPIO7 base pointer */ +#define GPIO7 ((GPIO_Type *)GPIO7_BASE) +#define GPIO7_BASE_PTR (GPIO7) +/** Array initializer of GPIO peripheral base adresses */ +#define GPIO_BASE_ADDRS { GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7 } + +/* ---------------------------------------------------------------------------- + -- GPIO - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros + * @{ + */ + + +/* GPIO - Register instance definitions */ +/* GPIO1 */ +#define GPIO1_DR GPIO_DR_REG(GPIO1_BASE_PTR) +#define GPIO1_GDIR GPIO_GDIR_REG(GPIO1_BASE_PTR) +#define GPIO1_PSR GPIO_PSR_REG(GPIO1_BASE_PTR) +#define GPIO1_ICR1 GPIO_ICR1_REG(GPIO1_BASE_PTR) +#define GPIO1_ICR2 GPIO_ICR2_REG(GPIO1_BASE_PTR) +#define GPIO1_IMR GPIO_IMR_REG(GPIO1_BASE_PTR) +#define GPIO1_ISR GPIO_ISR_REG(GPIO1_BASE_PTR) +#define GPIO1_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO1_BASE_PTR) +/* GPIO2 */ +#define GPIO2_DR GPIO_DR_REG(GPIO2_BASE_PTR) +#define GPIO2_GDIR GPIO_GDIR_REG(GPIO2_BASE_PTR) +#define GPIO2_PSR GPIO_PSR_REG(GPIO2_BASE_PTR) +#define GPIO2_ICR1 GPIO_ICR1_REG(GPIO2_BASE_PTR) +#define GPIO2_ICR2 GPIO_ICR2_REG(GPIO2_BASE_PTR) +#define GPIO2_IMR GPIO_IMR_REG(GPIO2_BASE_PTR) +#define GPIO2_ISR GPIO_ISR_REG(GPIO2_BASE_PTR) +#define GPIO2_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO2_BASE_PTR) +/* GPIO3 */ +#define GPIO3_DR GPIO_DR_REG(GPIO3_BASE_PTR) +#define GPIO3_GDIR GPIO_GDIR_REG(GPIO3_BASE_PTR) +#define GPIO3_PSR GPIO_PSR_REG(GPIO3_BASE_PTR) +#define GPIO3_ICR1 GPIO_ICR1_REG(GPIO3_BASE_PTR) +#define GPIO3_ICR2 GPIO_ICR2_REG(GPIO3_BASE_PTR) +#define GPIO3_IMR GPIO_IMR_REG(GPIO3_BASE_PTR) +#define GPIO3_ISR GPIO_ISR_REG(GPIO3_BASE_PTR) +#define GPIO3_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO3_BASE_PTR) +/* GPIO4 */ +#define GPIO4_DR GPIO_DR_REG(GPIO4_BASE_PTR) +#define GPIO4_GDIR GPIO_GDIR_REG(GPIO4_BASE_PTR) +#define GPIO4_PSR GPIO_PSR_REG(GPIO4_BASE_PTR) +#define GPIO4_ICR1 GPIO_ICR1_REG(GPIO4_BASE_PTR) +#define GPIO4_ICR2 GPIO_ICR2_REG(GPIO4_BASE_PTR) +#define GPIO4_IMR GPIO_IMR_REG(GPIO4_BASE_PTR) +#define GPIO4_ISR GPIO_ISR_REG(GPIO4_BASE_PTR) +#define GPIO4_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO4_BASE_PTR) +/* GPIO5 */ +#define GPIO5_DR GPIO_DR_REG(GPIO5_BASE_PTR) +#define GPIO5_GDIR GPIO_GDIR_REG(GPIO5_BASE_PTR) +#define GPIO5_PSR GPIO_PSR_REG(GPIO5_BASE_PTR) +#define GPIO5_ICR1 GPIO_ICR1_REG(GPIO5_BASE_PTR) +#define GPIO5_ICR2 GPIO_ICR2_REG(GPIO5_BASE_PTR) +#define GPIO5_IMR GPIO_IMR_REG(GPIO5_BASE_PTR) +#define GPIO5_ISR GPIO_ISR_REG(GPIO5_BASE_PTR) +#define GPIO5_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO5_BASE_PTR) +/* GPIO6 */ +#define GPIO6_DR GPIO_DR_REG(GPIO6_BASE_PTR) +#define GPIO6_GDIR GPIO_GDIR_REG(GPIO6_BASE_PTR) +#define GPIO6_PSR GPIO_PSR_REG(GPIO6_BASE_PTR) +#define GPIO6_ICR1 GPIO_ICR1_REG(GPIO6_BASE_PTR) +#define GPIO6_ICR2 GPIO_ICR2_REG(GPIO6_BASE_PTR) +#define GPIO6_IMR GPIO_IMR_REG(GPIO6_BASE_PTR) +#define GPIO6_ISR GPIO_ISR_REG(GPIO6_BASE_PTR) +#define GPIO6_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO6_BASE_PTR) +/* GPIO7 */ +#define GPIO7_DR GPIO_DR_REG(GPIO7_BASE_PTR) +#define GPIO7_GDIR GPIO_GDIR_REG(GPIO7_BASE_PTR) +#define GPIO7_PSR GPIO_PSR_REG(GPIO7_BASE_PTR) +#define GPIO7_ICR1 GPIO_ICR1_REG(GPIO7_BASE_PTR) +#define GPIO7_ICR2 GPIO_ICR2_REG(GPIO7_BASE_PTR) +#define GPIO7_IMR GPIO_IMR_REG(GPIO7_BASE_PTR) +#define GPIO7_ISR GPIO_ISR_REG(GPIO7_BASE_PTR) +#define GPIO7_EDGE_SEL GPIO_EDGE_SEL_REG(GPIO7_BASE_PTR) + +/*! + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group GPIO_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- GPMI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer + * @{ + */ + +/** GPMI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ + __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ + __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ + __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ + __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ + __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ + uint8_t RESERVED_2[12]; + __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ + __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ + __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ + __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ + __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t DEBUG; /**< GPMI Debug Information Register Description, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __I uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ + uint8_t RESERVED_11[12]; + __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ + uint8_t RESERVED_13[28]; + __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ +} GPMI_Type, *GPMI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- GPMI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros + * @{ + */ + + +/* GPMI - Register accessors */ +#define GPMI_CTRL0_REG(base) ((base)->CTRL0) +#define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define GPMI_COMPARE_REG(base) ((base)->COMPARE) +#define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) +#define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) +#define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) +#define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) +#define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) +#define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) +#define GPMI_CTRL1_REG(base) ((base)->CTRL1) +#define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define GPMI_TIMING0_REG(base) ((base)->TIMING0) +#define GPMI_TIMING1_REG(base) ((base)->TIMING1) +#define GPMI_TIMING2_REG(base) ((base)->TIMING2) +#define GPMI_DATA_REG(base) ((base)->DATA) +#define GPMI_STAT_REG(base) ((base)->STAT) +#define GPMI_DEBUG_REG(base) ((base)->DEBUG) +#define GPMI_VERSION_REG(base) ((base)->VERSION) +#define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) +#define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) +#define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) +#define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) + +/*! + * @} + */ /* end of group GPMI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_XFER_COUNT_SHIFT))&GPMI_CTRL0_XFER_COUNT_MASK) +#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK 0x10000u +#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT 16 +#define GPMI_CTRL0_ADDRESS_MASK 0xE0000u +#define GPMI_CTRL0_ADDRESS_SHIFT 17 +#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_ADDRESS_SHIFT))&GPMI_CTRL0_ADDRESS_MASK) +#define GPMI_CTRL0_CS_MASK 0x700000u +#define GPMI_CTRL0_CS_SHIFT 20 +#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CS_SHIFT))&GPMI_CTRL0_CS_MASK) +#define GPMI_CTRL0_WORD_LENGTH_MASK 0x800000u +#define GPMI_CTRL0_WORD_LENGTH_SHIFT 23 +#define GPMI_CTRL0_COMMAND_MODE_MASK 0x3000000u +#define GPMI_CTRL0_COMMAND_MODE_SHIFT 24 +#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_COMMAND_MODE_SHIFT))&GPMI_CTRL0_COMMAND_MODE_MASK) +#define GPMI_CTRL0_UDMA_MASK 0x4000000u +#define GPMI_CTRL0_UDMA_SHIFT 26 +#define GPMI_CTRL0_LOCK_CS_MASK 0x8000000u +#define GPMI_CTRL0_LOCK_CS_SHIFT 27 +#define GPMI_CTRL0_DEV_IRQ_EN_MASK 0x10000000u +#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT 28 +#define GPMI_CTRL0_RUN_MASK 0x20000000u +#define GPMI_CTRL0_RUN_SHIFT 29 +#define GPMI_CTRL0_CLKGATE_MASK 0x40000000u +#define GPMI_CTRL0_CLKGATE_SHIFT 30 +#define GPMI_CTRL0_SFTRST_MASK 0x80000000u +#define GPMI_CTRL0_SFTRST_SHIFT 31 +/* CTRL0_SET Bit Fields */ +#define GPMI_CTRL0_SET_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_XFER_COUNT_SHIFT))&GPMI_CTRL0_SET_XFER_COUNT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK 0x10000u +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT 16 +#define GPMI_CTRL0_SET_ADDRESS_MASK 0xE0000u +#define GPMI_CTRL0_SET_ADDRESS_SHIFT 17 +#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_ADDRESS_SHIFT))&GPMI_CTRL0_SET_ADDRESS_MASK) +#define GPMI_CTRL0_SET_CS_MASK 0x700000u +#define GPMI_CTRL0_SET_CS_SHIFT 20 +#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_CS_SHIFT))&GPMI_CTRL0_SET_CS_MASK) +#define GPMI_CTRL0_SET_WORD_LENGTH_MASK 0x800000u +#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT 23 +#define GPMI_CTRL0_SET_COMMAND_MODE_MASK 0x3000000u +#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT 24 +#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_SET_COMMAND_MODE_SHIFT))&GPMI_CTRL0_SET_COMMAND_MODE_MASK) +#define GPMI_CTRL0_SET_UDMA_MASK 0x4000000u +#define GPMI_CTRL0_SET_UDMA_SHIFT 26 +#define GPMI_CTRL0_SET_LOCK_CS_MASK 0x8000000u +#define GPMI_CTRL0_SET_LOCK_CS_SHIFT 27 +#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK 0x10000000u +#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT 28 +#define GPMI_CTRL0_SET_RUN_MASK 0x20000000u +#define GPMI_CTRL0_SET_RUN_SHIFT 29 +#define GPMI_CTRL0_SET_CLKGATE_MASK 0x40000000u +#define GPMI_CTRL0_SET_CLKGATE_SHIFT 30 +#define GPMI_CTRL0_SET_SFTRST_MASK 0x80000000u +#define GPMI_CTRL0_SET_SFTRST_SHIFT 31 +/* CTRL0_CLR Bit Fields */ +#define GPMI_CTRL0_CLR_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_XFER_COUNT_SHIFT))&GPMI_CTRL0_CLR_XFER_COUNT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK 0x10000u +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT 16 +#define GPMI_CTRL0_CLR_ADDRESS_MASK 0xE0000u +#define GPMI_CTRL0_CLR_ADDRESS_SHIFT 17 +#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_ADDRESS_SHIFT))&GPMI_CTRL0_CLR_ADDRESS_MASK) +#define GPMI_CTRL0_CLR_CS_MASK 0x700000u +#define GPMI_CTRL0_CLR_CS_SHIFT 20 +#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_CS_SHIFT))&GPMI_CTRL0_CLR_CS_MASK) +#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK 0x800000u +#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT 23 +#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK 0x3000000u +#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT 24 +#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT))&GPMI_CTRL0_CLR_COMMAND_MODE_MASK) +#define GPMI_CTRL0_CLR_UDMA_MASK 0x4000000u +#define GPMI_CTRL0_CLR_UDMA_SHIFT 26 +#define GPMI_CTRL0_CLR_LOCK_CS_MASK 0x8000000u +#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT 27 +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK 0x10000000u +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT 28 +#define GPMI_CTRL0_CLR_RUN_MASK 0x20000000u +#define GPMI_CTRL0_CLR_RUN_SHIFT 29 +#define GPMI_CTRL0_CLR_CLKGATE_MASK 0x40000000u +#define GPMI_CTRL0_CLR_CLKGATE_SHIFT 30 +#define GPMI_CTRL0_CLR_SFTRST_MASK 0x80000000u +#define GPMI_CTRL0_CLR_SFTRST_SHIFT 31 +/* CTRL0_TOG Bit Fields */ +#define GPMI_CTRL0_TOG_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_XFER_COUNT_SHIFT))&GPMI_CTRL0_TOG_XFER_COUNT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK 0x10000u +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT 16 +#define GPMI_CTRL0_TOG_ADDRESS_MASK 0xE0000u +#define GPMI_CTRL0_TOG_ADDRESS_SHIFT 17 +#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_ADDRESS_SHIFT))&GPMI_CTRL0_TOG_ADDRESS_MASK) +#define GPMI_CTRL0_TOG_CS_MASK 0x700000u +#define GPMI_CTRL0_TOG_CS_SHIFT 20 +#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_CS_SHIFT))&GPMI_CTRL0_TOG_CS_MASK) +#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK 0x800000u +#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT 23 +#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK 0x3000000u +#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT 24 +#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT))&GPMI_CTRL0_TOG_COMMAND_MODE_MASK) +#define GPMI_CTRL0_TOG_UDMA_MASK 0x4000000u +#define GPMI_CTRL0_TOG_UDMA_SHIFT 26 +#define GPMI_CTRL0_TOG_LOCK_CS_MASK 0x8000000u +#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT 27 +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK 0x10000000u +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT 28 +#define GPMI_CTRL0_TOG_RUN_MASK 0x20000000u +#define GPMI_CTRL0_TOG_RUN_SHIFT 29 +#define GPMI_CTRL0_TOG_CLKGATE_MASK 0x40000000u +#define GPMI_CTRL0_TOG_CLKGATE_SHIFT 30 +#define GPMI_CTRL0_TOG_SFTRST_MASK 0x80000000u +#define GPMI_CTRL0_TOG_SFTRST_SHIFT 31 +/* COMPARE Bit Fields */ +#define GPMI_COMPARE_REFERENCE_MASK 0xFFFFu +#define GPMI_COMPARE_REFERENCE_SHIFT 0 +#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_REFERENCE_SHIFT))&GPMI_COMPARE_REFERENCE_MASK) +#define GPMI_COMPARE_MASK_MASK 0xFFFF0000u +#define GPMI_COMPARE_MASK_SHIFT 16 +#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_COMPARE_MASK_SHIFT))&GPMI_COMPARE_MASK_MASK) +/* ECCCTRL Bit Fields */ +#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1FFu +#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT 0 +#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_RSVD1_MASK 0xE00u +#define GPMI_ECCCTRL_RSVD1_SHIFT 9 +#define GPMI_ECCCTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_RSVD1_SHIFT))&GPMI_ECCCTRL_RSVD1_MASK) +#define GPMI_ECCCTRL_ENABLE_ECC_MASK 0x1000u +#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT 12 +#define GPMI_ECCCTRL_ECC_CMD_MASK 0x6000u +#define GPMI_ECCCTRL_ECC_CMD_SHIFT 13 +#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_ECC_CMD_SHIFT))&GPMI_ECCCTRL_ECC_CMD_MASK) +#define GPMI_ECCCTRL_RSVD2_MASK 0x8000u +#define GPMI_ECCCTRL_RSVD2_SHIFT 15 +#define GPMI_ECCCTRL_HANDLE_MASK 0xFFFF0000u +#define GPMI_ECCCTRL_HANDLE_SHIFT 16 +#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_HANDLE_SHIFT))&GPMI_ECCCTRL_HANDLE_MASK) +/* ECCCTRL_SET Bit Fields */ +#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK 0x1FFu +#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT 0 +#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_SET_RSVD1_MASK 0xE00u +#define GPMI_ECCCTRL_SET_RSVD1_SHIFT 9 +#define GPMI_ECCCTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_RSVD1_SHIFT))&GPMI_ECCCTRL_SET_RSVD1_MASK) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK 0x1000u +#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT 12 +#define GPMI_ECCCTRL_SET_ECC_CMD_MASK 0x6000u +#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT 13 +#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_ECC_CMD_SHIFT))&GPMI_ECCCTRL_SET_ECC_CMD_MASK) +#define GPMI_ECCCTRL_SET_RSVD2_MASK 0x8000u +#define GPMI_ECCCTRL_SET_RSVD2_SHIFT 15 +#define GPMI_ECCCTRL_SET_HANDLE_MASK 0xFFFF0000u +#define GPMI_ECCCTRL_SET_HANDLE_SHIFT 16 +#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_SET_HANDLE_SHIFT))&GPMI_ECCCTRL_SET_HANDLE_MASK) +/* ECCCTRL_CLR Bit Fields */ +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK 0x1FFu +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT 0 +#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_CLR_RSVD1_MASK 0xE00u +#define GPMI_ECCCTRL_CLR_RSVD1_SHIFT 9 +#define GPMI_ECCCTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_RSVD1_SHIFT))&GPMI_ECCCTRL_CLR_RSVD1_MASK) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK 0x1000u +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT 12 +#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK 0x6000u +#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT 13 +#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT))&GPMI_ECCCTRL_CLR_ECC_CMD_MASK) +#define GPMI_ECCCTRL_CLR_RSVD2_MASK 0x8000u +#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT 15 +#define GPMI_ECCCTRL_CLR_HANDLE_MASK 0xFFFF0000u +#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT 16 +#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_CLR_HANDLE_SHIFT))&GPMI_ECCCTRL_CLR_HANDLE_MASK) +/* ECCCTRL_TOG Bit Fields */ +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK 0x1FFu +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT 0 +#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT))&GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_TOG_RSVD1_MASK 0xE00u +#define GPMI_ECCCTRL_TOG_RSVD1_SHIFT 9 +#define GPMI_ECCCTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_RSVD1_SHIFT))&GPMI_ECCCTRL_TOG_RSVD1_MASK) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK 0x1000u +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT 12 +#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK 0x6000u +#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT 13 +#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT))&GPMI_ECCCTRL_TOG_ECC_CMD_MASK) +#define GPMI_ECCCTRL_TOG_RSVD2_MASK 0x8000u +#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT 15 +#define GPMI_ECCCTRL_TOG_HANDLE_MASK 0xFFFF0000u +#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT 16 +#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCTRL_TOG_HANDLE_SHIFT))&GPMI_ECCCTRL_TOG_HANDLE_MASK) +/* ECCCOUNT Bit Fields */ +#define GPMI_ECCCOUNT_COUNT_MASK 0xFFFFu +#define GPMI_ECCCOUNT_COUNT_SHIFT 0 +#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_ECCCOUNT_COUNT_SHIFT))&GPMI_ECCCOUNT_COUNT_MASK) +/* PAYLOAD Bit Fields */ +#define GPMI_PAYLOAD_RSVD0_MASK 0x3u +#define GPMI_PAYLOAD_RSVD0_SHIFT 0 +#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_RSVD0_SHIFT))&GPMI_PAYLOAD_RSVD0_MASK) +#define GPMI_PAYLOAD_ADDRESS_MASK 0xFFFFFFFCu +#define GPMI_PAYLOAD_ADDRESS_SHIFT 2 +#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_PAYLOAD_ADDRESS_SHIFT))&GPMI_PAYLOAD_ADDRESS_MASK) +/* AUXILIARY Bit Fields */ +#define GPMI_AUXILIARY_RSVD0_MASK 0x3u +#define GPMI_AUXILIARY_RSVD0_SHIFT 0 +#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_RSVD0_SHIFT))&GPMI_AUXILIARY_RSVD0_MASK) +#define GPMI_AUXILIARY_ADDRESS_MASK 0xFFFFFFFCu +#define GPMI_AUXILIARY_ADDRESS_SHIFT 2 +#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<GPMI_AUXILIARY_ADDRESS_SHIFT))&GPMI_AUXILIARY_ADDRESS_MASK) +/* CTRL1 Bit Fields */ +#define GPMI_CTRL1_GPMI_MODE_MASK 0x1u +#define GPMI_CTRL1_GPMI_MODE_SHIFT 0 +#define GPMI_CTRL1_CAMERA_MODE_MASK 0x2u +#define GPMI_CTRL1_CAMERA_MODE_SHIFT 1 +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK 0x4u +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT 2 +#define GPMI_CTRL1_DEV_RESET_MASK 0x8u +#define GPMI_CTRL1_DEV_RESET_SHIFT 3 +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK 0x80u +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT 7 +#define GPMI_CTRL1_BURST_EN_MASK 0x100u +#define GPMI_CTRL1_BURST_EN_SHIFT 8 +#define GPMI_CTRL1_TIMEOUT_IRQ_MASK 0x200u +#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT 9 +#define GPMI_CTRL1_DEV_IRQ_MASK 0x400u +#define GPMI_CTRL1_DEV_IRQ_SHIFT 10 +#define GPMI_CTRL1_DMA2ECC_MODE_MASK 0x800u +#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT 11 +#define GPMI_CTRL1_RDN_DELAY_MASK 0xF000u +#define GPMI_CTRL1_RDN_DELAY_SHIFT 12 +#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_RDN_DELAY_SHIFT))&GPMI_CTRL1_RDN_DELAY_MASK) +#define GPMI_CTRL1_HALF_PERIOD_MASK 0x10000u +#define GPMI_CTRL1_HALF_PERIOD_SHIFT 16 +#define GPMI_CTRL1_DLL_ENABLE_MASK 0x20000u +#define GPMI_CTRL1_DLL_ENABLE_SHIFT 17 +#define GPMI_CTRL1_BCH_MODE_MASK 0x40000u +#define GPMI_CTRL1_BCH_MODE_SHIFT 18 +#define GPMI_CTRL1_GANGED_RDYBUSY_MASK 0x80000u +#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT 19 +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK 0x100000u +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT 20 +#define GPMI_CTRL1_TEST_TRIGGER_MASK 0x200000u +#define GPMI_CTRL1_TEST_TRIGGER_SHIFT 21 +#define GPMI_CTRL1_WRN_DLY_SEL_MASK 0xC00000u +#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT 22 +#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_DECOUPLE_CS_MASK 0x1000000u +#define GPMI_CTRL1_DECOUPLE_CS_SHIFT 24 +#define GPMI_CTRL1_SSYNCMODE_MASK 0x2000000u +#define GPMI_CTRL1_SSYNCMODE_SHIFT 25 +#define GPMI_CTRL1_UPDATE_CS_MASK 0x4000000u +#define GPMI_CTRL1_UPDATE_CS_SHIFT 26 +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK 0x8000000u +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT 27 +#define GPMI_CTRL1_TOGGLE_MODE_MASK 0x10000000u +#define GPMI_CTRL1_TOGGLE_MODE_SHIFT 28 +#define GPMI_CTRL1_WRITE_CLK_STOP_MASK 0x20000000u +#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT 29 +#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK 0x40000000u +#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT 30 +#define GPMI_CTRL1_DEV_CLK_STOP_MASK 0x80000000u +#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT 31 +/* CTRL1_SET Bit Fields */ +#define GPMI_CTRL1_SET_GPMI_MODE_MASK 0x1u +#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT 0 +#define GPMI_CTRL1_SET_CAMERA_MODE_MASK 0x2u +#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT 1 +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK 0x4u +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT 2 +#define GPMI_CTRL1_SET_DEV_RESET_MASK 0x8u +#define GPMI_CTRL1_SET_DEV_RESET_SHIFT 3 +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK 0x80u +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT 7 +#define GPMI_CTRL1_SET_BURST_EN_MASK 0x100u +#define GPMI_CTRL1_SET_BURST_EN_SHIFT 8 +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK 0x200u +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT 9 +#define GPMI_CTRL1_SET_DEV_IRQ_MASK 0x400u +#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT 10 +#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK 0x800u +#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT 11 +#define GPMI_CTRL1_SET_RDN_DELAY_MASK 0xF000u +#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT 12 +#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_RDN_DELAY_SHIFT))&GPMI_CTRL1_SET_RDN_DELAY_MASK) +#define GPMI_CTRL1_SET_HALF_PERIOD_MASK 0x10000u +#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT 16 +#define GPMI_CTRL1_SET_DLL_ENABLE_MASK 0x20000u +#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT 17 +#define GPMI_CTRL1_SET_BCH_MODE_MASK 0x40000u +#define GPMI_CTRL1_SET_BCH_MODE_SHIFT 18 +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK 0x80000u +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT 19 +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK 0x100000u +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT 20 +#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK 0x200000u +#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT 21 +#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK 0xC00000u +#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT 22 +#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK 0x1000000u +#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT 24 +#define GPMI_CTRL1_SET_SSYNCMODE_MASK 0x2000000u +#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT 25 +#define GPMI_CTRL1_SET_UPDATE_CS_MASK 0x4000000u +#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT 26 +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK 0x8000000u +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT 27 +#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK 0x10000000u +#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT 28 +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK 0x20000000u +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT 29 +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK 0x40000000u +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT 30 +#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK 0x80000000u +#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT 31 +/* CTRL1_CLR Bit Fields */ +#define GPMI_CTRL1_CLR_GPMI_MODE_MASK 0x1u +#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT 0 +#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK 0x2u +#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT 1 +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK 0x4u +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT 2 +#define GPMI_CTRL1_CLR_DEV_RESET_MASK 0x8u +#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT 3 +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK 0x80u +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT 7 +#define GPMI_CTRL1_CLR_BURST_EN_MASK 0x100u +#define GPMI_CTRL1_CLR_BURST_EN_SHIFT 8 +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK 0x200u +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT 9 +#define GPMI_CTRL1_CLR_DEV_IRQ_MASK 0x400u +#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT 10 +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK 0x800u +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT 11 +#define GPMI_CTRL1_CLR_RDN_DELAY_MASK 0xF000u +#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT 12 +#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_RDN_DELAY_SHIFT))&GPMI_CTRL1_CLR_RDN_DELAY_MASK) +#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK 0x10000u +#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT 16 +#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK 0x20000u +#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT 17 +#define GPMI_CTRL1_CLR_BCH_MODE_MASK 0x40000u +#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT 18 +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK 0x80000u +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT 19 +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK 0x100000u +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT 20 +#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK 0x200000u +#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT 21 +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK 0xC00000u +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT 22 +#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK 0x1000000u +#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT 24 +#define GPMI_CTRL1_CLR_SSYNCMODE_MASK 0x2000000u +#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT 25 +#define GPMI_CTRL1_CLR_UPDATE_CS_MASK 0x4000000u +#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT 26 +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK 0x8000000u +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT 27 +#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK 0x10000000u +#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT 28 +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK 0x20000000u +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT 29 +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK 0x40000000u +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT 30 +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK 0x80000000u +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT 31 +/* CTRL1_TOG Bit Fields */ +#define GPMI_CTRL1_TOG_GPMI_MODE_MASK 0x1u +#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT 0 +#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK 0x2u +#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT 1 +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK 0x4u +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT 2 +#define GPMI_CTRL1_TOG_DEV_RESET_MASK 0x8u +#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT 3 +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK 0x70u +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT 4 +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT))&GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK 0x80u +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT 7 +#define GPMI_CTRL1_TOG_BURST_EN_MASK 0x100u +#define GPMI_CTRL1_TOG_BURST_EN_SHIFT 8 +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK 0x200u +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT 9 +#define GPMI_CTRL1_TOG_DEV_IRQ_MASK 0x400u +#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT 10 +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK 0x800u +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT 11 +#define GPMI_CTRL1_TOG_RDN_DELAY_MASK 0xF000u +#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT 12 +#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_RDN_DELAY_SHIFT))&GPMI_CTRL1_TOG_RDN_DELAY_MASK) +#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK 0x10000u +#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT 16 +#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK 0x20000u +#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT 17 +#define GPMI_CTRL1_TOG_BCH_MODE_MASK 0x40000u +#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT 18 +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK 0x80000u +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT 19 +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK 0x100000u +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT 20 +#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK 0x200000u +#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT 21 +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK 0xC00000u +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT 22 +#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT))&GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK 0x1000000u +#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT 24 +#define GPMI_CTRL1_TOG_SSYNCMODE_MASK 0x2000000u +#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT 25 +#define GPMI_CTRL1_TOG_UPDATE_CS_MASK 0x4000000u +#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT 26 +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK 0x8000000u +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT 27 +#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK 0x10000000u +#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT 28 +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK 0x20000000u +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT 29 +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK 0x40000000u +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT 30 +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK 0x80000000u +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT 31 +/* TIMING0 Bit Fields */ +#define GPMI_TIMING0_DATA_SETUP_MASK 0xFFu +#define GPMI_TIMING0_DATA_SETUP_SHIFT 0 +#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_SETUP_SHIFT))&GPMI_TIMING0_DATA_SETUP_MASK) +#define GPMI_TIMING0_DATA_HOLD_MASK 0xFF00u +#define GPMI_TIMING0_DATA_HOLD_SHIFT 8 +#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_DATA_HOLD_SHIFT))&GPMI_TIMING0_DATA_HOLD_MASK) +#define GPMI_TIMING0_ADDRESS_SETUP_MASK 0xFF0000u +#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT 16 +#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_ADDRESS_SETUP_SHIFT))&GPMI_TIMING0_ADDRESS_SETUP_MASK) +#define GPMI_TIMING0_RSVD1_MASK 0xFF000000u +#define GPMI_TIMING0_RSVD1_SHIFT 24 +#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING0_RSVD1_SHIFT))&GPMI_TIMING0_RSVD1_MASK) +/* TIMING1 Bit Fields */ +#define GPMI_TIMING1_RSVD1_MASK 0xFFFFu +#define GPMI_TIMING1_RSVD1_SHIFT 0 +#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_RSVD1_SHIFT))&GPMI_TIMING1_RSVD1_MASK) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK 0xFFFF0000u +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT 16 +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT))&GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) +/* TIMING2 Bit Fields */ +#define GPMI_TIMING2_DATA_PAUSE_MASK 0xFu +#define GPMI_TIMING2_DATA_PAUSE_SHIFT 0 +#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_DATA_PAUSE_SHIFT))&GPMI_TIMING2_DATA_PAUSE_MASK) +#define GPMI_TIMING2_CMDADD_PAUSE_MASK 0xF0u +#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT 4 +#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CMDADD_PAUSE_SHIFT))&GPMI_TIMING2_CMDADD_PAUSE_MASK) +#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK 0xF00u +#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT 8 +#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT))&GPMI_TIMING2_POSTAMBLE_DELAY_MASK) +#define GPMI_TIMING2_PREAMBLE_DELAY_MASK 0xF000u +#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT 12 +#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_PREAMBLE_DELAY_SHIFT))&GPMI_TIMING2_PREAMBLE_DELAY_MASK) +#define GPMI_TIMING2_CE_DELAY_MASK 0x1F0000u +#define GPMI_TIMING2_CE_DELAY_SHIFT 16 +#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_CE_DELAY_SHIFT))&GPMI_TIMING2_CE_DELAY_MASK) +#define GPMI_TIMING2_RSVD0_MASK 0xE00000u +#define GPMI_TIMING2_RSVD0_SHIFT 21 +#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_RSVD0_SHIFT))&GPMI_TIMING2_RSVD0_MASK) +#define GPMI_TIMING2_READ_LATENCY_MASK 0x7000000u +#define GPMI_TIMING2_READ_LATENCY_SHIFT 24 +#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_READ_LATENCY_SHIFT))&GPMI_TIMING2_READ_LATENCY_MASK) +#define GPMI_TIMING2_TCR_MASK 0x18000000u +#define GPMI_TIMING2_TCR_SHIFT 27 +#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TCR_SHIFT))&GPMI_TIMING2_TCR_MASK) +#define GPMI_TIMING2_TRPSTH_MASK 0xE0000000u +#define GPMI_TIMING2_TRPSTH_SHIFT 29 +#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x))<<GPMI_TIMING2_TRPSTH_SHIFT))&GPMI_TIMING2_TRPSTH_MASK) +/* DATA Bit Fields */ +#define GPMI_DATA_DATA_MASK 0xFFFFFFFFu +#define GPMI_DATA_DATA_SHIFT 0 +#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DATA_DATA_SHIFT))&GPMI_DATA_DATA_MASK) +/* STAT Bit Fields */ +#define GPMI_STAT_PRESENT_MASK 0x1u +#define GPMI_STAT_PRESENT_SHIFT 0 +#define GPMI_STAT_FIFO_FULL_MASK 0x2u +#define GPMI_STAT_FIFO_FULL_SHIFT 1 +#define GPMI_STAT_FIFO_EMPTY_MASK 0x4u +#define GPMI_STAT_FIFO_EMPTY_SHIFT 2 +#define GPMI_STAT_INVALID_BUFFER_MASK_MASK 0x8u +#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT 3 +#define GPMI_STAT_ATA_IRQ_MASK 0x10u +#define GPMI_STAT_ATA_IRQ_SHIFT 4 +#define GPMI_STAT_RSVD1_MASK 0xE0u +#define GPMI_STAT_RSVD1_SHIFT 5 +#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RSVD1_SHIFT))&GPMI_STAT_RSVD1_MASK) +#define GPMI_STAT_DEV0_ERROR_MASK 0x100u +#define GPMI_STAT_DEV0_ERROR_SHIFT 8 +#define GPMI_STAT_DEV1_ERROR_MASK 0x200u +#define GPMI_STAT_DEV1_ERROR_SHIFT 9 +#define GPMI_STAT_DEV2_ERROR_MASK 0x400u +#define GPMI_STAT_DEV2_ERROR_SHIFT 10 +#define GPMI_STAT_DEV3_ERROR_MASK 0x800u +#define GPMI_STAT_DEV3_ERROR_SHIFT 11 +#define GPMI_STAT_DEV4_ERROR_MASK 0x1000u +#define GPMI_STAT_DEV4_ERROR_SHIFT 12 +#define GPMI_STAT_DEV5_ERROR_MASK 0x2000u +#define GPMI_STAT_DEV5_ERROR_SHIFT 13 +#define GPMI_STAT_DEV6_ERROR_MASK 0x4000u +#define GPMI_STAT_DEV6_ERROR_SHIFT 14 +#define GPMI_STAT_DEV7_ERROR_MASK 0x8000u +#define GPMI_STAT_DEV7_ERROR_SHIFT 15 +#define GPMI_STAT_RDY_TIMEOUT_MASK 0xFF0000u +#define GPMI_STAT_RDY_TIMEOUT_SHIFT 16 +#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_RDY_TIMEOUT_SHIFT))&GPMI_STAT_RDY_TIMEOUT_MASK) +#define GPMI_STAT_READY_BUSY_MASK 0xFF000000u +#define GPMI_STAT_READY_BUSY_SHIFT 24 +#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x))<<GPMI_STAT_READY_BUSY_SHIFT))&GPMI_STAT_READY_BUSY_MASK) +/* DEBUG Bit Fields */ +#define GPMI_DEBUG_CMD_END_MASK 0xFFu +#define GPMI_DEBUG_CMD_END_SHIFT 0 +#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_CMD_END_SHIFT))&GPMI_DEBUG_CMD_END_MASK) +#define GPMI_DEBUG_DMAREQ_MASK 0xFF00u +#define GPMI_DEBUG_DMAREQ_SHIFT 8 +#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMAREQ_SHIFT))&GPMI_DEBUG_DMAREQ_MASK) +#define GPMI_DEBUG_DMA_SENSE_MASK 0xFF0000u +#define GPMI_DEBUG_DMA_SENSE_SHIFT 16 +#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_DMA_SENSE_SHIFT))&GPMI_DEBUG_DMA_SENSE_MASK) +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK 0xFF000000u +#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT 24 +#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT))&GPMI_DEBUG_WAIT_FOR_READY_END_MASK) +/* VERSION Bit Fields */ +#define GPMI_VERSION_STEP_MASK 0xFFFFu +#define GPMI_VERSION_STEP_SHIFT 0 +#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_STEP_SHIFT))&GPMI_VERSION_STEP_MASK) +#define GPMI_VERSION_MINOR_MASK 0xFF0000u +#define GPMI_VERSION_MINOR_SHIFT 16 +#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MINOR_SHIFT))&GPMI_VERSION_MINOR_MASK) +#define GPMI_VERSION_MAJOR_MASK 0xFF000000u +#define GPMI_VERSION_MAJOR_SHIFT 24 +#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_VERSION_MAJOR_SHIFT))&GPMI_VERSION_MAJOR_MASK) +/* DEBUG2 Bit Fields */ +#define GPMI_DEBUG2_RDN_TAP_MASK 0x3Fu +#define GPMI_DEBUG2_RDN_TAP_SHIFT 0 +#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RDN_TAP_SHIFT))&GPMI_DEBUG2_RDN_TAP_MASK) +#define GPMI_DEBUG2_UPDATE_WINDOW_MASK 0x40u +#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT 6 +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK 0x80u +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT 7 +#define GPMI_DEBUG2_SYND2GPMI_READY_MASK 0x100u +#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT 8 +#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK 0x200u +#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT 9 +#define GPMI_DEBUG2_GPMI2SYND_READY_MASK 0x400u +#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT 10 +#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK 0x800u +#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT 11 +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK 0xF000u +#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT 12 +#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_SYND2GPMI_BE_SHIFT))&GPMI_DEBUG2_SYND2GPMI_BE_MASK) +#define GPMI_DEBUG2_MAIN_STATE_MASK 0xF0000u +#define GPMI_DEBUG2_MAIN_STATE_SHIFT 16 +#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_MAIN_STATE_SHIFT))&GPMI_DEBUG2_MAIN_STATE_MASK) +#define GPMI_DEBUG2_PIN_STATE_MASK 0x700000u +#define GPMI_DEBUG2_PIN_STATE_SHIFT 20 +#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_PIN_STATE_SHIFT))&GPMI_DEBUG2_PIN_STATE_MASK) +#define GPMI_DEBUG2_BUSY_MASK 0x800000u +#define GPMI_DEBUG2_BUSY_SHIFT 23 +#define GPMI_DEBUG2_UDMA_STATE_MASK 0xF000000u +#define GPMI_DEBUG2_UDMA_STATE_SHIFT 24 +#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_UDMA_STATE_SHIFT))&GPMI_DEBUG2_UDMA_STATE_MASK) +#define GPMI_DEBUG2_RSVD1_MASK 0xF0000000u +#define GPMI_DEBUG2_RSVD1_SHIFT 28 +#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG2_RSVD1_SHIFT))&GPMI_DEBUG2_RSVD1_MASK) +/* DEBUG3 Bit Fields */ +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xFFFFu +#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT 0 +#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT))&GPMI_DEBUG3_DEV_WORD_CNTR_MASK) +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK 0xFFFF0000u +#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT 16 +#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x))<<GPMI_DEBUG3_APB_WORD_CNTR_SHIFT))&GPMI_DEBUG3_APB_WORD_CNTR_MASK) +/* READ_DDR_DLL_CTRL Bit Fields */ +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK 0x1u +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT 0 +#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK 0x2u +#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT 1 +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK 0x78u +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK 0x80u +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT 7 +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK 0x100u +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT 8 +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK 0x200u +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT 9 +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0x3FC00u +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 10 +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK 0xC0000u +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT 18 +#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20 +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT))&GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) +/* READ_DDR_DLL_STS Bit Fields */ +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK 0x1u +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT 0 +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK 0x1FEu +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT 1 +#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK 0xFE00u +#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT 9 +#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK 0x10000u +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT 16 +#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK 0x1FE0000u +#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT 17 +#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT))&GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK 0xFE000000u +#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT 25 +#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT))&GPMI_READ_DDR_DLL_STS_RSVD1_MASK) + +/*! + * @} + */ /* end of group GPMI_Register_Masks */ + + +/* GPMI - Peripheral instance base addresses */ +/** Peripheral GPMI base address */ +#define GPMI_BASE (0x33002000u) +/** Peripheral GPMI base pointer */ +#define GPMI ((GPMI_Type *)GPMI_BASE) +#define GPMI_BASE_PTR (GPMI) +/** Array initializer of GPMI peripheral base adresses */ +#define GPMI_BASE_ADDRS { GPMI_BASE } +/** Array initializer of GPMI peripheral base pointers */ +#define GPMI_BASE_PTRS { GPMI } + +/* ---------------------------------------------------------------------------- + -- GPMI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Accessor_Macros GPMI - Register accessor macros + * @{ + */ + + +/* GPMI - Register instance definitions */ +/* GPMI */ +#define GPMI_CTRL0 GPMI_CTRL0_REG(GPMI_BASE_PTR) +#define GPMI_CTRL0_SET GPMI_CTRL0_SET_REG(GPMI_BASE_PTR) +#define GPMI_CTRL0_CLR GPMI_CTRL0_CLR_REG(GPMI_BASE_PTR) +#define GPMI_CTRL0_TOG GPMI_CTRL0_TOG_REG(GPMI_BASE_PTR) +#define GPMI_COMPARE GPMI_COMPARE_REG(GPMI_BASE_PTR) +#define GPMI_ECCCTRL GPMI_ECCCTRL_REG(GPMI_BASE_PTR) +#define GPMI_ECCCTRL_SET GPMI_ECCCTRL_SET_REG(GPMI_BASE_PTR) +#define GPMI_ECCCTRL_CLR GPMI_ECCCTRL_CLR_REG(GPMI_BASE_PTR) +#define GPMI_ECCCTRL_TOG GPMI_ECCCTRL_TOG_REG(GPMI_BASE_PTR) +#define GPMI_ECCCOUNT GPMI_ECCCOUNT_REG(GPMI_BASE_PTR) +#define GPMI_PAYLOAD GPMI_PAYLOAD_REG(GPMI_BASE_PTR) +#define GPMI_AUXILIARY GPMI_AUXILIARY_REG(GPMI_BASE_PTR) +#define GPMI_CTRL1 GPMI_CTRL1_REG(GPMI_BASE_PTR) +#define GPMI_CTRL1_SET GPMI_CTRL1_SET_REG(GPMI_BASE_PTR) +#define GPMI_CTRL1_CLR GPMI_CTRL1_CLR_REG(GPMI_BASE_PTR) +#define GPMI_CTRL1_TOG GPMI_CTRL1_TOG_REG(GPMI_BASE_PTR) +#define GPMI_TIMING0 GPMI_TIMING0_REG(GPMI_BASE_PTR) +#define GPMI_TIMING1 GPMI_TIMING1_REG(GPMI_BASE_PTR) +#define GPMI_TIMING2 GPMI_TIMING2_REG(GPMI_BASE_PTR) +#define GPMI_DATA GPMI_DATA_REG(GPMI_BASE_PTR) +#define GPMI_STAT GPMI_STAT_REG(GPMI_BASE_PTR) +#define GPMI_DEBUG GPMI_DEBUG_REG(GPMI_BASE_PTR) +#define GPMI_VERSION GPMI_VERSION_REG(GPMI_BASE_PTR) +#define GPMI_DEBUG2 GPMI_DEBUG2_REG(GPMI_BASE_PTR) +#define GPMI_DEBUG3 GPMI_DEBUG3_REG(GPMI_BASE_PTR) +#define GPMI_READ_DDR_DLL_CTRL GPMI_READ_DDR_DLL_CTRL_REG(GPMI_BASE_PTR) +#define GPMI_READ_DDR_DLL_STS GPMI_READ_DDR_DLL_STS_REG(GPMI_BASE_PTR) + +/*! + * @} + */ /* end of group GPMI_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group GPMI_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR1; /**< GPT Output Compare Register 1, offset: 0x10 */ + __IO uint32_t OCR2; /**< GPT Output Compare Register 2, offset: 0x14 */ + __IO uint32_t OCR3; /**< GPT Output Compare Register 3, offset: 0x18 */ + __I uint32_t ICR1; /**< GPT Input Capture Register 1, offset: 0x1C */ + __I uint32_t ICR2; /**< GPT Input Capture Register 2, offset: 0x20 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type, *GPT_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- GPT - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros + * @{ + */ + + +/* GPT - Register accessors */ +#define GPT_CR_REG(base) ((base)->CR) +#define GPT_PR_REG(base) ((base)->PR) +#define GPT_SR_REG(base) ((base)->SR) +#define GPT_IR_REG(base) ((base)->IR) +#define GPT_OCR1_REG(base) ((base)->OCR1) +#define GPT_OCR2_REG(base) ((base)->OCR2) +#define GPT_OCR3_REG(base) ((base)->OCR3) +#define GPT_ICR1_REG(base) ((base)->ICR1) +#define GPT_ICR2_REG(base) ((base)->ICR2) +#define GPT_CNT_REG(base) ((base)->CNT) + +/*! + * @} + */ /* end of group GPT_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define GPT_CR_EN_MASK 0x1u +#define GPT_CR_EN_SHIFT 0 +#define GPT_CR_ENMOD_MASK 0x2u +#define GPT_CR_ENMOD_SHIFT 1 +#define GPT_CR_DBGEN_MASK 0x4u +#define GPT_CR_DBGEN_SHIFT 2 +#define GPT_CR_WAITEN_MASK 0x8u +#define GPT_CR_WAITEN_SHIFT 3 +#define GPT_CR_DOZEEN_MASK 0x10u +#define GPT_CR_DOZEEN_SHIFT 4 +#define GPT_CR_STOPEN_MASK 0x20u +#define GPT_CR_STOPEN_SHIFT 5 +#define GPT_CR_CLKSRC_MASK 0x1C0u +#define GPT_CR_CLKSRC_SHIFT 6 +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_CLKSRC_SHIFT))&GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK 0x200u +#define GPT_CR_FRR_SHIFT 9 +#define GPT_CR_ENABLE_24MHZ_MASK 0x400u +#define GPT_CR_ENABLE_24MHZ_SHIFT 10 +#define GPT_CR_SWR_MASK 0x8000u +#define GPT_CR_SWR_SHIFT 15 +#define GPT_CR_IM1_MASK 0x30000u +#define GPT_CR_IM1_SHIFT 16 +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM1_SHIFT))&GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK 0xC0000u +#define GPT_CR_IM2_SHIFT 18 +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_IM2_SHIFT))&GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK 0x700000u +#define GPT_CR_OM1_SHIFT 20 +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM1_SHIFT))&GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK 0x3800000u +#define GPT_CR_OM2_SHIFT 23 +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM2_SHIFT))&GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK 0x1C000000u +#define GPT_CR_OM3_SHIFT 26 +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x))<<GPT_CR_OM3_SHIFT))&GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK 0x20000000u +#define GPT_CR_FO1_SHIFT 29 +#define GPT_CR_FO2_MASK 0x40000000u +#define GPT_CR_FO2_SHIFT 30 +#define GPT_CR_FO3_MASK 0x80000000u +#define GPT_CR_FO3_SHIFT 31 +/* PR Bit Fields */ +#define GPT_PR_PRESCALER_MASK 0xFFFu +#define GPT_PR_PRESCALER_SHIFT 0 +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER_SHIFT))&GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK 0xF000u +#define GPT_PR_PRESCALER24M_SHIFT 12 +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x))<<GPT_PR_PRESCALER24M_SHIFT))&GPT_PR_PRESCALER24M_MASK) +/* SR Bit Fields */ +#define GPT_SR_OF1_MASK 0x1u +#define GPT_SR_OF1_SHIFT 0 +#define GPT_SR_OF2_MASK 0x2u +#define GPT_SR_OF2_SHIFT 1 +#define GPT_SR_OF3_MASK 0x4u +#define GPT_SR_OF3_SHIFT 2 +#define GPT_SR_IF1_MASK 0x8u +#define GPT_SR_IF1_SHIFT 3 +#define GPT_SR_IF2_MASK 0x10u +#define GPT_SR_IF2_SHIFT 4 +#define GPT_SR_ROV_MASK 0x20u +#define GPT_SR_ROV_SHIFT 5 +/* IR Bit Fields */ +#define GPT_IR_OF1IE_MASK 0x1u +#define GPT_IR_OF1IE_SHIFT 0 +#define GPT_IR_OF2IE_MASK 0x2u +#define GPT_IR_OF2IE_SHIFT 1 +#define GPT_IR_OF3IE_MASK 0x4u +#define GPT_IR_OF3IE_SHIFT 2 +#define GPT_IR_IF1IE_MASK 0x8u +#define GPT_IR_IF1IE_SHIFT 3 +#define GPT_IR_IF2IE_MASK 0x10u +#define GPT_IR_IF2IE_SHIFT 4 +#define GPT_IR_ROVIE_MASK 0x20u +#define GPT_IR_ROVIE_SHIFT 5 +/* OCR1 Bit Fields */ +#define GPT_OCR1_COMP_MASK 0xFFFFFFFFu +#define GPT_OCR1_COMP_SHIFT 0 +#define GPT_OCR1_COMP(x) (((uint32_t)(((uint32_t)(x))<<GPT_OCR1_COMP_SHIFT))&GPT_OCR1_COMP_MASK) +/* OCR2 Bit Fields */ +#define GPT_OCR2_COMP_MASK 0xFFFFFFFFu +#define GPT_OCR2_COMP_SHIFT 0 +#define GPT_OCR2_COMP(x) (((uint32_t)(((uint32_t)(x))<<GPT_OCR2_COMP_SHIFT))&GPT_OCR2_COMP_MASK) +/* OCR3 Bit Fields */ +#define GPT_OCR3_COMP_MASK 0xFFFFFFFFu +#define GPT_OCR3_COMP_SHIFT 0 +#define GPT_OCR3_COMP(x) (((uint32_t)(((uint32_t)(x))<<GPT_OCR3_COMP_SHIFT))&GPT_OCR3_COMP_MASK) +/* ICR1 Bit Fields */ +#define GPT_ICR1_CAPT_MASK 0xFFFFFFFFu +#define GPT_ICR1_CAPT_SHIFT 0 +#define GPT_ICR1_CAPT(x) (((uint32_t)(((uint32_t)(x))<<GPT_ICR1_CAPT_SHIFT))&GPT_ICR1_CAPT_MASK) +/* ICR2 Bit Fields */ +#define GPT_ICR2_CAPT_MASK 0xFFFFFFFFu +#define GPT_ICR2_CAPT_SHIFT 0 +#define GPT_ICR2_CAPT(x) (((uint32_t)(((uint32_t)(x))<<GPT_ICR2_CAPT_SHIFT))&GPT_ICR2_CAPT_MASK) +/* CNT Bit Fields */ +#define GPT_CNT_COUNT_MASK 0xFFFFFFFFu +#define GPT_CNT_COUNT_SHIFT 0 +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<GPT_CNT_COUNT_SHIFT))&GPT_CNT_COUNT_MASK) + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x302D0000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +#define GPT1_BASE_PTR (GPT1) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x302E0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +#define GPT2_BASE_PTR (GPT2) +/** Peripheral GPT3 base address */ +#define GPT3_BASE (0x302F0000u) +/** Peripheral GPT3 base pointer */ +#define GPT3 ((GPT_Type *)GPT3_BASE) +#define GPT3_BASE_PTR (GPT3) +/** Peripheral GPT4 base address */ +#define GPT4_BASE (0x30300000u) +/** Peripheral GPT4 base pointer */ +#define GPT4 ((GPT_Type *)GPT4_BASE) +#define GPT4_BASE_PTR (GPT4) +/** Array initializer of GPT peripheral base adresses */ +#define GPT_BASE_ADDRS { GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { GPT1, GPT2, GPT3, GPT4 } + +/* ---------------------------------------------------------------------------- + -- GPT - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Accessor_Macros GPT - Register accessor macros + * @{ + */ + + +/* GPT - Register instance definitions */ +/* GPT1 */ +#define GPT1_CR GPT_CR_REG(GPT1_BASE_PTR) +#define GPT1_PR GPT_PR_REG(GPT1_BASE_PTR) +#define GPT1_SR GPT_SR_REG(GPT1_BASE_PTR) +#define GPT1_IR GPT_IR_REG(GPT1_BASE_PTR) +#define GPT1_OCR1 GPT_OCR1_REG(GPT1_BASE_PTR) +#define GPT1_OCR2 GPT_OCR2_REG(GPT1_BASE_PTR) +#define GPT1_OCR3 GPT_OCR3_REG(GPT1_BASE_PTR) +#define GPT1_ICR1 GPT_ICR1_REG(GPT1_BASE_PTR) +#define GPT1_ICR2 GPT_ICR2_REG(GPT1_BASE_PTR) +#define GPT1_CNT GPT_CNT_REG(GPT1_BASE_PTR) +/* GPT2 */ +#define GPT2_CR GPT_CR_REG(GPT2_BASE_PTR) +#define GPT2_PR GPT_PR_REG(GPT2_BASE_PTR) +#define GPT2_SR GPT_SR_REG(GPT2_BASE_PTR) +#define GPT2_IR GPT_IR_REG(GPT2_BASE_PTR) +#define GPT2_OCR1 GPT_OCR1_REG(GPT2_BASE_PTR) +#define GPT2_OCR2 GPT_OCR2_REG(GPT2_BASE_PTR) +#define GPT2_OCR3 GPT_OCR3_REG(GPT2_BASE_PTR) +#define GPT2_ICR1 GPT_ICR1_REG(GPT2_BASE_PTR) +#define GPT2_ICR2 GPT_ICR2_REG(GPT2_BASE_PTR) +#define GPT2_CNT GPT_CNT_REG(GPT2_BASE_PTR) +/* GPT3 */ +#define GPT3_CR GPT_CR_REG(GPT3_BASE_PTR) +#define GPT3_PR GPT_PR_REG(GPT3_BASE_PTR) +#define GPT3_SR GPT_SR_REG(GPT3_BASE_PTR) +#define GPT3_IR GPT_IR_REG(GPT3_BASE_PTR) +#define GPT3_OCR1 GPT_OCR1_REG(GPT3_BASE_PTR) +#define GPT3_OCR2 GPT_OCR2_REG(GPT3_BASE_PTR) +#define GPT3_OCR3 GPT_OCR3_REG(GPT3_BASE_PTR) +#define GPT3_ICR1 GPT_ICR1_REG(GPT3_BASE_PTR) +#define GPT3_ICR2 GPT_ICR2_REG(GPT3_BASE_PTR) +#define GPT3_CNT GPT_CNT_REG(GPT3_BASE_PTR) +/* GPT4 */ +#define GPT4_CR GPT_CR_REG(GPT4_BASE_PTR) +#define GPT4_PR GPT_PR_REG(GPT4_BASE_PTR) +#define GPT4_SR GPT_SR_REG(GPT4_BASE_PTR) +#define GPT4_IR GPT_IR_REG(GPT4_BASE_PTR) +#define GPT4_OCR1 GPT_OCR1_REG(GPT4_BASE_PTR) +#define GPT4_OCR2 GPT_OCR2_REG(GPT4_BASE_PTR) +#define GPT4_OCR3 GPT_OCR3_REG(GPT4_BASE_PTR) +#define GPT4_ICR1 GPT_ICR1_REG(GPT4_BASE_PTR) +#define GPT4_ICR2 GPT_ICR2_REG(GPT4_BASE_PTR) +#define GPT4_CNT GPT_CNT_REG(GPT4_BASE_PTR) + +/*! + * @} + */ /* end of group GPT_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group GPT_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ + uint8_t RESERVED_0[2]; + __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ + uint8_t RESERVED_1[2]; + __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ + uint8_t RESERVED_2[2]; + __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ + uint8_t RESERVED_3[2]; + __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ +} I2C_Type, *I2C_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- I2C - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros + * @{ + */ + + +/* I2C - Register accessors */ +#define I2C_IADR_REG(base) ((base)->IADR) +#define I2C_IFDR_REG(base) ((base)->IFDR) +#define I2C_I2CR_REG(base) ((base)->I2CR) +#define I2C_I2SR_REG(base) ((base)->I2SR) +#define I2C_I2DR_REG(base) ((base)->I2DR) + +/*! + * @} + */ /* end of group I2C_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* IADR Bit Fields */ +#define I2C_IADR_ADR_MASK 0xFEu +#define I2C_IADR_ADR_SHIFT 1 +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<<I2C_IADR_ADR_SHIFT))&I2C_IADR_ADR_MASK) +/* IFDR Bit Fields */ +#define I2C_IFDR_IC_MASK 0x3Fu +#define I2C_IFDR_IC_SHIFT 0 +#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x))<<I2C_IFDR_IC_SHIFT))&I2C_IFDR_IC_MASK) +/* I2CR Bit Fields */ +#define I2C_I2CR_RSTA_MASK 0x4u +#define I2C_I2CR_RSTA_SHIFT 2 +#define I2C_I2CR_TXAK_MASK 0x8u +#define I2C_I2CR_TXAK_SHIFT 3 +#define I2C_I2CR_MTX_MASK 0x10u +#define I2C_I2CR_MTX_SHIFT 4 +#define I2C_I2CR_MSTA_MASK 0x20u +#define I2C_I2CR_MSTA_SHIFT 5 +#define I2C_I2CR_IIEN_MASK 0x40u +#define I2C_I2CR_IIEN_SHIFT 6 +#define I2C_I2CR_IEN_MASK 0x80u +#define I2C_I2CR_IEN_SHIFT 7 +/* I2SR Bit Fields */ +#define I2C_I2SR_RXAK_MASK 0x1u +#define I2C_I2SR_RXAK_SHIFT 0 +#define I2C_I2SR_IIF_MASK 0x2u +#define I2C_I2SR_IIF_SHIFT 1 +#define I2C_I2SR_SRW_MASK 0x4u +#define I2C_I2SR_SRW_SHIFT 2 +#define I2C_I2SR_IAL_MASK 0x10u +#define I2C_I2SR_IAL_SHIFT 4 +#define I2C_I2SR_IBB_MASK 0x20u +#define I2C_I2SR_IBB_SHIFT 5 +#define I2C_I2SR_IAAS_MASK 0x40u +#define I2C_I2SR_IAAS_SHIFT 6 +#define I2C_I2SR_ICF_MASK 0x80u +#define I2C_I2SR_ICF_SHIFT 7 +/* I2DR Bit Fields */ +#define I2C_I2DR_DATA_MASK 0xFFu +#define I2C_I2DR_DATA_SHIFT 0 +#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x))<<I2C_I2DR_DATA_SHIFT))&I2C_I2DR_DATA_MASK) + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x30A20000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +#define I2C1_BASE_PTR (I2C1) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x30A30000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +#define I2C2_BASE_PTR (I2C2) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x30A40000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +#define I2C3_BASE_PTR (I2C3) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x30A50000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +#define I2C4_BASE_PTR (I2C4) +/** Array initializer of I2C peripheral base adresses */ +#define I2C_BASE_ADDRS { I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C1, I2C2, I2C3, I2C4 } + +/* ---------------------------------------------------------------------------- + -- I2C - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros + * @{ + */ + + +/* I2C - Register instance definitions */ +/* I2C1 */ +#define I2C1_IADR I2C_IADR_REG(I2C1_BASE_PTR) +#define I2C1_IFDR I2C_IFDR_REG(I2C1_BASE_PTR) +#define I2C1_I2CR I2C_I2CR_REG(I2C1_BASE_PTR) +#define I2C1_I2SR I2C_I2SR_REG(I2C1_BASE_PTR) +#define I2C1_I2DR I2C_I2DR_REG(I2C1_BASE_PTR) +/* I2C2 */ +#define I2C2_IADR I2C_IADR_REG(I2C2_BASE_PTR) +#define I2C2_IFDR I2C_IFDR_REG(I2C2_BASE_PTR) +#define I2C2_I2CR I2C_I2CR_REG(I2C2_BASE_PTR) +#define I2C2_I2SR I2C_I2SR_REG(I2C2_BASE_PTR) +#define I2C2_I2DR I2C_I2DR_REG(I2C2_BASE_PTR) +/* I2C3 */ +#define I2C3_IADR I2C_IADR_REG(I2C3_BASE_PTR) +#define I2C3_IFDR I2C_IFDR_REG(I2C3_BASE_PTR) +#define I2C3_I2CR I2C_I2CR_REG(I2C3_BASE_PTR) +#define I2C3_I2SR I2C_I2SR_REG(I2C3_BASE_PTR) +#define I2C3_I2DR I2C_I2DR_REG(I2C3_BASE_PTR) +/* I2C4 */ +#define I2C4_IADR I2C_IADR_REG(I2C4_BASE_PTR) +#define I2C4_IFDR I2C_IFDR_REG(I2C4_BASE_PTR) +#define I2C4_I2CR I2C_I2CR_REG(I2C4_BASE_PTR) +#define I2C4_I2SR I2C_I2SR_REG(I2C4_BASE_PTR) +#define I2C4_I2DR I2C_I2DR_REG(I2C4_BASE_PTR) + +/*! + * @} + */ /* end of group I2C_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group I2C_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[28]; + __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[28]; + __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type, *I2S_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- I2S - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros + * @{ + */ + + +/* I2S - Register accessors */ +#define I2S_TCSR_REG(base) ((base)->TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) + +/*! + * @} + */ /* end of group I2S_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x1Fu +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK) +/* TCR2 Bit Fields */ +#define I2S_TCR2_DIV_MASK 0xFFu +#define I2S_TCR2_DIV_SHIFT 0 +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK 0x1000000u +#define I2S_TCR2_BCD_SHIFT 24 +#define I2S_TCR2_BCP_MASK 0x2000000u +#define I2S_TCR2_BCP_SHIFT 25 +#define I2S_TCR2_MSEL_MASK 0xC000000u +#define I2S_TCR2_MSEL_SHIFT 26 +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK 0x10000000u +#define I2S_TCR2_BCI_SHIFT 28 +#define I2S_TCR2_BCS_MASK 0x20000000u +#define I2S_TCR2_BCS_SHIFT 29 +#define I2S_TCR2_SYNC_MASK 0xC0000000u +#define I2S_TCR2_SYNC_SHIFT 30 +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK) +/* TCR3 Bit Fields */ +#define I2S_TCR3_WDFL_MASK 0x1Fu +#define I2S_TCR3_WDFL_SHIFT 0 +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK 0x10000u +#define I2S_TCR3_TCE_SHIFT 16 +/* TCR4 Bit Fields */ +#define I2S_TCR4_FSD_MASK 0x1u +#define I2S_TCR4_FSD_SHIFT 0 +#define I2S_TCR4_FSP_MASK 0x2u +#define I2S_TCR4_FSP_SHIFT 1 +#define I2S_TCR4_FSE_MASK 0x8u +#define I2S_TCR4_FSE_SHIFT 3 +#define I2S_TCR4_MF_MASK 0x10u +#define I2S_TCR4_MF_SHIFT 4 +#define I2S_TCR4_SYWD_MASK 0x1F00u +#define I2S_TCR4_SYWD_SHIFT 8 +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK 0x1F0000u +#define I2S_TCR4_FRSZ_SHIFT 16 +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK) +/* TCR5 Bit Fields */ +#define I2S_TCR5_FBT_MASK 0x1F00u +#define I2S_TCR5_FBT_SHIFT 8 +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK 0x1F0000u +#define I2S_TCR5_W0W_SHIFT 16 +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK 0x1F000000u +#define I2S_TCR5_WNW_SHIFT 24 +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) +/* TDR Bit Fields */ +#define I2S_TDR_TDR_MASK 0xFFFFFFFFu +#define I2S_TDR_TDR_SHIFT 0 +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) +/* TFR Bit Fields */ +#define I2S_TFR_RFP_MASK 0x3Fu +#define I2S_TFR_RFP_SHIFT 0 +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK 0x3F0000u +#define I2S_TFR_WFP_SHIFT 16 +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK) +/* TMR Bit Fields */ +#define I2S_TMR_TWM_MASK 0xFFFFFFFFu +#define I2S_TMR_TWM_SHIFT 0 +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) +/* RCSR Bit Fields */ +#define I2S_RCSR_FRDE_MASK 0x1u +#define I2S_RCSR_FRDE_SHIFT 0 +#define I2S_RCSR_FWDE_MASK 0x2u +#define I2S_RCSR_FWDE_SHIFT 1 +#define I2S_RCSR_FRIE_MASK 0x100u +#define I2S_RCSR_FRIE_SHIFT 8 +#define I2S_RCSR_FWIE_MASK 0x200u +#define I2S_RCSR_FWIE_SHIFT 9 +#define I2S_RCSR_FEIE_MASK 0x400u +#define I2S_RCSR_FEIE_SHIFT 10 +#define I2S_RCSR_SEIE_MASK 0x800u +#define I2S_RCSR_SEIE_SHIFT 11 +#define I2S_RCSR_WSIE_MASK 0x1000u +#define I2S_RCSR_WSIE_SHIFT 12 +#define I2S_RCSR_FRF_MASK 0x10000u +#define I2S_RCSR_FRF_SHIFT 16 +#define I2S_RCSR_FWF_MASK 0x20000u +#define I2S_RCSR_FWF_SHIFT 17 +#define I2S_RCSR_FEF_MASK 0x40000u +#define I2S_RCSR_FEF_SHIFT 18 +#define I2S_RCSR_SEF_MASK 0x80000u +#define I2S_RCSR_SEF_SHIFT 19 +#define I2S_RCSR_WSF_MASK 0x100000u +#define I2S_RCSR_WSF_SHIFT 20 +#define I2S_RCSR_SR_MASK 0x1000000u +#define I2S_RCSR_SR_SHIFT 24 +#define I2S_RCSR_FR_MASK 0x2000000u +#define I2S_RCSR_FR_SHIFT 25 +#define I2S_RCSR_BCE_MASK 0x10000000u +#define I2S_RCSR_BCE_SHIFT 28 +#define I2S_RCSR_DBGE_MASK 0x20000000u +#define I2S_RCSR_DBGE_SHIFT 29 +#define I2S_RCSR_STOPE_MASK 0x40000000u +#define I2S_RCSR_STOPE_SHIFT 30 +#define I2S_RCSR_RE_MASK 0x80000000u +#define I2S_RCSR_RE_SHIFT 31 +/* RCR1 Bit Fields */ +#define I2S_RCR1_RFW_MASK 0x1Fu +#define I2S_RCR1_RFW_SHIFT 0 +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK) +/* RCR2 Bit Fields */ +#define I2S_RCR2_DIV_MASK 0xFFu +#define I2S_RCR2_DIV_SHIFT 0 +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK 0x1000000u +#define I2S_RCR2_BCD_SHIFT 24 +#define I2S_RCR2_BCP_MASK 0x2000000u +#define I2S_RCR2_BCP_SHIFT 25 +#define I2S_RCR2_MSEL_MASK 0xC000000u +#define I2S_RCR2_MSEL_SHIFT 26 +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK 0x10000000u +#define I2S_RCR2_BCI_SHIFT 28 +#define I2S_RCR2_BCS_MASK 0x20000000u +#define I2S_RCR2_BCS_SHIFT 29 +#define I2S_RCR2_SYNC_MASK 0xC0000000u +#define I2S_RCR2_SYNC_SHIFT 30 +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK) +/* RCR3 Bit Fields */ +#define I2S_RCR3_WDFL_MASK 0x1Fu +#define I2S_RCR3_WDFL_SHIFT 0 +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK 0x10000u +#define I2S_RCR3_RCE_SHIFT 16 +/* RCR4 Bit Fields */ +#define I2S_RCR4_FSD_MASK 0x1u +#define I2S_RCR4_FSD_SHIFT 0 +#define I2S_RCR4_FSP_MASK 0x2u +#define I2S_RCR4_FSP_SHIFT 1 +#define I2S_RCR4_FSE_MASK 0x8u +#define I2S_RCR4_FSE_SHIFT 3 +#define I2S_RCR4_MF_MASK 0x10u +#define I2S_RCR4_MF_SHIFT 4 +#define I2S_RCR4_SYWD_MASK 0x1F00u +#define I2S_RCR4_SYWD_SHIFT 8 +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK 0x1F0000u +#define I2S_RCR4_FRSZ_SHIFT 16 +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK) +/* RCR5 Bit Fields */ +#define I2S_RCR5_FBT_MASK 0x1F00u +#define I2S_RCR5_FBT_SHIFT 8 +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK 0x1F0000u +#define I2S_RCR5_W0W_SHIFT 16 +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK 0x1F000000u +#define I2S_RCR5_WNW_SHIFT 24 +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) +/* RDR Bit Fields */ +#define I2S_RDR_RDR_MASK 0xFFFFFFFFu +#define I2S_RDR_RDR_SHIFT 0 +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) +/* RFR Bit Fields */ +#define I2S_RFR_RFP_MASK 0x3Fu +#define I2S_RFR_RFP_SHIFT 0 +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK 0x3F0000u +#define I2S_RFR_WFP_SHIFT 16 +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK) +/* RMR Bit Fields */ +#define I2S_RMR_RWM_MASK 0xFFFFFFFFu +#define I2S_RMR_RWM_SHIFT 0 +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x308A0000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +#define I2S1_BASE_PTR (I2S1) +/** Peripheral I2S2 base address */ +#define I2S2_BASE (0x308B0000u) +/** Peripheral I2S2 base pointer */ +#define I2S2 ((I2S_Type *)I2S2_BASE) +#define I2S2_BASE_PTR (I2S2) +/** Peripheral I2S3 base address */ +#define I2S3_BASE (0x308C0000u) +/** Peripheral I2S3 base pointer */ +#define I2S3 ((I2S_Type *)I2S3_BASE) +#define I2S3_BASE_PTR (I2S3) +/** Array initializer of I2S peripheral base adresses */ +#define I2S_BASE_ADDRS { I2S1_BASE, I2S2_BASE, I2S3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S1, I2S2, I2S3 } + +/* ---------------------------------------------------------------------------- + -- I2S - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros + * @{ + */ + + +/* I2S - Register instance definitions */ +/* I2S1 */ +#define I2S1_TCSR I2S_TCSR_REG(I2S1_BASE_PTR) +#define I2S1_TCR1 I2S_TCR1_REG(I2S1_BASE_PTR) +#define I2S1_TCR2 I2S_TCR2_REG(I2S1_BASE_PTR) +#define I2S1_TCR3 I2S_TCR3_REG(I2S1_BASE_PTR) +#define I2S1_TCR4 I2S_TCR4_REG(I2S1_BASE_PTR) +#define I2S1_TCR5 I2S_TCR5_REG(I2S1_BASE_PTR) +#define I2S1_TDR0 I2S_TDR_REG(I2S1_BASE_PTR,0) +#define I2S1_TFR0 I2S_TFR_REG(I2S1_BASE_PTR,0) +#define I2S1_TMR I2S_TMR_REG(I2S1_BASE_PTR) +#define I2S1_RCSR I2S_RCSR_REG(I2S1_BASE_PTR) +#define I2S1_RCR1 I2S_RCR1_REG(I2S1_BASE_PTR) +#define I2S1_RCR2 I2S_RCR2_REG(I2S1_BASE_PTR) +#define I2S1_RCR3 I2S_RCR3_REG(I2S1_BASE_PTR) +#define I2S1_RCR4 I2S_RCR4_REG(I2S1_BASE_PTR) +#define I2S1_RCR5 I2S_RCR5_REG(I2S1_BASE_PTR) +#define I2S1_RDR0 I2S_RDR_REG(I2S1_BASE_PTR,0) +#define I2S1_RFR0 I2S_RFR_REG(I2S1_BASE_PTR,0) +#define I2S1_RMR I2S_RMR_REG(I2S1_BASE_PTR) +/* I2S2 */ +#define I2S2_TCSR I2S_TCSR_REG(I2S2_BASE_PTR) +#define I2S2_TCR1 I2S_TCR1_REG(I2S2_BASE_PTR) +#define I2S2_TCR2 I2S_TCR2_REG(I2S2_BASE_PTR) +#define I2S2_TCR3 I2S_TCR3_REG(I2S2_BASE_PTR) +#define I2S2_TCR4 I2S_TCR4_REG(I2S2_BASE_PTR) +#define I2S2_TCR5 I2S_TCR5_REG(I2S2_BASE_PTR) +#define I2S2_TDR0 I2S_TDR_REG(I2S2_BASE_PTR,0) +#define I2S2_TFR0 I2S_TFR_REG(I2S2_BASE_PTR,0) +#define I2S2_TMR I2S_TMR_REG(I2S2_BASE_PTR) +#define I2S2_RCSR I2S_RCSR_REG(I2S2_BASE_PTR) +#define I2S2_RCR1 I2S_RCR1_REG(I2S2_BASE_PTR) +#define I2S2_RCR2 I2S_RCR2_REG(I2S2_BASE_PTR) +#define I2S2_RCR3 I2S_RCR3_REG(I2S2_BASE_PTR) +#define I2S2_RCR4 I2S_RCR4_REG(I2S2_BASE_PTR) +#define I2S2_RCR5 I2S_RCR5_REG(I2S2_BASE_PTR) +#define I2S2_RDR0 I2S_RDR_REG(I2S2_BASE_PTR,0) +#define I2S2_RFR0 I2S_RFR_REG(I2S2_BASE_PTR,0) +#define I2S2_RMR I2S_RMR_REG(I2S2_BASE_PTR) +/* I2S3 */ +#define I2S3_TCSR I2S_TCSR_REG(I2S3_BASE_PTR) +#define I2S3_TCR1 I2S_TCR1_REG(I2S3_BASE_PTR) +#define I2S3_TCR2 I2S_TCR2_REG(I2S3_BASE_PTR) +#define I2S3_TCR3 I2S_TCR3_REG(I2S3_BASE_PTR) +#define I2S3_TCR4 I2S_TCR4_REG(I2S3_BASE_PTR) +#define I2S3_TCR5 I2S_TCR5_REG(I2S3_BASE_PTR) +#define I2S3_TDR0 I2S_TDR_REG(I2S3_BASE_PTR,0) +#define I2S3_TFR0 I2S_TFR_REG(I2S3_BASE_PTR,0) +#define I2S3_TMR I2S_TMR_REG(I2S3_BASE_PTR) +#define I2S3_RCSR I2S_RCSR_REG(I2S3_BASE_PTR) +#define I2S3_RCR1 I2S_RCR1_REG(I2S3_BASE_PTR) +#define I2S3_RCR2 I2S_RCR2_REG(I2S3_BASE_PTR) +#define I2S3_RCR3 I2S_RCR3_REG(I2S3_BASE_PTR) +#define I2S3_RCR4 I2S_RCR4_REG(I2S3_BASE_PTR) +#define I2S3_RCR5 I2S_RCR5_REG(I2S3_BASE_PTR) +#define I2S3_RDR0 I2S_RDR_REG(I2S3_BASE_PTR,0) +#define I2S3_RFR0 I2S_RFR_REG(I2S3_BASE_PTR,0) +#define I2S3_RMR I2S_RMR_REG(I2S3_BASE_PTR) + +/* I2S - Register array accessors */ +#define I2S1_TDR(index) I2S_TDR_REG(I2S1_BASE_PTR,index) +#define I2S2_TDR(index) I2S_TDR_REG(I2S2_BASE_PTR,index) +#define I2S3_TDR(index) I2S_TDR_REG(I2S3_BASE_PTR,index) +#define I2S1_TFR(index) I2S_TFR_REG(I2S1_BASE_PTR,index) +#define I2S2_TFR(index) I2S_TFR_REG(I2S2_BASE_PTR,index) +#define I2S3_TFR(index) I2S_TFR_REG(I2S3_BASE_PTR,index) +#define I2S1_RDR(index) I2S_RDR_REG(I2S1_BASE_PTR,index) +#define I2S2_RDR(index) I2S_RDR_REG(I2S2_BASE_PTR,index) +#define I2S3_RDR(index) I2S_RDR_REG(I2S3_BASE_PTR,index) +#define I2S1_RFR(index) I2S_RFR_REG(I2S1_BASE_PTR,index) +#define I2S2_RFR(index) I2S_RFR_REG(I2S2_BASE_PTR,index) +#define I2S3_RFR(index) I2S_RFR_REG(I2S3_BASE_PTR,index) + +/*! + * @} + */ /* end of group I2S_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group I2S_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[20]; + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO08; /**< SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register, offset: 0x14 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO09; /**< SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register, offset: 0x18 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO10; /**< SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register, offset: 0x1C */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO11; /**< SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register, offset: 0x20 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO12; /**< SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register, offset: 0x24 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO13; /**< SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register, offset: 0x28 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO14; /**< SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register, offset: 0x2C */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO15; /**< SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register, offset: 0x30 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA00; /**< SW_MUX_CTL_PAD_EPDC_DATA00 SW MUX Control Register, offset: 0x34 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA01; /**< SW_MUX_CTL_PAD_EPDC_DATA01 SW MUX Control Register, offset: 0x38 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA02; /**< SW_MUX_CTL_PAD_EPDC_DATA02 SW MUX Control Register, offset: 0x3C */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA03; /**< SW_MUX_CTL_PAD_EPDC_DATA03 SW MUX Control Register, offset: 0x40 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA04; /**< SW_MUX_CTL_PAD_EPDC_DATA04 SW MUX Control Register, offset: 0x44 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA05; /**< SW_MUX_CTL_PAD_EPDC_DATA05 SW MUX Control Register, offset: 0x48 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA06; /**< SW_MUX_CTL_PAD_EPDC_DATA06 SW MUX Control Register, offset: 0x4C */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA07; /**< SW_MUX_CTL_PAD_EPDC_DATA07 SW MUX Control Register, offset: 0x50 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA08; /**< SW_MUX_CTL_PAD_EPDC_DATA08 SW MUX Control Register, offset: 0x54 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA09; /**< SW_MUX_CTL_PAD_EPDC_DATA09 SW MUX Control Register, offset: 0x58 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA10; /**< SW_MUX_CTL_PAD_EPDC_DATA10 SW MUX Control Register, offset: 0x5C */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA11; /**< SW_MUX_CTL_PAD_EPDC_DATA11 SW MUX Control Register, offset: 0x60 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA12; /**< SW_MUX_CTL_PAD_EPDC_DATA12 SW MUX Control Register, offset: 0x64 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA13; /**< SW_MUX_CTL_PAD_EPDC_DATA13 SW MUX Control Register, offset: 0x68 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA14; /**< SW_MUX_CTL_PAD_EPDC_DATA14 SW MUX Control Register, offset: 0x6C */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_DATA15; /**< SW_MUX_CTL_PAD_EPDC_DATA15 SW MUX Control Register, offset: 0x70 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDCLK; /**< SW_MUX_CTL_PAD_EPDC_SDCLK SW MUX Control Register, offset: 0x74 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDLE; /**< SW_MUX_CTL_PAD_EPDC_SDLE SW MUX Control Register, offset: 0x78 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDOE; /**< SW_MUX_CTL_PAD_EPDC_SDOE SW MUX Control Register, offset: 0x7C */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDSHR; /**< SW_MUX_CTL_PAD_EPDC_SDSHR SW MUX Control Register, offset: 0x80 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDCE0; /**< SW_MUX_CTL_PAD_EPDC_SDCE0 SW MUX Control Register, offset: 0x84 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDCE1; /**< SW_MUX_CTL_PAD_EPDC_SDCE1 SW MUX Control Register, offset: 0x88 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDCE2; /**< SW_MUX_CTL_PAD_EPDC_SDCE2 SW MUX Control Register, offset: 0x8C */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_SDCE3; /**< SW_MUX_CTL_PAD_EPDC_SDCE3 SW MUX Control Register, offset: 0x90 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_GDCLK; /**< SW_MUX_CTL_PAD_EPDC_GDCLK SW MUX Control Register, offset: 0x94 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_GDOE; /**< SW_MUX_CTL_PAD_EPDC_GDOE SW MUX Control Register, offset: 0x98 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_GDRL; /**< SW_MUX_CTL_PAD_EPDC_GDRL SW MUX Control Register, offset: 0x9C */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_GDSP; /**< SW_MUX_CTL_PAD_EPDC_GDSP SW MUX Control Register, offset: 0xA0 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_BDR0; /**< SW_MUX_CTL_PAD_EPDC_BDR0 SW MUX Control Register, offset: 0xA4 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_BDR1; /**< SW_MUX_CTL_PAD_EPDC_BDR1 SW MUX Control Register, offset: 0xA8 */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_PWR_COM; /**< SW_MUX_CTL_PAD_EPDC_PWR_COM SW MUX Control Register, offset: 0xAC */ + __IO uint32_t SW_MUX_CTL_PAD_EPDC_PWR_STAT; /**< SW_MUX_CTL_PAD_EPDC_PWR_STAT SW MUX Control Register, offset: 0xB0 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_CLK; /**< SW_MUX_CTL_PAD_LCD_CLK SW MUX Control Register, offset: 0xB4 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_ENABLE; /**< SW_MUX_CTL_PAD_LCD_ENABLE SW MUX Control Register, offset: 0xB8 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_HSYNC; /**< SW_MUX_CTL_PAD_LCD_HSYNC SW MUX Control Register, offset: 0xBC */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_VSYNC; /**< SW_MUX_CTL_PAD_LCD_VSYNC SW MUX Control Register, offset: 0xC0 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_RESET; /**< SW_MUX_CTL_PAD_LCD_RESET SW MUX Control Register, offset: 0xC4 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA00; /**< SW_MUX_CTL_PAD_LCD_DATA00 SW MUX Control Register, offset: 0xC8 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA01; /**< SW_MUX_CTL_PAD_LCD_DATA01 SW MUX Control Register, offset: 0xCC */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA02; /**< SW_MUX_CTL_PAD_LCD_DATA02 SW MUX Control Register, offset: 0xD0 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA03; /**< SW_MUX_CTL_PAD_LCD_DATA03 SW MUX Control Register, offset: 0xD4 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA04; /**< SW_MUX_CTL_PAD_LCD_DATA04 SW MUX Control Register, offset: 0xD8 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA05; /**< SW_MUX_CTL_PAD_LCD_DATA05 SW MUX Control Register, offset: 0xDC */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA06; /**< SW_MUX_CTL_PAD_LCD_DATA06 SW MUX Control Register, offset: 0xE0 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA07; /**< SW_MUX_CTL_PAD_LCD_DATA07 SW MUX Control Register, offset: 0xE4 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA08; /**< SW_MUX_CTL_PAD_LCD_DATA08 SW MUX Control Register, offset: 0xE8 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA09; /**< SW_MUX_CTL_PAD_LCD_DATA09 SW MUX Control Register, offset: 0xEC */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA10; /**< SW_MUX_CTL_PAD_LCD_DATA10 SW MUX Control Register, offset: 0xF0 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA11; /**< SW_MUX_CTL_PAD_LCD_DATA11 SW MUX Control Register, offset: 0xF4 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA12; /**< SW_MUX_CTL_PAD_LCD_DATA12 SW MUX Control Register, offset: 0xF8 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA13; /**< SW_MUX_CTL_PAD_LCD_DATA13 SW MUX Control Register, offset: 0xFC */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA14; /**< SW_MUX_CTL_PAD_LCD_DATA14 SW MUX Control Register, offset: 0x100 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA15; /**< SW_MUX_CTL_PAD_LCD_DATA15 SW MUX Control Register, offset: 0x104 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA16; /**< SW_MUX_CTL_PAD_LCD_DATA16 SW MUX Control Register, offset: 0x108 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA17; /**< SW_MUX_CTL_PAD_LCD_DATA17 SW MUX Control Register, offset: 0x10C */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA18; /**< SW_MUX_CTL_PAD_LCD_DATA18 SW MUX Control Register, offset: 0x110 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA19; /**< SW_MUX_CTL_PAD_LCD_DATA19 SW MUX Control Register, offset: 0x114 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA20; /**< SW_MUX_CTL_PAD_LCD_DATA20 SW MUX Control Register, offset: 0x118 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA21; /**< SW_MUX_CTL_PAD_LCD_DATA21 SW MUX Control Register, offset: 0x11C */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA22; /**< SW_MUX_CTL_PAD_LCD_DATA22 SW MUX Control Register, offset: 0x120 */ + __IO uint32_t SW_MUX_CTL_PAD_LCD_DATA23; /**< SW_MUX_CTL_PAD_LCD_DATA23 SW MUX Control Register, offset: 0x124 */ + __IO uint32_t SW_MUX_CTL_PAD_UART1_RX_DATA; /**< SW_MUX_CTL_PAD_UART1_RX_DATA SW MUX Control Register, offset: 0x128 */ + __IO uint32_t SW_MUX_CTL_PAD_UART1_TX_DATA; /**< SW_MUX_CTL_PAD_UART1_TX_DATA SW MUX Control Register, offset: 0x12C */ + __IO uint32_t SW_MUX_CTL_PAD_UART2_RX_DATA; /**< SW_MUX_CTL_PAD_UART2_RX_DATA SW MUX Control Register, offset: 0x130 */ + __IO uint32_t SW_MUX_CTL_PAD_UART2_TX_DATA; /**< SW_MUX_CTL_PAD_UART2_TX_DATA SW MUX Control Register, offset: 0x134 */ + __IO uint32_t SW_MUX_CTL_PAD_UART3_RX_DATA; /**< SW_MUX_CTL_PAD_UART3_RX_DATA SW MUX Control Register, offset: 0x138 */ + __IO uint32_t SW_MUX_CTL_PAD_UART3_TX_DATA; /**< SW_MUX_CTL_PAD_UART3_TX_DATA SW MUX Control Register, offset: 0x13C */ + __IO uint32_t SW_MUX_CTL_PAD_UART3_RTS_B; /**< SW_MUX_CTL_PAD_UART3_RTS_B SW MUX Control Register, offset: 0x140 */ + __IO uint32_t SW_MUX_CTL_PAD_UART3_CTS_B; /**< SW_MUX_CTL_PAD_UART3_CTS_B SW MUX Control Register, offset: 0x144 */ + __IO uint32_t SW_MUX_CTL_PAD_I2C1_SCL; /**< SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register, offset: 0x148 */ + __IO uint32_t SW_MUX_CTL_PAD_I2C1_SDA; /**< SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register, offset: 0x14C */ + __IO uint32_t SW_MUX_CTL_PAD_I2C2_SCL; /**< SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register, offset: 0x150 */ + __IO uint32_t SW_MUX_CTL_PAD_I2C2_SDA; /**< SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register, offset: 0x154 */ + __IO uint32_t SW_MUX_CTL_PAD_I2C3_SCL; /**< SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register, offset: 0x158 */ + __IO uint32_t SW_MUX_CTL_PAD_I2C3_SDA; /**< SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register, offset: 0x15C */ + __IO uint32_t SW_MUX_CTL_PAD_I2C4_SCL; /**< SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register, offset: 0x160 */ + __IO uint32_t SW_MUX_CTL_PAD_I2C4_SDA; /**< SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register, offset: 0x164 */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI1_SCLK; /**< SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control Register, offset: 0x168 */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI1_MOSI; /**< SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control Register, offset: 0x16C */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI1_MISO; /**< SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control Register, offset: 0x170 */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI1_SS0; /**< SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control Register, offset: 0x174 */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI2_SCLK; /**< SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control Register, offset: 0x178 */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI2_MOSI; /**< SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control Register, offset: 0x17C */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI2_MISO; /**< SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control Register, offset: 0x180 */ + __IO uint32_t SW_MUX_CTL_PAD_ECSPI2_SS0; /**< SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control Register, offset: 0x184 */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_CD_B; /**< SW_MUX_CTL_PAD_SD1_CD_B SW MUX Control Register, offset: 0x188 */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_WP; /**< SW_MUX_CTL_PAD_SD1_WP SW MUX Control Register, offset: 0x18C */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_RESET_B; /**< SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control Register, offset: 0x190 */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_CLK; /**< SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register, offset: 0x194 */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_CMD; /**< SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register, offset: 0x198 */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA0; /**< SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register, offset: 0x19C */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA1; /**< SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register, offset: 0x1A0 */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA2; /**< SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register, offset: 0x1A4 */ + __IO uint32_t SW_MUX_CTL_PAD_SD1_DATA3; /**< SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register, offset: 0x1A8 */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_CD_B; /**< SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register, offset: 0x1AC */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_WP; /**< SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register, offset: 0x1B0 */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_RESET_B; /**< SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control Register, offset: 0x1B4 */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_CLK; /**< SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register, offset: 0x1B8 */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_CMD; /**< SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register, offset: 0x1BC */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA0; /**< SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register, offset: 0x1C0 */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA1; /**< SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register, offset: 0x1C4 */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA2; /**< SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register, offset: 0x1C8 */ + __IO uint32_t SW_MUX_CTL_PAD_SD2_DATA3; /**< SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register, offset: 0x1CC */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_CLK; /**< SW_MUX_CTL_PAD_SD3_CLK SW MUX Control Register, offset: 0x1D0 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_CMD; /**< SW_MUX_CTL_PAD_SD3_CMD SW MUX Control Register, offset: 0x1D4 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA0; /**< SW_MUX_CTL_PAD_SD3_DATA0 SW MUX Control Register, offset: 0x1D8 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA1; /**< SW_MUX_CTL_PAD_SD3_DATA1 SW MUX Control Register, offset: 0x1DC */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA2; /**< SW_MUX_CTL_PAD_SD3_DATA2 SW MUX Control Register, offset: 0x1E0 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA3; /**< SW_MUX_CTL_PAD_SD3_DATA3 SW MUX Control Register, offset: 0x1E4 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA4; /**< SW_MUX_CTL_PAD_SD3_DATA4 SW MUX Control Register, offset: 0x1E8 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA5; /**< SW_MUX_CTL_PAD_SD3_DATA5 SW MUX Control Register, offset: 0x1EC */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA6; /**< SW_MUX_CTL_PAD_SD3_DATA6 SW MUX Control Register, offset: 0x1F0 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_DATA7; /**< SW_MUX_CTL_PAD_SD3_DATA7 SW MUX Control Register, offset: 0x1F4 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_STROBE; /**< SW_MUX_CTL_PAD_SD3_STROBE SW MUX Control Register, offset: 0x1F8 */ + __IO uint32_t SW_MUX_CTL_PAD_SD3_RESET_B; /**< SW_MUX_CTL_PAD_SD3_RESET_B SW MUX Control Register, offset: 0x1FC */ + __IO uint32_t SW_MUX_CTL_PAD_SAI1_RX_DATA; /**< SW_MUX_CTL_PAD_SAI1_RX_DATA SW MUX Control Register, offset: 0x200 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI1_TX_BCLK; /**< SW_MUX_CTL_PAD_SAI1_TX_BCLK SW MUX Control Register, offset: 0x204 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI1_TX_SYNC; /**< SW_MUX_CTL_PAD_SAI1_TX_SYNC SW MUX Control Register, offset: 0x208 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI1_TX_DATA; /**< SW_MUX_CTL_PAD_SAI1_TX_DATA SW MUX Control Register, offset: 0x20C */ + __IO uint32_t SW_MUX_CTL_PAD_SAI1_RX_SYNC; /**< SW_MUX_CTL_PAD_SAI1_RX_SYNC SW MUX Control Register, offset: 0x210 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI1_RX_BCLK; /**< SW_MUX_CTL_PAD_SAI1_RX_BCLK SW MUX Control Register, offset: 0x214 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI1_MCLK; /**< SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register, offset: 0x218 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI2_TX_SYNC; /**< SW_MUX_CTL_PAD_SAI2_TX_SYNC SW MUX Control Register, offset: 0x21C */ + __IO uint32_t SW_MUX_CTL_PAD_SAI2_TX_BCLK; /**< SW_MUX_CTL_PAD_SAI2_TX_BCLK SW MUX Control Register, offset: 0x220 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI2_RX_DATA; /**< SW_MUX_CTL_PAD_SAI2_RX_DATA SW MUX Control Register, offset: 0x224 */ + __IO uint32_t SW_MUX_CTL_PAD_SAI2_TX_DATA; /**< SW_MUX_CTL_PAD_SAI2_TX_DATA SW MUX Control Register, offset: 0x228 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD0; /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD0 SW MUX Control Register, offset: 0x22C */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD1; /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD1 SW MUX Control Register, offset: 0x230 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD2; /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD2 SW MUX Control Register, offset: 0x234 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RD3; /**< SW_MUX_CTL_PAD_ENET1_RGMII_RD3 SW MUX Control Register, offset: 0x238 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL; /**< SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL SW MUX Control Register, offset: 0x23C */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_RXC; /**< SW_MUX_CTL_PAD_ENET1_RGMII_RXC SW MUX Control Register, offset: 0x240 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD0; /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD0 SW MUX Control Register, offset: 0x244 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD1; /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD1 SW MUX Control Register, offset: 0x248 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD2; /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD2 SW MUX Control Register, offset: 0x24C */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TD3; /**< SW_MUX_CTL_PAD_ENET1_RGMII_TD3 SW MUX Control Register, offset: 0x250 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL; /**< SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL SW MUX Control Register, offset: 0x254 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RGMII_TXC; /**< SW_MUX_CTL_PAD_ENET1_RGMII_TXC SW MUX Control Register, offset: 0x258 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_TX_CLK; /**< SW_MUX_CTL_PAD_ENET1_TX_CLK SW MUX Control Register, offset: 0x25C */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_RX_CLK; /**< SW_MUX_CTL_PAD_ENET1_RX_CLK SW MUX Control Register, offset: 0x260 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_CRS; /**< SW_MUX_CTL_PAD_ENET1_CRS SW MUX Control Register, offset: 0x264 */ + __IO uint32_t SW_MUX_CTL_PAD_ENET1_COL; /**< SW_MUX_CTL_PAD_ENET1_COL SW MUX Control Register, offset: 0x268 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO08; /**< SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register, offset: 0x26C */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO09; /**< SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register, offset: 0x270 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO10; /**< SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control Register, offset: 0x274 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO11; /**< SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control Register, offset: 0x278 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO12; /**< SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control Register, offset: 0x27C */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO13; /**< SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control Register, offset: 0x280 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO14; /**< SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control Register, offset: 0x284 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO15; /**< SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control Register, offset: 0x288 */ + __IO uint32_t SW_PAD_CTL_PAD_JTAG_MOD; /**< SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register, offset: 0x28C */ + __IO uint32_t SW_PAD_CTL_PAD_JTAG_TCK; /**< SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register, offset: 0x290 */ + __IO uint32_t SW_PAD_CTL_PAD_JTAG_TDI; /**< SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register, offset: 0x294 */ + __IO uint32_t SW_PAD_CTL_PAD_JTAG_TDO; /**< SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register, offset: 0x298 */ + __IO uint32_t SW_PAD_CTL_PAD_JTAG_TMS; /**< SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register, offset: 0x29C */ + __IO uint32_t SW_PAD_CTL_PAD_JTAG_TRST_B; /**< SW_PAD_CTL_PAD_JTAG_TRST_B SW PAD Control Register, offset: 0x2A0 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA00; /**< SW_PAD_CTL_PAD_EPDC_DATA00 SW PAD Control Register, offset: 0x2A4 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA01; /**< SW_PAD_CTL_PAD_EPDC_DATA01 SW PAD Control Register, offset: 0x2A8 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA02; /**< SW_PAD_CTL_PAD_EPDC_DATA02 SW PAD Control Register, offset: 0x2AC */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA03; /**< SW_PAD_CTL_PAD_EPDC_DATA03 SW PAD Control Register, offset: 0x2B0 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA04; /**< SW_PAD_CTL_PAD_EPDC_DATA04 SW PAD Control Register, offset: 0x2B4 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA05; /**< SW_PAD_CTL_PAD_EPDC_DATA05 SW PAD Control Register, offset: 0x2B8 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA06; /**< SW_PAD_CTL_PAD_EPDC_DATA06 SW PAD Control Register, offset: 0x2BC */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA07; /**< SW_PAD_CTL_PAD_EPDC_DATA07 SW PAD Control Register, offset: 0x2C0 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA08; /**< SW_PAD_CTL_PAD_EPDC_DATA08 SW PAD Control Register, offset: 0x2C4 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA09; /**< SW_PAD_CTL_PAD_EPDC_DATA09 SW PAD Control Register, offset: 0x2C8 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA10; /**< SW_PAD_CTL_PAD_EPDC_DATA10 SW PAD Control Register, offset: 0x2CC */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA11; /**< SW_PAD_CTL_PAD_EPDC_DATA11 SW PAD Control Register, offset: 0x2D0 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA12; /**< SW_PAD_CTL_PAD_EPDC_DATA12 SW PAD Control Register, offset: 0x2D4 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA13; /**< SW_PAD_CTL_PAD_EPDC_DATA13 SW PAD Control Register, offset: 0x2D8 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA14; /**< SW_PAD_CTL_PAD_EPDC_DATA14 SW PAD Control Register, offset: 0x2DC */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_DATA15; /**< SW_PAD_CTL_PAD_EPDC_DATA15 SW PAD Control Register, offset: 0x2E0 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDCLK; /**< SW_PAD_CTL_PAD_EPDC_SDCLK SW PAD Control Register, offset: 0x2E4 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDLE; /**< SW_PAD_CTL_PAD_EPDC_SDLE SW PAD Control Register, offset: 0x2E8 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDOE; /**< SW_PAD_CTL_PAD_EPDC_SDOE SW PAD Control Register, offset: 0x2EC */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDSHR; /**< SW_PAD_CTL_PAD_EPDC_SDSHR SW PAD Control Register, offset: 0x2F0 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDCE0; /**< SW_PAD_CTL_PAD_EPDC_SDCE0 SW PAD Control Register, offset: 0x2F4 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDCE1; /**< SW_PAD_CTL_PAD_EPDC_SDCE1 SW PAD Control Register, offset: 0x2F8 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDCE2; /**< SW_PAD_CTL_PAD_EPDC_SDCE2 SW PAD Control Register, offset: 0x2FC */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_SDCE3; /**< SW_PAD_CTL_PAD_EPDC_SDCE3 SW PAD Control Register, offset: 0x300 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_GDCLK; /**< SW_PAD_CTL_PAD_EPDC_GDCLK SW PAD Control Register, offset: 0x304 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_GDOE; /**< SW_PAD_CTL_PAD_EPDC_GDOE SW PAD Control Register, offset: 0x308 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_GDRL; /**< SW_PAD_CTL_PAD_EPDC_GDRL SW PAD Control Register, offset: 0x30C */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_GDSP; /**< SW_PAD_CTL_PAD_EPDC_GDSP SW PAD Control Register, offset: 0x310 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_BDR0; /**< SW_PAD_CTL_PAD_EPDC_BDR0 SW PAD Control Register, offset: 0x314 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_BDR1; /**< SW_PAD_CTL_PAD_EPDC_BDR1 SW PAD Control Register, offset: 0x318 */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_PWR_COM; /**< SW_PAD_CTL_PAD_EPDC_PWR_COM SW PAD Control Register, offset: 0x31C */ + __IO uint32_t SW_PAD_CTL_PAD_EPDC_PWR_STAT; /**< SW_PAD_CTL_PAD_EPDC_PWR_STAT SW PAD Control Register, offset: 0x320 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_CLK; /**< SW_PAD_CTL_PAD_LCD_CLK SW PAD Control Register, offset: 0x324 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_ENABLE; /**< SW_PAD_CTL_PAD_LCD_ENABLE SW PAD Control Register, offset: 0x328 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_HSYNC; /**< SW_PAD_CTL_PAD_LCD_HSYNC SW PAD Control Register, offset: 0x32C */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_VSYNC; /**< SW_PAD_CTL_PAD_LCD_VSYNC SW PAD Control Register, offset: 0x330 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_RESET; /**< SW_PAD_CTL_PAD_LCD_RESET SW PAD Control Register, offset: 0x334 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA00; /**< SW_PAD_CTL_PAD_LCD_DATA00 SW PAD Control Register, offset: 0x338 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA01; /**< SW_PAD_CTL_PAD_LCD_DATA01 SW PAD Control Register, offset: 0x33C */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA02; /**< SW_PAD_CTL_PAD_LCD_DATA02 SW PAD Control Register, offset: 0x340 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA03; /**< SW_PAD_CTL_PAD_LCD_DATA03 SW PAD Control Register, offset: 0x344 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA04; /**< SW_PAD_CTL_PAD_LCD_DATA04 SW PAD Control Register, offset: 0x348 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA05; /**< SW_PAD_CTL_PAD_LCD_DATA05 SW PAD Control Register, offset: 0x34C */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA06; /**< SW_PAD_CTL_PAD_LCD_DATA06 SW PAD Control Register, offset: 0x350 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA07; /**< SW_PAD_CTL_PAD_LCD_DATA07 SW PAD Control Register, offset: 0x354 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA08; /**< SW_PAD_CTL_PAD_LCD_DATA08 SW PAD Control Register, offset: 0x358 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA09; /**< SW_PAD_CTL_PAD_LCD_DATA09 SW PAD Control Register, offset: 0x35C */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA10; /**< SW_PAD_CTL_PAD_LCD_DATA10 SW PAD Control Register, offset: 0x360 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA11; /**< SW_PAD_CTL_PAD_LCD_DATA11 SW PAD Control Register, offset: 0x364 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA12; /**< SW_PAD_CTL_PAD_LCD_DATA12 SW PAD Control Register, offset: 0x368 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA13; /**< SW_PAD_CTL_PAD_LCD_DATA13 SW PAD Control Register, offset: 0x36C */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA14; /**< SW_PAD_CTL_PAD_LCD_DATA14 SW PAD Control Register, offset: 0x370 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA15; /**< SW_PAD_CTL_PAD_LCD_DATA15 SW PAD Control Register, offset: 0x374 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA16; /**< SW_PAD_CTL_PAD_LCD_DATA16 SW PAD Control Register, offset: 0x378 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA17; /**< SW_PAD_CTL_PAD_LCD_DATA17 SW PAD Control Register, offset: 0x37C */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA18; /**< SW_PAD_CTL_PAD_LCD_DATA18 SW PAD Control Register, offset: 0x380 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA19; /**< SW_PAD_CTL_PAD_LCD_DATA19 SW PAD Control Register, offset: 0x384 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA20; /**< SW_PAD_CTL_PAD_LCD_DATA20 SW PAD Control Register, offset: 0x388 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA21; /**< SW_PAD_CTL_PAD_LCD_DATA21 SW PAD Control Register, offset: 0x38C */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA22; /**< SW_PAD_CTL_PAD_LCD_DATA22 SW PAD Control Register, offset: 0x390 */ + __IO uint32_t SW_PAD_CTL_PAD_LCD_DATA23; /**< SW_PAD_CTL_PAD_LCD_DATA23 SW PAD Control Register, offset: 0x394 */ + __IO uint32_t SW_PAD_CTL_PAD_UART1_RX_DATA; /**< SW_PAD_CTL_PAD_UART1_RX_DATA SW PAD Control Register, offset: 0x398 */ + __IO uint32_t SW_PAD_CTL_PAD_UART1_TX_DATA; /**< SW_PAD_CTL_PAD_UART1_TX_DATA SW PAD Control Register, offset: 0x39C */ + __IO uint32_t SW_PAD_CTL_PAD_UART2_RX_DATA; /**< SW_PAD_CTL_PAD_UART2_RX_DATA SW PAD Control Register, offset: 0x3A0 */ + __IO uint32_t SW_PAD_CTL_PAD_UART2_TX_DATA; /**< SW_PAD_CTL_PAD_UART2_TX_DATA SW PAD Control Register, offset: 0x3A4 */ + __IO uint32_t SW_PAD_CTL_PAD_UART3_RX_DATA; /**< SW_PAD_CTL_PAD_UART3_RX_DATA SW PAD Control Register, offset: 0x3A8 */ + __IO uint32_t SW_PAD_CTL_PAD_UART3_TX_DATA; /**< SW_PAD_CTL_PAD_UART3_TX_DATA SW PAD Control Register, offset: 0x3AC */ + __IO uint32_t SW_PAD_CTL_PAD_UART3_RTS; /**< SW_PAD_CTL_PAD_UART3_RTS SW PAD Control Register, offset: 0x3B0 */ + __IO uint32_t SW_PAD_CTL_PAD_UART3_CTS; /**< SW_PAD_CTL_PAD_UART3_CTS SW PAD Control Register, offset: 0x3B4 */ + __IO uint32_t SW_PAD_CTL_PAD_I2C1_SCL; /**< SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register, offset: 0x3B8 */ + __IO uint32_t SW_PAD_CTL_PAD_I2C1_SDA; /**< SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register, offset: 0x3BC */ + __IO uint32_t SW_PAD_CTL_PAD_I2C2_SCL; /**< SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register, offset: 0x3C0 */ + __IO uint32_t SW_PAD_CTL_PAD_I2C2_SDA; /**< SW_PAD_CTL_PAD_I2C2_SDA SW PAD Control Register, offset: 0x3C4 */ + __IO uint32_t SW_PAD_CTL_PAD_I2C3_SCL; /**< SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register, offset: 0x3C8 */ + __IO uint32_t SW_PAD_CTL_PAD_I2C3_SDA; /**< SW_PAD_CTL_PAD_I2C3_SDA SW PAD Control Register, offset: 0x3CC */ + __IO uint32_t SW_PAD_CTL_PAD_I2C4_SCL; /**< SW_PAD_CTL_PAD_I2C4_SCL SW PAD Control Register, offset: 0x3D0 */ + __IO uint32_t SW_PAD_CTL_PAD_I2C4_SDA; /**< SW_PAD_CTL_PAD_I2C4_SDA SW PAD Control Register, offset: 0x3D4 */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI1_SCLK; /**< SW_PAD_CTL_PAD_ECSPI1_SCLK SW PAD Control Register, offset: 0x3D8 */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI1_MOSI; /**< SW_PAD_CTL_PAD_ECSPI1_MOSI SW PAD Control Register, offset: 0x3DC */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI1_MISO; /**< SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control Register, offset: 0x3E0 */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI1_SS0; /**< SW_PAD_CTL_PAD_ECSPI1_SS0 SW PAD Control Register, offset: 0x3E4 */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI2_SCLK; /**< SW_PAD_CTL_PAD_ECSPI2_SCLK SW PAD Control Register, offset: 0x3E8 */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI2_MOSI; /**< SW_PAD_CTL_PAD_ECSPI2_MOSI SW PAD Control Register, offset: 0x3EC */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI2_MISO; /**< SW_PAD_CTL_PAD_ECSPI2_MISO SW PAD Control Register, offset: 0x3F0 */ + __IO uint32_t SW_PAD_CTL_PAD_ECSPI2_SS0; /**< SW_PAD_CTL_PAD_ECSPI2_SS0 SW PAD Control Register, offset: 0x3F4 */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_CD_B; /**< SW_PAD_CTL_PAD_SD1_CD_B SW PAD Control Register, offset: 0x3F8 */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_WP; /**< SW_PAD_CTL_PAD_SD1_WP SW PAD Control Register, offset: 0x3FC */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_RESET_B; /**< SW_PAD_CTL_PAD_SD1_RESET_B SW PAD Control Register, offset: 0x400 */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_CLK; /**< SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register, offset: 0x404 */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_CMD; /**< SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register, offset: 0x408 */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA0; /**< SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control Register, offset: 0x40C */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA1; /**< SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control Register, offset: 0x410 */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA2; /**< SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control Register, offset: 0x414 */ + __IO uint32_t SW_PAD_CTL_PAD_SD1_DATA3; /**< SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control Register, offset: 0x418 */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_CD_B; /**< SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control Register, offset: 0x41C */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_WP; /**< SW_PAD_CTL_PAD_SD2_WP SW PAD Control Register, offset: 0x420 */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_RESET_B; /**< SW_PAD_CTL_PAD_SD2_RESET_B SW PAD Control Register, offset: 0x424 */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_CLK; /**< SW_PAD_CTL_PAD_SD2_CLK SW PAD Control Register, offset: 0x428 */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_CMD; /**< SW_PAD_CTL_PAD_SD2_CMD SW PAD Control Register, offset: 0x42C */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA0; /**< SW_PAD_CTL_PAD_SD2_DATA0 SW PAD Control Register, offset: 0x430 */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA1; /**< SW_PAD_CTL_PAD_SD2_DATA1 SW PAD Control Register, offset: 0x434 */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA2; /**< SW_PAD_CTL_PAD_SD2_DATA2 SW PAD Control Register, offset: 0x438 */ + __IO uint32_t SW_PAD_CTL_PAD_SD2_DATA3; /**< SW_PAD_CTL_PAD_SD2_DATA3 SW PAD Control Register, offset: 0x43C */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_CLK; /**< SW_PAD_CTL_PAD_SD3_CLK SW PAD Control Register, offset: 0x440 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_CMD; /**< SW_PAD_CTL_PAD_SD3_CMD SW PAD Control Register, offset: 0x444 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA0; /**< SW_PAD_CTL_PAD_SD3_DATA0 SW PAD Control Register, offset: 0x448 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA1; /**< SW_PAD_CTL_PAD_SD3_DATA1 SW PAD Control Register, offset: 0x44C */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA2; /**< SW_PAD_CTL_PAD_SD3_DATA2 SW PAD Control Register, offset: 0x450 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA3; /**< SW_PAD_CTL_PAD_SD3_DATA3 SW PAD Control Register, offset: 0x454 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA4; /**< SW_PAD_CTL_PAD_SD3_DATA4 SW PAD Control Register, offset: 0x458 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA5; /**< SW_PAD_CTL_PAD_SD3_DATA5 SW PAD Control Register, offset: 0x45C */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA6; /**< SW_PAD_CTL_PAD_SD3_DATA6 SW PAD Control Register, offset: 0x460 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_DATA7; /**< SW_PAD_CTL_PAD_SD3_DATA7 SW PAD Control Register, offset: 0x464 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_STROBE; /**< SW_PAD_CTL_PAD_SD3_STROBE SW PAD Control Register, offset: 0x468 */ + __IO uint32_t SW_PAD_CTL_PAD_SD3_RESET_B; /**< SW_PAD_CTL_PAD_SD3_RESET_B SW PAD Control Register, offset: 0x46C */ + __IO uint32_t SW_PAD_CTL_PAD_SAI1_RX_DATA; /**< SW_PAD_CTL_PAD_SAI1_RX_DATA SW PAD Control Register, offset: 0x470 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI1_TX_BCLK; /**< SW_PAD_CTL_PAD_SAI1_TX_BCLK SW PAD Control Register, offset: 0x474 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI1_TX_SYNC; /**< SW_PAD_CTL_PAD_SAI1_TX_SYNC SW PAD Control Register, offset: 0x478 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI1_TX_DATA; /**< SW_PAD_CTL_PAD_SAI1_TX_DATA SW PAD Control Register, offset: 0x47C */ + __IO uint32_t SW_PAD_CTL_PAD_SAI1_RX_SYNC; /**< SW_PAD_CTL_PAD_SAI1_RX_SYNC SW PAD Control Register, offset: 0x480 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI1_RX_BCLK; /**< SW_PAD_CTL_PAD_SAI1_RX_BCLK SW PAD Control Register, offset: 0x484 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI1_MCLK; /**< SW_PAD_CTL_PAD_SAI1_MCLK SW PAD Control Register, offset: 0x488 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI2_TX_SYNC; /**< SW_PAD_CTL_PAD_SAI2_TX_SYNC SW PAD Control Register, offset: 0x48C */ + __IO uint32_t SW_PAD_CTL_PAD_SAI2_TX_BCLK; /**< SW_PAD_CTL_PAD_SAI2_TX_BCLK SW PAD Control Register, offset: 0x490 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI2_RX_DATA; /**< SW_PAD_CTL_PAD_SAI2_RX_DATA SW PAD Control Register, offset: 0x494 */ + __IO uint32_t SW_PAD_CTL_PAD_SAI2_TX_DATA; /**< SW_PAD_CTL_PAD_SAI2_TX_DATA SW PAD Control Register, offset: 0x498 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD0; /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD0 SW PAD Control Register, offset: 0x49C */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD1; /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD1 SW PAD Control Register, offset: 0x4A0 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD2; /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD2 SW PAD Control Register, offset: 0x4A4 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RD3; /**< SW_PAD_CTL_PAD_ENET1_RGMII_RD3 SW PAD Control Register, offset: 0x4A8 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL; /**< SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL SW PAD Control Register, offset: 0x4AC */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_RXC; /**< SW_PAD_CTL_PAD_ENET1_RGMII_RXC SW PAD Control Register, offset: 0x4B0 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD0; /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD0 SW PAD Control Register, offset: 0x4B4 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD1; /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD1 SW PAD Control Register, offset: 0x4B8 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD2; /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD2 SW PAD Control Register, offset: 0x4BC */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TD3; /**< SW_PAD_CTL_PAD_ENET1_RGMII_TD3 SW PAD Control Register, offset: 0x4C0 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL; /**< SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL SW PAD Control Register, offset: 0x4C4 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RGMII_TXC; /**< SW_PAD_CTL_PAD_ENET1_RGMII_TXC SW PAD Control Register, offset: 0x4C8 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_TX_CLK; /**< SW_PAD_CTL_PAD_ENET1_TX_CLK SW PAD Control Register, offset: 0x4CC */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_RX_CLK; /**< SW_PAD_CTL_PAD_ENET1_RX_CLK SW PAD Control Register, offset: 0x4D0 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_CRS; /**< SW_PAD_CTL_PAD_ENET1_CRS SW PAD Control Register, offset: 0x4D4 */ + __IO uint32_t SW_PAD_CTL_PAD_ENET1_COL; /**< SW_PAD_CTL_PAD_ENET1_COL SW PAD Control Register, offset: 0x4D8 */ + __IO uint32_t FLEXCAN1_RX_SELECT_INPUT; /**< FLEXCAN1_RX_SELECT_INPUT DAISY Register, offset: 0x4DC */ + __IO uint32_t FLEXCAN2_RX_SELECT_INPUT; /**< FLEXCAN2_RX_SELECT_INPUT DAISY Register, offset: 0x4E0 */ + __IO uint32_t CCM_EXT_CLK_1_SELECT_INPUT; /**< CCM_EXT_CLK_1_SELECT_INPUT DAISY Register, offset: 0x4E4 */ + __IO uint32_t CCM_EXT_CLK_2_SELECT_INPUT; /**< CCM_EXT_CLK_2_SELECT_INPUT DAISY Register, offset: 0x4E8 */ + __IO uint32_t CCM_EXT_CLK_3_SELECT_INPUT; /**< CCM_EXT_CLK_3_SELECT_INPUT DAISY Register, offset: 0x4EC */ + __IO uint32_t CCM_EXT_CLK_4_SELECT_INPUT; /**< CCM_EXT_CLK_4_SELECT_INPUT DAISY Register, offset: 0x4F0 */ + __IO uint32_t CCM_PMIC_READY_SELECT_INPUT; /**< CCM_PMIC_READY_SELECT_INPUT DAISY Register, offset: 0x4F4 */ + __IO uint32_t CSI_DATA2_SELECT_INPUT; /**< CSI_DATA2_SELECT_INPUT DAISY Register, offset: 0x4F8 */ + __IO uint32_t CSI_DATA3_SELECT_INPUT; /**< CSI_DATA3_SELECT_INPUT DAISY Register, offset: 0x4FC */ + __IO uint32_t CSI_DATA4_SELECT_INPUT; /**< CSI_DATA4_SELECT_INPUT DAISY Register, offset: 0x500 */ + __IO uint32_t CSI_DATA5_SELECT_INPUT; /**< CSI_DATA5_SELECT_INPUT DAISY Register, offset: 0x504 */ + __IO uint32_t CSI_DATA6_SELECT_INPUT; /**< CSI_DATA6_SELECT_INPUT DAISY Register, offset: 0x508 */ + __IO uint32_t CSI_DATA7_SELECT_INPUT; /**< CSI_DATA7_SELECT_INPUT DAISY Register, offset: 0x50C */ + __IO uint32_t CSI_DATA8_SELECT_INPUT; /**< CSI_DATA8_SELECT_INPUT DAISY Register, offset: 0x510 */ + __IO uint32_t CSI_DATA9_SELECT_INPUT; /**< CSI_DATA9_SELECT_INPUT DAISY Register, offset: 0x514 */ + __IO uint32_t CSI_HSYNC_SELECT_INPUT; /**< CSI_HSYNC_SELECT_INPUT DAISY Register, offset: 0x518 */ + __IO uint32_t CSI_PIXCLK_SELECT_INPUT; /**< CSI_PIXCLK_SELECT_INPUT DAISY Register, offset: 0x51C */ + __IO uint32_t CSI_VSYNC_SELECT_INPUT; /**< CSI_VSYNC_SELECT_INPUT DAISY Register, offset: 0x520 */ + __IO uint32_t ECSPI1_SCLK_SELECT_INPUT; /**< ECSPI1_SCLK_SELECT_INPUT DAISY Register, offset: 0x524 */ + __IO uint32_t ECSPI1_MISO_SELECT_INPUT; /**< ECSPI1_MISO_SELECT_INPUT DAISY Register, offset: 0x528 */ + __IO uint32_t ECSPI1_MOSI_SELECT_INPUT; /**< ECSPI1_MOSI_SELECT_INPUT DAISY Register, offset: 0x52C */ + __IO uint32_t ECSPI1_SS0_B_SELECT_INPUT; /**< ECSPI1_SS0_B_SELECT_INPUT DAISY Register, offset: 0x530 */ + __IO uint32_t ECSPI2_SCLK_SELECT_INPUT; /**< ECSPI2_SCLK_SELECT_INPUT DAISY Register, offset: 0x534 */ + __IO uint32_t ECSPI2_MISO_SELECT_INPUT; /**< ECSPI2_MISO_SELECT_INPUT DAISY Register, offset: 0x538 */ + __IO uint32_t ECSPI2_MOSI_SELECT_INPUT; /**< ECSPI2_MOSI_SELECT_INPUT DAISY Register, offset: 0x53C */ + __IO uint32_t ECSPI2_SS0_B_SELECT_INPUT; /**< ECSPI2_SS0_B_SELECT_INPUT DAISY Register, offset: 0x540 */ + __IO uint32_t ECSPI3_SCLK_SELECT_INPUT; /**< ECSPI3_SCLK_SELECT_INPUT DAISY Register, offset: 0x544 */ + __IO uint32_t ECSPI3_MISO_SELECT_INPUT; /**< ECSPI3_MISO_SELECT_INPUT DAISY Register, offset: 0x548 */ + __IO uint32_t ECSPI3_MOSI_SELECT_INPUT; /**< ECSPI3_MOSI_SELECT_INPUT DAISY Register, offset: 0x54C */ + __IO uint32_t ECSPI3_SS0_B_SELECT_INPUT; /**< ECSPI3_SS0_B_SELECT_INPUT DAISY Register, offset: 0x550 */ + __IO uint32_t ECSPI4_SCLK_SELECT_INPUT; /**< ECSPI4_SCLK_SELECT_INPUT DAISY Register, offset: 0x554 */ + __IO uint32_t ECSPI4_MISO_SELECT_INPUT; /**< ECSPI4_MISO_SELECT_INPUT DAISY Register, offset: 0x558 */ + __IO uint32_t ECSPI4_MOSI_SELECT_INPUT; /**< ECSPI4_MOSI_SELECT_INPUT DAISY Register, offset: 0x55C */ + __IO uint32_t ECSPI4_SS0_B_SELECT_INPUT; /**< ECSPI4_SS0_B_SELECT_INPUT DAISY Register, offset: 0x560 */ + __IO uint32_t CCM_ENET_REF_CLK1_SELECT_INPUT; /**< CCM_ENET_REF_CLK1_SELECT_INPUT DAISY Register, offset: 0x564 */ + __IO uint32_t ENET1_MDIO_SELECT_INPUT; /**< ENET1_MDIO_SELECT_INPUT DAISY Register, offset: 0x568 */ + __IO uint32_t ENET1_RX_CLK_SELECT_INPUT; /**< ENET1_RX_CLK_SELECT_INPUT DAISY Register, offset: 0x56C */ + __IO uint32_t CCM_ENET_REF_CLK2_SELECT_INPUT; /**< CCM_ENET_REF_CLK2_SELECT_INPUT DAISY Register, offset: 0x570 */ + __IO uint32_t ENET2_MDIO_SELECT_INPUT; /**< ENET2_MDIO_SELECT_INPUT DAISY Register, offset: 0x574 */ + __IO uint32_t ENET2_RX_CLK_SELECT_INPUT; /**< ENET2_RX_CLK_SELECT_INPUT DAISY Register, offset: 0x578 */ + __IO uint32_t EPDC_PWR_IRQ_SELECT_INPUT; /**< EPDC_PWR_IRQ_SELECT_INPUT DAISY Register, offset: 0x57C */ + __IO uint32_t EPDC_PWR_STAT_SELECT_INPUT; /**< EPDC_PWR_STAT_SELECT_INPUT DAISY Register, offset: 0x580 */ + __IO uint32_t FLEXTIMER1_CH0_SELECT_INPUT; /**< FLEXTIMER1_CH0_SELECT_INPUT DAISY Register, offset: 0x584 */ + __IO uint32_t FLEXTIMER1_CH1_SELECT_INPUT; /**< FLEXTIMER1_CH1_SELECT_INPUT DAISY Register, offset: 0x588 */ + __IO uint32_t FLEXTIMER1_CH2_SELECT_INPUT; /**< FLEXTIMER1_CH2_SELECT_INPUT DAISY Register, offset: 0x58C */ + __IO uint32_t FLEXTIMER1_CH3_SELECT_INPUT; /**< FLEXTIMER1_CH3_SELECT_INPUT DAISY Register, offset: 0x590 */ + __IO uint32_t FLEXTIMER1_CH4_SELECT_INPUT; /**< FLEXTIMER1_CH4_SELECT_INPUT DAISY Register, offset: 0x594 */ + __IO uint32_t FLEXTIMER1_CH5_SELECT_INPUT; /**< FLEXTIMER1_CH5_SELECT_INPUT DAISY Register, offset: 0x598 */ + __IO uint32_t FLEXTIMER1_CH6_SELECT_INPUT; /**< FLEXTIMER1_CH6_SELECT_INPUT DAISY Register, offset: 0x59C */ + __IO uint32_t FLEXTIMER1_CH7_SELECT_INPUT; /**< FLEXTIMER1_CH7_SELECT_INPUT DAISY Register, offset: 0x5A0 */ + __IO uint32_t FLEXTIMER1_PHA_SELECT_INPUT; /**< FLEXTIMER1_PHA_SELECT_INPUT DAISY Register, offset: 0x5A4 */ + __IO uint32_t FLEXTIMER1_PHB_SELECT_INPUT; /**< FLEXTIMER1_PHB_SELECT_INPUT DAISY Register, offset: 0x5A8 */ + __IO uint32_t FLEXTIMER2_CH0_SELECT_INPUT; /**< FLEXTIMER2_CH0_SELECT_INPUT DAISY Register, offset: 0x5AC */ + __IO uint32_t FLEXTIMER2_CH1_SELECT_INPUT; /**< FLEXTIMER2_CH1_SELECT_INPUT DAISY Register, offset: 0x5B0 */ + __IO uint32_t FLEXTIMER2_CH2_SELECT_INPUT; /**< FLEXTIMER2_CH2_SELECT_INPUT DAISY Register, offset: 0x5B4 */ + __IO uint32_t FLEXTIMER2_CH3_SELECT_INPUT; /**< FLEXTIMER2_CH3_SELECT_INPUT DAISY Register, offset: 0x5B8 */ + __IO uint32_t FLEXTIMER2_CH4_SELECT_INPUT; /**< FLEXTIMER2_CH4_SELECT_INPUT DAISY Register, offset: 0x5BC */ + __IO uint32_t FLEXTIMER2_CH5_SELECT_INPUT; /**< FLEXTIMER2_CH5_SELECT_INPUT DAISY Register, offset: 0x5C0 */ + __IO uint32_t FLEXTIMER2_CH6_SELECT_INPUT; /**< FLEXTIMER2_CH6_SELECT_INPUT DAISY Register, offset: 0x5C4 */ + __IO uint32_t FLEXTIMER2_CH7_SELECT_INPUT; /**< FLEXTIMER2_CH7_SELECT_INPUT DAISY Register, offset: 0x5C8 */ + __IO uint32_t FLEXTIMER2_PHA_SELECT_INPUT; /**< FLEXTIMER2_PHA_SELECT_INPUT DAISY Register, offset: 0x5CC */ + __IO uint32_t FLEXTIMER2_PHB_SELECT_INPUT; /**< FLEXTIMER2_PHB_SELECT_INPUT DAISY Register, offset: 0x5D0 */ + __IO uint32_t I2C1_SCL_SELECT_INPUT; /**< I2C1_SCL_SELECT_INPUT DAISY Register, offset: 0x5D4 */ + __IO uint32_t I2C1_SDA_SELECT_INPUT; /**< I2C1_SDA_SELECT_INPUT DAISY Register, offset: 0x5D8 */ + __IO uint32_t I2C2_SCL_SELECT_INPUT; /**< I2C2_SCL_SELECT_INPUT DAISY Register, offset: 0x5DC */ + __IO uint32_t I2C2_SDA_SELECT_INPUT; /**< I2C2_SDA_SELECT_INPUT DAISY Register, offset: 0x5E0 */ + __IO uint32_t I2C3_SCL_SELECT_INPUT; /**< I2C3_SCL_SELECT_INPUT DAISY Register, offset: 0x5E4 */ + __IO uint32_t I2C3_SDA_SELECT_INPUT; /**< I2C3_SDA_SELECT_INPUT DAISY Register, offset: 0x5E8 */ + __IO uint32_t I2C4_SCL_SELECT_INPUT; /**< I2C4_SCL_SELECT_INPUT DAISY Register, offset: 0x5EC */ + __IO uint32_t I2C4_SDA_SELECT_INPUT; /**< I2C4_SDA_SELECT_INPUT DAISY Register, offset: 0x5F0 */ + __IO uint32_t KPP_COL0_SELECT_INPUT; /**< KPP_COL0_SELECT_INPUT DAISY Register, offset: 0x5F4 */ + __IO uint32_t KPP_COL1_SELECT_INPUT; /**< KPP_COL1_SELECT_INPUT DAISY Register, offset: 0x5F8 */ + __IO uint32_t KPP_COL2_SELECT_INPUT; /**< KPP_COL2_SELECT_INPUT DAISY Register, offset: 0x5FC */ + __IO uint32_t KPP_COL3_SELECT_INPUT; /**< KPP_COL3_SELECT_INPUT DAISY Register, offset: 0x600 */ + __IO uint32_t KPP_COL4_SELECT_INPUT; /**< KPP_COL4_SELECT_INPUT DAISY Register, offset: 0x604 */ + __IO uint32_t KPP_COL5_SELECT_INPUT; /**< KPP_COL5_SELECT_INPUT DAISY Register, offset: 0x608 */ + __IO uint32_t KPP_COL6_SELECT_INPUT; /**< KPP_COL6_SELECT_INPUT DAISY Register, offset: 0x60C */ + __IO uint32_t KPP_COL7_SELECT_INPUT; /**< KPP_COL7_SELECT_INPUT DAISY Register, offset: 0x610 */ + __IO uint32_t KPP_ROW0_SELECT_INPUT; /**< KPP_ROW0_SELECT_INPUT DAISY Register, offset: 0x614 */ + __IO uint32_t KPP_ROW1_SELECT_INPUT; /**< KPP_ROW1_SELECT_INPUT DAISY Register, offset: 0x618 */ + __IO uint32_t KPP_ROW2_SELECT_INPUT; /**< KPP_ROW2_SELECT_INPUT DAISY Register, offset: 0x61C */ + __IO uint32_t KPP_ROW3_SELECT_INPUT; /**< KPP_ROW3_SELECT_INPUT DAISY Register, offset: 0x620 */ + __IO uint32_t KPP_ROW4_SELECT_INPUT; /**< KPP_ROW4_SELECT_INPUT DAISY Register, offset: 0x624 */ + __IO uint32_t KPP_ROW5_SELECT_INPUT; /**< KPP_ROW5_SELECT_INPUT DAISY Register, offset: 0x628 */ + __IO uint32_t KPP_ROW6_SELECT_INPUT; /**< KPP_ROW6_SELECT_INPUT DAISY Register, offset: 0x62C */ + __IO uint32_t KPP_ROW7_SELECT_INPUT; /**< KPP_ROW7_SELECT_INPUT DAISY Register, offset: 0x630 */ + __IO uint32_t LCD_BUSY_SELECT_INPUT; /**< LCD_BUSY_SELECT_INPUT DAISY Register, offset: 0x634 */ + __IO uint32_t LCD_DATA00_SELECT_INPUT; /**< LCD_DATA00_SELECT_INPUT DAISY Register, offset: 0x638 */ + __IO uint32_t LCD_DATA01_SELECT_INPUT; /**< LCD_DATA01_SELECT_INPUT DAISY Register, offset: 0x63C */ + __IO uint32_t LCD_DATA02_SELECT_INPUT; /**< LCD_DATA02_SELECT_INPUT DAISY Register, offset: 0x640 */ + __IO uint32_t LCD_DATA03_SELECT_INPUT; /**< LCD_DATA03_SELECT_INPUT DAISY Register, offset: 0x644 */ + __IO uint32_t LCD_DATA04_SELECT_INPUT; /**< LCD_DATA04_SELECT_INPUT DAISY Register, offset: 0x648 */ + __IO uint32_t LCD_DATA05_SELECT_INPUT; /**< LCD_DATA05_SELECT_INPUT DAISY Register, offset: 0x64C */ + __IO uint32_t LCD_DATA06_SELECT_INPUT; /**< LCD_DATA06_SELECT_INPUT DAISY Register, offset: 0x650 */ + __IO uint32_t LCD_DATA07_SELECT_INPUT; /**< LCD_DATA07_SELECT_INPUT DAISY Register, offset: 0x654 */ + __IO uint32_t LCD_DATA08_SELECT_INPUT; /**< LCD_DATA08_SELECT_INPUT DAISY Register, offset: 0x658 */ + __IO uint32_t LCD_DATA09_SELECT_INPUT; /**< LCD_DATA09_SELECT_INPUT DAISY Register, offset: 0x65C */ + __IO uint32_t LCD_DATA10_SELECT_INPUT; /**< LCD_DATA10_SELECT_INPUT DAISY Register, offset: 0x660 */ + __IO uint32_t LCD_DATA11_SELECT_INPUT; /**< LCD_DATA11_SELECT_INPUT DAISY Register, offset: 0x664 */ + __IO uint32_t LCD_DATA12_SELECT_INPUT; /**< LCD_DATA12_SELECT_INPUT DAISY Register, offset: 0x668 */ + __IO uint32_t LCD_DATA13_SELECT_INPUT; /**< LCD_DATA13_SELECT_INPUT DAISY Register, offset: 0x66C */ + __IO uint32_t LCD_DATA14_SELECT_INPUT; /**< LCD_DATA14_SELECT_INPUT DAISY Register, offset: 0x670 */ + __IO uint32_t LCD_DATA15_SELECT_INPUT; /**< LCD_DATA15_SELECT_INPUT DAISY Register, offset: 0x674 */ + __IO uint32_t LCD_DATA16_SELECT_INPUT; /**< LCD_DATA16_SELECT_INPUT DAISY Register, offset: 0x678 */ + __IO uint32_t LCD_DATA17_SELECT_INPUT; /**< LCD_DATA17_SELECT_INPUT DAISY Register, offset: 0x67C */ + __IO uint32_t LCD_DATA18_SELECT_INPUT; /**< LCD_DATA18_SELECT_INPUT DAISY Register, offset: 0x680 */ + __IO uint32_t LCD_DATA19_SELECT_INPUT; /**< LCD_DATA19_SELECT_INPUT DAISY Register, offset: 0x684 */ + __IO uint32_t LCD_DATA20_SELECT_INPUT; /**< LCD_DATA20_SELECT_INPUT DAISY Register, offset: 0x688 */ + __IO uint32_t LCD_DATA21_SELECT_INPUT; /**< LCD_DATA21_SELECT_INPUT DAISY Register, offset: 0x68C */ + __IO uint32_t LCD_DATA22_SELECT_INPUT; /**< LCD_DATA22_SELECT_INPUT DAISY Register, offset: 0x690 */ + __IO uint32_t LCD_DATA23_SELECT_INPUT; /**< LCD_DATA23_SELECT_INPUT DAISY Register, offset: 0x694 */ + __IO uint32_t LCD_VSYNC_SELECT_INPUT; /**< LCD_VSYNC_SELECT_INPUT DAISY Register, offset: 0x698 */ + __IO uint32_t SAI1_RX_BCLK_SELECT_INPUT; /**< SAI1_RX_BCLK_SELECT_INPUT DAISY Register, offset: 0x69C */ + __IO uint32_t SAI1_RX_DATA_SELECT_INPUT; /**< SAI1_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6A0 */ + __IO uint32_t SAI1_RX_SYNC_SELECT_INPUT; /**< SAI1_RX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6A4 */ + __IO uint32_t SAI1_TX_BCLK_SELECT_INPUT; /**< SAI1_TX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6A8 */ + __IO uint32_t SAI1_TX_SYNC_SELECT_INPUT; /**< SAI1_TX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6AC */ + __IO uint32_t SAI2_RX_BCLK_SELECT_INPUT; /**< SAI2_RX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6B0 */ + __IO uint32_t SAI2_RX_DATA_SELECT_INPUT; /**< SAI2_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6B4 */ + __IO uint32_t SAI2_RX_SYNC_SELECT_INPUT; /**< SAI2_RX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6B8 */ + __IO uint32_t SAI2_TX_BCLK_SELECT_INPUT; /**< SAI2_TX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6BC */ + __IO uint32_t SAI2_TX_SYNC_SELECT_INPUT; /**< SAI2_TX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6C0 */ + __IO uint32_t SAI3_RX_BCLK_SELECT_INPUT; /**< SAI3_RX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6C4 */ + __IO uint32_t SAI3_RX_DATA_SELECT_INPUT; /**< SAI3_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6C8 */ + __IO uint32_t SAI3_RX_SYNC_SELECT_INPUT; /**< SAI3_RX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6CC */ + __IO uint32_t SAI3_TX_BCLK_SELECT_INPUT; /**< SAI3_TX_BCLK_SELECT_INPUT DAISY Register, offset: 0x6D0 */ + __IO uint32_t SAI3_TX_SYNC_SELECT_INPUT; /**< SAI3_TX_SYNC_SELECT_INPUT DAISY Register, offset: 0x6D4 */ + __IO uint32_t SDMA_EVENTS0_SELECT_INPUT; /**< SDMA_EVENTS0_SELECT_INPUT DAISY Register, offset: 0x6D8 */ + __IO uint32_t SDMA_EVENTS1_SELECT_INPUT; /**< SDMA_EVENTS1_SELECT_INPUT DAISY Register, offset: 0x6DC */ + __IO uint32_t SIM1_PORT1_PD_SELECT_INPUT; /**< SIM1_PORT1_PD_SELECT_INPUT DAISY Register, offset: 0x6E0 */ + __IO uint32_t SIM1_PORT1_TRXD_SELECT_INPUT; /**< SIM1_PORT1_TRXD_SELECT_INPUT DAISY Register, offset: 0x6E4 */ + __IO uint32_t SIM2_PORT1_PD_SELECT_INPUT; /**< SIM2_PORT1_PD_SELECT_INPUT DAISY Register, offset: 0x6E8 */ + __IO uint32_t SIM2_PORT1_TRXD_SELECT_INPUT; /**< SIM2_PORT1_TRXD_SELECT_INPUT DAISY Register, offset: 0x6EC */ + __IO uint32_t UART1_RTS_B_SELECT_INPUT; /**< UART1_RTS_B_SELECT_INPUT DAISY Register, offset: 0x6F0 */ + __IO uint32_t UART1_RX_DATA_SELECT_INPUT; /**< UART1_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6F4 */ + __IO uint32_t UART2_RTS_B_SELECT_INPUT; /**< UART2_RTS_B_SELECT_INPUT DAISY Register, offset: 0x6F8 */ + __IO uint32_t UART2_RX_DATA_SELECT_INPUT; /**< UART2_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x6FC */ + __IO uint32_t UART3_RTS_B_SELECT_INPUT; /**< UART3_RTS_B_SELECT_INPUT DAISY Register, offset: 0x700 */ + __IO uint32_t UART3_RX_DATA_SELECT_INPUT; /**< UART3_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x704 */ + __IO uint32_t UART4_RTS_B_SELECT_INPUT; /**< UART4_RTS_B_SELECT_INPUT DAISY Register, offset: 0x708 */ + __IO uint32_t UART4_RX_DATA_SELECT_INPUT; /**< UART4_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x70C */ + __IO uint32_t UART5_RTS_B_SELECT_INPUT; /**< UART5_RTS_B_SELECT_INPUT DAISY Register, offset: 0x710 */ + __IO uint32_t UART5_RX_DATA_SELECT_INPUT; /**< UART5_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x714 */ + __IO uint32_t UART6_RTS_B_SELECT_INPUT; /**< UART6_RTS_B_SELECT_INPUT DAISY Register, offset: 0x718 */ + __IO uint32_t UART6_RX_DATA_SELECT_INPUT; /**< UART6_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x71C */ + __IO uint32_t UART7_RTS_B_SELECT_INPUT; /**< UART7_RTS_B_SELECT_INPUT DAISY Register, offset: 0x720 */ + __IO uint32_t UART7_RX_DATA_SELECT_INPUT; /**< UART7_RX_DATA_SELECT_INPUT DAISY Register, offset: 0x724 */ + __IO uint32_t USB_OTG2_OC_SELECT_INPUT; /**< USB_OTG2_OC_SELECT_INPUT DAISY Register, offset: 0x728 */ + __IO uint32_t USB_OTG1_OC_SELECT_INPUT; /**< USB_OTG1_OC_SELECT_INPUT DAISY Register, offset: 0x72C */ + __IO uint32_t USB_OTG2_ID_SELECT_INPUT; /**< USB_OTG2_ID_SELECT_INPUT DAISY Register, offset: 0x730 */ + __IO uint32_t USB_OTG1_ID_SELECT_INPUT; /**< USB_OTG1_ID_SELECT_INPUT DAISY Register, offset: 0x734 */ + __IO uint32_t SD3_CD_B_SELECT_INPUT; /**< SD3_CD_B_SELECT_INPUT DAISY Register, offset: 0x738 */ + __IO uint32_t SD3_WP_SELECT_INPUT; /**< SD3_WP_SELECT_INPUT DAISY Register, offset: 0x73C */ +} IOMUXC_Type, *IOMUXC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- IOMUXC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros + * @{ + */ + + +/* IOMUXC - Register accessors */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO14) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO15) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCLK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDLE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDOE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDSHR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE0) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE1) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE2) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE3) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDCLK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDOE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDRL) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDSP) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR0) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR1) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_COM) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_STAT) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_ENABLE) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_HSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_VSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_RESET) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA16) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA17) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA18) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA19) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA20) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA21) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA22) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA23) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RTS_B) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_CTS_B) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MOSI) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MISO) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SS0) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MOSI) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MISO) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SS0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CD_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_WP) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CD_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_WP) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_STROBE) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_MCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD0) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD1) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD2) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD3) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RXC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD0) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD1) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD2) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD3) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TXC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO14) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO15) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCLK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDLE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDOE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDSHR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE0) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE1) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE2) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE3) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDCLK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDOE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDRL) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDSP) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR0) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR1) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_COM) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_STAT) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_ENABLE) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_HSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_VSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_RESET) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA16) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA17) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA18) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA19) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA20) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA21) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA22) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA23) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RTS) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_CTS) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MOSI) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MISO) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SS0) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MOSI) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MISO) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SS0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CD_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_WP) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CD_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_WP) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_STROBE) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_MCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD0) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD1) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD2) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD3) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RXC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD0) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD1) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD2) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD3) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TXC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) +#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN1_RX_SELECT_INPUT) +#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN2_RX_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_1_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_2_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_3_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_4_SELECT_INPUT) +#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_READY_SELECT_INPUT) +#define IOMUXC_CSI_DATA2_SELECT_INPUT_REG(base) ((base)->CSI_DATA2_SELECT_INPUT) +#define IOMUXC_CSI_DATA3_SELECT_INPUT_REG(base) ((base)->CSI_DATA3_SELECT_INPUT) +#define IOMUXC_CSI_DATA4_SELECT_INPUT_REG(base) ((base)->CSI_DATA4_SELECT_INPUT) +#define IOMUXC_CSI_DATA5_SELECT_INPUT_REG(base) ((base)->CSI_DATA5_SELECT_INPUT) +#define IOMUXC_CSI_DATA6_SELECT_INPUT_REG(base) ((base)->CSI_DATA6_SELECT_INPUT) +#define IOMUXC_CSI_DATA7_SELECT_INPUT_REG(base) ((base)->CSI_DATA7_SELECT_INPUT) +#define IOMUXC_CSI_DATA8_SELECT_INPUT_REG(base) ((base)->CSI_DATA8_SELECT_INPUT) +#define IOMUXC_CSI_DATA9_SELECT_INPUT_REG(base) ((base)->CSI_DATA9_SELECT_INPUT) +#define IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI_HSYNC_SELECT_INPUT) +#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI_PIXCLK_SELECT_INPUT) +#define IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI_VSYNC_SELECT_INPUT) +#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI1_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI1_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI2_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI2_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI3_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI3_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI4_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI4_SS0_B_SELECT_INPUT) +#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_REG(base) ((base)->CCM_ENET_REF_CLK1_SELECT_INPUT) +#define IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_MDIO_SELECT_INPUT) +#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET1_RX_CLK_SELECT_INPUT) +#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_REG(base) ((base)->CCM_ENET_REF_CLK2_SELECT_INPUT) +#define IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_MDIO_SELECT_INPUT) +#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET2_RX_CLK_SELECT_INPUT) +#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_IRQ_SELECT_INPUT) +#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_STAT_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH0_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH1_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH2_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH3_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH4_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH5_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH6_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH7_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHA_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHB_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH0_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH1_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH2_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH3_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH4_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH5_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH6_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH7_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHA_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHB_SELECT_INPUT) +#define IOMUXC_I2C1_SCL_SELECT_INPUT_REG(base) ((base)->I2C1_SCL_SELECT_INPUT) +#define IOMUXC_I2C1_SDA_SELECT_INPUT_REG(base) ((base)->I2C1_SDA_SELECT_INPUT) +#define IOMUXC_I2C2_SCL_SELECT_INPUT_REG(base) ((base)->I2C2_SCL_SELECT_INPUT) +#define IOMUXC_I2C2_SDA_SELECT_INPUT_REG(base) ((base)->I2C2_SDA_SELECT_INPUT) +#define IOMUXC_I2C3_SCL_SELECT_INPUT_REG(base) ((base)->I2C3_SCL_SELECT_INPUT) +#define IOMUXC_I2C3_SDA_SELECT_INPUT_REG(base) ((base)->I2C3_SDA_SELECT_INPUT) +#define IOMUXC_I2C4_SCL_SELECT_INPUT_REG(base) ((base)->I2C4_SCL_SELECT_INPUT) +#define IOMUXC_I2C4_SDA_SELECT_INPUT_REG(base) ((base)->I2C4_SDA_SELECT_INPUT) +#define IOMUXC_KPP_COL0_SELECT_INPUT_REG(base) ((base)->KPP_COL0_SELECT_INPUT) +#define IOMUXC_KPP_COL1_SELECT_INPUT_REG(base) ((base)->KPP_COL1_SELECT_INPUT) +#define IOMUXC_KPP_COL2_SELECT_INPUT_REG(base) ((base)->KPP_COL2_SELECT_INPUT) +#define IOMUXC_KPP_COL3_SELECT_INPUT_REG(base) ((base)->KPP_COL3_SELECT_INPUT) +#define IOMUXC_KPP_COL4_SELECT_INPUT_REG(base) ((base)->KPP_COL4_SELECT_INPUT) +#define IOMUXC_KPP_COL5_SELECT_INPUT_REG(base) ((base)->KPP_COL5_SELECT_INPUT) +#define IOMUXC_KPP_COL6_SELECT_INPUT_REG(base) ((base)->KPP_COL6_SELECT_INPUT) +#define IOMUXC_KPP_COL7_SELECT_INPUT_REG(base) ((base)->KPP_COL7_SELECT_INPUT) +#define IOMUXC_KPP_ROW0_SELECT_INPUT_REG(base) ((base)->KPP_ROW0_SELECT_INPUT) +#define IOMUXC_KPP_ROW1_SELECT_INPUT_REG(base) ((base)->KPP_ROW1_SELECT_INPUT) +#define IOMUXC_KPP_ROW2_SELECT_INPUT_REG(base) ((base)->KPP_ROW2_SELECT_INPUT) +#define IOMUXC_KPP_ROW3_SELECT_INPUT_REG(base) ((base)->KPP_ROW3_SELECT_INPUT) +#define IOMUXC_KPP_ROW4_SELECT_INPUT_REG(base) ((base)->KPP_ROW4_SELECT_INPUT) +#define IOMUXC_KPP_ROW5_SELECT_INPUT_REG(base) ((base)->KPP_ROW5_SELECT_INPUT) +#define IOMUXC_KPP_ROW6_SELECT_INPUT_REG(base) ((base)->KPP_ROW6_SELECT_INPUT) +#define IOMUXC_KPP_ROW7_SELECT_INPUT_REG(base) ((base)->KPP_ROW7_SELECT_INPUT) +#define IOMUXC_LCD_BUSY_SELECT_INPUT_REG(base) ((base)->LCD_BUSY_SELECT_INPUT) +#define IOMUXC_LCD_DATA00_SELECT_INPUT_REG(base) ((base)->LCD_DATA00_SELECT_INPUT) +#define IOMUXC_LCD_DATA01_SELECT_INPUT_REG(base) ((base)->LCD_DATA01_SELECT_INPUT) +#define IOMUXC_LCD_DATA02_SELECT_INPUT_REG(base) ((base)->LCD_DATA02_SELECT_INPUT) +#define IOMUXC_LCD_DATA03_SELECT_INPUT_REG(base) ((base)->LCD_DATA03_SELECT_INPUT) +#define IOMUXC_LCD_DATA04_SELECT_INPUT_REG(base) ((base)->LCD_DATA04_SELECT_INPUT) +#define IOMUXC_LCD_DATA05_SELECT_INPUT_REG(base) ((base)->LCD_DATA05_SELECT_INPUT) +#define IOMUXC_LCD_DATA06_SELECT_INPUT_REG(base) ((base)->LCD_DATA06_SELECT_INPUT) +#define IOMUXC_LCD_DATA07_SELECT_INPUT_REG(base) ((base)->LCD_DATA07_SELECT_INPUT) +#define IOMUXC_LCD_DATA08_SELECT_INPUT_REG(base) ((base)->LCD_DATA08_SELECT_INPUT) +#define IOMUXC_LCD_DATA09_SELECT_INPUT_REG(base) ((base)->LCD_DATA09_SELECT_INPUT) +#define IOMUXC_LCD_DATA10_SELECT_INPUT_REG(base) ((base)->LCD_DATA10_SELECT_INPUT) +#define IOMUXC_LCD_DATA11_SELECT_INPUT_REG(base) ((base)->LCD_DATA11_SELECT_INPUT) +#define IOMUXC_LCD_DATA12_SELECT_INPUT_REG(base) ((base)->LCD_DATA12_SELECT_INPUT) +#define IOMUXC_LCD_DATA13_SELECT_INPUT_REG(base) ((base)->LCD_DATA13_SELECT_INPUT) +#define IOMUXC_LCD_DATA14_SELECT_INPUT_REG(base) ((base)->LCD_DATA14_SELECT_INPUT) +#define IOMUXC_LCD_DATA15_SELECT_INPUT_REG(base) ((base)->LCD_DATA15_SELECT_INPUT) +#define IOMUXC_LCD_DATA16_SELECT_INPUT_REG(base) ((base)->LCD_DATA16_SELECT_INPUT) +#define IOMUXC_LCD_DATA17_SELECT_INPUT_REG(base) ((base)->LCD_DATA17_SELECT_INPUT) +#define IOMUXC_LCD_DATA18_SELECT_INPUT_REG(base) ((base)->LCD_DATA18_SELECT_INPUT) +#define IOMUXC_LCD_DATA19_SELECT_INPUT_REG(base) ((base)->LCD_DATA19_SELECT_INPUT) +#define IOMUXC_LCD_DATA20_SELECT_INPUT_REG(base) ((base)->LCD_DATA20_SELECT_INPUT) +#define IOMUXC_LCD_DATA21_SELECT_INPUT_REG(base) ((base)->LCD_DATA21_SELECT_INPUT) +#define IOMUXC_LCD_DATA22_SELECT_INPUT_REG(base) ((base)->LCD_DATA22_SELECT_INPUT) +#define IOMUXC_LCD_DATA23_SELECT_INPUT_REG(base) ((base)->LCD_DATA23_SELECT_INPUT) +#define IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(base) ((base)->LCD_VSYNC_SELECT_INPUT) +#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI1_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI2_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI3_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS0_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS1_SELECT_INPUT) +#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_PD_SELECT_INPUT) +#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_TRXD_SELECT_INPUT) +#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_PD_SELECT_INPUT) +#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_TRXD_SELECT_INPUT) +#define IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_RTS_B_SELECT_INPUT) +#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART1_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_RTS_B_SELECT_INPUT) +#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART2_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_RTS_B_SELECT_INPUT) +#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART3_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_RTS_B_SELECT_INPUT) +#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART4_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_RTS_B_SELECT_INPUT) +#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART5_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_RTS_B_SELECT_INPUT) +#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART6_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(base) ((base)->UART7_RTS_B_SELECT_INPUT) +#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART7_RX_DATA_SELECT_INPUT) +#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG2_OC_SELECT_INPUT) +#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG1_OC_SELECT_INPUT) +#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG2_ID_SELECT_INPUT) +#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG1_ID_SELECT_INPUT) +#define IOMUXC_SD3_CD_B_SELECT_INPUT_REG(base) ((base)->SD3_CD_B_SELECT_INPUT) +#define IOMUXC_SD3_WP_SELECT_INPUT_REG(base) ((base)->SD3_WP_SELECT_INPUT) + +/*! + * @} + */ /* end of group IOMUXC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO08 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO09 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO10 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO11 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO12 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO13 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO14 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO15 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA00 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA01 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA02 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA03 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA04 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA05 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA06 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA07 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA08 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA09 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA10 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA11 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA12 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA13 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA14 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_DATA15 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_MASK 0xFu +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDLE Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDOE Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDSHR Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDCE0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDCE1 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDCE2 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_SDCE3 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_GDCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_GDOE Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_GDRL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_GDSP Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_BDR0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_BDR1 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_PWR_COM Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_EPDC_PWR_STAT Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_CLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_ENABLE Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_HSYNC Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_VSYNC Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_RESET Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA00 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA01 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA02 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA03 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA04 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA05 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA06 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA07 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA08 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA09 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA10 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA11 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA12 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA13 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA14 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA15 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA16 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA17 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA18 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA19 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA20 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA21 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA22 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_LCD_DATA23 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART1_RX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART1_TX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART2_RX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART2_TX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART3_RX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART3_TX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART3_RTS_B Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_UART3_CTS_B Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C1_SCL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C1_SDA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C2_SCL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C2_SDA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C3_SCL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C3_SDA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C4_SCL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_I2C4_SDA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI1_SCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI1_MOSI Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI1_MISO Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI1_SS0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI2_SCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI2_MOSI Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI2_MISO Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ECSPI2_SS0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_CD_B Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_WP Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_WP_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_RESET_B Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_CLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_CMD Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_DATA0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_DATA1 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_DATA2 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD1_DATA3 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_CD_B Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_WP Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_WP_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_RESET_B Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_CLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_CMD Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_DATA0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_DATA1 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_DATA2 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD2_DATA3 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_CLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_CMD Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA1 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA2 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA3 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA4 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA5 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA6 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_DATA7 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_STROBE Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SD3_RESET_B Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI1_RX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI1_TX_BCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI1_TX_SYNC Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI1_TX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI1_RX_SYNC Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI1_RX_BCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI1_MCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI2_TX_SYNC Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI2_TX_BCLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI2_RX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_SAI2_TX_DATA Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_RD0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_RD1 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_RD2 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_RD3 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_RXC Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_TD0 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_TD1 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_TD2 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_TD3 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RGMII_TXC Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_TX_CLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_RX_CLK Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_CRS Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_ENET1_COL Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_SHIFT))&IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_MASK 0x10u +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_SION_SHIFT 4 +/* SW_PAD_CTL_PAD_GPIO1_IO08 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO09 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO10 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO11 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO12 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO13 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO14 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO15 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_PS_MASK) +/* SW_PAD_CTL_PAD_JTAG_MOD Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_PS_MASK) +/* SW_PAD_CTL_PAD_JTAG_TCK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_PS_MASK) +/* SW_PAD_CTL_PAD_JTAG_TDI Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_PS_MASK) +/* SW_PAD_CTL_PAD_JTAG_TDO Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_PS_MASK) +/* SW_PAD_CTL_PAD_JTAG_TMS Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_PS_MASK) +/* SW_PAD_CTL_PAD_JTAG_TRST_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA00 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA01 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA02 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA03 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA04 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA05 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA06 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA07 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA08 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA09 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA10 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA11 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA12 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA13 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA14 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_DATA15 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDLE Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDOE Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDSHR Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDCE0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDCE1 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDCE2 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_SDCE3 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_GDCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_GDOE Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_GDRL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_GDSP Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_BDR0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_BDR1 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_PWR_COM Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_PS_MASK) +/* SW_PAD_CTL_PAD_EPDC_PWR_STAT Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_CLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_ENABLE Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_HSYNC Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_VSYNC Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_RESET Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA00 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA01 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA02 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA03 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA04 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA05 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA06 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA07 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA08 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA09 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA10 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA11 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA12 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA13 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA14 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA15 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA16 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA17 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA18 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA19 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA20 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA21 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA22 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_PS_MASK) +/* SW_PAD_CTL_PAD_LCD_DATA23 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_PS_MASK) +/* SW_PAD_CTL_PAD_UART1_RX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_UART1_TX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_UART2_RX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_UART2_TX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_UART3_RX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_UART3_TX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_UART3_RTS Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_PS_MASK) +/* SW_PAD_CTL_PAD_UART3_CTS Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_PS_MASK) +/* SW_PAD_CTL_PAD_I2C1_SCL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS_MASK) +/* SW_PAD_CTL_PAD_I2C1_SDA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS_MASK) +/* SW_PAD_CTL_PAD_I2C2_SCL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS_MASK) +/* SW_PAD_CTL_PAD_I2C2_SDA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS_MASK) +/* SW_PAD_CTL_PAD_I2C3_SCL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS_MASK) +/* SW_PAD_CTL_PAD_I2C3_SDA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS_MASK) +/* SW_PAD_CTL_PAD_I2C4_SCL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_PS_MASK) +/* SW_PAD_CTL_PAD_I2C4_SDA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI1_SCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI1_MOSI Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI1_MISO Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI1_SS0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI2_SCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI2_MOSI Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI2_MISO Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_PS_MASK) +/* SW_PAD_CTL_PAD_ECSPI2_SS0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_CD_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_WP Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_WP_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_WP_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_RESET_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_CLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_CMD Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_DATA0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_DATA1 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_DATA2 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_PS_MASK) +/* SW_PAD_CTL_PAD_SD1_DATA3 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_CD_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_WP Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_WP_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_WP_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_RESET_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_CLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_CMD Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_DATA0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_DATA1 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_DATA2 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_PS_MASK) +/* SW_PAD_CTL_PAD_SD2_DATA3 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_CLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_CMD Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA1 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA2 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA3 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA4 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA5 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA6 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_DATA7 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_STROBE Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_PS_MASK) +/* SW_PAD_CTL_PAD_SD3_RESET_B Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_PS_MASK) +/* SW_PAD_CTL_PAD_SAI1_RX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_SAI1_TX_BCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_PS_MASK) +/* SW_PAD_CTL_PAD_SAI1_TX_SYNC Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_PS_MASK) +/* SW_PAD_CTL_PAD_SAI1_TX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_SAI1_RX_SYNC Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_PS_MASK) +/* SW_PAD_CTL_PAD_SAI1_RX_BCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_PS_MASK) +/* SW_PAD_CTL_PAD_SAI1_MCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_PS_MASK) +/* SW_PAD_CTL_PAD_SAI2_TX_SYNC Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_PS_MASK) +/* SW_PAD_CTL_PAD_SAI2_TX_BCLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_PS_MASK) +/* SW_PAD_CTL_PAD_SAI2_RX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_SAI2_TX_DATA Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_RD0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_RD1 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_RD2 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_RD3 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_RXC Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_TD0 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_TD1 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_TD2 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_TD3 Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RGMII_TXC Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_TX_CLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_RX_CLK Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_CRS Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_PS_MASK) +/* SW_PAD_CTL_PAD_ENET1_COL Bit Fields */ +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK 0x3u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT 0 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_MASK 0x4u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_SRE_SHIFT 2 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_MASK 0x8u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_HYS_SHIFT 3 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PE_MASK 0x10u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PE_SHIFT 4 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_MASK 0x60u +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_SHIFT 5 +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_SHIFT))&IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_PS_MASK) +/* FLEXCAN1_RX_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_MASK) +/* FLEXCAN2_RX_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_MASK) +/* CCM_EXT_CLK_1_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_DAISY_MASK) +/* CCM_EXT_CLK_2_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_DAISY_MASK) +/* CCM_EXT_CLK_3_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_DAISY_MASK) +/* CCM_EXT_CLK_4_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_DAISY_MASK) +/* CCM_PMIC_READY_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_PMIC_READY_SELECT_INPUT_DAISY_MASK) +/* CSI_DATA2_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA2_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA2_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_DATA3_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA3_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA3_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_DATA4_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA4_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA4_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_DATA5_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA5_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA5_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_DATA6_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA6_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA6_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_DATA7_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA7_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA7_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_DATA8_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA8_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA8_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_DATA9_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_DATA9_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_DATA9_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_HSYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_HSYNC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_HSYNC_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_PIXCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* CSI_VSYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_CSI_VSYNC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_CSI_VSYNC_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI1_SCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI1_MISO_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI1_MOSI_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI1_SS0_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI2_SCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI2_MISO_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI2_MOSI_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI2_SS0_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI3_SCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI3_MISO_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI3_MOSI_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI3_SS0_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_DAISY_SHIFT 0 +/* ECSPI4_SCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_SCLK_SELECT_INPUT_DAISY_MASK) +/* ECSPI4_MISO_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_MISO_SELECT_INPUT_DAISY_MASK) +/* ECSPI4_MOSI_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_MOSI_SELECT_INPUT_DAISY_MASK) +/* ECSPI4_SS0_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_DAISY_MASK) +/* CCM_ENET_REF_CLK1_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_DAISY_MASK) +/* ENET1_MDIO_SELECT_INPUT Bit Fields */ +#define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET1_MDIO_SELECT_INPUT_DAISY_MASK) +/* ENET1_RX_CLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_DAISY_SHIFT 0 +/* CCM_ENET_REF_CLK2_SELECT_INPUT Bit Fields */ +#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_DAISY_MASK) +/* ENET2_MDIO_SELECT_INPUT Bit Fields */ +#define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_ENET2_MDIO_SELECT_INPUT_DAISY_MASK) +/* ENET2_RX_CLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_DAISY_SHIFT 0 +/* EPDC_PWR_IRQ_SELECT_INPUT Bit Fields */ +#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_DAISY_SHIFT 0 +/* EPDC_PWR_STAT_SELECT_INPUT Bit Fields */ +#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH0_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH1_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH2_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH3_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH4_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH5_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH6_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_CH7_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_PHA_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER1_PHB_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH0_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH1_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH2_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH3_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH4_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH5_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH6_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_CH7_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_PHA_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_DAISY_SHIFT 0 +/* FLEXTIMER2_PHB_SELECT_INPUT Bit Fields */ +#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_DAISY_SHIFT 0 +/* I2C1_SCL_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY_MASK) +/* I2C1_SDA_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY_MASK) +/* I2C2_SCL_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY_MASK) +/* I2C2_SDA_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY_MASK) +/* I2C3_SCL_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY_MASK) +/* I2C3_SDA_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY_MASK) +/* I2C4_SCL_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY_MASK) +/* I2C4_SDA_SELECT_INPUT Bit Fields */ +#define IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY_MASK) +/* KPP_COL0_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL0_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL0_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_COL1_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL1_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL1_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_COL2_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL2_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL2_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_COL3_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL3_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL3_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_COL4_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL4_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL4_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_COL5_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL5_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL5_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_COL6_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL6_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL6_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_COL7_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_COL7_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_COL7_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW0_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW0_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW0_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW1_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW1_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW1_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW2_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW2_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW2_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW3_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW3_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW3_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW4_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW4_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW4_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW5_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW5_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW5_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW6_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW6_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW6_SELECT_INPUT_DAISY_SHIFT 0 +/* KPP_ROW7_SELECT_INPUT Bit Fields */ +#define IOMUXC_KPP_ROW7_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_KPP_ROW7_SELECT_INPUT_DAISY_SHIFT 0 +/* LCD_BUSY_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_BUSY_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_LCD_BUSY_SELECT_INPUT_DAISY_SHIFT 0 +/* LCD_DATA00_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA00_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA01_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA01_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA02_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA02_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA03_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA03_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA04_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA04_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA05_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA05_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA06_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA06_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA07_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA07_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA08_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA08_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA09_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA09_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA10_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA10_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA11_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA11_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA12_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA12_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA13_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA13_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA14_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA14_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA15_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA15_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA16_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA16_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA17_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA17_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA18_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA18_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA19_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA19_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA20_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA20_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA21_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA21_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA22_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA22_SELECT_INPUT_DAISY_MASK) +/* LCD_DATA23_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_DATA23_SELECT_INPUT_DAISY_MASK) +/* LCD_VSYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_LCD_VSYNC_SELECT_INPUT_DAISY_MASK) +/* SAI1_RX_BCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI1_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI1_RX_SYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI1_TX_BCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI1_TX_SYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI2_RX_BCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI2_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI2_RX_SYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI2_TX_BCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI2_TX_SYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_DAISY_SHIFT 0 +/* SAI3_RX_BCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_DAISY_MASK) +/* SAI3_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* SAI3_RX_SYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_DAISY_MASK) +/* SAI3_TX_BCLK_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_DAISY_MASK) +/* SAI3_TX_SYNC_SELECT_INPUT Bit Fields */ +#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_DAISY_MASK) +/* SDMA_EVENTS0_SELECT_INPUT Bit Fields */ +#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SDMA_EVENTS0_SELECT_INPUT_DAISY_MASK) +/* SDMA_EVENTS1_SELECT_INPUT Bit Fields */ +#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SDMA_EVENTS1_SELECT_INPUT_DAISY_MASK) +/* SIM1_PORT1_PD_SELECT_INPUT Bit Fields */ +#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_DAISY_SHIFT 0 +/* SIM1_PORT1_TRXD_SELECT_INPUT Bit Fields */ +#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_DAISY_SHIFT 0 +/* SIM2_PORT1_PD_SELECT_INPUT Bit Fields */ +#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_DAISY_SHIFT 0 +/* SIM2_PORT1_TRXD_SELECT_INPUT Bit Fields */ +#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_DAISY_SHIFT 0 +/* UART1_RTS_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_RTS_B_SELECT_INPUT_DAISY_MASK) +/* UART1_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART1_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* UART2_RTS_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_RTS_B_SELECT_INPUT_DAISY_MASK) +/* UART2_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* UART3_RTS_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_RTS_B_SELECT_INPUT_DAISY_MASK) +/* UART3_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART3_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* UART4_RTS_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_RTS_B_SELECT_INPUT_DAISY_MASK) +/* UART4_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART4_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* UART5_RTS_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_RTS_B_SELECT_INPUT_DAISY_MASK) +/* UART5_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART5_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* UART6_RTS_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_RTS_B_SELECT_INPUT_DAISY_MASK) +/* UART6_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* UART7_RTS_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART7_RTS_B_SELECT_INPUT_DAISY_MASK) +/* UART7_RX_DATA_SELECT_INPUT Bit Fields */ +#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_MASK 0x7u +#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_UART7_RX_DATA_SELECT_INPUT_DAISY_MASK) +/* USB_OTG2_OC_SELECT_INPUT Bit Fields */ +#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_DAISY_SHIFT 0 +/* USB_OTG1_OC_SELECT_INPUT Bit Fields */ +#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_DAISY_MASK 0x1u +#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_DAISY_SHIFT 0 +/* USB_OTG2_ID_SELECT_INPUT Bit Fields */ +#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_OTG2_ID_SELECT_INPUT_DAISY_MASK) +/* USB_OTG1_ID_SELECT_INPUT Bit Fields */ +#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_USB_OTG1_ID_SELECT_INPUT_DAISY_MASK) +/* SD3_CD_B_SELECT_INPUT Bit Fields */ +#define IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SD3_CD_B_SELECT_INPUT_DAISY_MASK) +/* SD3_WP_SELECT_INPUT Bit Fields */ +#define IOMUXC_SD3_WP_SELECT_INPUT_DAISY_MASK 0x3u +#define IOMUXC_SD3_WP_SELECT_INPUT_DAISY_SHIFT 0 +#define IOMUXC_SD3_WP_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_SD3_WP_SELECT_INPUT_DAISY_SHIFT))&IOMUXC_SD3_WP_SELECT_INPUT_DAISY_MASK) + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x30330000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +#define IOMUXC_BASE_PTR (IOMUXC) +/** Array initializer of IOMUXC peripheral base adresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/* ---------------------------------------------------------------------------- + -- IOMUXC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Accessor_Macros IOMUXC - Register accessor macros + * @{ + */ + + +/* IOMUXC - Register instance definitions */ +/* IOMUXC */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15 IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3 IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0 IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1 IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3 IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15 IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3 IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0 IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1 IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3 IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA2_SELECT_INPUT IOMUXC_CSI_DATA2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA3_SELECT_INPUT IOMUXC_CSI_DATA3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA4_SELECT_INPUT IOMUXC_CSI_DATA4_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA5_SELECT_INPUT IOMUXC_CSI_DATA5_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA6_SELECT_INPUT IOMUXC_CSI_DATA6_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA7_SELECT_INPUT IOMUXC_CSI_DATA7_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA8_SELECT_INPUT IOMUXC_CSI_DATA8_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_DATA9_SELECT_INPUT IOMUXC_CSI_DATA9_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_HSYNC_SELECT_INPUT IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_PIXCLK_SELECT_INPUT IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CSI_VSYNC_SELECT_INPUT IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI1_MISO_SELECT_INPUT IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI2_MISO_SELECT_INPUT IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI3_MISO_SELECT_INPUT IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI4_MISO_SELECT_INPUT IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT IOMUXC_CCM_ENET_REF_CLK1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ENET1_MDIO_SELECT_INPUT IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT IOMUXC_CCM_ENET_REF_CLK2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ENET2_MDIO_SELECT_INPUT IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C1_SCL_SELECT_INPUT IOMUXC_I2C1_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C1_SDA_SELECT_INPUT IOMUXC_I2C1_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C2_SCL_SELECT_INPUT IOMUXC_I2C2_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C2_SDA_SELECT_INPUT IOMUXC_I2C2_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C3_SCL_SELECT_INPUT IOMUXC_I2C3_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C3_SDA_SELECT_INPUT IOMUXC_I2C3_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C4_SCL_SELECT_INPUT IOMUXC_I2C4_SCL_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_I2C4_SDA_SELECT_INPUT IOMUXC_I2C4_SDA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL0_SELECT_INPUT IOMUXC_KPP_COL0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL1_SELECT_INPUT IOMUXC_KPP_COL1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL2_SELECT_INPUT IOMUXC_KPP_COL2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL3_SELECT_INPUT IOMUXC_KPP_COL3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL4_SELECT_INPUT IOMUXC_KPP_COL4_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL5_SELECT_INPUT IOMUXC_KPP_COL5_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL6_SELECT_INPUT IOMUXC_KPP_COL6_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_COL7_SELECT_INPUT IOMUXC_KPP_COL7_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW0_SELECT_INPUT IOMUXC_KPP_ROW0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW1_SELECT_INPUT IOMUXC_KPP_ROW1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW2_SELECT_INPUT IOMUXC_KPP_ROW2_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW3_SELECT_INPUT IOMUXC_KPP_ROW3_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW4_SELECT_INPUT IOMUXC_KPP_ROW4_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW5_SELECT_INPUT IOMUXC_KPP_ROW5_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW6_SELECT_INPUT IOMUXC_KPP_ROW6_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_KPP_ROW7_SELECT_INPUT IOMUXC_KPP_ROW7_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_BUSY_SELECT_INPUT IOMUXC_LCD_BUSY_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA00_SELECT_INPUT IOMUXC_LCD_DATA00_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA01_SELECT_INPUT IOMUXC_LCD_DATA01_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA02_SELECT_INPUT IOMUXC_LCD_DATA02_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA03_SELECT_INPUT IOMUXC_LCD_DATA03_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA04_SELECT_INPUT IOMUXC_LCD_DATA04_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA05_SELECT_INPUT IOMUXC_LCD_DATA05_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA06_SELECT_INPUT IOMUXC_LCD_DATA06_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA07_SELECT_INPUT IOMUXC_LCD_DATA07_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA08_SELECT_INPUT IOMUXC_LCD_DATA08_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA09_SELECT_INPUT IOMUXC_LCD_DATA09_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA10_SELECT_INPUT IOMUXC_LCD_DATA10_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA11_SELECT_INPUT IOMUXC_LCD_DATA11_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA12_SELECT_INPUT IOMUXC_LCD_DATA12_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA13_SELECT_INPUT IOMUXC_LCD_DATA13_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA14_SELECT_INPUT IOMUXC_LCD_DATA14_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA15_SELECT_INPUT IOMUXC_LCD_DATA15_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA16_SELECT_INPUT IOMUXC_LCD_DATA16_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA17_SELECT_INPUT IOMUXC_LCD_DATA17_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA18_SELECT_INPUT IOMUXC_LCD_DATA18_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA19_SELECT_INPUT IOMUXC_LCD_DATA19_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA20_SELECT_INPUT IOMUXC_LCD_DATA20_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA21_SELECT_INPUT IOMUXC_LCD_DATA21_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA22_SELECT_INPUT IOMUXC_LCD_DATA22_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_DATA23_SELECT_INPUT IOMUXC_LCD_DATA23_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_LCD_VSYNC_SELECT_INPUT IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART1_RTS_B_SELECT_INPUT IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART1_RX_DATA_SELECT_INPUT IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART2_RTS_B_SELECT_INPUT IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART2_RX_DATA_SELECT_INPUT IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART3_RTS_B_SELECT_INPUT IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART3_RX_DATA_SELECT_INPUT IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART4_RTS_B_SELECT_INPUT IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART4_RX_DATA_SELECT_INPUT IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART5_RTS_B_SELECT_INPUT IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART5_RX_DATA_SELECT_INPUT IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART6_RTS_B_SELECT_INPUT IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART6_RX_DATA_SELECT_INPUT IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART7_RTS_B_SELECT_INPUT IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_UART7_RX_DATA_SELECT_INPUT IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_USB_OTG2_OC_SELECT_INPUT IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_USB_OTG1_OC_SELECT_INPUT IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_USB_OTG2_ID_SELECT_INPUT IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_USB_OTG1_ID_SELECT_INPUT IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SD3_CD_B_SELECT_INPUT IOMUXC_SD3_CD_B_SELECT_INPUT_REG(IOMUXC_BASE_PTR) +#define IOMUXC_SD3_WP_SELECT_INPUT IOMUXC_SD3_WP_SELECT_INPUT_REG(IOMUXC_BASE_PTR) + +/*! + * @} + */ /* end of group IOMUXC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group IOMUXC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ + __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ + __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ + __IO uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ + __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ + __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ + __IO uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ + __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ + __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ + __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ + __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ + __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ + __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ + __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ +} IOMUXC_GPR_Type, *IOMUXC_GPR_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros + * @{ + */ + + +/* IOMUXC_GPR - Register accessors */ +#define IOMUXC_GPR_GPR0_REG(base) ((base)->GPR0) +#define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) +#define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) +#define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) +#define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) +#define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) +#define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) +#define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) +#define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) +#define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) +#define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) +#define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) +#define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) +#define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) +#define IOMUXC_GPR_GPR14_REG(base) ((base)->GPR14) +#define IOMUXC_GPR_GPR15_REG(base) ((base)->GPR15) +#define IOMUXC_GPR_GPR16_REG(base) ((base)->GPR16) +#define IOMUXC_GPR_GPR17_REG(base) ((base)->GPR17) +#define IOMUXC_GPR_GPR18_REG(base) ((base)->GPR18) +#define IOMUXC_GPR_GPR19_REG(base) ((base)->GPR19) +#define IOMUXC_GPR_GPR20_REG(base) ((base)->GPR20) +#define IOMUXC_GPR_GPR21_REG(base) ((base)->GPR21) +#define IOMUXC_GPR_GPR22_REG(base) ((base)->GPR22) + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +/* GPR1 Bit Fields */ +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK) +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK) +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK) +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK) +#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u +#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 +#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u +#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 +#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u +#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 +#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u +#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 +#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 +#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u +#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 +#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u +#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 +#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u +#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) +#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u +#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 +/* GPR2 Bit Fields */ +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u +#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 +#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u +#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 +#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u +#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 +/* GPR3 Bit Fields */ +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 +/* GPR4 Bit Fields */ +#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u +#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 +#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u +#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 +#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u +#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 +#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u +#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 +#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u +#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 +#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u +#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 +#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u +#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 +#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u +#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 +#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u +#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 +#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u +#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 +#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u +#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 +#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u +#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 +#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u +#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 +#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u +#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 +#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u +#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 +#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u +#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK) +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK) +/* GPR5 Bit Fields */ +#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u +#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 +#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u +#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 +#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u +#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 +#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u +#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 +#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u +#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 +#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u +#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 +#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u +#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 +#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u +#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 +#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u +#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 +#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u +#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 +#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u +#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 +/* GPR6 Bit Fields */ +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 +/* GPR7 Bit Fields */ +#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u +#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 +#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u +#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 +#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u +#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 +#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u +#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK) +#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u +#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 +#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u +#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 +#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u +#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 +#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u +#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK) +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 +/* GPR8 Bit Fields */ +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK) +#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u +#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 +/* GPR9 Bit Fields */ +#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u +#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK) +/* GPR10 Bit Fields */ +#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u +#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 +#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u +#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 +#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u +#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK) +/* GPR11 Bit Fields */ +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK) +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) +/* GPR12 Bit Fields */ +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK) +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK) +/* GPR13 Bit Fields */ +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK) +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 +/* GPR14 Bit Fields */ +#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u +#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 +#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u +#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 +/* GPR15 Bit Fields */ +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK) +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK) +/* GPR16 Bit Fields */ +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u +#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 +#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u +#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 +#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK) +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 +#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 +/* GPR17 Bit Fields */ +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK) +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK) +/* GPR18 Bit Fields */ +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK) +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 +#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 +#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u +#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 +/* GPR19 Bit Fields */ +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK) +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 +#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u +#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 +/* GPR20 Bit Fields */ +#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu +#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 +#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK) +#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u +#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 +#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK) +#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 +#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK) +#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 +#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK) +/* GPR21 Bit Fields */ +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK) +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK) +#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u +#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 +#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u +#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 +/* GPR22 Bit Fields */ +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK) +#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u +#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 +#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u +#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 +#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u +#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 +#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u +#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 +#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u +#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 +#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u +#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 +#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u +#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x30340000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +#define IOMUXC_GPR_BASE_PTR (IOMUXC_GPR) +/** Array initializer of IOMUXC_GPR peripheral base adresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Accessor_Macros IOMUXC_GPR - Register accessor macros + * @{ + */ + + +/* IOMUXC_GPR - Register instance definitions */ +/* IOMUXC_GPR */ +#define IOMUXC_GPR_GPR0 IOMUXC_GPR_GPR0_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR1 IOMUXC_GPR_GPR1_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR2 IOMUXC_GPR_GPR2_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR3 IOMUXC_GPR_GPR3_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR4 IOMUXC_GPR_GPR4_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR5 IOMUXC_GPR_GPR5_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR6 IOMUXC_GPR_GPR6_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR7 IOMUXC_GPR_GPR7_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR8 IOMUXC_GPR_GPR8_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR9 IOMUXC_GPR_GPR9_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR10 IOMUXC_GPR_GPR10_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR11 IOMUXC_GPR_GPR11_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR12 IOMUXC_GPR_GPR12_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR13 IOMUXC_GPR_GPR13_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR14 IOMUXC_GPR_GPR14_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR15 IOMUXC_GPR_GPR15_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR16 IOMUXC_GPR_GPR16_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR17 IOMUXC_GPR_GPR17_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR18 IOMUXC_GPR_GPR18_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR19 IOMUXC_GPR_GPR19_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR20 IOMUXC_GPR_GPR20_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR21 IOMUXC_GPR_GPR21_REG(IOMUXC_GPR_BASE_PTR) +#define IOMUXC_GPR_GPR22 IOMUXC_GPR_GPR22_REG(IOMUXC_GPR_BASE_PTR) + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_Peripheral_Access_Layer IOMUXC_LPSR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_LPSR - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO00; /**< SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register, offset: 0x0 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO01; /**< SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register, offset: 0x4 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO02; /**< SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register, offset: 0x8 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO03; /**< SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register, offset: 0xC */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO04; /**< SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register, offset: 0x10 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO05; /**< SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register, offset: 0x14 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO06; /**< SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register, offset: 0x18 */ + __IO uint32_t SW_MUX_CTL_PAD_GPIO1_IO07; /**< SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register, offset: 0x1C */ + __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0x20 */ + __IO uint32_t SW_PAD_CTL_PAD_SRC_POR_B; /**< SW_PAD_CTL_PAD_SRC_POR_B SW PAD Control Register, offset: 0x24 */ + __IO uint32_t SW_PAD_CTL_PAD_BOOT_MODE0; /**< SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register, offset: 0x28 */ + __IO uint32_t SW_PAD_CTL_PAD_BOOT_MODE1; /**< SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control Register, offset: 0x2C */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO00; /**< SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register, offset: 0x30 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO01; /**< SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register, offset: 0x34 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO02; /**< SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register, offset: 0x38 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO03; /**< SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register, offset: 0x3C */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO04; /**< SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register, offset: 0x40 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO05; /**< SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register, offset: 0x44 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO06; /**< SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register, offset: 0x48 */ + __IO uint32_t SW_PAD_CTL_PAD_GPIO1_IO07; /**< SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register, offset: 0x4C */ +} IOMUXC_LPSR_Type, *IOMUXC_LPSR_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_Register_Accessor_Macros IOMUXC_LPSR - Register accessor macros + * @{ + */ + + +/* IOMUXC_LPSR - Register accessors */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO00) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_REG(base) ((base)->SW_PAD_CTL_PAD_TEST_MODE) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_REG(base) ((base)->SW_PAD_CTL_PAD_SRC_POR_B) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE0) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE1) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO01 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO02 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO03 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO04 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO05 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO06 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_SION_SHIFT 4 +/* SW_MUX_CTL_PAD_GPIO1_IO07 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_SHIFT))&IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_MUX_MODE_MASK) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_SION_MASK 0x10u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_SION_SHIFT 4 +/* SW_PAD_CTL_PAD_TEST_MODE Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_PS_MASK) +/* SW_PAD_CTL_PAD_SRC_POR_B Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_PS_MASK) +/* SW_PAD_CTL_PAD_BOOT_MODE0 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_PS_MASK) +/* SW_PAD_CTL_PAD_BOOT_MODE1 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO00 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO01 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO02 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO03 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO04 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO05 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO06 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_PS_MASK) +/* SW_PAD_CTL_PAD_GPIO1_IO07 Bit Fields */ +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK 0x3u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT 0 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_DSE_MASK) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_MASK 0x4u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_SRE_SHIFT 2 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_MASK 0x8u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_HYS_SHIFT 3 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PE_MASK 0x10u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PE_SHIFT 4 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_MASK 0x60u +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_SHIFT 5 +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_SHIFT))&IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_PS_MASK) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_Register_Masks */ + + +/* IOMUXC_LPSR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_LPSR base address */ +#define IOMUXC_LPSR_BASE (0x302C0000u) +/** Peripheral IOMUXC_LPSR base pointer */ +#define IOMUXC_LPSR ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE) +#define IOMUXC_LPSR_BASE_PTR (IOMUXC_LPSR) +/** Array initializer of IOMUXC_LPSR peripheral base adresses */ +#define IOMUXC_LPSR_BASE_ADDRS { IOMUXC_LPSR_BASE } +/** Array initializer of IOMUXC_LPSR peripheral base pointers */ +#define IOMUXC_LPSR_BASE_PTRS { IOMUXC_LPSR } + +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_Register_Accessor_Macros IOMUXC_LPSR - Register accessor macros + * @{ + */ + + +/* IOMUXC_LPSR - Register instance definitions */ +/* IOMUXC_LPSR */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07 IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0 IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1 IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(IOMUXC_LPSR_BASE_PTR) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07 IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(IOMUXC_LPSR_BASE_PTR) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group IOMUXC_LPSR_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type, *KPP_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- KPP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros + * @{ + */ + + +/* KPP - Register accessors */ +#define KPP_KPCR_REG(base) ((base)->KPCR) +#define KPP_KPSR_REG(base) ((base)->KPSR) +#define KPP_KDDR_REG(base) ((base)->KDDR) +#define KPP_KPDR_REG(base) ((base)->KPDR) + +/*! + * @} + */ /* end of group KPP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/* KPCR Bit Fields */ +#define KPP_KPCR_KRE_MASK 0xFFu +#define KPP_KPCR_KRE_SHIFT 0 +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KRE_SHIFT))&KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK 0xFF00u +#define KPP_KPCR_KCO_SHIFT 8 +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPCR_KCO_SHIFT))&KPP_KPCR_KCO_MASK) +/* KPSR Bit Fields */ +#define KPP_KPSR_KPKD_MASK 0x1u +#define KPP_KPSR_KPKD_SHIFT 0 +#define KPP_KPSR_KPKR_MASK 0x2u +#define KPP_KPSR_KPKR_SHIFT 1 +#define KPP_KPSR_KDSC_MASK 0x4u +#define KPP_KPSR_KDSC_SHIFT 2 +#define KPP_KPSR_KRSS_MASK 0x8u +#define KPP_KPSR_KRSS_SHIFT 3 +#define KPP_KPSR_KDIE_MASK 0x100u +#define KPP_KPSR_KDIE_SHIFT 8 +#define KPP_KPSR_KRIE_MASK 0x200u +#define KPP_KPSR_KRIE_SHIFT 9 +/* KDDR Bit Fields */ +#define KPP_KDDR_KRDD_MASK 0xFFu +#define KPP_KDDR_KRDD_SHIFT 0 +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KRDD_SHIFT))&KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK 0xFF00u +#define KPP_KDDR_KCDD_SHIFT 8 +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KDDR_KCDD_SHIFT))&KPP_KDDR_KCDD_MASK) +/* KPDR Bit Fields */ +#define KPP_KPDR_KRD_MASK 0xFFu +#define KPP_KPDR_KRD_SHIFT 0 +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KRD_SHIFT))&KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK 0xFF00u +#define KPP_KPDR_KCD_SHIFT 8 +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x))<<KPP_KPDR_KCD_SHIFT))&KPP_KPDR_KCD_MASK) + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x30320000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +#define KPP_BASE_PTR (KPP) +/** Array initializer of KPP peripheral base adresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } + +/* ---------------------------------------------------------------------------- + -- KPP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Accessor_Macros KPP - Register accessor macros + * @{ + */ + + +/* KPP - Register instance definitions */ +/* KPP */ +#define KPP_KPCR KPP_KPCR_REG(KPP_BASE_PTR) +#define KPP_KPSR KPP_KPSR_REG(KPP_BASE_PTR) +#define KPP_KDDR KPP_KDDR_REG(KPP_BASE_PTR) +#define KPP_KPDR KPP_KPDR_REG(KPP_BASE_PTR) + +/*! + * @} + */ /* end of group KPP_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group KPP_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t RL; /**< eLCDIF General Control Register, offset: 0x0 */ + __IO uint32_t RL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ + __IO uint32_t RL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ + __IO uint32_t RL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __I uint32_t VERSION; /**< LCD Interface Version Register, offset: 0x1C0 */ + uint8_t RESERVED_24[12]; + __I uint32_t DEBUG0; /**< LCD Interface Debug0 Register, offset: 0x1D0 */ + uint8_t RESERVED_25[12]; + __I uint32_t DEBUG1; /**< LCD Interface Debug1 Register, offset: 0x1E0 */ + uint8_t RESERVED_26[12]; + __I uint32_t DEBUG2; /**< LCD Interface Debug2 Register, offset: 0x1F0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_28[12]; + __IO uint32_t AS_CTRL; /**< eLCDIF AS Buffer Control Register, offset: 0x210 */ + uint8_t RESERVED_29[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ + uint8_t RESERVED_30[12]; + __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ + uint8_t RESERVED_31[12]; + __IO uint32_t AS_CLRKEYLOW; /**< eLCDIF Overlay Color Key Low, offset: 0x240 */ + uint8_t RESERVED_32[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< eLCDIF Overlay Color Key High, offset: 0x250 */ + uint8_t RESERVED_33[12]; + __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ + uint8_t RESERVED_34[12]; + __I uint32_t DEBUG3; /**< eLCDIF Interface Debug3 Register, offset: 0x270 */ + uint8_t RESERVED_35[12]; + __I uint32_t DEBUG4; /**< LCD Interface Debug4, offset: 0x280 */ + uint8_t RESERVED_36[12]; + __I uint32_t DEBUG5; /**< LCD Interface Debug5, offset: 0x290 */ +} LCDIF_Type, *LCDIF_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- LCDIF - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros + * @{ + */ + + +/* LCDIF - Register accessors */ +#define LCDIF_RL_REG(base) ((base)->RL) +#define LCDIF_RL_SET_REG(base) ((base)->RL_SET) +#define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) +#define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) +#define LCDIF_CTRL1_REG(base) ((base)->CTRL1) +#define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define LCDIF_CTRL2_REG(base) ((base)->CTRL2) +#define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) +#define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) +#define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) +#define LCDIF_TIMING_REG(base) ((base)->TIMING) +#define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) +#define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) +#define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) +#define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) +#define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) +#define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) +#define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) +#define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) +#define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) +#define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) +#define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) +#define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) +#define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) +#define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) +#define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) +#define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) +#define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) +#define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) +#define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) +#define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) +#define LCDIF_DATA_REG(base) ((base)->DATA) +#define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) +#define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) +#define LCDIF_STAT_REG(base) ((base)->STAT) +#define LCDIF_VERSION_REG(base) ((base)->VERSION) +#define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) +#define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) +#define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) +#define LCDIF_THRES_REG(base) ((base)->THRES) +#define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) +#define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) +#define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) +#define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) +#define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) +#define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) +#define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) +#define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) + +/*! + * @} + */ /* end of group LCDIF_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/* RL Bit Fields */ +#define LCDIF_RL_RUN_MASK 0x1u +#define LCDIF_RL_RUN_SHIFT 0 +#define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_RSRVD0_MASK 0x10u +#define LCDIF_RL_RSRVD0_SHIFT 4 +#define LCDIF_RL_MASTER_MASK 0x20u +#define LCDIF_RL_MASTER_SHIFT 5 +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_WORD_LENGTH_SHIFT))&LCDIF_RL_WORD_LENGTH_MASK) +#define LCDIF_RL_LCD_DATABUS_WIDTH_MASK 0xC00u +#define LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT 10 +#define LCDIF_RL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_RL_CSC_DATA_SWIZZLE_MASK 0x3000u +#define LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT 12 +#define LCDIF_RL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_RL_INPUT_DATA_SWIZZLE_MASK 0xC000u +#define LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT 14 +#define LCDIF_RL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_RL_DATA_SELECT_MASK 0x10000u +#define LCDIF_RL_DATA_SELECT_SHIFT 16 +#define LCDIF_RL_DOTCLK_MODE_MASK 0x20000u +#define LCDIF_RL_DOTCLK_MODE_SHIFT 17 +#define LCDIF_RL_VSYNC_MODE_MASK 0x40000u +#define LCDIF_RL_VSYNC_MODE_SHIFT 18 +#define LCDIF_RL_BYPASS_COUNT_MASK 0x80000u +#define LCDIF_RL_BYPASS_COUNT_SHIFT 19 +#define LCDIF_RL_DVI_MODE_MASK 0x100000u +#define LCDIF_RL_DVI_MODE_SHIFT 20 +#define LCDIF_RL_SHIFT_NUM_BITS_MASK 0x3E00000u +#define LCDIF_RL_SHIFT_NUM_BITS_SHIFT 21 +#define LCDIF_RL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SHIFT_NUM_BITS_MASK) +#define LCDIF_RL_DATA_SHIFT_DIR_MASK 0x4000000u +#define LCDIF_RL_DATA_SHIFT_DIR_SHIFT 26 +#define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u +#define LCDIF_RL_WAIT_FOR_VSYNC_EDGE_SHIFT 27 +#define LCDIF_RL_READ_WRITEB_MASK 0x10000000u +#define LCDIF_RL_READ_WRITEB_SHIFT 28 +#define LCDIF_RL_YCBCR422_INPUT_MASK 0x20000000u +#define LCDIF_RL_YCBCR422_INPUT_SHIFT 29 +#define LCDIF_RL_CLKGATE_MASK 0x40000000u +#define LCDIF_RL_CLKGATE_SHIFT 30 +#define LCDIF_RL_SFTRST_MASK 0x80000000u +#define LCDIF_RL_SFTRST_SHIFT 31 +/* RL_SET Bit Fields */ +#define LCDIF_RL_SET_RUN_MASK 0x1u +#define LCDIF_RL_SET_RUN_SHIFT 0 +#define LCDIF_RL_SET_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_SET_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_SET_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_SET_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_SET_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_SET_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_SET_RSRVD0_MASK 0x10u +#define LCDIF_RL_SET_RSRVD0_SHIFT 4 +#define LCDIF_RL_SET_MASTER_MASK 0x20u +#define LCDIF_RL_SET_MASTER_SHIFT 5 +#define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_SET_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_SET_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_SET_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_SET_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_WORD_LENGTH_SHIFT))&LCDIF_RL_SET_WORD_LENGTH_MASK) +#define LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK 0xC00u +#define LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT 10 +#define LCDIF_RL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK 0x3000u +#define LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT 12 +#define LCDIF_RL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK 0xC000u +#define LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT 14 +#define LCDIF_RL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_RL_SET_DATA_SELECT_MASK 0x10000u +#define LCDIF_RL_SET_DATA_SELECT_SHIFT 16 +#define LCDIF_RL_SET_DOTCLK_MODE_MASK 0x20000u +#define LCDIF_RL_SET_DOTCLK_MODE_SHIFT 17 +#define LCDIF_RL_SET_VSYNC_MODE_MASK 0x40000u +#define LCDIF_RL_SET_VSYNC_MODE_SHIFT 18 +#define LCDIF_RL_SET_BYPASS_COUNT_MASK 0x80000u +#define LCDIF_RL_SET_BYPASS_COUNT_SHIFT 19 +#define LCDIF_RL_SET_DVI_MODE_MASK 0x100000u +#define LCDIF_RL_SET_DVI_MODE_SHIFT 20 +#define LCDIF_RL_SET_SHIFT_NUM_BITS_MASK 0x3E00000u +#define LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT 21 +#define LCDIF_RL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_SET_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_RL_SET_DATA_SHIFT_DIR_MASK 0x4000000u +#define LCDIF_RL_SET_DATA_SHIFT_DIR_SHIFT 26 +#define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u +#define LCDIF_RL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT 27 +#define LCDIF_RL_SET_READ_WRITEB_MASK 0x10000000u +#define LCDIF_RL_SET_READ_WRITEB_SHIFT 28 +#define LCDIF_RL_SET_YCBCR422_INPUT_MASK 0x20000000u +#define LCDIF_RL_SET_YCBCR422_INPUT_SHIFT 29 +#define LCDIF_RL_SET_CLKGATE_MASK 0x40000000u +#define LCDIF_RL_SET_CLKGATE_SHIFT 30 +#define LCDIF_RL_SET_SFTRST_MASK 0x80000000u +#define LCDIF_RL_SET_SFTRST_SHIFT 31 +/* RL_CLR Bit Fields */ +#define LCDIF_RL_CLR_RUN_MASK 0x1u +#define LCDIF_RL_CLR_RUN_SHIFT 0 +#define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_CLR_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_CLR_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_CLR_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_CLR_RSRVD0_MASK 0x10u +#define LCDIF_RL_CLR_RSRVD0_SHIFT 4 +#define LCDIF_RL_CLR_MASTER_MASK 0x20u +#define LCDIF_RL_CLR_MASTER_SHIFT 5 +#define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_CLR_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_CLR_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_CLR_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_WORD_LENGTH_SHIFT))&LCDIF_RL_CLR_WORD_LENGTH_MASK) +#define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK 0xC00u +#define LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT 10 +#define LCDIF_RL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK 0x3000u +#define LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT 12 +#define LCDIF_RL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK 0xC000u +#define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT 14 +#define LCDIF_RL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_RL_CLR_DATA_SELECT_MASK 0x10000u +#define LCDIF_RL_CLR_DATA_SELECT_SHIFT 16 +#define LCDIF_RL_CLR_DOTCLK_MODE_MASK 0x20000u +#define LCDIF_RL_CLR_DOTCLK_MODE_SHIFT 17 +#define LCDIF_RL_CLR_VSYNC_MODE_MASK 0x40000u +#define LCDIF_RL_CLR_VSYNC_MODE_SHIFT 18 +#define LCDIF_RL_CLR_BYPASS_COUNT_MASK 0x80000u +#define LCDIF_RL_CLR_BYPASS_COUNT_SHIFT 19 +#define LCDIF_RL_CLR_DVI_MODE_MASK 0x100000u +#define LCDIF_RL_CLR_DVI_MODE_SHIFT 20 +#define LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK 0x3E00000u +#define LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT 21 +#define LCDIF_RL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_CLR_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_RL_CLR_DATA_SHIFT_DIR_MASK 0x4000000u +#define LCDIF_RL_CLR_DATA_SHIFT_DIR_SHIFT 26 +#define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u +#define LCDIF_RL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT 27 +#define LCDIF_RL_CLR_READ_WRITEB_MASK 0x10000000u +#define LCDIF_RL_CLR_READ_WRITEB_SHIFT 28 +#define LCDIF_RL_CLR_YCBCR422_INPUT_MASK 0x20000000u +#define LCDIF_RL_CLR_YCBCR422_INPUT_SHIFT 29 +#define LCDIF_RL_CLR_CLKGATE_MASK 0x40000000u +#define LCDIF_RL_CLR_CLKGATE_SHIFT 30 +#define LCDIF_RL_CLR_SFTRST_MASK 0x80000000u +#define LCDIF_RL_CLR_SFTRST_SHIFT 31 +/* RL_TOG Bit Fields */ +#define LCDIF_RL_TOG_RUN_MASK 0x1u +#define LCDIF_RL_TOG_RUN_SHIFT 0 +#define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_TOG_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_TOG_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_TOG_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_TOG_RSRVD0_MASK 0x10u +#define LCDIF_RL_TOG_RSRVD0_SHIFT 4 +#define LCDIF_RL_TOG_MASTER_MASK 0x20u +#define LCDIF_RL_TOG_MASTER_SHIFT 5 +#define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_TOG_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_TOG_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_TOG_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_WORD_LENGTH_SHIFT))&LCDIF_RL_TOG_WORD_LENGTH_MASK) +#define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK 0xC00u +#define LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT 10 +#define LCDIF_RL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_LCD_DATABUS_WIDTH_SHIFT))&LCDIF_RL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK 0x3000u +#define LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT 12 +#define LCDIF_RL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_CSC_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK 0xC000u +#define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT 14 +#define LCDIF_RL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_RL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_RL_TOG_DATA_SELECT_MASK 0x10000u +#define LCDIF_RL_TOG_DATA_SELECT_SHIFT 16 +#define LCDIF_RL_TOG_DOTCLK_MODE_MASK 0x20000u +#define LCDIF_RL_TOG_DOTCLK_MODE_SHIFT 17 +#define LCDIF_RL_TOG_VSYNC_MODE_MASK 0x40000u +#define LCDIF_RL_TOG_VSYNC_MODE_SHIFT 18 +#define LCDIF_RL_TOG_BYPASS_COUNT_MASK 0x80000u +#define LCDIF_RL_TOG_BYPASS_COUNT_SHIFT 19 +#define LCDIF_RL_TOG_DVI_MODE_MASK 0x100000u +#define LCDIF_RL_TOG_DVI_MODE_SHIFT 20 +#define LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK 0x3E00000u +#define LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT 21 +#define LCDIF_RL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_RL_TOG_SHIFT_NUM_BITS_SHIFT))&LCDIF_RL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_RL_TOG_DATA_SHIFT_DIR_MASK 0x4000000u +#define LCDIF_RL_TOG_DATA_SHIFT_DIR_SHIFT 26 +#define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_MASK 0x8000000u +#define LCDIF_RL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT 27 +#define LCDIF_RL_TOG_READ_WRITEB_MASK 0x10000000u +#define LCDIF_RL_TOG_READ_WRITEB_SHIFT 28 +#define LCDIF_RL_TOG_YCBCR422_INPUT_MASK 0x20000000u +#define LCDIF_RL_TOG_YCBCR422_INPUT_SHIFT 29 +#define LCDIF_RL_TOG_CLKGATE_MASK 0x40000000u +#define LCDIF_RL_TOG_CLKGATE_SHIFT 30 +#define LCDIF_RL_TOG_SFTRST_MASK 0x80000000u +#define LCDIF_RL_TOG_SFTRST_SHIFT 31 +/* CTRL1 Bit Fields */ +#define LCDIF_CTRL1_RESET_MASK 0x1u +#define LCDIF_CTRL1_RESET_SHIFT 0 +#define LCDIF_CTRL1_MODE86_MASK 0x2u +#define LCDIF_CTRL1_MODE86_SHIFT 1 +#define LCDIF_CTRL1_BUSY_ENABLE_MASK 0x4u +#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT 2 +#define LCDIF_CTRL1_RSRVD0_MASK 0xF8u +#define LCDIF_CTRL1_RSRVD0_SHIFT 3 +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD0_SHIFT))&LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK 0x100u +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT 8 +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK 0x200u +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT 9 +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK 0x400u +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT 10 +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK 0x800u +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT 11 +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK 0x1000u +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT 12 +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK 0x4000u +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT 14 +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK 0x8000u +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT 15 +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK 0xF0000u +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT 16 +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 +#define LCDIF_CTRL1_FIFO_CLEAR_MASK 0x200000u +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT 21 +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK 0x800000u +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT 23 +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK 0x1000000u +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT 24 +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK 0x2000000u +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT 25 +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK 0x4000000u +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT 26 +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK 0x8000000u +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT 27 +#define LCDIF_CTRL1_RSRVD1_MASK 0xF0000000u +#define LCDIF_CTRL1_RSRVD1_SHIFT 28 +#define LCDIF_CTRL1_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_RSRVD1_SHIFT))&LCDIF_CTRL1_RSRVD1_MASK) +/* CTRL1_SET Bit Fields */ +#define LCDIF_CTRL1_SET_RESET_MASK 0x1u +#define LCDIF_CTRL1_SET_RESET_SHIFT 0 +#define LCDIF_CTRL1_SET_MODE86_MASK 0x2u +#define LCDIF_CTRL1_SET_MODE86_SHIFT 1 +#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK 0x4u +#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT 2 +#define LCDIF_CTRL1_SET_RSRVD0_MASK 0xF8u +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT 3 +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD0_SHIFT))&LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK 0x100u +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT 8 +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK 0x200u +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT 9 +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK 0x400u +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT 10 +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK 0x800u +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT 11 +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK 0x1000u +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT 12 +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK 0x4000u +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT 14 +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK 0x8000u +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT 15 +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK 0xF0000u +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT 16 +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK 0x200000u +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT 21 +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK 0x800000u +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT 23 +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK 0x1000000u +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT 24 +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK 0x2000000u +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT 25 +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK 0x4000000u +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT 26 +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK 0x8000000u +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT 27 +#define LCDIF_CTRL1_SET_RSRVD1_MASK 0xF0000000u +#define LCDIF_CTRL1_SET_RSRVD1_SHIFT 28 +#define LCDIF_CTRL1_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_SET_RSRVD1_SHIFT))&LCDIF_CTRL1_SET_RSRVD1_MASK) +/* CTRL1_CLR Bit Fields */ +#define LCDIF_CTRL1_CLR_RESET_MASK 0x1u +#define LCDIF_CTRL1_CLR_RESET_SHIFT 0 +#define LCDIF_CTRL1_CLR_MODE86_MASK 0x2u +#define LCDIF_CTRL1_CLR_MODE86_SHIFT 1 +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK 0x4u +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT 2 +#define LCDIF_CTRL1_CLR_RSRVD0_MASK 0xF8u +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT 3 +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD0_SHIFT))&LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK 0x100u +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT 8 +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK 0x200u +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT 9 +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK 0x400u +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT 10 +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK 0x800u +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT 11 +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK 0x1000u +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT 12 +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK 0x4000u +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT 14 +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK 0x8000u +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT 15 +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK 0xF0000u +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT 16 +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK 0x200000u +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT 21 +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK 0x800000u +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT 23 +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK 0x1000000u +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT 24 +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK 0x2000000u +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT 25 +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK 0x4000000u +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT 26 +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK 0x8000000u +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT 27 +#define LCDIF_CTRL1_CLR_RSRVD1_MASK 0xF0000000u +#define LCDIF_CTRL1_CLR_RSRVD1_SHIFT 28 +#define LCDIF_CTRL1_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD1_SHIFT))&LCDIF_CTRL1_CLR_RSRVD1_MASK) +/* CTRL1_TOG Bit Fields */ +#define LCDIF_CTRL1_TOG_RESET_MASK 0x1u +#define LCDIF_CTRL1_TOG_RESET_SHIFT 0 +#define LCDIF_CTRL1_TOG_MODE86_MASK 0x2u +#define LCDIF_CTRL1_TOG_MODE86_SHIFT 1 +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK 0x4u +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT 2 +#define LCDIF_CTRL1_TOG_RSRVD0_MASK 0xF8u +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT 3 +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD0_SHIFT))&LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK 0x100u +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT 8 +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK 0x200u +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT 9 +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK 0x400u +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT 10 +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK 0x800u +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT 11 +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK 0x1000u +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT 12 +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK 0x2000u +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT 13 +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK 0x4000u +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT 14 +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK 0x8000u +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT 15 +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK 0xF0000u +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT 16 +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT))&LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK 0x100000u +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT 20 +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK 0x200000u +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT 21 +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK 0x400000u +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT 22 +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK 0x800000u +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT 23 +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK 0x1000000u +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT 24 +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK 0x2000000u +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT 25 +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK 0x4000000u +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT 26 +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK 0x8000000u +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT 27 +#define LCDIF_CTRL1_TOG_RSRVD1_MASK 0xF0000000u +#define LCDIF_CTRL1_TOG_RSRVD1_SHIFT 28 +#define LCDIF_CTRL1_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_TOG_RSRVD1_SHIFT))&LCDIF_CTRL1_TOG_RSRVD1_MASK) +/* CTRL2 Bit Fields */ +#define LCDIF_CTRL2_RSRVD0_MASK 0x1u +#define LCDIF_CTRL2_RSRVD0_SHIFT 0 +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK 0xEu +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT 1 +#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_RSRVD1_MASK 0x80u +#define LCDIF_CTRL2_RSRVD1_SHIFT 7 +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK 0x100u +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT 8 +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 +#define LCDIF_CTRL2_READ_PACK_DIR_MASK 0x400u +#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT 10 +#define LCDIF_CTRL2_RSRVD2_MASK 0x800u +#define LCDIF_CTRL2_RSRVD2_SHIFT 11 +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK 0x7000u +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT 12 +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK 0x8000u +#define LCDIF_CTRL2_RSRVD3_SHIFT 15 +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK 0x70000u +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT 16 +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK 0x80000u +#define LCDIF_CTRL2_RSRVD4_SHIFT 19 +#define LCDIF_CTRL2_BURST_LEN_8_MASK 0x100000u +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT 20 +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK 0xE00000u +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT 21 +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK 0xFF000000u +#define LCDIF_CTRL2_RSRVD5_SHIFT 24 +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_RSRVD5_SHIFT))&LCDIF_CTRL2_RSRVD5_MASK) +/* CTRL2_SET Bit Fields */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK 0x1u +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT 0 +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK 0xEu +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT 1 +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_SET_RSRVD1_MASK 0x80u +#define LCDIF_CTRL2_SET_RSRVD1_SHIFT 7 +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK 0x100u +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT 8 +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 +#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK 0x400u +#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT 10 +#define LCDIF_CTRL2_SET_RSRVD2_MASK 0x800u +#define LCDIF_CTRL2_SET_RSRVD2_SHIFT 11 +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK 0x7000u +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT 12 +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK 0x8000u +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT 15 +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK 0x70000u +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT 16 +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK 0x80000u +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT 19 +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK 0x100000u +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT 20 +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK 0xE00000u +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT 21 +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK 0xFF000000u +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT 24 +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_SET_RSRVD5_SHIFT))&LCDIF_CTRL2_SET_RSRVD5_MASK) +/* CTRL2_CLR Bit Fields */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK 0x1u +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT 0 +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK 0xEu +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT 1 +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD1_MASK 0x80u +#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT 7 +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK 0x100u +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT 8 +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK 0x400u +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT 10 +#define LCDIF_CTRL2_CLR_RSRVD2_MASK 0x800u +#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT 11 +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK 0x7000u +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT 12 +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK 0x8000u +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT 15 +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK 0x70000u +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT 16 +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK 0x80000u +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT 19 +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK 0x100000u +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT 20 +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK 0xE00000u +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT 21 +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK 0xFF000000u +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT 24 +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_CLR_RSRVD5_SHIFT))&LCDIF_CTRL2_CLR_RSRVD5_MASK) +/* CTRL2_TOG Bit Fields */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK 0x1u +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT 0 +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK 0xEu +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT 1 +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT))&LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK 0x70u +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT 4 +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT))&LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD1_MASK 0x80u +#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT 7 +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK 0x100u +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT 8 +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK 0x200u +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT 9 +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK 0x400u +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT 10 +#define LCDIF_CTRL2_TOG_RSRVD2_MASK 0x800u +#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT 11 +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK 0x7000u +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT 12 +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK 0x8000u +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT 15 +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK 0x70000u +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT 16 +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT))&LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK 0x80000u +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT 19 +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK 0x100000u +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT 20 +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK 0xE00000u +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT 21 +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT))&LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK 0xFF000000u +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT 24 +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_RSRVD5_SHIFT))&LCDIF_CTRL2_TOG_RSRVD5_MASK) +/* TRANSFER_COUNT Bit Fields */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK 0xFFFFu +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT 0 +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK 0xFFFF0000u +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT 16 +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT))&LCDIF_TRANSFER_COUNT_V_COUNT_MASK) +/* CUR_BUF Bit Fields */ +#define LCDIF_CUR_BUF_ADDR_MASK 0xFFFFFFFFu +#define LCDIF_CUR_BUF_ADDR_SHIFT 0 +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CUR_BUF_ADDR_SHIFT))&LCDIF_CUR_BUF_ADDR_MASK) +/* NEXT_BUF Bit Fields */ +#define LCDIF_NEXT_BUF_ADDR_MASK 0xFFFFFFFFu +#define LCDIF_NEXT_BUF_ADDR_SHIFT 0 +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_NEXT_BUF_ADDR_SHIFT))&LCDIF_NEXT_BUF_ADDR_MASK) +/* TIMING Bit Fields */ +#define LCDIF_TIMING_DATA_SETUP_MASK 0xFFu +#define LCDIF_TIMING_DATA_SETUP_SHIFT 0 +#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_SETUP_SHIFT))&LCDIF_TIMING_DATA_SETUP_MASK) +#define LCDIF_TIMING_DATA_HOLD_MASK 0xFF00u +#define LCDIF_TIMING_DATA_HOLD_SHIFT 8 +#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_DATA_HOLD_SHIFT))&LCDIF_TIMING_DATA_HOLD_MASK) +#define LCDIF_TIMING_CMD_SETUP_MASK 0xFF0000u +#define LCDIF_TIMING_CMD_SETUP_SHIFT 16 +#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_SETUP_SHIFT))&LCDIF_TIMING_CMD_SETUP_MASK) +#define LCDIF_TIMING_CMD_HOLD_MASK 0xFF000000u +#define LCDIF_TIMING_CMD_HOLD_SHIFT 24 +#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_TIMING_CMD_HOLD_SHIFT))&LCDIF_TIMING_CMD_HOLD_MASK) +/* VDCTRL0 Bit Fields */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT 0 +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK 0x40000u +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT 18 +#define LCDIF_VDCTRL0_HALF_LINE_MASK 0x80000u +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT 19 +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK 0x200000u +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT 21 +#define LCDIF_VDCTRL0_RSRVD1_MASK 0xC00000u +#define LCDIF_VDCTRL0_RSRVD1_SHIFT 22 +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD1_SHIFT))&LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK 0x1000000u +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT 24 +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK 0x2000000u +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT 25 +#define LCDIF_VDCTRL0_HSYNC_POL_MASK 0x4000000u +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT 26 +#define LCDIF_VDCTRL0_VSYNC_POL_MASK 0x8000000u +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT 27 +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK 0x10000000u +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT 28 +#define LCDIF_VDCTRL0_VSYNC_OEB_MASK 0x20000000u +#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT 29 +#define LCDIF_VDCTRL0_RSRVD2_MASK 0xC0000000u +#define LCDIF_VDCTRL0_RSRVD2_SHIFT 30 +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_RSRVD2_SHIFT))&LCDIF_VDCTRL0_RSRVD2_MASK) +/* VDCTRL0_SET Bit Fields */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT 0 +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK 0x40000u +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT 18 +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK 0x80000u +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT 19 +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK 0x200000u +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT 21 +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK 0xC00000u +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT 22 +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD1_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK 0x1000000u +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT 24 +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK 0x2000000u +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT 25 +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK 0x4000000u +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT 26 +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK 0x8000000u +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT 27 +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK 0x10000000u +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT 28 +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK 0x20000000u +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT 29 +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK 0xC0000000u +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT 30 +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_SET_RSRVD2_SHIFT))&LCDIF_VDCTRL0_SET_RSRVD2_MASK) +/* VDCTRL0_CLR Bit Fields */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT 0 +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK 0x40000u +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT 18 +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK 0x80000u +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT 19 +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK 0x200000u +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT 21 +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK 0xC00000u +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT 22 +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK 0x1000000u +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT 24 +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK 0x2000000u +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT 25 +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK 0x4000000u +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT 26 +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK 0x8000000u +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT 27 +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK 0x10000000u +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT 28 +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK 0x20000000u +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT 29 +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK 0xC0000000u +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT 30 +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT))&LCDIF_VDCTRL0_CLR_RSRVD2_MASK) +/* VDCTRL0_TOG Bit Fields */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK 0x3FFFFu +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT 0 +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK 0x40000u +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT 18 +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK 0x80000u +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT 19 +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK 0x100000u +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT 20 +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK 0x200000u +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT 21 +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK 0xC00000u +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT 22 +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK 0x1000000u +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT 24 +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK 0x2000000u +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT 25 +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK 0x4000000u +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT 26 +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK 0x8000000u +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT 27 +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK 0x10000000u +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT 28 +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK 0x20000000u +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT 29 +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK 0xC0000000u +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT 30 +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT))&LCDIF_VDCTRL0_TOG_RSRVD2_MASK) +/* VDCTRL1 Bit Fields */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xFFFFFFFFu +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT 0 +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) +/* VDCTRL2 Bit Fields */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3FFFFu +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT 0 +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT))&LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK 0xFFFC0000u +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT 18 +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT))&LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) +/* VDCTRL3 Bit Fields */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK 0xFFFFu +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT 0 +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK 0xFFF0000u +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT 16 +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT))&LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK 0x10000000u +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT 28 +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK 0x20000000u +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT 29 +#define LCDIF_VDCTRL3_RSRVD0_MASK 0xC0000000u +#define LCDIF_VDCTRL3_RSRVD0_SHIFT 30 +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_RSRVD0_SHIFT))&LCDIF_VDCTRL3_RSRVD0_MASK) +/* VDCTRL4 Bit Fields */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3FFFFu +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT 0 +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT))&LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK 0x40000u +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT 18 +#define LCDIF_VDCTRL4_RSRVD0_MASK 0x1FF80000u +#define LCDIF_VDCTRL4_RSRVD0_SHIFT 19 +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_RSRVD0_SHIFT))&LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK 0xE0000000u +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT 29 +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT))&LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) +/* DVICTRL0 Bit Fields */ +#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK 0xFFFu +#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT 0 +#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT))&LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD0_MASK 0xF000u +#define LCDIF_DVICTRL0_RSRVD0_SHIFT 12 +#define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD0_SHIFT))&LCDIF_DVICTRL0_RSRVD0_MASK) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK 0xFFF0000u +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT 16 +#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT))&LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD1_MASK 0xF0000000u +#define LCDIF_DVICTRL0_RSRVD1_SHIFT 28 +#define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL0_RSRVD1_SHIFT))&LCDIF_DVICTRL0_RSRVD1_MASK) +/* DVICTRL1 Bit Fields */ +#define LCDIF_DVICTRL1_F2_START_LINE_MASK 0x3FFu +#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT 0 +#define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F2_START_LINE_SHIFT))&LCDIF_DVICTRL1_F2_START_LINE_MASK) +#define LCDIF_DVICTRL1_F1_END_LINE_MASK 0xFFC00u +#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT 10 +#define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_END_LINE_SHIFT))&LCDIF_DVICTRL1_F1_END_LINE_MASK) +#define LCDIF_DVICTRL1_F1_START_LINE_MASK 0x3FF00000u +#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT 20 +#define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_F1_START_LINE_SHIFT))&LCDIF_DVICTRL1_F1_START_LINE_MASK) +#define LCDIF_DVICTRL1_RSRVD0_MASK 0xC0000000u +#define LCDIF_DVICTRL1_RSRVD0_SHIFT 30 +#define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL1_RSRVD0_SHIFT))&LCDIF_DVICTRL1_RSRVD0_MASK) +/* DVICTRL2 Bit Fields */ +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK 0x3FFu +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT 0 +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK 0xFFC00u +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT 10 +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL2_F2_END_LINE_MASK 0x3FF00000u +#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT 20 +#define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_F2_END_LINE_SHIFT))&LCDIF_DVICTRL2_F2_END_LINE_MASK) +#define LCDIF_DVICTRL2_RSRVD0_MASK 0xC0000000u +#define LCDIF_DVICTRL2_RSRVD0_SHIFT 30 +#define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL2_RSRVD0_SHIFT))&LCDIF_DVICTRL2_RSRVD0_MASK) +/* DVICTRL3 Bit Fields */ +#define LCDIF_DVICTRL3_V_LINES_CNT_MASK 0x3FFu +#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT 0 +#define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V_LINES_CNT_SHIFT))&LCDIF_DVICTRL3_V_LINES_CNT_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK 0xFFC00u +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT 10 +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK 0x3FF00000u +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT 20 +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT))&LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL3_RSRVD0_MASK 0xC0000000u +#define LCDIF_DVICTRL3_RSRVD0_SHIFT 30 +#define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL3_RSRVD0_SHIFT))&LCDIF_DVICTRL3_RSRVD0_MASK) +/* DVICTRL4 Bit Fields */ +#define LCDIF_DVICTRL4_H_FILL_CNT_MASK 0xFFu +#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT 0 +#define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_H_FILL_CNT_SHIFT))&LCDIF_DVICTRL4_H_FILL_CNT_MASK) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK 0xFF00u +#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT 8 +#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK 0xFF0000u +#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT 16 +#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK 0xFF000000u +#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT 24 +#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT))&LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) +/* CSC_COEFF0 Bit Fields */ +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK 0x3u +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT 0 +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT))&LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) +#define LCDIF_CSC_COEFF0_RSRVD0_MASK 0xFFFCu +#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT 2 +#define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD0_SHIFT))&LCDIF_CSC_COEFF0_RSRVD0_MASK) +#define LCDIF_CSC_COEFF0_C0_MASK 0x3FF0000u +#define LCDIF_CSC_COEFF0_C0_SHIFT 16 +#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_C0_SHIFT))&LCDIF_CSC_COEFF0_C0_MASK) +#define LCDIF_CSC_COEFF0_RSRVD1_MASK 0xFC000000u +#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT 26 +#define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF0_RSRVD1_SHIFT))&LCDIF_CSC_COEFF0_RSRVD1_MASK) +/* CSC_COEFF1 Bit Fields */ +#define LCDIF_CSC_COEFF1_C1_MASK 0x3FFu +#define LCDIF_CSC_COEFF1_C1_SHIFT 0 +#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C1_SHIFT))&LCDIF_CSC_COEFF1_C1_MASK) +#define LCDIF_CSC_COEFF1_RSRVD0_MASK 0xFC00u +#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT 10 +#define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD0_SHIFT))&LCDIF_CSC_COEFF1_RSRVD0_MASK) +#define LCDIF_CSC_COEFF1_C2_MASK 0x3FF0000u +#define LCDIF_CSC_COEFF1_C2_SHIFT 16 +#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_C2_SHIFT))&LCDIF_CSC_COEFF1_C2_MASK) +#define LCDIF_CSC_COEFF1_RSRVD1_MASK 0xFC000000u +#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT 26 +#define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF1_RSRVD1_SHIFT))&LCDIF_CSC_COEFF1_RSRVD1_MASK) +/* CSC_COEFF2 Bit Fields */ +#define LCDIF_CSC_COEFF2_C3_MASK 0x3FFu +#define LCDIF_CSC_COEFF2_C3_SHIFT 0 +#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C3_SHIFT))&LCDIF_CSC_COEFF2_C3_MASK) +#define LCDIF_CSC_COEFF2_RSRVD0_MASK 0xFC00u +#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT 10 +#define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD0_SHIFT))&LCDIF_CSC_COEFF2_RSRVD0_MASK) +#define LCDIF_CSC_COEFF2_C4_MASK 0x3FF0000u +#define LCDIF_CSC_COEFF2_C4_SHIFT 16 +#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_C4_SHIFT))&LCDIF_CSC_COEFF2_C4_MASK) +#define LCDIF_CSC_COEFF2_RSRVD1_MASK 0xFC000000u +#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT 26 +#define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF2_RSRVD1_SHIFT))&LCDIF_CSC_COEFF2_RSRVD1_MASK) +/* CSC_COEFF3 Bit Fields */ +#define LCDIF_CSC_COEFF3_C5_MASK 0x3FFu +#define LCDIF_CSC_COEFF3_C5_SHIFT 0 +#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C5_SHIFT))&LCDIF_CSC_COEFF3_C5_MASK) +#define LCDIF_CSC_COEFF3_RSRVD0_MASK 0xFC00u +#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT 10 +#define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD0_SHIFT))&LCDIF_CSC_COEFF3_RSRVD0_MASK) +#define LCDIF_CSC_COEFF3_C6_MASK 0x3FF0000u +#define LCDIF_CSC_COEFF3_C6_SHIFT 16 +#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_C6_SHIFT))&LCDIF_CSC_COEFF3_C6_MASK) +#define LCDIF_CSC_COEFF3_RSRVD1_MASK 0xFC000000u +#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT 26 +#define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF3_RSRVD1_SHIFT))&LCDIF_CSC_COEFF3_RSRVD1_MASK) +/* CSC_COEFF4 Bit Fields */ +#define LCDIF_CSC_COEFF4_C7_MASK 0x3FFu +#define LCDIF_CSC_COEFF4_C7_SHIFT 0 +#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C7_SHIFT))&LCDIF_CSC_COEFF4_C7_MASK) +#define LCDIF_CSC_COEFF4_RSRVD0_MASK 0xFC00u +#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT 10 +#define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD0_SHIFT))&LCDIF_CSC_COEFF4_RSRVD0_MASK) +#define LCDIF_CSC_COEFF4_C8_MASK 0x3FF0000u +#define LCDIF_CSC_COEFF4_C8_SHIFT 16 +#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_C8_SHIFT))&LCDIF_CSC_COEFF4_C8_MASK) +#define LCDIF_CSC_COEFF4_RSRVD1_MASK 0xFC000000u +#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT 26 +#define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_COEFF4_RSRVD1_SHIFT))&LCDIF_CSC_COEFF4_RSRVD1_MASK) +/* CSC_OFFSET Bit Fields */ +#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK 0x1FFu +#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT 0 +#define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_Y_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD0_MASK 0xFE00u +#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT 9 +#define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD0_SHIFT))&LCDIF_CSC_OFFSET_RSRVD0_MASK) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK 0x1FF0000u +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT 16 +#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT))&LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD1_MASK 0xFE000000u +#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT 25 +#define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_OFFSET_RSRVD1_SHIFT))&LCDIF_CSC_OFFSET_RSRVD1_MASK) +/* CSC_LIMIT Bit Fields */ +#define LCDIF_CSC_LIMIT_Y_MAX_MASK 0xFFu +#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT 0 +#define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MAX_SHIFT))&LCDIF_CSC_LIMIT_Y_MAX_MASK) +#define LCDIF_CSC_LIMIT_Y_MIN_MASK 0xFF00u +#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT 8 +#define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_Y_MIN_SHIFT))&LCDIF_CSC_LIMIT_Y_MIN_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK 0xFF0000u +#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT 16 +#define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MAX_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK 0xFF000000u +#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT 24 +#define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT))&LCDIF_CSC_LIMIT_CBCR_MIN_MASK) +/* DATA Bit Fields */ +#define LCDIF_DATA_DATA_ZERO_MASK 0xFFu +#define LCDIF_DATA_DATA_ZERO_SHIFT 0 +#define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ZERO_SHIFT))&LCDIF_DATA_DATA_ZERO_MASK) +#define LCDIF_DATA_DATA_ONE_MASK 0xFF00u +#define LCDIF_DATA_DATA_ONE_SHIFT 8 +#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_ONE_SHIFT))&LCDIF_DATA_DATA_ONE_MASK) +#define LCDIF_DATA_DATA_TWO_MASK 0xFF0000u +#define LCDIF_DATA_DATA_TWO_SHIFT 16 +#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_TWO_SHIFT))&LCDIF_DATA_DATA_TWO_MASK) +#define LCDIF_DATA_DATA_THREE_MASK 0xFF000000u +#define LCDIF_DATA_DATA_THREE_SHIFT 24 +#define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DATA_DATA_THREE_SHIFT))&LCDIF_DATA_DATA_THREE_MASK) +/* BM_ERROR_STAT Bit Fields */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK 0xFFFFFFFFu +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT 0 +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_BM_ERROR_STAT_ADDR_SHIFT))&LCDIF_BM_ERROR_STAT_ADDR_MASK) +/* CRC_STAT Bit Fields */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK 0xFFFFFFFFu +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT 0 +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_CRC_STAT_CRC_VALUE_SHIFT))&LCDIF_CRC_STAT_CRC_VALUE_MASK) +/* STAT Bit Fields */ +#define LCDIF_STAT_LFIFO_COUNT_MASK 0x1FFu +#define LCDIF_STAT_LFIFO_COUNT_SHIFT 0 +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_LFIFO_COUNT_SHIFT))&LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK 0xFFFE00u +#define LCDIF_STAT_RSRVD0_SHIFT 9 +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_STAT_RSRVD0_SHIFT))&LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK 0x1000000u +#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT 24 +#define LCDIF_STAT_BUSY_MASK 0x2000000u +#define LCDIF_STAT_BUSY_SHIFT 25 +#define LCDIF_STAT_TXFIFO_EMPTY_MASK 0x4000000u +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT 26 +#define LCDIF_STAT_TXFIFO_FULL_MASK 0x8000000u +#define LCDIF_STAT_TXFIFO_FULL_SHIFT 27 +#define LCDIF_STAT_LFIFO_EMPTY_MASK 0x10000000u +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT 28 +#define LCDIF_STAT_LFIFO_FULL_MASK 0x20000000u +#define LCDIF_STAT_LFIFO_FULL_SHIFT 29 +#define LCDIF_STAT_PRESENT_MASK 0x80000000u +#define LCDIF_STAT_PRESENT_SHIFT 31 +/* VERSION Bit Fields */ +#define LCDIF_VERSION_STEP_MASK 0xFFFFu +#define LCDIF_VERSION_STEP_SHIFT 0 +#define LCDIF_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_STEP_SHIFT))&LCDIF_VERSION_STEP_MASK) +#define LCDIF_VERSION_MINOR_MASK 0xFF0000u +#define LCDIF_VERSION_MINOR_SHIFT 16 +#define LCDIF_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MINOR_SHIFT))&LCDIF_VERSION_MINOR_MASK) +#define LCDIF_VERSION_MAJOR_MASK 0xFF000000u +#define LCDIF_VERSION_MAJOR_SHIFT 24 +#define LCDIF_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_VERSION_MAJOR_SHIFT))&LCDIF_VERSION_MAJOR_MASK) +/* DEBUG0 Bit Fields */ +#define LCDIF_DEBUG0_MST_WORDS_MASK 0xFu +#define LCDIF_DEBUG0_MST_WORDS_SHIFT 0 +#define LCDIF_DEBUG0_MST_WORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_WORDS_SHIFT))&LCDIF_DEBUG0_MST_WORDS_MASK) +#define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK 0x1F0u +#define LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT 4 +#define LCDIF_DEBUG0_MST_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG0_MST_OUTSTANDING_REQS_MASK) +#define LCDIF_DEBUG0_MST_AVALID_MASK 0x200u +#define LCDIF_DEBUG0_MST_AVALID_SHIFT 9 +#define LCDIF_DEBUG0_CUR_REQ_STATE_MASK 0xC00u +#define LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT 10 +#define LCDIF_DEBUG0_CUR_REQ_STATE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG0_CUR_REQ_STATE_MASK) +#define LCDIF_DEBUG0_PXP_B1_DONE_MASK 0x1000u +#define LCDIF_DEBUG0_PXP_B1_DONE_SHIFT 12 +#define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_MASK 0x2000u +#define LCDIF_DEBUG0_PXP_LCDIF_B1_READY_SHIFT 13 +#define LCDIF_DEBUG0_PXP_B0_DONE_MASK 0x4000u +#define LCDIF_DEBUG0_PXP_B0_DONE_SHIFT 14 +#define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_MASK 0x8000u +#define LCDIF_DEBUG0_PXP_LCDIF_B0_READY_SHIFT 15 +#define LCDIF_DEBUG0_CUR_STATE_MASK 0x7F0000u +#define LCDIF_DEBUG0_CUR_STATE_SHIFT 16 +#define LCDIF_DEBUG0_CUR_STATE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG0_CUR_STATE_SHIFT))&LCDIF_DEBUG0_CUR_STATE_MASK) +#define LCDIF_DEBUG0_EMPTY_WORD_MASK 0x800000u +#define LCDIF_DEBUG0_EMPTY_WORD_SHIFT 23 +#define LCDIF_DEBUG0_CUR_FRAME_TX_MASK 0x1000000u +#define LCDIF_DEBUG0_CUR_FRAME_TX_SHIFT 24 +#define LCDIF_DEBUG0_VSYNC_MASK 0x2000000u +#define LCDIF_DEBUG0_VSYNC_SHIFT 25 +#define LCDIF_DEBUG0_HSYNC_MASK 0x4000000u +#define LCDIF_DEBUG0_HSYNC_SHIFT 26 +#define LCDIF_DEBUG0_ENABLE_MASK 0x8000000u +#define LCDIF_DEBUG0_ENABLE_SHIFT 27 +#define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_MASK 0x20000000u +#define LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG_SHIFT 29 +#define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_MASK 0x40000000u +#define LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT_SHIFT 30 +#define LCDIF_DEBUG0_STREAMING_END_DETECTED_MASK 0x80000000u +#define LCDIF_DEBUG0_STREAMING_END_DETECTED_SHIFT 31 +/* DEBUG1 Bit Fields */ +#define LCDIF_DEBUG1_V_DATA_COUNT_MASK 0xFFFFu +#define LCDIF_DEBUG1_V_DATA_COUNT_SHIFT 0 +#define LCDIF_DEBUG1_V_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_V_DATA_COUNT_MASK) +#define LCDIF_DEBUG1_H_DATA_COUNT_MASK 0xFFFF0000u +#define LCDIF_DEBUG1_H_DATA_COUNT_SHIFT 16 +#define LCDIF_DEBUG1_H_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG1_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG1_H_DATA_COUNT_MASK) +/* DEBUG2 Bit Fields */ +#define LCDIF_DEBUG2_MST_ADDRESS_MASK 0xFFFFFFFFu +#define LCDIF_DEBUG2_MST_ADDRESS_SHIFT 0 +#define LCDIF_DEBUG2_MST_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG2_MST_ADDRESS_SHIFT))&LCDIF_DEBUG2_MST_ADDRESS_MASK) +/* THRES Bit Fields */ +#define LCDIF_THRES_PANIC_MASK 0x1FFu +#define LCDIF_THRES_PANIC_SHIFT 0 +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_PANIC_SHIFT))&LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK 0xFE00u +#define LCDIF_THRES_RSRVD1_SHIFT 9 +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD1_SHIFT))&LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK 0x1FF0000u +#define LCDIF_THRES_FASTCLOCK_SHIFT 16 +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_FASTCLOCK_SHIFT))&LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK 0xFE000000u +#define LCDIF_THRES_RSRVD2_SHIFT 25 +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_THRES_RSRVD2_SHIFT))&LCDIF_THRES_RSRVD2_MASK) +/* AS_CTRL Bit Fields */ +#define LCDIF_AS_CTRL_AS_ENABLE_MASK 0x1u +#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT 0 +#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK 0x6u +#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT 1 +#define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT))&LCDIF_AS_CTRL_ALPHA_CTRL_MASK) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK 0x8u +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT 3 +#define LCDIF_AS_CTRL_FORMAT_MASK 0xF0u +#define LCDIF_AS_CTRL_FORMAT_SHIFT 4 +#define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_FORMAT_SHIFT))&LCDIF_AS_CTRL_FORMAT_MASK) +#define LCDIF_AS_CTRL_ALPHA_MASK 0xFF00u +#define LCDIF_AS_CTRL_ALPHA_SHIFT 8 +#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ALPHA_SHIFT))&LCDIF_AS_CTRL_ALPHA_MASK) +#define LCDIF_AS_CTRL_ROP_MASK 0xF0000u +#define LCDIF_AS_CTRL_ROP_SHIFT 16 +#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_ROP_SHIFT))&LCDIF_AS_CTRL_ROP_MASK) +#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK 0x100000u +#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT 20 +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK 0x600000u +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT 21 +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT))&LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_AS_CTRL_PS_DISABLE_MASK 0x800000u +#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT 23 +#define LCDIF_AS_CTRL_RVDS1_MASK 0x7000000u +#define LCDIF_AS_CTRL_RVDS1_SHIFT 24 +#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CTRL_RVDS1_SHIFT))&LCDIF_AS_CTRL_RVDS1_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK 0x8000000u +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT 27 +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK 0x10000000u +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT 28 +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK 0x20000000u +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT 29 +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK 0x40000000u +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT 30 +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK 0x80000000u +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT 31 +/* AS_BUF Bit Fields */ +#define LCDIF_AS_BUF_ADDR_MASK 0xFFFFFFFFu +#define LCDIF_AS_BUF_ADDR_SHIFT 0 +#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_BUF_ADDR_SHIFT))&LCDIF_AS_BUF_ADDR_MASK) +/* AS_NEXT_BUF Bit Fields */ +#define LCDIF_AS_NEXT_BUF_ADDR_MASK 0xFFFFFFFFu +#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT 0 +#define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_NEXT_BUF_ADDR_SHIFT))&LCDIF_AS_NEXT_BUF_ADDR_MASK) +/* AS_CLRKEYLOW Bit Fields */ +#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK 0xFFFFFFu +#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT 0 +#define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT))&LCDIF_AS_CLRKEYLOW_PIXEL_MASK) +#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK 0xFF000000u +#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT 24 +#define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT))&LCDIF_AS_CLRKEYLOW_RSVD1_MASK) +/* AS_CLRKEYHIGH Bit Fields */ +#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK 0xFFFFFFu +#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT 0 +#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT))&LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK 0xFF000000u +#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT 24 +#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT))&LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) +/* SYNC_DELAY Bit Fields */ +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK 0xFFFFu +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT 0 +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK 0xFFFF0000u +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT 16 +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT))&LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) +/* DEBUG3 Bit Fields */ +#define LCDIF_DEBUG3_MST_WORDS_MASK 0xFu +#define LCDIF_DEBUG3_MST_WORDS_SHIFT 0 +#define LCDIF_DEBUG3_MST_WORDS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_WORDS_SHIFT))&LCDIF_DEBUG3_MST_WORDS_MASK) +#define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK 0x1F0u +#define LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT 4 +#define LCDIF_DEBUG3_MST_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_MST_OUTSTANDING_REQS_SHIFT))&LCDIF_DEBUG3_MST_OUTSTANDING_REQS_MASK) +#define LCDIF_DEBUG3_MST_AVALID_MASK 0x200u +#define LCDIF_DEBUG3_MST_AVALID_SHIFT 9 +#define LCDIF_DEBUG3_CUR_REQ_STATE_MASK 0xC00u +#define LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT 10 +#define LCDIF_DEBUG3_CUR_REQ_STATE(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_CUR_REQ_STATE_SHIFT))&LCDIF_DEBUG3_CUR_REQ_STATE_MASK) +#define LCDIF_DEBUG3_RSVD0_MASK 0xFFFFF000u +#define LCDIF_DEBUG3_RSVD0_SHIFT 12 +#define LCDIF_DEBUG3_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG3_RSVD0_SHIFT))&LCDIF_DEBUG3_RSVD0_MASK) +/* DEBUG4 Bit Fields */ +#define LCDIF_DEBUG4_V_DATA_COUNT_MASK 0xFFFFu +#define LCDIF_DEBUG4_V_DATA_COUNT_SHIFT 0 +#define LCDIF_DEBUG4_V_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_V_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_V_DATA_COUNT_MASK) +#define LCDIF_DEBUG4_H_DATA_COUNT_MASK 0xFFFF0000u +#define LCDIF_DEBUG4_H_DATA_COUNT_SHIFT 16 +#define LCDIF_DEBUG4_H_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG4_H_DATA_COUNT_SHIFT))&LCDIF_DEBUG4_H_DATA_COUNT_MASK) +/* DEBUG5 Bit Fields */ +#define LCDIF_DEBUG5_MST_ADDRESS_MASK 0xFFFFFFFFu +#define LCDIF_DEBUG5_MST_ADDRESS_SHIFT 0 +#define LCDIF_DEBUG5_MST_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<LCDIF_DEBUG5_MST_ADDRESS_SHIFT))&LCDIF_DEBUG5_MST_ADDRESS_MASK) + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF1 base address */ +#define LCDIF1_BASE (0x30730000u) +/** Peripheral LCDIF1 base pointer */ +#define LCDIF1 ((LCDIF_Type *)LCDIF1_BASE) +#define LCDIF1_BASE_PTR (LCDIF1) +/** Peripheral LCDIF2 base address */ +#define LCDIF2_BASE (0x30734000u) +/** Peripheral LCDIF2 base pointer */ +#define LCDIF2 ((LCDIF_Type *)LCDIF2_BASE) +#define LCDIF2_BASE_PTR (LCDIF2) +/** Array initializer of LCDIF peripheral base adresses */ +#define LCDIF_BASE_ADDRS { LCDIF1_BASE, LCDIF2_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF1, LCDIF2 } + +/* ---------------------------------------------------------------------------- + -- LCDIF - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Accessor_Macros LCDIF - Register accessor macros + * @{ + */ + + +/* LCDIF - Register instance definitions */ +/* LCDIF1 */ +#define LCDIF1_RL LCDIF_RL_REG(LCDIF1_BASE_PTR) +#define LCDIF1_RL_SET LCDIF_RL_SET_REG(LCDIF1_BASE_PTR) +#define LCDIF1_RL_CLR LCDIF_RL_CLR_REG(LCDIF1_BASE_PTR) +#define LCDIF1_RL_TOG LCDIF_RL_TOG_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL1 LCDIF_CTRL1_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL1_SET LCDIF_CTRL1_SET_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL1_CLR LCDIF_CTRL1_CLR_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL1_TOG LCDIF_CTRL1_TOG_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL2 LCDIF_CTRL2_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL2_SET LCDIF_CTRL2_SET_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL2_CLR LCDIF_CTRL2_CLR_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CTRL2_TOG LCDIF_CTRL2_TOG_REG(LCDIF1_BASE_PTR) +#define LCDIF1_TRANSFER_COUNT LCDIF_TRANSFER_COUNT_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CUR_BUF LCDIF_CUR_BUF_REG(LCDIF1_BASE_PTR) +#define LCDIF1_NEXT_BUF LCDIF_NEXT_BUF_REG(LCDIF1_BASE_PTR) +#define LCDIF1_TIMING LCDIF_TIMING_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL0 LCDIF_VDCTRL0_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL0_SET LCDIF_VDCTRL0_SET_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL0_CLR LCDIF_VDCTRL0_CLR_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL0_TOG LCDIF_VDCTRL0_TOG_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL1 LCDIF_VDCTRL1_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL2 LCDIF_VDCTRL2_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL3 LCDIF_VDCTRL3_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VDCTRL4 LCDIF_VDCTRL4_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DVICTRL0 LCDIF_DVICTRL0_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DVICTRL1 LCDIF_DVICTRL1_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DVICTRL2 LCDIF_DVICTRL2_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DVICTRL3 LCDIF_DVICTRL3_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DVICTRL4 LCDIF_DVICTRL4_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CSC_COEFF0 LCDIF_CSC_COEFF0_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CSC_COEFF1 LCDIF_CSC_COEFF1_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CSC_COEFF2 LCDIF_CSC_COEFF2_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CSC_COEFF3 LCDIF_CSC_COEFF3_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CSC_COEFF4 LCDIF_CSC_COEFF4_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CSC_OFFSET LCDIF_CSC_OFFSET_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CSC_LIMIT LCDIF_CSC_LIMIT_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DATA LCDIF_DATA_REG(LCDIF1_BASE_PTR) +#define LCDIF1_BM_ERROR_STAT LCDIF_BM_ERROR_STAT_REG(LCDIF1_BASE_PTR) +#define LCDIF1_CRC_STAT LCDIF_CRC_STAT_REG(LCDIF1_BASE_PTR) +#define LCDIF1_STAT LCDIF_STAT_REG(LCDIF1_BASE_PTR) +#define LCDIF1_VERSION LCDIF_VERSION_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DEBUG0 LCDIF_DEBUG0_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DEBUG1 LCDIF_DEBUG1_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DEBUG2 LCDIF_DEBUG2_REG(LCDIF1_BASE_PTR) +#define LCDIF1_THRES LCDIF_THRES_REG(LCDIF1_BASE_PTR) +#define LCDIF1_AS_CTRL LCDIF_AS_CTRL_REG(LCDIF1_BASE_PTR) +#define LCDIF1_AS_BUF LCDIF_AS_BUF_REG(LCDIF1_BASE_PTR) +#define LCDIF1_AS_NEXT_BUF LCDIF_AS_NEXT_BUF_REG(LCDIF1_BASE_PTR) +#define LCDIF1_AS_CLRKEYLOW LCDIF_AS_CLRKEYLOW_REG(LCDIF1_BASE_PTR) +#define LCDIF1_AS_CLRKEYHIGH LCDIF_AS_CLRKEYHIGH_REG(LCDIF1_BASE_PTR) +#define LCDIF1_SYNC_DELAY LCDIF_SYNC_DELAY_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DEBUG3 LCDIF_DEBUG3_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DEBUG4 LCDIF_DEBUG4_REG(LCDIF1_BASE_PTR) +#define LCDIF1_DEBUG5 LCDIF_DEBUG5_REG(LCDIF1_BASE_PTR) +/* LCDIF2 */ +#define LCDIF2_RL LCDIF_RL_REG(LCDIF2_BASE_PTR) +#define LCDIF2_RL_SET LCDIF_RL_SET_REG(LCDIF2_BASE_PTR) +#define LCDIF2_RL_CLR LCDIF_RL_CLR_REG(LCDIF2_BASE_PTR) +#define LCDIF2_RL_TOG LCDIF_RL_TOG_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL1 LCDIF_CTRL1_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL1_SET LCDIF_CTRL1_SET_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL1_CLR LCDIF_CTRL1_CLR_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL1_TOG LCDIF_CTRL1_TOG_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL2 LCDIF_CTRL2_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL2_SET LCDIF_CTRL2_SET_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL2_CLR LCDIF_CTRL2_CLR_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CTRL2_TOG LCDIF_CTRL2_TOG_REG(LCDIF2_BASE_PTR) +#define LCDIF2_TRANSFER_COUNT LCDIF_TRANSFER_COUNT_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CUR_BUF LCDIF_CUR_BUF_REG(LCDIF2_BASE_PTR) +#define LCDIF2_NEXT_BUF LCDIF_NEXT_BUF_REG(LCDIF2_BASE_PTR) +#define LCDIF2_TIMING LCDIF_TIMING_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL0 LCDIF_VDCTRL0_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL0_SET LCDIF_VDCTRL0_SET_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL0_CLR LCDIF_VDCTRL0_CLR_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL0_TOG LCDIF_VDCTRL0_TOG_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL1 LCDIF_VDCTRL1_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL2 LCDIF_VDCTRL2_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL3 LCDIF_VDCTRL3_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VDCTRL4 LCDIF_VDCTRL4_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DVICTRL0 LCDIF_DVICTRL0_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DVICTRL1 LCDIF_DVICTRL1_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DVICTRL2 LCDIF_DVICTRL2_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DVICTRL3 LCDIF_DVICTRL3_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DVICTRL4 LCDIF_DVICTRL4_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CSC_COEFF0 LCDIF_CSC_COEFF0_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CSC_COEFF1 LCDIF_CSC_COEFF1_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CSC_COEFF2 LCDIF_CSC_COEFF2_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CSC_COEFF3 LCDIF_CSC_COEFF3_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CSC_COEFF4 LCDIF_CSC_COEFF4_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CSC_OFFSET LCDIF_CSC_OFFSET_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CSC_LIMIT LCDIF_CSC_LIMIT_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DATA LCDIF_DATA_REG(LCDIF2_BASE_PTR) +#define LCDIF2_BM_ERROR_STAT LCDIF_BM_ERROR_STAT_REG(LCDIF2_BASE_PTR) +#define LCDIF2_CRC_STAT LCDIF_CRC_STAT_REG(LCDIF2_BASE_PTR) +#define LCDIF2_STAT LCDIF_STAT_REG(LCDIF2_BASE_PTR) +#define LCDIF2_VERSION LCDIF_VERSION_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DEBUG0 LCDIF_DEBUG0_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DEBUG1 LCDIF_DEBUG1_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DEBUG2 LCDIF_DEBUG2_REG(LCDIF2_BASE_PTR) +#define LCDIF2_THRES LCDIF_THRES_REG(LCDIF2_BASE_PTR) +#define LCDIF2_AS_CTRL LCDIF_AS_CTRL_REG(LCDIF2_BASE_PTR) +#define LCDIF2_AS_BUF LCDIF_AS_BUF_REG(LCDIF2_BASE_PTR) +#define LCDIF2_AS_NEXT_BUF LCDIF_AS_NEXT_BUF_REG(LCDIF2_BASE_PTR) +#define LCDIF2_AS_CLRKEYLOW LCDIF_AS_CLRKEYLOW_REG(LCDIF2_BASE_PTR) +#define LCDIF2_AS_CLRKEYHIGH LCDIF_AS_CLRKEYHIGH_REG(LCDIF2_BASE_PTR) +#define LCDIF2_SYNC_DELAY LCDIF_SYNC_DELAY_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DEBUG3 LCDIF_DEBUG3_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DEBUG4 LCDIF_DEBUG4_REG(LCDIF2_BASE_PTR) +#define LCDIF2_DEBUG5 LCDIF_DEBUG5_REG(LCDIF2_BASE_PTR) + +/*! + * @} + */ /* end of group LCDIF_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group LCDIF_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- LMEM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer + * @{ + */ + +/** LMEM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ + __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ + __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ + __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ + uint8_t RESERVED_0[2032]; + __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */ + __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */ + __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ + __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ +} LMEM_Type, *LMEM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- LMEM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros + * @{ + */ + + +/* LMEM - Register accessors */ +#define LMEM_PCCCR_REG(base) ((base)->PCCCR) +#define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) +#define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) +#define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) +#define LMEM_PSCCR_REG(base) ((base)->PSCCR) +#define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) +#define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) +#define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) + +/*! + * @} + */ /* end of group LMEM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- LMEM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/* PCCCR Bit Fields */ +#define LMEM_PCCCR_ENCACHE_MASK 0x1u +#define LMEM_PCCCR_ENCACHE_SHIFT 0 +#define LMEM_PCCCR_ENWRBUF_MASK 0x2u +#define LMEM_PCCCR_ENWRBUF_SHIFT 1 +#define LMEM_PCCCR_PCCR2_MASK 0x4u +#define LMEM_PCCCR_PCCR2_SHIFT 2 +#define LMEM_PCCCR_PCCR3_MASK 0x8u +#define LMEM_PCCCR_PCCR3_SHIFT 3 +#define LMEM_PCCCR_INVW0_MASK 0x1000000u +#define LMEM_PCCCR_INVW0_SHIFT 24 +#define LMEM_PCCCR_PUSHW0_MASK 0x2000000u +#define LMEM_PCCCR_PUSHW0_SHIFT 25 +#define LMEM_PCCCR_INVW1_MASK 0x4000000u +#define LMEM_PCCCR_INVW1_SHIFT 26 +#define LMEM_PCCCR_PUSHW1_MASK 0x8000000u +#define LMEM_PCCCR_PUSHW1_SHIFT 27 +#define LMEM_PCCCR_GO_MASK 0x80000000u +#define LMEM_PCCCR_GO_SHIFT 31 +/* PCCLCR Bit Fields */ +#define LMEM_PCCLCR_LGO_MASK 0x1u +#define LMEM_PCCLCR_LGO_SHIFT 0 +#define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu +#define LMEM_PCCLCR_CACHEADDR_SHIFT 2 +#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK) +#define LMEM_PCCLCR_WSEL_MASK 0x4000u +#define LMEM_PCCLCR_WSEL_SHIFT 14 +#define LMEM_PCCLCR_TDSEL_MASK 0x10000u +#define LMEM_PCCLCR_TDSEL_SHIFT 16 +#define LMEM_PCCLCR_LCIVB_MASK 0x100000u +#define LMEM_PCCLCR_LCIVB_SHIFT 20 +#define LMEM_PCCLCR_LCIMB_MASK 0x200000u +#define LMEM_PCCLCR_LCIMB_SHIFT 21 +#define LMEM_PCCLCR_LCWAY_MASK 0x400000u +#define LMEM_PCCLCR_LCWAY_SHIFT 22 +#define LMEM_PCCLCR_LCMD_MASK 0x3000000u +#define LMEM_PCCLCR_LCMD_SHIFT 24 +#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK) +#define LMEM_PCCLCR_LADSEL_MASK 0x4000000u +#define LMEM_PCCLCR_LADSEL_SHIFT 26 +#define LMEM_PCCLCR_LACC_MASK 0x8000000u +#define LMEM_PCCLCR_LACC_SHIFT 27 +/* PCCSAR Bit Fields */ +#define LMEM_PCCSAR_LGO_MASK 0x1u +#define LMEM_PCCSAR_LGO_SHIFT 0 +#define LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu +#define LMEM_PCCSAR_PHYADDR_SHIFT 2 +#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK) +/* PCCCVR Bit Fields */ +#define LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu +#define LMEM_PCCCVR_DATA_SHIFT 0 +#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK) +/* PSCCR Bit Fields */ +#define LMEM_PSCCR_ENCACHE_MASK 0x1u +#define LMEM_PSCCR_ENCACHE_SHIFT 0 +#define LMEM_PSCCR_ENWRBUF_MASK 0x2u +#define LMEM_PSCCR_ENWRBUF_SHIFT 1 +#define LMEM_PSCCR_INVW0_MASK 0x1000000u +#define LMEM_PSCCR_INVW0_SHIFT 24 +#define LMEM_PSCCR_PUSHW0_MASK 0x2000000u +#define LMEM_PSCCR_PUSHW0_SHIFT 25 +#define LMEM_PSCCR_INVW1_MASK 0x4000000u +#define LMEM_PSCCR_INVW1_SHIFT 26 +#define LMEM_PSCCR_PUSHW1_MASK 0x8000000u +#define LMEM_PSCCR_PUSHW1_SHIFT 27 +#define LMEM_PSCCR_GO_MASK 0x80000000u +#define LMEM_PSCCR_GO_SHIFT 31 +/* PSCLCR Bit Fields */ +#define LMEM_PSCLCR_LGO_MASK 0x1u +#define LMEM_PSCLCR_LGO_SHIFT 0 +#define LMEM_PSCLCR_CACHEADDR_MASK 0x1FFCu +#define LMEM_PSCLCR_CACHEADDR_SHIFT 2 +#define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_CACHEADDR_SHIFT))&LMEM_PSCLCR_CACHEADDR_MASK) +#define LMEM_PSCLCR_WSEL_MASK 0x4000u +#define LMEM_PSCLCR_WSEL_SHIFT 14 +#define LMEM_PSCLCR_TDSEL_MASK 0x10000u +#define LMEM_PSCLCR_TDSEL_SHIFT 16 +#define LMEM_PSCLCR_LCIVB_MASK 0x100000u +#define LMEM_PSCLCR_LCIVB_SHIFT 20 +#define LMEM_PSCLCR_LCIMB_MASK 0x200000u +#define LMEM_PSCLCR_LCIMB_SHIFT 21 +#define LMEM_PSCLCR_LCWAY_MASK 0x400000u +#define LMEM_PSCLCR_LCWAY_SHIFT 22 +#define LMEM_PSCLCR_LCMD_MASK 0x3000000u +#define LMEM_PSCLCR_LCMD_SHIFT 24 +#define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCLCR_LCMD_SHIFT))&LMEM_PSCLCR_LCMD_MASK) +#define LMEM_PSCLCR_LADSEL_MASK 0x4000000u +#define LMEM_PSCLCR_LADSEL_SHIFT 26 +#define LMEM_PSCLCR_LACC_MASK 0x8000000u +#define LMEM_PSCLCR_LACC_SHIFT 27 +/* PSCSAR Bit Fields */ +#define LMEM_PSCSAR_LGO_MASK 0x1u +#define LMEM_PSCSAR_LGO_SHIFT 0 +#define LMEM_PSCSAR_PHYADDR_MASK 0xFFFFFFFCu +#define LMEM_PSCSAR_PHYADDR_SHIFT 2 +#define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCSAR_PHYADDR_SHIFT))&LMEM_PSCSAR_PHYADDR_MASK) +/* PSCCVR Bit Fields */ +#define LMEM_PSCCVR_DATA_MASK 0xFFFFFFFFu +#define LMEM_PSCCVR_DATA_SHIFT 0 +#define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PSCCVR_DATA_SHIFT))&LMEM_PSCCVR_DATA_MASK) + +/*! + * @} + */ /* end of group LMEM_Register_Masks */ + + +/* LMEM - Peripheral instance base addresses */ +/** Peripheral LMEM base address */ +#define LMEM_BASE (0xE0082000u) +/** Peripheral LMEM base pointer */ +#define LMEM ((LMEM_Type *)LMEM_BASE) +#define LMEM_BASE_PTR (LMEM) +/** Array initializer of LMEM peripheral base adresses */ +#define LMEM_BASE_ADDRS { LMEM_BASE } +/** Array initializer of LMEM peripheral base pointers */ +#define LMEM_BASE_PTRS { LMEM } + +/* ---------------------------------------------------------------------------- + -- LMEM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Accessor_Macros LMEM - Register accessor macros + * @{ + */ + + +/* LMEM - Register instance definitions */ +/* LMEM */ +#define LMEM_PCCCR LMEM_PCCCR_REG(LMEM_BASE_PTR) +#define LMEM_PCCLCR LMEM_PCCLCR_REG(LMEM_BASE_PTR) +#define LMEM_PCCSAR LMEM_PCCSAR_REG(LMEM_BASE_PTR) +#define LMEM_PCCCVR LMEM_PCCCVR_REG(LMEM_BASE_PTR) +#define LMEM_PSCCR LMEM_PSCCR_REG(LMEM_BASE_PTR) +#define LMEM_PSCLCR LMEM_PSCLCR_REG(LMEM_BASE_PTR) +#define LMEM_PSCSAR LMEM_PSCSAR_REG(LMEM_BASE_PTR) +#define LMEM_PSCCVR LMEM_PSCCVR_REG(LMEM_BASE_PTR) + +/*! + * @} + */ /* end of group LMEM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group LMEM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer + * @{ + */ + +/** MCM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ + __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ + uint8_t RESERVED_1[20]; + __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ + __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ + __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ +} MCM_Type, *MCM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- MCM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros + * @{ + */ + + +/* MCM - Register accessors */ +#define MCM_PLASC_REG(base) ((base)->PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_FADR_REG(base) ((base)->FADR) +#define MCM_FATR_REG(base) ((base)->FATR) +#define MCM_FDR_REG(base) ((base)->FDR) + +/*! + * @} + */ /* end of group MCM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) +/* PLAMC Bit Fields */ +#define MCM_PLAMC_AMC_MASK 0xFFu +#define MCM_PLAMC_AMC_SHIFT 0 +#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) +/* FADR Bit Fields */ +#define MCM_FADR_ADDRESS_MASK 0xFFFFFFFFu +#define MCM_FADR_ADDRESS_SHIFT 0 +#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<MCM_FADR_ADDRESS_SHIFT))&MCM_FADR_ADDRESS_MASK) +/* FATR Bit Fields */ +#define MCM_FATR_BEDA_MASK 0x1u +#define MCM_FATR_BEDA_SHIFT 0 +#define MCM_FATR_BEMD_MASK 0x2u +#define MCM_FATR_BEMD_SHIFT 1 +#define MCM_FATR_BESZ_MASK 0x30u +#define MCM_FATR_BESZ_SHIFT 4 +#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BESZ_SHIFT))&MCM_FATR_BESZ_MASK) +#define MCM_FATR_BEWT_MASK 0x80u +#define MCM_FATR_BEWT_SHIFT 7 +#define MCM_FATR_BEMN_MASK 0xF00u +#define MCM_FATR_BEMN_SHIFT 8 +#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x))<<MCM_FATR_BEMN_SHIFT))&MCM_FATR_BEMN_MASK) +#define MCM_FATR_BEOVR_MASK 0x80000000u +#define MCM_FATR_BEOVR_SHIFT 31 +/* FDR Bit Fields */ +#define MCM_FDR_DATA_MASK 0xFFFFFFFFu +#define MCM_FDR_DATA_SHIFT 0 +#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<MCM_FDR_DATA_SHIFT))&MCM_FDR_DATA_MASK) + +/*! + * @} + */ /* end of group MCM_Register_Masks */ + + +/* MCM - Peripheral instance base addresses */ +/** Peripheral MCM base address */ +#define MCM_BASE (0xE0000000u) +/** Peripheral MCM base pointer */ +#define MCM ((MCM_Type *)MCM_BASE) +#define MCM_BASE_PTR (MCM) +/** Array initializer of MCM peripheral base adresses */ +#define MCM_BASE_ADDRS { MCM_BASE } +/** Array initializer of MCM peripheral base pointers */ +#define MCM_BASE_PTRS { MCM } + +/* ---------------------------------------------------------------------------- + -- MCM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros + * @{ + */ + + +/* MCM - Register instance definitions */ +/* MCM */ +#define MCM_PLASC MCM_PLASC_REG(MCM_BASE_PTR) +#define MCM_PLAMC MCM_PLAMC_REG(MCM_BASE_PTR) +#define MCM_FADR MCM_FADR_REG(MCM_BASE_PTR) +#define MCM_FATR MCM_FATR_REG(MCM_BASE_PTR) +#define MCM_FDR MCM_FDR_REG(MCM_BASE_PTR) + +/*! + * @} + */ /* end of group MCM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group MCM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_Peripheral_Access_Layer MIPI_DSI Peripheral Access Layer + * @{ + */ + +/** MIPI_DSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t VERSION; /**< Version Register, offset: 0x0 */ + __IO uint32_t STATUS; /**< , offset: 0x4 */ + __IO uint32_t RGB_STATUS; /**< RGB Status Register, offset: 0x8 */ + __IO uint32_t SWRST; /**< , offset: 0xC */ + __IO uint32_t CLKCTRL; /**< Clock Control Register, offset: 0x10 */ + __IO uint32_t TIMEOUT; /**< , offset: 0x14 */ + __IO uint32_t CONFIG; /**< , offset: 0x18 */ + __IO uint32_t ESCMODE; /**< Escape Mode Register, offset: 0x1C */ + __IO uint32_t MDRESOL; /**< Main Display Image Resolution Register, offset: 0x20 */ + __IO uint32_t MVPORCH; /**< Main Display VPORCH Register, offset: 0x24 */ + __IO uint32_t MHPORCH; /**< , offset: 0x28 */ + __IO uint32_t MSYNC; /**< , offset: 0x2C */ + __IO uint32_t SDRESOL; /**< Sub Display Image Resolution Register, offset: 0x30 */ + __IO uint32_t INTSRC; /**< Interrupt Source Register, offset: 0x34 */ + __IO uint32_t INTMSK; /**< Interrupt Mask Register, offset: 0x38 */ + __IO uint32_t PKTHDR; /**< Packet Header FIFO Register, offset: 0x3C */ + __IO uint32_t PAYLOAD; /**< Payload FIFO Register, offset: 0x40 */ + __IO uint32_t RXFIFO; /**< Payload FIFO Register, offset: 0x44 */ + __IO uint32_t FIFOTHLD; /**< FIFO Threshold Level Register, offset: 0x48 */ + __IO uint32_t FIFOCTRL; /**< FIFO Status and Control Register, offset: 0x4C */ + __IO uint32_t MEMACCHR; /**< FIFO Memory AC Characteristic Register, offset: 0x50 */ + uint8_t RESERVED_0[36]; + __IO uint32_t MULTI_PKT; /**< , offset: 0x78 */ + uint8_t RESERVED_1[20]; + __IO uint32_t PLLCTRL_1G; /**< 1 Gbps D-PHY PLL Control Register, offset: 0x90 */ + __IO uint32_t PLLCTRL; /**< PLL Control register, offset: 0x94 */ + __IO uint32_t PLLCTRL1; /**< PLL Control Register 1, offset: 0x98 */ + __IO uint32_t PLLCTRL2; /**< PLL control register 2, offset: 0x9C */ + __IO uint32_t PLLTMR; /**< PLL Timer Register, offset: 0xA0 */ + union { /* offset: 0xA4 */ + struct { /* offset: 0xA4 */ + __IO uint32_t PHYCTRL_B1; /**< D-PHY Master and Slave Analog Block Control Register 1, offset: 0xA4 */ + __IO uint32_t PHYCTRL_B2; /**< D-PHY Master and Slave Analog Block Control Register 2, offset: 0xA8 */ + } PHYCTRL_B; + struct { /* offset: 0xA4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PHYCTRL_M1; /**< D-PHY Master Analog Block Control Register 1, offset: 0xA8 */ + __IO uint32_t PHYCTRL_M2; /**< D-PHY Master Analog Block Control Register 1, offset: 0xAC */ + } PHYCTRL_M; + }; + uint8_t RESERVED_2[4]; + __IO uint32_t PHYTIMING; /**< D-PHY Timing register, offset: 0xB4 */ + __IO uint32_t PHYTIMING1; /**< , offset: 0xB8 */ + __IO uint32_t PHYTIMING2; /**< D-PHY Timing Register 2, offset: 0xBC */ +} MIPI_DSI_Type, *MIPI_DSI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_Register_Accessor_Macros MIPI_DSI - Register accessor macros + * @{ + */ + + +/* MIPI_DSI - Register accessors */ +#define MIPI_DSI_VERSION_REG(base) ((base)->VERSION) +#define MIPI_DSI_STATUS_REG(base) ((base)->STATUS) +#define MIPI_DSI_RGB_STATUS_REG(base) ((base)->RGB_STATUS) +#define MIPI_DSI_SWRST_REG(base) ((base)->SWRST) +#define MIPI_DSI_CLKCTRL_REG(base) ((base)->CLKCTRL) +#define MIPI_DSI_TIMEOUT_REG(base) ((base)->TIMEOUT) +#define MIPI_DSI_CONFIG_REG(base) ((base)->CONFIG) +#define MIPI_DSI_ESCMODE_REG(base) ((base)->ESCMODE) +#define MIPI_DSI_MDRESOL_REG(base) ((base)->MDRESOL) +#define MIPI_DSI_MVPORCH_REG(base) ((base)->MVPORCH) +#define MIPI_DSI_MHPORCH_REG(base) ((base)->MHPORCH) +#define MIPI_DSI_MSYNC_REG(base) ((base)->MSYNC) +#define MIPI_DSI_SDRESOL_REG(base) ((base)->SDRESOL) +#define MIPI_DSI_INTSRC_REG(base) ((base)->INTSRC) +#define MIPI_DSI_INTMSK_REG(base) ((base)->INTMSK) +#define MIPI_DSI_PKTHDR_REG(base) ((base)->PKTHDR) +#define MIPI_DSI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define MIPI_DSI_RXFIFO_REG(base) ((base)->RXFIFO) +#define MIPI_DSI_FIFOTHLD_REG(base) ((base)->FIFOTHLD) +#define MIPI_DSI_FIFOCTRL_REG(base) ((base)->FIFOCTRL) +#define MIPI_DSI_MEMACCHR_REG(base) ((base)->MEMACCHR) +#define MIPI_DSI_MULTI_PKT_REG(base) ((base)->MULTI_PKT) +#define MIPI_DSI_PLLCTRL_1G_REG(base) ((base)->PLLCTRL_1G) +#define MIPI_DSI_PLLCTRL_REG(base) ((base)->PLLCTRL) +#define MIPI_DSI_PLLCTRL1_REG(base) ((base)->PLLCTRL1) +#define MIPI_DSI_PLLCTRL2_REG(base) ((base)->PLLCTRL2) +#define MIPI_DSI_PLLTMR_REG(base) ((base)->PLLTMR) +#define MIPI_DSI_PHYCTRL_B1_REG(base) ((base)->PHYCTRL_B.PHYCTRL_B1) +#define MIPI_DSI_PHYCTRL_B2_REG(base) ((base)->PHYCTRL_B.PHYCTRL_B2) +#define MIPI_DSI_PHYCTRL_M1_REG(base) ((base)->PHYCTRL_M.PHYCTRL_M1) +#define MIPI_DSI_PHYCTRL_M2_REG(base) ((base)->PHYCTRL_M.PHYCTRL_M2) +#define MIPI_DSI_PHYTIMING_REG(base) ((base)->PHYTIMING) +#define MIPI_DSI_PHYTIMING1_REG(base) ((base)->PHYTIMING1) +#define MIPI_DSI_PHYTIMING2_REG(base) ((base)->PHYTIMING2) + +/*! + * @} + */ /* end of group MIPI_DSI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks + * @{ + */ + +/* VERSION Bit Fields */ +#define MIPI_DSI_VERSION_VERSION_MASK 0xFFFFFFFFu +#define MIPI_DSI_VERSION_VERSION_SHIFT 0 +#define MIPI_DSI_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_VERSION_VERSION_SHIFT))&MIPI_DSI_VERSION_VERSION_MASK) +/* STATUS Bit Fields */ +#define MIPI_DSI_STATUS_STOPSTATEDAT_MASK 0xFu +#define MIPI_DSI_STATUS_STOPSTATEDAT_SHIFT 0 +#define MIPI_DSI_STATUS_STOPSTATEDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_STATUS_STOPSTATEDAT_SHIFT))&MIPI_DSI_STATUS_STOPSTATEDAT_MASK) +#define MIPI_DSI_STATUS_ULPSDAT_MASK 0xF0u +#define MIPI_DSI_STATUS_ULPSDAT_SHIFT 4 +#define MIPI_DSI_STATUS_ULPSDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_STATUS_ULPSDAT_SHIFT))&MIPI_DSI_STATUS_ULPSDAT_MASK) +#define MIPI_DSI_STATUS_STOPSTATECLK_MASK 0x100u +#define MIPI_DSI_STATUS_STOPSTATECLK_SHIFT 8 +#define MIPI_DSI_STATUS_ULPSCLK_MASK 0x200u +#define MIPI_DSI_STATUS_ULPSCLK_SHIFT 9 +#define MIPI_DSI_STATUS_TXREADYHSCLK_MASK 0x400u +#define MIPI_DSI_STATUS_TXREADYHSCLK_SHIFT 10 +#define MIPI_DSI_STATUS_DIRECTION_MASK 0x10000u +#define MIPI_DSI_STATUS_DIRECTION_SHIFT 16 +#define MIPI_DSI_STATUS_SWRSTRLS_MASK 0x100000u +#define MIPI_DSI_STATUS_SWRSTRLS_SHIFT 20 +#define MIPI_DSI_STATUS_PLLSTABLE_MASK 0x80000000u +#define MIPI_DSI_STATUS_PLLSTABLE_SHIFT 31 +/* RGB_STATUS Bit Fields */ +#define MIPI_DSI_RGB_STATUS_RGBSTATE_MASK 0x1FFFu +#define MIPI_DSI_RGB_STATUS_RGBSTATE_SHIFT 0 +#define MIPI_DSI_RGB_STATUS_RGBSTATE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_RGB_STATUS_RGBSTATE_SHIFT))&MIPI_DSI_RGB_STATUS_RGBSTATE_MASK) +#define MIPI_DSI_RGB_STATUS_CMDMODE_INSEL_MASK 0x80000000u +#define MIPI_DSI_RGB_STATUS_CMDMODE_INSEL_SHIFT 31 +/* SWRST Bit Fields */ +#define MIPI_DSI_SWRST_SWRST_MASK 0x1u +#define MIPI_DSI_SWRST_SWRST_SHIFT 0 +#define MIPI_DSI_SWRST_FUNCRST_MASK 0x10000u +#define MIPI_DSI_SWRST_FUNCRST_SHIFT 16 +/* CLKCTRL Bit Fields */ +#define MIPI_DSI_CLKCTRL_ESCPRESCALER_MASK 0xFFFFu +#define MIPI_DSI_CLKCTRL_ESCPRESCALER_SHIFT 0 +#define MIPI_DSI_CLKCTRL_ESCPRESCALER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CLKCTRL_ESCPRESCALER_SHIFT))&MIPI_DSI_CLKCTRL_ESCPRESCALER_MASK) +#define MIPI_DSI_CLKCTRL_LANEESCCLKEN_MASK 0xF80000u +#define MIPI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT 19 +#define MIPI_DSI_CLKCTRL_LANEESCCLKEN(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT))&MIPI_DSI_CLKCTRL_LANEESCCLKEN_MASK) +#define MIPI_DSI_CLKCTRL_ByteClkEn_MASK 0x1000000u +#define MIPI_DSI_CLKCTRL_ByteClkEn_SHIFT 24 +#define MIPI_DSI_CLKCTRL_BYTECLKSRC_MASK 0x6000000u +#define MIPI_DSI_CLKCTRL_BYTECLKSRC_SHIFT 25 +#define MIPI_DSI_CLKCTRL_BYTECLKSRC(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CLKCTRL_BYTECLKSRC_SHIFT))&MIPI_DSI_CLKCTRL_BYTECLKSRC_MASK) +#define MIPI_DSI_CLKCTRL_PLLBYPASS_MASK 0x8000000u +#define MIPI_DSI_CLKCTRL_PLLBYPASS_SHIFT 27 +#define MIPI_DSI_CLKCTRL_ESCCLKEN_MASK 0x10000000u +#define MIPI_DSI_CLKCTRL_ESCCLKEN_SHIFT 28 +#define MIPI_DSI_CLKCTRL_DPHY_SEL_MASK 0x20000000u +#define MIPI_DSI_CLKCTRL_DPHY_SEL_SHIFT 29 +#define MIPI_DSI_CLKCTRL_TXREQUESTHSCLK_MASK 0x80000000u +#define MIPI_DSI_CLKCTRL_TXREQUESTHSCLK_SHIFT 31 +/* TIMEOUT Bit Fields */ +#define MIPI_DSI_TIMEOUT_LPDRTOUT_MASK 0xFFFFu +#define MIPI_DSI_TIMEOUT_LPDRTOUT_SHIFT 0 +#define MIPI_DSI_TIMEOUT_LPDRTOUT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_TIMEOUT_LPDRTOUT_SHIFT))&MIPI_DSI_TIMEOUT_LPDRTOUT_MASK) +#define MIPI_DSI_TIMEOUT_BTAOUT_MASK 0xFF0000u +#define MIPI_DSI_TIMEOUT_BTAOUT_SHIFT 16 +#define MIPI_DSI_TIMEOUT_BTAOUT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_TIMEOUT_BTAOUT_SHIFT))&MIPI_DSI_TIMEOUT_BTAOUT_MASK) +/* CONFIG Bit Fields */ +#define MIPI_DSI_CONFIG_LANEEN_MASK 0x1Fu +#define MIPI_DSI_CONFIG_LANEEN_SHIFT 0 +#define MIPI_DSI_CONFIG_LANEEN(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_LANEEN_SHIFT))&MIPI_DSI_CONFIG_LANEEN_MASK) +#define MIPI_DSI_CONFIG_NUMOFDATLANE_MASK 0x60u +#define MIPI_DSI_CONFIG_NUMOFDATLANE_SHIFT 5 +#define MIPI_DSI_CONFIG_NUMOFDATLANE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_NUMOFDATLANE_SHIFT))&MIPI_DSI_CONFIG_NUMOFDATLANE_MASK) +#define MIPI_DSI_CONFIG_SUBPIXFORMAT_MASK 0x700u +#define MIPI_DSI_CONFIG_SUBPIXFORMAT_SHIFT 8 +#define MIPI_DSI_CONFIG_SUBPIXFORMAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_SUBPIXFORMAT_SHIFT))&MIPI_DSI_CONFIG_SUBPIXFORMAT_MASK) +#define MIPI_DSI_CONFIG_MAINPIXFORMAT_MASK 0x7000u +#define MIPI_DSI_CONFIG_MAINPIXFORMAT_SHIFT 12 +#define MIPI_DSI_CONFIG_MAINPIXFORMAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_MAINPIXFORMAT_SHIFT))&MIPI_DSI_CONFIG_MAINPIXFORMAT_MASK) +#define MIPI_DSI_CONFIG_SUBVC_MASK 0x30000u +#define MIPI_DSI_CONFIG_SUBVC_SHIFT 16 +#define MIPI_DSI_CONFIG_SUBVC(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_SUBVC_SHIFT))&MIPI_DSI_CONFIG_SUBVC_MASK) +#define MIPI_DSI_CONFIG_MAINVC_MASK 0xC0000u +#define MIPI_DSI_CONFIG_MAINVC_SHIFT 18 +#define MIPI_DSI_CONFIG_MAINVC(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_CONFIG_MAINVC_SHIFT))&MIPI_DSI_CONFIG_MAINVC_MASK) +#define MIPI_DSI_CONFIG_HSADISABLEMODE_MASK 0x100000u +#define MIPI_DSI_CONFIG_HSADISABLEMODE_SHIFT 20 +#define MIPI_DSI_CONFIG_HBPDISABLEMODE_MASK 0x200000u +#define MIPI_DSI_CONFIG_HBPDISABLEMODE_SHIFT 21 +#define MIPI_DSI_CONFIG_HFPDISABLEMODE_MASK 0x400000u +#define MIPI_DSI_CONFIG_HFPDISABLEMODE_SHIFT 22 +#define MIPI_DSI_CONFIG_HSEDISABLEMODE_MASK 0x800000u +#define MIPI_DSI_CONFIG_HSEDISABLEMODE_SHIFT 23 +#define MIPI_DSI_CONFIG_AUTOMODE_MASK 0x1000000u +#define MIPI_DSI_CONFIG_AUTOMODE_SHIFT 24 +#define MIPI_DSI_CONFIG_VIDEOMODE_MASK 0x2000000u +#define MIPI_DSI_CONFIG_VIDEOMODE_SHIFT 25 +#define MIPI_DSI_CONFIG_BURSTMODE_MASK 0x4000000u +#define MIPI_DSI_CONFIG_BURSTMODE_SHIFT 26 +#define MIPI_DSI_CONFIG_SYNCINFORM_MASK 0x8000000u +#define MIPI_DSI_CONFIG_SYNCINFORM_SHIFT 27 +#define MIPI_DSI_CONFIG_EOT_R03_MASK 0x10000000u +#define MIPI_DSI_CONFIG_EOT_R03_SHIFT 28 +#define MIPI_DSI_CONFIG_MFLUSH_VS_MASK 0x20000000u +#define MIPI_DSI_CONFIG_MFLUSH_VS_SHIFT 29 +#define MIPI_DSI_CONFIG_CLKLANE_STOP_START_MASK 0x40000000u +#define MIPI_DSI_CONFIG_CLKLANE_STOP_START_SHIFT 30 +#define MIPI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_MASK 0x80000000u +#define MIPI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_SHIFT 31 +/* ESCMODE Bit Fields */ +#define MIPI_DSI_ESCMODE_TXULPSCLKEXIT_MASK 0x1u +#define MIPI_DSI_ESCMODE_TXULPSCLKEXIT_SHIFT 0 +#define MIPI_DSI_ESCMODE_TXULPSCLK_MASK 0x2u +#define MIPI_DSI_ESCMODE_TXULPSCLK_SHIFT 1 +#define MIPI_DSI_ESCMODE_TXULPSEXIT_MASK 0x4u +#define MIPI_DSI_ESCMODE_TXULPSEXIT_SHIFT 2 +#define MIPI_DSI_ESCMODE_TXULPSDAT_MASK 0x8u +#define MIPI_DSI_ESCMODE_TXULPSDAT_SHIFT 3 +#define MIPI_DSI_ESCMODE_TXTRIGGERRST_MASK 0x10u +#define MIPI_DSI_ESCMODE_TXTRIGGERRST_SHIFT 4 +#define MIPI_DSI_ESCMODE_TXLPDT_MASK 0x40u +#define MIPI_DSI_ESCMODE_TXLPDT_SHIFT 6 +#define MIPI_DSI_ESCMODE_CMDLPDT_MASK 0x80u +#define MIPI_DSI_ESCMODE_CMDLPDT_SHIFT 7 +#define MIPI_DSI_ESCMODE_FORCEBTA_MASK 0x10000u +#define MIPI_DSI_ESCMODE_FORCEBTA_SHIFT 16 +#define MIPI_DSI_ESCMODE_FORCESTOPSTATE_MASK 0x100000u +#define MIPI_DSI_ESCMODE_FORCESTOPSTATE_SHIFT 20 +#define MIPI_DSI_ESCMODE_STOPSTATE_CNT_MASK 0xFFE00000u +#define MIPI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT 21 +#define MIPI_DSI_ESCMODE_STOPSTATE_CNT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT))&MIPI_DSI_ESCMODE_STOPSTATE_CNT_MASK) +/* MDRESOL Bit Fields */ +#define MIPI_DSI_MDRESOL_MAINHRESOL_MASK 0xFFFu +#define MIPI_DSI_MDRESOL_MAINHRESOL_SHIFT 0 +#define MIPI_DSI_MDRESOL_MAINHRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MDRESOL_MAINHRESOL_SHIFT))&MIPI_DSI_MDRESOL_MAINHRESOL_MASK) +#define MIPI_DSI_MDRESOL_MainVResol_MASK 0xFFF0000u +#define MIPI_DSI_MDRESOL_MainVResol_SHIFT 16 +#define MIPI_DSI_MDRESOL_MainVResol(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MDRESOL_MainVResol_SHIFT))&MIPI_DSI_MDRESOL_MainVResol_MASK) +#define MIPI_DSI_MDRESOL_MAINSTANDBY_MASK 0x80000000u +#define MIPI_DSI_MDRESOL_MAINSTANDBY_SHIFT 31 +/* MVPORCH Bit Fields */ +#define MIPI_DSI_MVPORCH_MAINVBP_MASK 0x7FFu +#define MIPI_DSI_MVPORCH_MAINVBP_SHIFT 0 +#define MIPI_DSI_MVPORCH_MAINVBP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MVPORCH_MAINVBP_SHIFT))&MIPI_DSI_MVPORCH_MAINVBP_MASK) +#define MIPI_DSI_MVPORCH_STABLEVFP_MASK 0x7FF0000u +#define MIPI_DSI_MVPORCH_STABLEVFP_SHIFT 16 +#define MIPI_DSI_MVPORCH_STABLEVFP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MVPORCH_STABLEVFP_SHIFT))&MIPI_DSI_MVPORCH_STABLEVFP_MASK) +#define MIPI_DSI_MVPORCH_CMDALLOW_MASK 0xF0000000u +#define MIPI_DSI_MVPORCH_CMDALLOW_SHIFT 28 +#define MIPI_DSI_MVPORCH_CMDALLOW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MVPORCH_CMDALLOW_SHIFT))&MIPI_DSI_MVPORCH_CMDALLOW_MASK) +/* MHPORCH Bit Fields */ +#define MIPI_DSI_MHPORCH_MAINHBP_MASK 0xFFFFu +#define MIPI_DSI_MHPORCH_MAINHBP_SHIFT 0 +#define MIPI_DSI_MHPORCH_MAINHBP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MHPORCH_MAINHBP_SHIFT))&MIPI_DSI_MHPORCH_MAINHBP_MASK) +#define MIPI_DSI_MHPORCH_MAINHFP_MASK 0xFFFF0000u +#define MIPI_DSI_MHPORCH_MAINHFP_SHIFT 16 +#define MIPI_DSI_MHPORCH_MAINHFP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MHPORCH_MAINHFP_SHIFT))&MIPI_DSI_MHPORCH_MAINHFP_MASK) +/* MSYNC Bit Fields */ +#define MIPI_DSI_MSYNC_MAINHSA_MASK 0xFFFFu +#define MIPI_DSI_MSYNC_MAINHSA_SHIFT 0 +#define MIPI_DSI_MSYNC_MAINHSA(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MSYNC_MAINHSA_SHIFT))&MIPI_DSI_MSYNC_MAINHSA_MASK) +#define MIPI_DSI_MSYNC_MAINVSA_MASK 0xFFC00000u +#define MIPI_DSI_MSYNC_MAINVSA_SHIFT 22 +#define MIPI_DSI_MSYNC_MAINVSA(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MSYNC_MAINVSA_SHIFT))&MIPI_DSI_MSYNC_MAINVSA_MASK) +/* SDRESOL Bit Fields */ +#define MIPI_DSI_SDRESOL_SUBHRESOL_MASK 0x7FFu +#define MIPI_DSI_SDRESOL_SUBHRESOL_SHIFT 0 +#define MIPI_DSI_SDRESOL_SUBHRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_SDRESOL_SUBHRESOL_SHIFT))&MIPI_DSI_SDRESOL_SUBHRESOL_MASK) +#define MIPI_DSI_SDRESOL_SUBVRESOL_MASK 0x7FF0000u +#define MIPI_DSI_SDRESOL_SUBVRESOL_SHIFT 16 +#define MIPI_DSI_SDRESOL_SUBVRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_SDRESOL_SUBVRESOL_SHIFT))&MIPI_DSI_SDRESOL_SUBVRESOL_MASK) +#define MIPI_DSI_SDRESOL_SUBSTANDBY_MASK 0x80000000u +#define MIPI_DSI_SDRESOL_SUBSTANDBY_SHIFT 31 +/* INTSRC Bit Fields */ +#define MIPI_DSI_INTSRC_ERRCONTENTLP1_MASK 0x1u +#define MIPI_DSI_INTSRC_ERRCONTENTLP1_SHIFT 0 +#define MIPI_DSI_INTSRC_ERRCONTENTLP0_MASK 0x2u +#define MIPI_DSI_INTSRC_ERRCONTENTLP0_SHIFT 1 +#define MIPI_DSI_INTSRC_ERRCONTROL0_MASK 0x4u +#define MIPI_DSI_INTSRC_ERRCONTROL0_SHIFT 2 +#define MIPI_DSI_INTSRC_ERRCONTROL1_MASK 0x8u +#define MIPI_DSI_INTSRC_ERRCONTROL1_SHIFT 3 +#define MIPI_DSI_INTSRC_ERRSYNC0_MASK 0x40u +#define MIPI_DSI_INTSRC_ERRSYNC0_SHIFT 6 +#define MIPI_DSI_INTSRC_ERRSYNC1_MASK 0x80u +#define MIPI_DSI_INTSRC_ERRSYNC1_SHIFT 7 +#define MIPI_DSI_INTSRC_ERRESC0_MASK 0x400u +#define MIPI_DSI_INTSRC_ERRESC0_SHIFT 10 +#define MIPI_DSI_INTSRC_ERRESC1_MASK 0x800u +#define MIPI_DSI_INTSRC_ERRESC1_SHIFT 11 +#define MIPI_DSI_INTSRC_ERRRXCRC_MASK 0x4000u +#define MIPI_DSI_INTSRC_ERRRXCRC_SHIFT 14 +#define MIPI_DSI_INTSRC_ERRRXECC_MASK 0x8000u +#define MIPI_DSI_INTSRC_ERRRXECC_SHIFT 15 +#define MIPI_DSI_INTSRC_RXACK_MASK 0x10000u +#define MIPI_DSI_INTSRC_RXACK_SHIFT 16 +#define MIPI_DSI_INTSRC_RXTE_MASK 0x20000u +#define MIPI_DSI_INTSRC_RXTE_SHIFT 17 +#define MIPI_DSI_INTSRC_RXDATDONE_MASK 0x40000u +#define MIPI_DSI_INTSRC_RXDATDONE_SHIFT 18 +#define MIPI_DSI_INTSRC_TATOUT_MASK 0x100000u +#define MIPI_DSI_INTSRC_TATOUT_SHIFT 20 +#define MIPI_DSI_INTSRC_LPDRTOUT_MASK 0x200000u +#define MIPI_DSI_INTSRC_LPDRTOUT_SHIFT 21 +#define MIPI_DSI_INTSRC_FRAMEDONE_MASK 0x1000000u +#define MIPI_DSI_INTSRC_FRAMEDONE_SHIFT 24 +#define MIPI_DSI_INTSRC_BUSTURNOVER_MASK 0x2000000u +#define MIPI_DSI_INTSRC_BUSTURNOVER_SHIFT 25 +#define MIPI_DSI_INTSRC_SYNCOVERRIDE_MASK 0x8000000u +#define MIPI_DSI_INTSRC_SYNCOVERRIDE_SHIFT 27 +#define MIPI_DSI_INTSRC_SFRPHFIFOEMPTY_MASK 0x10000000u +#define MIPI_DSI_INTSRC_SFRPHFIFOEMPTY_SHIFT 28 +#define MIPI_DSI_INTSRC_SFRPLFIFOEMPTY_MASK 0x20000000u +#define MIPI_DSI_INTSRC_SFRPLFIFOEMPTY_SHIFT 29 +#define MIPI_DSI_INTSRC_SWRSTRELEASE_MASK 0x40000000u +#define MIPI_DSI_INTSRC_SWRSTRELEASE_SHIFT 30 +#define MIPI_DSI_INTSRC_PLLSTABLE_MASK 0x80000000u +#define MIPI_DSI_INTSRC_PLLSTABLE_SHIFT 31 +/* INTMSK Bit Fields */ +#define MIPI_DSI_INTMSK_MSKCONTENTLP1_MASK 0x1u +#define MIPI_DSI_INTMSK_MSKCONTENTLP1_SHIFT 0 +#define MIPI_DSI_INTMSK_MSKCONTENTLP0_MASK 0x2u +#define MIPI_DSI_INTMSK_MSKCONTENTLP0_SHIFT 1 +#define MIPI_DSI_INTMSK_MSKCONTROL0_MASK 0x4u +#define MIPI_DSI_INTMSK_MSKCONTROL0_SHIFT 2 +#define MIPI_DSI_INTMSK_MSKCONTROL1_MASK 0x8u +#define MIPI_DSI_INTMSK_MSKCONTROL1_SHIFT 3 +#define MIPI_DSI_INTMSK_MSKSYNC0_MASK 0x40u +#define MIPI_DSI_INTMSK_MSKSYNC0_SHIFT 6 +#define MIPI_DSI_INTMSK_MSKSYNC1_MASK 0x80u +#define MIPI_DSI_INTMSK_MSKSYNC1_SHIFT 7 +#define MIPI_DSI_INTMSK_MSKESC0_MASK 0x400u +#define MIPI_DSI_INTMSK_MSKESC0_SHIFT 10 +#define MIPI_DSI_INTMSK_MSKESC1_MASK 0x800u +#define MIPI_DSI_INTMSK_MSKESC1_SHIFT 11 +#define MIPI_DSI_INTMSK_MSKRXCRC_MASK 0x4000u +#define MIPI_DSI_INTMSK_MSKRXCRC_SHIFT 14 +#define MIPI_DSI_INTMSK_MSKRXECC_MASK 0x8000u +#define MIPI_DSI_INTMSK_MSKRXECC_SHIFT 15 +#define MIPI_DSI_INTMSK_MSKRXACK_MASK 0x10000u +#define MIPI_DSI_INTMSK_MSKRXACK_SHIFT 16 +#define MIPI_DSI_INTMSK_MSKRXTE_MASK 0x20000u +#define MIPI_DSI_INTMSK_MSKRXTE_SHIFT 17 +#define MIPI_DSI_INTMSK_MSKRXDATDONE_MASK 0x40000u +#define MIPI_DSI_INTMSK_MSKRXDATDONE_SHIFT 18 +#define MIPI_DSI_INTMSK_MSKTATOUT_MASK 0x100000u +#define MIPI_DSI_INTMSK_MSKTATOUT_SHIFT 20 +#define MIPI_DSI_INTMSK_MSKLPDRTOUT_MASK 0x200000u +#define MIPI_DSI_INTMSK_MSKLPDRTOUT_SHIFT 21 +#define MIPI_DSI_INTMSK_MSKFRAMEDONE_MASK 0x1000000u +#define MIPI_DSI_INTMSK_MSKFRAMEDONE_SHIFT 24 +#define MIPI_DSI_INTMSK_MSKBUSTURNOVER_MASK 0x2000000u +#define MIPI_DSI_INTMSK_MSKBUSTURNOVER_SHIFT 25 +#define MIPI_DSI_INTMSK_MSKSYNCOVERRIDE_MASK 0x8000000u +#define MIPI_DSI_INTMSK_MSKSYNCOVERRIDE_SHIFT 27 +#define MIPI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_MASK 0x10000000u +#define MIPI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_SHIFT 28 +#define MIPI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_MASK 0x20000000u +#define MIPI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_SHIFT 29 +#define MIPI_DSI_INTMSK_MSKSWRSTRELEASE_MASK 0x40000000u +#define MIPI_DSI_INTMSK_MSKSWRSTRELEASE_SHIFT 30 +#define MIPI_DSI_INTMSK_MSKPLLSTABLE_MASK 0x80000000u +#define MIPI_DSI_INTMSK_MSKPLLSTABLE_SHIFT 31 +/* PKTHDR Bit Fields */ +#define MIPI_DSI_PKTHDR_PACKETHEADER_MASK 0xFFFFFFu +#define MIPI_DSI_PKTHDR_PACKETHEADER_SHIFT 0 +#define MIPI_DSI_PKTHDR_PACKETHEADER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PKTHDR_PACKETHEADER_SHIFT))&MIPI_DSI_PKTHDR_PACKETHEADER_MASK) +/* PAYLOAD Bit Fields */ +#define MIPI_DSI_PAYLOAD_PAYLOAD_MASK 0xFFFFFFFFu +#define MIPI_DSI_PAYLOAD_PAYLOAD_SHIFT 0 +#define MIPI_DSI_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PAYLOAD_PAYLOAD_SHIFT))&MIPI_DSI_PAYLOAD_PAYLOAD_MASK) +/* RXFIFO Bit Fields */ +#define MIPI_DSI_RXFIFO_RXFIFO_MASK 0xFFFFFFFFu +#define MIPI_DSI_RXFIFO_RXFIFO_SHIFT 0 +#define MIPI_DSI_RXFIFO_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_RXFIFO_RXFIFO_SHIFT))&MIPI_DSI_RXFIFO_RXFIFO_MASK) +/* FIFOTHLD Bit Fields */ +#define MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK 0x1FFu +#define MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT 0 +#define MIPI_DSI_FIFOTHLD_WFULLLEVELSFR(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT))&MIPI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK) +/* FIFOCTRL Bit Fields */ +#define MIPI_DSI_FIFOCTRL_NINITMAIN_MASK 0x1u +#define MIPI_DSI_FIFOCTRL_NINITMAIN_SHIFT 0 +#define MIPI_DSI_FIFOCTRL_NINITSUB_MASK 0x2u +#define MIPI_DSI_FIFOCTRL_NINITSUB_SHIFT 1 +#define MIPI_DSI_FIFOCTRL_NLNITL80_MASK 0x4u +#define MIPI_DSI_FIFOCTRL_NLNITL80_SHIFT 2 +#define MIPI_DSI_FIFOCTRL_NINITSFR_MASK 0x8u +#define MIPI_DSI_FIFOCTRL_NINITSFR_SHIFT 3 +#define MIPI_DSI_FIFOCTRL_NINITRX_MASK 0x10u +#define MIPI_DSI_FIFOCTRL_NINITRX_SHIFT 4 +#define MIPI_DSI_FIFOCTRL_EMPTYLMAIN_MASK 0x100u +#define MIPI_DSI_FIFOCTRL_EMPTYLMAIN_SHIFT 8 +#define MIPI_DSI_FIFOCTRL_FULLLMAIN_MASK 0x200u +#define MIPI_DSI_FIFOCTRL_FULLLMAIN_SHIFT 9 +#define MIPI_DSI_FIFOCTRL_EMPTYHMAIN_MASK 0x400u +#define MIPI_DSI_FIFOCTRL_EMPTYHMAIN_SHIFT 10 +#define MIPI_DSI_FIFOCTRL_FULLHMAIN_MASK 0x800u +#define MIPI_DSI_FIFOCTRL_FULLHMAIN_SHIFT 11 +#define MIPI_DSI_FIFOCTRL_EMPTYLSUB_MASK 0x1000u +#define MIPI_DSI_FIFOCTRL_EMPTYLSUB_SHIFT 12 +#define MIPI_DSI_FIFOCTRL_FULLLSUB_MASK 0x2000u +#define MIPI_DSI_FIFOCTRL_FULLLSUB_SHIFT 13 +#define MIPI_DSI_FIFOCTRL_EMPTYHSUB_MASK 0x4000u +#define MIPI_DSI_FIFOCTRL_EMPTYHSUB_SHIFT 14 +#define MIPI_DSI_FIFOCTRL_FULLHSUB_MASK 0x8000u +#define MIPI_DSI_FIFOCTRL_FULLHSUB_SHIFT 15 +#define MIPI_DSI_FIFOCTRL_EMPTYLI80_MASK 0x10000u +#define MIPI_DSI_FIFOCTRL_EMPTYLI80_SHIFT 16 +#define MIPI_DSI_FIFOCTRL_FULLLI80_MASK 0x20000u +#define MIPI_DSI_FIFOCTRL_FULLLI80_SHIFT 17 +#define MIPI_DSI_FIFOCTRL_EMPTYHI80_MASK 0x40000u +#define MIPI_DSI_FIFOCTRL_EMPTYHI80_SHIFT 18 +#define MIPI_DSI_FIFOCTRL_FULLHI80_MASK 0x80000u +#define MIPI_DSI_FIFOCTRL_FULLHI80_SHIFT 19 +#define MIPI_DSI_FIFOCTRL_EMPTYLSFR_MASK 0x100000u +#define MIPI_DSI_FIFOCTRL_EMPTYLSFR_SHIFT 20 +#define MIPI_DSI_FIFOCTRL_FULLLSFR_MASK 0x200000u +#define MIPI_DSI_FIFOCTRL_FULLLSFR_SHIFT 21 +#define MIPI_DSI_FIFOCTRL_EMPTYHSFR_MASK 0x400000u +#define MIPI_DSI_FIFOCTRL_EMPTYHSFR_SHIFT 22 +#define MIPI_DSI_FIFOCTRL_FullHSfr_MASK 0x800000u +#define MIPI_DSI_FIFOCTRL_FullHSfr_SHIFT 23 +#define MIPI_DSI_FIFOCTRL_EMPTYRX_MASK 0x1000000u +#define MIPI_DSI_FIFOCTRL_EMPTYRX_SHIFT 24 +#define MIPI_DSI_FIFOCTRL_FULLRX_MASK 0x2000000u +#define MIPI_DSI_FIFOCTRL_FULLRX_SHIFT 25 +/* MEMACCHR Bit Fields */ +#define MIPI_DSI_MEMACCHR_EMAA_MD_MASK 0x7u +#define MIPI_DSI_MEMACCHR_EMAA_MD_SHIFT 0 +#define MIPI_DSI_MEMACCHR_EMAA_MD(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAA_MD_SHIFT))&MIPI_DSI_MEMACCHR_EMAA_MD_MASK) +#define MIPI_DSI_MEMACCHR_EMAB_MD_MASK 0x38u +#define MIPI_DSI_MEMACCHR_EMAB_MD_SHIFT 3 +#define MIPI_DSI_MEMACCHR_EMAB_MD(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAB_MD_SHIFT))&MIPI_DSI_MEMACCHR_EMAB_MD_MASK) +#define MIPI_DSI_MEMACCHR_RETN_MD_MASK 0x40u +#define MIPI_DSI_MEMACCHR_RETN_MD_SHIFT 6 +#define MIPI_DSI_MEMACCHR_PGEN_MD_MASK 0x80u +#define MIPI_DSI_MEMACCHR_PGEN_MD_SHIFT 7 +#define MIPI_DSI_MEMACCHR_EMAA_SD_MASK 0x700u +#define MIPI_DSI_MEMACCHR_EMAA_SD_SHIFT 8 +#define MIPI_DSI_MEMACCHR_EMAA_SD(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAA_SD_SHIFT))&MIPI_DSI_MEMACCHR_EMAA_SD_MASK) +#define MIPI_DSI_MEMACCHR_EMAB_SD_MASK 0x3800u +#define MIPI_DSI_MEMACCHR_EMAB_SD_SHIFT 11 +#define MIPI_DSI_MEMACCHR_EMAB_SD(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MEMACCHR_EMAB_SD_SHIFT))&MIPI_DSI_MEMACCHR_EMAB_SD_MASK) +#define MIPI_DSI_MEMACCHR_RETN_SD_MASK 0x4000u +#define MIPI_DSI_MEMACCHR_RETN_SD_SHIFT 14 +#define MIPI_DSI_MEMACCHR_PGEN_SD_MASK 0x8000u +#define MIPI_DSI_MEMACCHR_PGEN_SD_SHIFT 15 +/* MULTI_PKT Bit Fields */ +#define MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK 0xFFFFu +#define MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT 0 +#define MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT))&MIPI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK) +#define MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK 0xFFF0000u +#define MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT 16 +#define MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT))&MIPI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK) +#define MIPI_DSI_MULTI_PKT_PKT_GO_RDY_MASK 0x10000000u +#define MIPI_DSI_MULTI_PKT_PKT_GO_RDY_SHIFT 28 +#define MIPI_DSI_MULTI_PKT_PKT_GO_EN_MASK 0x20000000u +#define MIPI_DSI_MULTI_PKT_PKT_GO_EN_SHIFT 29 +#define MIPI_DSI_MULTI_PKT_MULTI_PKT_EN_MASK 0x40000000u +#define MIPI_DSI_MULTI_PKT_MULTI_PKT_EN_SHIFT 30 +/* PLLCTRL_1G Bit Fields */ +#define MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK 0x7u +#define MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT 0 +#define MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT))&MIPI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK) +#define MIPI_DSI_PLLCTRL_1G_PREPRCTL_MASK 0x70u +#define MIPI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT 4 +#define MIPI_DSI_PLLCTRL_1G_PREPRCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT))&MIPI_DSI_PLLCTRL_1G_PREPRCTL_MASK) +#define MIPI_DSI_PLLCTRL_1G_FREQ_BAND_MASK 0xF00u +#define MIPI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT 8 +#define MIPI_DSI_PLLCTRL_1G_FREQ_BAND(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT))&MIPI_DSI_PLLCTRL_1G_FREQ_BAND_MASK) +#define MIPI_DSI_PLLCTRL_1G_HSZEROCTL_MASK 0xF000u +#define MIPI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT 12 +#define MIPI_DSI_PLLCTRL_1G_HSZEROCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT))&MIPI_DSI_PLLCTRL_1G_HSZEROCTL_MASK) +/* PLLCTRL Bit Fields */ +#define MIPI_DSI_PLLCTRL_PMS_MASK 0xFFFFEu +#define MIPI_DSI_PLLCTRL_PMS_SHIFT 1 +#define MIPI_DSI_PLLCTRL_PMS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL_PMS_SHIFT))&MIPI_DSI_PLLCTRL_PMS_MASK) +#define MIPI_DSI_PLLCTRL_PLLEN_MASK 0x800000u +#define MIPI_DSI_PLLCTRL_PLLEN_SHIFT 23 +#define MIPI_DSI_PLLCTRL_DPDNSWAP_DAT_MASK 0x1000000u +#define MIPI_DSI_PLLCTRL_DPDNSWAP_DAT_SHIFT 24 +#define MIPI_DSI_PLLCTRL_DPDNSWAP_CLK_MASK 0x2000000u +#define MIPI_DSI_PLLCTRL_DPDNSWAP_CLK_SHIFT 25 +/* PLLCTRL1 Bit Fields */ +#define MIPI_DSI_PLLCTRL1_M_PLLCTL0_MASK 0xFFFFFFFFu +#define MIPI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT 0 +#define MIPI_DSI_PLLCTRL1_M_PLLCTL0(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT))&MIPI_DSI_PLLCTRL1_M_PLLCTL0_MASK) +/* PLLCTRL2 Bit Fields */ +#define MIPI_DSI_PLLCTRL2_M_PLLCTL1_MASK 0xFFu +#define MIPI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT 0 +#define MIPI_DSI_PLLCTRL2_M_PLLCTL1(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT))&MIPI_DSI_PLLCTRL2_M_PLLCTL1_MASK) +/* PLLTMR Bit Fields */ +#define MIPI_DSI_PLLTMR_PLLTIMER_MASK 0xFFFFFFFFu +#define MIPI_DSI_PLLTMR_PLLTIMER_SHIFT 0 +#define MIPI_DSI_PLLTMR_PLLTIMER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PLLTMR_PLLTIMER_SHIFT))&MIPI_DSI_PLLTMR_PLLTIMER_MASK) +/* PHYCTRL_B1 Bit Fields */ +#define MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK 0xFFFFFFFFu +#define MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT 0 +#define MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT))&MIPI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK) +/* PHYCTRL_B2 Bit Fields */ +#define MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK 0xFFFFFFFFu +#define MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT 0 +#define MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT))&MIPI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK) +/* PHYCTRL_M1 Bit Fields */ +#define MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK 0xFFFFFFFFu +#define MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT 0 +#define MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT))&MIPI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK) +/* PHYCTRL_M2 Bit Fields */ +#define MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK 0xFFFFFFFFu +#define MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT 0 +#define MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT))&MIPI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK) +/* PHYTIMING Bit Fields */ +#define MIPI_DSI_PHYTIMING_M_THSEXITCTL_MASK 0xFFu +#define MIPI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT 0 +#define MIPI_DSI_PHYTIMING_M_THSEXITCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT))&MIPI_DSI_PHYTIMING_M_THSEXITCTL_MASK) +#define MIPI_DSI_PHYTIMING_M_TLPXCTL_MASK 0xFF00u +#define MIPI_DSI_PHYTIMING_M_TLPXCTL_SHIFT 8 +#define MIPI_DSI_PHYTIMING_M_TLPXCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING_M_TLPXCTL_SHIFT))&MIPI_DSI_PHYTIMING_M_TLPXCTL_MASK) +/* PHYTIMING1 Bit Fields */ +#define MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK 0xFFu +#define MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT 0 +#define MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK) +#define MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK 0xFF00u +#define MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT 8 +#define MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK) +#define MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK 0xFF0000u +#define MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT 16 +#define MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK) +#define MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK 0xFF000000u +#define MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT 24 +#define MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT))&MIPI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK) +/* PHYTIMING2 Bit Fields */ +#define MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK 0xFFu +#define MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT 0 +#define MIPI_DSI_PHYTIMING2_M_THSTRAILCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT))&MIPI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK) +#define MIPI_DSI_PHYTIMING2_M_THSZEROCTL_MASK 0xFF00u +#define MIPI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT 8 +#define MIPI_DSI_PHYTIMING2_M_THSZEROCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT))&MIPI_DSI_PHYTIMING2_M_THSZEROCTL_MASK) +#define MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK 0xFF0000u +#define MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT 16 +#define MIPI_DSI_PHYTIMING2_M_THSPRPRCTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT))&MIPI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK) + +/*! + * @} + */ /* end of group MIPI_DSI_Register_Masks */ + + +/* MIPI_DSI - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI base address */ +#define MIPI_DSI_BASE (0x30760000u) +/** Peripheral MIPI_DSI base pointer */ +#define MIPI_DSI ((MIPI_DSI_Type *)MIPI_DSI_BASE) +#define MIPI_DSI_BASE_PTR (MIPI_DSI) +/** Array initializer of MIPI_DSI peripheral base adresses */ +#define MIPI_DSI_BASE_ADDRS { MIPI_DSI_BASE } +/** Array initializer of MIPI_DSI peripheral base pointers */ +#define MIPI_DSI_BASE_PTRS { MIPI_DSI } + +/* ---------------------------------------------------------------------------- + -- MIPI_DSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_Register_Accessor_Macros MIPI_DSI - Register accessor macros + * @{ + */ + + +/* MIPI_DSI - Register instance definitions */ +/* MIPI_DSI */ +#define MIPI_DSI_VERSION MIPI_DSI_VERSION_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_STATUS MIPI_DSI_STATUS_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_RGB_STATUS MIPI_DSI_RGB_STATUS_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_SWRST MIPI_DSI_SWRST_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_CLKCTRL MIPI_DSI_CLKCTRL_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_TIMEOUT MIPI_DSI_TIMEOUT_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_CONFIG MIPI_DSI_CONFIG_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_ESCMODE MIPI_DSI_ESCMODE_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_MDRESOL MIPI_DSI_MDRESOL_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_MVPORCH MIPI_DSI_MVPORCH_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_MHPORCH MIPI_DSI_MHPORCH_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_MSYNC MIPI_DSI_MSYNC_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_SDRESOL MIPI_DSI_SDRESOL_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_INTSRC MIPI_DSI_INTSRC_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_INTMSK MIPI_DSI_INTMSK_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PKTHDR MIPI_DSI_PKTHDR_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PAYLOAD MIPI_DSI_PAYLOAD_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_RXFIFO MIPI_DSI_RXFIFO_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_FIFOTHLD MIPI_DSI_FIFOTHLD_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_FIFOCTRL MIPI_DSI_FIFOCTRL_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_MEMACCHR MIPI_DSI_MEMACCHR_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_MULTI_PKT MIPI_DSI_MULTI_PKT_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PLLCTRL_1G MIPI_DSI_PLLCTRL_1G_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PLLCTRL MIPI_DSI_PLLCTRL_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PLLCTRL1 MIPI_DSI_PLLCTRL1_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PLLCTRL2 MIPI_DSI_PLLCTRL2_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PLLTMR MIPI_DSI_PLLTMR_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PHYCTRL_B1 MIPI_DSI_PHYCTRL_B1_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PHYCTRL_B2 MIPI_DSI_PHYCTRL_B2_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PHYCTRL_M1 MIPI_DSI_PHYCTRL_M1_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PHYCTRL_M2 MIPI_DSI_PHYCTRL_M2_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PHYTIMING MIPI_DSI_PHYTIMING_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PHYTIMING1 MIPI_DSI_PHYTIMING1_REG(MIPI_DSI_BASE_PTR) +#define MIPI_DSI_PHYTIMING2 MIPI_DSI_PHYTIMING2_REG(MIPI_DSI_BASE_PTR) + +/*! + * @} + */ /* end of group MIPI_DSI_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group MIPI_DSI_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_HSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_HSI_Peripheral_Access_Layer MIPI_HSI Peripheral Access Layer + * @{ + */ + +/** MIPI_HSI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t CSIS_CMN_CTRL; /**< CSIS Common Control, offset: 0x4 */ + __IO uint32_t CSIS_CLK_CTRL; /**< CSIS Clock gate Control, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSIS_INT_MSK; /**< CSIS Interrupt Mask, offset: 0x10 */ + __IO uint32_t CSIS_INT_SRC; /**< CSIS Interrupt Source, offset: 0x14 */ + uint8_t RESERVED_2[8]; + __IO uint32_t DPHY_STATUS; /**< D-PHY Status, offset: 0x20 */ + __IO uint32_t DPHY_CMN_CTRL; /**< D-PHY Common Control, offset: 0x24 */ + uint8_t RESERVED_3[8]; + __IO uint32_t DPHY_BCTRL_L; /**< D-PHY Master and Slave Control register low, offset: 0x30 */ + __IO uint32_t DPHY_BCTRL_H; /**< D-PHY Master and Slave Control register high, offset: 0x34 */ + __IO uint32_t DPHY_SCTRL_L; /**< D-PHY Slave Control register low, offset: 0x38 */ + __IO uint32_t DPHY_SCTRL_H; /**< D-PHY Slave Control register high, offset: 0x3C */ + __IO uint32_t ISP_CONFIG_CH0; /**< ISP Configuration register of CH0, offset: 0x40 */ + __IO uint32_t ISP_RESOL_CH0; /**< ISP Image Resolution register of CH0, offset: 0x44 */ + __IO uint32_t ISP_SYNC_CH0; /**< ISP SYNC register of CH0, offset: 0x48 */ + uint8_t RESERVED_4[52]; + __IO uint32_t SDW_CONFIG_CH0; /**< Shadow Configuration register of CH0, offset: 0x80 */ + __IO uint32_t SDW_RESOL_CH0; /**< Shadow Resolution register of CH0, offset: 0x84 */ + __IO uint32_t SDW_SYNC_CH0; /**< Shadow SYNC register of CH0, offset: 0x88 */ + uint8_t RESERVED_5[52]; + __IO uint32_t DBG_CTRL; /**< Debug Control register, offset: 0xC0 */ + __IO uint32_t DBG_INTR_MSK; /**< Debug Interrupt Mask, offset: 0xC4 */ + __IO uint32_t DBG_INTR_SRC; /**< Debug Interrupt Mask, offset: 0xC8 */ + uint8_t RESERVED_6[7988]; + __IO uint32_t NON_IMG_DATA; /**< Non Image Data, offset: 0x2000 */ +} MIPI_HSI_Type, *MIPI_HSI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- MIPI_HSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_HSI_Register_Accessor_Macros MIPI_HSI - Register accessor macros + * @{ + */ + + +/* MIPI_HSI - Register accessors */ +#define MIPI_HSI_CSIS_CMN_CTRL_REG(base) ((base)->CSIS_CMN_CTRL) +#define MIPI_HSI_CSIS_CLK_CTRL_REG(base) ((base)->CSIS_CLK_CTRL) +#define MIPI_HSI_CSIS_INT_MSK_REG(base) ((base)->CSIS_INT_MSK) +#define MIPI_HSI_CSIS_INT_SRC_REG(base) ((base)->CSIS_INT_SRC) +#define MIPI_HSI_DPHY_STATUS_REG(base) ((base)->DPHY_STATUS) +#define MIPI_HSI_DPHY_CMN_CTRL_REG(base) ((base)->DPHY_CMN_CTRL) +#define MIPI_HSI_DPHY_BCTRL_L_REG(base) ((base)->DPHY_BCTRL_L) +#define MIPI_HSI_DPHY_BCTRL_H_REG(base) ((base)->DPHY_BCTRL_H) +#define MIPI_HSI_DPHY_SCTRL_L_REG(base) ((base)->DPHY_SCTRL_L) +#define MIPI_HSI_DPHY_SCTRL_H_REG(base) ((base)->DPHY_SCTRL_H) +#define MIPI_HSI_ISP_CONFIG_CH0_REG(base) ((base)->ISP_CONFIG_CH0) +#define MIPI_HSI_ISP_RESOL_CH0_REG(base) ((base)->ISP_RESOL_CH0) +#define MIPI_HSI_ISP_SYNC_CH0_REG(base) ((base)->ISP_SYNC_CH0) +#define MIPI_HSI_SDW_CONFIG_CH0_REG(base) ((base)->SDW_CONFIG_CH0) +#define MIPI_HSI_SDW_RESOL_CH0_REG(base) ((base)->SDW_RESOL_CH0) +#define MIPI_HSI_SDW_SYNC_CH0_REG(base) ((base)->SDW_SYNC_CH0) +#define MIPI_HSI_DBG_CTRL_REG(base) ((base)->DBG_CTRL) +#define MIPI_HSI_DBG_INTR_MSK_REG(base) ((base)->DBG_INTR_MSK) +#define MIPI_HSI_DBG_INTR_SRC_REG(base) ((base)->DBG_INTR_SRC) +#define MIPI_HSI_NON_IMG_DATA_REG(base) ((base)->NON_IMG_DATA) + +/*! + * @} + */ /* end of group MIPI_HSI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MIPI_HSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_HSI_Register_Masks MIPI_HSI Register Masks + * @{ + */ + +/* CSIS_CMN_CTRL Bit Fields */ +#define MIPI_HSI_CSIS_CMN_CTRL_CSI_EN_MASK 0x1u +#define MIPI_HSI_CSIS_CMN_CTRL_CSI_EN_SHIFT 0 +#define MIPI_HSI_CSIS_CMN_CTRL_SW_REST_MASK 0x2u +#define MIPI_HSI_CSIS_CMN_CTRL_SW_REST_SHIFT 1 +#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_MASK 0x4u +#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_SHIFT 2 +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD3_MASK 0xF8u +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD3_SHIFT 3 +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_RSVD3_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_RSVD3_MASK) +#define MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_MASK 0x300u +#define MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT 8 +#define MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_LANE_NUMBER_MASK) +#define MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK 0xC00u +#define MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT 10 +#define MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_INTERLEAVE_MODE_MASK) +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD2_MASK 0xF000u +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD2_SHIFT 12 +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_RSVD2_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_RSVD2_MASK) +#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK 0xF0000u +#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT 16 +#define MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_UPDATE_SHADOW_MASK) +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD1_MASK 0xFFF00000u +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD1_SHIFT 20 +#define MIPI_HSI_CSIS_CMN_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CMN_CTRL_RSVD1_SHIFT))&MIPI_HSI_CSIS_CMN_CTRL_RSVD1_MASK) +/* CSIS_CLK_CTRL Bit Fields */ +#define MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_MASK 0xFu +#define MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_SHIFT 0 +#define MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_WCLK_SRC_MASK) +#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_MASK 0xF0u +#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT 4 +#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_EN_MASK) +#define MIPI_HSI_CSIS_CLK_CTRL_RSVD4_MASK 0xFF00u +#define MIPI_HSI_CSIS_CLK_CTRL_RSVD4_SHIFT 8 +#define MIPI_HSI_CSIS_CLK_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_RSVD4_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_RSVD4_MASK) +#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK 0xFFFF0000u +#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT 16 +#define MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_SHIFT))&MIPI_HSI_CSIS_CLK_CTRL_CLKGATE_TRAIL_MASK) +/* CSIS_INT_MSK Bit Fields */ +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_id_MASK 0x1u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_id_SHIFT 0 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_CRC_MASK 0x2u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_CRC_SHIFT 1 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_ECC_MASK 0x4u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_ECC_SHIFT 2 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_MASK 0x8u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_WRONG_CFG_SHIFT 3 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_MASK 0xF0u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT 4 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_OVER_MASK) +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK 0xF00u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT 8 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FE_MASK) +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK 0xF000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT 12 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_LOST_FS_MASK) +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK 0xF0000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT 16 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_ERR_SOT_HS_MASK) +#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_MASK 0xF00000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT 20 +#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_FRAMEEND_MASK) +#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_MASK 0xF000000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT 24 +#define MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_SHIFT))&MIPI_HSI_CSIS_INT_MSK_MSK_FRAMESTART_MASK) +#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDAFTER_MASK 0x10000000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDAFTER_SHIFT 28 +#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDBEFORE_MASK 0x20000000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_ODDBEFORE_SHIFT 29 +#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENAFTER_MASK 0x40000000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENAFTER_SHIFT 30 +#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENBEFORE_MASK 0x80000000u +#define MIPI_HSI_CSIS_INT_MSK_MSK_EVENBEFORE_SHIFT 31 +/* CSIS_INT_SRC Bit Fields */ +#define MIPI_HSI_CSIS_INT_SRC_ERR_ID_MASK 0x1u +#define MIPI_HSI_CSIS_INT_SRC_ERR_ID_SHIFT 0 +#define MIPI_HSI_CSIS_INT_SRC_ERR_CRC_MASK 0x2u +#define MIPI_HSI_CSIS_INT_SRC_ERR_CRC_SHIFT 1 +#define MIPI_HSI_CSIS_INT_SRC_ERR_ECC_MASK 0x4u +#define MIPI_HSI_CSIS_INT_SRC_ERR_ECC_SHIFT 2 +#define MIPI_HSI_CSIS_INT_SRC_ERR_WRONG_CFG_MASK 0x8u +#define MIPI_HSI_CSIS_INT_SRC_ERR_WRONG_CFG_SHIFT 3 +#define MIPI_HSI_CSIS_INT_SRC_ERR_OVER_MASK 0xF0u +#define MIPI_HSI_CSIS_INT_SRC_ERR_OVER_SHIFT 4 +#define MIPI_HSI_CSIS_INT_SRC_ERR_OVER(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_OVER_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_OVER_MASK) +#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_MASK 0xF00u +#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_SHIFT 8 +#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FE_MASK) +#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_MASK 0xF000u +#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_SHIFT 12 +#define MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_LOST_FS_MASK) +#define MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_MASK 0xF0000u +#define MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_SHIFT 16 +#define MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_SHIFT))&MIPI_HSI_CSIS_INT_SRC_ERR_SOT_HS_MASK) +#define MIPI_HSI_CSIS_INT_SRC_FRAMEEND_MASK 0xF00000u +#define MIPI_HSI_CSIS_INT_SRC_FRAMEEND_SHIFT 20 +#define MIPI_HSI_CSIS_INT_SRC_FRAMEEND(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_FRAMEEND_SHIFT))&MIPI_HSI_CSIS_INT_SRC_FRAMEEND_MASK) +#define MIPI_HSI_CSIS_INT_SRC_FRAMESTART_MASK 0xF000000u +#define MIPI_HSI_CSIS_INT_SRC_FRAMESTART_SHIFT 24 +#define MIPI_HSI_CSIS_INT_SRC_FRAMESTART(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_CSIS_INT_SRC_FRAMESTART_SHIFT))&MIPI_HSI_CSIS_INT_SRC_FRAMESTART_MASK) +#define MIPI_HSI_CSIS_INT_SRC_ODDAFTER_MASK 0x10000000u +#define MIPI_HSI_CSIS_INT_SRC_ODDAFTER_SHIFT 28 +#define MIPI_HSI_CSIS_INT_SRC_ODDBEFORE_MASK 0x20000000u +#define MIPI_HSI_CSIS_INT_SRC_ODDBEFORE_SHIFT 29 +#define MIPI_HSI_CSIS_INT_SRC_EVENAFTER_MASK 0x40000000u +#define MIPI_HSI_CSIS_INT_SRC_EVENAFTER_SHIFT 30 +#define MIPI_HSI_CSIS_INT_SRC_EVENBEFORE_MASK 0x80000000u +#define MIPI_HSI_CSIS_INT_SRC_EVENBEFORE_SHIFT 31 +/* DPHY_STATUS Bit Fields */ +#define MIPI_HSI_DPHY_STATUS_STOPSTATECLK_MASK 0x1u +#define MIPI_HSI_DPHY_STATUS_STOPSTATECLK_SHIFT 0 +#define MIPI_HSI_DPHY_STATUS_ULPSCLK_MASK 0x2u +#define MIPI_HSI_DPHY_STATUS_ULPSCLK_SHIFT 1 +#define MIPI_HSI_DPHY_STATUS_RSVD6_MASK 0xCu +#define MIPI_HSI_DPHY_STATUS_RSVD6_SHIFT 2 +#define MIPI_HSI_DPHY_STATUS_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_RSVD6_SHIFT))&MIPI_HSI_DPHY_STATUS_RSVD6_MASK) +#define MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_MASK 0xF0u +#define MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_SHIFT 4 +#define MIPI_HSI_DPHY_STATUS_STOPSTATEDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_SHIFT))&MIPI_HSI_DPHY_STATUS_STOPSTATEDAT_MASK) +#define MIPI_HSI_DPHY_STATUS_ULPSDAT_MASK 0xF00u +#define MIPI_HSI_DPHY_STATUS_ULPSDAT_SHIFT 8 +#define MIPI_HSI_DPHY_STATUS_ULPSDAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_ULPSDAT_SHIFT))&MIPI_HSI_DPHY_STATUS_ULPSDAT_MASK) +#define MIPI_HSI_DPHY_STATUS_RSVD5_MASK 0xFFFFF000u +#define MIPI_HSI_DPHY_STATUS_RSVD5_SHIFT 12 +#define MIPI_HSI_DPHY_STATUS_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_STATUS_RSVD5_SHIFT))&MIPI_HSI_DPHY_STATUS_RSVD5_MASK) +/* DPHY_CMN_CTRL Bit Fields */ +#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_CLK_MASK 0x1u +#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_CLK_SHIFT 0 +#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_MASK 0x1Eu +#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT 1 +#define MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_ENABLE_DAT_MASK) +#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_MASK 0x20u +#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT_SHIFT 5 +#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_MASK 0x40u +#define MIPI_HSI_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK_SHIFT 6 +#define MIPI_HSI_DPHY_CMN_CTRL_RSVD7_MASK 0x3FFF80u +#define MIPI_HSI_DPHY_CMN_CTRL_RSVD7_SHIFT 7 +#define MIPI_HSI_DPHY_CMN_CTRL_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_RSVD7_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_RSVD7_MASK) +#define MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK 0xC00000u +#define MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT 22 +#define MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_S_CLKSETTLECTL_MASK) +#define MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_MASK 0xFF000000u +#define MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_SHIFT 24 +#define MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_SHIFT))&MIPI_HSI_DPHY_CMN_CTRL_HSSETTLE_MASK) +/* DPHY_BCTRL_L Bit Fields */ +#define MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT 0 +#define MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_BCTRL_L_B_DPHYCTRL_MASK) +/* DPHY_BCTRL_H Bit Fields */ +#define MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT 0 +#define MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_BCTRL_H_B_DPHYCTRL_MASK) +/* DPHY_SCTRL_L Bit Fields */ +#define MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT 0 +#define MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_SCTRL_L_S_DPHYCTRL_MASK) +/* DPHY_SCTRL_H Bit Fields */ +#define MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_MASK 0xFFFFFFFFu +#define MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT 0 +#define MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_SHIFT))&MIPI_HSI_DPHY_SCTRL_H_S_DPHYCTRL_MASK) +/* ISP_CONFIG_CH0 Bit Fields */ +#define MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u +#define MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0 +#define MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_VIRTUAL_CHANNEL_MASK) +#define MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_MASK 0xFCu +#define MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_SHIFT 2 +#define MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_DATAFORMAT_MASK) +#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_EN_MASK 0x100u +#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_EN_SHIFT 8 +#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_PREDICT_MASK 0x200u +#define MIPI_HSI_ISP_CONFIG_CH0_DECOMP_PREDICT_SHIFT 9 +#define MIPI_HSI_ISP_CONFIG_CH0_RGB_SWAP_MASK 0x400u +#define MIPI_HSI_ISP_CONFIG_CH0_RGB_SWAP_SHIFT 10 +#define MIPI_HSI_ISP_CONFIG_CH0_PARALLEL_MASK 0x800u +#define MIPI_HSI_ISP_CONFIG_CH0_PARALLEL_SHIFT 11 +#define MIPI_HSI_ISP_CONFIG_CH0_DOUBLE_CMPNT_MASK 0x1000u +#define MIPI_HSI_ISP_CONFIG_CH0_DOUBLE_CMPNT_SHIFT 12 +#define MIPI_HSI_ISP_CONFIG_CH0_RSVD8_MASK 0xFFE000u +#define MIPI_HSI_ISP_CONFIG_CH0_RSVD8_SHIFT 13 +#define MIPI_HSI_ISP_CONFIG_CH0_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_RSVD8_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_RSVD8_MASK) +#define MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK 0xFF000000u +#define MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT 24 +#define MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_SHIFT))&MIPI_HSI_ISP_CONFIG_CH0_MEM_FULL_GAP_MASK) +/* ISP_RESOL_CH0 Bit Fields */ +#define MIPI_HSI_ISP_RESOL_CH0_HRESOL_MASK 0xFFFFu +#define MIPI_HSI_ISP_RESOL_CH0_HRESOL_SHIFT 0 +#define MIPI_HSI_ISP_RESOL_CH0_HRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_RESOL_CH0_HRESOL_SHIFT))&MIPI_HSI_ISP_RESOL_CH0_HRESOL_MASK) +#define MIPI_HSI_ISP_RESOL_CH0_VRESOL_MASK 0xFFFF0000u +#define MIPI_HSI_ISP_RESOL_CH0_VRESOL_SHIFT 16 +#define MIPI_HSI_ISP_RESOL_CH0_VRESOL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_RESOL_CH0_VRESOL_SHIFT))&MIPI_HSI_ISP_RESOL_CH0_VRESOL_MASK) +/* ISP_SYNC_CH0 Bit Fields */ +#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_MASK 0xFFFu +#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT 0 +#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_VSYNC_EINTV_MASK) +#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_MASK 0x3F000u +#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT 12 +#define MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_VSYNC_SINTV_MASK) +#define MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_MASK 0xFC0000u +#define MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT 18 +#define MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_HSYNC_LINTV_MASK) +#define MIPI_HSI_ISP_SYNC_CH0_RSVD9_MASK 0xFF000000u +#define MIPI_HSI_ISP_SYNC_CH0_RSVD9_SHIFT 24 +#define MIPI_HSI_ISP_SYNC_CH0_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_ISP_SYNC_CH0_RSVD9_SHIFT))&MIPI_HSI_ISP_SYNC_CH0_RSVD9_MASK) +/* SDW_CONFIG_CH0 Bit Fields */ +#define MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK 0x3u +#define MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT 0 +#define MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_VIRTUAL_CHANNEL_MASK) +#define MIPI_HSI_SDW_CONFIG_CH0_DataFormat_MASK 0xFCu +#define MIPI_HSI_SDW_CONFIG_CH0_DataFormat_SHIFT 2 +#define MIPI_HSI_SDW_CONFIG_CH0_DataFormat(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_DataFormat_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_DataFormat_MASK) +#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_EN_SDW_MASK 0x100u +#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_EN_SDW_SHIFT 8 +#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_MASK 0x200u +#define MIPI_HSI_SDW_CONFIG_CH0_DECOMP_PREDICT_SDW_SHIFT 9 +#define MIPI_HSI_SDW_CONFIG_CH0_RGB_SWAP_SDW_MASK 0x400u +#define MIPI_HSI_SDW_CONFIG_CH0_RGB_SWAP_SDW_SHIFT 10 +#define MIPI_HSI_SDW_CONFIG_CH0_PARALLEL_SDW_MASK 0x800u +#define MIPI_HSI_SDW_CONFIG_CH0_PARALLEL_SDW_SHIFT 11 +#define MIPI_HSI_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_MASK 0x1000u +#define MIPI_HSI_SDW_CONFIG_CH0_DOUBLE_CMPNT_SDW_SHIFT 12 +#define MIPI_HSI_SDW_CONFIG_CH0_RSVD10_MASK 0xFFE000u +#define MIPI_HSI_SDW_CONFIG_CH0_RSVD10_SHIFT 13 +#define MIPI_HSI_SDW_CONFIG_CH0_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_RSVD10_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_RSVD10_MASK) +#define MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK 0xFF000000u +#define MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT 24 +#define MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_SHIFT))&MIPI_HSI_SDW_CONFIG_CH0_NAMEMEM_FULL_GAP_SDW_MASK) +/* SDW_RESOL_CH0 Bit Fields */ +#define MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_MASK 0xFFFFu +#define MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_SHIFT 0 +#define MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_SHIFT))&MIPI_HSI_SDW_RESOL_CH0_HRESOL_SDW_MASK) +#define MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_MASK 0xFFFF0000u +#define MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_SHIFT 16 +#define MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_SHIFT))&MIPI_HSI_SDW_RESOL_CH0_VRESOL_SDW_MASK) +/* SDW_SYNC_CH0 Bit Fields */ +#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK 0xFFFu +#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT 0 +#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_VSYNC_EINTV_SDW_MASK) +#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK 0x3F000u +#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT 12 +#define MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_VSYNC_SINTV_SDW_MASK) +#define MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK 0xFC0000u +#define MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT 18 +#define MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_HSYNC_LINTV_SDW_MASK) +#define MIPI_HSI_SDW_SYNC_CH0_RSVD11_MASK 0xFF000000u +#define MIPI_HSI_SDW_SYNC_CH0_RSVD11_SHIFT 24 +#define MIPI_HSI_SDW_SYNC_CH0_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_SDW_SYNC_CH0_RSVD11_SHIFT))&MIPI_HSI_SDW_SYNC_CH0_RSVD11_MASK) +/* DBG_CTRL Bit Fields */ +#define MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_MASK 0xFu +#define MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_SHIFT 0 +#define MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_CH_OUTPUT_MASK) +#define MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK 0xF0u +#define MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT 4 +#define MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_BLK_EXC_FRAME_MASK) +#define MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK 0xF00u +#define MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT 8 +#define MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_DONT_STOP_LAST_LINE_MASK) +#define MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_MASK 0xF000u +#define MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT 12 +#define MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_SHIFT))&MIPI_HSI_DBG_CTRL_DBG_FORCE_UPDATE_MASK) +#define MIPI_HSI_DBG_CTRL_RSVD12_MASK 0xFFFF0000u +#define MIPI_HSI_DBG_CTRL_RSVD12_SHIFT 16 +#define MIPI_HSI_DBG_CTRL_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_CTRL_RSVD12_SHIFT))&MIPI_HSI_DBG_CTRL_RSVD12_MASK) +/* DBG_INTR_MSK Bit Fields */ +#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK 0xFu +#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT 0 +#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_SHIFT))&MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_RISE_MASK) +#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK 0xF0u +#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT 4 +#define MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_SHIFT))&MIPI_HSI_DBG_INTR_MSK_CAM_VSYNC_FALL_MASK) +#define MIPI_HSI_DBG_INTR_MSK_EARLY_FS_MASK 0xF00u +#define MIPI_HSI_DBG_INTR_MSK_EARLY_FS_SHIFT 8 +#define MIPI_HSI_DBG_INTR_MSK_EARLY_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_EARLY_FS_SHIFT))&MIPI_HSI_DBG_INTR_MSK_EARLY_FS_MASK) +#define MIPI_HSI_DBG_INTR_MSK_EARLY_FE_MASK 0xF000u +#define MIPI_HSI_DBG_INTR_MSK_EARLY_FE_SHIFT 12 +#define MIPI_HSI_DBG_INTR_MSK_EARLY_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_EARLY_FE_SHIFT))&MIPI_HSI_DBG_INTR_MSK_EARLY_FE_MASK) +#define MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_MASK 0xF0000u +#define MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT 16 +#define MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_SHIFT))&MIPI_HSI_DBG_INTR_MSK_TRUNCATED_FRAME_MASK) +#define MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK 0xF00000u +#define MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT 20 +#define MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_SHIFT))&MIPI_HSI_DBG_INTR_MSK_ERR_FRAME_SIZE_MASK) +#define MIPI_HSI_DBG_INTR_MSK_DT_IGNORE_MASK 0x1000000u +#define MIPI_HSI_DBG_INTR_MSK_DT_IGNORE_SHIFT 24 +#define MIPI_HSI_DBG_INTR_MSK_DT_NOT_SUPPORT_MASK 0x2000000u +#define MIPI_HSI_DBG_INTR_MSK_DT_NOT_SUPPORT_SHIFT 25 +#define MIPI_HSI_DBG_INTR_MSK_RSVD13_MASK 0xFC000000u +#define MIPI_HSI_DBG_INTR_MSK_RSVD13_SHIFT 26 +#define MIPI_HSI_DBG_INTR_MSK_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_MSK_RSVD13_SHIFT))&MIPI_HSI_DBG_INTR_MSK_RSVD13_MASK) +/* DBG_INTR_SRC Bit Fields */ +#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK 0xFu +#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT 0 +#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_SHIFT))&MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_RISE_MASK) +#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK 0xF0u +#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT 4 +#define MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_SHIFT))&MIPI_HSI_DBG_INTR_SRC_CAM_VSYNC_FALL_MASK) +#define MIPI_HSI_DBG_INTR_SRC_EARLY_FS_MASK 0xF00u +#define MIPI_HSI_DBG_INTR_SRC_EARLY_FS_SHIFT 8 +#define MIPI_HSI_DBG_INTR_SRC_EARLY_FS(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_EARLY_FS_SHIFT))&MIPI_HSI_DBG_INTR_SRC_EARLY_FS_MASK) +#define MIPI_HSI_DBG_INTR_SRC_EARLY_FE_MASK 0xF000u +#define MIPI_HSI_DBG_INTR_SRC_EARLY_FE_SHIFT 12 +#define MIPI_HSI_DBG_INTR_SRC_EARLY_FE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_EARLY_FE_SHIFT))&MIPI_HSI_DBG_INTR_SRC_EARLY_FE_MASK) +#define MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_MASK 0xF0000u +#define MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT 16 +#define MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_SHIFT))&MIPI_HSI_DBG_INTR_SRC_TRUNCATED_FRAME_MASK) +#define MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK 0xF00000u +#define MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT 20 +#define MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_SHIFT))&MIPI_HSI_DBG_INTR_SRC_ERR_FRAME_SIZE_MASK) +#define MIPI_HSI_DBG_INTR_SRC_DT_IGNORE_MASK 0x1000000u +#define MIPI_HSI_DBG_INTR_SRC_DT_IGNORE_SHIFT 24 +#define MIPI_HSI_DBG_INTR_SRC_DT_NOT_SUPPURT_MASK 0x2000000u +#define MIPI_HSI_DBG_INTR_SRC_DT_NOT_SUPPURT_SHIFT 25 +#define MIPI_HSI_DBG_INTR_SRC_RSVD14_MASK 0xFC000000u +#define MIPI_HSI_DBG_INTR_SRC_RSVD14_SHIFT 26 +#define MIPI_HSI_DBG_INTR_SRC_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_DBG_INTR_SRC_RSVD14_SHIFT))&MIPI_HSI_DBG_INTR_SRC_RSVD14_MASK) +/* NON_IMG_DATA Bit Fields */ +#define MIPI_HSI_NON_IMG_DATA_NONIMGDATA_MASK 0xFFFFFFFFu +#define MIPI_HSI_NON_IMG_DATA_NONIMGDATA_SHIFT 0 +#define MIPI_HSI_NON_IMG_DATA_NONIMGDATA(x) (((uint32_t)(((uint32_t)(x))<<MIPI_HSI_NON_IMG_DATA_NONIMGDATA_SHIFT))&MIPI_HSI_NON_IMG_DATA_NONIMGDATA_MASK) + +/*! + * @} + */ /* end of group MIPI_HSI_Register_Masks */ + + +/* MIPI_HSI - Peripheral instance base addresses */ +/** Peripheral MIPI_HSI base address */ +#define MIPI_HSI_BASE (0x30750000u) +/** Peripheral MIPI_HSI base pointer */ +#define MIPI_HSI ((MIPI_HSI_Type *)MIPI_HSI_BASE) +#define MIPI_HSI_BASE_PTR (MIPI_HSI) +/** Array initializer of MIPI_HSI peripheral base adresses */ +#define MIPI_HSI_BASE_ADDRS { MIPI_HSI_BASE } +/** Array initializer of MIPI_HSI peripheral base pointers */ +#define MIPI_HSI_BASE_PTRS { MIPI_HSI } + +/* ---------------------------------------------------------------------------- + -- MIPI_HSI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_HSI_Register_Accessor_Macros MIPI_HSI - Register accessor macros + * @{ + */ + + +/* MIPI_HSI - Register instance definitions */ +/* MIPI_HSI */ +#define MIPI_HSI_CSIS_CMN_CTRL MIPI_HSI_CSIS_CMN_CTRL_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_CSIS_CLK_CTRL MIPI_HSI_CSIS_CLK_CTRL_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_CSIS_INT_MSK MIPI_HSI_CSIS_INT_MSK_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_CSIS_INT_SRC MIPI_HSI_CSIS_INT_SRC_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DPHY_STATUS MIPI_HSI_DPHY_STATUS_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DPHY_CMN_CTRL MIPI_HSI_DPHY_CMN_CTRL_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DPHY_BCTRL_L MIPI_HSI_DPHY_BCTRL_L_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DPHY_BCTRL_H MIPI_HSI_DPHY_BCTRL_H_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DPHY_SCTRL_L MIPI_HSI_DPHY_SCTRL_L_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DPHY_SCTRL_H MIPI_HSI_DPHY_SCTRL_H_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_ISP_CONFIG_CH0 MIPI_HSI_ISP_CONFIG_CH0_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_ISP_RESOL_CH0 MIPI_HSI_ISP_RESOL_CH0_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_ISP_SYNC_CH0 MIPI_HSI_ISP_SYNC_CH0_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_SDW_CONFIG_CH0 MIPI_HSI_SDW_CONFIG_CH0_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_SDW_RESOL_CH0 MIPI_HSI_SDW_RESOL_CH0_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_SDW_SYNC_CH0 MIPI_HSI_SDW_SYNC_CH0_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DBG_CTRL MIPI_HSI_DBG_CTRL_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DBG_INTR_MSK MIPI_HSI_DBG_INTR_MSK_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_DBG_INTR_SRC MIPI_HSI_DBG_INTR_SRC_REG(MIPI_HSI_BASE_PTR) +#define MIPI_HSI_NON_IMG_DATA MIPI_HSI_NON_IMG_DATA_REG(MIPI_HSI_BASE_PTR) + +/*! + * @} + */ /* end of group MIPI_HSI_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group MIPI_HSI_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- MU Peripheral Access Layer + ---------------------------------------------------------------------------- */ +typedef struct { + __IO uint32_t TR[4]; /**< Processor B Transmit Register 0, offset: 0x0 */ + __I uint32_t RR[4]; /**< Processor B Receive Register 0, offset: 0x10 */ + __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */ + __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */ +} MU_Type, *MU_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- MU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros + * @{ + */ + + +/* MU - Register accessors */ +#define MU_TR_REG(base,index) ((base)->TR[index]) +#define MU_TR_COUNT 4 +#define MU_RR_REG(base,index) ((base)->RR[index]) +#define MU_RR_COUNT 4 +#define MU_SR_REG(base) ((base)->SR) +#define MU_CR_REG(base) ((base)->CR) + +/*! + * @} + */ /* end of group MU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ +/* TR Bit Fields */ +#define MU_TR_DATA_MASK 0xFFFFFFFFu +#define MU_TR_DATA_SHIFT 0 +#define MU_TR_DATA_WIDTH 32 +#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x))<<MU_TR_DATA_SHIFT))&MU_TR_DATA_MASK) +/* RR Bit Fields */ +#define MU_RR_DATA_MASK 0xFFFFFFFFu +#define MU_RR_DATA_SHIFT 0 +#define MU_RR_DATA_WIDTH 32 +#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x))<<MU_RR_DATA_SHIFT))&MU_RR_DATA_MASK) +/* SR Bit Fields */ +#define MU_SR_Fn_MASK 0x7u +#define MU_SR_Fn_SHIFT 0 +#define MU_SR_Fn_WIDTH 3 +#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_Fn_SHIFT))&MU_SR_Fn_MASK) +#define MU_SR_EP_MASK 0x10u +#define MU_SR_EP_SHIFT 4 +#define MU_SR_EP_WIDTH 1 +#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_EP_SHIFT))&MU_SR_EP_MASK) +#define MU_SR_PM_MASK 0x60u +#define MU_SR_PM_SHIFT 5 +#define MU_SR_PM_WIDTH 2 +#define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_PM_SHIFT))&MU_SR_PM_MASK) +#define MU_SR_RS_MASK 0x80u +#define MU_SR_RS_SHIFT 7 +#define MU_SR_RS_WIDTH 1 +#define MU_SR_RS(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_RS_SHIFT))&MU_SR_RS_MASK) +#define MU_SR_FUP_MASK 0x100u +#define MU_SR_FUP_SHIFT 8 +#define MU_SR_FUP_WIDTH 1 +#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_FUP_SHIFT))&MU_SR_FUP_MASK) +#define MU_SR_TEn_MASK 0xF00000u +#define MU_SR_TEn_SHIFT 20 +#define MU_SR_TEn_WIDTH 4 +#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_TEn_SHIFT))&MU_SR_TEn_MASK) +#define MU_SR_RFn_MASK 0xF000000u +#define MU_SR_RFn_SHIFT 24 +#define MU_SR_RFn_WIDTH 4 +#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_RFn_SHIFT))&MU_SR_RFn_MASK) +#define MU_SR_GIPn_MASK 0xF0000000u +#define MU_SR_GIPn_SHIFT 28 +#define MU_SR_GIPn_WIDTH 4 +#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x))<<MU_SR_GIPn_SHIFT))&MU_SR_GIPn_MASK) +/* CR Bit Fields */ +#define MU_CR_Fn_MASK 0x7u +#define MU_CR_Fn_SHIFT 0 +#define MU_CR_Fn_WIDTH 3 +#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_Fn_SHIFT))&MU_CR_Fn_MASK) +#define MU_CR_GIRn_MASK 0xF0000u +#define MU_CR_GIRn_SHIFT 16 +#define MU_CR_GIRn_WIDTH 4 +#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_GIRn_SHIFT))&MU_CR_GIRn_MASK) +#define MU_CR_TIEn_MASK 0xF00000u +#define MU_CR_TIEn_SHIFT 20 +#define MU_CR_TIEn_WIDTH 4 +#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_TIEn_SHIFT))&MU_CR_TIEn_MASK) +#define MU_CR_RIEn_MASK 0xF000000u +#define MU_CR_RIEn_SHIFT 24 +#define MU_CR_RIEn_WIDTH 4 +#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_RIEn_SHIFT))&MU_CR_RIEn_MASK) +#define MU_CR_GIEn_MASK 0xF0000000u +#define MU_CR_GIEn_SHIFT 28 +#define MU_CR_GIEn_WIDTH 4 +#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x))<<MU_CR_GIEn_SHIFT))&MU_CR_GIEn_MASK) + +/*! + * @} + */ /* end of group MU_Register_Masks */ + + +/* MU - Peripheral instance base addresses */ +/** Peripheral MU0_B base address */ +#define MU0_B_BASE (0x30AB0000u) +/** Peripheral MU0_B base pointer */ +#define MU0_B ((MU_Type *)MU0_B_BASE) +#define MU0_B_BASE_PTR (MU0_B) +/** Array initializer of MU peripheral base adresses */ +#define MU_BASE_ADDRS { MU0_B_BASE } +/** Array initializer of MU peripheral base pointers */ +#define MU_BASE_PTRS { MU0_B } + +/* ---------------------------------------------------------------------------- + -- MU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Accessor_Macros MU - Register accessor macros + * @{ + */ + + +/* MU - Register instance definitions */ +/* MU0_B */ +#define MU0_B_TR0 MU_TR_REG(MU0_B,0) +#define MU0_B_TR1 MU_TR_REG(MU0_B,1) +#define MU0_B_TR2 MU_TR_REG(MU0_B,2) +#define MU0_B_TR3 MU_TR_REG(MU0_B,3) +#define MU0_B_RR0 MU_RR_REG(MU0_B,0) +#define MU0_B_RR1 MU_RR_REG(MU0_B,1) +#define MU0_B_RR2 MU_RR_REG(MU0_B,2) +#define MU0_B_RR3 MU_RR_REG(MU0_B,3) +#define MU0_B_SR MU_SR_REG(MU0_B) +#define MU0_B_CR MU_CR_REG(MU0_B) + +/*! + * @} + */ /* end of group MU_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group MU_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA0; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DATA1; /**< OTP Controller Write Data Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t DATA2; /**< OTP Controller Write Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t DATA3; /**< OTP Controller Write Data Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __IO uint32_t READ_FUSE_DATA0; /**< OTP Controller Read Data Register, offset: 0x70 */ + uint8_t RESERVED_6[12]; + __IO uint32_t READ_FUSE_DATA1; /**< OTP Controller Read Data Register, offset: 0x80 */ + uint8_t RESERVED_7[12]; + __IO uint32_t READ_FUSE_DATA2; /**< OTP Controller Read Data Register, offset: 0x90 */ + uint8_t RESERVED_8[12]; + __IO uint32_t READ_FUSE_DATA3; /**< OTP Controller Read Data Register, offset: 0xA0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0xB0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0xC0 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0xC4 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0xC8 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0xCC */ + __IO uint32_t CRC_ADDR; /**< OTP Controller CRC test address, offset: 0xD0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CRC_VALUE; /**< OTP Controller CRC Value Register, offset: 0xE0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t VERSION; /**< OTP Controller Version Register, offset: 0xF0 */ + uint8_t RESERVED_13[780]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_14[12]; + __IO uint32_t TESTER0; /**< Value of OTP Bank0 Word1 (Tester Information), offset: 0x410 */ + uint8_t RESERVED_15[12]; + __IO uint32_t TESTER1; /**< Value of OTP Bank0 Word2 (Tester Information), offset: 0x420 */ + uint8_t RESERVED_16[12]; + __IO uint32_t TESTER2; /**< Value of OTP Bank0 Word3 (Tester Information), offset: 0x430 */ + uint8_t RESERVED_17[12]; + __IO uint32_t TESTER3; /**< Value of OTP Bank1 Word0 (Tester Information), offset: 0x440 */ + uint8_t RESERVED_18[12]; + __IO uint32_t TESTER4; /**< Value of OTP Bank1 Word1 (Tester Information), offset: 0x450 */ + uint8_t RESERVED_19[12]; + __IO uint32_t TESTER5; /**< Value of OTP Bank1 Word2 (Tester Information), offset: 0x460 */ + uint8_t RESERVED_20[12]; + __IO uint32_t BOOT_CFG0; /**< Value of OTP Bank1 Word3 (Boot Configuration Information), offset: 0x470 */ + uint8_t RESERVED_21[12]; + __IO uint32_t BOOT_CFG1; /**< Value of OTP Bank2 Word0 (Boot Configuration Information), offset: 0x480 */ + uint8_t RESERVED_22[12]; + __IO uint32_t BOOT_CFG2; /**< Value of OTP Bank2 Word1 (Boot Configuration Information), offset: 0x490 */ + uint8_t RESERVED_23[12]; + __IO uint32_t BOOT_CFG3; /**< Value of OTP Bank2 Word2 (Boot Configuration Information), offset: 0x4A0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t BOOT_CFG4; /**< Value of OTP Bank2 Word3 (BOOT Configuration Information), offset: 0x4B0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t MEM_TRIM0; /**< Value of OTP Bank3 Word0 (Memory Related Information), offset: 0x4C0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t MEM_TRIM1; /**< Value of OTP Bank3 Word1 (Memory Related Information), offset: 0x4D0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank3 Word2 (Analog Information), offset: 0x4E0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank3 Word3 (Analog Info.), offset: 0x4F0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t OTPMK0; /**< Shadow Register for OTP Bank4 Word0 (OTPMK Key), offset: 0x500 */ + uint8_t RESERVED_30[12]; + __IO uint32_t OTPMK1; /**< Shadow Register for OTP Bank4 Word1 (OTPMK Key), offset: 0x510 */ + uint8_t RESERVED_31[12]; + __IO uint32_t OTPMK2; /**< Shadow Register for OTP Bank4 Word2 (OTPMK Key), offset: 0x520 */ + uint8_t RESERVED_32[12]; + __IO uint32_t OTPMK3; /**< Shadow Register for OTP Bank4 Word3 (OTPMK Key), offset: 0x530 */ + uint8_t RESERVED_33[12]; + __IO uint32_t OTPMK4; /**< Shadow Register for OTP Bank5 Word0 (OTPMK Key), offset: 0x540 */ + uint8_t RESERVED_34[12]; + __IO uint32_t OTPMK5; /**< Shadow Register for OTP Bank5 Word1 (OTPMK Key), offset: 0x550 */ + uint8_t RESERVED_35[12]; + __IO uint32_t OTPMK6; /**< Shadow Register for OTP Bank5 Word2 (OTPMK Key), offset: 0x560 */ + uint8_t RESERVED_36[12]; + __IO uint32_t OTPMK7; /**< Shadow Register for OTP Bank5 Word3 (OTPMK Key), offset: 0x570 */ + uint8_t RESERVED_37[12]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank6 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank6 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank6 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank6 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank7 Word0 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_42[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank7 Word1 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_43[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank7 Word2 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_44[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank7 Word3 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_46[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_47[12]; + __IO uint32_t USB_ID; /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */ + uint8_t RESERVED_48[12]; + __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank8 Word3 (Field Return), offset: 0x630 */ + uint8_t RESERVED_49[12]; + __IO uint32_t MAC_ADDR0; /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */ + uint8_t RESERVED_50[12]; + __IO uint32_t MAC_ADDR1; /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */ + uint8_t RESERVED_51[12]; + __IO uint32_t MAC_ADDR2; /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */ + uint8_t RESERVED_52[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank9 Word3 (SRK Revoke), offset: 0x670 */ + uint8_t RESERVED_53[12]; + __IO uint32_t MAU_KEY0; /**< Shadow Register for OTP Bank10 Word0 (MAU Key), offset: 0x680 */ + uint8_t RESERVED_54[12]; + __IO uint32_t MAU_KEY1; /**< Shadow Register for OTP Bank10 Word1 (MAU Key), offset: 0x690 */ + uint8_t RESERVED_55[12]; + __IO uint32_t MAU_KEY2; /**< Shadow Register for OTP Bank10 Word2 (MAU Key), offset: 0x6A0 */ + uint8_t RESERVED_56[12]; + __IO uint32_t MAU_KEY3; /**< Shadow Register for OTP Bank10 Word3 (MAU Key), offset: 0x6B0 */ + uint8_t RESERVED_57[12]; + __IO uint32_t MAU_KEY4; /**< Shadow Register for OTP Bank11 Word0 (MAU Key), offset: 0x6C0 */ + uint8_t RESERVED_58[12]; + __IO uint32_t MAU_KEY5; /**< Shadow Register for OTP Bank11 Word1 (MAU Key), offset: 0x6D0 */ + uint8_t RESERVED_59[12]; + __IO uint32_t MAU_KEY6; /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */ + uint8_t RESERVED_60[12]; + __IO uint32_t MAU_KEY7; /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */ + uint8_t RESERVED_61[12]; + __IO uint32_t ROM_PATCH0; /**< Value of OTP Bank12 Word0 (Rom Patch), offset: 0x700 */ + uint8_t RESERVED_62[12]; + __IO uint32_t ROM_PATCH1; /**< Value of OTP Bank12 Word1 (Rom Patch), offset: 0x710 */ + uint8_t RESERVED_63[12]; + __IO uint32_t ROM_PATCH2; /**< Value of OTP Bank12 Word2 (Rom Patch), offset: 0x720 */ + uint8_t RESERVED_64[12]; + __IO uint32_t ROM_PATCH3; /**< Value of OTP Bank12 Word3 (Rom Patch), offset: 0x730 */ + uint8_t RESERVED_65[12]; + __IO uint32_t ROM_PATCH4; /**< Value of OTP Bank13 Word0 (Rom Patch), offset: 0x740 */ + uint8_t RESERVED_66[12]; + __IO uint32_t ROM_PATCH5; /**< Value of OTP Bank13 Word1 (Rom Patch), offset: 0x750 */ + uint8_t RESERVED_67[12]; + __IO uint32_t ROM_PATCH6; /**< Value of OTP Bank13 Word2 (Rom Patch), offset: 0x760 */ + uint8_t RESERVED_68[12]; + __IO uint32_t ROM_PATCH7; /**< Value of OTP Bank13 Word3 (Rom Patch), offset: 0x770 */ + uint8_t RESERVED_69[12]; + __IO uint32_t GP10; /**< Value of OTP Bank14 Word0, offset: 0x780 */ + uint8_t RESERVED_70[12]; + __IO uint32_t GP11; /**< Value of OTP Bank14 Word1, offset: 0x790 */ + uint8_t RESERVED_71[12]; + __IO uint32_t GP20; /**< Value of OTP Bank14 Word2, offset: 0x7A0 */ + uint8_t RESERVED_72[12]; + __IO uint32_t GP21; /**< Value of OTP Bank14 Word3, offset: 0x7B0 */ + uint8_t RESERVED_73[12]; + __IO uint32_t CRC_GP10; /**< Value of OTP Bank15 Word0 (CRC Key), offset: 0x7C0 */ + uint8_t RESERVED_74[12]; + __IO uint32_t CRC_GP11; /**< Value of OTP Bank15 Word1 (CRC Key), offset: 0x7D0 */ + uint8_t RESERVED_75[12]; + __IO uint32_t CRC_GP20; /**< Value of OTP Bank15 Word2 (CRC Key), offset: 0x7E0 */ + uint8_t RESERVED_76[12]; + __IO uint32_t CRC_GP21; /**< Value of OTP Bank15 Word3 (CRC Key), offset: 0x7F0 */ +} OCOTP_Type, *OCOTP_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- OCOTP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros + * @{ + */ + + +/* OCOTP - Register accessors */ +#define OCOTP_CTRL_REG(base) ((base)->CTRL) +#define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define OCOTP_TIMING_REG(base) ((base)->TIMING) +#define OCOTP_DATA0_REG(base) ((base)->DATA0) +#define OCOTP_DATA1_REG(base) ((base)->DATA1) +#define OCOTP_DATA2_REG(base) ((base)->DATA2) +#define OCOTP_DATA3_REG(base) ((base)->DATA3) +#define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) +#define OCOTP_READ_FUSE_DATA0_REG(base) ((base)->READ_FUSE_DATA0) +#define OCOTP_READ_FUSE_DATA1_REG(base) ((base)->READ_FUSE_DATA1) +#define OCOTP_READ_FUSE_DATA2_REG(base) ((base)->READ_FUSE_DATA2) +#define OCOTP_READ_FUSE_DATA3_REG(base) ((base)->READ_FUSE_DATA3) +#define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) +#define OCOTP_SCS_REG(base) ((base)->SCS) +#define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) +#define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) +#define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) +#define OCOTP_CRC_ADDR_REG(base) ((base)->CRC_ADDR) +#define OCOTP_CRC_VALUE_REG(base) ((base)->CRC_VALUE) +#define OCOTP_VERSION_REG(base) ((base)->VERSION) +#define OCOTP_LOCK_REG(base) ((base)->LOCK) +#define OCOTP_TESTER0_REG(base) ((base)->TESTER0) +#define OCOTP_TESTER1_REG(base) ((base)->TESTER1) +#define OCOTP_TESTER2_REG(base) ((base)->TESTER2) +#define OCOTP_TESTER3_REG(base) ((base)->TESTER3) +#define OCOTP_TESTER4_REG(base) ((base)->TESTER4) +#define OCOTP_TESTER5_REG(base) ((base)->TESTER5) +#define OCOTP_BOOT_CFG0_REG(base) ((base)->BOOT_CFG0) +#define OCOTP_BOOT_CFG1_REG(base) ((base)->BOOT_CFG1) +#define OCOTP_BOOT_CFG2_REG(base) ((base)->BOOT_CFG2) +#define OCOTP_BOOT_CFG3_REG(base) ((base)->BOOT_CFG3) +#define OCOTP_BOOT_CFG4_REG(base) ((base)->BOOT_CFG4) +#define OCOTP_MEM_TRIM0_REG(base) ((base)->MEM_TRIM0) +#define OCOTP_MEM_TRIM1_REG(base) ((base)->MEM_TRIM1) +#define OCOTP_ANA0_REG(base) ((base)->ANA0) +#define OCOTP_ANA1_REG(base) ((base)->ANA1) +#define OCOTP_OTPMK0_REG(base) ((base)->OTPMK0) +#define OCOTP_OTPMK1_REG(base) ((base)->OTPMK1) +#define OCOTP_OTPMK2_REG(base) ((base)->OTPMK2) +#define OCOTP_OTPMK3_REG(base) ((base)->OTPMK3) +#define OCOTP_OTPMK4_REG(base) ((base)->OTPMK4) +#define OCOTP_OTPMK5_REG(base) ((base)->OTPMK5) +#define OCOTP_OTPMK6_REG(base) ((base)->OTPMK6) +#define OCOTP_OTPMK7_REG(base) ((base)->OTPMK7) +#define OCOTP_SRK0_REG(base) ((base)->SRK0) +#define OCOTP_SRK1_REG(base) ((base)->SRK1) +#define OCOTP_SRK2_REG(base) ((base)->SRK2) +#define OCOTP_SRK3_REG(base) ((base)->SRK3) +#define OCOTP_SRK4_REG(base) ((base)->SRK4) +#define OCOTP_SRK5_REG(base) ((base)->SRK5) +#define OCOTP_SRK6_REG(base) ((base)->SRK6) +#define OCOTP_SRK7_REG(base) ((base)->SRK7) +#define OCOTP_SJC_RESP0_REG(base) ((base)->SJC_RESP0) +#define OCOTP_SJC_RESP1_REG(base) ((base)->SJC_RESP1) +#define OCOTP_USB_ID_REG(base) ((base)->USB_ID) +#define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) +#define OCOTP_MAC_ADDR0_REG(base) ((base)->MAC_ADDR0) +#define OCOTP_MAC_ADDR1_REG(base) ((base)->MAC_ADDR1) +#define OCOTP_MAC_ADDR2_REG(base) ((base)->MAC_ADDR2) +#define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) +#define OCOTP_MAU_KEY0_REG(base) ((base)->MAU_KEY0) +#define OCOTP_MAU_KEY1_REG(base) ((base)->MAU_KEY1) +#define OCOTP_MAU_KEY2_REG(base) ((base)->MAU_KEY2) +#define OCOTP_MAU_KEY3_REG(base) ((base)->MAU_KEY3) +#define OCOTP_MAU_KEY4_REG(base) ((base)->MAU_KEY4) +#define OCOTP_MAU_KEY5_REG(base) ((base)->MAU_KEY5) +#define OCOTP_MAU_KEY6_REG(base) ((base)->MAU_KEY6) +#define OCOTP_MAU_KEY7_REG(base) ((base)->MAU_KEY7) +#define OCOTP_ROM_PATCH0_REG(base) ((base)->ROM_PATCH0) +#define OCOTP_ROM_PATCH1_REG(base) ((base)->ROM_PATCH1) +#define OCOTP_ROM_PATCH2_REG(base) ((base)->ROM_PATCH2) +#define OCOTP_ROM_PATCH3_REG(base) ((base)->ROM_PATCH3) +#define OCOTP_ROM_PATCH4_REG(base) ((base)->ROM_PATCH4) +#define OCOTP_ROM_PATCH5_REG(base) ((base)->ROM_PATCH5) +#define OCOTP_ROM_PATCH6_REG(base) ((base)->ROM_PATCH6) +#define OCOTP_ROM_PATCH7_REG(base) ((base)->ROM_PATCH7) +#define OCOTP_GP10_REG(base) ((base)->GP10) +#define OCOTP_GP11_REG(base) ((base)->GP11) +#define OCOTP_GP20_REG(base) ((base)->GP20) +#define OCOTP_GP21_REG(base) ((base)->GP21) +#define OCOTP_CRC_GP10_REG(base) ((base)->CRC_GP10) +#define OCOTP_CRC_GP11_REG(base) ((base)->CRC_GP11) +#define OCOTP_CRC_GP20_REG(base) ((base)->CRC_GP20) +#define OCOTP_CRC_GP21_REG(base) ((base)->CRC_GP21) + +/*! + * @} + */ /* end of group OCOTP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define OCOTP_CTRL_ADDR_MASK 0xFu +#define OCOTP_CTRL_ADDR_SHIFT 0 +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_ADDR_SHIFT))&OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_RSVD0_MASK 0xF0u +#define OCOTP_CTRL_RSVD0_SHIFT 4 +#define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_RSVD0_SHIFT))&OCOTP_CTRL_RSVD0_MASK) +#define OCOTP_CTRL_BUSY_MASK 0x100u +#define OCOTP_CTRL_BUSY_SHIFT 8 +#define OCOTP_CTRL_ERROR_MASK 0x200u +#define OCOTP_CTRL_ERROR_SHIFT 9 +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK 0x400u +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT 10 +#define OCOTP_CTRL_CRC_TEST_MASK 0x800u +#define OCOTP_CTRL_CRC_TEST_SHIFT 11 +#define OCOTP_CTRL_CRC_FAIL_MASK 0x1000u +#define OCOTP_CTRL_CRC_FAIL_SHIFT 12 +#define OCOTP_CTRL_RSVD1_MASK 0xE000u +#define OCOTP_CTRL_RSVD1_SHIFT 13 +#define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_RSVD1_SHIFT))&OCOTP_CTRL_RSVD1_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK 0xFFFF0000u +#define OCOTP_CTRL_WR_UNLOCK_SHIFT 16 +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_WR_UNLOCK_SHIFT))&OCOTP_CTRL_WR_UNLOCK_MASK) +/* CTRL_SET Bit Fields */ +#define OCOTP_CTRL_SET_ADDR_MASK 0xFu +#define OCOTP_CTRL_SET_ADDR_SHIFT 0 +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_ADDR_SHIFT))&OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_RSVD0_MASK 0xF0u +#define OCOTP_CTRL_SET_RSVD0_SHIFT 4 +#define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_RSVD0_SHIFT))&OCOTP_CTRL_SET_RSVD0_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK 0x100u +#define OCOTP_CTRL_SET_BUSY_SHIFT 8 +#define OCOTP_CTRL_SET_ERROR_MASK 0x200u +#define OCOTP_CTRL_SET_ERROR_SHIFT 9 +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK 0x400u +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT 10 +#define OCOTP_CTRL_SET_CRC_TEST_MASK 0x800u +#define OCOTP_CTRL_SET_CRC_TEST_SHIFT 11 +#define OCOTP_CTRL_SET_CRC_FAIL_MASK 0x1000u +#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT 12 +#define OCOTP_CTRL_SET_RSVD1_MASK 0xE000u +#define OCOTP_CTRL_SET_RSVD1_SHIFT 13 +#define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_RSVD1_SHIFT))&OCOTP_CTRL_SET_RSVD1_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK 0xFFFF0000u +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT 16 +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_SET_WR_UNLOCK_SHIFT))&OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/* CTRL_CLR Bit Fields */ +#define OCOTP_CTRL_CLR_ADDR_MASK 0xFu +#define OCOTP_CTRL_CLR_ADDR_SHIFT 0 +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_ADDR_SHIFT))&OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_RSVD0_MASK 0xF0u +#define OCOTP_CTRL_CLR_RSVD0_SHIFT 4 +#define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_RSVD0_SHIFT))&OCOTP_CTRL_CLR_RSVD0_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK 0x100u +#define OCOTP_CTRL_CLR_BUSY_SHIFT 8 +#define OCOTP_CTRL_CLR_ERROR_MASK 0x200u +#define OCOTP_CTRL_CLR_ERROR_SHIFT 9 +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK 0x400u +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT 10 +#define OCOTP_CTRL_CLR_CRC_TEST_MASK 0x800u +#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT 11 +#define OCOTP_CTRL_CLR_CRC_FAIL_MASK 0x1000u +#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT 12 +#define OCOTP_CTRL_CLR_RSVD1_MASK 0xE000u +#define OCOTP_CTRL_CLR_RSVD1_SHIFT 13 +#define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_RSVD1_SHIFT))&OCOTP_CTRL_CLR_RSVD1_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK 0xFFFF0000u +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT 16 +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT))&OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/* CTRL_TOG Bit Fields */ +#define OCOTP_CTRL_TOG_ADDR_MASK 0xFu +#define OCOTP_CTRL_TOG_ADDR_SHIFT 0 +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_ADDR_SHIFT))&OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_RSVD0_MASK 0xF0u +#define OCOTP_CTRL_TOG_RSVD0_SHIFT 4 +#define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_RSVD0_SHIFT))&OCOTP_CTRL_TOG_RSVD0_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK 0x100u +#define OCOTP_CTRL_TOG_BUSY_SHIFT 8 +#define OCOTP_CTRL_TOG_ERROR_MASK 0x200u +#define OCOTP_CTRL_TOG_ERROR_SHIFT 9 +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK 0x400u +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT 10 +#define OCOTP_CTRL_TOG_CRC_TEST_MASK 0x800u +#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT 11 +#define OCOTP_CTRL_TOG_CRC_FAIL_MASK 0x1000u +#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT 12 +#define OCOTP_CTRL_TOG_RSVD1_MASK 0xE000u +#define OCOTP_CTRL_TOG_RSVD1_SHIFT 13 +#define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_RSVD1_SHIFT))&OCOTP_CTRL_TOG_RSVD1_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK 0xFFFF0000u +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT 16 +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT))&OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/* TIMING Bit Fields */ +#define OCOTP_TIMING_PROG_MASK 0xFFFu +#define OCOTP_TIMING_PROG_SHIFT 0 +#define OCOTP_TIMING_PROG(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_PROG_SHIFT))&OCOTP_TIMING_PROG_MASK) +#define OCOTP_TIMING_FSOURCE_MASK 0x7F000u +#define OCOTP_TIMING_FSOURCE_SHIFT 12 +#define OCOTP_TIMING_FSOURCE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_FSOURCE_SHIFT))&OCOTP_TIMING_FSOURCE_MASK) +#define OCOTP_TIMING_RSRVD0_MASK 0xFFF80000u +#define OCOTP_TIMING_RSRVD0_SHIFT 19 +#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TIMING_RSRVD0_SHIFT))&OCOTP_TIMING_RSRVD0_MASK) +/* DATA0 Bit Fields */ +#define OCOTP_DATA0_DATA0_MASK 0xFFFFFFFFu +#define OCOTP_DATA0_DATA0_SHIFT 0 +#define OCOTP_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA0_DATA0_SHIFT))&OCOTP_DATA0_DATA0_MASK) +/* DATA1 Bit Fields */ +#define OCOTP_DATA1_DATA1_MASK 0xFFFFFFFFu +#define OCOTP_DATA1_DATA1_SHIFT 0 +#define OCOTP_DATA1_DATA1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA1_DATA1_SHIFT))&OCOTP_DATA1_DATA1_MASK) +/* DATA2 Bit Fields */ +#define OCOTP_DATA2_DATA2_MASK 0xFFFFFFFFu +#define OCOTP_DATA2_DATA2_SHIFT 0 +#define OCOTP_DATA2_DATA2(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA2_DATA2_SHIFT))&OCOTP_DATA2_DATA2_MASK) +/* DATA3 Bit Fields */ +#define OCOTP_DATA3_DATA3_MASK 0xFFFFFFFFu +#define OCOTP_DATA3_DATA3_SHIFT 0 +#define OCOTP_DATA3_DATA3(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_DATA3_DATA3_SHIFT))&OCOTP_DATA3_DATA3_MASK) +/* READ_CTRL Bit Fields */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK 0x1u +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT 0 +#define OCOTP_READ_CTRL_RSVD0_MASK 0xFFFFFFFEu +#define OCOTP_READ_CTRL_RSVD0_SHIFT 1 +#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_CTRL_RSVD0_SHIFT))&OCOTP_READ_CTRL_RSVD0_MASK) +/* READ_FUSE_DATA0 Bit Fields */ +#define OCOTP_READ_FUSE_DATA0_DATA0_MASK 0xFFFFFFFFu +#define OCOTP_READ_FUSE_DATA0_DATA0_SHIFT 0 +#define OCOTP_READ_FUSE_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA0_DATA0_SHIFT))&OCOTP_READ_FUSE_DATA0_DATA0_MASK) +/* READ_FUSE_DATA1 Bit Fields */ +#define OCOTP_READ_FUSE_DATA1_DATA1_MASK 0xFFFFFFFFu +#define OCOTP_READ_FUSE_DATA1_DATA1_SHIFT 0 +#define OCOTP_READ_FUSE_DATA1_DATA1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA1_DATA1_SHIFT))&OCOTP_READ_FUSE_DATA1_DATA1_MASK) +/* READ_FUSE_DATA2 Bit Fields */ +#define OCOTP_READ_FUSE_DATA2_DATA2_MASK 0xFFFFFFFFu +#define OCOTP_READ_FUSE_DATA2_DATA2_SHIFT 0 +#define OCOTP_READ_FUSE_DATA2_DATA2(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA2_DATA2_SHIFT))&OCOTP_READ_FUSE_DATA2_DATA2_MASK) +/* READ_FUSE_DATA3 Bit Fields */ +#define OCOTP_READ_FUSE_DATA3_DATA3_MASK 0xFFFFFFFFu +#define OCOTP_READ_FUSE_DATA3_DATA3_SHIFT 0 +#define OCOTP_READ_FUSE_DATA3_DATA3(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_READ_FUSE_DATA3_DATA3_SHIFT))&OCOTP_READ_FUSE_DATA3_DATA3_MASK) +/* SW_STICKY Bit Fields */ +#define OCOTP_SW_STICKY_RSVD0_MASK 0x1u +#define OCOTP_SW_STICKY_RSVD0_SHIFT 0 +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK 0x2u +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT 1 +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK 0x4u +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT 2 +#define OCOTP_SW_STICKY_RSVD1_MASK 0xFFFFFFF8u +#define OCOTP_SW_STICKY_RSVD1_SHIFT 3 +#define OCOTP_SW_STICKY_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SW_STICKY_RSVD1_SHIFT))&OCOTP_SW_STICKY_RSVD1_MASK) +/* SCS Bit Fields */ +#define OCOTP_SCS_HAB_JDE_MASK 0x1u +#define OCOTP_SCS_HAB_JDE_SHIFT 0 +#define OCOTP_SCS_SPARE_MASK 0x7FFFFFFEu +#define OCOTP_SCS_SPARE_SHIFT 1 +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SPARE_SHIFT))&OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK 0x80000000u +#define OCOTP_SCS_LOCK_SHIFT 31 +/* SCS_SET Bit Fields */ +#define OCOTP_SCS_SET_HAB_JDE_MASK 0x1u +#define OCOTP_SCS_SET_HAB_JDE_SHIFT 0 +#define OCOTP_SCS_SET_SPARE_MASK 0x7FFFFFFEu +#define OCOTP_SCS_SET_SPARE_SHIFT 1 +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_SET_SPARE_SHIFT))&OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK 0x80000000u +#define OCOTP_SCS_SET_LOCK_SHIFT 31 +/* SCS_CLR Bit Fields */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK 0x1u +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT 0 +#define OCOTP_SCS_CLR_SPARE_MASK 0x7FFFFFFEu +#define OCOTP_SCS_CLR_SPARE_SHIFT 1 +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_CLR_SPARE_SHIFT))&OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK 0x80000000u +#define OCOTP_SCS_CLR_LOCK_SHIFT 31 +/* SCS_TOG Bit Fields */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK 0x1u +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT 0 +#define OCOTP_SCS_TOG_SPARE_MASK 0x7FFFFFFEu +#define OCOTP_SCS_TOG_SPARE_SHIFT 1 +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SCS_TOG_SPARE_SHIFT))&OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK 0x80000000u +#define OCOTP_SCS_TOG_LOCK_SHIFT 31 +/* CRC_ADDR Bit Fields */ +#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK 0xFFu +#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT 0 +#define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT))&OCOTP_CRC_ADDR_DATA_START_ADDR_MASK) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK 0xFF00u +#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT 8 +#define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT))&OCOTP_CRC_ADDR_DATA_END_ADDR_MASK) +#define OCOTP_CRC_ADDR_CRC_ADDR_MASK 0x30000u +#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT 16 +#define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_CRC_ADDR_SHIFT))&OCOTP_CRC_ADDR_CRC_ADDR_MASK) +#define OCOTP_CRC_ADDR_RSVD0_MASK 0xFFFC0000u +#define OCOTP_CRC_ADDR_RSVD0_SHIFT 18 +#define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_ADDR_RSVD0_SHIFT))&OCOTP_CRC_ADDR_RSVD0_MASK) +/* CRC_VALUE Bit Fields */ +#define OCOTP_CRC_VALUE_DATA_MASK 0xFFFFFFFFu +#define OCOTP_CRC_VALUE_DATA_SHIFT 0 +#define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_VALUE_DATA_SHIFT))&OCOTP_CRC_VALUE_DATA_MASK) +/* VERSION Bit Fields */ +#define OCOTP_VERSION_STEP_MASK 0xFFFFu +#define OCOTP_VERSION_STEP_SHIFT 0 +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_STEP_SHIFT))&OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK 0xFF0000u +#define OCOTP_VERSION_MINOR_SHIFT 16 +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MINOR_SHIFT))&OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK 0xFF000000u +#define OCOTP_VERSION_MAJOR_SHIFT 24 +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_VERSION_MAJOR_SHIFT))&OCOTP_VERSION_MAJOR_MASK) +/* LOCK Bit Fields */ +#define OCOTP_LOCK_TESTER_MASK 0x3u +#define OCOTP_LOCK_TESTER_SHIFT 0 +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_TESTER_SHIFT))&OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK 0xCu +#define OCOTP_LOCK_BOOT_CFG_SHIFT 2 +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_BOOT_CFG_SHIFT))&OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK 0x30u +#define OCOTP_LOCK_MEM_TRIM_SHIFT 4 +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MEM_TRIM_SHIFT))&OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_ANALOG_MASK 0xC0u +#define OCOTP_LOCK_ANALOG_SHIFT 6 +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_ANALOG_SHIFT))&OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_MASK 0x100u +#define OCOTP_LOCK_OTPMK_SHIFT 8 +#define OCOTP_LOCK_SRK_MASK 0x200u +#define OCOTP_LOCK_SRK_SHIFT 9 +#define OCOTP_LOCK_SJC_RESP_MASK 0x400u +#define OCOTP_LOCK_SJC_RESP_SHIFT 10 +#define OCOTP_LOCK_RSVD0_MASK 0x800u +#define OCOTP_LOCK_RSVD0_SHIFT 11 +#define OCOTP_LOCK_USB_ID_MASK 0x3000u +#define OCOTP_LOCK_USB_ID_SHIFT 12 +#define OCOTP_LOCK_USB_ID(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_USB_ID_SHIFT))&OCOTP_LOCK_USB_ID_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK 0xC000u +#define OCOTP_LOCK_MAC_ADDR_SHIFT 14 +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_MAC_ADDR_SHIFT))&OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_MAU_KEY_MASK 0x10000u +#define OCOTP_LOCK_MAU_KEY_SHIFT 16 +#define OCOTP_LOCK_ROM_PATCH_MASK 0x20000u +#define OCOTP_LOCK_ROM_PATCH_SHIFT 17 +#define OCOTP_LOCK_RSVD1_MASK 0xC0000u +#define OCOTP_LOCK_RSVD1_SHIFT 18 +#define OCOTP_LOCK_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_RSVD1_SHIFT))&OCOTP_LOCK_RSVD1_MASK) +#define OCOTP_LOCK_GP1_MASK 0x300000u +#define OCOTP_LOCK_GP1_SHIFT 20 +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP1_SHIFT))&OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK 0xC00000u +#define OCOTP_LOCK_GP2_SHIFT 22 +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_GP2_SHIFT))&OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_RSVD2_MASK 0xF000000u +#define OCOTP_LOCK_RSVD2_SHIFT 24 +#define OCOTP_LOCK_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_RSVD2_SHIFT))&OCOTP_LOCK_RSVD2_MASK) +#define OCOTP_LOCK_CRC_GP1_MASK 0x30000000u +#define OCOTP_LOCK_CRC_GP1_SHIFT 28 +#define OCOTP_LOCK_CRC_GP1(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_CRC_GP1_SHIFT))&OCOTP_LOCK_CRC_GP1_MASK) +#define OCOTP_LOCK_CRC_GP2_MASK 0xC0000000u +#define OCOTP_LOCK_CRC_GP2_SHIFT 30 +#define OCOTP_LOCK_CRC_GP2(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_LOCK_CRC_GP2_SHIFT))&OCOTP_LOCK_CRC_GP2_MASK) +/* TESTER0 Bit Fields */ +#define OCOTP_TESTER0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_TESTER0_BITS_SHIFT 0 +#define OCOTP_TESTER0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER0_BITS_SHIFT))&OCOTP_TESTER0_BITS_MASK) +/* TESTER1 Bit Fields */ +#define OCOTP_TESTER1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_TESTER1_BITS_SHIFT 0 +#define OCOTP_TESTER1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER1_BITS_SHIFT))&OCOTP_TESTER1_BITS_MASK) +/* TESTER2 Bit Fields */ +#define OCOTP_TESTER2_BITS_MASK 0xFFFFFFFFu +#define OCOTP_TESTER2_BITS_SHIFT 0 +#define OCOTP_TESTER2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER2_BITS_SHIFT))&OCOTP_TESTER2_BITS_MASK) +/* TESTER3 Bit Fields */ +#define OCOTP_TESTER3_BITS_MASK 0xFFFFFFFFu +#define OCOTP_TESTER3_BITS_SHIFT 0 +#define OCOTP_TESTER3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER3_BITS_SHIFT))&OCOTP_TESTER3_BITS_MASK) +/* TESTER4 Bit Fields */ +#define OCOTP_TESTER4_BITS_MASK 0xFFFFFFFFu +#define OCOTP_TESTER4_BITS_SHIFT 0 +#define OCOTP_TESTER4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER4_BITS_SHIFT))&OCOTP_TESTER4_BITS_MASK) +/* TESTER5 Bit Fields */ +#define OCOTP_TESTER5_BITS_MASK 0xFFFFFFFFu +#define OCOTP_TESTER5_BITS_SHIFT 0 +#define OCOTP_TESTER5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_TESTER5_BITS_SHIFT))&OCOTP_TESTER5_BITS_MASK) +/* BOOT_CFG0 Bit Fields */ +#define OCOTP_BOOT_CFG0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_BOOT_CFG0_BITS_SHIFT 0 +#define OCOTP_BOOT_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG0_BITS_SHIFT))&OCOTP_BOOT_CFG0_BITS_MASK) +/* BOOT_CFG1 Bit Fields */ +#define OCOTP_BOOT_CFG1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_BOOT_CFG1_BITS_SHIFT 0 +#define OCOTP_BOOT_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG1_BITS_SHIFT))&OCOTP_BOOT_CFG1_BITS_MASK) +/* BOOT_CFG2 Bit Fields */ +#define OCOTP_BOOT_CFG2_BITS_MASK 0xFFFFFFFFu +#define OCOTP_BOOT_CFG2_BITS_SHIFT 0 +#define OCOTP_BOOT_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG2_BITS_SHIFT))&OCOTP_BOOT_CFG2_BITS_MASK) +/* BOOT_CFG3 Bit Fields */ +#define OCOTP_BOOT_CFG3_BITS_MASK 0xFFFFFFFFu +#define OCOTP_BOOT_CFG3_BITS_SHIFT 0 +#define OCOTP_BOOT_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG3_BITS_SHIFT))&OCOTP_BOOT_CFG3_BITS_MASK) +/* BOOT_CFG4 Bit Fields */ +#define OCOTP_BOOT_CFG4_BITS_MASK 0xFFFFFFFFu +#define OCOTP_BOOT_CFG4_BITS_SHIFT 0 +#define OCOTP_BOOT_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_BOOT_CFG4_BITS_SHIFT))&OCOTP_BOOT_CFG4_BITS_MASK) +/* MEM_TRIM0 Bit Fields */ +#define OCOTP_MEM_TRIM0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MEM_TRIM0_BITS_SHIFT 0 +#define OCOTP_MEM_TRIM0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM_TRIM0_BITS_SHIFT))&OCOTP_MEM_TRIM0_BITS_MASK) +/* MEM_TRIM1 Bit Fields */ +#define OCOTP_MEM_TRIM1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MEM_TRIM1_BITS_SHIFT 0 +#define OCOTP_MEM_TRIM1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MEM_TRIM1_BITS_SHIFT))&OCOTP_MEM_TRIM1_BITS_MASK) +/* ANA0 Bit Fields */ +#define OCOTP_ANA0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ANA0_BITS_SHIFT 0 +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA0_BITS_SHIFT))&OCOTP_ANA0_BITS_MASK) +/* ANA1 Bit Fields */ +#define OCOTP_ANA1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ANA1_BITS_SHIFT 0 +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ANA1_BITS_SHIFT))&OCOTP_ANA1_BITS_MASK) +/* OTPMK0 Bit Fields */ +#define OCOTP_OTPMK0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK0_BITS_SHIFT 0 +#define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK0_BITS_SHIFT))&OCOTP_OTPMK0_BITS_MASK) +/* OTPMK1 Bit Fields */ +#define OCOTP_OTPMK1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK1_BITS_SHIFT 0 +#define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK1_BITS_SHIFT))&OCOTP_OTPMK1_BITS_MASK) +/* OTPMK2 Bit Fields */ +#define OCOTP_OTPMK2_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK2_BITS_SHIFT 0 +#define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK2_BITS_SHIFT))&OCOTP_OTPMK2_BITS_MASK) +/* OTPMK3 Bit Fields */ +#define OCOTP_OTPMK3_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK3_BITS_SHIFT 0 +#define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK3_BITS_SHIFT))&OCOTP_OTPMK3_BITS_MASK) +/* OTPMK4 Bit Fields */ +#define OCOTP_OTPMK4_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK4_BITS_SHIFT 0 +#define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK4_BITS_SHIFT))&OCOTP_OTPMK4_BITS_MASK) +/* OTPMK5 Bit Fields */ +#define OCOTP_OTPMK5_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK5_BITS_SHIFT 0 +#define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK5_BITS_SHIFT))&OCOTP_OTPMK5_BITS_MASK) +/* OTPMK6 Bit Fields */ +#define OCOTP_OTPMK6_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK6_BITS_SHIFT 0 +#define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK6_BITS_SHIFT))&OCOTP_OTPMK6_BITS_MASK) +/* OTPMK7 Bit Fields */ +#define OCOTP_OTPMK7_BITS_MASK 0xFFFFFFFFu +#define OCOTP_OTPMK7_BITS_SHIFT 0 +#define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_OTPMK7_BITS_SHIFT))&OCOTP_OTPMK7_BITS_MASK) +/* SRK0 Bit Fields */ +#define OCOTP_SRK0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK0_BITS_SHIFT 0 +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK0_BITS_SHIFT))&OCOTP_SRK0_BITS_MASK) +/* SRK1 Bit Fields */ +#define OCOTP_SRK1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK1_BITS_SHIFT 0 +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK1_BITS_SHIFT))&OCOTP_SRK1_BITS_MASK) +/* SRK2 Bit Fields */ +#define OCOTP_SRK2_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK2_BITS_SHIFT 0 +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK2_BITS_SHIFT))&OCOTP_SRK2_BITS_MASK) +/* SRK3 Bit Fields */ +#define OCOTP_SRK3_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK3_BITS_SHIFT 0 +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK3_BITS_SHIFT))&OCOTP_SRK3_BITS_MASK) +/* SRK4 Bit Fields */ +#define OCOTP_SRK4_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK4_BITS_SHIFT 0 +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK4_BITS_SHIFT))&OCOTP_SRK4_BITS_MASK) +/* SRK5 Bit Fields */ +#define OCOTP_SRK5_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK5_BITS_SHIFT 0 +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK5_BITS_SHIFT))&OCOTP_SRK5_BITS_MASK) +/* SRK6 Bit Fields */ +#define OCOTP_SRK6_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK6_BITS_SHIFT 0 +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK6_BITS_SHIFT))&OCOTP_SRK6_BITS_MASK) +/* SRK7 Bit Fields */ +#define OCOTP_SRK7_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK7_BITS_SHIFT 0 +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK7_BITS_SHIFT))&OCOTP_SRK7_BITS_MASK) +/* SJC_RESP0 Bit Fields */ +#define OCOTP_SJC_RESP0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SJC_RESP0_BITS_SHIFT 0 +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SJC_RESP0_BITS_SHIFT))&OCOTP_SJC_RESP0_BITS_MASK) +/* SJC_RESP1 Bit Fields */ +#define OCOTP_SJC_RESP1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SJC_RESP1_BITS_SHIFT 0 +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SJC_RESP1_BITS_SHIFT))&OCOTP_SJC_RESP1_BITS_MASK) +/* USB_ID Bit Fields */ +#define OCOTP_USB_ID_BITS_MASK 0xFFFFFFFFu +#define OCOTP_USB_ID_BITS_SHIFT 0 +#define OCOTP_USB_ID_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_USB_ID_BITS_SHIFT))&OCOTP_USB_ID_BITS_MASK) +/* FIELD_RETURN Bit Fields */ +#define OCOTP_FIELD_RETURN_BITS_MASK 0xFFFFFFFFu +#define OCOTP_FIELD_RETURN_BITS_SHIFT 0 +#define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_FIELD_RETURN_BITS_SHIFT))&OCOTP_FIELD_RETURN_BITS_MASK) +/* MAC_ADDR0 Bit Fields */ +#define OCOTP_MAC_ADDR0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAC_ADDR0_BITS_SHIFT 0 +#define OCOTP_MAC_ADDR0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC_ADDR0_BITS_SHIFT))&OCOTP_MAC_ADDR0_BITS_MASK) +/* MAC_ADDR1 Bit Fields */ +#define OCOTP_MAC_ADDR1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAC_ADDR1_BITS_SHIFT 0 +#define OCOTP_MAC_ADDR1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC_ADDR1_BITS_SHIFT))&OCOTP_MAC_ADDR1_BITS_MASK) +/* MAC_ADDR2 Bit Fields */ +#define OCOTP_MAC_ADDR2_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAC_ADDR2_BITS_SHIFT 0 +#define OCOTP_MAC_ADDR2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAC_ADDR2_BITS_SHIFT))&OCOTP_MAC_ADDR2_BITS_MASK) +/* SRK_REVOKE Bit Fields */ +#define OCOTP_SRK_REVOKE_BITS_MASK 0xFFFFFFFFu +#define OCOTP_SRK_REVOKE_BITS_SHIFT 0 +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_SRK_REVOKE_BITS_SHIFT))&OCOTP_SRK_REVOKE_BITS_MASK) +/* MAU_KEY0 Bit Fields */ +#define OCOTP_MAU_KEY0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY0_BITS_SHIFT 0 +#define OCOTP_MAU_KEY0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY0_BITS_SHIFT))&OCOTP_MAU_KEY0_BITS_MASK) +/* MAU_KEY1 Bit Fields */ +#define OCOTP_MAU_KEY1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY1_BITS_SHIFT 0 +#define OCOTP_MAU_KEY1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY1_BITS_SHIFT))&OCOTP_MAU_KEY1_BITS_MASK) +/* MAU_KEY2 Bit Fields */ +#define OCOTP_MAU_KEY2_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY2_BITS_SHIFT 0 +#define OCOTP_MAU_KEY2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY2_BITS_SHIFT))&OCOTP_MAU_KEY2_BITS_MASK) +/* MAU_KEY3 Bit Fields */ +#define OCOTP_MAU_KEY3_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY3_BITS_SHIFT 0 +#define OCOTP_MAU_KEY3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY3_BITS_SHIFT))&OCOTP_MAU_KEY3_BITS_MASK) +/* MAU_KEY4 Bit Fields */ +#define OCOTP_MAU_KEY4_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY4_BITS_SHIFT 0 +#define OCOTP_MAU_KEY4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY4_BITS_SHIFT))&OCOTP_MAU_KEY4_BITS_MASK) +/* MAU_KEY5 Bit Fields */ +#define OCOTP_MAU_KEY5_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY5_BITS_SHIFT 0 +#define OCOTP_MAU_KEY5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY5_BITS_SHIFT))&OCOTP_MAU_KEY5_BITS_MASK) +/* MAU_KEY6 Bit Fields */ +#define OCOTP_MAU_KEY6_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY6_BITS_SHIFT 0 +#define OCOTP_MAU_KEY6_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY6_BITS_SHIFT))&OCOTP_MAU_KEY6_BITS_MASK) +/* MAU_KEY7 Bit Fields */ +#define OCOTP_MAU_KEY7_BITS_MASK 0xFFFFFFFFu +#define OCOTP_MAU_KEY7_BITS_SHIFT 0 +#define OCOTP_MAU_KEY7_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_MAU_KEY7_BITS_SHIFT))&OCOTP_MAU_KEY7_BITS_MASK) +/* ROM_PATCH0 Bit Fields */ +#define OCOTP_ROM_PATCH0_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH0_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH0_BITS_SHIFT))&OCOTP_ROM_PATCH0_BITS_MASK) +/* ROM_PATCH1 Bit Fields */ +#define OCOTP_ROM_PATCH1_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH1_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH1_BITS_SHIFT))&OCOTP_ROM_PATCH1_BITS_MASK) +/* ROM_PATCH2 Bit Fields */ +#define OCOTP_ROM_PATCH2_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH2_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH2_BITS_SHIFT))&OCOTP_ROM_PATCH2_BITS_MASK) +/* ROM_PATCH3 Bit Fields */ +#define OCOTP_ROM_PATCH3_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH3_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH3_BITS_SHIFT))&OCOTP_ROM_PATCH3_BITS_MASK) +/* ROM_PATCH4 Bit Fields */ +#define OCOTP_ROM_PATCH4_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH4_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH4_BITS_SHIFT))&OCOTP_ROM_PATCH4_BITS_MASK) +/* ROM_PATCH5 Bit Fields */ +#define OCOTP_ROM_PATCH5_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH5_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH5_BITS_SHIFT))&OCOTP_ROM_PATCH5_BITS_MASK) +/* ROM_PATCH6 Bit Fields */ +#define OCOTP_ROM_PATCH6_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH6_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH6_BITS_SHIFT))&OCOTP_ROM_PATCH6_BITS_MASK) +/* ROM_PATCH7 Bit Fields */ +#define OCOTP_ROM_PATCH7_BITS_MASK 0xFFFFFFFFu +#define OCOTP_ROM_PATCH7_BITS_SHIFT 0 +#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_ROM_PATCH7_BITS_SHIFT))&OCOTP_ROM_PATCH7_BITS_MASK) +/* GP10 Bit Fields */ +#define OCOTP_GP10_BITS_MASK 0xFFFFFFFFu +#define OCOTP_GP10_BITS_SHIFT 0 +#define OCOTP_GP10_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP10_BITS_SHIFT))&OCOTP_GP10_BITS_MASK) +/* GP11 Bit Fields */ +#define OCOTP_GP11_BITS_MASK 0xFFFFFFFFu +#define OCOTP_GP11_BITS_SHIFT 0 +#define OCOTP_GP11_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP11_BITS_SHIFT))&OCOTP_GP11_BITS_MASK) +/* GP20 Bit Fields */ +#define OCOTP_GP20_BITS_MASK 0xFFFFFFFFu +#define OCOTP_GP20_BITS_SHIFT 0 +#define OCOTP_GP20_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP20_BITS_SHIFT))&OCOTP_GP20_BITS_MASK) +/* GP21 Bit Fields */ +#define OCOTP_GP21_BITS_MASK 0xFFFFFFFFu +#define OCOTP_GP21_BITS_SHIFT 0 +#define OCOTP_GP21_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_GP21_BITS_SHIFT))&OCOTP_GP21_BITS_MASK) +/* CRC_GP10 Bit Fields */ +#define OCOTP_CRC_GP10_BITS_MASK 0xFFFFFFFFu +#define OCOTP_CRC_GP10_BITS_SHIFT 0 +#define OCOTP_CRC_GP10_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP10_BITS_SHIFT))&OCOTP_CRC_GP10_BITS_MASK) +/* CRC_GP11 Bit Fields */ +#define OCOTP_CRC_GP11_BITS_MASK 0xFFFFFFFFu +#define OCOTP_CRC_GP11_BITS_SHIFT 0 +#define OCOTP_CRC_GP11_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP11_BITS_SHIFT))&OCOTP_CRC_GP11_BITS_MASK) +/* CRC_GP20 Bit Fields */ +#define OCOTP_CRC_GP20_BITS_MASK 0xFFFFFFFFu +#define OCOTP_CRC_GP20_BITS_SHIFT 0 +#define OCOTP_CRC_GP20_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP20_BITS_SHIFT))&OCOTP_CRC_GP20_BITS_MASK) +/* CRC_GP21 Bit Fields */ +#define OCOTP_CRC_GP21_BITS_MASK 0xFFFFFFFFu +#define OCOTP_CRC_GP21_BITS_SHIFT 0 +#define OCOTP_CRC_GP21_BITS(x) (((uint32_t)(((uint32_t)(x))<<OCOTP_CRC_GP21_BITS_SHIFT))&OCOTP_CRC_GP21_BITS_MASK) + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x30350000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +#define OCOTP_BASE_PTR (OCOTP) +/** Array initializer of OCOTP peripheral base adresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/* ---------------------------------------------------------------------------- + -- OCOTP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Accessor_Macros OCOTP - Register accessor macros + * @{ + */ + + +/* OCOTP - Register instance definitions */ +/* OCOTP */ +#define OCOTP_CTRL OCOTP_CTRL_REG(OCOTP_BASE_PTR) +#define OCOTP_CTRL_SET OCOTP_CTRL_SET_REG(OCOTP_BASE_PTR) +#define OCOTP_CTRL_CLR OCOTP_CTRL_CLR_REG(OCOTP_BASE_PTR) +#define OCOTP_CTRL_TOG OCOTP_CTRL_TOG_REG(OCOTP_BASE_PTR) +#define OCOTP_TIMING OCOTP_TIMING_REG(OCOTP_BASE_PTR) +#define OCOTP_DATA0 OCOTP_DATA0_REG(OCOTP_BASE_PTR) +#define OCOTP_DATA1 OCOTP_DATA1_REG(OCOTP_BASE_PTR) +#define OCOTP_DATA2 OCOTP_DATA2_REG(OCOTP_BASE_PTR) +#define OCOTP_DATA3 OCOTP_DATA3_REG(OCOTP_BASE_PTR) +#define OCOTP_READ_CTRL OCOTP_READ_CTRL_REG(OCOTP_BASE_PTR) +#define OCOTP_READ_FUSE_DATA0 OCOTP_READ_FUSE_DATA0_REG(OCOTP_BASE_PTR) +#define OCOTP_READ_FUSE_DATA1 OCOTP_READ_FUSE_DATA1_REG(OCOTP_BASE_PTR) +#define OCOTP_READ_FUSE_DATA2 OCOTP_READ_FUSE_DATA2_REG(OCOTP_BASE_PTR) +#define OCOTP_READ_FUSE_DATA3 OCOTP_READ_FUSE_DATA3_REG(OCOTP_BASE_PTR) +#define OCOTP_SW_STICKY OCOTP_SW_STICKY_REG(OCOTP_BASE_PTR) +#define OCOTP_SCS OCOTP_SCS_REG(OCOTP_BASE_PTR) +#define OCOTP_SCS_SET OCOTP_SCS_SET_REG(OCOTP_BASE_PTR) +#define OCOTP_SCS_CLR OCOTP_SCS_CLR_REG(OCOTP_BASE_PTR) +#define OCOTP_SCS_TOG OCOTP_SCS_TOG_REG(OCOTP_BASE_PTR) +#define OCOTP_CRC_ADDR OCOTP_CRC_ADDR_REG(OCOTP_BASE_PTR) +#define OCOTP_CRC_VALUE OCOTP_CRC_VALUE_REG(OCOTP_BASE_PTR) +#define OCOTP_VERSION OCOTP_VERSION_REG(OCOTP_BASE_PTR) +#define OCOTP_LOCK OCOTP_LOCK_REG(OCOTP_BASE_PTR) +#define OCOTP_TESTER0 OCOTP_TESTER0_REG(OCOTP_BASE_PTR) +#define OCOTP_TESTER1 OCOTP_TESTER1_REG(OCOTP_BASE_PTR) +#define OCOTP_TESTER2 OCOTP_TESTER2_REG(OCOTP_BASE_PTR) +#define OCOTP_TESTER3 OCOTP_TESTER3_REG(OCOTP_BASE_PTR) +#define OCOTP_TESTER4 OCOTP_TESTER4_REG(OCOTP_BASE_PTR) +#define OCOTP_TESTER5 OCOTP_TESTER5_REG(OCOTP_BASE_PTR) +#define OCOTP_BOOT_CFG0 OCOTP_BOOT_CFG0_REG(OCOTP_BASE_PTR) +#define OCOTP_BOOT_CFG1 OCOTP_BOOT_CFG1_REG(OCOTP_BASE_PTR) +#define OCOTP_BOOT_CFG2 OCOTP_BOOT_CFG2_REG(OCOTP_BASE_PTR) +#define OCOTP_BOOT_CFG3 OCOTP_BOOT_CFG3_REG(OCOTP_BASE_PTR) +#define OCOTP_BOOT_CFG4 OCOTP_BOOT_CFG4_REG(OCOTP_BASE_PTR) +#define OCOTP_MEM_TRIM0 OCOTP_MEM_TRIM0_REG(OCOTP_BASE_PTR) +#define OCOTP_MEM_TRIM1 OCOTP_MEM_TRIM1_REG(OCOTP_BASE_PTR) +#define OCOTP_ANA0 OCOTP_ANA0_REG(OCOTP_BASE_PTR) +#define OCOTP_ANA1 OCOTP_ANA1_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK0 OCOTP_OTPMK0_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK1 OCOTP_OTPMK1_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK2 OCOTP_OTPMK2_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK3 OCOTP_OTPMK3_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK4 OCOTP_OTPMK4_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK5 OCOTP_OTPMK5_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK6 OCOTP_OTPMK6_REG(OCOTP_BASE_PTR) +#define OCOTP_OTPMK7 OCOTP_OTPMK7_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK0 OCOTP_SRK0_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK1 OCOTP_SRK1_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK2 OCOTP_SRK2_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK3 OCOTP_SRK3_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK4 OCOTP_SRK4_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK5 OCOTP_SRK5_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK6 OCOTP_SRK6_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK7 OCOTP_SRK7_REG(OCOTP_BASE_PTR) +#define OCOTP_SJC_RESP0 OCOTP_SJC_RESP0_REG(OCOTP_BASE_PTR) +#define OCOTP_SJC_RESP1 OCOTP_SJC_RESP1_REG(OCOTP_BASE_PTR) +#define OCOTP_USB_ID OCOTP_USB_ID_REG(OCOTP_BASE_PTR) +#define OCOTP_FIELD_RETURN OCOTP_FIELD_RETURN_REG(OCOTP_BASE_PTR) +#define OCOTP_MAC_ADDR0 OCOTP_MAC_ADDR0_REG(OCOTP_BASE_PTR) +#define OCOTP_MAC_ADDR1 OCOTP_MAC_ADDR1_REG(OCOTP_BASE_PTR) +#define OCOTP_MAC_ADDR2 OCOTP_MAC_ADDR2_REG(OCOTP_BASE_PTR) +#define OCOTP_SRK_REVOKE OCOTP_SRK_REVOKE_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY0 OCOTP_MAU_KEY0_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY1 OCOTP_MAU_KEY1_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY2 OCOTP_MAU_KEY2_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY3 OCOTP_MAU_KEY3_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY4 OCOTP_MAU_KEY4_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY5 OCOTP_MAU_KEY5_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY6 OCOTP_MAU_KEY6_REG(OCOTP_BASE_PTR) +#define OCOTP_MAU_KEY7 OCOTP_MAU_KEY7_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH0 OCOTP_ROM_PATCH0_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH1 OCOTP_ROM_PATCH1_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH2 OCOTP_ROM_PATCH2_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH3 OCOTP_ROM_PATCH3_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH4 OCOTP_ROM_PATCH4_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH5 OCOTP_ROM_PATCH5_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH6 OCOTP_ROM_PATCH6_REG(OCOTP_BASE_PTR) +#define OCOTP_ROM_PATCH7 OCOTP_ROM_PATCH7_REG(OCOTP_BASE_PTR) +#define OCOTP_GP10 OCOTP_GP10_REG(OCOTP_BASE_PTR) +#define OCOTP_GP11 OCOTP_GP11_REG(OCOTP_BASE_PTR) +#define OCOTP_GP20 OCOTP_GP20_REG(OCOTP_BASE_PTR) +#define OCOTP_GP21 OCOTP_GP21_REG(OCOTP_BASE_PTR) +#define OCOTP_CRC_GP10 OCOTP_CRC_GP10_REG(OCOTP_BASE_PTR) +#define OCOTP_CRC_GP11 OCOTP_CRC_GP11_REG(OCOTP_BASE_PTR) +#define OCOTP_CRC_GP20 OCOTP_CRC_GP20_REG(OCOTP_BASE_PTR) +#define OCOTP_CRC_GP21 OCOTP_CRC_GP21_REG(OCOTP_BASE_PTR) + +/*! + * @} + */ /* end of group OCOTP_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group OCOTP_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_CMN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_CMN_Peripheral_Access_Layer PCIE_PHY_CMN Peripheral Access Layer + * @{ + */ + +/** PCIE_PHY_CMN - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t REG01; /**< Impedance Calibration Register, offset: 0x4 */ + __IO uint32_t REG02; /**< , offset: 0x8 */ + uint8_t RESERVED_1[6]; + __IO uint32_t REG03; /**< , offset: 0x12 */ + __IO uint32_t REG04; /**< , offset: 0x16 */ + uint8_t RESERVED_2[6]; + __IO uint32_t REG05; /**< , offset: 0x20 */ + __IO uint32_t REG06; /**< , offset: 0x24 */ + __IO uint32_t REG07; /**< , offset: 0x28 */ + __IO uint32_t REG0B; /**< , offset: 0x2C */ + uint8_t RESERVED_3[2]; + __IO uint32_t REG08; /**< , offset: 0x32 */ + __IO uint32_t REG09; /**< , offset: 0x36 */ + uint8_t RESERVED_4[6]; + __IO uint32_t REG11; /**< , offset: 0x40 */ + uint8_t RESERVED_5[28]; + __IO uint32_t REG15; /**< , offset: 0x60 */ + __IO uint32_t REG16; /**< , offset: 0x64 */ + __IO uint32_t REG17; /**< , offset: 0x68 */ + uint8_t RESERVED_6[6]; + __IO uint32_t REG18; /**< , offset: 0x72 */ + __IO uint32_t REG19; /**< , offset: 0x76 */ + uint8_t RESERVED_7[6]; + __IO uint32_t REG1A; /**< , offset: 0x80 */ +} PCIE_PHY_CMN_Type, *PCIE_PHY_CMN_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_CMN - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_CMN_Register_Accessor_Macros PCIE_PHY_CMN - Register accessor macros + * @{ + */ + + +/* PCIE_PHY_CMN - Register accessors */ +#define PCIE_PHY_CMN_REG01_REG(base) ((base)->REG01) +#define PCIE_PHY_CMN_REG02_REG(base) ((base)->REG02) +#define PCIE_PHY_CMN_REG03_REG(base) ((base)->REG03) +#define PCIE_PHY_CMN_REG04_REG(base) ((base)->REG04) +#define PCIE_PHY_CMN_REG05_REG(base) ((base)->REG05) +#define PCIE_PHY_CMN_REG06_REG(base) ((base)->REG06) +#define PCIE_PHY_CMN_REG07_REG(base) ((base)->REG07) +#define PCIE_PHY_CMN_REG0B_REG(base) ((base)->REG0B) +#define PCIE_PHY_CMN_REG08_REG(base) ((base)->REG08) +#define PCIE_PHY_CMN_REG09_REG(base) ((base)->REG09) +#define PCIE_PHY_CMN_REG11_REG(base) ((base)->REG11) +#define PCIE_PHY_CMN_REG15_REG(base) ((base)->REG15) +#define PCIE_PHY_CMN_REG16_REG(base) ((base)->REG16) +#define PCIE_PHY_CMN_REG17_REG(base) ((base)->REG17) +#define PCIE_PHY_CMN_REG18_REG(base) ((base)->REG18) +#define PCIE_PHY_CMN_REG19_REG(base) ((base)->REG19) +#define PCIE_PHY_CMN_REG1A_REG(base) ((base)->REG1A) + +/*! + * @} + */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_CMN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_CMN_Register_Masks PCIE_PHY_CMN Register Masks + * @{ + */ + +/* REG01 Bit Fields */ +#define PCIE_PHY_CMN_REG01_TCODE_MASK 0xFu +#define PCIE_PHY_CMN_REG01_TCODE_SHIFT 0 +#define PCIE_PHY_CMN_REG01_TCODE(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG01_TCODE_SHIFT))&PCIE_PHY_CMN_REG01_TCODE_MASK) +#define PCIE_PHY_CMN_REG01_RCODE_MASK 0xF0u +#define PCIE_PHY_CMN_REG01_RCODE_SHIFT 4 +#define PCIE_PHY_CMN_REG01_RCODE(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG01_RCODE_SHIFT))&PCIE_PHY_CMN_REG01_RCODE_MASK) +/* REG02 Bit Fields */ +#define PCIE_PHY_CMN_REG02_FORCE_MASK 0x1u +#define PCIE_PHY_CMN_REG02_FORCE_SHIFT 0 +#define PCIE_PHY_CMN_REG02_PDIV_MASK 0xF0u +#define PCIE_PHY_CMN_REG02_PDIV_SHIFT 4 +#define PCIE_PHY_CMN_REG02_PDIV(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG02_PDIV_SHIFT))&PCIE_PHY_CMN_REG02_PDIV_MASK) +/* REG03 Bit Fields */ +#define PCIE_PHY_CMN_REG03_CTRL_CP_MASK 0xFu +#define PCIE_PHY_CMN_REG03_CTRL_CP_SHIFT 0 +#define PCIE_PHY_CMN_REG03_CTRL_CP(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG03_CTRL_CP_SHIFT))&PCIE_PHY_CMN_REG03_CTRL_CP_MASK) +/* REG04 Bit Fields */ +#define PCIE_PHY_CMN_REG04_CTRL_C_MASK 0xEu +#define PCIE_PHY_CMN_REG04_CTRL_C_SHIFT 1 +#define PCIE_PHY_CMN_REG04_CTRL_C(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG04_CTRL_C_SHIFT))&PCIE_PHY_CMN_REG04_CTRL_C_MASK) +#define PCIE_PHY_CMN_REG04_CTRL_R_MASK 0xF0u +#define PCIE_PHY_CMN_REG04_CTRL_R_SHIFT 4 +#define PCIE_PHY_CMN_REG04_CTRL_R(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG04_CTRL_R_SHIFT))&PCIE_PHY_CMN_REG04_CTRL_R_MASK) +/* REG05 Bit Fields */ +#define PCIE_PHY_CMN_REG05_DCC_FB_EN_MASK 0x40u +#define PCIE_PHY_CMN_REG05_DCC_FB_EN_SHIFT 6 +#define PCIE_PHY_CMN_REG05_CKFB_MON_EN_MASK 0x80u +#define PCIE_PHY_CMN_REG05_CKFB_MON_EN_SHIFT 7 +/* REG06 Bit Fields */ +#define PCIE_PHY_CMN_REG06_SD_DIV_MASK 0x7u +#define PCIE_PHY_CMN_REG06_SD_DIV_SHIFT 0 +#define PCIE_PHY_CMN_REG06_SD_DIV(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG06_SD_DIV_SHIFT))&PCIE_PHY_CMN_REG06_SD_DIV_MASK) +#define PCIE_PHY_CMN_REG06_CK100M_EN_MASK 0x10u +#define PCIE_PHY_CMN_REG06_CK100M_EN_SHIFT 4 +#define PCIE_PHY_CMN_REG06_MDIV_HS_MASK 0x80u +#define PCIE_PHY_CMN_REG06_MDIV_HS_SHIFT 7 +/* REG07 Bit Fields */ +#define PCIE_PHY_CMN_REG07_MDIV_MS_MASK 0xFFu +#define PCIE_PHY_CMN_REG07_MDIV_MS_SHIFT 0 +#define PCIE_PHY_CMN_REG07_MDIV_MS(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG07_MDIV_MS_SHIFT))&PCIE_PHY_CMN_REG07_MDIV_MS_MASK) +/* REG0B Bit Fields */ +#define PCIE_PHY_CMN_REG0B_SSC_MASK 0x7Fu +#define PCIE_PHY_CMN_REG0B_SSC_SHIFT 0 +#define PCIE_PHY_CMN_REG0B_SSC(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG0B_SSC_SHIFT))&PCIE_PHY_CMN_REG0B_SSC_MASK) +/* REG08 Bit Fields */ +#define PCIE_PHY_CMN_REG08_PI_EN_MASK 0x1u +#define PCIE_PHY_CMN_REG08_PI_EN_SHIFT 0 +#define PCIE_PHY_CMN_REG08_PI_STR_MASK 0x1Eu +#define PCIE_PHY_CMN_REG08_PI_STR_SHIFT 1 +#define PCIE_PHY_CMN_REG08_PI_STR(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG08_PI_STR_SHIFT))&PCIE_PHY_CMN_REG08_PI_STR_MASK) +/* REG09 Bit Fields */ +#define PCIE_PHY_CMN_REG09_SSC_CNTL_MASK 0x60u +#define PCIE_PHY_CMN_REG09_SSC_CNTL_SHIFT 5 +#define PCIE_PHY_CMN_REG09_SSC_CNTL(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG09_SSC_CNTL_SHIFT))&PCIE_PHY_CMN_REG09_SSC_CNTL_MASK) +/* REG11 Bit Fields */ +#define PCIE_PHY_CMN_REG11_PREF_MASK 0xFFu +#define PCIE_PHY_CMN_REG11_PREF_SHIFT 0 +#define PCIE_PHY_CMN_REG11_PREF(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG11_PREF_SHIFT))&PCIE_PHY_CMN_REG11_PREF_MASK) +/* REG15 Bit Fields */ +#define PCIE_PHY_CMN_REG15_MON_EN_MASK 0x10u +#define PCIE_PHY_CMN_REG15_MON_EN_SHIFT 4 +#define PCIE_PHY_CMN_REG15_PD_SCMN_MASK 0x60u +#define PCIE_PHY_CMN_REG15_PD_SCMN_SHIFT 5 +#define PCIE_PHY_CMN_REG15_PD_SCMN(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG15_PD_SCMN_SHIFT))&PCIE_PHY_CMN_REG15_PD_SCMN_MASK) +#define PCIE_PHY_CMN_REG15_PHY_CMNPD_EN_MASK 0x80u +#define PCIE_PHY_CMN_REG15_PHY_CMNPD_EN_SHIFT 7 +/* REG16 Bit Fields */ +#define PCIE_PHY_CMN_REG16_PHY_SSC_EN_MASK 0xCu +#define PCIE_PHY_CMN_REG16_PHY_SSC_EN_SHIFT 2 +#define PCIE_PHY_CMN_REG16_PHY_SSC_EN(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG16_PHY_SSC_EN_SHIFT))&PCIE_PHY_CMN_REG16_PHY_SSC_EN_MASK) +/* REG17 Bit Fields */ +#define PCIE_PHY_CMN_REG17_RDIV_MASK 0xFu +#define PCIE_PHY_CMN_REG17_RDIV_SHIFT 0 +#define PCIE_PHY_CMN_REG17_RDIV(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG17_RDIV_SHIFT))&PCIE_PHY_CMN_REG17_RDIV_MASK) +#define PCIE_PHY_CMN_REG17_RDIV_EN_MASK 0x10u +#define PCIE_PHY_CMN_REG17_RDIV_EN_SHIFT 4 +#define PCIE_PHY_CMN_REG17_TG_CODE_EN_MASK 0x80u +#define PCIE_PHY_CMN_REG17_TG_CODE_EN_SHIFT 7 +/* REG18 Bit Fields */ +#define PCIE_PHY_CMN_REG18_TG_CODE_MASK 0xFFu +#define PCIE_PHY_CMN_REG18_TG_CODE_SHIFT 0 +#define PCIE_PHY_CMN_REG18_TG_CODE(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG18_TG_CODE_SHIFT))&PCIE_PHY_CMN_REG18_TG_CODE_MASK) +/* REG19 Bit Fields */ +#define PCIE_PHY_CMN_REG19_TOL_MASK 0x7u +#define PCIE_PHY_CMN_REG19_TOL_SHIFT 0 +#define PCIE_PHY_CMN_REG19_TOL(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG19_TOL_SHIFT))&PCIE_PHY_CMN_REG19_TOL_MASK) +#define PCIE_PHY_CMN_REG19_PD_CMN_MASK 0x8u +#define PCIE_PHY_CMN_REG19_PD_CMN_SHIFT 3 +#define PCIE_PHY_CMN_REG19_RTOL_MASK 0xF0u +#define PCIE_PHY_CMN_REG19_RTOL_SHIFT 4 +#define PCIE_PHY_CMN_REG19_RTOL(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG19_RTOL_SHIFT))&PCIE_PHY_CMN_REG19_RTOL_MASK) +/* REG1A Bit Fields */ +#define PCIE_PHY_CMN_REG1A_CMNRST_MASK 0xFFu +#define PCIE_PHY_CMN_REG1A_CMNRST_SHIFT 0 +#define PCIE_PHY_CMN_REG1A_CMNRST(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_CMN_REG1A_CMNRST_SHIFT))&PCIE_PHY_CMN_REG1A_CMNRST_MASK) + +/*! + * @} + */ /* end of group PCIE_PHY_CMN_Register_Masks */ + + +/* PCIE_PHY_CMN - Peripheral instance base addresses */ +/** Peripheral PCIE_PHY_CMN base address */ +#define PCIE_PHY_CMN_BASE (0x306D0000u) +/** Peripheral PCIE_PHY_CMN base pointer */ +#define PCIE_PHY_CMN ((PCIE_PHY_CMN_Type *)PCIE_PHY_CMN_BASE) +#define PCIE_PHY_CMN_BASE_PTR (PCIE_PHY_CMN) +/** Array initializer of PCIE_PHY_CMN peripheral base adresses */ +#define PCIE_PHY_CMN_BASE_ADDRS { PCIE_PHY_CMN_BASE } +/** Array initializer of PCIE_PHY_CMN peripheral base pointers */ +#define PCIE_PHY_CMN_BASE_PTRS { PCIE_PHY_CMN } + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_CMN - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_CMN_Register_Accessor_Macros PCIE_PHY_CMN - Register accessor macros + * @{ + */ + + +/* PCIE_PHY_CMN - Register instance definitions */ +/* PCIE_PHY_CMN */ +#define PCIE_PHY_CMN_REG01 PCIE_PHY_CMN_REG01_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG02 PCIE_PHY_CMN_REG02_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG03 PCIE_PHY_CMN_REG03_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG04 PCIE_PHY_CMN_REG04_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG05 PCIE_PHY_CMN_REG05_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG06 PCIE_PHY_CMN_REG06_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG07 PCIE_PHY_CMN_REG07_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG0B PCIE_PHY_CMN_REG0B_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG08 PCIE_PHY_CMN_REG08_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG09 PCIE_PHY_CMN_REG09_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG11 PCIE_PHY_CMN_REG11_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG15 PCIE_PHY_CMN_REG15_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG16 PCIE_PHY_CMN_REG16_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG17 PCIE_PHY_CMN_REG17_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG18 PCIE_PHY_CMN_REG18_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG19 PCIE_PHY_CMN_REG19_REG(PCIE_PHY_CMN_BASE_PTR) +#define PCIE_PHY_CMN_REG1A PCIE_PHY_CMN_REG1A_REG(PCIE_PHY_CMN_BASE_PTR) + +/*! + * @} + */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group PCIE_PHY_CMN_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_TRSV Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_TRSV_Peripheral_Access_Layer PCIE_PHY_TRSV Peripheral Access Layer + * @{ + */ + +/** PCIE_PHY_TRSV - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[132]; + __IO uint32_t REG21; /**< , offset: 0x84 */ + __IO uint32_t REG22; /**< , offset: 0x88 */ + uint8_t RESERVED_1[10]; + __IO uint32_t REG24; /**< , offset: 0x96 */ + uint8_t RESERVED_2[18]; + __IO uint32_t REG2B; /**< , offset: 0xAC */ + uint8_t RESERVED_3[56]; + __IO uint32_t REG3A; /**< , offset: 0xE8 */ + uint8_t RESERVED_4[12]; + __IO uint32_t REG3E; /**< , offset: 0xF8 */ + uint8_t RESERVED_5[4]; + __IO uint32_t REG25; /**< , offset: 0x100 */ + __IO uint32_t REG26; /**< , offset: 0x104 */ + uint8_t RESERVED_6[14]; + __IO uint32_t REG29; /**< , offset: 0x116 */ + uint8_t RESERVED_7[10]; + __IO uint32_t REG31; /**< , offset: 0x124 */ + uint8_t RESERVED_8[10]; + __IO uint32_t REG33; /**< , offset: 0x132 */ + uint8_t RESERVED_9[14]; + __IO uint32_t REG36; /**< , offset: 0x144 */ + __IO uint32_t REG37; /**< , offset: 0x148 */ + uint8_t RESERVED_10[6]; + __IO uint32_t REG38; /**< , offset: 0x152 */ + __IO uint32_t REG39; /**< , offset: 0x156 */ + uint8_t RESERVED_11[6]; + __IO uint32_t REG40; /**< , offset: 0x160 */ + uint8_t RESERVED_12[4]; + __IO uint32_t REG42; /**< , offset: 0x168 */ +} PCIE_PHY_TRSV_Type, *PCIE_PHY_TRSV_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_TRSV - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_TRSV_Register_Accessor_Macros PCIE_PHY_TRSV - Register accessor macros + * @{ + */ + + +/* PCIE_PHY_TRSV - Register accessors */ +#define PCIE_PHY_TRSV_REG21_REG(base) ((base)->REG21) +#define PCIE_PHY_TRSV_REG22_REG(base) ((base)->REG22) +#define PCIE_PHY_TRSV_REG24_REG(base) ((base)->REG24) +#define PCIE_PHY_TRSV_REG2B_REG(base) ((base)->REG2B) +#define PCIE_PHY_TRSV_REG3A_REG(base) ((base)->REG3A) +#define PCIE_PHY_TRSV_REG3E_REG(base) ((base)->REG3E) +#define PCIE_PHY_TRSV_REG25_REG(base) ((base)->REG25) +#define PCIE_PHY_TRSV_REG26_REG(base) ((base)->REG26) +#define PCIE_PHY_TRSV_REG29_REG(base) ((base)->REG29) +#define PCIE_PHY_TRSV_REG31_REG(base) ((base)->REG31) +#define PCIE_PHY_TRSV_REG33_REG(base) ((base)->REG33) +#define PCIE_PHY_TRSV_REG36_REG(base) ((base)->REG36) +#define PCIE_PHY_TRSV_REG37_REG(base) ((base)->REG37) +#define PCIE_PHY_TRSV_REG38_REG(base) ((base)->REG38) +#define PCIE_PHY_TRSV_REG39_REG(base) ((base)->REG39) +#define PCIE_PHY_TRSV_REG40_REG(base) ((base)->REG40) +#define PCIE_PHY_TRSV_REG42_REG(base) ((base)->REG42) + +/*! + * @} + */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_TRSV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_TRSV_Register_Masks PCIE_PHY_TRSV Register Masks + * @{ + */ + +/* REG21 Bit Fields */ +#define PCIE_PHY_TRSV_REG21_EMP_LVL_MASK 0x1Fu +#define PCIE_PHY_TRSV_REG21_EMP_LVL_SHIFT 0 +#define PCIE_PHY_TRSV_REG21_EMP_LVL(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG21_EMP_LVL_SHIFT))&PCIE_PHY_TRSV_REG21_EMP_LVL_MASK) +#define PCIE_PHY_TRSV_REG21_DRVR_PDH_MASK 0x80u +#define PCIE_PHY_TRSV_REG21_DRVR_PDH_SHIFT 7 +/* REG22 Bit Fields */ +#define PCIE_PHY_TRSV_REG22_DRV_LVL_MASK 0x3Fu +#define PCIE_PHY_TRSV_REG22_DRV_LVL_SHIFT 0 +#define PCIE_PHY_TRSV_REG22_DRV_LVL(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG22_DRV_LVL_SHIFT))&PCIE_PHY_TRSV_REG22_DRV_LVL_MASK) +/* REG24 Bit Fields */ +#define PCIE_PHY_TRSV_REG24_RX_EQ_SEL_MASK 0x8u +#define PCIE_PHY_TRSV_REG24_RX_EQ_SEL_SHIFT 3 +#define PCIE_PHY_TRSV_REG24_RX_SS_MASK 0x30u +#define PCIE_PHY_TRSV_REG24_RX_SS_SHIFT 4 +#define PCIE_PHY_TRSV_REG24_RX_SS(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG24_RX_SS_SHIFT))&PCIE_PHY_TRSV_REG24_RX_SS_MASK) +#define PCIE_PHY_TRSV_REG24_RX_EQS_MASK 0x40u +#define PCIE_PHY_TRSV_REG24_RX_EQS_SHIFT 6 +#define PCIE_PHY_TRSV_REG24_RX_SS_PD_MASK 0x80u +#define PCIE_PHY_TRSV_REG24_RX_SS_PD_SHIFT 7 +/* REG2B Bit Fields */ +#define PCIE_PHY_TRSV_REG2B_RXCDR_MASK 0xFu +#define PCIE_PHY_TRSV_REG2B_RXCDR_SHIFT 0 +#define PCIE_PHY_TRSV_REG2B_RXCDR(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG2B_RXCDR_SHIFT))&PCIE_PHY_TRSV_REG2B_RXCDR_MASK) +/* REG3A Bit Fields */ +#define PCIE_PHY_TRSV_REG3A_TDIMODE_MASK 0x1u +#define PCIE_PHY_TRSV_REG3A_TDIMODE_SHIFT 0 +#define PCIE_PHY_TRSV_REG3A_RDIMODE_MASK 0x2u +#define PCIE_PHY_TRSV_REG3A_RDIMODE_SHIFT 1 +#define PCIE_PHY_TRSV_REG3A_COMDET_EN_MASK 0x8u +#define PCIE_PHY_TRSV_REG3A_COMDET_EN_SHIFT 3 +/* REG3E Bit Fields */ +#define PCIE_PHY_TRSV_REG3E_DET_CNT_MASK 0xFu +#define PCIE_PHY_TRSV_REG3E_DET_CNT_SHIFT 0 +#define PCIE_PHY_TRSV_REG3E_DET_CNT(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG3E_DET_CNT_SHIFT))&PCIE_PHY_TRSV_REG3E_DET_CNT_MASK) +/* REG25 Bit Fields */ +#define PCIE_PHY_TRSV_REG25_RXEQS_MASK 0x7u +#define PCIE_PHY_TRSV_REG25_RXEQS_SHIFT 0 +#define PCIE_PHY_TRSV_REG25_RXEQS(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG25_RXEQS_SHIFT))&PCIE_PHY_TRSV_REG25_RXEQS_MASK) +#define PCIE_PHY_TRSV_REG25_RXEQ_MASK 0xF0u +#define PCIE_PHY_TRSV_REG25_RXEQ_SHIFT 4 +#define PCIE_PHY_TRSV_REG25_RXEQ(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG25_RXEQ_SHIFT))&PCIE_PHY_TRSV_REG25_RXEQ_MASK) +/* REG26 Bit Fields */ +#define PCIE_PHY_TRSV_REG26_SQTH_MASK 0x70u +#define PCIE_PHY_TRSV_REG26_SQTH_SHIFT 4 +#define PCIE_PHY_TRSV_REG26_SQTH(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG26_SQTH_SHIFT))&PCIE_PHY_TRSV_REG26_SQTH_MASK) +/* REG29 Bit Fields */ +#define PCIE_PHY_TRSV_REG29_BIAS_MASK 0xFFu +#define PCIE_PHY_TRSV_REG29_BIAS_SHIFT 0 +#define PCIE_PHY_TRSV_REG29_BIAS(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG29_BIAS_SHIFT))&PCIE_PHY_TRSV_REG29_BIAS_MASK) +/* REG31 Bit Fields */ +#define PCIE_PHY_TRSV_REG31_PD_TSV_MASK 0x80u +#define PCIE_PHY_TRSV_REG31_PD_TSV_SHIFT 7 +/* REG36 Bit Fields */ +#define PCIE_PHY_TRSV_REG36_SR_LVL_MASK 0x7u +#define PCIE_PHY_TRSV_REG36_SR_LVL_SHIFT 0 +#define PCIE_PHY_TRSV_REG36_SR_LVL(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG36_SR_LVL_SHIFT))&PCIE_PHY_TRSV_REG36_SR_LVL_MASK) +#define PCIE_PHY_TRSV_REG36_TX_SWING_MASK 0x8u +#define PCIE_PHY_TRSV_REG36_TX_SWING_SHIFT 3 +#define PCIE_PHY_TRSV_REG36_DRVR_CNT_MASK 0x30u +#define PCIE_PHY_TRSV_REG36_DRVR_CNT_SHIFT 4 +#define PCIE_PHY_TRSV_REG36_DRVR_CNT(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG36_DRVR_CNT_SHIFT))&PCIE_PHY_TRSV_REG36_DRVR_CNT_MASK) +/* REG38 Bit Fields */ +#define PCIE_PHY_TRSV_REG38_ADD_ALIGN_MASK 0x8u +#define PCIE_PHY_TRSV_REG38_ADD_ALIGN_SHIFT 3 +#define PCIE_PHY_TRSV_REG38_RX_INV_MASK 0x10u +#define PCIE_PHY_TRSV_REG38_RX_INV_SHIFT 4 +#define PCIE_PHY_TRSV_REG38_TX_INV_MASK 0x20u +#define PCIE_PHY_TRSV_REG38_TX_INV_SHIFT 5 +/* REG39 Bit Fields */ +#define PCIE_PHY_TRSV_REG39_TD_ORD_MASK 0x30u +#define PCIE_PHY_TRSV_REG39_TD_ORD_SHIFT 4 +#define PCIE_PHY_TRSV_REG39_TD_ORD(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG39_TD_ORD_SHIFT))&PCIE_PHY_TRSV_REG39_TD_ORD_MASK) +#define PCIE_PHY_TRSV_REG39_RD_ORD_MASK 0xC0u +#define PCIE_PHY_TRSV_REG39_RD_ORD_SHIFT 6 +#define PCIE_PHY_TRSV_REG39_RD_ORD(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG39_RD_ORD_SHIFT))&PCIE_PHY_TRSV_REG39_RD_ORD_MASK) +/* REG40 Bit Fields */ +#define PCIE_PHY_TRSV_REG40_PD_TRAS_MASK 0x7Cu +#define PCIE_PHY_TRSV_REG40_PD_TRAS_SHIFT 2 +#define PCIE_PHY_TRSV_REG40_PD_TRAS(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG40_PD_TRAS_SHIFT))&PCIE_PHY_TRSV_REG40_PD_TRAS_MASK) +#define PCIE_PHY_TRSV_REG40_PHY_TRSV_EN_MASK 0x80u +#define PCIE_PHY_TRSV_REG40_PHY_TRSV_EN_SHIFT 7 +/* REG42 Bit Fields */ +#define PCIE_PHY_TRSV_REG42_TRSVRST_MASK 0xFFu +#define PCIE_PHY_TRSV_REG42_TRSVRST_SHIFT 0 +#define PCIE_PHY_TRSV_REG42_TRSVRST(x) (((uint32_t)(((uint32_t)(x))<<PCIE_PHY_TRSV_REG42_TRSVRST_SHIFT))&PCIE_PHY_TRSV_REG42_TRSVRST_MASK) + +/*! + * @} + */ /* end of group PCIE_PHY_TRSV_Register_Masks */ + + +/* PCIE_PHY_TRSV - Peripheral instance base addresses */ +/** Peripheral PCIE_PHY_TRSV base address */ +#define PCIE_PHY_TRSV_BASE (0x306D0000u) +/** Peripheral PCIE_PHY_TRSV base pointer */ +#define PCIE_PHY_TRSV ((PCIE_PHY_TRSV_Type *)PCIE_PHY_TRSV_BASE) +#define PCIE_PHY_TRSV_BASE_PTR (PCIE_PHY_TRSV) +/** Array initializer of PCIE_PHY_TRSV peripheral base adresses */ +#define PCIE_PHY_TRSV_BASE_ADDRS { PCIE_PHY_TRSV_BASE } +/** Array initializer of PCIE_PHY_TRSV peripheral base pointers */ +#define PCIE_PHY_TRSV_BASE_PTRS { PCIE_PHY_TRSV } + +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_TRSV - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_TRSV_Register_Accessor_Macros PCIE_PHY_TRSV - Register accessor macros + * @{ + */ + + +/* PCIE_PHY_TRSV - Register instance definitions */ +/* PCIE_PHY_TRSV */ +#define PCIE_PHY_TRSV_REG21 PCIE_PHY_TRSV_REG21_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG22 PCIE_PHY_TRSV_REG22_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG24 PCIE_PHY_TRSV_REG24_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG2B PCIE_PHY_TRSV_REG2B_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG3A PCIE_PHY_TRSV_REG3A_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG3E PCIE_PHY_TRSV_REG3E_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG25 PCIE_PHY_TRSV_REG25_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG26 PCIE_PHY_TRSV_REG26_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG29 PCIE_PHY_TRSV_REG29_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG31 PCIE_PHY_TRSV_REG31_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG33 PCIE_PHY_TRSV_REG33_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG36 PCIE_PHY_TRSV_REG36_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG37 PCIE_PHY_TRSV_REG37_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG38 PCIE_PHY_TRSV_REG38_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG39 PCIE_PHY_TRSV_REG39_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG40 PCIE_PHY_TRSV_REG40_REG(PCIE_PHY_TRSV_BASE_PTR) +#define PCIE_PHY_TRSV_REG42 PCIE_PHY_TRSV_REG42_REG(PCIE_PHY_TRSV_BASE_PTR) + +/*! + * @} + */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group PCIE_PHY_TRSV_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[608]; + __IO uint32_t GPU_CTRL; /**< PGC Control Register, offset: 0x260 */ + __IO uint32_t GPU_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x264 */ + __IO uint32_t GPU_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x268 */ + __I uint32_t GPU_SR; /**< Power Gating Controller Status Register, offset: 0x26C */ + uint8_t RESERVED_1[48]; + __IO uint32_t CPU_CTRL; /**< PGC Control Register, offset: 0x2A0 */ + __IO uint32_t CPU_PUPSCR; /**< Power Up Sequence Control Register, offset: 0x2A4 */ + __IO uint32_t CPU_PDNSCR; /**< Pull Down Sequence Control Register, offset: 0x2A8 */ + __I uint32_t CPU_SR; /**< Power Gating Controller Status Register, offset: 0x2AC */ +} PGC_Type, *PGC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PGC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros + * @{ + */ + + +/* PGC - Register accessors */ +#define PGC_GPU_CTRL_REG(base) ((base)->GPU_CTRL) +#define PGC_GPU_PUPSCR_REG(base) ((base)->GPU_PUPSCR) +#define PGC_GPU_PDNSCR_REG(base) ((base)->GPU_PDNSCR) +#define PGC_GPU_SR_REG(base) ((base)->GPU_SR) +#define PGC_CPU_CTRL_REG(base) ((base)->CPU_CTRL) +#define PGC_CPU_PUPSCR_REG(base) ((base)->CPU_PUPSCR) +#define PGC_CPU_PDNSCR_REG(base) ((base)->CPU_PDNSCR) +#define PGC_CPU_SR_REG(base) ((base)->CPU_SR) + +/*! + * @} + */ /* end of group PGC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/* GPU_CTRL Bit Fields */ +#define PGC_GPU_CTRL_PCR_MASK 0x1u +#define PGC_GPU_CTRL_PCR_SHIFT 0 +/* GPU_PUPSCR Bit Fields */ +#define PGC_GPU_PUPSCR_SW_MASK 0x3Fu +#define PGC_GPU_PUPSCR_SW_SHIFT 0 +#define PGC_GPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW_SHIFT))&PGC_GPU_PUPSCR_SW_MASK) +#define PGC_GPU_PUPSCR_SW2ISO_MASK 0x3F00u +#define PGC_GPU_PUPSCR_SW2ISO_SHIFT 8 +#define PGC_GPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PUPSCR_SW2ISO_SHIFT))&PGC_GPU_PUPSCR_SW2ISO_MASK) +/* GPU_PDNSCR Bit Fields */ +#define PGC_GPU_PDNSCR_ISO_MASK 0x3Fu +#define PGC_GPU_PDNSCR_ISO_SHIFT 0 +#define PGC_GPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO_SHIFT))&PGC_GPU_PDNSCR_ISO_MASK) +#define PGC_GPU_PDNSCR_ISO2SW_MASK 0x3F00u +#define PGC_GPU_PDNSCR_ISO2SW_SHIFT 8 +#define PGC_GPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_GPU_PDNSCR_ISO2SW_SHIFT))&PGC_GPU_PDNSCR_ISO2SW_MASK) +/* GPU_SR Bit Fields */ +#define PGC_GPU_SR_PSR_MASK 0x1u +#define PGC_GPU_SR_PSR_SHIFT 0 +/* CPU_CTRL Bit Fields */ +#define PGC_CPU_CTRL_PCR_MASK 0x1u +#define PGC_CPU_CTRL_PCR_SHIFT 0 +/* CPU_PUPSCR Bit Fields */ +#define PGC_CPU_PUPSCR_SW_MASK 0x3Fu +#define PGC_CPU_PUPSCR_SW_SHIFT 0 +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW_SHIFT))&PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK 0x3F00u +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT 8 +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PUPSCR_SW2ISO_SHIFT))&PGC_CPU_PUPSCR_SW2ISO_MASK) +/* CPU_PDNSCR Bit Fields */ +#define PGC_CPU_PDNSCR_ISO_MASK 0x3Fu +#define PGC_CPU_PDNSCR_ISO_SHIFT 0 +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO_SHIFT))&PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK 0x3F00u +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT 8 +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x))<<PGC_CPU_PDNSCR_ISO2SW_SHIFT))&PGC_CPU_PDNSCR_ISO2SW_MASK) +/* CPU_SR Bit Fields */ +#define PGC_CPU_SR_PSR_MASK 0x1u +#define PGC_CPU_SR_PSR_SHIFT 0 + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC_ARM base address */ +#define PGC_ARM_BASE (0x303A0040u) +/** Peripheral PGC_ARM base pointer */ +#define PGC_ARM ((PGC_ARM_Type *)PGC_ARM_BASE) +#define PGC_ARM_BASE_PTR (PGC_ARM) +/** Peripheral PGC_GPU base address */ +#define PGC_GPU_BASE (0x303A0000u) +/** Peripheral PGC_GPU base pointer */ +#define PGC_GPU ((PGC_GPU_Type *)PGC_GPU_BASE) +#define PGC_GPU_BASE_PTR (PGC_GPU) +/** Array initializer of PGC peripheral base adresses */ +#define PGC_BASE_ADDRS { PGC_ARM_BASE, PGC_GPU_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC_ARM, PGC_GPU } + +/* ---------------------------------------------------------------------------- + -- PGC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Accessor_Macros PGC - Register accessor macros + * @{ + */ + + +/* PGC - Register instance definitions */ +/* PGC_ARM */ +#define PGC_ARM_GPU_CTRL PGC_GPU_CTRL_REG(PGC_ARM_BASE_PTR) +#define PGC_ARM_GPU_PUPSCR PGC_GPU_PUPSCR_REG(PGC_ARM_BASE_PTR) +#define PGC_ARM_GPU_PDNSCR PGC_GPU_PDNSCR_REG(PGC_ARM_BASE_PTR) +#define PGC_ARM_GPU_SR PGC_GPU_SR_REG(PGC_ARM_BASE_PTR) +#define PGC_ARM_CPU_CTRL PGC_CPU_CTRL_REG(PGC_ARM_BASE_PTR) +#define PGC_ARM_CPU_PUPSCR PGC_CPU_PUPSCR_REG(PGC_ARM_BASE_PTR) +#define PGC_ARM_CPU_PDNSCR PGC_CPU_PDNSCR_REG(PGC_ARM_BASE_PTR) +#define PGC_ARM_CPU_SR PGC_CPU_SR_REG(PGC_ARM_BASE_PTR) +/* PGC_GPU */ +#define PGC_GPU_GPU_CTRL PGC_GPU_CTRL_REG(PGC_GPU_BASE_PTR) +#define PGC_GPU_GPU_PUPSCR PGC_GPU_PUPSCR_REG(PGC_GPU_BASE_PTR) +#define PGC_GPU_GPU_PDNSCR PGC_GPU_PDNSCR_REG(PGC_GPU_BASE_PTR) +#define PGC_GPU_GPU_SR PGC_GPU_SR_REG(PGC_GPU_BASE_PTR) +#define PGC_GPU_CPU_CTRL PGC_CPU_CTRL_REG(PGC_GPU_BASE_PTR) +#define PGC_GPU_CPU_PUPSCR PGC_CPU_PUPSCR_REG(PGC_GPU_BASE_PTR) +#define PGC_GPU_CPU_PDNSCR PGC_CPU_PDNSCR_REG(PGC_GPU_BASE_PTR) +#define PGC_GPU_CPU_SR PGC_CPU_SR_REG(PGC_GPU_BASE_PTR) + +/*! + * @} + */ /* end of group PGC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group PGC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[512]; + __IO uint32_t REG_1P0A; /**< Anadig 1.0V A Regulator Control Register, offset: 0x200 */ + __IO uint32_t REG_1P0A_SET; /**< Anadig 1.0V A Regulator Control Register, offset: 0x204 */ + __IO uint32_t REG_1P0A_CLR; /**< Anadig 1.0V A Regulator Control Register, offset: 0x208 */ + __IO uint32_t REG_1P0A_TOG; /**< Anadig 1.0V A Regulator Control Register, offset: 0x20C */ + __IO uint32_t REG_1P0D; /**< Anadig 1.0V D Regulator Control Register, offset: 0x210 */ + __IO uint32_t REG_1P0D_SET; /**< Anadig 1.0V D Regulator Control Register, offset: 0x214 */ + __IO uint32_t REG_1P0D_CLR; /**< Anadig 1.0V D Regulator Control Register, offset: 0x218 */ + __IO uint32_t REG_1P0D_TOG; /**< Anadig 1.0V D Regulator Control Register, offset: 0x21C */ + __IO uint32_t REG_HSIC_1P2; /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x220 */ + __IO uint32_t REG_HSIC_1P2_SET; /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x224 */ + __IO uint32_t REG_HSIC_1P2_CLR; /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x228 */ + __IO uint32_t REG_HSIC_1P2_TOG; /**< Anadig 1.2V HSIC Regulator Control Register, offset: 0x22C */ + __IO uint32_t REG_LPSR_1P0; /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x230 */ + __IO uint32_t REG_LPSR_1P0_SET; /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x234 */ + __IO uint32_t REG_LPSR_1P0_CLR; /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x238 */ + __IO uint32_t REG_LPSR_1P0_TOG; /**< Anadig 1.0V Low Power State Retention Regulator Control Register, offset: 0x23C */ + __IO uint32_t REG_3P0; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x240 */ + __IO uint32_t REG_3P0_SET; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x244 */ + __IO uint32_t REG_3P0_CLR; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x248 */ + __IO uint32_t REG_3P0_TOG; /**< Anadig 3.0V USB Regulator Control Register, offset: 0x24C */ + uint8_t RESERVED_1[32]; + __IO uint32_t REF; /**< Anadig Reference Analog Control and Status Register, offset: 0x270 */ + __IO uint32_t REF_SET; /**< Anadig Reference Analog Control and Status Register, offset: 0x274 */ + __IO uint32_t REF_CLR; /**< Anadig Reference Analog Control and Status Register, offset: 0x278 */ + __IO uint32_t REF_TOG; /**< Anadig Reference Analog Control and Status Register, offset: 0x27C */ + uint8_t RESERVED_2[176]; + __IO uint32_t LOWPWR_CTRL; /**< Anadig Low Power Control Register, offset: 0x330 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< Anadig Low Power Control Register, offset: 0x334 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< Anadig Low Power Control Register, offset: 0x338 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< Anadig Low Power Control Register, offset: 0x33C */ +} PMU_Type, *PMU_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PMU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros + * @{ + */ + + +/* PMU - Register accessors */ +#define PMU_REG_1P0A_REG(base) ((base)->REG_1P0A) +#define PMU_REG_1P0A_SET_REG(base) ((base)->REG_1P0A_SET) +#define PMU_REG_1P0A_CLR_REG(base) ((base)->REG_1P0A_CLR) +#define PMU_REG_1P0A_TOG_REG(base) ((base)->REG_1P0A_TOG) +#define PMU_REG_1P0D_REG(base) ((base)->REG_1P0D) +#define PMU_REG_1P0D_SET_REG(base) ((base)->REG_1P0D_SET) +#define PMU_REG_1P0D_CLR_REG(base) ((base)->REG_1P0D_CLR) +#define PMU_REG_1P0D_TOG_REG(base) ((base)->REG_1P0D_TOG) +#define PMU_REG_HSIC_1P2_REG(base) ((base)->REG_HSIC_1P2) +#define PMU_REG_HSIC_1P2_SET_REG(base) ((base)->REG_HSIC_1P2_SET) +#define PMU_REG_HSIC_1P2_CLR_REG(base) ((base)->REG_HSIC_1P2_CLR) +#define PMU_REG_HSIC_1P2_TOG_REG(base) ((base)->REG_HSIC_1P2_TOG) +#define PMU_REG_LPSR_1P0_REG(base) ((base)->REG_LPSR_1P0) +#define PMU_REG_LPSR_1P0_SET_REG(base) ((base)->REG_LPSR_1P0_SET) +#define PMU_REG_LPSR_1P0_CLR_REG(base) ((base)->REG_LPSR_1P0_CLR) +#define PMU_REG_LPSR_1P0_TOG_REG(base) ((base)->REG_LPSR_1P0_TOG) +#define PMU_REG_3P0_REG(base) ((base)->REG_3P0) +#define PMU_REG_3P0_SET_REG(base) ((base)->REG_3P0_SET) +#define PMU_REG_3P0_CLR_REG(base) ((base)->REG_3P0_CLR) +#define PMU_REG_3P0_TOG_REG(base) ((base)->REG_3P0_TOG) +#define PMU_REF_REG(base) ((base)->REF) +#define PMU_REF_SET_REG(base) ((base)->REF_SET) +#define PMU_REF_CLR_REG(base) ((base)->REF_CLR) +#define PMU_REF_TOG_REG(base) ((base)->REF_TOG) +#define PMU_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) +#define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) +#define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) +#define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) + +/*! + * @} + */ /* end of group PMU_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/* REG_1P0A Bit Fields */ +#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK) +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK) +#define PMU_REG_1P0A_BO_MASK 0x10000u +#define PMU_REG_1P0A_BO_SHIFT 16 +#define PMU_REG_1P0A_OK_MASK 0x20000u +#define PMU_REG_1P0A_OK_SHIFT 17 +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK) +#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK) +/* REG_1P0A_SET Bit Fields */ +#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK) +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK) +#define PMU_REG_1P0A_SET_BO_MASK 0x10000u +#define PMU_REG_1P0A_SET_BO_SHIFT 16 +#define PMU_REG_1P0A_SET_OK_MASK 0x20000u +#define PMU_REG_1P0A_SET_OK_SHIFT 17 +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK) +#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK) +/* REG_1P0A_CLR Bit Fields */ +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK) +#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u +#define PMU_REG_1P0A_CLR_BO_SHIFT 16 +#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u +#define PMU_REG_1P0A_CLR_OK_SHIFT 17 +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK) +#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK) +/* REG_1P0A_TOG Bit Fields */ +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13 +#define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK) +#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u +#define PMU_REG_1P0A_TOG_BO_SHIFT 16 +#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u +#define PMU_REG_1P0A_TOG_OK_SHIFT 17 +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK) +#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u +#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24 +#define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK) +/* REG_1P0D Bit Fields */ +#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK) +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK) +#define PMU_REG_1P0D_BO_MASK 0x10000u +#define PMU_REG_1P0D_BO_SHIFT 16 +#define PMU_REG_1P0D_OK_MASK 0x20000u +#define PMU_REG_1P0D_OK_SHIFT 17 +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK) +#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK) +#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_OVERRIDE_SHIFT 31 +/* REG_1P0D_SET Bit Fields */ +#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK) +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK) +#define PMU_REG_1P0D_SET_BO_MASK 0x10000u +#define PMU_REG_1P0D_SET_BO_SHIFT 16 +#define PMU_REG_1P0D_SET_OK_MASK 0x20000u +#define PMU_REG_1P0D_SET_OK_SHIFT 17 +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK) +#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK) +#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31 +/* REG_1P0D_CLR Bit Fields */ +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK) +#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u +#define PMU_REG_1P0D_CLR_BO_SHIFT 16 +#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u +#define PMU_REG_1P0D_CLR_OK_SHIFT 17 +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK) +#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK) +#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31 +/* REG_1P0D_TOG Bit Fields */ +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13 +#define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK) +#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u +#define PMU_REG_1P0D_TOG_BO_SHIFT 16 +#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u +#define PMU_REG_1P0D_TOG_OK_SHIFT 17 +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK) +#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u +#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24 +#define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK) +#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u +#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2 Bit Fields */ +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_SET Bit Fields */ +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_CLR Bit Fields */ +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31 +/* REG_HSIC_1P2_TOG Bit Fields */ +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK) +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13 +#define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK) +#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u +#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16 +#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u +#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17 +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK) +#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u +#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24 +#define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK) +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31 +/* REG_LPSR_1P0 Bit Fields */ +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK) +/* REG_LPSR_1P0_SET Bit Fields */ +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK) +/* REG_LPSR_1P0_CLR Bit Fields */ +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK) +/* REG_LPSR_1P0_TOG Bit Fields */ +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7 +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u +#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13 +#define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK) +#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u +#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16 +#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u +#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17 +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18 +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19 +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20 +#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK) +#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u +#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 +#define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK) +/* REG_3P0 Bit Fields */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_RSVD0_MASK 0x8u +#define PMU_REG_3P0_RSVD0_SHIFT 3 +#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_RSVD1_SHIFT 13 +#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK) +#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_RSVD2_SHIFT 22 +#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK) +/* REG_3P0_SET Bit Fields */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u +#define PMU_REG_3P0_SET_RSVD0_SHIFT 3 +#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_SET_RSVD1_SHIFT 13 +#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK) +#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_SET_RSVD2_SHIFT 22 +#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK) +/* REG_3P0_CLR Bit Fields */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u +#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 +#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK) +#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 +#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK) +/* REG_3P0_TOG Bit Fields */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u +#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u +#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 +#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 +#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u +#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 +#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK) +#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u +#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 +#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK) +/* REF Bit Fields */ +#define PMU_REF_REFTOP_PWD_MASK 0x1u +#define PMU_REF_REFTOP_PWD_SHIFT 0 +#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK) +#define PMU_REF_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK) +#define PMU_REF_LPBG_SEL_MASK 0x400u +#define PMU_REF_LPBG_SEL_SHIFT 10 +#define PMU_REF_LPBG_TEST_MASK 0x800u +#define PMU_REF_LPBG_TEST_SHIFT 11 +#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_RSVD1_SHIFT 14 +#define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK) +/* REF_SET Bit Fields */ +#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u +#define PMU_REF_SET_REFTOP_PWD_SHIFT 0 +#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK) +#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK) +#define PMU_REF_SET_LPBG_SEL_MASK 0x400u +#define PMU_REF_SET_LPBG_SEL_SHIFT 10 +#define PMU_REF_SET_LPBG_TEST_MASK 0x800u +#define PMU_REF_SET_LPBG_TEST_SHIFT 11 +#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_SET_RSVD1_SHIFT 14 +#define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK) +/* REF_CLR Bit Fields */ +#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u +#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0 +#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK) +#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK) +#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u +#define PMU_REF_CLR_LPBG_SEL_SHIFT 10 +#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u +#define PMU_REF_CLR_LPBG_TEST_SHIFT 11 +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_CLR_RSVD1_SHIFT 14 +#define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK) +/* REF_TOG Bit Fields */ +#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u +#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0 +#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u +#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1 +#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u +#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2 +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3 +#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u +#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4 +#define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK) +#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u +#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7 +#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u +#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8 +#define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK) +#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u +#define PMU_REF_TOG_LPBG_SEL_SHIFT 10 +#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u +#define PMU_REF_TOG_LPBG_TEST_SHIFT 11 +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12 +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13 +#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u +#define PMU_REF_TOG_RSVD1_SHIFT 14 +#define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK) +/* LOWPWR_CTRL Bit Fields */ +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK) +/* LOWPWR_CTRL_SET Bit Fields */ +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK) +/* LOWPWR_CTRL_CLR Bit Fields */ +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK) +/* LOWPWR_CTRL_TOG Bit Fields */ +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0 +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu +#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2 +#define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12 +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13 +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14 +#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK) +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 +#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x30360000u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +#define PMU_BASE_PTR (PMU) +/** Array initializer of PMU peripheral base adresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } + +/* ---------------------------------------------------------------------------- + -- PMU - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Accessor_Macros PMU - Register accessor macros + * @{ + */ + + +/* PMU - Register instance definitions */ +/* PMU */ +#define PMU_REG_1P0A PMU_REG_1P0A_REG(PMU_BASE_PTR) +#define PMU_REG_1P0A_SET PMU_REG_1P0A_SET_REG(PMU_BASE_PTR) +#define PMU_REG_1P0A_CLR PMU_REG_1P0A_CLR_REG(PMU_BASE_PTR) +#define PMU_REG_1P0A_TOG PMU_REG_1P0A_TOG_REG(PMU_BASE_PTR) +#define PMU_REG_1P0D PMU_REG_1P0D_REG(PMU_BASE_PTR) +#define PMU_REG_1P0D_SET PMU_REG_1P0D_SET_REG(PMU_BASE_PTR) +#define PMU_REG_1P0D_CLR PMU_REG_1P0D_CLR_REG(PMU_BASE_PTR) +#define PMU_REG_1P0D_TOG PMU_REG_1P0D_TOG_REG(PMU_BASE_PTR) +#define PMU_REG_HSIC_1P2 PMU_REG_HSIC_1P2_REG(PMU_BASE_PTR) +#define PMU_REG_HSIC_1P2_SET PMU_REG_HSIC_1P2_SET_REG(PMU_BASE_PTR) +#define PMU_REG_HSIC_1P2_CLR PMU_REG_HSIC_1P2_CLR_REG(PMU_BASE_PTR) +#define PMU_REG_HSIC_1P2_TOG PMU_REG_HSIC_1P2_TOG_REG(PMU_BASE_PTR) +#define PMU_REG_LPSR_1P0 PMU_REG_LPSR_1P0_REG(PMU_BASE_PTR) +#define PMU_REG_LPSR_1P0_SET PMU_REG_LPSR_1P0_SET_REG(PMU_BASE_PTR) +#define PMU_REG_LPSR_1P0_CLR PMU_REG_LPSR_1P0_CLR_REG(PMU_BASE_PTR) +#define PMU_REG_LPSR_1P0_TOG PMU_REG_LPSR_1P0_TOG_REG(PMU_BASE_PTR) +#define PMU_REG_3P0 PMU_REG_3P0_REG(PMU_BASE_PTR) +#define PMU_REG_3P0_SET PMU_REG_3P0_SET_REG(PMU_BASE_PTR) +#define PMU_REG_3P0_CLR PMU_REG_3P0_CLR_REG(PMU_BASE_PTR) +#define PMU_REG_3P0_TOG PMU_REG_3P0_TOG_REG(PMU_BASE_PTR) +#define PMU_REF PMU_REF_REG(PMU_BASE_PTR) +#define PMU_REF_SET PMU_REF_SET_REG(PMU_BASE_PTR) +#define PMU_REF_CLR PMU_REF_CLR_REG(PMU_BASE_PTR) +#define PMU_REF_TOG PMU_REF_TOG_REG(PMU_BASE_PTR) +#define PMU_LOWPWR_CTRL PMU_LOWPWR_CTRL_REG(PMU_BASE_PTR) +#define PMU_LOWPWR_CTRL_SET PMU_LOWPWR_CTRL_SET_REG(PMU_BASE_PTR) +#define PMU_LOWPWR_CTRL_CLR PMU_LOWPWR_CTRL_CLR_REG(PMU_BASE_PTR) +#define PMU_LOWPWR_CTRL_TOG PMU_LOWPWR_CTRL_TOG_REG(PMU_BASE_PTR) + +/*! + * @} + */ /* end of group PMU_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group PMU_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ + __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ + __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ + __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ + __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ + __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ +} PWM_Type, *PWM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PWM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros + * @{ + */ + + +/* PWM - Register accessors */ +#define PWM_PWMCR_REG(base) ((base)->PWMCR) +#define PWM_PWMSR_REG(base) ((base)->PWMSR) +#define PWM_PWMIR_REG(base) ((base)->PWMIR) +#define PWM_PWMSAR_REG(base) ((base)->PWMSAR) +#define PWM_PWMPR_REG(base) ((base)->PWMPR) +#define PWM_PWMCNR_REG(base) ((base)->PWMCNR) + +/*! + * @} + */ /* end of group PWM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/* PWMCR Bit Fields */ +#define PWM_PWMCR_EN_MASK 0x1u +#define PWM_PWMCR_EN_SHIFT 0 +#define PWM_PWMCR_REPEAT_MASK 0x6u +#define PWM_PWMCR_REPEAT_SHIFT 1 +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_REPEAT_SHIFT))&PWM_PWMCR_REPEAT_MASK) +#define PWM_PWMCR_SWR_MASK 0x8u +#define PWM_PWMCR_SWR_SHIFT 3 +#define PWM_PWMCR_PRESCALER_MASK 0xFFF0u +#define PWM_PWMCR_PRESCALER_SHIFT 4 +#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_PRESCALER_SHIFT))&PWM_PWMCR_PRESCALER_MASK) +#define PWM_PWMCR_CLKSRC_MASK 0x30000u +#define PWM_PWMCR_CLKSRC_SHIFT 16 +#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_CLKSRC_SHIFT))&PWM_PWMCR_CLKSRC_MASK) +#define PWM_PWMCR_POUTC_MASK 0xC0000u +#define PWM_PWMCR_POUTC_SHIFT 18 +#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_POUTC_SHIFT))&PWM_PWMCR_POUTC_MASK) +#define PWM_PWMCR_HCTR_MASK 0x100000u +#define PWM_PWMCR_HCTR_SHIFT 20 +#define PWM_PWMCR_BCTR_MASK 0x200000u +#define PWM_PWMCR_BCTR_SHIFT 21 +#define PWM_PWMCR_DBGEN_MASK 0x400000u +#define PWM_PWMCR_DBGEN_SHIFT 22 +#define PWM_PWMCR_WAITEN_MASK 0x800000u +#define PWM_PWMCR_WAITEN_SHIFT 23 +#define PWM_PWMCR_DOZEN_MASK 0x1000000u +#define PWM_PWMCR_DOZEN_SHIFT 24 +#define PWM_PWMCR_STOPEN_MASK 0x2000000u +#define PWM_PWMCR_STOPEN_SHIFT 25 +#define PWM_PWMCR_FWM_MASK 0xC000000u +#define PWM_PWMCR_FWM_SHIFT 26 +#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCR_FWM_SHIFT))&PWM_PWMCR_FWM_MASK) +/* PWMSR Bit Fields */ +#define PWM_PWMSR_FIFOAV_MASK 0x7u +#define PWM_PWMSR_FIFOAV_SHIFT 0 +#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMSR_FIFOAV_SHIFT))&PWM_PWMSR_FIFOAV_MASK) +#define PWM_PWMSR_FE_MASK 0x8u +#define PWM_PWMSR_FE_SHIFT 3 +#define PWM_PWMSR_ROV_MASK 0x10u +#define PWM_PWMSR_ROV_SHIFT 4 +#define PWM_PWMSR_CMP_MASK 0x20u +#define PWM_PWMSR_CMP_SHIFT 5 +#define PWM_PWMSR_FWE_MASK 0x40u +#define PWM_PWMSR_FWE_SHIFT 6 +/* PWMIR Bit Fields */ +#define PWM_PWMIR_FIE_MASK 0x1u +#define PWM_PWMIR_FIE_SHIFT 0 +#define PWM_PWMIR_RIE_MASK 0x2u +#define PWM_PWMIR_RIE_SHIFT 1 +#define PWM_PWMIR_CIE_MASK 0x4u +#define PWM_PWMIR_CIE_SHIFT 2 +/* PWMSAR Bit Fields */ +#define PWM_PWMSAR_SAMPLE_MASK 0xFFFFu +#define PWM_PWMSAR_SAMPLE_SHIFT 0 +#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMSAR_SAMPLE_SHIFT))&PWM_PWMSAR_SAMPLE_MASK) +/* PWMPR Bit Fields */ +#define PWM_PWMPR_PERIOD_MASK 0xFFFFu +#define PWM_PWMPR_PERIOD_SHIFT 0 +#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMPR_PERIOD_SHIFT))&PWM_PWMPR_PERIOD_MASK) +/* PWMCNR Bit Fields */ +#define PWM_PWMCNR_COUNT_MASK 0xFFFFu +#define PWM_PWMCNR_COUNT_SHIFT 0 +#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<PWM_PWMCNR_COUNT_SHIFT))&PWM_PWMCNR_COUNT_MASK) + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x30660000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +#define PWM1_BASE_PTR (PWM1) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x30670000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +#define PWM2_BASE_PTR (PWM2) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x30680000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +#define PWM3_BASE_PTR (PWM3) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x30690000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +#define PWM4_BASE_PTR (PWM4) +/** Array initializer of PWM peripheral base adresses */ +#define PWM_BASE_ADDRS { PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { PWM1, PWM2, PWM3, PWM4 } + +/* ---------------------------------------------------------------------------- + -- PWM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Accessor_Macros PWM - Register accessor macros + * @{ + */ + + +/* PWM - Register instance definitions */ +/* PWM1 */ +#define PWM1_PWMCR PWM_PWMCR_REG(PWM1_BASE_PTR) +#define PWM1_PWMSR PWM_PWMSR_REG(PWM1_BASE_PTR) +#define PWM1_PWMIR PWM_PWMIR_REG(PWM1_BASE_PTR) +#define PWM1_PWMSAR PWM_PWMSAR_REG(PWM1_BASE_PTR) +#define PWM1_PWMPR PWM_PWMPR_REG(PWM1_BASE_PTR) +#define PWM1_PWMCNR PWM_PWMCNR_REG(PWM1_BASE_PTR) +/* PWM2 */ +#define PWM2_PWMCR PWM_PWMCR_REG(PWM2_BASE_PTR) +#define PWM2_PWMSR PWM_PWMSR_REG(PWM2_BASE_PTR) +#define PWM2_PWMIR PWM_PWMIR_REG(PWM2_BASE_PTR) +#define PWM2_PWMSAR PWM_PWMSAR_REG(PWM2_BASE_PTR) +#define PWM2_PWMPR PWM_PWMPR_REG(PWM2_BASE_PTR) +#define PWM2_PWMCNR PWM_PWMCNR_REG(PWM2_BASE_PTR) +/* PWM3 */ +#define PWM3_PWMCR PWM_PWMCR_REG(PWM3_BASE_PTR) +#define PWM3_PWMSR PWM_PWMSR_REG(PWM3_BASE_PTR) +#define PWM3_PWMIR PWM_PWMIR_REG(PWM3_BASE_PTR) +#define PWM3_PWMSAR PWM_PWMSAR_REG(PWM3_BASE_PTR) +#define PWM3_PWMPR PWM_PWMPR_REG(PWM3_BASE_PTR) +#define PWM3_PWMCNR PWM_PWMCNR_REG(PWM3_BASE_PTR) +/* PWM4 */ +#define PWM4_PWMCR PWM_PWMCR_REG(PWM4_BASE_PTR) +#define PWM4_PWMSR PWM_PWMSR_REG(PWM4_BASE_PTR) +#define PWM4_PWMIR PWM_PWMIR_REG(PWM4_BASE_PTR) +#define PWM4_PWMSAR PWM_PWMSAR_REG(PWM4_BASE_PTR) +#define PWM4_PWMPR PWM_PWMPR_REG(PWM4_BASE_PTR) +#define PWM4_PWMCNR PWM_PWMCNR_REG(PWM4_BASE_PTR) + +/*! + * @} + */ /* end of group PWM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group PWM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t HW_PXP_PS_BACKGROUND_0; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_16[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_17[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_18[12]; + __IO uint32_t HW_PXP_PS_CLRKEYLOW_0; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_19[12]; + __IO uint32_t HW_PXP_PS_CLRKEYHIGH_0; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_21[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_22[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_23[12]; + __IO uint32_t HW_PXP_AS_CLRKEYLOW_0; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_24[12]; + __IO uint32_t HW_PXP_AS_CLRKEYHIGH_0; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ + uint8_t RESERVED_30[12]; + __IO uint32_t CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ + uint8_t RESERVED_32[12]; + __IO uint32_t CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ + uint8_t RESERVED_33[12]; + __IO uint32_t CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ + uint8_t RESERVED_34[12]; + __IO uint32_t CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ + uint8_t RESERVED_35[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ + uint8_t RESERVED_36[12]; + __IO uint32_t LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ + uint8_t RESERVED_37[12]; + __IO uint32_t LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ + uint8_t RESERVED_38[12]; + __IO uint32_t LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ + uint8_t RESERVED_39[12]; + __IO uint32_t CFA; /**< Color Filter Array Register., offset: 0x280 */ + uint8_t RESERVED_40[12]; + __IO uint32_t HW_PXP_ALPHA_A_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x290 */ + uint8_t RESERVED_41[12]; + __IO uint32_t HW_PXP_ALPHA_B_CTRL; /**< PXP Alpha Engine B Control Register., offset: 0x2A0 */ + uint8_t RESERVED_42[12]; + __IO uint32_t HW_PXP_ALPHA_B_CTRL_1; /**< , offset: 0x2B0 */ + uint8_t RESERVED_43[12]; + __IO uint32_t HW_PXP_PS_BACKGROUND_1; /**< PS Background Color 1, offset: 0x2C0 */ + uint8_t RESERVED_44[12]; + __IO uint32_t HW_PXP_PS_CLRKEYLOW_1; /**< PS Color Key Low 1, offset: 0x2D0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t HW_PXP_PS_CLRKEYHIGH_1; /**< PS Color Key High 1, offset: 0x2E0 */ + uint8_t RESERVED_46[12]; + __IO uint32_t HW_PXP_AS_CLRKEYLOW_1; /**< Overlay Color Key Low, offset: 0x2F0 */ + uint8_t RESERVED_47[12]; + __IO uint32_t HW_PXP_AS_CLRKEYHIGH_1; /**< Overlay Color Key High, offset: 0x300 */ + uint8_t RESERVED_48[12]; + __IO uint32_t HW_PXP_CTRL2; /**< Control Register 2, offset: 0x310 */ + uint8_t RESERVED_49[12]; + __IO uint32_t HW_PXP_POWER_REG0; /**< PXP Power Control Register., offset: 0x320 */ + uint8_t RESERVED_50[12]; + __IO uint32_t HW_PXP_POWER_REG1; /**< PXP Power Control Register 1., offset: 0x330 */ + uint8_t RESERVED_51[12]; + __IO uint32_t HW_PXP_DATA_PATH_CTRL0; /**< , offset: 0x340 */ + uint8_t RESERVED_52[12]; + __IO uint32_t HW_PXP_DATA_PATH_CTRL1; /**< , offset: 0x350 */ + uint8_t RESERVED_53[12]; + __IO uint32_t HW_PXP_INIT_MEM_CTRL; /**< Initialize memory buffer control Register, offset: 0x360 */ + uint8_t RESERVED_54[12]; + __IO uint32_t HW_PXP_INIT_MEM_DATA; /**< Write data Register, offset: 0x370 */ + uint8_t RESERVED_55[12]; + __IO uint32_t HW_PXP_INIT_MEM_DATA_HIGH; /**< Write data Register, offset: 0x380 */ + uint8_t RESERVED_56[12]; + __IO uint32_t HW_PXP_IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ + uint8_t RESERVED_57[12]; + __IO uint32_t HW_PXP_IRQ; /**< PXP Interrupt Register, offset: 0x3A0 */ + uint8_t RESERVED_58[92]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_59[76]; + __IO uint32_t HW_PXP_INPUT_FETCH_CTRL_CH0; /**< Pre-fetch engine Control Channel 0 Register, offset: 0x450 */ + uint8_t RESERVED_60[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_CTRL_CH1; /**< Pre-fetch engine Control Channel 1 Register, offset: 0x460 */ + uint8_t RESERVED_61[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_STATUS_CH0; /**< Pre-fetch engine status Channel 0 Register, offset: 0x470 */ + uint8_t RESERVED_62[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x480 */ + uint8_t RESERVED_63[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0; /**< , offset: 0x490 */ + uint8_t RESERVED_64[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0; /**< , offset: 0x4A0 */ + uint8_t RESERVED_65[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1; /**< , offset: 0x4B0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1; /**< , offset: 0x4C0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SIZE_CH0; /**< , offset: 0x4D0 */ + uint8_t RESERVED_68[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SIZE_CH1; /**< , offset: 0x4E0 */ + uint8_t RESERVED_69[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0; /**< , offset: 0x4F0 */ + uint8_t RESERVED_70[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1; /**< , offset: 0x500 */ + uint8_t RESERVED_71[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_PITCH; /**< , offset: 0x510 */ + uint8_t RESERVED_72[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0; /**< , offset: 0x520 */ + uint8_t RESERVED_73[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1; /**< , offset: 0x530 */ + uint8_t RESERVED_74[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0; /**< , offset: 0x540 */ + uint8_t RESERVED_75[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1; /**< , offset: 0x550 */ + uint8_t RESERVED_76[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0; /**< , offset: 0x560 */ + uint8_t RESERVED_77[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1; /**< , offset: 0x570 */ + uint8_t RESERVED_78[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ADDR_0_CH0; /**< , offset: 0x580 */ + uint8_t RESERVED_79[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ADDR_1_CH0; /**< , offset: 0x590 */ + uint8_t RESERVED_80[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ADDR_0_CH1; /**< , offset: 0x5A0 */ + uint8_t RESERVED_81[12]; + __IO uint32_t HW_PXP_INPUT_FETCH_ADDR_1_CH1; /**< , offset: 0x5B0 */ + uint8_t RESERVED_82[12]; + __IO uint32_t HW_PXP_INPUT_STORE_CTRL_CH0; /**< Store engine Control Channel 0 Register, offset: 0x5C0 */ + uint8_t RESERVED_83[12]; + __IO uint32_t HW_PXP_INPUT_STORE_CTRL_CH1; /**< Store engine Control Channel 1 Register, offset: 0x5D0 */ + uint8_t RESERVED_84[12]; + __IO uint32_t HW_PXP_INPUT_STORE_STATUS_CH0; /**< Store engine status Channel 0 Register, offset: 0x5E0 */ + uint8_t RESERVED_85[12]; + __IO uint32_t HW_PXP_INPUT_STORE_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x5F0 */ + uint8_t RESERVED_86[12]; + __IO uint32_t HW_PXP_INPUT_STORE_SIZE_CH0; /**< , offset: 0x600 */ + uint8_t RESERVED_87[12]; + __IO uint32_t HW_PXP_INPUT_STORE_SIZE_CH1; /**< , offset: 0x610 */ + uint8_t RESERVED_88[12]; + __IO uint32_t HW_PXP_INPUT_STORE_PITCH; /**< , offset: 0x620 */ + uint8_t RESERVED_89[12]; + __IO uint32_t HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0; /**< , offset: 0x630 */ + uint8_t RESERVED_90[12]; + __IO uint32_t HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1; /**< , offset: 0x640 */ + uint8_t RESERVED_91[76]; + __IO uint32_t HW_PXP_INPUT_STORE_ADDR_0_CH0; /**< , offset: 0x690 */ + uint8_t RESERVED_92[12]; + __IO uint32_t HW_PXP_INPUT_STORE_ADDR_1_CH0; /**< , offset: 0x6A0 */ + uint8_t RESERVED_93[12]; + __IO uint32_t HW_PXP_INPUT_STORE_FILL_DATA_CH0; /**< , offset: 0x6B0 */ + uint8_t RESERVED_94[12]; + __IO uint32_t HW_PXP_INPUT_STORE_ADDR_0_CH1; /**< , offset: 0x6C0 */ + uint8_t RESERVED_95[12]; + __IO uint32_t HW_PXP_INPUT_STORE_ADDR_1_CH1; /**< , offset: 0x6D0 */ + uint8_t RESERVED_96[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK0_H_CH0; /**< , offset: 0x6E0 */ + uint8_t RESERVED_97[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK0_L_CH0; /**< , offset: 0x6F0 */ + uint8_t RESERVED_98[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK1_H_CH0; /**< , offset: 0x700 */ + uint8_t RESERVED_99[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK1_L_CH0; /**< , offset: 0x710 */ + uint8_t RESERVED_100[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK2_H_CH0; /**< , offset: 0x720 */ + uint8_t RESERVED_101[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK2_L_CH0; /**< , offset: 0x730 */ + uint8_t RESERVED_102[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK3_H_CH0; /**< , offset: 0x740 */ + uint8_t RESERVED_103[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK3_L_CH0; /**< , offset: 0x750 */ + uint8_t RESERVED_104[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK4_H_CH0; /**< , offset: 0x760 */ + uint8_t RESERVED_105[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK4_L_CH0; /**< , offset: 0x770 */ + uint8_t RESERVED_106[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK5_H_CH0; /**< , offset: 0x780 */ + uint8_t RESERVED_107[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK5_L_CH0; /**< , offset: 0x790 */ + uint8_t RESERVED_108[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK6_H_CH0; /**< , offset: 0x7A0 */ + uint8_t RESERVED_109[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK6_L_CH0; /**< , offset: 0x7B0 */ + uint8_t RESERVED_110[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK7_H_CH0; /**< , offset: 0x7C0 */ + uint8_t RESERVED_111[28]; + __IO uint32_t HW_PXP_INPUT_STORE_D_MASK7_L_CH0; /**< , offset: 0x7E0 */ + uint8_t RESERVED_112[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_SHIFT_L_CH0; /**< , offset: 0x7F0 */ + uint8_t RESERVED_113[12]; + __IO uint32_t HW_PXP_INPUT_STORE_D_SHIFT_H_CH0; /**< , offset: 0x800 */ + uint8_t RESERVED_114[12]; + __IO uint32_t HW_PXP_INPUT_STORE_F_SHIFT_L_CH0; /**< , offset: 0x810 */ + uint8_t RESERVED_115[12]; + __IO uint32_t HW_PXP_INPUT_STORE_F_SHIFT_H_CH0; /**< , offset: 0x820 */ + uint8_t RESERVED_116[12]; + __IO uint32_t HW_PXP_INPUT_STORE_F_MASK_L_CH0; /**< , offset: 0x830 */ + uint8_t RESERVED_117[12]; + __IO uint32_t HW_PXP_INPUT_STORE_F_MASK_H_CH0; /**< , offset: 0x840 */ + uint8_t RESERVED_118[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_CTRL_CH0; /**< Pre-fetch engine Control Channel 0 Register, offset: 0x850 */ + uint8_t RESERVED_119[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_CTRL_CH1; /**< Pre-fetch engine Control Channel 1 Register, offset: 0x860 */ + uint8_t RESERVED_120[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_STATUS_CH0; /**< Pre-fetch engine status Channel 0 Register, offset: 0x870 */ + uint8_t RESERVED_121[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x880 */ + uint8_t RESERVED_122[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0; /**< , offset: 0x890 */ + uint8_t RESERVED_123[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0; /**< , offset: 0x8A0 */ + uint8_t RESERVED_124[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1; /**< , offset: 0x8B0 */ + uint8_t RESERVED_125[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1; /**< , offset: 0x8C0 */ + uint8_t RESERVED_126[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SIZE_CH0; /**< , offset: 0x8D0 */ + uint8_t RESERVED_127[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SIZE_CH1; /**< , offset: 0x8E0 */ + uint8_t RESERVED_128[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0; /**< , offset: 0x8F0 */ + uint8_t RESERVED_129[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1; /**< , offset: 0x900 */ + uint8_t RESERVED_130[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_PITCH; /**< , offset: 0x910 */ + uint8_t RESERVED_131[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0; /**< , offset: 0x920 */ + uint8_t RESERVED_132[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1; /**< , offset: 0x930 */ + uint8_t RESERVED_133[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0; /**< , offset: 0x940 */ + uint8_t RESERVED_134[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1; /**< , offset: 0x950 */ + uint8_t RESERVED_135[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0; /**< , offset: 0x960 */ + uint8_t RESERVED_136[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1; /**< , offset: 0x970 */ + uint8_t RESERVED_137[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ADDR_0_CH0; /**< , offset: 0x980 */ + uint8_t RESERVED_138[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ADDR_1_CH0; /**< , offset: 0x990 */ + uint8_t RESERVED_139[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ADDR_0_CH1; /**< , offset: 0x9A0 */ + uint8_t RESERVED_140[12]; + __IO uint32_t HW_PXP_DITHER_FETCH_ADDR_1_CH1; /**< , offset: 0x9B0 */ + uint8_t RESERVED_141[12]; + __IO uint32_t HW_PXP_DITHER_STORE_CTRL_CH0; /**< Store engine Control Channel 0 Register, offset: 0x9C0 */ + uint8_t RESERVED_142[12]; + __IO uint32_t HW_PXP_DITHER_STORE_CTRL_CH1; /**< Store engine Control Channel 1 Register, offset: 0x9D0 */ + uint8_t RESERVED_143[12]; + __IO uint32_t HW_PXP_DITHER_STORE_STATUS_CH0; /**< Store engine status Channel 0 Register, offset: 0x9E0 */ + uint8_t RESERVED_144[12]; + __IO uint32_t HW_PXP_DITHER_STORE_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x9F0 */ + uint8_t RESERVED_145[12]; + __IO uint32_t HW_PXP_DITHER_STORE_SIZE_CH0; /**< , offset: 0xA00 */ + uint8_t RESERVED_146[12]; + __IO uint32_t HW_PXP_DITHER_STORE_SIZE_CH1; /**< , offset: 0xA10 */ + uint8_t RESERVED_147[12]; + __IO uint32_t HW_PXP_DITHER_STORE_PITCH; /**< , offset: 0xA20 */ + uint8_t RESERVED_148[12]; + __IO uint32_t HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0; /**< , offset: 0xA30 */ + uint8_t RESERVED_149[12]; + __IO uint32_t HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1; /**< , offset: 0xA40 */ + uint8_t RESERVED_150[76]; + __IO uint32_t HW_PXP_DITHER_STORE_ADDR_0_CH0; /**< , offset: 0xA90 */ + uint8_t RESERVED_151[12]; + __IO uint32_t HW_PXP_DITHER_STORE_ADDR_1_CH0; /**< , offset: 0xAA0 */ + uint8_t RESERVED_152[12]; + __IO uint32_t HW_PXP_DITHER_STORE_FILL_DATA_CH0; /**< , offset: 0xAB0 */ + uint8_t RESERVED_153[12]; + __IO uint32_t HW_PXP_DITHER_STORE_ADDR_0_CH1; /**< , offset: 0xAC0 */ + uint8_t RESERVED_154[12]; + __IO uint32_t HW_PXP_DITHER_STORE_ADDR_1_CH1; /**< , offset: 0xAD0 */ + uint8_t RESERVED_155[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK0_H_CH0; /**< , offset: 0xAE0 */ + uint8_t RESERVED_156[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK0_L_CH0; /**< , offset: 0xAF0 */ + uint8_t RESERVED_157[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK1_H_CH0; /**< , offset: 0xB00 */ + uint8_t RESERVED_158[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK1_L_CH0; /**< , offset: 0xB10 */ + uint8_t RESERVED_159[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK2_H_CH0; /**< , offset: 0xB20 */ + uint8_t RESERVED_160[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK2_L_CH0; /**< , offset: 0xB30 */ + uint8_t RESERVED_161[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK3_H_CH0; /**< , offset: 0xB40 */ + uint8_t RESERVED_162[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK3_L_CH0; /**< , offset: 0xB50 */ + uint8_t RESERVED_163[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK4_H_CH0; /**< , offset: 0xB60 */ + uint8_t RESERVED_164[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK4_L_CH0; /**< , offset: 0xB70 */ + uint8_t RESERVED_165[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK5_H_CH0; /**< , offset: 0xB80 */ + uint8_t RESERVED_166[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK5_L_CH0; /**< , offset: 0xB90 */ + uint8_t RESERVED_167[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK6_H_CH0; /**< , offset: 0xBA0 */ + uint8_t RESERVED_168[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK6_L_CH0; /**< , offset: 0xBB0 */ + uint8_t RESERVED_169[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK7_H_CH0; /**< , offset: 0xBC0 */ + uint8_t RESERVED_170[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_MASK7_L_CH0; /**< , offset: 0xBD0 */ + uint8_t RESERVED_171[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_SHIFT_L_CH0; /**< , offset: 0xBE0 */ + uint8_t RESERVED_172[12]; + __IO uint32_t HW_PXP_DITHER_STORE_D_SHIFT_H_CH0; /**< , offset: 0xBF0 */ + uint8_t RESERVED_173[12]; + __IO uint32_t HW_PXP_DITHER_STORE_F_SHIFT_L_CH0; /**< , offset: 0xC00 */ + uint8_t RESERVED_174[12]; + __IO uint32_t HW_PXP_DITHER_STORE_F_SHIFT_H_CH0; /**< , offset: 0xC10 */ + uint8_t RESERVED_175[12]; + __IO uint32_t HW_PXP_DITHER_STORE_F_MASK_L_CH0; /**< , offset: 0xC20 */ + uint8_t RESERVED_176[12]; + __IO uint32_t HW_PXP_DITHER_STORE_F_MASK_H_CH0; /**< , offset: 0xC30 */ + uint8_t RESERVED_177[2620]; + __IO uint32_t HW_PXP_DITHER_CTRL; /**< Dither Control Register 0, offset: 0x1670 */ + uint8_t RESERVED_178[12]; + __IO uint32_t HW_PXP_DITHER_FINAL_LUT_DATA0; /**< Final stage lookup value Register, offset: 0x1680 */ + uint8_t RESERVED_179[12]; + __IO uint32_t HW_PXP_DITHER_FINAL_LUT_DATA1; /**< Final stage lookup value Register, offset: 0x1690 */ + uint8_t RESERVED_180[12]; + __IO uint32_t HW_PXP_DITHER_FINAL_LUT_DATA2; /**< Final stage lookup value Register, offset: 0x16A0 */ + uint8_t RESERVED_181[12]; + __IO uint32_t HW_PXP_DITHER_FINAL_LUT_DATA3; /**< Final stage lookup value Register, offset: 0x16B0 */ + uint8_t RESERVED_182[4940]; + __IO uint32_t HW_PXP_HIST_A_CTRL; /**< Histogram Control Register., offset: 0x2A00 */ + uint8_t RESERVED_183[12]; + __IO uint32_t HW_PXP_HIST_A_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A10 */ + uint8_t RESERVED_184[12]; + __IO uint32_t HW_PXP_HIST_A_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2A20 */ + uint8_t RESERVED_185[12]; + __IO uint32_t HW_PXP_HIST_A_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2A30 */ + uint8_t RESERVED_186[12]; + __IO uint32_t HW_PXP_HIST_A_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2A40 */ + uint8_t RESERVED_187[12]; + __IO uint32_t HW_PXP_HIST_A_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2A50 */ + uint8_t RESERVED_188[12]; + __IO uint32_t HW_PXP_HIST_A_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A60 */ + uint8_t RESERVED_189[12]; + __IO uint32_t HW_PXP_HIST_A_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A70 */ + uint8_t RESERVED_190[12]; + __IO uint32_t HW_PXP_HIST_B_CTRL; /**< Histogram Control Register., offset: 0x2A80 */ + uint8_t RESERVED_191[12]; + __IO uint32_t HW_PXP_HIST_B_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A90 */ + uint8_t RESERVED_192[12]; + __IO uint32_t HW_PXP_HIST_B_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2AA0 */ + uint8_t RESERVED_193[12]; + __IO uint32_t HW_PXP_HIST_B_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2AB0 */ + uint8_t RESERVED_194[12]; + __IO uint32_t HW_PXP_HIST_B_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2AC0 */ + uint8_t RESERVED_195[12]; + __IO uint32_t HW_PXP_HIST_B_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2AD0 */ + uint8_t RESERVED_196[12]; + __IO uint32_t HW_PXP_HIST_B_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AE0 */ + uint8_t RESERVED_197[12]; + __IO uint32_t HW_PXP_HIST_B_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */ + uint8_t RESERVED_198[12]; + __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2B00 */ + uint8_t RESERVED_199[12]; + __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B10 */ + uint8_t RESERVED_200[12]; + __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */ + uint8_t RESERVED_201[12]; + __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */ + uint8_t RESERVED_202[12]; + __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */ + uint8_t RESERVED_203[12]; + __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */ + uint8_t RESERVED_204[12]; + __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */ + uint8_t RESERVED_205[12]; + __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */ + uint8_t RESERVED_206[12]; + __IO uint32_t HW_PXP_HIST32_PARAM0; /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */ + uint8_t RESERVED_207[12]; + __IO uint32_t HW_PXP_HIST32_PARAM1; /**< 32-level Histogram Parameter 1 Register., offset: 0x2B90 */ + uint8_t RESERVED_208[12]; + __IO uint32_t HW_PXP_HIST32_PARAM2; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BA0 */ + uint8_t RESERVED_209[12]; + __IO uint32_t HW_PXP_HIST32_PARAM3; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BB0 */ + uint8_t RESERVED_210[12]; + __IO uint32_t HW_PXP_HIST32_PARAM4; /**< 32-level Histogram Parameter 0 Register., offset: 0x2BC0 */ + uint8_t RESERVED_211[12]; + __IO uint32_t HW_PXP_HIST32_PARAM5; /**< 32-level Histogram Parameter 1 Register., offset: 0x2BD0 */ + uint8_t RESERVED_212[12]; + __IO uint32_t HW_PXP_HIST32_PARAM6; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BE0 */ + uint8_t RESERVED_213[12]; + __IO uint32_t HW_PXP_HIST32_PARAM7; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BF0 */ + uint8_t RESERVED_214[12]; + __IO uint32_t HW_PXP_COMP_CTRL; /**< , offset: 0x2C00 */ + uint8_t RESERVED_215[12]; + __IO uint32_t HW_PXP_COMP_FORMAT0; /**< , offset: 0x2C10 */ + uint8_t RESERVED_216[12]; + __IO uint32_t HW_PXP_COMP_FORMAT1; /**< , offset: 0x2C20 */ + uint8_t RESERVED_217[12]; + __IO uint32_t HW_PXP_COMP_FORMAT2; /**< , offset: 0x2C30 */ + uint8_t RESERVED_218[12]; + __IO uint32_t HW_PXP_COMP_MASK0; /**< , offset: 0x2C40 */ + uint8_t RESERVED_219[12]; + __IO uint32_t HW_PXP_COMP_MASK1; /**< , offset: 0x2C50 */ + uint8_t RESERVED_220[12]; + __IO uint32_t HW_PXP_COMP_BUFFER_SIZE; /**< , offset: 0x2C60 */ + uint8_t RESERVED_221[12]; + __IO uint32_t HW_PXP_COMP_SOURCE; /**< , offset: 0x2C70 */ + uint8_t RESERVED_222[12]; + __IO uint32_t HW_PXP_COMP_TARGET; /**< , offset: 0x2C80 */ + uint8_t RESERVED_223[12]; + __IO uint32_t HW_PXP_COMP_BUFFER_A; /**< , offset: 0x2C90 */ + uint8_t RESERVED_224[12]; + __IO uint32_t HW_PXP_COMP_BUFFER_B; /**< , offset: 0x2CA0 */ + uint8_t RESERVED_225[12]; + __IO uint32_t HW_PXP_COMP_BUFFER_C; /**< , offset: 0x2CB0 */ + uint8_t RESERVED_226[12]; + __IO uint32_t HW_PXP_COMP_BUFFER_D; /**< , offset: 0x2CC0 */ + uint8_t RESERVED_227[12]; + __IO uint32_t HW_PXP_COMP_DEBUG; /**< , offset: 0x2CD0 */ + uint8_t RESERVED_228[12]; + __IO uint32_t HW_PXP_BUS_MUX; /**< , offset: 0x2CE0 */ + uint8_t RESERVED_229[12]; + __IO uint32_t HW_PXP_HANDSHAKE_READY_MUX0; /**< , offset: 0x2CF0 */ + uint8_t RESERVED_230[12]; + __IO uint32_t HW_PXP_HANDSHAKE_READY_MUX1; /**< , offset: 0x2D00 */ + uint8_t RESERVED_231[12]; + __IO uint32_t HW_PXP_HANDSHAKE_DONE_MUX0; /**< , offset: 0x2D10 */ + uint8_t RESERVED_232[12]; + __IO uint32_t HW_PXP_HANDSHAKE_DONE_MUX1; /**< , offset: 0x2D20 */ + uint8_t RESERVED_233[12]; + __IO uint32_t HW_PXP_HANDSHAKE_CPU_FETCH; /**< , offset: 0x2D30 */ + uint8_t RESERVED_234[12]; + __IO uint32_t HW_PXP_HANDSHAKE_CPU_STORE; /**< , offset: 0x2D40 */ +} PXP_Type, *PXP_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- PXP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros + * @{ + */ + + +/* PXP - Register accessors */ +#define PXP_CTRL_REG(base) ((base)->CTRL) +#define PXP_STAT_REG(base) ((base)->STAT) +#define PXP_OUT_CTRL_REG(base) ((base)->OUT_CTRL) +#define PXP_OUT_BUF_REG(base) ((base)->OUT_BUF) +#define PXP_OUT_BUF2_REG(base) ((base)->OUT_BUF2) +#define PXP_OUT_PITCH_REG(base) ((base)->OUT_PITCH) +#define PXP_OUT_LRC_REG(base) ((base)->OUT_LRC) +#define PXP_OUT_PS_ULC_REG(base) ((base)->OUT_PS_ULC) +#define PXP_OUT_PS_LRC_REG(base) ((base)->OUT_PS_LRC) +#define PXP_OUT_AS_ULC_REG(base) ((base)->OUT_AS_ULC) +#define PXP_OUT_AS_LRC_REG(base) ((base)->OUT_AS_LRC) +#define PXP_PS_CTRL_REG(base) ((base)->PS_CTRL) +#define PXP_PS_BUF_REG(base) ((base)->PS_BUF) +#define PXP_PS_UBUF_REG(base) ((base)->PS_UBUF) +#define PXP_PS_VBUF_REG(base) ((base)->PS_VBUF) +#define PXP_PS_PITCH_REG(base) ((base)->PS_PITCH) +#define PXP_HW_PXP_PS_BACKGROUND_0_REG(base) ((base)->HW_PXP_PS_BACKGROUND_0) +#define PXP_PS_SCALE_REG(base) ((base)->PS_SCALE) +#define PXP_PS_OFFSET_REG(base) ((base)->PS_OFFSET) +#define PXP_HW_PXP_PS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_0) +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_0) +#define PXP_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define PXP_AS_BUF_REG(base) ((base)->AS_BUF) +#define PXP_AS_PITCH_REG(base) ((base)->AS_PITCH) +#define PXP_HW_PXP_AS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_0) +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_0) +#define PXP_CSC1_COEF0_REG(base) ((base)->CSC1_COEF0) +#define PXP_CSC1_COEF1_REG(base) ((base)->CSC1_COEF1) +#define PXP_CSC1_COEF2_REG(base) ((base)->CSC1_COEF2) +#define PXP_CSC2_CTRL_REG(base) ((base)->CSC2_CTRL) +#define PXP_CSC2_COEF0_REG(base) ((base)->CSC2_COEF0) +#define PXP_CSC2_COEF1_REG(base) ((base)->CSC2_COEF1) +#define PXP_CSC2_COEF2_REG(base) ((base)->CSC2_COEF2) +#define PXP_CSC2_COEF3_REG(base) ((base)->CSC2_COEF3) +#define PXP_CSC2_COEF4_REG(base) ((base)->CSC2_COEF4) +#define PXP_CSC2_COEF5_REG(base) ((base)->CSC2_COEF5) +#define PXP_LUT_CTRL_REG(base) ((base)->LUT_CTRL) +#define PXP_LUT_ADDR_REG(base) ((base)->LUT_ADDR) +#define PXP_LUT_DATA_REG(base) ((base)->LUT_DATA) +#define PXP_LUT_EXTMEM_REG(base) ((base)->LUT_EXTMEM) +#define PXP_CFA_REG(base) ((base)->CFA) +#define PXP_HW_PXP_ALPHA_A_CTRL_REG(base) ((base)->HW_PXP_ALPHA_A_CTRL) +#define PXP_HW_PXP_ALPHA_B_CTRL_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL) +#define PXP_HW_PXP_ALPHA_B_CTRL_1_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL_1) +#define PXP_HW_PXP_PS_BACKGROUND_1_REG(base) ((base)->HW_PXP_PS_BACKGROUND_1) +#define PXP_HW_PXP_PS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_1) +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_1) +#define PXP_HW_PXP_AS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_1) +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_1) +#define PXP_HW_PXP_CTRL2_REG(base) ((base)->HW_PXP_CTRL2) +#define PXP_HW_PXP_POWER_REG0_REG(base) ((base)->HW_PXP_POWER_REG0) +#define PXP_HW_PXP_POWER_REG1_REG(base) ((base)->HW_PXP_POWER_REG1) +#define PXP_HW_PXP_DATA_PATH_CTRL0_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL0) +#define PXP_HW_PXP_DATA_PATH_CTRL1_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL1) +#define PXP_HW_PXP_INIT_MEM_CTRL_REG(base) ((base)->HW_PXP_INIT_MEM_CTRL) +#define PXP_HW_PXP_INIT_MEM_DATA_REG(base) ((base)->HW_PXP_INIT_MEM_DATA) +#define PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(base) ((base)->HW_PXP_INIT_MEM_DATA_HIGH) +#define PXP_HW_PXP_IRQ_MASK_REG(base) ((base)->HW_PXP_IRQ_MASK) +#define PXP_HW_PXP_IRQ_REG(base) ((base)->HW_PXP_IRQ) +#define PXP_NEXT_REG(base) ((base)->NEXT) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH0) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH1) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH0) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH1) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1) +#define PXP_HW_PXP_INPUT_FETCH_PITCH_REG(base) ((base)->HW_PXP_INPUT_FETCH_PITCH) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH1) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH0) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH1) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH0) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH1) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH0) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH1) +#define PXP_HW_PXP_INPUT_STORE_PITCH_REG(base) ((base)->HW_PXP_INPUT_STORE_PITCH) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH0) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH0) +#define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_FILL_DATA_CH0) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH1) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH1) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_H_CH0) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH0) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH1) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH0) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH1) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1) +#define PXP_HW_PXP_DITHER_FETCH_PITCH_REG(base) ((base)->HW_PXP_DITHER_FETCH_PITCH) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH1) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH0) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH1) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH0) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH1) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH0) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH1) +#define PXP_HW_PXP_DITHER_STORE_PITCH_REG(base) ((base)->HW_PXP_DITHER_STORE_PITCH) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH0) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH0) +#define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_FILL_DATA_CH0) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH1) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH1) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_H_CH0) +#define PXP_HW_PXP_DITHER_CTRL_REG(base) ((base)->HW_PXP_DITHER_CTRL) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA0) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA1) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA2) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA3) +#define PXP_HW_PXP_HIST_A_CTRL_REG(base) ((base)->HW_PXP_HIST_A_CTRL) +#define PXP_HW_PXP_HIST_A_MASK_REG(base) ((base)->HW_PXP_HIST_A_MASK) +#define PXP_HW_PXP_HIST_A_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_A_BUF_SIZE) +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_A_TOTAL_PIXEL) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_X) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_Y) +#define PXP_HW_PXP_HIST_A_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT0) +#define PXP_HW_PXP_HIST_A_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT1) +#define PXP_HW_PXP_HIST_B_CTRL_REG(base) ((base)->HW_PXP_HIST_B_CTRL) +#define PXP_HW_PXP_HIST_B_MASK_REG(base) ((base)->HW_PXP_HIST_B_MASK) +#define PXP_HW_PXP_HIST_B_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_B_BUF_SIZE) +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_B_TOTAL_PIXEL) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_X) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_Y) +#define PXP_HW_PXP_HIST_B_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT0) +#define PXP_HW_PXP_HIST_B_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT1) +#define PXP_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) +#define PXP_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) +#define PXP_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) +#define PXP_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) +#define PXP_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) +#define PXP_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) +#define PXP_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) +#define PXP_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) +#define PXP_HW_PXP_HIST32_PARAM0_REG(base) ((base)->HW_PXP_HIST32_PARAM0) +#define PXP_HW_PXP_HIST32_PARAM1_REG(base) ((base)->HW_PXP_HIST32_PARAM1) +#define PXP_HW_PXP_HIST32_PARAM2_REG(base) ((base)->HW_PXP_HIST32_PARAM2) +#define PXP_HW_PXP_HIST32_PARAM3_REG(base) ((base)->HW_PXP_HIST32_PARAM3) +#define PXP_HW_PXP_HIST32_PARAM4_REG(base) ((base)->HW_PXP_HIST32_PARAM4) +#define PXP_HW_PXP_HIST32_PARAM5_REG(base) ((base)->HW_PXP_HIST32_PARAM5) +#define PXP_HW_PXP_HIST32_PARAM6_REG(base) ((base)->HW_PXP_HIST32_PARAM6) +#define PXP_HW_PXP_HIST32_PARAM7_REG(base) ((base)->HW_PXP_HIST32_PARAM7) +#define PXP_HW_PXP_COMP_CTRL_REG(base) ((base)->HW_PXP_COMP_CTRL) +#define PXP_HW_PXP_COMP_FORMAT0_REG(base) ((base)->HW_PXP_COMP_FORMAT0) +#define PXP_HW_PXP_COMP_FORMAT1_REG(base) ((base)->HW_PXP_COMP_FORMAT1) +#define PXP_HW_PXP_COMP_FORMAT2_REG(base) ((base)->HW_PXP_COMP_FORMAT2) +#define PXP_HW_PXP_COMP_MASK0_REG(base) ((base)->HW_PXP_COMP_MASK0) +#define PXP_HW_PXP_COMP_MASK1_REG(base) ((base)->HW_PXP_COMP_MASK1) +#define PXP_HW_PXP_COMP_BUFFER_SIZE_REG(base) ((base)->HW_PXP_COMP_BUFFER_SIZE) +#define PXP_HW_PXP_COMP_SOURCE_REG(base) ((base)->HW_PXP_COMP_SOURCE) +#define PXP_HW_PXP_COMP_TARGET_REG(base) ((base)->HW_PXP_COMP_TARGET) +#define PXP_HW_PXP_COMP_BUFFER_A_REG(base) ((base)->HW_PXP_COMP_BUFFER_A) +#define PXP_HW_PXP_COMP_BUFFER_B_REG(base) ((base)->HW_PXP_COMP_BUFFER_B) +#define PXP_HW_PXP_COMP_BUFFER_C_REG(base) ((base)->HW_PXP_COMP_BUFFER_C) +#define PXP_HW_PXP_COMP_BUFFER_D_REG(base) ((base)->HW_PXP_COMP_BUFFER_D) +#define PXP_HW_PXP_COMP_DEBUG_REG(base) ((base)->HW_PXP_COMP_DEBUG) +#define PXP_HW_PXP_BUS_MUX_REG(base) ((base)->HW_PXP_BUS_MUX) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX0) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX1) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX0) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX1) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_FETCH) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_STORE) + +/*! + * @} + */ /* end of group PXP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define PXP_CTRL_ENABLE_MASK 0x1u +#define PXP_CTRL_ENABLE_SHIFT 0 +#define PXP_CTRL_IRQ_ENABLE_MASK 0x2u +#define PXP_CTRL_IRQ_ENABLE_SHIFT 1 +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK 0x10u +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT 4 +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK 0x20u +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT 5 +#define PXP_CTRL_RSVD0_MASK 0xC0u +#define PXP_CTRL_RSVD0_SHIFT 6 +#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_RSVD0_SHIFT))&PXP_CTRL_RSVD0_MASK) +#define PXP_CTRL_ROTATE0_MASK 0x300u +#define PXP_CTRL_ROTATE0_SHIFT 8 +#define PXP_CTRL_ROTATE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_ROTATE0_SHIFT))&PXP_CTRL_ROTATE0_MASK) +#define PXP_CTRL_HFLIP0_MASK 0x400u +#define PXP_CTRL_HFLIP0_SHIFT 10 +#define PXP_CTRL_VFLIP0_MASK 0x800u +#define PXP_CTRL_VFLIP0_SHIFT 11 +#define PXP_CTRL_ROTATE1_MASK 0x3000u +#define PXP_CTRL_ROTATE1_SHIFT 12 +#define PXP_CTRL_ROTATE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CTRL_ROTATE1_SHIFT))&PXP_CTRL_ROTATE1_MASK) +#define PXP_CTRL_HFLIP1_MASK 0x4000u +#define PXP_CTRL_HFLIP1_SHIFT 14 +#define PXP_CTRL_VFLIP1_MASK 0x8000u +#define PXP_CTRL_VFLIP1_SHIFT 15 +#define PXP_CTRL_ENABLE_PS_AS_OUT_MASK 0x10000u +#define PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT 16 +#define PXP_CTRL_ENABLE_DITHER_MASK 0x20000u +#define PXP_CTRL_ENABLE_DITHER_SHIFT 17 +#define PXP_CTRL_ENABLE_WFE_A_MASK 0x40000u +#define PXP_CTRL_ENABLE_WFE_A_SHIFT 18 +#define PXP_CTRL_ENABLE_WFE_B_MASK 0x80000u +#define PXP_CTRL_ENABLE_WFE_B_SHIFT 19 +#define PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK 0x100000u +#define PXP_CTRL_ENABLE_INPUT_FETCH_STORE_SHIFT 20 +#define PXP_CTRL_ENABLE_ALPHA_B_MASK 0x200000u +#define PXP_CTRL_ENABLE_ALPHA_B_SHIFT 21 +#define PXP_CTRL_RSVD1_MASK 0x400000u +#define PXP_CTRL_RSVD1_SHIFT 22 +#define PXP_CTRL_BLOCK_SIZE_MASK 0x800000u +#define PXP_CTRL_BLOCK_SIZE_SHIFT 23 +#define PXP_CTRL_ENABLE_CSC2_MASK 0x1000000u +#define PXP_CTRL_ENABLE_CSC2_SHIFT 24 +#define PXP_CTRL_ENABLE_LUT_MASK 0x2000000u +#define PXP_CTRL_ENABLE_LUT_SHIFT 25 +#define PXP_CTRL_ENABLE_ROTATE0_MASK 0x4000000u +#define PXP_CTRL_ENABLE_ROTATE0_SHIFT 26 +#define PXP_CTRL_ENABLE_ROTATE1_MASK 0x8000000u +#define PXP_CTRL_ENABLE_ROTATE1_SHIFT 27 +#define PXP_CTRL_EN_REPEAT_MASK 0x10000000u +#define PXP_CTRL_EN_REPEAT_SHIFT 28 +#define PXP_CTRL_RSVD4_MASK 0x20000000u +#define PXP_CTRL_RSVD4_SHIFT 29 +#define PXP_CTRL_CLKGATE_MASK 0x40000000u +#define PXP_CTRL_CLKGATE_SHIFT 30 +#define PXP_CTRL_SFTRST_MASK 0x80000000u +#define PXP_CTRL_SFTRST_SHIFT 31 +/* STAT Bit Fields */ +#define PXP_STAT_IRQ0_MASK 0x1u +#define PXP_STAT_IRQ0_SHIFT 0 +#define PXP_STAT_AXI_WRITE_ERROR_0_MASK 0x2u +#define PXP_STAT_AXI_WRITE_ERROR_0_SHIFT 1 +#define PXP_STAT_AXI_READ_ERROR_0_MASK 0x4u +#define PXP_STAT_AXI_READ_ERROR_0_SHIFT 2 +#define PXP_STAT_NEXT_IRQ_MASK 0x8u +#define PXP_STAT_NEXT_IRQ_SHIFT 3 +#define PXP_STAT_AXI_ERROR_ID_0_MASK 0xF0u +#define PXP_STAT_AXI_ERROR_ID_0_SHIFT 4 +#define PXP_STAT_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_AXI_ERROR_ID_0_SHIFT))&PXP_STAT_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK 0x100u +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT 8 +#define PXP_STAT_AXI_WRITE_ERROR_1_MASK 0x200u +#define PXP_STAT_AXI_WRITE_ERROR_1_SHIFT 9 +#define PXP_STAT_AXI_READ_ERROR_1_MASK 0x400u +#define PXP_STAT_AXI_READ_ERROR_1_SHIFT 10 +#define PXP_STAT_RSVD2_MASK 0x800u +#define PXP_STAT_RSVD2_SHIFT 11 +#define PXP_STAT_AXI_ERROR_ID_1_MASK 0xF000u +#define PXP_STAT_AXI_ERROR_ID_1_SHIFT 12 +#define PXP_STAT_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_AXI_ERROR_ID_1_SHIFT))&PXP_STAT_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_BLOCKY_MASK 0xFF0000u +#define PXP_STAT_BLOCKY_SHIFT 16 +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKY_SHIFT))&PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK 0xFF000000u +#define PXP_STAT_BLOCKX_SHIFT 24 +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x))<<PXP_STAT_BLOCKX_SHIFT))&PXP_STAT_BLOCKX_MASK) +/* OUT_CTRL Bit Fields */ +#define PXP_OUT_CTRL_FORMAT_MASK 0x1Fu +#define PXP_OUT_CTRL_FORMAT_SHIFT 0 +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_FORMAT_SHIFT))&PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_RSVD0_MASK 0xE0u +#define PXP_OUT_CTRL_RSVD0_SHIFT 5 +#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD0_SHIFT))&PXP_OUT_CTRL_RSVD0_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK 0x300u +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT 8 +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT))&PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_RSVD1_MASK 0x7FFC00u +#define PXP_OUT_CTRL_RSVD1_SHIFT 10 +#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_RSVD1_SHIFT))&PXP_OUT_CTRL_RSVD1_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK 0x800000u +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT 23 +#define PXP_OUT_CTRL_ALPHA_MASK 0xFF000000u +#define PXP_OUT_CTRL_ALPHA_SHIFT 24 +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_CTRL_ALPHA_SHIFT))&PXP_OUT_CTRL_ALPHA_MASK) +/* OUT_BUF Bit Fields */ +#define PXP_OUT_BUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_OUT_BUF_ADDR_SHIFT 0 +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF_ADDR_SHIFT))&PXP_OUT_BUF_ADDR_MASK) +/* OUT_BUF2 Bit Fields */ +#define PXP_OUT_BUF2_ADDR_MASK 0xFFFFFFFFu +#define PXP_OUT_BUF2_ADDR_SHIFT 0 +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_BUF2_ADDR_SHIFT))&PXP_OUT_BUF2_ADDR_MASK) +/* OUT_PITCH Bit Fields */ +#define PXP_OUT_PITCH_PITCH_MASK 0xFFFFu +#define PXP_OUT_PITCH_PITCH_SHIFT 0 +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_PITCH_SHIFT))&PXP_OUT_PITCH_PITCH_MASK) +#define PXP_OUT_PITCH_RSVD_MASK 0xFFFF0000u +#define PXP_OUT_PITCH_RSVD_SHIFT 16 +#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PITCH_RSVD_SHIFT))&PXP_OUT_PITCH_RSVD_MASK) +/* OUT_LRC Bit Fields */ +#define PXP_OUT_LRC_Y_MASK 0x3FFFu +#define PXP_OUT_LRC_Y_SHIFT 0 +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_Y_SHIFT))&PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_RSVD0_MASK 0xC000u +#define PXP_OUT_LRC_RSVD0_SHIFT 14 +#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD0_SHIFT))&PXP_OUT_LRC_RSVD0_MASK) +#define PXP_OUT_LRC_X_MASK 0x3FFF0000u +#define PXP_OUT_LRC_X_SHIFT 16 +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_X_SHIFT))&PXP_OUT_LRC_X_MASK) +#define PXP_OUT_LRC_RSVD1_MASK 0xC0000000u +#define PXP_OUT_LRC_RSVD1_SHIFT 30 +#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_LRC_RSVD1_SHIFT))&PXP_OUT_LRC_RSVD1_MASK) +/* OUT_PS_ULC Bit Fields */ +#define PXP_OUT_PS_ULC_Y_MASK 0x3FFFu +#define PXP_OUT_PS_ULC_Y_SHIFT 0 +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_Y_SHIFT))&PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_RSVD0_MASK 0xC000u +#define PXP_OUT_PS_ULC_RSVD0_SHIFT 14 +#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD0_SHIFT))&PXP_OUT_PS_ULC_RSVD0_MASK) +#define PXP_OUT_PS_ULC_X_MASK 0x3FFF0000u +#define PXP_OUT_PS_ULC_X_SHIFT 16 +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_X_SHIFT))&PXP_OUT_PS_ULC_X_MASK) +#define PXP_OUT_PS_ULC_RSVD1_MASK 0xC0000000u +#define PXP_OUT_PS_ULC_RSVD1_SHIFT 30 +#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_ULC_RSVD1_SHIFT))&PXP_OUT_PS_ULC_RSVD1_MASK) +/* OUT_PS_LRC Bit Fields */ +#define PXP_OUT_PS_LRC_Y_MASK 0x3FFFu +#define PXP_OUT_PS_LRC_Y_SHIFT 0 +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_Y_SHIFT))&PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_RSVD0_MASK 0xC000u +#define PXP_OUT_PS_LRC_RSVD0_SHIFT 14 +#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD0_SHIFT))&PXP_OUT_PS_LRC_RSVD0_MASK) +#define PXP_OUT_PS_LRC_X_MASK 0x3FFF0000u +#define PXP_OUT_PS_LRC_X_SHIFT 16 +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_X_SHIFT))&PXP_OUT_PS_LRC_X_MASK) +#define PXP_OUT_PS_LRC_RSVD1_MASK 0xC0000000u +#define PXP_OUT_PS_LRC_RSVD1_SHIFT 30 +#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_PS_LRC_RSVD1_SHIFT))&PXP_OUT_PS_LRC_RSVD1_MASK) +/* OUT_AS_ULC Bit Fields */ +#define PXP_OUT_AS_ULC_Y_MASK 0x3FFFu +#define PXP_OUT_AS_ULC_Y_SHIFT 0 +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_Y_SHIFT))&PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_RSVD0_MASK 0xC000u +#define PXP_OUT_AS_ULC_RSVD0_SHIFT 14 +#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD0_SHIFT))&PXP_OUT_AS_ULC_RSVD0_MASK) +#define PXP_OUT_AS_ULC_X_MASK 0x3FFF0000u +#define PXP_OUT_AS_ULC_X_SHIFT 16 +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_X_SHIFT))&PXP_OUT_AS_ULC_X_MASK) +#define PXP_OUT_AS_ULC_RSVD1_MASK 0xC0000000u +#define PXP_OUT_AS_ULC_RSVD1_SHIFT 30 +#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_ULC_RSVD1_SHIFT))&PXP_OUT_AS_ULC_RSVD1_MASK) +/* OUT_AS_LRC Bit Fields */ +#define PXP_OUT_AS_LRC_Y_MASK 0x3FFFu +#define PXP_OUT_AS_LRC_Y_SHIFT 0 +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_Y_SHIFT))&PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_RSVD0_MASK 0xC000u +#define PXP_OUT_AS_LRC_RSVD0_SHIFT 14 +#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD0_SHIFT))&PXP_OUT_AS_LRC_RSVD0_MASK) +#define PXP_OUT_AS_LRC_X_MASK 0x3FFF0000u +#define PXP_OUT_AS_LRC_X_SHIFT 16 +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_X_SHIFT))&PXP_OUT_AS_LRC_X_MASK) +#define PXP_OUT_AS_LRC_RSVD1_MASK 0xC0000000u +#define PXP_OUT_AS_LRC_RSVD1_SHIFT 30 +#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_OUT_AS_LRC_RSVD1_SHIFT))&PXP_OUT_AS_LRC_RSVD1_MASK) +/* PS_CTRL Bit Fields */ +#define PXP_PS_CTRL_FORMAT_MASK 0x3Fu +#define PXP_PS_CTRL_FORMAT_SHIFT 0 +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_FORMAT_SHIFT))&PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK 0x40u +#define PXP_PS_CTRL_WB_SWAP_SHIFT 6 +#define PXP_PS_CTRL_RSVD0_MASK 0x80u +#define PXP_PS_CTRL_RSVD0_SHIFT 7 +#define PXP_PS_CTRL_DECY_MASK 0x300u +#define PXP_PS_CTRL_DECY_SHIFT 8 +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECY_SHIFT))&PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK 0xC00u +#define PXP_PS_CTRL_DECX_SHIFT 10 +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_DECX_SHIFT))&PXP_PS_CTRL_DECX_MASK) +#define PXP_PS_CTRL_RSVD1_MASK 0xFFFFF000u +#define PXP_PS_CTRL_RSVD1_SHIFT 12 +#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_CTRL_RSVD1_SHIFT))&PXP_PS_CTRL_RSVD1_MASK) +/* PS_BUF Bit Fields */ +#define PXP_PS_BUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_PS_BUF_ADDR_SHIFT 0 +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_BUF_ADDR_SHIFT))&PXP_PS_BUF_ADDR_MASK) +/* PS_UBUF Bit Fields */ +#define PXP_PS_UBUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_PS_UBUF_ADDR_SHIFT 0 +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_UBUF_ADDR_SHIFT))&PXP_PS_UBUF_ADDR_MASK) +/* PS_VBUF Bit Fields */ +#define PXP_PS_VBUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_PS_VBUF_ADDR_SHIFT 0 +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_VBUF_ADDR_SHIFT))&PXP_PS_VBUF_ADDR_MASK) +/* PS_PITCH Bit Fields */ +#define PXP_PS_PITCH_PITCH_MASK 0xFFFFu +#define PXP_PS_PITCH_PITCH_SHIFT 0 +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_PITCH_SHIFT))&PXP_PS_PITCH_PITCH_MASK) +#define PXP_PS_PITCH_RSVD_MASK 0xFFFF0000u +#define PXP_PS_PITCH_RSVD_SHIFT 16 +#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_PITCH_RSVD_SHIFT))&PXP_PS_PITCH_RSVD_MASK) +/* HW_PXP_PS_BACKGROUND_0 Bit Fields */ +#define PXP_HW_PXP_PS_BACKGROUND_0_COLOR_MASK 0xFFFFFFu +#define PXP_HW_PXP_PS_BACKGROUND_0_COLOR_SHIFT 0 +#define PXP_HW_PXP_PS_BACKGROUND_0_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_0_COLOR_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_0_COLOR_MASK) +#define PXP_HW_PXP_PS_BACKGROUND_0_RSVD_MASK 0xFF000000u +#define PXP_HW_PXP_PS_BACKGROUND_0_RSVD_SHIFT 24 +#define PXP_HW_PXP_PS_BACKGROUND_0_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_0_RSVD_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_0_RSVD_MASK) +/* PS_SCALE Bit Fields */ +#define PXP_PS_SCALE_XSCALE_MASK 0x7FFFu +#define PXP_PS_SCALE_XSCALE_SHIFT 0 +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_XSCALE_SHIFT))&PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_RSVD1_MASK 0x8000u +#define PXP_PS_SCALE_RSVD1_SHIFT 15 +#define PXP_PS_SCALE_YSCALE_MASK 0x7FFF0000u +#define PXP_PS_SCALE_YSCALE_SHIFT 16 +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_SCALE_YSCALE_SHIFT))&PXP_PS_SCALE_YSCALE_MASK) +#define PXP_PS_SCALE_RSVD2_MASK 0x80000000u +#define PXP_PS_SCALE_RSVD2_SHIFT 31 +/* PS_OFFSET Bit Fields */ +#define PXP_PS_OFFSET_XOFFSET_MASK 0xFFFu +#define PXP_PS_OFFSET_XOFFSET_SHIFT 0 +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_XOFFSET_SHIFT))&PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD1_MASK 0xF000u +#define PXP_PS_OFFSET_RSVD1_SHIFT 12 +#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD1_SHIFT))&PXP_PS_OFFSET_RSVD1_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK 0xFFF0000u +#define PXP_PS_OFFSET_YOFFSET_SHIFT 16 +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_YOFFSET_SHIFT))&PXP_PS_OFFSET_YOFFSET_MASK) +#define PXP_PS_OFFSET_RSVD2_MASK 0xF0000000u +#define PXP_PS_OFFSET_RSVD2_SHIFT 28 +#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_PS_OFFSET_RSVD2_SHIFT))&PXP_PS_OFFSET_RSVD2_MASK) +/* HW_PXP_PS_CLRKEYLOW_0 Bit Fields */ +#define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT 0 +#define PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_0_PIXEL_MASK) +#define PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_SHIFT 24 +#define PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_0_RSVD1_MASK) +/* HW_PXP_PS_CLRKEYHIGH_0 Bit Fields */ +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT 0 +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_0_PIXEL_MASK) +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT 24 +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_0_RSVD1_MASK) +/* AS_CTRL Bit Fields */ +#define PXP_AS_CTRL_RSVD0_MASK 0x1u +#define PXP_AS_CTRL_RSVD0_SHIFT 0 +#define PXP_AS_CTRL_ALPHA_CTRL_MASK 0x6u +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT 1 +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_CTRL_SHIFT))&PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK 0x8u +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT 3 +#define PXP_AS_CTRL_FORMAT_MASK 0xF0u +#define PXP_AS_CTRL_FORMAT_SHIFT 4 +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_FORMAT_SHIFT))&PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK 0xFF00u +#define PXP_AS_CTRL_ALPHA_SHIFT 8 +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ALPHA_SHIFT))&PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK 0xF0000u +#define PXP_AS_CTRL_ROP_SHIFT 16 +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_ROP_SHIFT))&PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA0_INVERT_MASK 0x100000u +#define PXP_AS_CTRL_ALPHA0_INVERT_SHIFT 20 +#define PXP_AS_CTRL_ALPHA1_INVERT_MASK 0x200000u +#define PXP_AS_CTRL_ALPHA1_INVERT_SHIFT 21 +#define PXP_AS_CTRL_RSVD1_MASK 0xFFC00000u +#define PXP_AS_CTRL_RSVD1_SHIFT 22 +#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_CTRL_RSVD1_SHIFT))&PXP_AS_CTRL_RSVD1_MASK) +/* AS_BUF Bit Fields */ +#define PXP_AS_BUF_ADDR_MASK 0xFFFFFFFFu +#define PXP_AS_BUF_ADDR_SHIFT 0 +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_BUF_ADDR_SHIFT))&PXP_AS_BUF_ADDR_MASK) +/* AS_PITCH Bit Fields */ +#define PXP_AS_PITCH_PITCH_MASK 0xFFFFu +#define PXP_AS_PITCH_PITCH_SHIFT 0 +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_PITCH_SHIFT))&PXP_AS_PITCH_PITCH_MASK) +#define PXP_AS_PITCH_RSVD_MASK 0xFFFF0000u +#define PXP_AS_PITCH_RSVD_SHIFT 16 +#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_AS_PITCH_RSVD_SHIFT))&PXP_AS_PITCH_RSVD_MASK) +/* HW_PXP_AS_CLRKEYLOW_0 Bit Fields */ +#define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT 0 +#define PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_0_PIXEL_MASK) +#define PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_SHIFT 24 +#define PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_0_RSVD1_MASK) +/* HW_PXP_AS_CLRKEYHIGH_0 Bit Fields */ +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT 0 +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_0_PIXEL_MASK) +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT 24 +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_0_RSVD1_MASK) +/* CSC1_COEF0 Bit Fields */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK 0x1FFu +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT 0 +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_Y_OFFSET_SHIFT))&PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK 0x3FE00u +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT 9 +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_UV_OFFSET_SHIFT))&PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK 0x1FFC0000u +#define PXP_CSC1_COEF0_C0_SHIFT 18 +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF0_C0_SHIFT))&PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_RSVD1_MASK 0x20000000u +#define PXP_CSC1_COEF0_RSVD1_SHIFT 29 +#define PXP_CSC1_COEF0_BYPASS_MASK 0x40000000u +#define PXP_CSC1_COEF0_BYPASS_SHIFT 30 +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK 0x80000000u +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT 31 +/* CSC1_COEF1 Bit Fields */ +#define PXP_CSC1_COEF1_C4_MASK 0x7FFu +#define PXP_CSC1_COEF1_C4_SHIFT 0 +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C4_SHIFT))&PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_RSVD0_MASK 0xF800u +#define PXP_CSC1_COEF1_RSVD0_SHIFT 11 +#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD0_SHIFT))&PXP_CSC1_COEF1_RSVD0_MASK) +#define PXP_CSC1_COEF1_C1_MASK 0x7FF0000u +#define PXP_CSC1_COEF1_C1_SHIFT 16 +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_C1_SHIFT))&PXP_CSC1_COEF1_C1_MASK) +#define PXP_CSC1_COEF1_RSVD1_MASK 0xF8000000u +#define PXP_CSC1_COEF1_RSVD1_SHIFT 27 +#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF1_RSVD1_SHIFT))&PXP_CSC1_COEF1_RSVD1_MASK) +/* CSC1_COEF2 Bit Fields */ +#define PXP_CSC1_COEF2_C3_MASK 0x7FFu +#define PXP_CSC1_COEF2_C3_SHIFT 0 +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C3_SHIFT))&PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_RSVD0_MASK 0xF800u +#define PXP_CSC1_COEF2_RSVD0_SHIFT 11 +#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD0_SHIFT))&PXP_CSC1_COEF2_RSVD0_MASK) +#define PXP_CSC1_COEF2_C2_MASK 0x7FF0000u +#define PXP_CSC1_COEF2_C2_SHIFT 16 +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_C2_SHIFT))&PXP_CSC1_COEF2_C2_MASK) +#define PXP_CSC1_COEF2_RSVD1_MASK 0xF8000000u +#define PXP_CSC1_COEF2_RSVD1_SHIFT 27 +#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC1_COEF2_RSVD1_SHIFT))&PXP_CSC1_COEF2_RSVD1_MASK) +/* CSC2_CTRL Bit Fields */ +#define PXP_CSC2_CTRL_BYPASS_MASK 0x1u +#define PXP_CSC2_CTRL_BYPASS_SHIFT 0 +#define PXP_CSC2_CTRL_CSC_MODE_MASK 0x6u +#define PXP_CSC2_CTRL_CSC_MODE_SHIFT 1 +#define PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_CSC_MODE_SHIFT))&PXP_CSC2_CTRL_CSC_MODE_MASK) +#define PXP_CSC2_CTRL_RSVD_MASK 0xFFFFFFF8u +#define PXP_CSC2_CTRL_RSVD_SHIFT 3 +#define PXP_CSC2_CTRL_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_CTRL_RSVD_SHIFT))&PXP_CSC2_CTRL_RSVD_MASK) +/* CSC2_COEF0 Bit Fields */ +#define PXP_CSC2_COEF0_A1_MASK 0x7FFu +#define PXP_CSC2_COEF0_A1_SHIFT 0 +#define PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A1_SHIFT))&PXP_CSC2_COEF0_A1_MASK) +#define PXP_CSC2_COEF0_RSVD0_MASK 0xF800u +#define PXP_CSC2_COEF0_RSVD0_SHIFT 11 +#define PXP_CSC2_COEF0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD0_SHIFT))&PXP_CSC2_COEF0_RSVD0_MASK) +#define PXP_CSC2_COEF0_A2_MASK 0x7FF0000u +#define PXP_CSC2_COEF0_A2_SHIFT 16 +#define PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_A2_SHIFT))&PXP_CSC2_COEF0_A2_MASK) +#define PXP_CSC2_COEF0_RSVD1_MASK 0xF8000000u +#define PXP_CSC2_COEF0_RSVD1_SHIFT 27 +#define PXP_CSC2_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF0_RSVD1_SHIFT))&PXP_CSC2_COEF0_RSVD1_MASK) +/* CSC2_COEF1 Bit Fields */ +#define PXP_CSC2_COEF1_A3_MASK 0x7FFu +#define PXP_CSC2_COEF1_A3_SHIFT 0 +#define PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_A3_SHIFT))&PXP_CSC2_COEF1_A3_MASK) +#define PXP_CSC2_COEF1_RSVD0_MASK 0xF800u +#define PXP_CSC2_COEF1_RSVD0_SHIFT 11 +#define PXP_CSC2_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD0_SHIFT))&PXP_CSC2_COEF1_RSVD0_MASK) +#define PXP_CSC2_COEF1_B1_MASK 0x7FF0000u +#define PXP_CSC2_COEF1_B1_SHIFT 16 +#define PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_B1_SHIFT))&PXP_CSC2_COEF1_B1_MASK) +#define PXP_CSC2_COEF1_RSVD1_MASK 0xF8000000u +#define PXP_CSC2_COEF1_RSVD1_SHIFT 27 +#define PXP_CSC2_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF1_RSVD1_SHIFT))&PXP_CSC2_COEF1_RSVD1_MASK) +/* CSC2_COEF2 Bit Fields */ +#define PXP_CSC2_COEF2_B2_MASK 0x7FFu +#define PXP_CSC2_COEF2_B2_SHIFT 0 +#define PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B2_SHIFT))&PXP_CSC2_COEF2_B2_MASK) +#define PXP_CSC2_COEF2_RSVD0_MASK 0xF800u +#define PXP_CSC2_COEF2_RSVD0_SHIFT 11 +#define PXP_CSC2_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD0_SHIFT))&PXP_CSC2_COEF2_RSVD0_MASK) +#define PXP_CSC2_COEF2_B3_MASK 0x7FF0000u +#define PXP_CSC2_COEF2_B3_SHIFT 16 +#define PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_B3_SHIFT))&PXP_CSC2_COEF2_B3_MASK) +#define PXP_CSC2_COEF2_RSVD1_MASK 0xF8000000u +#define PXP_CSC2_COEF2_RSVD1_SHIFT 27 +#define PXP_CSC2_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF2_RSVD1_SHIFT))&PXP_CSC2_COEF2_RSVD1_MASK) +/* CSC2_COEF3 Bit Fields */ +#define PXP_CSC2_COEF3_C1_MASK 0x7FFu +#define PXP_CSC2_COEF3_C1_SHIFT 0 +#define PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C1_SHIFT))&PXP_CSC2_COEF3_C1_MASK) +#define PXP_CSC2_COEF3_RSVD0_MASK 0xF800u +#define PXP_CSC2_COEF3_RSVD0_SHIFT 11 +#define PXP_CSC2_COEF3_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD0_SHIFT))&PXP_CSC2_COEF3_RSVD0_MASK) +#define PXP_CSC2_COEF3_C2_MASK 0x7FF0000u +#define PXP_CSC2_COEF3_C2_SHIFT 16 +#define PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_C2_SHIFT))&PXP_CSC2_COEF3_C2_MASK) +#define PXP_CSC2_COEF3_RSVD1_MASK 0xF8000000u +#define PXP_CSC2_COEF3_RSVD1_SHIFT 27 +#define PXP_CSC2_COEF3_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF3_RSVD1_SHIFT))&PXP_CSC2_COEF3_RSVD1_MASK) +/* CSC2_COEF4 Bit Fields */ +#define PXP_CSC2_COEF4_C3_MASK 0x7FFu +#define PXP_CSC2_COEF4_C3_SHIFT 0 +#define PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_C3_SHIFT))&PXP_CSC2_COEF4_C3_MASK) +#define PXP_CSC2_COEF4_RSVD0_MASK 0xF800u +#define PXP_CSC2_COEF4_RSVD0_SHIFT 11 +#define PXP_CSC2_COEF4_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD0_SHIFT))&PXP_CSC2_COEF4_RSVD0_MASK) +#define PXP_CSC2_COEF4_D1_MASK 0x1FF0000u +#define PXP_CSC2_COEF4_D1_SHIFT 16 +#define PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_D1_SHIFT))&PXP_CSC2_COEF4_D1_MASK) +#define PXP_CSC2_COEF4_RSVD1_MASK 0xFE000000u +#define PXP_CSC2_COEF4_RSVD1_SHIFT 25 +#define PXP_CSC2_COEF4_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF4_RSVD1_SHIFT))&PXP_CSC2_COEF4_RSVD1_MASK) +/* CSC2_COEF5 Bit Fields */ +#define PXP_CSC2_COEF5_D2_MASK 0x1FFu +#define PXP_CSC2_COEF5_D2_SHIFT 0 +#define PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D2_SHIFT))&PXP_CSC2_COEF5_D2_MASK) +#define PXP_CSC2_COEF5_RSVD0_MASK 0xFE00u +#define PXP_CSC2_COEF5_RSVD0_SHIFT 9 +#define PXP_CSC2_COEF5_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD0_SHIFT))&PXP_CSC2_COEF5_RSVD0_MASK) +#define PXP_CSC2_COEF5_D3_MASK 0x1FF0000u +#define PXP_CSC2_COEF5_D3_SHIFT 16 +#define PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_D3_SHIFT))&PXP_CSC2_COEF5_D3_MASK) +#define PXP_CSC2_COEF5_RSVD1_MASK 0xFE000000u +#define PXP_CSC2_COEF5_RSVD1_SHIFT 25 +#define PXP_CSC2_COEF5_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_CSC2_COEF5_RSVD1_SHIFT))&PXP_CSC2_COEF5_RSVD1_MASK) +/* LUT_CTRL Bit Fields */ +#define PXP_LUT_CTRL_DMA_START_MASK 0x1u +#define PXP_LUT_CTRL_DMA_START_SHIFT 0 +#define PXP_LUT_CTRL_RSVD0_MASK 0xFEu +#define PXP_LUT_CTRL_RSVD0_SHIFT 1 +#define PXP_LUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD0_SHIFT))&PXP_LUT_CTRL_RSVD0_MASK) +#define PXP_LUT_CTRL_INVALID_MASK 0x100u +#define PXP_LUT_CTRL_INVALID_SHIFT 8 +#define PXP_LUT_CTRL_LRU_UPD_MASK 0x200u +#define PXP_LUT_CTRL_LRU_UPD_SHIFT 9 +#define PXP_LUT_CTRL_SEL_8KB_MASK 0x400u +#define PXP_LUT_CTRL_SEL_8KB_SHIFT 10 +#define PXP_LUT_CTRL_RSVD1_MASK 0xF800u +#define PXP_LUT_CTRL_RSVD1_SHIFT 11 +#define PXP_LUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD1_SHIFT))&PXP_LUT_CTRL_RSVD1_MASK) +#define PXP_LUT_CTRL_OUT_MODE_MASK 0x30000u +#define PXP_LUT_CTRL_OUT_MODE_SHIFT 16 +#define PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_OUT_MODE_SHIFT))&PXP_LUT_CTRL_OUT_MODE_MASK) +#define PXP_LUT_CTRL_RSVD2_MASK 0xFC0000u +#define PXP_LUT_CTRL_RSVD2_SHIFT 18 +#define PXP_LUT_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD2_SHIFT))&PXP_LUT_CTRL_RSVD2_MASK) +#define PXP_LUT_CTRL_LOOKUP_MODE_MASK 0x3000000u +#define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT 24 +#define PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_LOOKUP_MODE_SHIFT))&PXP_LUT_CTRL_LOOKUP_MODE_MASK) +#define PXP_LUT_CTRL_RSVD3_MASK 0x7C000000u +#define PXP_LUT_CTRL_RSVD3_SHIFT 26 +#define PXP_LUT_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_CTRL_RSVD3_SHIFT))&PXP_LUT_CTRL_RSVD3_MASK) +#define PXP_LUT_CTRL_BYPASS_MASK 0x80000000u +#define PXP_LUT_CTRL_BYPASS_SHIFT 31 +/* LUT_ADDR Bit Fields */ +#define PXP_LUT_ADDR_ADDR_MASK 0x3FFFu +#define PXP_LUT_ADDR_ADDR_SHIFT 0 +#define PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_ADDR_SHIFT))&PXP_LUT_ADDR_ADDR_MASK) +#define PXP_LUT_ADDR_RSVD1_MASK 0xC000u +#define PXP_LUT_ADDR_RSVD1_SHIFT 14 +#define PXP_LUT_ADDR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_RSVD1_SHIFT))&PXP_LUT_ADDR_RSVD1_MASK) +#define PXP_LUT_ADDR_NUM_BYTES_MASK 0x7FFF0000u +#define PXP_LUT_ADDR_NUM_BYTES_SHIFT 16 +#define PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_ADDR_NUM_BYTES_SHIFT))&PXP_LUT_ADDR_NUM_BYTES_MASK) +#define PXP_LUT_ADDR_RSVD2_MASK 0x80000000u +#define PXP_LUT_ADDR_RSVD2_SHIFT 31 +/* LUT_DATA Bit Fields */ +#define PXP_LUT_DATA_DATA_MASK 0xFFFFFFFFu +#define PXP_LUT_DATA_DATA_SHIFT 0 +#define PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_DATA_DATA_SHIFT))&PXP_LUT_DATA_DATA_MASK) +/* LUT_EXTMEM Bit Fields */ +#define PXP_LUT_EXTMEM_ADDR_MASK 0xFFFFFFFFu +#define PXP_LUT_EXTMEM_ADDR_SHIFT 0 +#define PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_LUT_EXTMEM_ADDR_SHIFT))&PXP_LUT_EXTMEM_ADDR_MASK) +/* CFA Bit Fields */ +#define PXP_CFA_DATA_MASK 0xFFFFFFFFu +#define PXP_CFA_DATA_SHIFT 0 +#define PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_CFA_DATA_SHIFT))&PXP_CFA_DATA_MASK) +/* HW_PXP_ALPHA_A_CTRL Bit Fields */ +#define PXP_HW_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK 0x1u +#define PXP_HW_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT 0 +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK 0x6u +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT 1 +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK 0x18u +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT 3 +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK 0x20u +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT 5 +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK 0x40u +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT 6 +#define PXP_HW_PXP_ALPHA_A_CTRL_RSVD1_MASK 0x80u +#define PXP_HW_PXP_ALPHA_A_CTRL_RSVD1_SHIFT 7 +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK 0x300u +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT 8 +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK 0xC00u +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT 10 +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK 0x1000u +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT 12 +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK 0x2000u +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT 13 +#define PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_MASK 0xC000u +#define PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_SHIFT 14 +#define PXP_HW_PXP_ALPHA_A_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK 0xFF0000u +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT 16 +#define PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK 0xFF000000u +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT 24 +#define PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK) +/* HW_PXP_ALPHA_B_CTRL Bit Fields */ +#define PXP_HW_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE_MASK 0x1u +#define PXP_HW_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE_SHIFT 0 +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_MASK 0x6u +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_SHIFT 1 +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_MASK 0x18u +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT 3 +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_MASK 0x20u +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE_SHIFT 5 +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_COLOR_MODE_MASK 0x40u +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_COLOR_MODE_SHIFT 6 +#define PXP_HW_PXP_ALPHA_B_CTRL_RSVD1_MASK 0x80u +#define PXP_HW_PXP_ALPHA_B_CTRL_RSVD1_SHIFT 7 +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_MASK 0x300u +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_SHIFT 8 +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_MASK 0xC00u +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT 10 +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_MASK 0x1000u +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE_SHIFT 12 +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_COLOR_MODE_MASK 0x2000u +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_COLOR_MODE_SHIFT 13 +#define PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_MASK 0xC000u +#define PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_SHIFT 14 +#define PXP_HW_PXP_ALPHA_B_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MASK 0xFF0000u +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_SHIFT 16 +#define PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MASK 0xFF000000u +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_SHIFT 24 +#define PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MASK) +/* HW_PXP_ALPHA_B_CTRL_1 Bit Fields */ +#define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_ENABLE_MASK 0x1u +#define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_ENABLE_SHIFT 0 +#define PXP_HW_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK 0x2u +#define PXP_HW_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_SHIFT 1 +#define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_MASK 0xCu +#define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_SHIFT 2 +#define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD1_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_MASK 0xF0u +#define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_SHIFT 4 +#define PXP_HW_PXP_ALPHA_B_CTRL_1_ROP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_1_ROP_MASK) +#define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_MASK 0xFFFFFF00u +#define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_SHIFT 8 +#define PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_SHIFT))&PXP_HW_PXP_ALPHA_B_CTRL_1_RSVD0_MASK) +/* HW_PXP_PS_BACKGROUND_1 Bit Fields */ +#define PXP_HW_PXP_PS_BACKGROUND_1_COLOR_MASK 0xFFFFFFu +#define PXP_HW_PXP_PS_BACKGROUND_1_COLOR_SHIFT 0 +#define PXP_HW_PXP_PS_BACKGROUND_1_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_1_COLOR_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_1_COLOR_MASK) +#define PXP_HW_PXP_PS_BACKGROUND_1_RSVD_MASK 0xFF000000u +#define PXP_HW_PXP_PS_BACKGROUND_1_RSVD_SHIFT 24 +#define PXP_HW_PXP_PS_BACKGROUND_1_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_BACKGROUND_1_RSVD_SHIFT))&PXP_HW_PXP_PS_BACKGROUND_1_RSVD_MASK) +/* HW_PXP_PS_CLRKEYLOW_1 Bit Fields */ +#define PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT 0 +#define PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_1_PIXEL_MASK) +#define PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_SHIFT 24 +#define PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYLOW_1_RSVD1_MASK) +/* HW_PXP_PS_CLRKEYHIGH_1 Bit Fields */ +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT 0 +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_1_PIXEL_MASK) +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_SHIFT 24 +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_SHIFT))&PXP_HW_PXP_PS_CLRKEYHIGH_1_RSVD1_MASK) +/* HW_PXP_AS_CLRKEYLOW_1 Bit Fields */ +#define PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT 0 +#define PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_1_PIXEL_MASK) +#define PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_SHIFT 24 +#define PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYLOW_1_RSVD1_MASK) +/* HW_PXP_AS_CLRKEYHIGH_1 Bit Fields */ +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT 0 +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_1_PIXEL_MASK) +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_SHIFT 24 +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_SHIFT))&PXP_HW_PXP_AS_CLRKEYHIGH_1_RSVD1_MASK) +/* HW_PXP_CTRL2 Bit Fields */ +#define PXP_HW_PXP_CTRL2_ENABLE_MASK 0x1u +#define PXP_HW_PXP_CTRL2_ENABLE_SHIFT 0 +#define PXP_HW_PXP_CTRL2_RSVD0_MASK 0xFEu +#define PXP_HW_PXP_CTRL2_RSVD0_SHIFT 1 +#define PXP_HW_PXP_CTRL2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_RSVD0_SHIFT))&PXP_HW_PXP_CTRL2_RSVD0_MASK) +#define PXP_HW_PXP_CTRL2_ROTATE0_MASK 0x300u +#define PXP_HW_PXP_CTRL2_ROTATE0_SHIFT 8 +#define PXP_HW_PXP_CTRL2_ROTATE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_ROTATE0_SHIFT))&PXP_HW_PXP_CTRL2_ROTATE0_MASK) +#define PXP_HW_PXP_CTRL2_HFLIP0_MASK 0x400u +#define PXP_HW_PXP_CTRL2_HFLIP0_SHIFT 10 +#define PXP_HW_PXP_CTRL2_VFLIP0_MASK 0x800u +#define PXP_HW_PXP_CTRL2_VFLIP0_SHIFT 11 +#define PXP_HW_PXP_CTRL2_ROTATE1_MASK 0x3000u +#define PXP_HW_PXP_CTRL2_ROTATE1_SHIFT 12 +#define PXP_HW_PXP_CTRL2_ROTATE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_ROTATE1_SHIFT))&PXP_HW_PXP_CTRL2_ROTATE1_MASK) +#define PXP_HW_PXP_CTRL2_HFLIP1_MASK 0x4000u +#define PXP_HW_PXP_CTRL2_HFLIP1_SHIFT 14 +#define PXP_HW_PXP_CTRL2_VFLIP1_MASK 0x8000u +#define PXP_HW_PXP_CTRL2_VFLIP1_SHIFT 15 +#define PXP_HW_PXP_CTRL2_RSVD1_MASK 0x10000u +#define PXP_HW_PXP_CTRL2_RSVD1_SHIFT 16 +#define PXP_HW_PXP_CTRL2_ENABLE_DITHER_MASK 0x20000u +#define PXP_HW_PXP_CTRL2_ENABLE_DITHER_SHIFT 17 +#define PXP_HW_PXP_CTRL2_ENABLE_WFE_A_MASK 0x40000u +#define PXP_HW_PXP_CTRL2_ENABLE_WFE_A_SHIFT 18 +#define PXP_HW_PXP_CTRL2_ENABLE_WFE_B_MASK 0x80000u +#define PXP_HW_PXP_CTRL2_ENABLE_WFE_B_SHIFT 19 +#define PXP_HW_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_MASK 0x100000u +#define PXP_HW_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE_SHIFT 20 +#define PXP_HW_PXP_CTRL2_ENABLE_ALPHA_B_MASK 0x200000u +#define PXP_HW_PXP_CTRL2_ENABLE_ALPHA_B_SHIFT 21 +#define PXP_HW_PXP_CTRL2_RSVD2_MASK 0x400000u +#define PXP_HW_PXP_CTRL2_RSVD2_SHIFT 22 +#define PXP_HW_PXP_CTRL2_BLOCK_SIZE_MASK 0x800000u +#define PXP_HW_PXP_CTRL2_BLOCK_SIZE_SHIFT 23 +#define PXP_HW_PXP_CTRL2_ENABLE_CSC2_MASK 0x1000000u +#define PXP_HW_PXP_CTRL2_ENABLE_CSC2_SHIFT 24 +#define PXP_HW_PXP_CTRL2_ENABLE_LUT_MASK 0x2000000u +#define PXP_HW_PXP_CTRL2_ENABLE_LUT_SHIFT 25 +#define PXP_HW_PXP_CTRL2_ENABLE_ROTATE0_MASK 0x4000000u +#define PXP_HW_PXP_CTRL2_ENABLE_ROTATE0_SHIFT 26 +#define PXP_HW_PXP_CTRL2_ENABLE_ROTATE1_MASK 0x8000000u +#define PXP_HW_PXP_CTRL2_ENABLE_ROTATE1_SHIFT 27 +#define PXP_HW_PXP_CTRL2_RSVD3_MASK 0xF0000000u +#define PXP_HW_PXP_CTRL2_RSVD3_SHIFT 28 +#define PXP_HW_PXP_CTRL2_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_CTRL2_RSVD3_SHIFT))&PXP_HW_PXP_CTRL2_RSVD3_MASK) +/* HW_PXP_POWER_REG0 Bit Fields */ +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK 0x7u +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT 0 +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT))&PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK) +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK 0x38u +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT 3 +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT))&PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK) +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK 0x1C0u +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT 6 +#define PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT))&PXP_HW_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK) +#define PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK 0xE00u +#define PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT 9 +#define PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG0_CTRL_MASK 0xFFFFF000u +#define PXP_HW_PXP_POWER_REG0_CTRL_SHIFT 12 +#define PXP_HW_PXP_POWER_REG0_CTRL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG0_CTRL_SHIFT))&PXP_HW_PXP_POWER_REG0_CTRL_MASK) +/* HW_PXP_POWER_REG1 Bit Fields */ +#define PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK 0x7u +#define PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT 0 +#define PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK 0x38u +#define PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT 3 +#define PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK 0x1C0u +#define PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT 6 +#define PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK 0xE00u +#define PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT 9 +#define PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK 0x7000u +#define PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT 12 +#define PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK 0x38000u +#define PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT 15 +#define PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK 0x1C0000u +#define PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT 18 +#define PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK 0xE00000u +#define PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT 21 +#define PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT))&PXP_HW_PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK) +#define PXP_HW_PXP_POWER_REG1_RSVD0_MASK 0xFF000000u +#define PXP_HW_PXP_POWER_REG1_RSVD0_SHIFT 24 +#define PXP_HW_PXP_POWER_REG1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_POWER_REG1_RSVD0_SHIFT))&PXP_HW_PXP_POWER_REG1_RSVD0_MASK) +/* HW_PXP_DATA_PATH_CTRL0 Bit Fields */ +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK 0x3u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT 0 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK 0xCu +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT 2 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_MASK 0x30u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_SHIFT 4 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX2_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK 0xC0u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT 6 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_MASK 0x300u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_SHIFT 8 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX4_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_MASK 0xC00u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_SHIFT 10 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX5_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_MASK 0x3000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_SHIFT 12 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX6_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_MASK 0xC000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_SHIFT 14 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX7_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK 0x30000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT 16 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK 0xC0000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT 18 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_MASK 0x300000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_SHIFT 20 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX10_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK 0xC00000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT 22 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK 0x3000000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT 24 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_MASK 0xC000000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_SHIFT 26 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX13_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK 0x30000000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT 28 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_MASK 0xC0000000u +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_SHIFT 30 +#define PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL0_MUX15_SEL_MASK) +/* HW_PXP_DATA_PATH_CTRL1 Bit Fields */ +#define PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK 0x3u +#define PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT 0 +#define PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK 0xCu +#define PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT 2 +#define PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK) +#define PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_MASK 0xFFFFFFF0u +#define PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_SHIFT 4 +#define PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_SHIFT))&PXP_HW_PXP_DATA_PATH_CTRL1_RSVD0_MASK) +/* HW_PXP_INIT_MEM_CTRL Bit Fields */ +#define PXP_HW_PXP_INIT_MEM_CTRL_ADDR_MASK 0xFFFFu +#define PXP_HW_PXP_INIT_MEM_CTRL_ADDR_SHIFT 0 +#define PXP_HW_PXP_INIT_MEM_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_CTRL_ADDR_SHIFT))&PXP_HW_PXP_INIT_MEM_CTRL_ADDR_MASK) +#define PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_MASK 0x7FF0000u +#define PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_SHIFT 16 +#define PXP_HW_PXP_INIT_MEM_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_INIT_MEM_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_INIT_MEM_CTRL_SELECT_MASK 0x78000000u +#define PXP_HW_PXP_INIT_MEM_CTRL_SELECT_SHIFT 27 +#define PXP_HW_PXP_INIT_MEM_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_CTRL_SELECT_SHIFT))&PXP_HW_PXP_INIT_MEM_CTRL_SELECT_MASK) +#define PXP_HW_PXP_INIT_MEM_CTRL_START_MASK 0x80000000u +#define PXP_HW_PXP_INIT_MEM_CTRL_START_SHIFT 31 +/* HW_PXP_INIT_MEM_DATA Bit Fields */ +#define PXP_HW_PXP_INIT_MEM_DATA_DATA_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INIT_MEM_DATA_DATA_SHIFT 0 +#define PXP_HW_PXP_INIT_MEM_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_DATA_DATA_SHIFT))&PXP_HW_PXP_INIT_MEM_DATA_DATA_MASK) +/* HW_PXP_INIT_MEM_DATA_HIGH Bit Fields */ +#define PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT 0 +#define PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT))&PXP_HW_PXP_INIT_MEM_DATA_HIGH_DATA_MASK) +/* HW_PXP_IRQ_MASK Bit Fields */ +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK 0x1u +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_SHIFT 0 +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK 0x2u +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_SHIFT 1 +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK 0x4u +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_SHIFT 2 +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK 0x8u +#define PXP_HW_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_SHIFT 3 +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK 0x10u +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_SHIFT 4 +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK 0x20u +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_SHIFT 5 +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK 0x40u +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_SHIFT 6 +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK 0x80u +#define PXP_HW_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_SHIFT 7 +#define PXP_HW_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK 0x100u +#define PXP_HW_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_SHIFT 8 +#define PXP_HW_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK 0x200u +#define PXP_HW_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_SHIFT 9 +#define PXP_HW_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK 0x400u +#define PXP_HW_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT 10 +#define PXP_HW_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK 0x800u +#define PXP_HW_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT 11 +#define PXP_HW_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK 0x1000u +#define PXP_HW_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_SHIFT 12 +#define PXP_HW_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK 0x2000u +#define PXP_HW_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_SHIFT 13 +#define PXP_HW_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK 0x4000u +#define PXP_HW_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_SHIFT 14 +#define PXP_HW_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK 0x8000u +#define PXP_HW_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT 15 +#define PXP_HW_PXP_IRQ_MASK_RSVD1_MASK 0x7FFF0000u +#define PXP_HW_PXP_IRQ_MASK_RSVD1_SHIFT 16 +#define PXP_HW_PXP_IRQ_MASK_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_IRQ_MASK_RSVD1_SHIFT))&PXP_HW_PXP_IRQ_MASK_RSVD1_MASK) +#define PXP_HW_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK 0x80000000u +#define PXP_HW_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_SHIFT 31 +/* HW_PXP_IRQ Bit Fields */ +#define PXP_HW_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK 0x1u +#define PXP_HW_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_SHIFT 0 +#define PXP_HW_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK 0x2u +#define PXP_HW_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_SHIFT 1 +#define PXP_HW_PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK 0x4u +#define PXP_HW_PXP_IRQ_FIRST_CH0_STORE_IRQ_SHIFT 2 +#define PXP_HW_PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK 0x8u +#define PXP_HW_PXP_IRQ_FIRST_CH1_STORE_IRQ_SHIFT 3 +#define PXP_HW_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK 0x10u +#define PXP_HW_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_SHIFT 4 +#define PXP_HW_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK 0x20u +#define PXP_HW_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_SHIFT 5 +#define PXP_HW_PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK 0x40u +#define PXP_HW_PXP_IRQ_DITHER_CH0_STORE_IRQ_SHIFT 6 +#define PXP_HW_PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK 0x80u +#define PXP_HW_PXP_IRQ_DITHER_CH1_STORE_IRQ_SHIFT 7 +#define PXP_HW_PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK 0x100u +#define PXP_HW_PXP_IRQ_WFE_A_CH0_STORE_IRQ_SHIFT 8 +#define PXP_HW_PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK 0x200u +#define PXP_HW_PXP_IRQ_WFE_A_CH1_STORE_IRQ_SHIFT 9 +#define PXP_HW_PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK 0x400u +#define PXP_HW_PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT 10 +#define PXP_HW_PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK 0x800u +#define PXP_HW_PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT 11 +#define PXP_HW_PXP_IRQ_FIRST_STORE_IRQ_MASK 0x1000u +#define PXP_HW_PXP_IRQ_FIRST_STORE_IRQ_SHIFT 12 +#define PXP_HW_PXP_IRQ_DITHER_STORE_IRQ_MASK 0x2000u +#define PXP_HW_PXP_IRQ_DITHER_STORE_IRQ_SHIFT 13 +#define PXP_HW_PXP_IRQ_WFE_A_STORE_IRQ_MASK 0x4000u +#define PXP_HW_PXP_IRQ_WFE_A_STORE_IRQ_SHIFT 14 +#define PXP_HW_PXP_IRQ_WFE_B_STORE_IRQ_MASK 0x8000u +#define PXP_HW_PXP_IRQ_WFE_B_STORE_IRQ_SHIFT 15 +#define PXP_HW_PXP_IRQ_RSVD1_MASK 0x7FFF0000u +#define PXP_HW_PXP_IRQ_RSVD1_SHIFT 16 +#define PXP_HW_PXP_IRQ_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_IRQ_RSVD1_SHIFT))&PXP_HW_PXP_IRQ_RSVD1_MASK) +#define PXP_HW_PXP_IRQ_COMPRESS_DONE_IRQ_MASK 0x80000000u +#define PXP_HW_PXP_IRQ_COMPRESS_DONE_IRQ_SHIFT 31 +/* NEXT Bit Fields */ +#define PXP_NEXT_ENABLED_MASK 0x1u +#define PXP_NEXT_ENABLED_SHIFT 0 +#define PXP_NEXT_RSVD_MASK 0x2u +#define PXP_NEXT_RSVD_SHIFT 1 +#define PXP_NEXT_POINTER_MASK 0xFFFFFFFCu +#define PXP_NEXT_POINTER_SHIFT 2 +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x))<<PXP_NEXT_POINTER_SHIFT))&PXP_NEXT_POINTER_MASK) +/* HW_PXP_INPUT_FETCH_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK 0x1u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_CH_EN_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK 0x10u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT 4 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_MASK 0x20u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT 5 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_MASK 0x1C0u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_SHIFT 6 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD4_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HFLIP_MASK 0x200u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HFLIP_SHIFT 9 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_VFLIP_MASK 0x400u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_VFLIP_SHIFT 10 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD3_MASK 0x800u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD3_SHIFT 11 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK 0x3000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT 12 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_MASK 0xC000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_SHIFT 14 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_MASK 0xFC0000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_SHIFT 18 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_MASK 0x7C000000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_SHIFT 26 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_RSVD0_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_MASK 0x80000000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_ARBIT_EN_SHIFT 31 +/* HW_PXP_INPUT_FETCH_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK 0x1u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_CH_EN_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK 0x10u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT 4 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_MASK 0x1E0u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_SHIFT 5 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD4_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HFLIP_MASK 0x200u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HFLIP_SHIFT 9 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_VFLIP_MASK 0x400u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_VFLIP_SHIFT 10 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD3_MASK 0x800u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD3_SHIFT 11 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK 0x3000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT 12 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_MASK 0xC000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_SHIFT 14 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_MASK 0xFC0000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_SHIFT 18 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_MASK 0xFC000000u +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_SHIFT 26 +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_INPUT_FETCH_STATUS_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK) +/* HW_PXP_INPUT_FETCH_STATUS_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK) +/* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK) +/* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK) +/* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK) +/* HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK) +/* HW_PXP_INPUT_FETCH_SIZE_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK) +/* HW_PXP_INPUT_FETCH_SIZE_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK) +/* HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK) +/* HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK) +/* HW_PXP_INPUT_FETCH_PITCH Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_PITCH_CH0_INPUT_PITCH_MASK) +#define PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_FETCH_PITCH_CH1_INPUT_PITCH_MASK) +/* HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK 0x3u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK 0xFCu +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT 2 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK 0x700u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT 8 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK 0x800u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT 11 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x1000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 12 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFE000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT 13 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK) +/* HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK 0x3u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK 0xFCu +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT 2 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK 0x700u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT 8 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK 0x800u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT 11 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK 0x1000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT 12 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFE000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT 13 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK 0x1Fu +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK 0xE0u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT 5 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK 0x1F00u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT 8 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK 0xE000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT 13 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK 0x1F0000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK 0xE00000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT 21 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK 0x1F000000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT 24 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK 0xE0000000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT 29 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK) +/* HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK 0x1Fu +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK 0xE0u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT 5 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK 0x1F00u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT 8 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK 0xE000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT 13 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK 0x1F0000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK 0xE00000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT 21 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK 0x1F000000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT 24 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK 0xE0000000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT 29 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK) +/* HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK 0xFu +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK 0xF0u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT 4 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK 0xF00u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT 8 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK 0xF000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT 12 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK) +/* HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK 0xFu +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK 0xF0u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT 4 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK 0xF00u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT 8 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK 0xF000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT 12 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT 16 +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK) +/* HW_PXP_INPUT_FETCH_ADDR_0_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK) +/* HW_PXP_INPUT_FETCH_ADDR_1_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK) +/* HW_PXP_INPUT_FETCH_ADDR_0_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK) +/* HW_PXP_INPUT_FETCH_ADDR_1_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK) +/* HW_PXP_INPUT_STORE_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK 0x1u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_CH_EN_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_MASK 0x10u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_EN_SHIFT 4 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK 0x60u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT 5 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD3_MASK 0x80u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD3_SHIFT 7 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK 0x100u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK 0x200u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT 9 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_MASK 0x400u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT 10 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_MASK 0x800u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT 11 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_MASK 0xF000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_SHIFT 12 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD2_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_WR_NUM_BYTES_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_MASK 0xFC0000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_SHIFT 18 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK 0x1000000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT 24 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_MASK 0x7E000000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_SHIFT 25 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH0_RSVD0_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_MASK 0x80000000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_ARBIT_EN_SHIFT 31 +/* HW_PXP_INPUT_STORE_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK 0x1u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_CH_EN_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_MASK 0x10u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_EN_SHIFT 4 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK 0x60u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT 5 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD3_MASK 0x80u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD3_SHIFT 7 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK 0x100u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK 0x200u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT 9 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_MASK 0x400u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT 10 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_MASK 0xF800u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_SHIFT 11 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD1_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_WR_NUM_BYTES_MASK) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_MASK 0xFFFC0000u +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_SHIFT 18 +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_INPUT_STORE_STATUS_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_X_MASK) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK) +/* HW_PXP_INPUT_STORE_STATUS_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_X_MASK) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_INPUT_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK) +/* HW_PXP_INPUT_STORE_SIZE_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH0_OUT_HEIGHT_MASK) +/* HW_PXP_INPUT_STORE_SIZE_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_WIDTH_MASK) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_INPUT_STORE_SIZE_CH1_OUT_HEIGHT_MASK) +/* HW_PXP_INPUT_STORE_PITCH Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK 0xFFFFu +#define PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_STORE_PITCH_CH0_OUT_PITCH_MASK) +#define PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_MASK 0xFFFF0000u +#define PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_SHIFT))&PXP_HW_PXP_INPUT_STORE_PITCH_CH1_OUT_PITCH_MASK) +/* HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_MASK 0x3u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD2_MASK) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK 0xCu +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT 2 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK 0x10u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT 4 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK 0x20u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT 5 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_MASK 0x40u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT 6 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x80u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 7 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFFF00u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_RSVD0_MASK) +/* HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_MASK 0x3u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD2_MASK) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK 0xCu +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT 2 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK 0x10u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT 4 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK 0x20u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT 5 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFFFC0u +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT 6 +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_INPUT_STORE_ADDR_0_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK) +/* HW_PXP_INPUT_STORE_ADDR_1_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK) +/* HW_PXP_INPUT_STORE_FILL_DATA_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK) +/* HW_PXP_INPUT_STORE_ADDR_0_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK) +/* HW_PXP_INPUT_STORE_ADDR_1_CH1 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK) +/* HW_PXP_INPUT_STORE_D_MASK0_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK0_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK1_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK1_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK2_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK2_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK3_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK3_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK4_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK4_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK5_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK5_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK6_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK6_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK7_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_MASK7_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK) +/* HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK 0x3Fu +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_MASK 0x40u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT 6 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK 0x80u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT 7 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK 0x3F00u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_MASK 0x4000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT 14 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK 0x8000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT 15 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK 0x3F0000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_MASK 0x400000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT 22 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK 0x800000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT 23 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK 0x3F000000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT 24 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_MASK 0x40000000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT 30 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK 0x80000000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT 31 +/* HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK 0x3Fu +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_MASK 0x40u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT 6 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK 0x80u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT 7 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK 0x3F00u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_MASK 0x4000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT 14 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK 0x8000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT 15 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK 0x3F0000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_MASK 0x400000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT 22 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK 0x800000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT 23 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK 0x3F000000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT 24 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_MASK 0x40000000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT 30 +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK 0x80000000u +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT 31 +/* HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK 0x3Fu +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK 0x40u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT 6 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_MASK 0x80u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT 7 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK 0x3F00u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK 0x4000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT 14 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_MASK 0x8000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT 15 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK 0x3F0000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK 0x400000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT 22 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_MASK 0x800000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT 23 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK 0x3F000000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT 24 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK 0x40000000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT 30 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_MASK 0x80000000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT 31 +/* HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK 0x3Fu +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK 0x40u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT 6 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_MASK 0x80u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT 7 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK 0x3F00u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK 0x4000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT 14 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_MASK 0x8000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT 15 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK 0x3F0000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK 0x400000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT 22 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_MASK 0x800000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT 23 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK 0x3F000000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT 24 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK 0x40000000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT 30 +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_MASK 0x80000000u +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT 31 +/* HW_PXP_INPUT_STORE_F_MASK_L_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_MASK 0xFFu +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK0_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_MASK 0xFF00u +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK1_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_MASK 0xFF0000u +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK2_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_MASK 0xFF000000u +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_SHIFT 24 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_F_MASK3_MASK) +/* HW_PXP_INPUT_STORE_F_MASK_H_CH0 Bit Fields */ +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_MASK 0xFFu +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_SHIFT 0 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK4_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_MASK 0xFF00u +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_SHIFT 8 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK5_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_MASK 0xFF0000u +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_SHIFT 16 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK6_MASK) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_MASK 0xFF000000u +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_SHIFT 24 +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_SHIFT))&PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_F_MASK7_MASK) +/* HW_PXP_DITHER_FETCH_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK 0x1u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_CH_EN_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_MASK 0x10u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_BYPASS_PIXEL_EN_SHIFT 4 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_MASK 0x20u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HIGH_BYTE_SHIFT 5 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_MASK 0x1C0u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_SHIFT 6 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD4_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HFLIP_MASK 0x200u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HFLIP_SHIFT 9 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_VFLIP_MASK 0x400u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_VFLIP_SHIFT 10 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD3_MASK 0x800u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD3_SHIFT 11 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK 0x3000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT 12 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ROTATION_ANGLE_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_MASK 0xC000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_SHIFT 14 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RD_NUM_BYTES_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_MASK 0xFC0000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_SHIFT 18 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_HANDSHAKE_SCAN_LINE_NUM_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_MASK 0x7C000000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_SHIFT 26 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_RSVD0_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_MASK 0x80000000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_ARBIT_EN_SHIFT 31 +/* HW_PXP_DITHER_FETCH_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK 0x1u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_CH_EN_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_MASK 0x10u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_BYPASS_PIXEL_EN_SHIFT 4 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_MASK 0x1E0u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_SHIFT 5 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD4_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HFLIP_MASK 0x200u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HFLIP_SHIFT 9 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_VFLIP_MASK 0x400u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_VFLIP_SHIFT 10 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD3_MASK 0x800u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD3_SHIFT 11 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK 0x3000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT 12 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_ROTATION_ANGLE_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_MASK 0xC000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_SHIFT 14 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RD_NUM_BYTES_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_MASK 0xFC0000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_SHIFT 18 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK 0x3000000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT 24 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_HANDSHAKE_SCAN_LINE_NUM_MASK) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_MASK 0xFC000000u +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_SHIFT 26 +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_DITHER_FETCH_STATUS_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_X_MASK) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_PREFETCH_BLOCK_Y_MASK) +/* HW_PXP_DITHER_FETCH_STATUS_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_X_MASK) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_PREFETCH_BLOCK_Y_MASK) +/* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_X_MASK) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_ACTIVE_SIZE_ULC_Y_MASK) +/* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_X_MASK) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_ACTIVE_SIZE_LRC_Y_MASK) +/* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_X_MASK) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_ACTIVE_SIZE_ULC_Y_MASK) +/* HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_X_MASK) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_ACTIVE_SIZE_LRC_Y_MASK) +/* HW_PXP_DITHER_FETCH_SIZE_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_WIDTH_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_INPUT_TOTAL_HEIGHT_MASK) +/* HW_PXP_DITHER_FETCH_SIZE_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_WIDTH_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_INPUT_TOTAL_HEIGHT_MASK) +/* HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_BACKGROUND_COLOR_MASK) +/* HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_SHIFT))&PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_BACKGROUND_COLOR_MASK) +/* HW_PXP_DITHER_FETCH_PITCH Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_PITCH_CH0_INPUT_PITCH_MASK) +#define PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_FETCH_PITCH_CH1_INPUT_PITCH_MASK) +/* HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK 0x3u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_INPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK 0xFCu +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT 2 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK 0x700u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT 8 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_FORMAT_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_MASK 0x800u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_EXPAND_EN_SHIFT 11 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x1000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 12 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFE000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT 13 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_RSVD0_MASK) +/* HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK 0x3u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_INPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK 0xFCu +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT 2 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK 0x700u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT 8 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_FORMAT_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_MASK 0x800u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_EXPAND_EN_SHIFT 11 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_MASK 0x1000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_SHIFT_BYPASS_SHIFT 12 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFE000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT 13 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK 0x1Fu +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET0_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK 0xE0u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT 5 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD3_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK 0x1F00u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT 8 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK 0xE000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT 13 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK 0x1F0000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK 0xE00000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT 21 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK 0x1F000000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT 24 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_OFFSET3_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK 0xE0000000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT 29 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_RSVD0_MASK) +/* HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK 0x1Fu +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET0_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK 0xE0u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT 5 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD3_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK 0x1F00u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT 8 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK 0xE000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT 13 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK 0x1F0000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK 0xE00000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT 21 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK 0x1F000000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT 24 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_OFFSET3_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK 0xE0000000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT 29 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_RSVD0_MASK) +/* HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK 0xFu +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH0_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK 0xF0u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT 4 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK 0xF00u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT 8 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK 0xF000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT 12 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_WIDTH3_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_RSVD0_MASK) +/* HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK 0xFu +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH0_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK 0xF0u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT 4 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH1_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK 0xF00u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT 8 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH2_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK 0xF000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT 12 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_WIDTH3_MASK) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT 16 +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_RSVD0_MASK) +/* HW_PXP_DITHER_FETCH_ADDR_0_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_INPUT_BASE_ADDR0_MASK) +/* HW_PXP_DITHER_FETCH_ADDR_1_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_INPUT_BASE_ADDR1_MASK) +/* HW_PXP_DITHER_FETCH_ADDR_0_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_INPUT_BASE_ADDR0_MASK) +/* HW_PXP_DITHER_FETCH_ADDR_1_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_INPUT_BASE_ADDR1_MASK) +/* HW_PXP_DITHER_STORE_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK 0x1u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_CH_EN_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_MASK 0x10u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_EN_SHIFT 4 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK 0x60u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT 5 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD3_MASK 0x80u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD3_SHIFT 7 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK 0x100u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK 0x200u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT 9 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_MASK 0x400u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT 10 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_MASK 0x800u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT 11 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_MASK 0xF000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_SHIFT 12 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD2_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_WR_NUM_BYTES_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_MASK 0xFC0000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_SHIFT 18 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK 0x1000000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT 24 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_MASK 0x7E000000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_SHIFT 25 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH0_RSVD0_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_MASK 0x80000000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_ARBIT_EN_SHIFT 31 +/* HW_PXP_DITHER_STORE_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK 0x1u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_CH_EN_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_MASK 0x2u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_EN_SHIFT 1 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_MASK 0x4u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_BLOCK_16_SHIFT 2 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_MASK 0x8u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT 3 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_MASK 0x10u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_EN_SHIFT 4 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK 0x60u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT 5 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD3_MASK 0x80u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD3_SHIFT 7 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK 0x100u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK 0x200u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT 9 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_MASK 0x400u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT 10 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_MASK 0xF800u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_SHIFT 11 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD1_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_MASK 0x30000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_WR_NUM_BYTES_MASK) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_MASK 0xFFFC0000u +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_SHIFT 18 +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_DITHER_STORE_STATUS_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_X_MASK) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK) +/* HW_PXP_DITHER_STORE_STATUS_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_X_MASK) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT))&PXP_HW_PXP_DITHER_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK) +/* HW_PXP_DITHER_STORE_SIZE_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK) +/* HW_PXP_DITHER_STORE_SIZE_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_WIDTH_MASK) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT))&PXP_HW_PXP_DITHER_STORE_SIZE_CH1_OUT_HEIGHT_MASK) +/* HW_PXP_DITHER_STORE_PITCH Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK 0xFFFFu +#define PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_STORE_PITCH_CH0_OUT_PITCH_MASK) +#define PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_MASK 0xFFFF0000u +#define PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_SHIFT))&PXP_HW_PXP_DITHER_STORE_PITCH_CH1_OUT_PITCH_MASK) +/* HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_MASK 0x3u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD2_MASK) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK 0xCu +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT 2 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK 0x10u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT 4 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK 0x20u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT 5 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_MASK 0x40u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD1_SHIFT 6 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK 0x80u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT 7 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_MASK 0xFFFFFF00u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_RSVD0_MASK) +/* HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_MASK 0x3u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD2_MASK) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK 0xCu +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT 2 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK 0x10u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT 4 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK 0x20u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT 5 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_MASK 0xFFFFFFC0u +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT 6 +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_RSVD0_MASK) +/* HW_PXP_DITHER_STORE_ADDR_0_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK) +/* HW_PXP_DITHER_STORE_ADDR_1_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK) +/* HW_PXP_DITHER_STORE_FILL_DATA_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK) +/* HW_PXP_DITHER_STORE_ADDR_0_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK) +/* HW_PXP_DITHER_STORE_ADDR_1_CH1 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT))&PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK) +/* HW_PXP_DITHER_STORE_D_MASK0_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK0_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK1_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK1_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK2_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK2_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK3_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK3_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK4_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK4_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK5_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK5_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK6_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK6_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK7_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_MASK7_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK) +/* HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK 0x3Fu +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_MASK 0x40u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD3_SHIFT 6 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK 0x80u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT 7 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK 0x3F00u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_MASK 0x4000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD2_SHIFT 14 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK 0x8000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT 15 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK 0x3F0000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_MASK 0x400000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD1_SHIFT 22 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK 0x800000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT 23 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK 0x3F000000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT 24 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_MASK 0x40000000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_RSVD0_SHIFT 30 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK 0x80000000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT 31 +/* HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK 0x3Fu +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_MASK 0x40u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD3_SHIFT 6 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK 0x80u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT 7 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK 0x3F00u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_MASK 0x4000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD2_SHIFT 14 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK 0x8000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT 15 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK 0x3F0000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_MASK 0x400000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD1_SHIFT 22 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK 0x800000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT 23 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK 0x3F000000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT 24 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_MASK 0x40000000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_RSVD0_SHIFT 30 +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK 0x80000000u +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT 31 +/* HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK 0x3Fu +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK 0x40u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT 6 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_MASK 0x80u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD3_SHIFT 7 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK 0x3F00u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK 0x4000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT 14 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_MASK 0x8000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD2_SHIFT 15 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK 0x3F0000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK 0x400000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT 22 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_MASK 0x800000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD1_SHIFT 23 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK 0x3F000000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT 24 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK 0x40000000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT 30 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_MASK 0x80000000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_RSVD0_SHIFT 31 +/* HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK 0x3Fu +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK 0x40u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT 6 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_MASK 0x80u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD3_SHIFT 7 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK 0x3F00u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK 0x4000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT 14 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_MASK 0x8000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD2_SHIFT 15 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK 0x3F0000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK 0x400000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT 22 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_MASK 0x800000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD1_SHIFT 23 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK 0x3F000000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT 24 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK 0x40000000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT 30 +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_MASK 0x80000000u +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_RSVD0_SHIFT 31 +/* HW_PXP_DITHER_STORE_F_MASK_L_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_MASK 0xFFu +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK0_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_MASK 0xFF00u +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK1_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_MASK 0xFF0000u +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK2_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_MASK 0xFF000000u +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_SHIFT 24 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_F_MASK3_MASK) +/* HW_PXP_DITHER_STORE_F_MASK_H_CH0 Bit Fields */ +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_MASK 0xFFu +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_SHIFT 0 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK4_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_MASK 0xFF00u +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_SHIFT 8 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK5_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_MASK 0xFF0000u +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_SHIFT 16 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK6_MASK) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_MASK 0xFF000000u +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_SHIFT 24 +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_SHIFT))&PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_F_MASK7_MASK) +/* HW_PXP_DITHER_CTRL Bit Fields */ +#define PXP_HW_PXP_DITHER_CTRL_ENABLE0_MASK 0x1u +#define PXP_HW_PXP_DITHER_CTRL_ENABLE0_SHIFT 0 +#define PXP_HW_PXP_DITHER_CTRL_ENABLE1_MASK 0x2u +#define PXP_HW_PXP_DITHER_CTRL_ENABLE1_SHIFT 1 +#define PXP_HW_PXP_DITHER_CTRL_ENABLE2_MASK 0x4u +#define PXP_HW_PXP_DITHER_CTRL_ENABLE2_SHIFT 2 +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_MASK 0x38u +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_SHIFT 3 +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_SHIFT))&PXP_HW_PXP_DITHER_CTRL_DITHER_MODE0_MASK) +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_MASK 0x1C0u +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_SHIFT 6 +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_SHIFT))&PXP_HW_PXP_DITHER_CTRL_DITHER_MODE1_MASK) +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_MASK 0xE00u +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_SHIFT 9 +#define PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_SHIFT))&PXP_HW_PXP_DITHER_CTRL_DITHER_MODE2_MASK) +#define PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK 0x7000u +#define PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT 12 +#define PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT))&PXP_HW_PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK) +#define PXP_HW_PXP_DITHER_CTRL_LUT_MODE_MASK 0x18000u +#define PXP_HW_PXP_DITHER_CTRL_LUT_MODE_SHIFT 15 +#define PXP_HW_PXP_DITHER_CTRL_LUT_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_LUT_MODE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_LUT_MODE_MASK) +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK 0x60000u +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT 17 +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK) +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK 0x180000u +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT 19 +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK) +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK 0x600000u +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT 21 +#define PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT))&PXP_HW_PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK) +#define PXP_HW_PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK 0x800000u +#define PXP_HW_PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT 23 +#define PXP_HW_PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK 0x1000000u +#define PXP_HW_PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT 24 +#define PXP_HW_PXP_DITHER_CTRL_RSVD0_MASK 0x1E000000u +#define PXP_HW_PXP_DITHER_CTRL_RSVD0_SHIFT 25 +#define PXP_HW_PXP_DITHER_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_DITHER_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_DITHER_CTRL_BUSY2_MASK 0x20000000u +#define PXP_HW_PXP_DITHER_CTRL_BUSY2_SHIFT 29 +#define PXP_HW_PXP_DITHER_CTRL_BUSY1_MASK 0x40000000u +#define PXP_HW_PXP_DITHER_CTRL_BUSY1_SHIFT 30 +#define PXP_HW_PXP_DITHER_CTRL_BUSY0_MASK 0x80000000u +#define PXP_HW_PXP_DITHER_CTRL_BUSY0_SHIFT 31 +/* HW_PXP_DITHER_FINAL_LUT_DATA0 Bit Fields */ +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK 0xFFu +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT 0 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK 0xFF00u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT 8 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK 0xFF0000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT 16 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK 0xFF000000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT 24 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK) +/* HW_PXP_DITHER_FINAL_LUT_DATA1 Bit Fields */ +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK 0xFFu +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT 0 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK 0xFF00u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT 8 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK 0xFF0000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT 16 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK 0xFF000000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT 24 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK) +/* HW_PXP_DITHER_FINAL_LUT_DATA2 Bit Fields */ +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK 0xFFu +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT 0 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK 0xFF00u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT 8 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK 0xFF0000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT 16 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK 0xFF000000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT 24 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK) +/* HW_PXP_DITHER_FINAL_LUT_DATA3 Bit Fields */ +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK 0xFFu +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT 0 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK 0xFF00u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT 8 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK 0xFF0000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT 16 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK 0xFF000000u +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT 24 +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT))&PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK) +/* HW_PXP_HIST_A_CTRL Bit Fields */ +#define PXP_HW_PXP_HIST_A_CTRL_ENABLE_MASK 0x1u +#define PXP_HW_PXP_HIST_A_CTRL_ENABLE_SHIFT 0 +#define PXP_HW_PXP_HIST_A_CTRL_RSVD0_MASK 0xEu +#define PXP_HW_PXP_HIST_A_CTRL_RSVD0_SHIFT 1 +#define PXP_HW_PXP_HIST_A_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_HIST_A_CTRL_CLEAR_MASK 0x10u +#define PXP_HW_PXP_HIST_A_CTRL_CLEAR_SHIFT 4 +#define PXP_HW_PXP_HIST_A_CTRL_RSVD1_MASK 0xE0u +#define PXP_HW_PXP_HIST_A_CTRL_RSVD1_SHIFT 5 +#define PXP_HW_PXP_HIST_A_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD1_MASK) +#define PXP_HW_PXP_HIST_A_CTRL_STATUS_MASK 0x1F00u +#define PXP_HW_PXP_HIST_A_CTRL_STATUS_SHIFT 8 +#define PXP_HW_PXP_HIST_A_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_STATUS_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_STATUS_MASK) +#define PXP_HW_PXP_HIST_A_CTRL_RSVD2_MASK 0xE000u +#define PXP_HW_PXP_HIST_A_CTRL_RSVD2_SHIFT 13 +#define PXP_HW_PXP_HIST_A_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD2_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD2_MASK) +#define PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK 0x7F0000u +#define PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT 16 +#define PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HW_PXP_HIST_A_CTRL_RSVD3_MASK 0x800000u +#define PXP_HW_PXP_HIST_A_CTRL_RSVD3_SHIFT 23 +#define PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK 0x7000000u +#define PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT 24 +#define PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK) +#define PXP_HW_PXP_HIST_A_CTRL_RSVD4_MASK 0xF8000000u +#define PXP_HW_PXP_HIST_A_CTRL_RSVD4_SHIFT 27 +#define PXP_HW_PXP_HIST_A_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_CTRL_RSVD4_SHIFT))&PXP_HW_PXP_HIST_A_CTRL_RSVD4_MASK) +/* HW_PXP_HIST_A_MASK Bit Fields */ +#define PXP_HW_PXP_HIST_A_MASK_MASK_EN_MASK 0x1u +#define PXP_HW_PXP_HIST_A_MASK_MASK_EN_SHIFT 0 +#define PXP_HW_PXP_HIST_A_MASK_RSVD0_MASK 0xEu +#define PXP_HW_PXP_HIST_A_MASK_RSVD0_SHIFT 1 +#define PXP_HW_PXP_HIST_A_MASK_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_MASK_RSVD0_MASK) +#define PXP_HW_PXP_HIST_A_MASK_MASK_MODE_MASK 0x30u +#define PXP_HW_PXP_HIST_A_MASK_MASK_MODE_SHIFT 4 +#define PXP_HW_PXP_HIST_A_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_MODE_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_MODE_MASK) +#define PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_MASK 0x1FC0u +#define PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_SHIFT 6 +#define PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_OFFSET_MASK) +#define PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_MASK 0xE000u +#define PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_SHIFT 13 +#define PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_WIDTH_MASK) +#define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_MASK 0xFF0000u +#define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_SHIFT 16 +#define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_VALUE0_MASK) +#define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_MASK 0xFF000000u +#define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_SHIFT 24 +#define PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_SHIFT))&PXP_HW_PXP_HIST_A_MASK_MASK_VALUE1_MASK) +/* HW_PXP_HIST_A_BUF_SIZE Bit Fields */ +#define PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_MASK 0xFFFu +#define PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT 0 +#define PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_WIDTH_MASK) +#define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_MASK 0xF000u +#define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_SHIFT 12 +#define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD1_MASK) +#define PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_MASK 0xFFF0000u +#define PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_HEIGHT_MASK) +#define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_MASK 0xF0000000u +#define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_SHIFT 28 +#define PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_BUF_SIZE_RSVD0_MASK) +/* HW_PXP_HIST_A_TOTAL_PIXEL Bit Fields */ +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT 0 +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT))&PXP_HW_PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK) +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_MASK 0xFF000000u +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_SHIFT 24 +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_TOTAL_PIXEL_RSVD0_MASK) +/* HW_PXP_HIST_A_ACTIVE_AREA_X Bit Fields */ +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK 0xFFFu +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT 0 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_MASK 0xF000u +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_SHIFT 12 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD0_MASK) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK 0xFFF0000u +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT 16 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_MASK 0xF0000000u +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_SHIFT 28 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_RSVD1_MASK) +/* HW_PXP_HIST_A_ACTIVE_AREA_Y Bit Fields */ +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK 0xFFFu +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT 0 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_MASK 0xF000u +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_SHIFT 12 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD0_MASK) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK 0xFFF0000u +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT 16 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_MASK 0xF0000000u +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_SHIFT 28 +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_SHIFT))&PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_RSVD1_MASK) +/* HW_PXP_HIST_A_RAW_STAT0 Bit Fields */ +#define PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_SHIFT 0 +#define PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_SHIFT))&PXP_HW_PXP_HIST_A_RAW_STAT0_STAT0_MASK) +/* HW_PXP_HIST_A_RAW_STAT1 Bit Fields */ +#define PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_SHIFT 0 +#define PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_SHIFT))&PXP_HW_PXP_HIST_A_RAW_STAT1_STAT1_MASK) +/* HW_PXP_HIST_B_CTRL Bit Fields */ +#define PXP_HW_PXP_HIST_B_CTRL_ENABLE_MASK 0x1u +#define PXP_HW_PXP_HIST_B_CTRL_ENABLE_SHIFT 0 +#define PXP_HW_PXP_HIST_B_CTRL_RSVD0_MASK 0xEu +#define PXP_HW_PXP_HIST_B_CTRL_RSVD0_SHIFT 1 +#define PXP_HW_PXP_HIST_B_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD0_MASK) +#define PXP_HW_PXP_HIST_B_CTRL_CLEAR_MASK 0x10u +#define PXP_HW_PXP_HIST_B_CTRL_CLEAR_SHIFT 4 +#define PXP_HW_PXP_HIST_B_CTRL_RSVD1_MASK 0xE0u +#define PXP_HW_PXP_HIST_B_CTRL_RSVD1_SHIFT 5 +#define PXP_HW_PXP_HIST_B_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD1_MASK) +#define PXP_HW_PXP_HIST_B_CTRL_STATUS_MASK 0x1F00u +#define PXP_HW_PXP_HIST_B_CTRL_STATUS_SHIFT 8 +#define PXP_HW_PXP_HIST_B_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_STATUS_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_STATUS_MASK) +#define PXP_HW_PXP_HIST_B_CTRL_RSVD2_MASK 0xE000u +#define PXP_HW_PXP_HIST_B_CTRL_RSVD2_SHIFT 13 +#define PXP_HW_PXP_HIST_B_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD2_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD2_MASK) +#define PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK 0x7F0000u +#define PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT 16 +#define PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HW_PXP_HIST_B_CTRL_RSVD3_MASK 0x800000u +#define PXP_HW_PXP_HIST_B_CTRL_RSVD3_SHIFT 23 +#define PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK 0x7000000u +#define PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT 24 +#define PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK) +#define PXP_HW_PXP_HIST_B_CTRL_RSVD4_MASK 0xF8000000u +#define PXP_HW_PXP_HIST_B_CTRL_RSVD4_SHIFT 27 +#define PXP_HW_PXP_HIST_B_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_CTRL_RSVD4_SHIFT))&PXP_HW_PXP_HIST_B_CTRL_RSVD4_MASK) +/* HW_PXP_HIST_B_MASK Bit Fields */ +#define PXP_HW_PXP_HIST_B_MASK_MASK_EN_MASK 0x1u +#define PXP_HW_PXP_HIST_B_MASK_MASK_EN_SHIFT 0 +#define PXP_HW_PXP_HIST_B_MASK_RSVD0_MASK 0xEu +#define PXP_HW_PXP_HIST_B_MASK_RSVD0_SHIFT 1 +#define PXP_HW_PXP_HIST_B_MASK_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_MASK_RSVD0_MASK) +#define PXP_HW_PXP_HIST_B_MASK_MASK_MODE_MASK 0x30u +#define PXP_HW_PXP_HIST_B_MASK_MASK_MODE_SHIFT 4 +#define PXP_HW_PXP_HIST_B_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_MODE_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_MODE_MASK) +#define PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_MASK 0x1FC0u +#define PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_SHIFT 6 +#define PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_OFFSET_MASK) +#define PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_MASK 0xE000u +#define PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_SHIFT 13 +#define PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_WIDTH_MASK) +#define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_MASK 0xFF0000u +#define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_SHIFT 16 +#define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_VALUE0_MASK) +#define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_MASK 0xFF000000u +#define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_SHIFT 24 +#define PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_SHIFT))&PXP_HW_PXP_HIST_B_MASK_MASK_VALUE1_MASK) +/* HW_PXP_HIST_B_BUF_SIZE Bit Fields */ +#define PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_MASK 0xFFFu +#define PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT 0 +#define PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_WIDTH_MASK) +#define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_MASK 0xF000u +#define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_SHIFT 12 +#define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD1_MASK) +#define PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_MASK 0xFFF0000u +#define PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT 16 +#define PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_HEIGHT_MASK) +#define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_MASK 0xF0000000u +#define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_SHIFT 28 +#define PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_BUF_SIZE_RSVD0_MASK) +/* HW_PXP_HIST_B_TOTAL_PIXEL Bit Fields */ +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK 0xFFFFFFu +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT 0 +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT))&PXP_HW_PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK) +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_MASK 0xFF000000u +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_SHIFT 24 +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_TOTAL_PIXEL_RSVD0_MASK) +/* HW_PXP_HIST_B_ACTIVE_AREA_X Bit Fields */ +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK 0xFFFu +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT 0 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_MASK 0xF000u +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_SHIFT 12 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD0_MASK) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK 0xFFF0000u +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT 16 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_MASK 0xF0000000u +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_SHIFT 28 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_RSVD1_MASK) +/* HW_PXP_HIST_B_ACTIVE_AREA_Y Bit Fields */ +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK 0xFFFu +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT 0 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_MASK 0xF000u +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_SHIFT 12 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD0_MASK) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK 0xFFF0000u +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT 16 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_MASK 0xF0000000u +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_SHIFT 28 +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_SHIFT))&PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_RSVD1_MASK) +/* HW_PXP_HIST_B_RAW_STAT0 Bit Fields */ +#define PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_SHIFT 0 +#define PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_SHIFT))&PXP_HW_PXP_HIST_B_RAW_STAT0_STAT0_MASK) +/* HW_PXP_HIST_B_RAW_STAT1 Bit Fields */ +#define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_SHIFT 0 +#define PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_SHIFT))&PXP_HW_PXP_HIST_B_RAW_STAT1_STAT1_MASK) +/* HIST2_PARAM Bit Fields */ +#define PXP_HIST2_PARAM_VALUE0_MASK 0x3Fu +#define PXP_HIST2_PARAM_VALUE0_SHIFT 0 +#define PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE0_SHIFT))&PXP_HIST2_PARAM_VALUE0_MASK) +#define PXP_HIST2_PARAM_RSVD0_MASK 0xC0u +#define PXP_HIST2_PARAM_RSVD0_SHIFT 6 +#define PXP_HIST2_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD0_SHIFT))&PXP_HIST2_PARAM_RSVD0_MASK) +#define PXP_HIST2_PARAM_VALUE1_MASK 0x3F00u +#define PXP_HIST2_PARAM_VALUE1_SHIFT 8 +#define PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_VALUE1_SHIFT))&PXP_HIST2_PARAM_VALUE1_MASK) +#define PXP_HIST2_PARAM_RSVD1_MASK 0xC000u +#define PXP_HIST2_PARAM_RSVD1_SHIFT 14 +#define PXP_HIST2_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD1_SHIFT))&PXP_HIST2_PARAM_RSVD1_MASK) +#define PXP_HIST2_PARAM_RSVD_MASK 0xFFFF0000u +#define PXP_HIST2_PARAM_RSVD_SHIFT 16 +#define PXP_HIST2_PARAM_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST2_PARAM_RSVD_SHIFT))&PXP_HIST2_PARAM_RSVD_MASK) +/* HIST4_PARAM Bit Fields */ +#define PXP_HIST4_PARAM_VALUE0_MASK 0x3Fu +#define PXP_HIST4_PARAM_VALUE0_SHIFT 0 +#define PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE0_SHIFT))&PXP_HIST4_PARAM_VALUE0_MASK) +#define PXP_HIST4_PARAM_RSVD0_MASK 0xC0u +#define PXP_HIST4_PARAM_RSVD0_SHIFT 6 +#define PXP_HIST4_PARAM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD0_SHIFT))&PXP_HIST4_PARAM_RSVD0_MASK) +#define PXP_HIST4_PARAM_VALUE1_MASK 0x3F00u +#define PXP_HIST4_PARAM_VALUE1_SHIFT 8 +#define PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE1_SHIFT))&PXP_HIST4_PARAM_VALUE1_MASK) +#define PXP_HIST4_PARAM_RSVD1_MASK 0xC000u +#define PXP_HIST4_PARAM_RSVD1_SHIFT 14 +#define PXP_HIST4_PARAM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD1_SHIFT))&PXP_HIST4_PARAM_RSVD1_MASK) +#define PXP_HIST4_PARAM_VALUE2_MASK 0x3F0000u +#define PXP_HIST4_PARAM_VALUE2_SHIFT 16 +#define PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE2_SHIFT))&PXP_HIST4_PARAM_VALUE2_MASK) +#define PXP_HIST4_PARAM_RSVD2_MASK 0xC00000u +#define PXP_HIST4_PARAM_RSVD2_SHIFT 22 +#define PXP_HIST4_PARAM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD2_SHIFT))&PXP_HIST4_PARAM_RSVD2_MASK) +#define PXP_HIST4_PARAM_VALUE3_MASK 0x3F000000u +#define PXP_HIST4_PARAM_VALUE3_SHIFT 24 +#define PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_VALUE3_SHIFT))&PXP_HIST4_PARAM_VALUE3_MASK) +#define PXP_HIST4_PARAM_RSVD3_MASK 0xC0000000u +#define PXP_HIST4_PARAM_RSVD3_SHIFT 30 +#define PXP_HIST4_PARAM_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST4_PARAM_RSVD3_SHIFT))&PXP_HIST4_PARAM_RSVD3_MASK) +/* HIST8_PARAM0 Bit Fields */ +#define PXP_HIST8_PARAM0_VALUE0_MASK 0x3Fu +#define PXP_HIST8_PARAM0_VALUE0_SHIFT 0 +#define PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE0_SHIFT))&PXP_HIST8_PARAM0_VALUE0_MASK) +#define PXP_HIST8_PARAM0_RSVD0_MASK 0xC0u +#define PXP_HIST8_PARAM0_RSVD0_SHIFT 6 +#define PXP_HIST8_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD0_SHIFT))&PXP_HIST8_PARAM0_RSVD0_MASK) +#define PXP_HIST8_PARAM0_VALUE1_MASK 0x3F00u +#define PXP_HIST8_PARAM0_VALUE1_SHIFT 8 +#define PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE1_SHIFT))&PXP_HIST8_PARAM0_VALUE1_MASK) +#define PXP_HIST8_PARAM0_RSVD1_MASK 0xC000u +#define PXP_HIST8_PARAM0_RSVD1_SHIFT 14 +#define PXP_HIST8_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD1_SHIFT))&PXP_HIST8_PARAM0_RSVD1_MASK) +#define PXP_HIST8_PARAM0_VALUE2_MASK 0x3F0000u +#define PXP_HIST8_PARAM0_VALUE2_SHIFT 16 +#define PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE2_SHIFT))&PXP_HIST8_PARAM0_VALUE2_MASK) +#define PXP_HIST8_PARAM0_RSVD2_MASK 0xC00000u +#define PXP_HIST8_PARAM0_RSVD2_SHIFT 22 +#define PXP_HIST8_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD2_SHIFT))&PXP_HIST8_PARAM0_RSVD2_MASK) +#define PXP_HIST8_PARAM0_VALUE3_MASK 0x3F000000u +#define PXP_HIST8_PARAM0_VALUE3_SHIFT 24 +#define PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_VALUE3_SHIFT))&PXP_HIST8_PARAM0_VALUE3_MASK) +#define PXP_HIST8_PARAM0_RSVD3_MASK 0xC0000000u +#define PXP_HIST8_PARAM0_RSVD3_SHIFT 30 +#define PXP_HIST8_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM0_RSVD3_SHIFT))&PXP_HIST8_PARAM0_RSVD3_MASK) +/* HIST8_PARAM1 Bit Fields */ +#define PXP_HIST8_PARAM1_VALUE4_MASK 0x3Fu +#define PXP_HIST8_PARAM1_VALUE4_SHIFT 0 +#define PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE4_SHIFT))&PXP_HIST8_PARAM1_VALUE4_MASK) +#define PXP_HIST8_PARAM1_RSVD4_MASK 0xC0u +#define PXP_HIST8_PARAM1_RSVD4_SHIFT 6 +#define PXP_HIST8_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD4_SHIFT))&PXP_HIST8_PARAM1_RSVD4_MASK) +#define PXP_HIST8_PARAM1_VALUE5_MASK 0x3F00u +#define PXP_HIST8_PARAM1_VALUE5_SHIFT 8 +#define PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE5_SHIFT))&PXP_HIST8_PARAM1_VALUE5_MASK) +#define PXP_HIST8_PARAM1_RSVD5_MASK 0xC000u +#define PXP_HIST8_PARAM1_RSVD5_SHIFT 14 +#define PXP_HIST8_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD5_SHIFT))&PXP_HIST8_PARAM1_RSVD5_MASK) +#define PXP_HIST8_PARAM1_VALUE6_MASK 0x3F0000u +#define PXP_HIST8_PARAM1_VALUE6_SHIFT 16 +#define PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE6_SHIFT))&PXP_HIST8_PARAM1_VALUE6_MASK) +#define PXP_HIST8_PARAM1_RSVD6_MASK 0xC00000u +#define PXP_HIST8_PARAM1_RSVD6_SHIFT 22 +#define PXP_HIST8_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD6_SHIFT))&PXP_HIST8_PARAM1_RSVD6_MASK) +#define PXP_HIST8_PARAM1_VALUE7_MASK 0x3F000000u +#define PXP_HIST8_PARAM1_VALUE7_SHIFT 24 +#define PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_VALUE7_SHIFT))&PXP_HIST8_PARAM1_VALUE7_MASK) +#define PXP_HIST8_PARAM1_RSVD7_MASK 0xC0000000u +#define PXP_HIST8_PARAM1_RSVD7_SHIFT 30 +#define PXP_HIST8_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST8_PARAM1_RSVD7_SHIFT))&PXP_HIST8_PARAM1_RSVD7_MASK) +/* HIST16_PARAM0 Bit Fields */ +#define PXP_HIST16_PARAM0_VALUE0_MASK 0x3Fu +#define PXP_HIST16_PARAM0_VALUE0_SHIFT 0 +#define PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE0_SHIFT))&PXP_HIST16_PARAM0_VALUE0_MASK) +#define PXP_HIST16_PARAM0_RSVD0_MASK 0xC0u +#define PXP_HIST16_PARAM0_RSVD0_SHIFT 6 +#define PXP_HIST16_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD0_SHIFT))&PXP_HIST16_PARAM0_RSVD0_MASK) +#define PXP_HIST16_PARAM0_VALUE1_MASK 0x3F00u +#define PXP_HIST16_PARAM0_VALUE1_SHIFT 8 +#define PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE1_SHIFT))&PXP_HIST16_PARAM0_VALUE1_MASK) +#define PXP_HIST16_PARAM0_RSVD1_MASK 0xC000u +#define PXP_HIST16_PARAM0_RSVD1_SHIFT 14 +#define PXP_HIST16_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD1_SHIFT))&PXP_HIST16_PARAM0_RSVD1_MASK) +#define PXP_HIST16_PARAM0_VALUE2_MASK 0x3F0000u +#define PXP_HIST16_PARAM0_VALUE2_SHIFT 16 +#define PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE2_SHIFT))&PXP_HIST16_PARAM0_VALUE2_MASK) +#define PXP_HIST16_PARAM0_RSVD2_MASK 0xC00000u +#define PXP_HIST16_PARAM0_RSVD2_SHIFT 22 +#define PXP_HIST16_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD2_SHIFT))&PXP_HIST16_PARAM0_RSVD2_MASK) +#define PXP_HIST16_PARAM0_VALUE3_MASK 0x3F000000u +#define PXP_HIST16_PARAM0_VALUE3_SHIFT 24 +#define PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_VALUE3_SHIFT))&PXP_HIST16_PARAM0_VALUE3_MASK) +#define PXP_HIST16_PARAM0_RSVD3_MASK 0xC0000000u +#define PXP_HIST16_PARAM0_RSVD3_SHIFT 30 +#define PXP_HIST16_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM0_RSVD3_SHIFT))&PXP_HIST16_PARAM0_RSVD3_MASK) +/* HIST16_PARAM1 Bit Fields */ +#define PXP_HIST16_PARAM1_VALUE4_MASK 0x3Fu +#define PXP_HIST16_PARAM1_VALUE4_SHIFT 0 +#define PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE4_SHIFT))&PXP_HIST16_PARAM1_VALUE4_MASK) +#define PXP_HIST16_PARAM1_RSVD4_MASK 0xC0u +#define PXP_HIST16_PARAM1_RSVD4_SHIFT 6 +#define PXP_HIST16_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD4_SHIFT))&PXP_HIST16_PARAM1_RSVD4_MASK) +#define PXP_HIST16_PARAM1_VALUE5_MASK 0x3F00u +#define PXP_HIST16_PARAM1_VALUE5_SHIFT 8 +#define PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE5_SHIFT))&PXP_HIST16_PARAM1_VALUE5_MASK) +#define PXP_HIST16_PARAM1_RSVD5_MASK 0xC000u +#define PXP_HIST16_PARAM1_RSVD5_SHIFT 14 +#define PXP_HIST16_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD5_SHIFT))&PXP_HIST16_PARAM1_RSVD5_MASK) +#define PXP_HIST16_PARAM1_VALUE6_MASK 0x3F0000u +#define PXP_HIST16_PARAM1_VALUE6_SHIFT 16 +#define PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE6_SHIFT))&PXP_HIST16_PARAM1_VALUE6_MASK) +#define PXP_HIST16_PARAM1_RSVD6_MASK 0xC00000u +#define PXP_HIST16_PARAM1_RSVD6_SHIFT 22 +#define PXP_HIST16_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD6_SHIFT))&PXP_HIST16_PARAM1_RSVD6_MASK) +#define PXP_HIST16_PARAM1_VALUE7_MASK 0x3F000000u +#define PXP_HIST16_PARAM1_VALUE7_SHIFT 24 +#define PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_VALUE7_SHIFT))&PXP_HIST16_PARAM1_VALUE7_MASK) +#define PXP_HIST16_PARAM1_RSVD7_MASK 0xC0000000u +#define PXP_HIST16_PARAM1_RSVD7_SHIFT 30 +#define PXP_HIST16_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM1_RSVD7_SHIFT))&PXP_HIST16_PARAM1_RSVD7_MASK) +/* HIST16_PARAM2 Bit Fields */ +#define PXP_HIST16_PARAM2_VALUE8_MASK 0x3Fu +#define PXP_HIST16_PARAM2_VALUE8_SHIFT 0 +#define PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE8_SHIFT))&PXP_HIST16_PARAM2_VALUE8_MASK) +#define PXP_HIST16_PARAM2_RSVD8_MASK 0xC0u +#define PXP_HIST16_PARAM2_RSVD8_SHIFT 6 +#define PXP_HIST16_PARAM2_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD8_SHIFT))&PXP_HIST16_PARAM2_RSVD8_MASK) +#define PXP_HIST16_PARAM2_VALUE9_MASK 0x3F00u +#define PXP_HIST16_PARAM2_VALUE9_SHIFT 8 +#define PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE9_SHIFT))&PXP_HIST16_PARAM2_VALUE9_MASK) +#define PXP_HIST16_PARAM2_RSVD9_MASK 0xC000u +#define PXP_HIST16_PARAM2_RSVD9_SHIFT 14 +#define PXP_HIST16_PARAM2_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD9_SHIFT))&PXP_HIST16_PARAM2_RSVD9_MASK) +#define PXP_HIST16_PARAM2_VALUE10_MASK 0x3F0000u +#define PXP_HIST16_PARAM2_VALUE10_SHIFT 16 +#define PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE10_SHIFT))&PXP_HIST16_PARAM2_VALUE10_MASK) +#define PXP_HIST16_PARAM2_RSVD10_MASK 0xC00000u +#define PXP_HIST16_PARAM2_RSVD10_SHIFT 22 +#define PXP_HIST16_PARAM2_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD10_SHIFT))&PXP_HIST16_PARAM2_RSVD10_MASK) +#define PXP_HIST16_PARAM2_VALUE11_MASK 0x3F000000u +#define PXP_HIST16_PARAM2_VALUE11_SHIFT 24 +#define PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_VALUE11_SHIFT))&PXP_HIST16_PARAM2_VALUE11_MASK) +#define PXP_HIST16_PARAM2_RSVD11_MASK 0xC0000000u +#define PXP_HIST16_PARAM2_RSVD11_SHIFT 30 +#define PXP_HIST16_PARAM2_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM2_RSVD11_SHIFT))&PXP_HIST16_PARAM2_RSVD11_MASK) +/* HIST16_PARAM3 Bit Fields */ +#define PXP_HIST16_PARAM3_VALUE12_MASK 0x3Fu +#define PXP_HIST16_PARAM3_VALUE12_SHIFT 0 +#define PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE12_SHIFT))&PXP_HIST16_PARAM3_VALUE12_MASK) +#define PXP_HIST16_PARAM3_RSVD12_MASK 0xC0u +#define PXP_HIST16_PARAM3_RSVD12_SHIFT 6 +#define PXP_HIST16_PARAM3_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD12_SHIFT))&PXP_HIST16_PARAM3_RSVD12_MASK) +#define PXP_HIST16_PARAM3_VALUE13_MASK 0x3F00u +#define PXP_HIST16_PARAM3_VALUE13_SHIFT 8 +#define PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE13_SHIFT))&PXP_HIST16_PARAM3_VALUE13_MASK) +#define PXP_HIST16_PARAM3_RSVD13_MASK 0xC000u +#define PXP_HIST16_PARAM3_RSVD13_SHIFT 14 +#define PXP_HIST16_PARAM3_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD13_SHIFT))&PXP_HIST16_PARAM3_RSVD13_MASK) +#define PXP_HIST16_PARAM3_VALUE14_MASK 0x3F0000u +#define PXP_HIST16_PARAM3_VALUE14_SHIFT 16 +#define PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE14_SHIFT))&PXP_HIST16_PARAM3_VALUE14_MASK) +#define PXP_HIST16_PARAM3_RSVD14_MASK 0xC00000u +#define PXP_HIST16_PARAM3_RSVD14_SHIFT 22 +#define PXP_HIST16_PARAM3_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD14_SHIFT))&PXP_HIST16_PARAM3_RSVD14_MASK) +#define PXP_HIST16_PARAM3_VALUE15_MASK 0x3F000000u +#define PXP_HIST16_PARAM3_VALUE15_SHIFT 24 +#define PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_VALUE15_SHIFT))&PXP_HIST16_PARAM3_VALUE15_MASK) +#define PXP_HIST16_PARAM3_RSVD15_MASK 0xC0000000u +#define PXP_HIST16_PARAM3_RSVD15_SHIFT 30 +#define PXP_HIST16_PARAM3_RSVD15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HIST16_PARAM3_RSVD15_SHIFT))&PXP_HIST16_PARAM3_RSVD15_MASK) +/* HW_PXP_HIST32_PARAM0 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM0_VALUE0_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM0_VALUE0_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE0_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE0_MASK) +#define PXP_HW_PXP_HIST32_PARAM0_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM0_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD0_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD0_MASK) +#define PXP_HW_PXP_HIST32_PARAM0_VALUE1_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM0_VALUE1_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE1_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE1_MASK) +#define PXP_HW_PXP_HIST32_PARAM0_RSVD1_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM0_RSVD1_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD1_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD1_MASK) +#define PXP_HW_PXP_HIST32_PARAM0_VALUE2_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM0_VALUE2_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE2_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE2_MASK) +#define PXP_HW_PXP_HIST32_PARAM0_RSVD2_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM0_RSVD2_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD2_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD2_MASK) +#define PXP_HW_PXP_HIST32_PARAM0_VALUE3_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM0_VALUE3_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_VALUE3_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_VALUE3_MASK) +#define PXP_HW_PXP_HIST32_PARAM0_RSVD3_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM0_RSVD3_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM0_RSVD3_SHIFT))&PXP_HW_PXP_HIST32_PARAM0_RSVD3_MASK) +/* HW_PXP_HIST32_PARAM1 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM1_VALUE4_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM1_VALUE4_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE4_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE4_MASK) +#define PXP_HW_PXP_HIST32_PARAM1_RSVD4_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM1_RSVD4_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM1_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD4_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD4_MASK) +#define PXP_HW_PXP_HIST32_PARAM1_VALUE5_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM1_VALUE5_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE5_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE5_MASK) +#define PXP_HW_PXP_HIST32_PARAM1_RSVD5_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM1_RSVD5_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM1_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD5_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD5_MASK) +#define PXP_HW_PXP_HIST32_PARAM1_VALUE6_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM1_VALUE6_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE6_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE6_MASK) +#define PXP_HW_PXP_HIST32_PARAM1_RSVD6_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM1_RSVD6_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM1_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD6_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD6_MASK) +#define PXP_HW_PXP_HIST32_PARAM1_VALUE7_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM1_VALUE7_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_VALUE7_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_VALUE7_MASK) +#define PXP_HW_PXP_HIST32_PARAM1_RSVD7_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM1_RSVD7_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM1_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM1_RSVD7_SHIFT))&PXP_HW_PXP_HIST32_PARAM1_RSVD7_MASK) +/* HW_PXP_HIST32_PARAM2 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM2_VALUE8_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM2_VALUE8_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE8_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE8_MASK) +#define PXP_HW_PXP_HIST32_PARAM2_RSVD8_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM2_RSVD8_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM2_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD8_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD8_MASK) +#define PXP_HW_PXP_HIST32_PARAM2_VALUE9_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM2_VALUE9_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE9_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE9_MASK) +#define PXP_HW_PXP_HIST32_PARAM2_RSVD9_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM2_RSVD9_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM2_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD9_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD9_MASK) +#define PXP_HW_PXP_HIST32_PARAM2_VALUE10_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM2_VALUE10_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE10_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE10_MASK) +#define PXP_HW_PXP_HIST32_PARAM2_RSVD10_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM2_RSVD10_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM2_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD10_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD10_MASK) +#define PXP_HW_PXP_HIST32_PARAM2_VALUE11_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM2_VALUE11_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_VALUE11_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_VALUE11_MASK) +#define PXP_HW_PXP_HIST32_PARAM2_RSVD11_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM2_RSVD11_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM2_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM2_RSVD11_SHIFT))&PXP_HW_PXP_HIST32_PARAM2_RSVD11_MASK) +/* HW_PXP_HIST32_PARAM3 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM3_VALUE12_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM3_VALUE12_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE12_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE12_MASK) +#define PXP_HW_PXP_HIST32_PARAM3_RSVD12_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM3_RSVD12_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM3_RSVD12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD12_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD12_MASK) +#define PXP_HW_PXP_HIST32_PARAM3_VALUE13_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM3_VALUE13_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE13_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE13_MASK) +#define PXP_HW_PXP_HIST32_PARAM3_RSVD13_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM3_RSVD13_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM3_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD13_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD13_MASK) +#define PXP_HW_PXP_HIST32_PARAM3_VALUE14_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM3_VALUE14_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE14_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE14_MASK) +#define PXP_HW_PXP_HIST32_PARAM3_RSVD14_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM3_RSVD14_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM3_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD14_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD14_MASK) +#define PXP_HW_PXP_HIST32_PARAM3_VALUE15_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM3_VALUE15_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_VALUE15_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_VALUE15_MASK) +#define PXP_HW_PXP_HIST32_PARAM3_RSVD15_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM3_RSVD15_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM3_RSVD15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM3_RSVD15_SHIFT))&PXP_HW_PXP_HIST32_PARAM3_RSVD15_MASK) +/* HW_PXP_HIST32_PARAM4 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM4_VALUE16_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM4_VALUE16_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM4_VALUE16(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE16_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE16_MASK) +#define PXP_HW_PXP_HIST32_PARAM4_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM4_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM4_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD0_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD0_MASK) +#define PXP_HW_PXP_HIST32_PARAM4_VALUE17_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM4_VALUE17_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM4_VALUE17(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE17_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE17_MASK) +#define PXP_HW_PXP_HIST32_PARAM4_RSVD1_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM4_RSVD1_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM4_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD1_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD1_MASK) +#define PXP_HW_PXP_HIST32_PARAM4_VALUE18_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM4_VALUE18_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM4_VALUE18(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE18_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE18_MASK) +#define PXP_HW_PXP_HIST32_PARAM4_RSVD2_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM4_RSVD2_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM4_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD2_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD2_MASK) +#define PXP_HW_PXP_HIST32_PARAM4_VALUE19_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM4_VALUE19_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM4_VALUE19(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_VALUE19_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_VALUE19_MASK) +#define PXP_HW_PXP_HIST32_PARAM4_RSVD3_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM4_RSVD3_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM4_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM4_RSVD3_SHIFT))&PXP_HW_PXP_HIST32_PARAM4_RSVD3_MASK) +/* HW_PXP_HIST32_PARAM5 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM5_VALUE20_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM5_VALUE20_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM5_VALUE20(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE20_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE20_MASK) +#define PXP_HW_PXP_HIST32_PARAM5_RSVD4_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM5_RSVD4_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM5_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD4_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD4_MASK) +#define PXP_HW_PXP_HIST32_PARAM5_VALUE21_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM5_VALUE21_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM5_VALUE21(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE21_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE21_MASK) +#define PXP_HW_PXP_HIST32_PARAM5_RSVD5_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM5_RSVD5_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM5_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD5_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD5_MASK) +#define PXP_HW_PXP_HIST32_PARAM5_VALUE22_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM5_VALUE22_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM5_VALUE22(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE22_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE22_MASK) +#define PXP_HW_PXP_HIST32_PARAM5_RSVD6_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM5_RSVD6_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM5_RSVD6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD6_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD6_MASK) +#define PXP_HW_PXP_HIST32_PARAM5_VALUE23_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM5_VALUE23_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM5_VALUE23(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_VALUE23_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_VALUE23_MASK) +#define PXP_HW_PXP_HIST32_PARAM5_RSVD7_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM5_RSVD7_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM5_RSVD7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM5_RSVD7_SHIFT))&PXP_HW_PXP_HIST32_PARAM5_RSVD7_MASK) +/* HW_PXP_HIST32_PARAM6 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM6_VALUE24_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM6_VALUE24_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM6_VALUE24(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE24_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE24_MASK) +#define PXP_HW_PXP_HIST32_PARAM6_RSVD8_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM6_RSVD8_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM6_RSVD8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD8_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD8_MASK) +#define PXP_HW_PXP_HIST32_PARAM6_VALUE25_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM6_VALUE25_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM6_VALUE25(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE25_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE25_MASK) +#define PXP_HW_PXP_HIST32_PARAM6_RSVD9_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM6_RSVD9_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM6_RSVD9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD9_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD9_MASK) +#define PXP_HW_PXP_HIST32_PARAM6_VALUE26_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM6_VALUE26_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM6_VALUE26(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE26_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE26_MASK) +#define PXP_HW_PXP_HIST32_PARAM6_RSVD10_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM6_RSVD10_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM6_RSVD10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD10_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD10_MASK) +#define PXP_HW_PXP_HIST32_PARAM6_VALUE27_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM6_VALUE27_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM6_VALUE27(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_VALUE27_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_VALUE27_MASK) +#define PXP_HW_PXP_HIST32_PARAM6_RSVD11_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM6_RSVD11_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM6_RSVD11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM6_RSVD11_SHIFT))&PXP_HW_PXP_HIST32_PARAM6_RSVD11_MASK) +/* HW_PXP_HIST32_PARAM7 Bit Fields */ +#define PXP_HW_PXP_HIST32_PARAM7_VALUE28_MASK 0x3Fu +#define PXP_HW_PXP_HIST32_PARAM7_VALUE28_SHIFT 0 +#define PXP_HW_PXP_HIST32_PARAM7_VALUE28(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE28_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE28_MASK) +#define PXP_HW_PXP_HIST32_PARAM7_RSVD2_MASK 0xC0u +#define PXP_HW_PXP_HIST32_PARAM7_RSVD2_SHIFT 6 +#define PXP_HW_PXP_HIST32_PARAM7_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD2_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD2_MASK) +#define PXP_HW_PXP_HIST32_PARAM7_VALUE29_MASK 0x3F00u +#define PXP_HW_PXP_HIST32_PARAM7_VALUE29_SHIFT 8 +#define PXP_HW_PXP_HIST32_PARAM7_VALUE29(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE29_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE29_MASK) +#define PXP_HW_PXP_HIST32_PARAM7_RSVD13_MASK 0xC000u +#define PXP_HW_PXP_HIST32_PARAM7_RSVD13_SHIFT 14 +#define PXP_HW_PXP_HIST32_PARAM7_RSVD13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD13_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD13_MASK) +#define PXP_HW_PXP_HIST32_PARAM7_VALUE30_MASK 0x3F0000u +#define PXP_HW_PXP_HIST32_PARAM7_VALUE30_SHIFT 16 +#define PXP_HW_PXP_HIST32_PARAM7_VALUE30(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE30_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE30_MASK) +#define PXP_HW_PXP_HIST32_PARAM7_RSVD14_MASK 0xC00000u +#define PXP_HW_PXP_HIST32_PARAM7_RSVD14_SHIFT 22 +#define PXP_HW_PXP_HIST32_PARAM7_RSVD14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD14_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD14_MASK) +#define PXP_HW_PXP_HIST32_PARAM7_VALUE31_MASK 0x3F000000u +#define PXP_HW_PXP_HIST32_PARAM7_VALUE31_SHIFT 24 +#define PXP_HW_PXP_HIST32_PARAM7_VALUE31(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_VALUE31_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_VALUE31_MASK) +#define PXP_HW_PXP_HIST32_PARAM7_RSVD15_MASK 0xC0000000u +#define PXP_HW_PXP_HIST32_PARAM7_RSVD15_SHIFT 30 +#define PXP_HW_PXP_HIST32_PARAM7_RSVD15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HIST32_PARAM7_RSVD15_SHIFT))&PXP_HW_PXP_HIST32_PARAM7_RSVD15_MASK) +/* HW_PXP_COMP_CTRL Bit Fields */ +#define PXP_HW_PXP_COMP_CTRL_START_MASK 0x1u +#define PXP_HW_PXP_COMP_CTRL_START_SHIFT 0 +#define PXP_HW_PXP_COMP_CTRL_RSVD1_MASK 0xFEu +#define PXP_HW_PXP_COMP_CTRL_RSVD1_SHIFT 1 +#define PXP_HW_PXP_COMP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_CTRL_RSVD1_SHIFT))&PXP_HW_PXP_COMP_CTRL_RSVD1_MASK) +#define PXP_HW_PXP_COMP_CTRL_SW_RESET_MASK 0x100u +#define PXP_HW_PXP_COMP_CTRL_SW_RESET_SHIFT 8 +#define PXP_HW_PXP_COMP_CTRL_RSVD0_MASK 0xFFFFFE00u +#define PXP_HW_PXP_COMP_CTRL_RSVD0_SHIFT 9 +#define PXP_HW_PXP_COMP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_CTRL_RSVD0_SHIFT))&PXP_HW_PXP_COMP_CTRL_RSVD0_MASK) +/* HW_PXP_COMP_FORMAT0 Bit Fields */ +#define PXP_HW_PXP_COMP_FORMAT0_FLAG_32B_MASK 0x1u +#define PXP_HW_PXP_COMP_FORMAT0_FLAG_32B_SHIFT 0 +#define PXP_HW_PXP_COMP_FORMAT0_RSVD3_MASK 0xEu +#define PXP_HW_PXP_COMP_FORMAT0_RSVD3_SHIFT 1 +#define PXP_HW_PXP_COMP_FORMAT0_RSVD3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD3_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD3_MASK) +#define PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_MASK 0x30u +#define PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_SHIFT 4 +#define PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_FIELD_NUM_MASK) +#define PXP_HW_PXP_COMP_FORMAT0_RSVD2_MASK 0xC0u +#define PXP_HW_PXP_COMP_FORMAT0_RSVD2_SHIFT 6 +#define PXP_HW_PXP_COMP_FORMAT0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD2_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD2_MASK) +#define PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_MASK 0x300u +#define PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_SHIFT 8 +#define PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_MASK_INDEX_MASK) +#define PXP_HW_PXP_COMP_FORMAT0_RSVD1_MASK 0xFC00u +#define PXP_HW_PXP_COMP_FORMAT0_RSVD1_SHIFT 10 +#define PXP_HW_PXP_COMP_FORMAT0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD1_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD1_MASK) +#define PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_MASK 0x3FF0000u +#define PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_SHIFT 16 +#define PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_PIXEL_PITCH_64B_MASK) +#define PXP_HW_PXP_COMP_FORMAT0_ERR_PRONE_MASK 0x4000000u +#define PXP_HW_PXP_COMP_FORMAT0_ERR_PRONE_SHIFT 26 +#define PXP_HW_PXP_COMP_FORMAT0_FIFOFULL_MASK 0x8000000u +#define PXP_HW_PXP_COMP_FORMAT0_FIFOFULL_SHIFT 27 +#define PXP_HW_PXP_COMP_FORMAT0_RSVD0_MASK 0xF0000000u +#define PXP_HW_PXP_COMP_FORMAT0_RSVD0_SHIFT 28 +#define PXP_HW_PXP_COMP_FORMAT0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT0_RSVD0_SHIFT))&PXP_HW_PXP_COMP_FORMAT0_RSVD0_MASK) +/* HW_PXP_COMP_FORMAT1 Bit Fields */ +#define PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_MASK 0x1Fu +#define PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_SHIFT 0 +#define PXP_HW_PXP_COMP_FORMAT1_A_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_A_OFFSET_MASK) +#define PXP_HW_PXP_COMP_FORMAT1_A_LEN_MASK 0xE0u +#define PXP_HW_PXP_COMP_FORMAT1_A_LEN_SHIFT 5 +#define PXP_HW_PXP_COMP_FORMAT1_A_LEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_A_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_A_LEN_MASK) +#define PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_MASK 0x1F00u +#define PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_SHIFT 8 +#define PXP_HW_PXP_COMP_FORMAT1_B_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_B_OFFSET_MASK) +#define PXP_HW_PXP_COMP_FORMAT1_B_LEN_MASK 0xE000u +#define PXP_HW_PXP_COMP_FORMAT1_B_LEN_SHIFT 13 +#define PXP_HW_PXP_COMP_FORMAT1_B_LEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_B_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_B_LEN_MASK) +#define PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_MASK 0x1F0000u +#define PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_SHIFT 16 +#define PXP_HW_PXP_COMP_FORMAT1_C_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_C_OFFSET_MASK) +#define PXP_HW_PXP_COMP_FORMAT1_C_LEN_MASK 0xE00000u +#define PXP_HW_PXP_COMP_FORMAT1_C_LEN_SHIFT 21 +#define PXP_HW_PXP_COMP_FORMAT1_C_LEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_C_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_C_LEN_MASK) +#define PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_MASK 0x1F000000u +#define PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_SHIFT 24 +#define PXP_HW_PXP_COMP_FORMAT1_D_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_D_OFFSET_MASK) +#define PXP_HW_PXP_COMP_FORMAT1_D_LEN_MASK 0xE0000000u +#define PXP_HW_PXP_COMP_FORMAT1_D_LEN_SHIFT 29 +#define PXP_HW_PXP_COMP_FORMAT1_D_LEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT1_D_LEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT1_D_LEN_MASK) +/* HW_PXP_COMP_FORMAT2 Bit Fields */ +#define PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_MASK 0xFu +#define PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_SHIFT 0 +#define PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_A_RUNLEN_MASK) +#define PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_MASK 0xF0u +#define PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_SHIFT 4 +#define PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_B_RUNLEN_MASK) +#define PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_MASK 0xF00u +#define PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_SHIFT 8 +#define PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_C_RUNLEN_MASK) +#define PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_MASK 0xF000u +#define PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_SHIFT 12 +#define PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_D_RUNLEN_MASK) +#define PXP_HW_PXP_COMP_FORMAT2_RSVD_MASK 0xFFFF0000u +#define PXP_HW_PXP_COMP_FORMAT2_RSVD_SHIFT 16 +#define PXP_HW_PXP_COMP_FORMAT2_RSVD(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_FORMAT2_RSVD_SHIFT))&PXP_HW_PXP_COMP_FORMAT2_RSVD_MASK) +/* HW_PXP_COMP_MASK0 Bit Fields */ +#define PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_SHIFT 0 +#define PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_SHIFT))&PXP_HW_PXP_COMP_MASK0_VLD_MASK_LOW_MASK) +/* HW_PXP_COMP_MASK1 Bit Fields */ +#define PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_SHIFT 0 +#define PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_SHIFT))&PXP_HW_PXP_COMP_MASK1_VLD_MASK_HIGH_MASK) +/* HW_PXP_COMP_BUFFER_SIZE Bit Fields */ +#define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_MASK 0x1FFFu +#define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_SHIFT 0 +#define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_LENGTH_MASK) +#define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_MASK 0xE000u +#define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_SHIFT 13 +#define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD1_MASK) +#define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_MASK 0x1FFF0000u +#define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_SHIFT 16 +#define PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_PIXEL_WIDTH_MASK) +#define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_MASK 0xE0000000u +#define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_SHIFT 29 +#define PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_SHIFT))&PXP_HW_PXP_COMP_BUFFER_SIZE_RSVD0_MASK) +/* HW_PXP_COMP_SOURCE Bit Fields */ +#define PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_SHIFT 0 +#define PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_SHIFT))&PXP_HW_PXP_COMP_SOURCE_SOURCE_ADDR_MASK) +/* HW_PXP_COMP_TARGET Bit Fields */ +#define PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_SHIFT 0 +#define PXP_HW_PXP_COMP_TARGET_TARGET_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_SHIFT))&PXP_HW_PXP_COMP_TARGET_TARGET_ADDR_MASK) +/* HW_PXP_COMP_BUFFER_A Bit Fields */ +#define PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_SHIFT 0 +#define PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_A_A_SRAM_ADDR_MASK) +/* HW_PXP_COMP_BUFFER_B Bit Fields */ +#define PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_SHIFT 0 +#define PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_B_B_SRAM_ADDR_MASK) +/* HW_PXP_COMP_BUFFER_C Bit Fields */ +#define PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_SHIFT 0 +#define PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_C_C_SRAM_ADDR_MASK) +/* HW_PXP_COMP_BUFFER_D Bit Fields */ +#define PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_MASK 0xFFFFFFFFu +#define PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_SHIFT 0 +#define PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_SHIFT))&PXP_HW_PXP_COMP_BUFFER_D_D_SRAM_ADDR_MASK) +/* HW_PXP_COMP_DEBUG Bit Fields */ +#define PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_MASK 0xFFu +#define PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_SHIFT 0 +#define PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_SHIFT))&PXP_HW_PXP_COMP_DEBUG_DEBUG_SEL_MASK) +#define PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_MASK 0xFFFFFF00u +#define PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_SHIFT 8 +#define PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_SHIFT))&PXP_HW_PXP_COMP_DEBUG_DEBUG_VALUE_MASK) +/* HW_PXP_BUS_MUX Bit Fields */ +#define PXP_HW_PXP_BUS_MUX_RD_SEL_MASK 0xFFu +#define PXP_HW_PXP_BUS_MUX_RD_SEL_SHIFT 0 +#define PXP_HW_PXP_BUS_MUX_RD_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_RD_SEL_SHIFT))&PXP_HW_PXP_BUS_MUX_RD_SEL_MASK) +#define PXP_HW_PXP_BUS_MUX_RSVD0_MASK 0xFF00u +#define PXP_HW_PXP_BUS_MUX_RSVD0_SHIFT 8 +#define PXP_HW_PXP_BUS_MUX_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_RSVD0_SHIFT))&PXP_HW_PXP_BUS_MUX_RSVD0_MASK) +#define PXP_HW_PXP_BUS_MUX_WR_SEL_MASK 0xFF0000u +#define PXP_HW_PXP_BUS_MUX_WR_SEL_SHIFT 16 +#define PXP_HW_PXP_BUS_MUX_WR_SEL(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_WR_SEL_SHIFT))&PXP_HW_PXP_BUS_MUX_WR_SEL_MASK) +#define PXP_HW_PXP_BUS_MUX_RSVD1_MASK 0xFF000000u +#define PXP_HW_PXP_BUS_MUX_RSVD1_SHIFT 24 +#define PXP_HW_PXP_BUS_MUX_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_BUS_MUX_RSVD1_SHIFT))&PXP_HW_PXP_BUS_MUX_RSVD1_MASK) +/* HW_PXP_HANDSHAKE_READY_MUX0 Bit Fields */ +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_MASK 0xFu +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT 0 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK0_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_MASK 0xF0u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT 4 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK1_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_MASK 0xF00u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT 8 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK2_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_MASK 0xF000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT 12 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK3_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_MASK 0xF0000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT 16 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK4_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_MASK 0xF00000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT 20 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK5_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_MASK 0xF000000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT 24 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK6_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_MASK 0xF0000000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT 28 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX0_HSK7_MASK) +/* HW_PXP_HANDSHAKE_READY_MUX1 Bit Fields */ +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_MASK 0xFu +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT 0 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK8_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_MASK 0xF0u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT 4 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK9_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_MASK 0xF00u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT 8 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK10_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_MASK 0xF000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT 12 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK11_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_MASK 0xF0000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT 16 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK12_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_MASK 0xF00000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT 20 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK13_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_MASK 0xF000000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT 24 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK14_MASK) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_MASK 0xF0000000u +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT 28 +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT))&PXP_HW_PXP_HANDSHAKE_READY_MUX1_HSK15_MASK) +/* HW_PXP_HANDSHAKE_DONE_MUX0 Bit Fields */ +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK 0xFu +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT 0 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK 0xF0u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT 4 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK 0xF00u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT 8 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK 0xF000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT 12 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK 0xF0000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT 16 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK 0xF00000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT 20 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK 0xF000000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT 24 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK 0xF0000000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT 28 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK) +/* HW_PXP_HANDSHAKE_DONE_MUX1 Bit Fields */ +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK 0xFu +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT 0 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK 0xF0u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT 4 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK 0xF00u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT 8 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK 0xF000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT 12 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK 0xF0000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT 16 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK 0xF00000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT 20 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK 0xF000000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT 24 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK 0xF0000000u +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT 28 +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT))&PXP_HW_PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK) +/* HW_PXP_HANDSHAKE_CPU_FETCH Bit Fields */ +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_MASK 0x1u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_READY_SHIFT 0 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_MASK 0x2u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_READY_SHIFT 1 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_MASK 0x4u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B0_DONE_SHIFT 2 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_MASK 0x8u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_B1_DONE_SHIFT 3 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_MASK 0x30u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_SHIFT 4 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_BUF_LINES_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_MASK 0x7FC0u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD0_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_MASK 0x8000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW0_HSK_EN_SHIFT 15 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_MASK 0x10000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_READY_SHIFT 16 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_MASK 0x20000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_READY_SHIFT 17 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_MASK 0x40000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B0_DONE_SHIFT 18 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_MASK 0x80000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_B1_DONE_SHIFT 19 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_MASK 0x300000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_SHIFT 20 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_BUF_LINES_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_MASK 0x7FC00000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_SHIFT 22 +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_FETCH_RSVD1_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_MASK 0x80000000u +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_SW1_HSK_EN_SHIFT 31 +/* HW_PXP_HANDSHAKE_CPU_STORE Bit Fields */ +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_MASK 0x1u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_READY_SHIFT 0 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_MASK 0x2u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_READY_SHIFT 1 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_MASK 0x4u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B0_DONE_SHIFT 2 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_MASK 0x8u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_B1_DONE_SHIFT 3 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_MASK 0x30u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_SHIFT 4 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_BUF_LINES_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_MASK 0x7FC0u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_SHIFT 6 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD0_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_MASK 0x8000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW0_HSK_EN_SHIFT 15 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_MASK 0x10000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_READY_SHIFT 16 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_MASK 0x20000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_READY_SHIFT 17 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_MASK 0x40000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B0_DONE_SHIFT 18 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_MASK 0x80000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_B1_DONE_SHIFT 19 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_MASK 0x300000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_SHIFT 20 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_BUF_LINES_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_MASK 0x7FC00000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_SHIFT 22 +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_SHIFT))&PXP_HW_PXP_HANDSHAKE_CPU_STORE_RSVD1_MASK) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_MASK 0x80000000u +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_SW1_HSK_EN_SHIFT 31 + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x30700000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +#define PXP_BASE_PTR (PXP) +/** Array initializer of PXP peripheral base adresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } + +/* ---------------------------------------------------------------------------- + -- PXP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Accessor_Macros PXP - Register accessor macros + * @{ + */ + + +/* PXP - Register instance definitions */ +/* PXP */ +#define PXP_HW_PXP_CTRL PXP_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_STAT PXP_STAT_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_CTRL PXP_OUT_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_BUF PXP_OUT_BUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_BUF2 PXP_OUT_BUF2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_PITCH PXP_OUT_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_LRC PXP_OUT_LRC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_PS_ULC PXP_OUT_PS_ULC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_PS_LRC PXP_OUT_PS_LRC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_AS_ULC PXP_OUT_AS_ULC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_OUT_AS_LRC PXP_OUT_AS_LRC_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_CTRL PXP_PS_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_BUF PXP_PS_BUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_UBUF PXP_PS_UBUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_VBUF PXP_PS_VBUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_PITCH PXP_PS_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_BACKGROUND_0 PXP_HW_PXP_PS_BACKGROUND_0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_SCALE PXP_PS_SCALE_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_OFFSET PXP_PS_OFFSET_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_CLRKEYLOW_0 PXP_HW_PXP_PS_CLRKEYLOW_0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_CLRKEYHIGH_0 PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_CTRL PXP_AS_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_BUF PXP_AS_BUF_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_PITCH PXP_AS_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_CLRKEYLOW_0 PXP_HW_PXP_AS_CLRKEYLOW_0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_CLRKEYHIGH_0 PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC1_COEF0 PXP_CSC1_COEF0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC1_COEF1 PXP_CSC1_COEF1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC1_COEF2 PXP_CSC1_COEF2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_CTRL PXP_CSC2_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF0 PXP_CSC2_COEF0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF1 PXP_CSC2_COEF1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF2 PXP_CSC2_COEF2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF3 PXP_CSC2_COEF3_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF4 PXP_CSC2_COEF4_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CSC2_COEF5 PXP_CSC2_COEF5_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_CTRL PXP_LUT_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_ADDR PXP_LUT_ADDR_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_DATA PXP_LUT_DATA_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_LUT_EXTMEM PXP_LUT_EXTMEM_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CFA PXP_CFA_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_ALPHA_A_CTRL PXP_HW_PXP_ALPHA_A_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_ALPHA_B_CTRL PXP_HW_PXP_ALPHA_B_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_ALPHA_B_CTRL_1 PXP_HW_PXP_ALPHA_B_CTRL_1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_BACKGROUND_1 PXP_HW_PXP_PS_BACKGROUND_1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_CLRKEYLOW_1 PXP_HW_PXP_PS_CLRKEYLOW_1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_PS_CLRKEYHIGH_1 PXP_HW_PXP_PS_CLRKEYHIGH_1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_CLRKEYLOW_1 PXP_HW_PXP_AS_CLRKEYLOW_1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_AS_CLRKEYHIGH_1 PXP_HW_PXP_AS_CLRKEYHIGH_1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_CTRL2 PXP_HW_PXP_CTRL2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_POWER_REG0 PXP_HW_PXP_POWER_REG0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_POWER_REG1 PXP_HW_PXP_POWER_REG1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DATA_PATH_CTRL0 PXP_HW_PXP_DATA_PATH_CTRL0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DATA_PATH_CTRL1 PXP_HW_PXP_DATA_PATH_CTRL1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INIT_MEM_CTRL PXP_HW_PXP_INIT_MEM_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INIT_MEM_DATA PXP_HW_PXP_INIT_MEM_DATA_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INIT_MEM_DATA_HIGH PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_IRQ_MASK PXP_HW_PXP_IRQ_MASK_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_IRQ PXP_HW_PXP_IRQ_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_NEXT PXP_NEXT_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0 PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1 PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0 PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1 PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1 PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0 PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1 PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0 PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1 PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_PITCH PXP_HW_PXP_INPUT_FETCH_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0 PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1 PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0 PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1 PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0 PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1 PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0 PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0 PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1 PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1 PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0 PXP_HW_PXP_INPUT_STORE_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1 PXP_HW_PXP_INPUT_STORE_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0 PXP_HW_PXP_INPUT_STORE_STATUS_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1 PXP_HW_PXP_INPUT_STORE_STATUS_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0 PXP_HW_PXP_INPUT_STORE_SIZE_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1 PXP_HW_PXP_INPUT_STORE_SIZE_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_PITCH PXP_HW_PXP_INPUT_STORE_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0 PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1 PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0 PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0 PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0 PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1 PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1 PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0 PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0 PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0 PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0 PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0 PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0 PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0 PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0 PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1 PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0 PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1 PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1 PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0 PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1 PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0 PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1 PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_PITCH PXP_HW_PXP_DITHER_FETCH_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0 PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1 PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0 PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1 PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0 PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1 PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0 PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0 PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1 PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1 PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0 PXP_HW_PXP_DITHER_STORE_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1 PXP_HW_PXP_DITHER_STORE_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0 PXP_HW_PXP_DITHER_STORE_STATUS_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1 PXP_HW_PXP_DITHER_STORE_STATUS_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0 PXP_HW_PXP_DITHER_STORE_SIZE_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1 PXP_HW_PXP_DITHER_STORE_SIZE_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_PITCH PXP_HW_PXP_DITHER_STORE_PITCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0 PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1 PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0 PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0 PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0 PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1 PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1 PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0 PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0 PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0 PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0 PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0 PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0 PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0 PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_CTRL PXP_HW_PXP_DITHER_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0 PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1 PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2 PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3 PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_CTRL PXP_HW_PXP_HIST_A_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_MASK PXP_HW_PXP_HIST_A_MASK_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_BUF_SIZE PXP_HW_PXP_HIST_A_BUF_SIZE_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL PXP_HW_PXP_HIST_A_TOTAL_PIXEL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_RAW_STAT0 PXP_HW_PXP_HIST_A_RAW_STAT0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_A_RAW_STAT1 PXP_HW_PXP_HIST_A_RAW_STAT1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_CTRL PXP_HW_PXP_HIST_B_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_MASK PXP_HW_PXP_HIST_B_MASK_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_BUF_SIZE PXP_HW_PXP_HIST_B_BUF_SIZE_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL PXP_HW_PXP_HIST_B_TOTAL_PIXEL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_RAW_STAT0 PXP_HW_PXP_HIST_B_RAW_STAT0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST_B_RAW_STAT1 PXP_HW_PXP_HIST_B_RAW_STAT1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST2_PARAM PXP_HIST2_PARAM_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST4_PARAM PXP_HIST4_PARAM_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST8_PARAM0 PXP_HIST8_PARAM0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST8_PARAM1 PXP_HIST8_PARAM1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM0 PXP_HIST16_PARAM0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM1 PXP_HIST16_PARAM1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM2 PXP_HIST16_PARAM2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST16_PARAM3 PXP_HIST16_PARAM3_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM0 PXP_HW_PXP_HIST32_PARAM0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM1 PXP_HW_PXP_HIST32_PARAM1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM2 PXP_HW_PXP_HIST32_PARAM2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM3 PXP_HW_PXP_HIST32_PARAM3_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM4 PXP_HW_PXP_HIST32_PARAM4_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM5 PXP_HW_PXP_HIST32_PARAM5_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM6 PXP_HW_PXP_HIST32_PARAM6_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HIST32_PARAM7 PXP_HW_PXP_HIST32_PARAM7_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_CTRL PXP_HW_PXP_COMP_CTRL_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_FORMAT0 PXP_HW_PXP_COMP_FORMAT0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_FORMAT1 PXP_HW_PXP_COMP_FORMAT1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_FORMAT2 PXP_HW_PXP_COMP_FORMAT2_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_MASK0 PXP_HW_PXP_COMP_MASK0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_MASK1 PXP_HW_PXP_COMP_MASK1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_BUFFER_SIZE PXP_HW_PXP_COMP_BUFFER_SIZE_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_SOURCE PXP_HW_PXP_COMP_SOURCE_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_TARGET PXP_HW_PXP_COMP_TARGET_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_BUFFER_A PXP_HW_PXP_COMP_BUFFER_A_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_BUFFER_B PXP_HW_PXP_COMP_BUFFER_B_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_BUFFER_C PXP_HW_PXP_COMP_BUFFER_C_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_BUFFER_D PXP_HW_PXP_COMP_BUFFER_D_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_COMP_DEBUG PXP_HW_PXP_COMP_DEBUG_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_BUS_MUX PXP_HW_PXP_BUS_MUX_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0 PXP_HW_PXP_HANDSHAKE_READY_MUX0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1 PXP_HW_PXP_HANDSHAKE_READY_MUX1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0 PXP_HW_PXP_HANDSHAKE_DONE_MUX0_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1 PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(PXP_BASE_PTR) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(PXP_BASE_PTR) + +/*! + * @} + */ /* end of group PXP_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group PXP_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- QuadSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer + * @{ + */ + +/** QuadSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ + __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ + __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ + __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ + __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ + __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ + __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ + __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ + __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ + uint8_t RESERVED_2[196]; + __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ + __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ + __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ + uint8_t RESERVED_4[60]; + __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ + __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ + uint8_t RESERVED_5[4]; + __I uint32_t SR; /**< Status Register, offset: 0x15C */ + __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ + __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ + __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ + __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ + uint8_t RESERVED_6[16]; + __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ + __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ + __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ + __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ + uint8_t RESERVED_7[112]; + __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[128]; + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ + __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ + uint8_t RESERVED_9[8]; + __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ +} QuadSPI_Type, *QuadSPI_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- QuadSPI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros + * @{ + */ + + +/* QuadSPI - Register accessors */ +#define QuadSPI_MCR_REG(base) ((base)->MCR) +#define QuadSPI_IPCR_REG(base) ((base)->IPCR) +#define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) +#define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) +#define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) +#define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) +#define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) +#define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) +#define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) +#define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) +#define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) +#define QuadSPI_SFAR_REG(base) ((base)->SFAR) +#define QuadSPI_SMPR_REG(base) ((base)->SMPR) +#define QuadSPI_RBSR_REG(base) ((base)->RBSR) +#define QuadSPI_RBCT_REG(base) ((base)->RBCT) +#define QuadSPI_TBSR_REG(base) ((base)->TBSR) +#define QuadSPI_TBDR_REG(base) ((base)->TBDR) +#define QuadSPI_SR_REG(base) ((base)->SR) +#define QuadSPI_FR_REG(base) ((base)->FR) +#define QuadSPI_RSER_REG(base) ((base)->RSER) +#define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) +#define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) +#define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) +#define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) +#define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) +#define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) +#define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) +#define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) +#define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) +#define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) + +/*! + * @} + */ /* end of group QuadSPI_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define QuadSPI_MCR_SWRSTSD_MASK 0x1u +#define QuadSPI_MCR_SWRSTSD_SHIFT 0 +#define QuadSPI_MCR_SWRSTHD_MASK 0x2u +#define QuadSPI_MCR_SWRSTHD_SHIFT 1 +#define QuadSPI_MCR_END_CFG_MASK 0xCu +#define QuadSPI_MCR_END_CFG_SHIFT 2 +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_END_CFG_SHIFT))&QuadSPI_MCR_END_CFG_MASK) +#define QuadSPI_MCR_DQS_EN_MASK 0x40u +#define QuadSPI_MCR_DQS_EN_SHIFT 6 +#define QuadSPI_MCR_DDR_EN_MASK 0x80u +#define QuadSPI_MCR_DDR_EN_SHIFT 7 +#define QuadSPI_MCR_CLR_RXF_MASK 0x400u +#define QuadSPI_MCR_CLR_RXF_SHIFT 10 +#define QuadSPI_MCR_CLR_TXF_MASK 0x800u +#define QuadSPI_MCR_CLR_TXF_SHIFT 11 +#define QuadSPI_MCR_MDIS_MASK 0x4000u +#define QuadSPI_MCR_MDIS_SHIFT 14 +#define QuadSPI_MCR_SCLKCFG_MASK 0xFF000000u +#define QuadSPI_MCR_SCLKCFG_SHIFT 24 +#define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_SCLKCFG_SHIFT))&QuadSPI_MCR_SCLKCFG_MASK) +/* IPCR Bit Fields */ +#define QuadSPI_IPCR_IDATSZ_MASK 0xFFFFu +#define QuadSPI_IPCR_IDATSZ_SHIFT 0 +#define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_IDATSZ_SHIFT))&QuadSPI_IPCR_IDATSZ_MASK) +#define QuadSPI_IPCR_PAR_EN_MASK 0x10000u +#define QuadSPI_IPCR_PAR_EN_SHIFT 16 +#define QuadSPI_IPCR_SEQID_MASK 0xF000000u +#define QuadSPI_IPCR_SEQID_SHIFT 24 +#define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK) +/* FLSHCR Bit Fields */ +#define QuadSPI_FLSHCR_TCSS_MASK 0xFu +#define QuadSPI_FLSHCR_TCSS_SHIFT 0 +#define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSS_SHIFT))&QuadSPI_FLSHCR_TCSS_MASK) +#define QuadSPI_FLSHCR_TCSH_MASK 0xF00u +#define QuadSPI_FLSHCR_TCSH_SHIFT 8 +#define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSH_SHIFT))&QuadSPI_FLSHCR_TCSH_MASK) +/* BUF0CR Bit Fields */ +#define QuadSPI_BUF0CR_MSTRID_MASK 0xFu +#define QuadSPI_BUF0CR_MSTRID_SHIFT 0 +#define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_MSTRID_SHIFT))&QuadSPI_BUF0CR_MSTRID_MASK) +#define QuadSPI_BUF0CR_ADATSZ_MASK 0xFF00u +#define QuadSPI_BUF0CR_ADATSZ_SHIFT 8 +#define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_ADATSZ_SHIFT))&QuadSPI_BUF0CR_ADATSZ_MASK) +#define QuadSPI_BUF0CR_HP_EN_MASK 0x80000000u +#define QuadSPI_BUF0CR_HP_EN_SHIFT 31 +/* BUF1CR Bit Fields */ +#define QuadSPI_BUF1CR_MSTRID_MASK 0xFu +#define QuadSPI_BUF1CR_MSTRID_SHIFT 0 +#define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_MSTRID_SHIFT))&QuadSPI_BUF1CR_MSTRID_MASK) +#define QuadSPI_BUF1CR_ADATSZ_MASK 0xFF00u +#define QuadSPI_BUF1CR_ADATSZ_SHIFT 8 +#define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_ADATSZ_SHIFT))&QuadSPI_BUF1CR_ADATSZ_MASK) +/* BUF2CR Bit Fields */ +#define QuadSPI_BUF2CR_MSTRID_MASK 0xFu +#define QuadSPI_BUF2CR_MSTRID_SHIFT 0 +#define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_MSTRID_SHIFT))&QuadSPI_BUF2CR_MSTRID_MASK) +#define QuadSPI_BUF2CR_ADATSZ_MASK 0xFF00u +#define QuadSPI_BUF2CR_ADATSZ_SHIFT 8 +#define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_ADATSZ_SHIFT))&QuadSPI_BUF2CR_ADATSZ_MASK) +/* BUF3CR Bit Fields */ +#define QuadSPI_BUF3CR_MSTRID_MASK 0xFu +#define QuadSPI_BUF3CR_MSTRID_SHIFT 0 +#define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_MSTRID_SHIFT))&QuadSPI_BUF3CR_MSTRID_MASK) +#define QuadSPI_BUF3CR_ADATSZ_MASK 0xFF00u +#define QuadSPI_BUF3CR_ADATSZ_SHIFT 8 +#define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_ADATSZ_SHIFT))&QuadSPI_BUF3CR_ADATSZ_MASK) +#define QuadSPI_BUF3CR_ALLMST_MASK 0x80000000u +#define QuadSPI_BUF3CR_ALLMST_SHIFT 31 +/* BFGENCR Bit Fields */ +#define QuadSPI_BFGENCR_SEQID_MASK 0xF000u +#define QuadSPI_BFGENCR_SEQID_SHIFT 12 +#define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BFGENCR_SEQID_SHIFT))&QuadSPI_BFGENCR_SEQID_MASK) +#define QuadSPI_BFGENCR_PAR_EN_MASK 0x10000u +#define QuadSPI_BFGENCR_PAR_EN_SHIFT 16 +/* BUF0IND Bit Fields */ +#define QuadSPI_BUF0IND_TPINDX0_MASK 0xFFFFFFF8u +#define QuadSPI_BUF0IND_TPINDX0_SHIFT 3 +#define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0IND_TPINDX0_SHIFT))&QuadSPI_BUF0IND_TPINDX0_MASK) +/* BUF1IND Bit Fields */ +#define QuadSPI_BUF1IND_TPINDX1_MASK 0xFFFFFFF8u +#define QuadSPI_BUF1IND_TPINDX1_SHIFT 3 +#define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1IND_TPINDX1_SHIFT))&QuadSPI_BUF1IND_TPINDX1_MASK) +/* BUF2IND Bit Fields */ +#define QuadSPI_BUF2IND_TPINDX2_MASK 0xFFFFFFF8u +#define QuadSPI_BUF2IND_TPINDX2_SHIFT 3 +#define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK) +/* SFAR Bit Fields */ +#define QuadSPI_SFAR_SFADR_MASK 0xFFFFFFFFu +#define QuadSPI_SFAR_SFADR_SHIFT 0 +#define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFAR_SFADR_SHIFT))&QuadSPI_SFAR_SFADR_MASK) +/* SMPR Bit Fields */ +#define QuadSPI_SMPR_HSENA_MASK 0x1u +#define QuadSPI_SMPR_HSENA_SHIFT 0 +#define QuadSPI_SMPR_HSPHS_MASK 0x2u +#define QuadSPI_SMPR_HSPHS_SHIFT 1 +#define QuadSPI_SMPR_HSDLY_MASK 0x4u +#define QuadSPI_SMPR_HSDLY_SHIFT 2 +#define QuadSPI_SMPR_FSPHS_MASK 0x20u +#define QuadSPI_SMPR_FSPHS_SHIFT 5 +#define QuadSPI_SMPR_FSDLY_MASK 0x40u +#define QuadSPI_SMPR_FSDLY_SHIFT 6 +#define QuadSPI_SMPR_DDRSMP_MASK 0x70000u +#define QuadSPI_SMPR_DDRSMP_SHIFT 16 +#define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_DDRSMP_SHIFT))&QuadSPI_SMPR_DDRSMP_MASK) +/* RBSR Bit Fields */ +#define QuadSPI_RBSR_RDBFL_MASK 0x3F00u +#define QuadSPI_RBSR_RDBFL_SHIFT 8 +#define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDBFL_SHIFT))&QuadSPI_RBSR_RDBFL_MASK) +#define QuadSPI_RBSR_RDCTR_MASK 0xFFFF0000u +#define QuadSPI_RBSR_RDCTR_SHIFT 16 +#define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDCTR_SHIFT))&QuadSPI_RBSR_RDCTR_MASK) +/* RBCT Bit Fields */ +#define QuadSPI_RBCT_WMRK_MASK 0x1Fu +#define QuadSPI_RBCT_WMRK_SHIFT 0 +#define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBCT_WMRK_SHIFT))&QuadSPI_RBCT_WMRK_MASK) +#define QuadSPI_RBCT_RXBRD_MASK 0x100u +#define QuadSPI_RBCT_RXBRD_SHIFT 8 +/* TBSR Bit Fields */ +#define QuadSPI_TBSR_TRBFL_MASK 0x3F00u +#define QuadSPI_TBSR_TRBFL_SHIFT 8 +#define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRBFL_SHIFT))&QuadSPI_TBSR_TRBFL_MASK) +#define QuadSPI_TBSR_TRCTR_MASK 0xFFFF0000u +#define QuadSPI_TBSR_TRCTR_SHIFT 16 +#define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRCTR_SHIFT))&QuadSPI_TBSR_TRCTR_MASK) +/* TBDR Bit Fields */ +#define QuadSPI_TBDR_TXDATA_MASK 0xFFFFFFFFu +#define QuadSPI_TBDR_TXDATA_SHIFT 0 +#define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBDR_TXDATA_SHIFT))&QuadSPI_TBDR_TXDATA_MASK) +/* SR Bit Fields */ +#define QuadSPI_SR_BUSY_MASK 0x1u +#define QuadSPI_SR_BUSY_SHIFT 0 +#define QuadSPI_SR_IP_ACC_MASK 0x2u +#define QuadSPI_SR_IP_ACC_SHIFT 1 +#define QuadSPI_SR_AHB_ACC_MASK 0x4u +#define QuadSPI_SR_AHB_ACC_SHIFT 2 +#define QuadSPI_SR_AHBGNT_MASK 0x20u +#define QuadSPI_SR_AHBGNT_SHIFT 5 +#define QuadSPI_SR_AHBTRN_MASK 0x40u +#define QuadSPI_SR_AHBTRN_SHIFT 6 +#define QuadSPI_SR_AHB0NE_MASK 0x80u +#define QuadSPI_SR_AHB0NE_SHIFT 7 +#define QuadSPI_SR_AHB1NE_MASK 0x100u +#define QuadSPI_SR_AHB1NE_SHIFT 8 +#define QuadSPI_SR_AHB2NE_MASK 0x200u +#define QuadSPI_SR_AHB2NE_SHIFT 9 +#define QuadSPI_SR_AHB3NE_MASK 0x400u +#define QuadSPI_SR_AHB3NE_SHIFT 10 +#define QuadSPI_SR_AHB0FUL_MASK 0x800u +#define QuadSPI_SR_AHB0FUL_SHIFT 11 +#define QuadSPI_SR_AHB1FUL_MASK 0x1000u +#define QuadSPI_SR_AHB1FUL_SHIFT 12 +#define QuadSPI_SR_AHB2FUL_MASK 0x2000u +#define QuadSPI_SR_AHB2FUL_SHIFT 13 +#define QuadSPI_SR_AHB3FUL_MASK 0x4000u +#define QuadSPI_SR_AHB3FUL_SHIFT 14 +#define QuadSPI_SR_RXWE_MASK 0x10000u +#define QuadSPI_SR_RXWE_SHIFT 16 +#define QuadSPI_SR_RXFULL_MASK 0x80000u +#define QuadSPI_SR_RXFULL_SHIFT 19 +#define QuadSPI_SR_RXDMA_MASK 0x800000u +#define QuadSPI_SR_RXDMA_SHIFT 23 +#define QuadSPI_SR_TXEDA_MASK 0x1000000u +#define QuadSPI_SR_TXEDA_SHIFT 24 +#define QuadSPI_SR_TXFULL_MASK 0x8000000u +#define QuadSPI_SR_TXFULL_SHIFT 27 +#define QuadSPI_SR_DLPSMP_MASK 0xE0000000u +#define QuadSPI_SR_DLPSMP_SHIFT 29 +#define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_DLPSMP_SHIFT))&QuadSPI_SR_DLPSMP_MASK) +/* FR Bit Fields */ +#define QuadSPI_FR_TFF_MASK 0x1u +#define QuadSPI_FR_TFF_SHIFT 0 +#define QuadSPI_FR_IPGEF_MASK 0x10u +#define QuadSPI_FR_IPGEF_SHIFT 4 +#define QuadSPI_FR_IPIEF_MASK 0x40u +#define QuadSPI_FR_IPIEF_SHIFT 6 +#define QuadSPI_FR_IPAEF_MASK 0x80u +#define QuadSPI_FR_IPAEF_SHIFT 7 +#define QuadSPI_FR_IUEF_MASK 0x800u +#define QuadSPI_FR_IUEF_SHIFT 11 +#define QuadSPI_FR_ABOF_MASK 0x1000u +#define QuadSPI_FR_ABOF_SHIFT 12 +#define QuadSPI_FR_ABSEF_MASK 0x8000u +#define QuadSPI_FR_ABSEF_SHIFT 15 +#define QuadSPI_FR_RBDF_MASK 0x10000u +#define QuadSPI_FR_RBDF_SHIFT 16 +#define QuadSPI_FR_RBOF_MASK 0x20000u +#define QuadSPI_FR_RBOF_SHIFT 17 +#define QuadSPI_FR_ILLINE_MASK 0x800000u +#define QuadSPI_FR_ILLINE_SHIFT 23 +#define QuadSPI_FR_TBUF_MASK 0x4000000u +#define QuadSPI_FR_TBUF_SHIFT 26 +#define QuadSPI_FR_TBFF_MASK 0x8000000u +#define QuadSPI_FR_TBFF_SHIFT 27 +#define QuadSPI_FR_DLPFF_MASK 0x80000000u +#define QuadSPI_FR_DLPFF_SHIFT 31 +/* RSER Bit Fields */ +#define QuadSPI_RSER_TFIE_MASK 0x1u +#define QuadSPI_RSER_TFIE_SHIFT 0 +#define QuadSPI_RSER_IPGEIE_MASK 0x10u +#define QuadSPI_RSER_IPGEIE_SHIFT 4 +#define QuadSPI_RSER_IPIEIE_MASK 0x40u +#define QuadSPI_RSER_IPIEIE_SHIFT 6 +#define QuadSPI_RSER_IPAEIE_MASK 0x80u +#define QuadSPI_RSER_IPAEIE_SHIFT 7 +#define QuadSPI_RSER_IUEIE_MASK 0x800u +#define QuadSPI_RSER_IUEIE_SHIFT 11 +#define QuadSPI_RSER_ABOIE_MASK 0x1000u +#define QuadSPI_RSER_ABOIE_SHIFT 12 +#define QuadSPI_RSER_ABSEIE_MASK 0x8000u +#define QuadSPI_RSER_ABSEIE_SHIFT 15 +#define QuadSPI_RSER_RBDIE_MASK 0x10000u +#define QuadSPI_RSER_RBDIE_SHIFT 16 +#define QuadSPI_RSER_RBOIE_MASK 0x20000u +#define QuadSPI_RSER_RBOIE_SHIFT 17 +#define QuadSPI_RSER_RBDDE_MASK 0x200000u +#define QuadSPI_RSER_RBDDE_SHIFT 21 +#define QuadSPI_RSER_ILLINIE_MASK 0x800000u +#define QuadSPI_RSER_ILLINIE_SHIFT 23 +#define QuadSPI_RSER_TBUIE_MASK 0x4000000u +#define QuadSPI_RSER_TBUIE_SHIFT 26 +#define QuadSPI_RSER_TBFIE_MASK 0x8000000u +#define QuadSPI_RSER_TBFIE_SHIFT 27 +#define QuadSPI_RSER_DLPFIE_MASK 0x80000000u +#define QuadSPI_RSER_DLPFIE_SHIFT 31 +/* SPNDST Bit Fields */ +#define QuadSPI_SPNDST_SUSPND_MASK 0x1u +#define QuadSPI_SPNDST_SUSPND_SHIFT 0 +#define QuadSPI_SPNDST_SPDBUF_MASK 0xC0u +#define QuadSPI_SPNDST_SPDBUF_SHIFT 6 +#define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_SPDBUF_SHIFT))&QuadSPI_SPNDST_SPDBUF_MASK) +#define QuadSPI_SPNDST_DATLFT_MASK 0xFE00u +#define QuadSPI_SPNDST_DATLFT_SHIFT 9 +#define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_DATLFT_SHIFT))&QuadSPI_SPNDST_DATLFT_MASK) +/* SPTRCLR Bit Fields */ +#define QuadSPI_SPTRCLR_BFPTRC_MASK 0x1u +#define QuadSPI_SPTRCLR_BFPTRC_SHIFT 0 +#define QuadSPI_SPTRCLR_IPPTRC_MASK 0x100u +#define QuadSPI_SPTRCLR_IPPTRC_SHIFT 8 +/* SFA1AD Bit Fields */ +#define QuadSPI_SFA1AD_TPADA1_MASK 0xFFFFFC00u +#define QuadSPI_SFA1AD_TPADA1_SHIFT 10 +#define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA1AD_TPADA1_SHIFT))&QuadSPI_SFA1AD_TPADA1_MASK) +/* SFA2AD Bit Fields */ +#define QuadSPI_SFA2AD_TPADA2_MASK 0xFFFFFC00u +#define QuadSPI_SFA2AD_TPADA2_SHIFT 10 +#define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA2AD_TPADA2_SHIFT))&QuadSPI_SFA2AD_TPADA2_MASK) +/* SFB1AD Bit Fields */ +#define QuadSPI_SFB1AD_TPADB1_MASK 0xFFFFFC00u +#define QuadSPI_SFB1AD_TPADB1_SHIFT 10 +#define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB1AD_TPADB1_SHIFT))&QuadSPI_SFB1AD_TPADB1_MASK) +/* SFB2AD Bit Fields */ +#define QuadSPI_SFB2AD_TPADB2_MASK 0xFFFFFC00u +#define QuadSPI_SFB2AD_TPADB2_SHIFT 10 +#define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB2AD_TPADB2_SHIFT))&QuadSPI_SFB2AD_TPADB2_MASK) +/* RBDR Bit Fields */ +#define QuadSPI_RBDR_RXDATA_MASK 0xFFFFFFFFu +#define QuadSPI_RBDR_RXDATA_SHIFT 0 +#define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBDR_RXDATA_SHIFT))&QuadSPI_RBDR_RXDATA_MASK) +/* LUTKEY Bit Fields */ +#define QuadSPI_LUTKEY_KEY_MASK 0xFFFFFFFFu +#define QuadSPI_LUTKEY_KEY_SHIFT 0 +#define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUTKEY_KEY_SHIFT))&QuadSPI_LUTKEY_KEY_MASK) +/* LCKCR Bit Fields */ +#define QuadSPI_LCKCR_LOCK_MASK 0x1u +#define QuadSPI_LCKCR_LOCK_SHIFT 0 +#define QuadSPI_LCKCR_UNLOCK_MASK 0x2u +#define QuadSPI_LCKCR_UNLOCK_SHIFT 1 +/* LUT Bit Fields */ +#define QuadSPI_LUT_OPRND0_MASK 0xFFu +#define QuadSPI_LUT_OPRND0_SHIFT 0 +#define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND0_SHIFT))&QuadSPI_LUT_OPRND0_MASK) +#define QuadSPI_LUT_PAD0_MASK 0x300u +#define QuadSPI_LUT_PAD0_SHIFT 8 +#define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD0_SHIFT))&QuadSPI_LUT_PAD0_MASK) +#define QuadSPI_LUT_INSTR0_MASK 0xFC00u +#define QuadSPI_LUT_INSTR0_SHIFT 10 +#define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR0_SHIFT))&QuadSPI_LUT_INSTR0_MASK) +#define QuadSPI_LUT_OPRND1_MASK 0xFF0000u +#define QuadSPI_LUT_OPRND1_SHIFT 16 +#define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND1_SHIFT))&QuadSPI_LUT_OPRND1_MASK) +#define QuadSPI_LUT_PAD1_MASK 0x3000000u +#define QuadSPI_LUT_PAD1_SHIFT 24 +#define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD1_SHIFT))&QuadSPI_LUT_PAD1_MASK) +#define QuadSPI_LUT_INSTR1_MASK 0xFC000000u +#define QuadSPI_LUT_INSTR1_SHIFT 26 +#define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR1_SHIFT))&QuadSPI_LUT_INSTR1_MASK) + +/*! + * @} + */ /* end of group QuadSPI_Register_Masks */ + + +/* QuadSPI - Peripheral instance base addresses */ +/** Peripheral QuadSPI1 base address */ +#define QuadSPI1_BASE (0x30BB0000u) +/** Peripheral QuadSPI1 base pointer */ +#define QuadSPI1 ((QuadSPI_Type *)QuadSPI1_BASE) +#define QuadSPI1_BASE_PTR (QuadSPI1) +/** Peripheral QuadSPI2 base address */ +#define QuadSPI2_BASE (0x30BB4000u) +/** Peripheral QuadSPI2 base pointer */ +#define QuadSPI2 ((QuadSPI_Type *)QuadSPI2_BASE) +#define QuadSPI2_BASE_PTR (QuadSPI2) +/** Array initializer of QuadSPI peripheral base adresses */ +#define QuadSPI_BASE_ADDRS { QuadSPI1_BASE, QuadSPI2_BASE } +/** Array initializer of QuadSPI peripheral base pointers */ +#define QuadSPI_BASE_PTRS { QuadSPI1, QuadSPI2 } + +/* ---------------------------------------------------------------------------- + -- QuadSPI - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Accessor_Macros QuadSPI - Register accessor macros + * @{ + */ + + +/* QuadSPI - Register instance definitions */ +/* QuadSPI1 */ +#define QuadSPI1_MCR QuadSPI_MCR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_IPCR QuadSPI_IPCR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_FLSHCR QuadSPI_FLSHCR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BUF0CR QuadSPI_BUF0CR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BUF1CR QuadSPI_BUF1CR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BUF2CR QuadSPI_BUF2CR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BUF3CR QuadSPI_BUF3CR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BFGENCR QuadSPI_BFGENCR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BUF0IND QuadSPI_BUF0IND_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BUF1IND QuadSPI_BUF1IND_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_BUF2IND QuadSPI_BUF2IND_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SFAR QuadSPI_SFAR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SMPR QuadSPI_SMPR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_RBSR QuadSPI_RBSR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_RBCT QuadSPI_RBCT_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_TBSR QuadSPI_TBSR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_TBDR QuadSPI_TBDR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SR QuadSPI_SR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_FR QuadSPI_FR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_RSER QuadSPI_RSER_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SPNDST QuadSPI_SPNDST_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SPTRCLR QuadSPI_SPTRCLR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SFA1AD QuadSPI_SFA1AD_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SFA2AD QuadSPI_SFA2AD_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SFB1AD QuadSPI_SFB1AD_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_SFB2AD QuadSPI_SFB2AD_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_RBDR0 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,0) +#define QuadSPI1_RBDR1 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,1) +#define QuadSPI1_RBDR2 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,2) +#define QuadSPI1_RBDR3 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,3) +#define QuadSPI1_RBDR4 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,4) +#define QuadSPI1_RBDR5 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,5) +#define QuadSPI1_RBDR6 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,6) +#define QuadSPI1_RBDR7 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,7) +#define QuadSPI1_RBDR8 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,8) +#define QuadSPI1_RBDR9 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,9) +#define QuadSPI1_RBDR10 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,10) +#define QuadSPI1_RBDR11 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,11) +#define QuadSPI1_RBDR12 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,12) +#define QuadSPI1_RBDR13 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,13) +#define QuadSPI1_RBDR14 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,14) +#define QuadSPI1_RBDR15 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,15) +#define QuadSPI1_RBDR16 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,16) +#define QuadSPI1_RBDR17 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,17) +#define QuadSPI1_RBDR18 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,18) +#define QuadSPI1_RBDR19 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,19) +#define QuadSPI1_RBDR20 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,20) +#define QuadSPI1_RBDR21 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,21) +#define QuadSPI1_RBDR22 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,22) +#define QuadSPI1_RBDR23 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,23) +#define QuadSPI1_RBDR24 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,24) +#define QuadSPI1_RBDR25 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,25) +#define QuadSPI1_RBDR26 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,26) +#define QuadSPI1_RBDR27 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,27) +#define QuadSPI1_RBDR28 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,28) +#define QuadSPI1_RBDR29 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,29) +#define QuadSPI1_RBDR30 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,30) +#define QuadSPI1_RBDR31 QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,31) +#define QuadSPI1_LUTKEY QuadSPI_LUTKEY_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_LCKCR QuadSPI_LCKCR_REG(QuadSPI1_BASE_PTR) +#define QuadSPI1_LUT0 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,0) +#define QuadSPI1_LUT1 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,1) +#define QuadSPI1_LUT2 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,2) +#define QuadSPI1_LUT3 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,3) +#define QuadSPI1_LUT4 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,4) +#define QuadSPI1_LUT5 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,5) +#define QuadSPI1_LUT6 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,6) +#define QuadSPI1_LUT7 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,7) +#define QuadSPI1_LUT8 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,8) +#define QuadSPI1_LUT9 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,9) +#define QuadSPI1_LUT10 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,10) +#define QuadSPI1_LUT11 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,11) +#define QuadSPI1_LUT12 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,12) +#define QuadSPI1_LUT13 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,13) +#define QuadSPI1_LUT14 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,14) +#define QuadSPI1_LUT15 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,15) +#define QuadSPI1_LUT16 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,16) +#define QuadSPI1_LUT17 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,17) +#define QuadSPI1_LUT18 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,18) +#define QuadSPI1_LUT19 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,19) +#define QuadSPI1_LUT20 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,20) +#define QuadSPI1_LUT21 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,21) +#define QuadSPI1_LUT22 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,22) +#define QuadSPI1_LUT23 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,23) +#define QuadSPI1_LUT24 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,24) +#define QuadSPI1_LUT25 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,25) +#define QuadSPI1_LUT26 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,26) +#define QuadSPI1_LUT27 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,27) +#define QuadSPI1_LUT28 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,28) +#define QuadSPI1_LUT29 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,29) +#define QuadSPI1_LUT30 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,30) +#define QuadSPI1_LUT31 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,31) +#define QuadSPI1_LUT32 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,32) +#define QuadSPI1_LUT33 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,33) +#define QuadSPI1_LUT34 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,34) +#define QuadSPI1_LUT35 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,35) +#define QuadSPI1_LUT36 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,36) +#define QuadSPI1_LUT37 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,37) +#define QuadSPI1_LUT38 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,38) +#define QuadSPI1_LUT39 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,39) +#define QuadSPI1_LUT40 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,40) +#define QuadSPI1_LUT41 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,41) +#define QuadSPI1_LUT42 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,42) +#define QuadSPI1_LUT43 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,43) +#define QuadSPI1_LUT44 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,44) +#define QuadSPI1_LUT45 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,45) +#define QuadSPI1_LUT46 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,46) +#define QuadSPI1_LUT47 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,47) +#define QuadSPI1_LUT48 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,48) +#define QuadSPI1_LUT49 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,49) +#define QuadSPI1_LUT50 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,50) +#define QuadSPI1_LUT51 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,51) +#define QuadSPI1_LUT52 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,52) +#define QuadSPI1_LUT53 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,53) +#define QuadSPI1_LUT54 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,54) +#define QuadSPI1_LUT55 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,55) +#define QuadSPI1_LUT56 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,56) +#define QuadSPI1_LUT57 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,57) +#define QuadSPI1_LUT58 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,58) +#define QuadSPI1_LUT59 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,59) +#define QuadSPI1_LUT60 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,60) +#define QuadSPI1_LUT61 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,61) +#define QuadSPI1_LUT62 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,62) +#define QuadSPI1_LUT63 QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,63) +/* QuadSPI2 */ +#define QuadSPI2_MCR QuadSPI_MCR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_IPCR QuadSPI_IPCR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_FLSHCR QuadSPI_FLSHCR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BUF0CR QuadSPI_BUF0CR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BUF1CR QuadSPI_BUF1CR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BUF2CR QuadSPI_BUF2CR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BUF3CR QuadSPI_BUF3CR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BFGENCR QuadSPI_BFGENCR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BUF0IND QuadSPI_BUF0IND_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BUF1IND QuadSPI_BUF1IND_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_BUF2IND QuadSPI_BUF2IND_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SFAR QuadSPI_SFAR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SMPR QuadSPI_SMPR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_RBSR QuadSPI_RBSR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_RBCT QuadSPI_RBCT_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_TBSR QuadSPI_TBSR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_TBDR QuadSPI_TBDR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SR QuadSPI_SR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_FR QuadSPI_FR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_RSER QuadSPI_RSER_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SPNDST QuadSPI_SPNDST_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SPTRCLR QuadSPI_SPTRCLR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SFA1AD QuadSPI_SFA1AD_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SFA2AD QuadSPI_SFA2AD_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SFB1AD QuadSPI_SFB1AD_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_SFB2AD QuadSPI_SFB2AD_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_RBDR0 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,0) +#define QuadSPI2_RBDR1 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,1) +#define QuadSPI2_RBDR2 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,2) +#define QuadSPI2_RBDR3 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,3) +#define QuadSPI2_RBDR4 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,4) +#define QuadSPI2_RBDR5 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,5) +#define QuadSPI2_RBDR6 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,6) +#define QuadSPI2_RBDR7 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,7) +#define QuadSPI2_RBDR8 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,8) +#define QuadSPI2_RBDR9 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,9) +#define QuadSPI2_RBDR10 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,10) +#define QuadSPI2_RBDR11 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,11) +#define QuadSPI2_RBDR12 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,12) +#define QuadSPI2_RBDR13 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,13) +#define QuadSPI2_RBDR14 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,14) +#define QuadSPI2_RBDR15 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,15) +#define QuadSPI2_RBDR16 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,16) +#define QuadSPI2_RBDR17 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,17) +#define QuadSPI2_RBDR18 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,18) +#define QuadSPI2_RBDR19 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,19) +#define QuadSPI2_RBDR20 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,20) +#define QuadSPI2_RBDR21 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,21) +#define QuadSPI2_RBDR22 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,22) +#define QuadSPI2_RBDR23 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,23) +#define QuadSPI2_RBDR24 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,24) +#define QuadSPI2_RBDR25 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,25) +#define QuadSPI2_RBDR26 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,26) +#define QuadSPI2_RBDR27 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,27) +#define QuadSPI2_RBDR28 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,28) +#define QuadSPI2_RBDR29 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,29) +#define QuadSPI2_RBDR30 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,30) +#define QuadSPI2_RBDR31 QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,31) +#define QuadSPI2_LUTKEY QuadSPI_LUTKEY_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_LCKCR QuadSPI_LCKCR_REG(QuadSPI2_BASE_PTR) +#define QuadSPI2_LUT0 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,0) +#define QuadSPI2_LUT1 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,1) +#define QuadSPI2_LUT2 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,2) +#define QuadSPI2_LUT3 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,3) +#define QuadSPI2_LUT4 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,4) +#define QuadSPI2_LUT5 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,5) +#define QuadSPI2_LUT6 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,6) +#define QuadSPI2_LUT7 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,7) +#define QuadSPI2_LUT8 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,8) +#define QuadSPI2_LUT9 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,9) +#define QuadSPI2_LUT10 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,10) +#define QuadSPI2_LUT11 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,11) +#define QuadSPI2_LUT12 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,12) +#define QuadSPI2_LUT13 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,13) +#define QuadSPI2_LUT14 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,14) +#define QuadSPI2_LUT15 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,15) +#define QuadSPI2_LUT16 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,16) +#define QuadSPI2_LUT17 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,17) +#define QuadSPI2_LUT18 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,18) +#define QuadSPI2_LUT19 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,19) +#define QuadSPI2_LUT20 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,20) +#define QuadSPI2_LUT21 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,21) +#define QuadSPI2_LUT22 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,22) +#define QuadSPI2_LUT23 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,23) +#define QuadSPI2_LUT24 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,24) +#define QuadSPI2_LUT25 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,25) +#define QuadSPI2_LUT26 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,26) +#define QuadSPI2_LUT27 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,27) +#define QuadSPI2_LUT28 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,28) +#define QuadSPI2_LUT29 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,29) +#define QuadSPI2_LUT30 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,30) +#define QuadSPI2_LUT31 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,31) +#define QuadSPI2_LUT32 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,32) +#define QuadSPI2_LUT33 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,33) +#define QuadSPI2_LUT34 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,34) +#define QuadSPI2_LUT35 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,35) +#define QuadSPI2_LUT36 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,36) +#define QuadSPI2_LUT37 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,37) +#define QuadSPI2_LUT38 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,38) +#define QuadSPI2_LUT39 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,39) +#define QuadSPI2_LUT40 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,40) +#define QuadSPI2_LUT41 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,41) +#define QuadSPI2_LUT42 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,42) +#define QuadSPI2_LUT43 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,43) +#define QuadSPI2_LUT44 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,44) +#define QuadSPI2_LUT45 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,45) +#define QuadSPI2_LUT46 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,46) +#define QuadSPI2_LUT47 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,47) +#define QuadSPI2_LUT48 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,48) +#define QuadSPI2_LUT49 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,49) +#define QuadSPI2_LUT50 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,50) +#define QuadSPI2_LUT51 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,51) +#define QuadSPI2_LUT52 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,52) +#define QuadSPI2_LUT53 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,53) +#define QuadSPI2_LUT54 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,54) +#define QuadSPI2_LUT55 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,55) +#define QuadSPI2_LUT56 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,56) +#define QuadSPI2_LUT57 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,57) +#define QuadSPI2_LUT58 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,58) +#define QuadSPI2_LUT59 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,59) +#define QuadSPI2_LUT60 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,60) +#define QuadSPI2_LUT61 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,61) +#define QuadSPI2_LUT62 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,62) +#define QuadSPI2_LUT63 QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,63) + +/* QuadSPI - Register array accessors */ +#define QuadSPI1_RBDR(index) QuadSPI_RBDR_REG(QuadSPI1_BASE_PTR,index) +#define QuadSPI2_RBDR(index) QuadSPI_RBDR_REG(QuadSPI2_BASE_PTR,index) +#define QuadSPI1_LUT(index) QuadSPI_LUT_REG(QuadSPI1_BASE_PTR,index) +#define QuadSPI2_LUT(index) QuadSPI_LUT_REG(QuadSPI2_BASE_PTR,index) + +/*! + * @} + */ /* end of group QuadSPI_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group QuadSPI_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- RDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer + * @{ + */ + +/** RDC - Register Layout Typedef */ +typedef struct { + __I uint32_t VIR; /**< Version Information, offset: 0x0 */ + uint8_t RESERVED_0[32]; + __IO uint32_t STAT; /**< Status, offset: 0x24 */ + __IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */ + __IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */ + uint8_t RESERVED_1[464]; + __IO uint32_t MDA[27]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_2[404]; + __IO uint32_t PDAP[118]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_3[552]; + struct { /* offset: 0x800, array step: 0x10 */ + __IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */ + __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */ + __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */ + __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */ + } MR[52]; +} RDC_Type, *RDC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- RDC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros + * @{ + */ + + +/* RDC - Register accessors */ +#define RDC_VIR_REG(base) ((base)->VIR) +#define RDC_STAT_REG(base) ((base)->STAT) +#define RDC_INTCTRL_REG(base) ((base)->INTCTRL) +#define RDC_INTSTAT_REG(base) ((base)->INTSTAT) +#define RDC_MDA_REG(base,index) ((base)->MDA[index]) +#define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) +#define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) +#define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) +#define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) +#define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) + +/*! + * @} + */ /* end of group RDC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Masks RDC Register Masks + * @{ + */ + +/* VIR Bit Fields */ +#define RDC_VIR_NDID_MASK 0xFu +#define RDC_VIR_NDID_SHIFT 0 +#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NDID_SHIFT))&RDC_VIR_NDID_MASK) +#define RDC_VIR_NMSTR_MASK 0xFF0u +#define RDC_VIR_NMSTR_SHIFT 4 +#define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NMSTR_SHIFT))&RDC_VIR_NMSTR_MASK) +#define RDC_VIR_NPER_MASK 0xFF000u +#define RDC_VIR_NPER_SHIFT 12 +#define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NPER_SHIFT))&RDC_VIR_NPER_MASK) +#define RDC_VIR_NRGN_MASK 0xFF00000u +#define RDC_VIR_NRGN_SHIFT 20 +#define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x))<<RDC_VIR_NRGN_SHIFT))&RDC_VIR_NRGN_MASK) +/* STAT Bit Fields */ +#define RDC_STAT_DID_MASK 0xFu +#define RDC_STAT_DID_SHIFT 0 +#define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x))<<RDC_STAT_DID_SHIFT))&RDC_STAT_DID_MASK) +#define RDC_STAT_PDS_MASK 0x100u +#define RDC_STAT_PDS_SHIFT 8 +/* INTCTRL Bit Fields */ +#define RDC_INTCTRL_RCI_EN_MASK 0x1u +#define RDC_INTCTRL_RCI_EN_SHIFT 0 +/* INTSTAT Bit Fields */ +#define RDC_INTSTAT_INT_MASK 0x1u +#define RDC_INTSTAT_INT_SHIFT 0 +/* MDA Bit Fields */ +#define RDC_MDA_DID_MASK 0x3u +#define RDC_MDA_DID_SHIFT 0 +#define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x))<<RDC_MDA_DID_SHIFT))&RDC_MDA_DID_MASK) +#define RDC_MDA_LCK_MASK 0x80000000u +#define RDC_MDA_LCK_SHIFT 31 +/* PDAP Bit Fields */ +#define RDC_PDAP_D0W_MASK 0x1u +#define RDC_PDAP_D0W_SHIFT 0 +#define RDC_PDAP_D0R_MASK 0x2u +#define RDC_PDAP_D0R_SHIFT 1 +#define RDC_PDAP_D1W_MASK 0x4u +#define RDC_PDAP_D1W_SHIFT 2 +#define RDC_PDAP_D1R_MASK 0x8u +#define RDC_PDAP_D1R_SHIFT 3 +#define RDC_PDAP_D2W_MASK 0x10u +#define RDC_PDAP_D2W_SHIFT 4 +#define RDC_PDAP_D2R_MASK 0x20u +#define RDC_PDAP_D2R_SHIFT 5 +#define RDC_PDAP_D3W_MASK 0x40u +#define RDC_PDAP_D3W_SHIFT 6 +#define RDC_PDAP_D3R_MASK 0x80u +#define RDC_PDAP_D3R_SHIFT 7 +#define RDC_PDAP_SREQ_MASK 0x40000000u +#define RDC_PDAP_SREQ_SHIFT 30 +#define RDC_PDAP_LCK_MASK 0x80000000u +#define RDC_PDAP_LCK_SHIFT 31 +/* MRSA Bit Fields */ +#define RDC_MRSA_SADR_MASK 0xFFFFFF80u +#define RDC_MRSA_SADR_SHIFT 7 +#define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x))<<RDC_MRSA_SADR_SHIFT))&RDC_MRSA_SADR_MASK) +/* MREA Bit Fields */ +#define RDC_MREA_EADR_MASK 0xFFFFFF80u +#define RDC_MREA_EADR_SHIFT 7 +#define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x))<<RDC_MREA_EADR_SHIFT))&RDC_MREA_EADR_MASK) +/* MRC Bit Fields */ +#define RDC_MRC_D0W_MASK 0x1u +#define RDC_MRC_D0W_SHIFT 0 +#define RDC_MRC_D0R_MASK 0x2u +#define RDC_MRC_D0R_SHIFT 1 +#define RDC_MRC_D1W_MASK 0x4u +#define RDC_MRC_D1W_SHIFT 2 +#define RDC_MRC_D1R_MASK 0x8u +#define RDC_MRC_D1R_SHIFT 3 +#define RDC_MRC_D2W_MASK 0x10u +#define RDC_MRC_D2W_SHIFT 4 +#define RDC_MRC_D2R_MASK 0x20u +#define RDC_MRC_D2R_SHIFT 5 +#define RDC_MRC_D3W_MASK 0x40u +#define RDC_MRC_D3W_SHIFT 6 +#define RDC_MRC_D3R_MASK 0x80u +#define RDC_MRC_D3R_SHIFT 7 +#define RDC_MRC_ENA_MASK 0x40000000u +#define RDC_MRC_ENA_SHIFT 30 +#define RDC_MRC_LCK_MASK 0x80000000u +#define RDC_MRC_LCK_SHIFT 31 +/* MRVS Bit Fields */ +#define RDC_MRVS_VDID_MASK 0x3u +#define RDC_MRVS_VDID_SHIFT 0 +#define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VDID_SHIFT))&RDC_MRVS_VDID_MASK) +#define RDC_MRVS_AD_MASK 0x10u +#define RDC_MRVS_AD_SHIFT 4 +#define RDC_MRVS_VADR_MASK 0xFFFFFFE0u +#define RDC_MRVS_VADR_SHIFT 5 +#define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x))<<RDC_MRVS_VADR_SHIFT))&RDC_MRVS_VADR_MASK) + +/*! + * @} + */ /* end of group RDC_Register_Masks */ + + +/* RDC - Peripheral instance base addresses */ +/** Peripheral RDC base address */ +#define RDC_BASE (0x303D0000u) +/** Peripheral RDC base pointer */ +#define RDC ((RDC_Type *)RDC_BASE) +#define RDC_BASE_PTR (RDC) +/** Array initializer of RDC peripheral base adresses */ +#define RDC_BASE_ADDRS { RDC_BASE } +/** Array initializer of RDC peripheral base pointers */ +#define RDC_BASE_PTRS { RDC } + +/* ---------------------------------------------------------------------------- + -- RDC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Accessor_Macros RDC - Register accessor macros + * @{ + */ + + +/* RDC - Register instance definitions */ +/* RDC */ +#define RDC_VIR RDC_VIR_REG(RDC_BASE_PTR) +#define RDC_STAT RDC_STAT_REG(RDC_BASE_PTR) +#define RDC_INTCTRL RDC_INTCTRL_REG(RDC_BASE_PTR) +#define RDC_INTSTAT RDC_INTSTAT_REG(RDC_BASE_PTR) +#define RDC_MDA0 RDC_MDA_REG(RDC_BASE_PTR,0) +#define RDC_MDA1 RDC_MDA_REG(RDC_BASE_PTR,1) +#define RDC_MDA2 RDC_MDA_REG(RDC_BASE_PTR,2) +#define RDC_MDA3 RDC_MDA_REG(RDC_BASE_PTR,3) +#define RDC_MDA4 RDC_MDA_REG(RDC_BASE_PTR,4) +#define RDC_MDA5 RDC_MDA_REG(RDC_BASE_PTR,5) +#define RDC_MDA6 RDC_MDA_REG(RDC_BASE_PTR,6) +#define RDC_MDA7 RDC_MDA_REG(RDC_BASE_PTR,7) +#define RDC_MDA8 RDC_MDA_REG(RDC_BASE_PTR,8) +#define RDC_MDA9 RDC_MDA_REG(RDC_BASE_PTR,9) +#define RDC_MDA10 RDC_MDA_REG(RDC_BASE_PTR,10) +#define RDC_MDA11 RDC_MDA_REG(RDC_BASE_PTR,11) +#define RDC_MDA12 RDC_MDA_REG(RDC_BASE_PTR,12) +#define RDC_MDA13 RDC_MDA_REG(RDC_BASE_PTR,13) +#define RDC_MDA14 RDC_MDA_REG(RDC_BASE_PTR,14) +#define RDC_MDA15 RDC_MDA_REG(RDC_BASE_PTR,15) +#define RDC_MDA16 RDC_MDA_REG(RDC_BASE_PTR,16) +#define RDC_MDA17 RDC_MDA_REG(RDC_BASE_PTR,17) +#define RDC_MDA18 RDC_MDA_REG(RDC_BASE_PTR,18) +#define RDC_MDA19 RDC_MDA_REG(RDC_BASE_PTR,19) +#define RDC_MDA20 RDC_MDA_REG(RDC_BASE_PTR,20) +#define RDC_MDA21 RDC_MDA_REG(RDC_BASE_PTR,21) +#define RDC_MDA22 RDC_MDA_REG(RDC_BASE_PTR,22) +#define RDC_MDA23 RDC_MDA_REG(RDC_BASE_PTR,23) +#define RDC_MDA24 RDC_MDA_REG(RDC_BASE_PTR,24) +#define RDC_MDA25 RDC_MDA_REG(RDC_BASE_PTR,25) +#define RDC_MDA26 RDC_MDA_REG(RDC_BASE_PTR,26) +#define RDC_PDAP0 RDC_PDAP_REG(RDC_BASE_PTR,0) +#define RDC_PDAP1 RDC_PDAP_REG(RDC_BASE_PTR,1) +#define RDC_PDAP2 RDC_PDAP_REG(RDC_BASE_PTR,2) +#define RDC_PDAP3 RDC_PDAP_REG(RDC_BASE_PTR,3) +#define RDC_PDAP4 RDC_PDAP_REG(RDC_BASE_PTR,4) +#define RDC_PDAP5 RDC_PDAP_REG(RDC_BASE_PTR,5) +#define RDC_PDAP6 RDC_PDAP_REG(RDC_BASE_PTR,6) +#define RDC_PDAP7 RDC_PDAP_REG(RDC_BASE_PTR,7) +#define RDC_PDAP8 RDC_PDAP_REG(RDC_BASE_PTR,8) +#define RDC_PDAP9 RDC_PDAP_REG(RDC_BASE_PTR,9) +#define RDC_PDAP10 RDC_PDAP_REG(RDC_BASE_PTR,10) +#define RDC_PDAP11 RDC_PDAP_REG(RDC_BASE_PTR,11) +#define RDC_PDAP12 RDC_PDAP_REG(RDC_BASE_PTR,12) +#define RDC_PDAP13 RDC_PDAP_REG(RDC_BASE_PTR,13) +#define RDC_PDAP14 RDC_PDAP_REG(RDC_BASE_PTR,14) +#define RDC_PDAP15 RDC_PDAP_REG(RDC_BASE_PTR,15) +#define RDC_PDAP16 RDC_PDAP_REG(RDC_BASE_PTR,16) +#define RDC_PDAP17 RDC_PDAP_REG(RDC_BASE_PTR,17) +#define RDC_PDAP18 RDC_PDAP_REG(RDC_BASE_PTR,18) +#define RDC_PDAP19 RDC_PDAP_REG(RDC_BASE_PTR,19) +#define RDC_PDAP20 RDC_PDAP_REG(RDC_BASE_PTR,20) +#define RDC_PDAP21 RDC_PDAP_REG(RDC_BASE_PTR,21) +#define RDC_PDAP22 RDC_PDAP_REG(RDC_BASE_PTR,22) +#define RDC_PDAP23 RDC_PDAP_REG(RDC_BASE_PTR,23) +#define RDC_PDAP24 RDC_PDAP_REG(RDC_BASE_PTR,24) +#define RDC_PDAP25 RDC_PDAP_REG(RDC_BASE_PTR,25) +#define RDC_PDAP26 RDC_PDAP_REG(RDC_BASE_PTR,26) +#define RDC_PDAP27 RDC_PDAP_REG(RDC_BASE_PTR,27) +#define RDC_PDAP28 RDC_PDAP_REG(RDC_BASE_PTR,28) +#define RDC_PDAP29 RDC_PDAP_REG(RDC_BASE_PTR,29) +#define RDC_PDAP30 RDC_PDAP_REG(RDC_BASE_PTR,30) +#define RDC_PDAP31 RDC_PDAP_REG(RDC_BASE_PTR,31) +#define RDC_PDAP32 RDC_PDAP_REG(RDC_BASE_PTR,32) +#define RDC_PDAP33 RDC_PDAP_REG(RDC_BASE_PTR,33) +#define RDC_PDAP34 RDC_PDAP_REG(RDC_BASE_PTR,34) +#define RDC_PDAP35 RDC_PDAP_REG(RDC_BASE_PTR,35) +#define RDC_PDAP36 RDC_PDAP_REG(RDC_BASE_PTR,36) +#define RDC_PDAP37 RDC_PDAP_REG(RDC_BASE_PTR,37) +#define RDC_PDAP38 RDC_PDAP_REG(RDC_BASE_PTR,38) +#define RDC_PDAP39 RDC_PDAP_REG(RDC_BASE_PTR,39) +#define RDC_PDAP40 RDC_PDAP_REG(RDC_BASE_PTR,40) +#define RDC_PDAP41 RDC_PDAP_REG(RDC_BASE_PTR,41) +#define RDC_PDAP42 RDC_PDAP_REG(RDC_BASE_PTR,42) +#define RDC_PDAP43 RDC_PDAP_REG(RDC_BASE_PTR,43) +#define RDC_PDAP44 RDC_PDAP_REG(RDC_BASE_PTR,44) +#define RDC_PDAP45 RDC_PDAP_REG(RDC_BASE_PTR,45) +#define RDC_PDAP46 RDC_PDAP_REG(RDC_BASE_PTR,46) +#define RDC_PDAP47 RDC_PDAP_REG(RDC_BASE_PTR,47) +#define RDC_PDAP48 RDC_PDAP_REG(RDC_BASE_PTR,48) +#define RDC_PDAP49 RDC_PDAP_REG(RDC_BASE_PTR,49) +#define RDC_PDAP50 RDC_PDAP_REG(RDC_BASE_PTR,50) +#define RDC_PDAP51 RDC_PDAP_REG(RDC_BASE_PTR,51) +#define RDC_PDAP52 RDC_PDAP_REG(RDC_BASE_PTR,52) +#define RDC_PDAP53 RDC_PDAP_REG(RDC_BASE_PTR,53) +#define RDC_PDAP54 RDC_PDAP_REG(RDC_BASE_PTR,54) +#define RDC_PDAP55 RDC_PDAP_REG(RDC_BASE_PTR,55) +#define RDC_PDAP56 RDC_PDAP_REG(RDC_BASE_PTR,56) +#define RDC_PDAP57 RDC_PDAP_REG(RDC_BASE_PTR,57) +#define RDC_PDAP58 RDC_PDAP_REG(RDC_BASE_PTR,58) +#define RDC_PDAP59 RDC_PDAP_REG(RDC_BASE_PTR,59) +#define RDC_PDAP60 RDC_PDAP_REG(RDC_BASE_PTR,60) +#define RDC_PDAP61 RDC_PDAP_REG(RDC_BASE_PTR,61) +#define RDC_PDAP62 RDC_PDAP_REG(RDC_BASE_PTR,62) +#define RDC_PDAP63 RDC_PDAP_REG(RDC_BASE_PTR,63) +#define RDC_PDAP64 RDC_PDAP_REG(RDC_BASE_PTR,64) +#define RDC_PDAP65 RDC_PDAP_REG(RDC_BASE_PTR,65) +#define RDC_PDAP66 RDC_PDAP_REG(RDC_BASE_PTR,66) +#define RDC_PDAP67 RDC_PDAP_REG(RDC_BASE_PTR,67) +#define RDC_PDAP68 RDC_PDAP_REG(RDC_BASE_PTR,68) +#define RDC_PDAP69 RDC_PDAP_REG(RDC_BASE_PTR,69) +#define RDC_PDAP70 RDC_PDAP_REG(RDC_BASE_PTR,70) +#define RDC_PDAP71 RDC_PDAP_REG(RDC_BASE_PTR,71) +#define RDC_PDAP72 RDC_PDAP_REG(RDC_BASE_PTR,72) +#define RDC_PDAP73 RDC_PDAP_REG(RDC_BASE_PTR,73) +#define RDC_PDAP74 RDC_PDAP_REG(RDC_BASE_PTR,74) +#define RDC_PDAP75 RDC_PDAP_REG(RDC_BASE_PTR,75) +#define RDC_PDAP76 RDC_PDAP_REG(RDC_BASE_PTR,76) +#define RDC_PDAP77 RDC_PDAP_REG(RDC_BASE_PTR,77) +#define RDC_PDAP78 RDC_PDAP_REG(RDC_BASE_PTR,78) +#define RDC_PDAP79 RDC_PDAP_REG(RDC_BASE_PTR,79) +#define RDC_PDAP80 RDC_PDAP_REG(RDC_BASE_PTR,80) +#define RDC_PDAP81 RDC_PDAP_REG(RDC_BASE_PTR,81) +#define RDC_PDAP82 RDC_PDAP_REG(RDC_BASE_PTR,82) +#define RDC_PDAP83 RDC_PDAP_REG(RDC_BASE_PTR,83) +#define RDC_PDAP84 RDC_PDAP_REG(RDC_BASE_PTR,84) +#define RDC_PDAP85 RDC_PDAP_REG(RDC_BASE_PTR,85) +#define RDC_PDAP86 RDC_PDAP_REG(RDC_BASE_PTR,86) +#define RDC_PDAP87 RDC_PDAP_REG(RDC_BASE_PTR,87) +#define RDC_PDAP88 RDC_PDAP_REG(RDC_BASE_PTR,88) +#define RDC_PDAP89 RDC_PDAP_REG(RDC_BASE_PTR,89) +#define RDC_PDAP90 RDC_PDAP_REG(RDC_BASE_PTR,90) +#define RDC_PDAP91 RDC_PDAP_REG(RDC_BASE_PTR,91) +#define RDC_PDAP92 RDC_PDAP_REG(RDC_BASE_PTR,92) +#define RDC_PDAP93 RDC_PDAP_REG(RDC_BASE_PTR,93) +#define RDC_PDAP94 RDC_PDAP_REG(RDC_BASE_PTR,94) +#define RDC_PDAP95 RDC_PDAP_REG(RDC_BASE_PTR,95) +#define RDC_PDAP96 RDC_PDAP_REG(RDC_BASE_PTR,96) +#define RDC_PDAP97 RDC_PDAP_REG(RDC_BASE_PTR,97) +#define RDC_PDAP98 RDC_PDAP_REG(RDC_BASE_PTR,98) +#define RDC_PDAP99 RDC_PDAP_REG(RDC_BASE_PTR,99) +#define RDC_PDAP100 RDC_PDAP_REG(RDC_BASE_PTR,100) +#define RDC_PDAP101 RDC_PDAP_REG(RDC_BASE_PTR,101) +#define RDC_PDAP102 RDC_PDAP_REG(RDC_BASE_PTR,102) +#define RDC_PDAP103 RDC_PDAP_REG(RDC_BASE_PTR,103) +#define RDC_PDAP104 RDC_PDAP_REG(RDC_BASE_PTR,104) +#define RDC_PDAP105 RDC_PDAP_REG(RDC_BASE_PTR,105) +#define RDC_PDAP106 RDC_PDAP_REG(RDC_BASE_PTR,106) +#define RDC_PDAP107 RDC_PDAP_REG(RDC_BASE_PTR,107) +#define RDC_PDAP108 RDC_PDAP_REG(RDC_BASE_PTR,108) +#define RDC_PDAP109 RDC_PDAP_REG(RDC_BASE_PTR,109) +#define RDC_PDAP110 RDC_PDAP_REG(RDC_BASE_PTR,110) +#define RDC_PDAP111 RDC_PDAP_REG(RDC_BASE_PTR,111) +#define RDC_PDAP112 RDC_PDAP_REG(RDC_BASE_PTR,112) +#define RDC_PDAP113 RDC_PDAP_REG(RDC_BASE_PTR,113) +#define RDC_PDAP114 RDC_PDAP_REG(RDC_BASE_PTR,114) +#define RDC_PDAP115 RDC_PDAP_REG(RDC_BASE_PTR,115) +#define RDC_PDAP116 RDC_PDAP_REG(RDC_BASE_PTR,116) +#define RDC_PDAP117 RDC_PDAP_REG(RDC_BASE_PTR,117) +#define RDC_MRSA0 RDC_MRSA_REG(RDC_BASE_PTR,0) +#define RDC_MREA0 RDC_MREA_REG(RDC_BASE_PTR,0) +#define RDC_MRC0 RDC_MRC_REG(RDC_BASE_PTR,0) +#define RDC_MRVS0 RDC_MRVS_REG(RDC_BASE_PTR,0) +#define RDC_MRSA1 RDC_MRSA_REG(RDC_BASE_PTR,1) +#define RDC_MREA1 RDC_MREA_REG(RDC_BASE_PTR,1) +#define RDC_MRC1 RDC_MRC_REG(RDC_BASE_PTR,1) +#define RDC_MRVS1 RDC_MRVS_REG(RDC_BASE_PTR,1) +#define RDC_MRSA2 RDC_MRSA_REG(RDC_BASE_PTR,2) +#define RDC_MREA2 RDC_MREA_REG(RDC_BASE_PTR,2) +#define RDC_MRC2 RDC_MRC_REG(RDC_BASE_PTR,2) +#define RDC_MRVS2 RDC_MRVS_REG(RDC_BASE_PTR,2) +#define RDC_MRSA3 RDC_MRSA_REG(RDC_BASE_PTR,3) +#define RDC_MREA3 RDC_MREA_REG(RDC_BASE_PTR,3) +#define RDC_MRC3 RDC_MRC_REG(RDC_BASE_PTR,3) +#define RDC_MRVS3 RDC_MRVS_REG(RDC_BASE_PTR,3) +#define RDC_MRSA4 RDC_MRSA_REG(RDC_BASE_PTR,4) +#define RDC_MREA4 RDC_MREA_REG(RDC_BASE_PTR,4) +#define RDC_MRC4 RDC_MRC_REG(RDC_BASE_PTR,4) +#define RDC_MRVS4 RDC_MRVS_REG(RDC_BASE_PTR,4) +#define RDC_MRSA5 RDC_MRSA_REG(RDC_BASE_PTR,5) +#define RDC_MREA5 RDC_MREA_REG(RDC_BASE_PTR,5) +#define RDC_MRC5 RDC_MRC_REG(RDC_BASE_PTR,5) +#define RDC_MRVS5 RDC_MRVS_REG(RDC_BASE_PTR,5) +#define RDC_MRSA6 RDC_MRSA_REG(RDC_BASE_PTR,6) +#define RDC_MREA6 RDC_MREA_REG(RDC_BASE_PTR,6) +#define RDC_MRC6 RDC_MRC_REG(RDC_BASE_PTR,6) +#define RDC_MRVS6 RDC_MRVS_REG(RDC_BASE_PTR,6) +#define RDC_MRSA7 RDC_MRSA_REG(RDC_BASE_PTR,7) +#define RDC_MREA7 RDC_MREA_REG(RDC_BASE_PTR,7) +#define RDC_MRC7 RDC_MRC_REG(RDC_BASE_PTR,7) +#define RDC_MRVS7 RDC_MRVS_REG(RDC_BASE_PTR,7) +#define RDC_MRSA8 RDC_MRSA_REG(RDC_BASE_PTR,8) +#define RDC_MREA8 RDC_MREA_REG(RDC_BASE_PTR,8) +#define RDC_MRC8 RDC_MRC_REG(RDC_BASE_PTR,8) +#define RDC_MRVS8 RDC_MRVS_REG(RDC_BASE_PTR,8) +#define RDC_MRSA9 RDC_MRSA_REG(RDC_BASE_PTR,9) +#define RDC_MREA9 RDC_MREA_REG(RDC_BASE_PTR,9) +#define RDC_MRC9 RDC_MRC_REG(RDC_BASE_PTR,9) +#define RDC_MRVS9 RDC_MRVS_REG(RDC_BASE_PTR,9) +#define RDC_MRSA10 RDC_MRSA_REG(RDC_BASE_PTR,10) +#define RDC_MREA10 RDC_MREA_REG(RDC_BASE_PTR,10) +#define RDC_MRC10 RDC_MRC_REG(RDC_BASE_PTR,10) +#define RDC_MRVS10 RDC_MRVS_REG(RDC_BASE_PTR,10) +#define RDC_MRSA11 RDC_MRSA_REG(RDC_BASE_PTR,11) +#define RDC_MREA11 RDC_MREA_REG(RDC_BASE_PTR,11) +#define RDC_MRC11 RDC_MRC_REG(RDC_BASE_PTR,11) +#define RDC_MRVS11 RDC_MRVS_REG(RDC_BASE_PTR,11) +#define RDC_MRSA12 RDC_MRSA_REG(RDC_BASE_PTR,12) +#define RDC_MREA12 RDC_MREA_REG(RDC_BASE_PTR,12) +#define RDC_MRC12 RDC_MRC_REG(RDC_BASE_PTR,12) +#define RDC_MRVS12 RDC_MRVS_REG(RDC_BASE_PTR,12) +#define RDC_MRSA13 RDC_MRSA_REG(RDC_BASE_PTR,13) +#define RDC_MREA13 RDC_MREA_REG(RDC_BASE_PTR,13) +#define RDC_MRC13 RDC_MRC_REG(RDC_BASE_PTR,13) +#define RDC_MRVS13 RDC_MRVS_REG(RDC_BASE_PTR,13) +#define RDC_MRSA14 RDC_MRSA_REG(RDC_BASE_PTR,14) +#define RDC_MREA14 RDC_MREA_REG(RDC_BASE_PTR,14) +#define RDC_MRC14 RDC_MRC_REG(RDC_BASE_PTR,14) +#define RDC_MRVS14 RDC_MRVS_REG(RDC_BASE_PTR,14) +#define RDC_MRSA15 RDC_MRSA_REG(RDC_BASE_PTR,15) +#define RDC_MREA15 RDC_MREA_REG(RDC_BASE_PTR,15) +#define RDC_MRC15 RDC_MRC_REG(RDC_BASE_PTR,15) +#define RDC_MRVS15 RDC_MRVS_REG(RDC_BASE_PTR,15) +#define RDC_MRSA16 RDC_MRSA_REG(RDC_BASE_PTR,16) +#define RDC_MREA16 RDC_MREA_REG(RDC_BASE_PTR,16) +#define RDC_MRC16 RDC_MRC_REG(RDC_BASE_PTR,16) +#define RDC_MRVS16 RDC_MRVS_REG(RDC_BASE_PTR,16) +#define RDC_MRSA17 RDC_MRSA_REG(RDC_BASE_PTR,17) +#define RDC_MREA17 RDC_MREA_REG(RDC_BASE_PTR,17) +#define RDC_MRC17 RDC_MRC_REG(RDC_BASE_PTR,17) +#define RDC_MRVS17 RDC_MRVS_REG(RDC_BASE_PTR,17) +#define RDC_MRSA18 RDC_MRSA_REG(RDC_BASE_PTR,18) +#define RDC_MREA18 RDC_MREA_REG(RDC_BASE_PTR,18) +#define RDC_MRC18 RDC_MRC_REG(RDC_BASE_PTR,18) +#define RDC_MRVS18 RDC_MRVS_REG(RDC_BASE_PTR,18) +#define RDC_MRSA19 RDC_MRSA_REG(RDC_BASE_PTR,19) +#define RDC_MREA19 RDC_MREA_REG(RDC_BASE_PTR,19) +#define RDC_MRC19 RDC_MRC_REG(RDC_BASE_PTR,19) +#define RDC_MRVS19 RDC_MRVS_REG(RDC_BASE_PTR,19) +#define RDC_MRSA20 RDC_MRSA_REG(RDC_BASE_PTR,20) +#define RDC_MREA20 RDC_MREA_REG(RDC_BASE_PTR,20) +#define RDC_MRC20 RDC_MRC_REG(RDC_BASE_PTR,20) +#define RDC_MRVS20 RDC_MRVS_REG(RDC_BASE_PTR,20) +#define RDC_MRSA21 RDC_MRSA_REG(RDC_BASE_PTR,21) +#define RDC_MREA21 RDC_MREA_REG(RDC_BASE_PTR,21) +#define RDC_MRC21 RDC_MRC_REG(RDC_BASE_PTR,21) +#define RDC_MRVS21 RDC_MRVS_REG(RDC_BASE_PTR,21) +#define RDC_MRSA22 RDC_MRSA_REG(RDC_BASE_PTR,22) +#define RDC_MREA22 RDC_MREA_REG(RDC_BASE_PTR,22) +#define RDC_MRC22 RDC_MRC_REG(RDC_BASE_PTR,22) +#define RDC_MRVS22 RDC_MRVS_REG(RDC_BASE_PTR,22) +#define RDC_MRSA23 RDC_MRSA_REG(RDC_BASE_PTR,23) +#define RDC_MREA23 RDC_MREA_REG(RDC_BASE_PTR,23) +#define RDC_MRC23 RDC_MRC_REG(RDC_BASE_PTR,23) +#define RDC_MRVS23 RDC_MRVS_REG(RDC_BASE_PTR,23) +#define RDC_MRSA24 RDC_MRSA_REG(RDC_BASE_PTR,24) +#define RDC_MREA24 RDC_MREA_REG(RDC_BASE_PTR,24) +#define RDC_MRC24 RDC_MRC_REG(RDC_BASE_PTR,24) +#define RDC_MRVS24 RDC_MRVS_REG(RDC_BASE_PTR,24) +#define RDC_MRSA25 RDC_MRSA_REG(RDC_BASE_PTR,25) +#define RDC_MREA25 RDC_MREA_REG(RDC_BASE_PTR,25) +#define RDC_MRC25 RDC_MRC_REG(RDC_BASE_PTR,25) +#define RDC_MRVS25 RDC_MRVS_REG(RDC_BASE_PTR,25) +#define RDC_MRSA26 RDC_MRSA_REG(RDC_BASE_PTR,26) +#define RDC_MREA26 RDC_MREA_REG(RDC_BASE_PTR,26) +#define RDC_MRC26 RDC_MRC_REG(RDC_BASE_PTR,26) +#define RDC_MRVS26 RDC_MRVS_REG(RDC_BASE_PTR,26) +#define RDC_MRSA27 RDC_MRSA_REG(RDC_BASE_PTR,27) +#define RDC_MREA27 RDC_MREA_REG(RDC_BASE_PTR,27) +#define RDC_MRC27 RDC_MRC_REG(RDC_BASE_PTR,27) +#define RDC_MRVS27 RDC_MRVS_REG(RDC_BASE_PTR,27) +#define RDC_MRSA28 RDC_MRSA_REG(RDC_BASE_PTR,28) +#define RDC_MREA28 RDC_MREA_REG(RDC_BASE_PTR,28) +#define RDC_MRC28 RDC_MRC_REG(RDC_BASE_PTR,28) +#define RDC_MRVS28 RDC_MRVS_REG(RDC_BASE_PTR,28) +#define RDC_MRSA29 RDC_MRSA_REG(RDC_BASE_PTR,29) +#define RDC_MREA29 RDC_MREA_REG(RDC_BASE_PTR,29) +#define RDC_MRC29 RDC_MRC_REG(RDC_BASE_PTR,29) +#define RDC_MRVS29 RDC_MRVS_REG(RDC_BASE_PTR,29) +#define RDC_MRSA30 RDC_MRSA_REG(RDC_BASE_PTR,30) +#define RDC_MREA30 RDC_MREA_REG(RDC_BASE_PTR,30) +#define RDC_MRC30 RDC_MRC_REG(RDC_BASE_PTR,30) +#define RDC_MRVS30 RDC_MRVS_REG(RDC_BASE_PTR,30) +#define RDC_MRSA31 RDC_MRSA_REG(RDC_BASE_PTR,31) +#define RDC_MREA31 RDC_MREA_REG(RDC_BASE_PTR,31) +#define RDC_MRC31 RDC_MRC_REG(RDC_BASE_PTR,31) +#define RDC_MRVS31 RDC_MRVS_REG(RDC_BASE_PTR,31) +#define RDC_MRSA32 RDC_MRSA_REG(RDC_BASE_PTR,32) +#define RDC_MREA32 RDC_MREA_REG(RDC_BASE_PTR,32) +#define RDC_MRC32 RDC_MRC_REG(RDC_BASE_PTR,32) +#define RDC_MRVS32 RDC_MRVS_REG(RDC_BASE_PTR,32) +#define RDC_MRSA33 RDC_MRSA_REG(RDC_BASE_PTR,33) +#define RDC_MREA33 RDC_MREA_REG(RDC_BASE_PTR,33) +#define RDC_MRC33 RDC_MRC_REG(RDC_BASE_PTR,33) +#define RDC_MRVS33 RDC_MRVS_REG(RDC_BASE_PTR,33) +#define RDC_MRSA34 RDC_MRSA_REG(RDC_BASE_PTR,34) +#define RDC_MREA34 RDC_MREA_REG(RDC_BASE_PTR,34) +#define RDC_MRC34 RDC_MRC_REG(RDC_BASE_PTR,34) +#define RDC_MRVS34 RDC_MRVS_REG(RDC_BASE_PTR,34) +#define RDC_MRSA35 RDC_MRSA_REG(RDC_BASE_PTR,35) +#define RDC_MREA35 RDC_MREA_REG(RDC_BASE_PTR,35) +#define RDC_MRC35 RDC_MRC_REG(RDC_BASE_PTR,35) +#define RDC_MRVS35 RDC_MRVS_REG(RDC_BASE_PTR,35) +#define RDC_MRSA36 RDC_MRSA_REG(RDC_BASE_PTR,36) +#define RDC_MREA36 RDC_MREA_REG(RDC_BASE_PTR,36) +#define RDC_MRC36 RDC_MRC_REG(RDC_BASE_PTR,36) +#define RDC_MRVS36 RDC_MRVS_REG(RDC_BASE_PTR,36) +#define RDC_MRSA37 RDC_MRSA_REG(RDC_BASE_PTR,37) +#define RDC_MREA37 RDC_MREA_REG(RDC_BASE_PTR,37) +#define RDC_MRC37 RDC_MRC_REG(RDC_BASE_PTR,37) +#define RDC_MRVS37 RDC_MRVS_REG(RDC_BASE_PTR,37) +#define RDC_MRSA38 RDC_MRSA_REG(RDC_BASE_PTR,38) +#define RDC_MREA38 RDC_MREA_REG(RDC_BASE_PTR,38) +#define RDC_MRC38 RDC_MRC_REG(RDC_BASE_PTR,38) +#define RDC_MRVS38 RDC_MRVS_REG(RDC_BASE_PTR,38) +#define RDC_MRSA39 RDC_MRSA_REG(RDC_BASE_PTR,39) +#define RDC_MREA39 RDC_MREA_REG(RDC_BASE_PTR,39) +#define RDC_MRC39 RDC_MRC_REG(RDC_BASE_PTR,39) +#define RDC_MRVS39 RDC_MRVS_REG(RDC_BASE_PTR,39) +#define RDC_MRSA40 RDC_MRSA_REG(RDC_BASE_PTR,40) +#define RDC_MREA40 RDC_MREA_REG(RDC_BASE_PTR,40) +#define RDC_MRC40 RDC_MRC_REG(RDC_BASE_PTR,40) +#define RDC_MRVS40 RDC_MRVS_REG(RDC_BASE_PTR,40) +#define RDC_MRSA41 RDC_MRSA_REG(RDC_BASE_PTR,41) +#define RDC_MREA41 RDC_MREA_REG(RDC_BASE_PTR,41) +#define RDC_MRC41 RDC_MRC_REG(RDC_BASE_PTR,41) +#define RDC_MRVS41 RDC_MRVS_REG(RDC_BASE_PTR,41) +#define RDC_MRSA42 RDC_MRSA_REG(RDC_BASE_PTR,42) +#define RDC_MREA42 RDC_MREA_REG(RDC_BASE_PTR,42) +#define RDC_MRC42 RDC_MRC_REG(RDC_BASE_PTR,42) +#define RDC_MRVS42 RDC_MRVS_REG(RDC_BASE_PTR,42) +#define RDC_MRSA43 RDC_MRSA_REG(RDC_BASE_PTR,43) +#define RDC_MREA43 RDC_MREA_REG(RDC_BASE_PTR,43) +#define RDC_MRC43 RDC_MRC_REG(RDC_BASE_PTR,43) +#define RDC_MRVS43 RDC_MRVS_REG(RDC_BASE_PTR,43) +#define RDC_MRSA44 RDC_MRSA_REG(RDC_BASE_PTR,44) +#define RDC_MREA44 RDC_MREA_REG(RDC_BASE_PTR,44) +#define RDC_MRC44 RDC_MRC_REG(RDC_BASE_PTR,44) +#define RDC_MRVS44 RDC_MRVS_REG(RDC_BASE_PTR,44) +#define RDC_MRSA45 RDC_MRSA_REG(RDC_BASE_PTR,45) +#define RDC_MREA45 RDC_MREA_REG(RDC_BASE_PTR,45) +#define RDC_MRC45 RDC_MRC_REG(RDC_BASE_PTR,45) +#define RDC_MRVS45 RDC_MRVS_REG(RDC_BASE_PTR,45) +#define RDC_MRSA46 RDC_MRSA_REG(RDC_BASE_PTR,46) +#define RDC_MREA46 RDC_MREA_REG(RDC_BASE_PTR,46) +#define RDC_MRC46 RDC_MRC_REG(RDC_BASE_PTR,46) +#define RDC_MRVS46 RDC_MRVS_REG(RDC_BASE_PTR,46) +#define RDC_MRSA47 RDC_MRSA_REG(RDC_BASE_PTR,47) +#define RDC_MREA47 RDC_MREA_REG(RDC_BASE_PTR,47) +#define RDC_MRC47 RDC_MRC_REG(RDC_BASE_PTR,47) +#define RDC_MRVS47 RDC_MRVS_REG(RDC_BASE_PTR,47) +#define RDC_MRSA48 RDC_MRSA_REG(RDC_BASE_PTR,48) +#define RDC_MREA48 RDC_MREA_REG(RDC_BASE_PTR,48) +#define RDC_MRC48 RDC_MRC_REG(RDC_BASE_PTR,48) +#define RDC_MRVS48 RDC_MRVS_REG(RDC_BASE_PTR,48) +#define RDC_MRSA49 RDC_MRSA_REG(RDC_BASE_PTR,49) +#define RDC_MREA49 RDC_MREA_REG(RDC_BASE_PTR,49) +#define RDC_MRC49 RDC_MRC_REG(RDC_BASE_PTR,49) +#define RDC_MRVS49 RDC_MRVS_REG(RDC_BASE_PTR,49) +#define RDC_MRSA50 RDC_MRSA_REG(RDC_BASE_PTR,50) +#define RDC_MREA50 RDC_MREA_REG(RDC_BASE_PTR,50) +#define RDC_MRC50 RDC_MRC_REG(RDC_BASE_PTR,50) +#define RDC_MRVS50 RDC_MRVS_REG(RDC_BASE_PTR,50) +#define RDC_MRSA51 RDC_MRSA_REG(RDC_BASE_PTR,51) +#define RDC_MREA51 RDC_MREA_REG(RDC_BASE_PTR,51) +#define RDC_MRC51 RDC_MRC_REG(RDC_BASE_PTR,51) +#define RDC_MRVS51 RDC_MRVS_REG(RDC_BASE_PTR,51) + +/* RDC - Register array accessors */ +#define RDC_MDA(index) RDC_MDA_REG(RDC_BASE_PTR,index) +#define RDC_PDAP(index) RDC_PDAP_REG(RDC_BASE_PTR,index) +#define RDC_MRSA(index) RDC_MRSA_REG(RDC_BASE_PTR,index) +#define RDC_MREA(index) RDC_MREA_REG(RDC_BASE_PTR,index) +#define RDC_MRC(index) RDC_MRC_REG(RDC_BASE_PTR,index) +#define RDC_MRVS(index) RDC_MRVS_REG(RDC_BASE_PTR,index) + +/* MANUAL: RDC ID definition */ +#define RDC_MDA_M4_CORE_ID (1) + +#define RDC_PDAP_GPIO1_ID (0) +#define RDC_PDAP_GPIO2_ID (1) +#define RDC_PDAP_GPIO3_ID (2) +#define RDC_PDAP_GPIO4_ID (3) +#define RDC_PDAP_GPIO5_ID (4) +#define RDC_PDAP_GPIO6_ID (5) +#define RDC_PDAP_GPIO7_ID (6) +#define RDC_PDAP_WDOG3_ID (10) +#define RDC_PDAP_GPT3_ID (15) +#define RDC_PDAP_GPT4_ID (16) +#define RDC_PDAP_ADC1_ID (33) +#define RDC_PDAP_ADC2_ID (34) +#define RDC_PDAP_CAN1_ID (64) +#define RDC_PDAP_CAN2_ID (65) +#define RDC_PDAP_ECSPI1_ID (98) +#define RDC_PDAP_ECSPI2_ID (99) +#define RDC_PDAP_UART2_ID (105) + +/** + * @brief Memory region map register indices + * + * RDC MRxx register indices for memories/ports + */ +#define RDC_MR_MMDC_0_ID (0) +#define RDC_MR_MMDC_1_ID (1) +#define RDC_MR_MMDC_2_ID (2) +#define RDC_MR_MMDC_3_ID (3) +#define RDC_MR_MMDC_4_ID (4) +#define RDC_MR_MMDC_5_ID (5) +#define RDC_MR_MMDC_6_ID (6) +#define RDC_MR_MMDC_7_ID (7) +#define RDC_MR_QSPI_0_ID (8) +#define RDC_MR_QSPI_1_ID (9) +#define RDC_MR_QSPI_2_ID (10) +#define RDC_MR_QSPI_3_ID (11) +#define RDC_MR_QSPI_4_ID (12) +#define RDC_MR_QSPI_5_ID (13) +#define RDC_MR_QSPI_6_ID (14) +#define RDC_MR_QSPI_7_ID (15) +#define RDC_MR_WEIM_0_ID (16) +#define RDC_MR_WEIM_1_ID (17) +#define RDC_MR_WEIM_2_ID (18) +#define RDC_MR_WEIM_3_ID (19) +#define RDC_MR_WEIM_4_ID (20) +#define RDC_MR_WEIM_5_ID (21) +#define RDC_MR_WEIM_6_ID (22) +#define RDC_MR_WEIM_7_ID (23) +#define RDC_MR_PCIe_0_ID (24) +#define RDC_MR_PCIe_1_ID (25) +#define RDC_MR_PCIe_2_ID (26) +#define RDC_MR_PCIe_3_ID (27) +#define RDC_MR_PCIe_4_ID (28) +#define RDC_MR_PCIe_5_ID (29) +#define RDC_MR_PCIe_6_ID (30) +#define RDC_MR_PCIe_7_ID (31) +#define RDC_MR_OCRAM_0_ID (32) +#define RDC_MR_OCRAM_1_ID (33) +#define RDC_MR_OCRAM_2_ID (34) +#define RDC_MR_OCRAM_3_ID (35) +#define RDC_MR_OCRAM_4_ID (36) +#define RDC_MR_OCRAM_S_0_ID (37) +#define RDC_MR_OCRAM_S_1_ID (38) +#define RDC_MR_OCRAM_S_2_ID (39) +#define RDC_MR_OCRAM_S_3_ID (40) +#define RDC_MR_OCRAM_S_4_ID (41) +#define RDC_MR_OCRAM_EPDC_0_ID (42) +#define RDC_MR_OCRAM_EPDC_1_ID (43) +#define RDC_MR_OCRAM_EPDC_2_ID (44) +#define RDC_MR_OCRAM_EPDC_3_ID (45) +#define RDC_MR_OCRAM_EPDC_4_ID (46) +#define RDC_MR_OCRAM_PXP_0_ID (47) +#define RDC_MR_OCRAM_PXP_1_ID (48) +#define RDC_MR_OCRAM_PXP_2_ID (49) +#define RDC_MR_OCRAM_PXP_3_ID (50) +#define RDC_MR_OCRAM_PXP_4_ID (51) + +/*! + * @} + */ /* end of group RDC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group RDC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer + * @{ + */ + +/** RDC_SEMAPHORE - Register Layout Typedef */ +typedef struct { + __IO uint8_t GATE[64]; /**< Gate Register, array offset: 0x0, array step: 0x1 */ + union { /* offset: 0x40 */ + __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */ + __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ + }; +} RDC_SEMAPHORE_Type, *RDC_SEMAPHORE_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros + * @{ + */ + + +/* RDC_SEMAPHORE - Register accessors */ +#define RDC_SEMAPHORE_GATE_REG(base,index) ((base)->GATE[index]) +#define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) +#define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks + * @{ + */ + +/* GATE Bit Fields */ +#define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu +#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 +#define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_GTFSM_SHIFT))&RDC_SEMAPHORE_GATE_GTFSM_MASK) +#define RDC_SEMAPHORE_GATE_LDOM_MASK 0x60u +#define RDC_SEMAPHORE_GATE_LDOM_SHIFT 5 +#define RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x))<<RDC_SEMAPHORE_GATE_LDOM_SHIFT))&RDC_SEMAPHORE_GATE_LDOM_MASK) +/* RSTGT_R Bit Fields */ +#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK 0xFu +#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT 0 +#define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK) +#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK 0x30u +#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT 4 +#define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) +#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK 0xFF00u +#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT 8 +#define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) +/* RSTGT_W Bit Fields */ +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK 0xFFu +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT 0 +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK 0xFF00u +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT 8 +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT))&RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Masks */ + + +/* RDC_SEMAPHORE - Peripheral instance base addresses */ +/** Peripheral RDC_SEMAPHORE1 base address */ +#define RDC_SEMAPHORE1_BASE (0x303B0000u) +/** Peripheral RDC_SEMAPHORE1 base pointer */ +#define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE) +#define RDC_SEMAPHORE1_BASE_PTR (RDC_SEMAPHORE1) +/** Peripheral RDC_SEMAPHORE2 base address */ +#define RDC_SEMAPHORE2_BASE (0x303C0000u) +/** Peripheral RDC_SEMAPHORE2 base pointer */ +#define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE) +#define RDC_SEMAPHORE2_BASE_PTR (RDC_SEMAPHORE2) +/** Array initializer of RDC_SEMAPHORE peripheral base adresses */ +#define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE } +/** Array initializer of RDC_SEMAPHORE peripheral base pointers */ +#define RDC_SEMAPHORE_BASE_PTRS { RDC_SEMAPHORE1, RDC_SEMAPHORE2 } + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Accessor_Macros RDC_SEMAPHORE - Register accessor macros + * @{ + */ + + +/* RDC_SEMAPHORE - Register instance definitions */ +/* RDC_SEMAPHORE1 */ +#define RDC_SEMAPHORE1_GATE0 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,0) +#define RDC_SEMAPHORE1_GATE1 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,1) +#define RDC_SEMAPHORE1_GATE2 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,2) +#define RDC_SEMAPHORE1_GATE3 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,3) +#define RDC_SEMAPHORE1_GATE4 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,4) +#define RDC_SEMAPHORE1_GATE5 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,5) +#define RDC_SEMAPHORE1_GATE6 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,6) +#define RDC_SEMAPHORE1_GATE7 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,7) +#define RDC_SEMAPHORE1_GATE8 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,8) +#define RDC_SEMAPHORE1_GATE9 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,9) +#define RDC_SEMAPHORE1_GATE10 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,10) +#define RDC_SEMAPHORE1_GATE11 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,11) +#define RDC_SEMAPHORE1_GATE12 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,12) +#define RDC_SEMAPHORE1_GATE13 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,13) +#define RDC_SEMAPHORE1_GATE14 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,14) +#define RDC_SEMAPHORE1_GATE15 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,15) +#define RDC_SEMAPHORE1_GATE16 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,16) +#define RDC_SEMAPHORE1_GATE17 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,17) +#define RDC_SEMAPHORE1_GATE18 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,18) +#define RDC_SEMAPHORE1_GATE19 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,19) +#define RDC_SEMAPHORE1_GATE20 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,20) +#define RDC_SEMAPHORE1_GATE21 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,21) +#define RDC_SEMAPHORE1_GATE22 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,22) +#define RDC_SEMAPHORE1_GATE23 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,23) +#define RDC_SEMAPHORE1_GATE24 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,24) +#define RDC_SEMAPHORE1_GATE25 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,25) +#define RDC_SEMAPHORE1_GATE26 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,26) +#define RDC_SEMAPHORE1_GATE27 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,27) +#define RDC_SEMAPHORE1_GATE28 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,28) +#define RDC_SEMAPHORE1_GATE29 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,29) +#define RDC_SEMAPHORE1_GATE30 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,30) +#define RDC_SEMAPHORE1_GATE31 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,31) +#define RDC_SEMAPHORE1_GATE32 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,32) +#define RDC_SEMAPHORE1_GATE33 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,33) +#define RDC_SEMAPHORE1_GATE34 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,34) +#define RDC_SEMAPHORE1_GATE35 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,35) +#define RDC_SEMAPHORE1_GATE36 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,36) +#define RDC_SEMAPHORE1_GATE37 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,37) +#define RDC_SEMAPHORE1_GATE38 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,38) +#define RDC_SEMAPHORE1_GATE39 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,39) +#define RDC_SEMAPHORE1_GATE40 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,40) +#define RDC_SEMAPHORE1_GATE41 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,41) +#define RDC_SEMAPHORE1_GATE42 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,42) +#define RDC_SEMAPHORE1_GATE43 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,43) +#define RDC_SEMAPHORE1_GATE44 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,44) +#define RDC_SEMAPHORE1_GATE45 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,45) +#define RDC_SEMAPHORE1_GATE46 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,46) +#define RDC_SEMAPHORE1_GATE47 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,47) +#define RDC_SEMAPHORE1_GATE48 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,48) +#define RDC_SEMAPHORE1_GATE49 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,49) +#define RDC_SEMAPHORE1_GATE50 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,50) +#define RDC_SEMAPHORE1_GATE51 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,51) +#define RDC_SEMAPHORE1_GATE52 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,52) +#define RDC_SEMAPHORE1_GATE53 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,53) +#define RDC_SEMAPHORE1_GATE54 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,54) +#define RDC_SEMAPHORE1_GATE55 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,55) +#define RDC_SEMAPHORE1_GATE56 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,56) +#define RDC_SEMAPHORE1_GATE57 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,57) +#define RDC_SEMAPHORE1_GATE58 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,58) +#define RDC_SEMAPHORE1_GATE59 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,59) +#define RDC_SEMAPHORE1_GATE60 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,60) +#define RDC_SEMAPHORE1_GATE61 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,61) +#define RDC_SEMAPHORE1_GATE62 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,62) +#define RDC_SEMAPHORE1_GATE63 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,63) +#define RDC_SEMAPHORE1_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE1_BASE_PTR) +#define RDC_SEMAPHORE1_RSTGT_W RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE1_BASE_PTR) +/* RDC_SEMAPHORE2 */ +#define RDC_SEMAPHORE2_GATE0 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,0) +#define RDC_SEMAPHORE2_GATE1 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,1) +#define RDC_SEMAPHORE2_GATE2 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,2) +#define RDC_SEMAPHORE2_GATE3 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,3) +#define RDC_SEMAPHORE2_GATE4 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,4) +#define RDC_SEMAPHORE2_GATE5 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,5) +#define RDC_SEMAPHORE2_GATE6 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,6) +#define RDC_SEMAPHORE2_GATE7 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,7) +#define RDC_SEMAPHORE2_GATE8 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,8) +#define RDC_SEMAPHORE2_GATE9 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,9) +#define RDC_SEMAPHORE2_GATE10 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,10) +#define RDC_SEMAPHORE2_GATE11 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,11) +#define RDC_SEMAPHORE2_GATE12 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,12) +#define RDC_SEMAPHORE2_GATE13 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,13) +#define RDC_SEMAPHORE2_GATE14 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,14) +#define RDC_SEMAPHORE2_GATE15 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,15) +#define RDC_SEMAPHORE2_GATE16 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,16) +#define RDC_SEMAPHORE2_GATE17 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,17) +#define RDC_SEMAPHORE2_GATE18 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,18) +#define RDC_SEMAPHORE2_GATE19 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,19) +#define RDC_SEMAPHORE2_GATE20 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,20) +#define RDC_SEMAPHORE2_GATE21 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,21) +#define RDC_SEMAPHORE2_GATE22 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,22) +#define RDC_SEMAPHORE2_GATE23 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,23) +#define RDC_SEMAPHORE2_GATE24 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,24) +#define RDC_SEMAPHORE2_GATE25 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,25) +#define RDC_SEMAPHORE2_GATE26 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,26) +#define RDC_SEMAPHORE2_GATE27 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,27) +#define RDC_SEMAPHORE2_GATE28 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,28) +#define RDC_SEMAPHORE2_GATE29 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,29) +#define RDC_SEMAPHORE2_GATE30 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,30) +#define RDC_SEMAPHORE2_GATE31 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,31) +#define RDC_SEMAPHORE2_GATE32 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,32) +#define RDC_SEMAPHORE2_GATE33 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,33) +#define RDC_SEMAPHORE2_GATE34 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,34) +#define RDC_SEMAPHORE2_GATE35 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,35) +#define RDC_SEMAPHORE2_GATE36 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,36) +#define RDC_SEMAPHORE2_GATE37 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,37) +#define RDC_SEMAPHORE2_GATE38 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,38) +#define RDC_SEMAPHORE2_GATE39 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,39) +#define RDC_SEMAPHORE2_GATE40 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,40) +#define RDC_SEMAPHORE2_GATE41 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,41) +#define RDC_SEMAPHORE2_GATE42 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,42) +#define RDC_SEMAPHORE2_GATE43 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,43) +#define RDC_SEMAPHORE2_GATE44 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,44) +#define RDC_SEMAPHORE2_GATE45 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,45) +#define RDC_SEMAPHORE2_GATE46 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,46) +#define RDC_SEMAPHORE2_GATE47 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,47) +#define RDC_SEMAPHORE2_GATE48 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,48) +#define RDC_SEMAPHORE2_GATE49 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,49) +#define RDC_SEMAPHORE2_GATE50 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,50) +#define RDC_SEMAPHORE2_GATE51 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,51) +#define RDC_SEMAPHORE2_GATE52 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,52) +#define RDC_SEMAPHORE2_GATE53 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,53) +#define RDC_SEMAPHORE2_GATE54 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,54) +#define RDC_SEMAPHORE2_GATE55 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,55) +#define RDC_SEMAPHORE2_GATE56 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,56) +#define RDC_SEMAPHORE2_GATE57 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,57) +#define RDC_SEMAPHORE2_GATE58 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,58) +#define RDC_SEMAPHORE2_GATE59 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,59) +#define RDC_SEMAPHORE2_GATE60 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,60) +#define RDC_SEMAPHORE2_GATE61 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,61) +#define RDC_SEMAPHORE2_GATE62 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,62) +#define RDC_SEMAPHORE2_GATE63 RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,63) +#define RDC_SEMAPHORE2_RSTGT_R RDC_SEMAPHORE_RSTGT_R_REG(RDC_SEMAPHORE2_BASE_PTR) +#define RDC_SEMAPHORE2_RSTGT_W RDC_SEMAPHORE_RSTGT_W_REG(RDC_SEMAPHORE2_BASE_PTR) + +/* RDC_SEMAPHORE - Register array accessors */ +#define RDC_SEMAPHORE1_GATE(index) RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE1_BASE_PTR,index) +#define RDC_SEMAPHORE2_GATE(index) RDC_SEMAPHORE_GATE_REG(RDC_SEMAPHORE2_BASE_PTR,index) + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + __I uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type, *ROMC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ROMC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros + * @{ + */ + + +/* ROMC - Register accessors */ +#define ROMC_ROMPATCHD_REG(base,index) ((base)->ROMPATCHD[index]) +#define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) +#define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) +#define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) +#define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) +#define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) + +/*! + * @} + */ /* end of group ROMC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/* ROMPATCHD Bit Fields */ +#define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu +#define ROMC_ROMPATCHD_DATAX_SHIFT 0 +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHD_DATAX_SHIFT))&ROMC_ROMPATCHD_DATAX_MASK) +/* ROMPATCHCNTL Bit Fields */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK 0xFFu +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT 0 +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHCNTL_DATAFIX_SHIFT))&ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK 0x20000000u +#define ROMC_ROMPATCHCNTL_DIS_SHIFT 29 +/* ROMPATCHENL Bit Fields */ +#define ROMC_ROMPATCHENL_ENABLE_MASK 0xFFFFu +#define ROMC_ROMPATCHENL_ENABLE_SHIFT 0 +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHENL_ENABLE_SHIFT))&ROMC_ROMPATCHENL_ENABLE_MASK) +/* ROMPATCHA Bit Fields */ +#define ROMC_ROMPATCHA_THUMBX_MASK 0x1u +#define ROMC_ROMPATCHA_THUMBX_SHIFT 0 +#define ROMC_ROMPATCHA_ADDRX_MASK 0x7FFFFEu +#define ROMC_ROMPATCHA_ADDRX_SHIFT 1 +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHA_ADDRX_SHIFT))&ROMC_ROMPATCHA_ADDRX_MASK) +/* ROMPATCHSR Bit Fields */ +#define ROMC_ROMPATCHSR_SOURCE_MASK 0x3Fu +#define ROMC_ROMPATCHSR_SOURCE_SHIFT 0 +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x))<<ROMC_ROMPATCHSR_SOURCE_SHIFT))&ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK 0x20000u +#define ROMC_ROMPATCHSR_SW_SHIFT 17 + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x30310000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +#define ROMC_BASE_PTR (ROMC) +/** Array initializer of ROMC peripheral base adresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/* ---------------------------------------------------------------------------- + -- ROMC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Accessor_Macros ROMC - Register accessor macros + * @{ + */ + + +/* ROMC - Register instance definitions */ +/* ROMC */ +#define ROMC_ROMPATCH0D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,0) +#define ROMC_ROMPATCH1D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,1) +#define ROMC_ROMPATCH2D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,2) +#define ROMC_ROMPATCH3D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,3) +#define ROMC_ROMPATCH4D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,4) +#define ROMC_ROMPATCH5D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,5) +#define ROMC_ROMPATCH6D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,6) +#define ROMC_ROMPATCH7D ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,7) +#define ROMC_ROMPATCHCNTL ROMC_ROMPATCHCNTL_REG(ROMC_BASE_PTR) +#define ROMC_ROMPATCHENH ROMC_ROMPATCHENH_REG(ROMC_BASE_PTR) +#define ROMC_ROMPATCHENL ROMC_ROMPATCHENL_REG(ROMC_BASE_PTR) +#define ROMC_ROMPATCH0A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,0) +#define ROMC_ROMPATCH1A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,1) +#define ROMC_ROMPATCH2A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,2) +#define ROMC_ROMPATCH3A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,3) +#define ROMC_ROMPATCH4A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,4) +#define ROMC_ROMPATCH5A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,5) +#define ROMC_ROMPATCH6A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,6) +#define ROMC_ROMPATCH7A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,7) +#define ROMC_ROMPATCH8A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,8) +#define ROMC_ROMPATCH9A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,9) +#define ROMC_ROMPATCH10A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,10) +#define ROMC_ROMPATCH11A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,11) +#define ROMC_ROMPATCH12A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,12) +#define ROMC_ROMPATCH13A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,13) +#define ROMC_ROMPATCH14A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,14) +#define ROMC_ROMPATCH15A ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,15) +#define ROMC_ROMPATCHSR ROMC_ROMPATCHSR_REG(ROMC_BASE_PTR) + +/* ROMC - Register array accessors */ +#define ROMC_ROMPATCHD(index) ROMC_ROMPATCHD_REG(ROMC_BASE_PTR,index) +#define ROMC_ROMPATCHA(index) ROMC_ROMPATCHA_REG(ROMC_BASE_PTR,index) + +/*! + * @} + */ /* end of group ROMC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group ROMC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SDMAARM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer + * @{ + */ + +/** SDMAARM - Register Layout Typedef */ +typedef struct { + __IO uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ + __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ + __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ + __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ + __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ + __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ + __IO uint32_t HOSTOVR; /**< Channel ARM platform Override, offset: 0x18 */ + __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ + uint8_t RESERVED_0[4]; + __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ + __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ + __IO uint32_t INTRMASK; /**< Channel ARM platform Interrupt Mask, offset: 0x2C */ + __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ + __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ + __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ + __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ + __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ + __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ + __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ + __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ + __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ + __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ + __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ + __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ + __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ + uint8_t RESERVED_3[136]; + __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_4[128]; + __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ +} SDMAARM_Type, *SDMAARM_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SDMAARM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros + * @{ + */ + + +/* SDMAARM - Register accessors */ +#define SDMAARM_MC0PTR_REG(base) ((base)->MC0PTR) +#define SDMAARM_INTR_REG(base) ((base)->INTR) +#define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMAARM_HSTART_REG(base) ((base)->HSTART) +#define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) +#define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) +#define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) +#define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) +#define SDMAARM_RESET_REG(base) ((base)->RESET) +#define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) +#define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMAARM_PSW_REG(base) ((base)->PSW) +#define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) +#define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) +#define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) +#define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) +#define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) +#define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) +#define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) +#define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) +#define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) +#define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) +#define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) +#define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) +#define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) +#define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) +#define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) +#define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) + +/*! + * @} + */ /* end of group SDMAARM_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/* MC0PTR Bit Fields */ +#define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_MC0PTR_MC0PTR_SHIFT))&SDMAARM_MC0PTR_MC0PTR_MASK) +/* INTR Bit Fields */ +#define SDMAARM_INTR_HI_MASK 0xFFFFFFFFu +#define SDMAARM_INTR_HI_SHIFT 0 +#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTR_HI_SHIFT))&SDMAARM_INTR_HI_MASK) +/* STOP_STAT Bit Fields */ +#define SDMAARM_STOP_STAT_HE_MASK 0xFFFFFFFFu +#define SDMAARM_STOP_STAT_HE_SHIFT 0 +#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_STOP_STAT_HE_SHIFT))&SDMAARM_STOP_STAT_HE_MASK) +/* HSTART Bit Fields */ +#define SDMAARM_HSTART_HSTART_HE_MASK 0xFFFFFFFFu +#define SDMAARM_HSTART_HSTART_HE_SHIFT 0 +#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_HSTART_HSTART_HE_SHIFT))&SDMAARM_HSTART_HSTART_HE_MASK) +/* EVTOVR Bit Fields */ +#define SDMAARM_EVTOVR_EO_MASK 0xFFFFFFFFu +#define SDMAARM_EVTOVR_EO_SHIFT 0 +#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTOVR_EO_SHIFT))&SDMAARM_EVTOVR_EO_MASK) +/* DSPOVR Bit Fields */ +#define SDMAARM_DSPOVR_DO_MASK 0xFFFFFFFFu +#define SDMAARM_DSPOVR_DO_SHIFT 0 +#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_DSPOVR_DO_SHIFT))&SDMAARM_DSPOVR_DO_MASK) +/* HOSTOVR Bit Fields */ +#define SDMAARM_HOSTOVR_HO_MASK 0xFFFFFFFFu +#define SDMAARM_HOSTOVR_HO_SHIFT 0 +#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_HOSTOVR_HO_SHIFT))&SDMAARM_HOSTOVR_HO_MASK) +/* EVTPEND Bit Fields */ +#define SDMAARM_EVTPEND_EP_MASK 0xFFFFFFFFu +#define SDMAARM_EVTPEND_EP_SHIFT 0 +#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTPEND_EP_SHIFT))&SDMAARM_EVTPEND_EP_MASK) +/* RESET Bit Fields */ +#define SDMAARM_RESET_RESET_MASK 0x1u +#define SDMAARM_RESET_RESET_SHIFT 0 +#define SDMAARM_RESET_RESCHED_MASK 0x2u +#define SDMAARM_RESET_RESCHED_SHIFT 1 +/* EVTERR Bit Fields */ +#define SDMAARM_EVTERR_CHNERR_MASK 0xFFFFFFFFu +#define SDMAARM_EVTERR_CHNERR_SHIFT 0 +#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERR_CHNERR_SHIFT))&SDMAARM_EVTERR_CHNERR_MASK) +/* INTRMASK Bit Fields */ +#define SDMAARM_INTRMASK_HIMASK_MASK 0xFFFFFFFFu +#define SDMAARM_INTRMASK_HIMASK_SHIFT 0 +#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_INTRMASK_HIMASK_SHIFT))&SDMAARM_INTRMASK_HIMASK_MASK) +/* PSW Bit Fields */ +#define SDMAARM_PSW_CCR_MASK 0xFu +#define SDMAARM_PSW_CCR_SHIFT 0 +#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCR_SHIFT))&SDMAARM_PSW_CCR_MASK) +#define SDMAARM_PSW_CCP_MASK 0xF0u +#define SDMAARM_PSW_CCP_SHIFT 4 +#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_CCP_SHIFT))&SDMAARM_PSW_CCP_MASK) +#define SDMAARM_PSW_NCR_MASK 0x1F00u +#define SDMAARM_PSW_NCR_SHIFT 8 +#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCR_SHIFT))&SDMAARM_PSW_NCR_MASK) +#define SDMAARM_PSW_NCP_MASK 0xE000u +#define SDMAARM_PSW_NCP_SHIFT 13 +#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_PSW_NCP_SHIFT))&SDMAARM_PSW_NCP_MASK) +/* EVTERRDBG Bit Fields */ +#define SDMAARM_EVTERRDBG_CHNERR_MASK 0xFFFFFFFFu +#define SDMAARM_EVTERRDBG_CHNERR_SHIFT 0 +#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVTERRDBG_CHNERR_SHIFT))&SDMAARM_EVTERRDBG_CHNERR_MASK) +/* CONFIG Bit Fields */ +#define SDMAARM_CONFIG_CSM_MASK 0x3u +#define SDMAARM_CONFIG_CSM_SHIFT 0 +#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_CONFIG_CSM_SHIFT))&SDMAARM_CONFIG_CSM_MASK) +#define SDMAARM_CONFIG_ACR_MASK 0x10u +#define SDMAARM_CONFIG_ACR_SHIFT 4 +#define SDMAARM_CONFIG_RTDOBS_MASK 0x800u +#define SDMAARM_CONFIG_RTDOBS_SHIFT 11 +#define SDMAARM_CONFIG_DSPDMA_MASK 0x1000u +#define SDMAARM_CONFIG_DSPDMA_SHIFT 12 +/* SDMA_LOCK Bit Fields */ +#define SDMAARM_SDMA_LOCK_LOCK_MASK 0x1u +#define SDMAARM_SDMA_LOCK_LOCK_SHIFT 0 +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK 0x2u +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT 1 +/* ONCE_ENB Bit Fields */ +#define SDMAARM_ONCE_ENB_ENB_MASK 0x1u +#define SDMAARM_ONCE_ENB_ENB_SHIFT 0 +/* ONCE_DATA Bit Fields */ +#define SDMAARM_ONCE_DATA_DATA_MASK 0xFFFFFFFFu +#define SDMAARM_ONCE_DATA_DATA_SHIFT 0 +#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_DATA_DATA_SHIFT))&SDMAARM_ONCE_DATA_DATA_MASK) +/* ONCE_INSTR Bit Fields */ +#define SDMAARM_ONCE_INSTR_INSTR_MASK 0xFFFFu +#define SDMAARM_ONCE_INSTR_INSTR_SHIFT 0 +#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_INSTR_INSTR_SHIFT))&SDMAARM_ONCE_INSTR_INSTR_MASK) +/* ONCE_STAT Bit Fields */ +#define SDMAARM_ONCE_STAT_ECDR_MASK 0x7u +#define SDMAARM_ONCE_STAT_ECDR_SHIFT 0 +#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_ECDR_SHIFT))&SDMAARM_ONCE_STAT_ECDR_MASK) +#define SDMAARM_ONCE_STAT_MST_MASK 0x80u +#define SDMAARM_ONCE_STAT_MST_SHIFT 7 +#define SDMAARM_ONCE_STAT_SWB_MASK 0x100u +#define SDMAARM_ONCE_STAT_SWB_SHIFT 8 +#define SDMAARM_ONCE_STAT_ODR_MASK 0x200u +#define SDMAARM_ONCE_STAT_ODR_SHIFT 9 +#define SDMAARM_ONCE_STAT_EDR_MASK 0x400u +#define SDMAARM_ONCE_STAT_EDR_SHIFT 10 +#define SDMAARM_ONCE_STAT_RCV_MASK 0x800u +#define SDMAARM_ONCE_STAT_RCV_SHIFT 11 +#define SDMAARM_ONCE_STAT_PST_MASK 0xF000u +#define SDMAARM_ONCE_STAT_PST_SHIFT 12 +#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_STAT_PST_SHIFT))&SDMAARM_ONCE_STAT_PST_MASK) +/* ONCE_CMD Bit Fields */ +#define SDMAARM_ONCE_CMD_CMD_MASK 0xFu +#define SDMAARM_ONCE_CMD_CMD_SHIFT 0 +#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ONCE_CMD_CMD_SHIFT))&SDMAARM_ONCE_CMD_CMD_MASK) +/* ILLINSTADDR Bit Fields */ +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK 0x3FFFu +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT 0 +#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT))&SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) +/* CHN0ADDR Bit Fields */ +#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK 0x3FFFu +#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT 0 +#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT))&SDMAARM_CHN0ADDR_CHN0ADDR_MASK) +#define SDMAARM_CHN0ADDR_SMSZ_MASK 0x4000u +#define SDMAARM_CHN0ADDR_SMSZ_SHIFT 14 +/* EVT_MIRROR Bit Fields */ +#define SDMAARM_EVT_MIRROR_EVENTS_MASK 0xFFFFFFFFu +#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT 0 +#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR_EVENTS_MASK) +/* EVT_MIRROR2 Bit Fields */ +#define SDMAARM_EVT_MIRROR2_EVENTS_MASK 0xFFFFu +#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT 0 +#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_EVT_MIRROR2_EVENTS_SHIFT))&SDMAARM_EVT_MIRROR2_EVENTS_MASK) +/* XTRIG_CONF1 Bit Fields */ +#define SDMAARM_XTRIG_CONF1_NUM0_MASK 0x3Fu +#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT 0 +#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM0_SHIFT))&SDMAARM_XTRIG_CONF1_NUM0_MASK) +#define SDMAARM_XTRIG_CONF1_CNF0_MASK 0x40u +#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT 6 +#define SDMAARM_XTRIG_CONF1_NUM1_MASK 0x3F00u +#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT 8 +#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM1_SHIFT))&SDMAARM_XTRIG_CONF1_NUM1_MASK) +#define SDMAARM_XTRIG_CONF1_CNF1_MASK 0x4000u +#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT 14 +#define SDMAARM_XTRIG_CONF1_NUM2_MASK 0x3F0000u +#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT 16 +#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM2_SHIFT))&SDMAARM_XTRIG_CONF1_NUM2_MASK) +#define SDMAARM_XTRIG_CONF1_CNF2_MASK 0x400000u +#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT 22 +#define SDMAARM_XTRIG_CONF1_NUM3_MASK 0x3F000000u +#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT 24 +#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF1_NUM3_SHIFT))&SDMAARM_XTRIG_CONF1_NUM3_MASK) +#define SDMAARM_XTRIG_CONF1_CNF3_MASK 0x40000000u +#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT 30 +/* XTRIG_CONF2 Bit Fields */ +#define SDMAARM_XTRIG_CONF2_NUM4_MASK 0x3Fu +#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT 0 +#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM4_SHIFT))&SDMAARM_XTRIG_CONF2_NUM4_MASK) +#define SDMAARM_XTRIG_CONF2_CNF4_MASK 0x40u +#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT 6 +#define SDMAARM_XTRIG_CONF2_NUM5_MASK 0x3F00u +#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT 8 +#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM5_SHIFT))&SDMAARM_XTRIG_CONF2_NUM5_MASK) +#define SDMAARM_XTRIG_CONF2_CNF5_MASK 0x4000u +#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT 14 +#define SDMAARM_XTRIG_CONF2_NUM6_MASK 0x3F0000u +#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT 16 +#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM6_SHIFT))&SDMAARM_XTRIG_CONF2_NUM6_MASK) +#define SDMAARM_XTRIG_CONF2_CNF6_MASK 0x400000u +#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT 22 +#define SDMAARM_XTRIG_CONF2_NUM7_MASK 0x3F000000u +#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT 24 +#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_XTRIG_CONF2_NUM7_SHIFT))&SDMAARM_XTRIG_CONF2_NUM7_MASK) +#define SDMAARM_XTRIG_CONF2_CNF7_MASK 0x40000000u +#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT 30 +/* SDMA_CHNPRI Bit Fields */ +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK 0x7u +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT 0 +#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT))&SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) +/* CHNENBL Bit Fields */ +#define SDMAARM_CHNENBL_ENBLn_MASK 0xFFFFFFFFu +#define SDMAARM_CHNENBL_ENBLn_SHIFT 0 +#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x))<<SDMAARM_CHNENBL_ENBLn_SHIFT))&SDMAARM_CHNENBL_ENBLn_MASK) + +/*! + * @} + */ /* end of group SDMAARM_Register_Masks */ + + +/* SDMAARM - Peripheral instance base addresses */ +/** Peripheral SDMAARM base address */ +#define SDMAARM_BASE (0x30BD0000u) +/** Peripheral SDMAARM base pointer */ +#define SDMAARM ((SDMAARM_Type *)SDMAARM_BASE) +#define SDMAARM_BASE_PTR (SDMAARM) +/** Array initializer of SDMAARM peripheral base adresses */ +#define SDMAARM_BASE_ADDRS { SDMAARM_BASE } +/** Array initializer of SDMAARM peripheral base pointers */ +#define SDMAARM_BASE_PTRS { SDMAARM } + +/* ---------------------------------------------------------------------------- + -- SDMAARM - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Accessor_Macros SDMAARM - Register accessor macros + * @{ + */ + + +/* SDMAARM - Register instance definitions */ +/* SDMAARM */ +#define SDMAARM_MC0PTR SDMAARM_MC0PTR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_INTR SDMAARM_INTR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_STOP_STAT SDMAARM_STOP_STAT_REG(SDMAARM_BASE_PTR) +#define SDMAARM_HSTART SDMAARM_HSTART_REG(SDMAARM_BASE_PTR) +#define SDMAARM_EVTOVR SDMAARM_EVTOVR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_DSPOVR SDMAARM_DSPOVR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_HOSTOVR SDMAARM_HOSTOVR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_EVTPEND SDMAARM_EVTPEND_REG(SDMAARM_BASE_PTR) +#define SDMAARM_RESET SDMAARM_RESET_REG(SDMAARM_BASE_PTR) +#define SDMAARM_EVTERR SDMAARM_EVTERR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_INTRMASK SDMAARM_INTRMASK_REG(SDMAARM_BASE_PTR) +#define SDMAARM_PSW SDMAARM_PSW_REG(SDMAARM_BASE_PTR) +#define SDMAARM_EVTERRDBG SDMAARM_EVTERRDBG_REG(SDMAARM_BASE_PTR) +#define SDMAARM_CONFIG SDMAARM_CONFIG_REG(SDMAARM_BASE_PTR) +#define SDMAARM_SDMA_LOCK SDMAARM_SDMA_LOCK_REG(SDMAARM_BASE_PTR) +#define SDMAARM_ONCE_ENB SDMAARM_ONCE_ENB_REG(SDMAARM_BASE_PTR) +#define SDMAARM_ONCE_DATA SDMAARM_ONCE_DATA_REG(SDMAARM_BASE_PTR) +#define SDMAARM_ONCE_INSTR SDMAARM_ONCE_INSTR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_ONCE_STAT SDMAARM_ONCE_STAT_REG(SDMAARM_BASE_PTR) +#define SDMAARM_ONCE_CMD SDMAARM_ONCE_CMD_REG(SDMAARM_BASE_PTR) +#define SDMAARM_ILLINSTADDR SDMAARM_ILLINSTADDR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_CHN0ADDR SDMAARM_CHN0ADDR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_EVT_MIRROR SDMAARM_EVT_MIRROR_REG(SDMAARM_BASE_PTR) +#define SDMAARM_EVT_MIRROR2 SDMAARM_EVT_MIRROR2_REG(SDMAARM_BASE_PTR) +#define SDMAARM_XTRIG_CONF1 SDMAARM_XTRIG_CONF1_REG(SDMAARM_BASE_PTR) +#define SDMAARM_XTRIG_CONF2 SDMAARM_XTRIG_CONF2_REG(SDMAARM_BASE_PTR) +#define SDMAARM_SDMA_CHNPRI0 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,0) +#define SDMAARM_SDMA_CHNPRI1 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,1) +#define SDMAARM_SDMA_CHNPRI2 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,2) +#define SDMAARM_SDMA_CHNPRI3 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,3) +#define SDMAARM_SDMA_CHNPRI4 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,4) +#define SDMAARM_SDMA_CHNPRI5 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,5) +#define SDMAARM_SDMA_CHNPRI6 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,6) +#define SDMAARM_SDMA_CHNPRI7 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,7) +#define SDMAARM_SDMA_CHNPRI8 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,8) +#define SDMAARM_SDMA_CHNPRI9 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,9) +#define SDMAARM_SDMA_CHNPRI10 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,10) +#define SDMAARM_SDMA_CHNPRI11 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,11) +#define SDMAARM_SDMA_CHNPRI12 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,12) +#define SDMAARM_SDMA_CHNPRI13 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,13) +#define SDMAARM_SDMA_CHNPRI14 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,14) +#define SDMAARM_SDMA_CHNPRI15 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,15) +#define SDMAARM_SDMA_CHNPRI16 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,16) +#define SDMAARM_SDMA_CHNPRI17 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,17) +#define SDMAARM_SDMA_CHNPRI18 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,18) +#define SDMAARM_SDMA_CHNPRI19 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,19) +#define SDMAARM_SDMA_CHNPRI20 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,20) +#define SDMAARM_SDMA_CHNPRI21 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,21) +#define SDMAARM_SDMA_CHNPRI22 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,22) +#define SDMAARM_SDMA_CHNPRI23 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,23) +#define SDMAARM_SDMA_CHNPRI24 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,24) +#define SDMAARM_SDMA_CHNPRI25 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,25) +#define SDMAARM_SDMA_CHNPRI26 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,26) +#define SDMAARM_SDMA_CHNPRI27 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,27) +#define SDMAARM_SDMA_CHNPRI28 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,28) +#define SDMAARM_SDMA_CHNPRI29 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,29) +#define SDMAARM_SDMA_CHNPRI30 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,30) +#define SDMAARM_SDMA_CHNPRI31 SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,31) +#define SDMAARM_CHNENBL0 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,0) +#define SDMAARM_CHNENBL1 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,1) +#define SDMAARM_CHNENBL2 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,2) +#define SDMAARM_CHNENBL3 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,3) +#define SDMAARM_CHNENBL4 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,4) +#define SDMAARM_CHNENBL5 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,5) +#define SDMAARM_CHNENBL6 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,6) +#define SDMAARM_CHNENBL7 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,7) +#define SDMAARM_CHNENBL8 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,8) +#define SDMAARM_CHNENBL9 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,9) +#define SDMAARM_CHNENBL10 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,10) +#define SDMAARM_CHNENBL11 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,11) +#define SDMAARM_CHNENBL12 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,12) +#define SDMAARM_CHNENBL13 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,13) +#define SDMAARM_CHNENBL14 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,14) +#define SDMAARM_CHNENBL15 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,15) +#define SDMAARM_CHNENBL16 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,16) +#define SDMAARM_CHNENBL17 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,17) +#define SDMAARM_CHNENBL18 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,18) +#define SDMAARM_CHNENBL19 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,19) +#define SDMAARM_CHNENBL20 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,20) +#define SDMAARM_CHNENBL21 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,21) +#define SDMAARM_CHNENBL22 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,22) +#define SDMAARM_CHNENBL23 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,23) +#define SDMAARM_CHNENBL24 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,24) +#define SDMAARM_CHNENBL25 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,25) +#define SDMAARM_CHNENBL26 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,26) +#define SDMAARM_CHNENBL27 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,27) +#define SDMAARM_CHNENBL28 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,28) +#define SDMAARM_CHNENBL29 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,29) +#define SDMAARM_CHNENBL30 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,30) +#define SDMAARM_CHNENBL31 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,31) +#define SDMAARM_CHNENBL32 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,32) +#define SDMAARM_CHNENBL33 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,33) +#define SDMAARM_CHNENBL34 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,34) +#define SDMAARM_CHNENBL35 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,35) +#define SDMAARM_CHNENBL36 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,36) +#define SDMAARM_CHNENBL37 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,37) +#define SDMAARM_CHNENBL38 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,38) +#define SDMAARM_CHNENBL39 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,39) +#define SDMAARM_CHNENBL40 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,40) +#define SDMAARM_CHNENBL41 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,41) +#define SDMAARM_CHNENBL42 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,42) +#define SDMAARM_CHNENBL43 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,43) +#define SDMAARM_CHNENBL44 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,44) +#define SDMAARM_CHNENBL45 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,45) +#define SDMAARM_CHNENBL46 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,46) +#define SDMAARM_CHNENBL47 SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,47) + +/* SDMAARM - Register array accessors */ +#define SDMAARM_SDMA_CHNPRI(index) SDMAARM_SDMA_CHNPRI_REG(SDMAARM_BASE_PTR,index) +#define SDMAARM_CHNENBL(index) SDMAARM_CHNENBL_REG(SDMAARM_BASE_PTR,index) + +/*! + * @} + */ /* end of group SDMAARM_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SDMAARM_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SDMABP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMABP_Peripheral_Access_Layer SDMABP Peripheral Access Layer + * @{ + */ + +/** SDMABP - Register Layout Typedef */ +typedef struct { + __IO uint32_t DC0PTR; /**< Channel 0 Pointer, offset: 0x0 */ + __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ + __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ + __I uint32_t DSTART; /**< Channel Start, offset: 0xC */ + uint8_t RESERVED_0[24]; + __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ + __IO uint32_t INTRMASK; /**< Channel DSP Interrupt Mask, offset: 0x2C */ + uint8_t RESERVED_1[4]; + __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ +} SDMABP_Type, *SDMABP_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SDMABP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros + * @{ + */ + + +/* SDMABP - Register accessors */ +#define SDMABP_DC0PTR_REG(base) ((base)->DC0PTR) +#define SDMABP_INTR_REG(base) ((base)->INTR) +#define SDMABP_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMABP_DSTART_REG(base) ((base)->DSTART) +#define SDMABP_EVTERR_REG(base) ((base)->EVTERR) +#define SDMABP_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMABP_EVTERRDBG_REG(base) ((base)->EVTERRDBG) + +/*! + * @} + */ /* end of group SDMABP_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDMABP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMABP_Register_Masks SDMABP Register Masks + * @{ + */ + +/* DC0PTR Bit Fields */ +#define SDMABP_DC0PTR_DC0PTR_MASK 0xFFFFFFFFu +#define SDMABP_DC0PTR_DC0PTR_SHIFT 0 +#define SDMABP_DC0PTR_DC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_DC0PTR_DC0PTR_SHIFT))&SDMABP_DC0PTR_DC0PTR_MASK) +/* INTR Bit Fields */ +#define SDMABP_INTR_DI_MASK 0xFFFFFFFFu +#define SDMABP_INTR_DI_SHIFT 0 +#define SDMABP_INTR_DI(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_INTR_DI_SHIFT))&SDMABP_INTR_DI_MASK) +/* STOP_STAT Bit Fields */ +#define SDMABP_STOP_STAT_DE_MASK 0xFFFFFFFFu +#define SDMABP_STOP_STAT_DE_SHIFT 0 +#define SDMABP_STOP_STAT_DE(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_STOP_STAT_DE_SHIFT))&SDMABP_STOP_STAT_DE_MASK) +/* DSTART Bit Fields */ +#define SDMABP_DSTART_DSTART_DE_MASK 0xFFFFFFFFu +#define SDMABP_DSTART_DSTART_DE_SHIFT 0 +#define SDMABP_DSTART_DSTART_DE(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_DSTART_DSTART_DE_SHIFT))&SDMABP_DSTART_DSTART_DE_MASK) +/* EVTERR Bit Fields */ +#define SDMABP_EVTERR_CHNERR_MASK 0xFFFFFFFFu +#define SDMABP_EVTERR_CHNERR_SHIFT 0 +#define SDMABP_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERR_CHNERR_SHIFT))&SDMABP_EVTERR_CHNERR_MASK) +/* INTRMASK Bit Fields */ +#define SDMABP_INTRMASK_DIMASK_MASK 0xFFFFFFFFu +#define SDMABP_INTRMASK_DIMASK_SHIFT 0 +#define SDMABP_INTRMASK_DIMASK(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_INTRMASK_DIMASK_SHIFT))&SDMABP_INTRMASK_DIMASK_MASK) +/* EVTERRDBG Bit Fields */ +#define SDMABP_EVTERRDBG_CHNERR_MASK 0xFFFFFFFFu +#define SDMABP_EVTERRDBG_CHNERR_SHIFT 0 +#define SDMABP_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x))<<SDMABP_EVTERRDBG_CHNERR_SHIFT))&SDMABP_EVTERRDBG_CHNERR_MASK) + +/*! + * @} + */ /* end of group SDMABP_Register_Masks */ + + +/* SDMABP - Peripheral instance base addresses */ +/** Peripheral SDMABP base address */ +#define SDMABP_BASE (0x30BD0000u) +/** Peripheral SDMABP base pointer */ +#define SDMABP ((SDMABP_Type *)SDMABP_BASE) +#define SDMABP_BASE_PTR (SDMABP) +/** Array initializer of SDMABP peripheral base adresses */ +#define SDMABP_BASE_ADDRS { SDMABP_BASE } +/** Array initializer of SDMABP peripheral base pointers */ +#define SDMABP_BASE_PTRS { SDMABP } + +/* ---------------------------------------------------------------------------- + -- SDMABP - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMABP_Register_Accessor_Macros SDMABP - Register accessor macros + * @{ + */ + + +/* SDMABP - Register instance definitions */ +/* SDMABP */ +#define SDMABP_DC0PTR SDMABP_DC0PTR_REG(SDMABP_BASE_PTR) +#define SDMABP_INTR SDMABP_INTR_REG(SDMABP_BASE_PTR) +#define SDMABP_STOP_STAT SDMABP_STOP_STAT_REG(SDMABP_BASE_PTR) +#define SDMABP_DSTART SDMABP_DSTART_REG(SDMABP_BASE_PTR) +#define SDMABP_EVTERR SDMABP_EVTERR_REG(SDMABP_BASE_PTR) +#define SDMABP_INTRMASK SDMABP_INTRMASK_REG(SDMABP_BASE_PTR) +#define SDMABP_EVTERRDBG SDMABP_EVTERRDBG_REG(SDMABP_BASE_PTR) + +/*! + * @} + */ /* end of group SDMABP_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SDMABP_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SDMACORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMACORE_Peripheral_Access_Layer SDMACORE Peripheral Access Layer + * @{ + */ + +/** SDMACORE - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[6]; + __I uint32_t CCPRI; /**< Current Channel Priority, offset: 0x6 */ + } CCPRI; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[2]; + __I uint32_t CCPTR; /**< Current Channel Pointer, offset: 0x2 */ + } CCPTR; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint32_t CCR; /**< Current Channel Register, offset: 0x3 */ + } CCR; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[11]; + __IO uint32_t EAA; /**< OnCE Event Address Register A, offset: 0xB */ + } EAA; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t EAB; /**< OnCE Event Cell Address Register B, offset: 0xC */ + } EAB; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[13]; + __IO uint32_t EAM; /**< OnCE Event Cell Address Mask, offset: 0xD */ + } EAM; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[9]; + __IO uint32_t ECOUNT; /**< OnCE Event Cell Counter, offset: 0x9 */ + } ECOUNT; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[10]; + __IO uint32_t ECTL; /**< OnCE Event Cell Control Register, offset: 0xA */ + } ECTL; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[14]; + __IO uint32_t ED; /**< OnCE Event Cell Data Register, offset: 0xE */ + } ED; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[15]; + __IO uint32_t EDM; /**< OnCE Event Cell Data Mask, offset: 0xF */ + } EDM; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[5]; + __I uint32_t EVENTS; /**< External DMA Requests Mirror, offset: 0x5 */ + } EVENTS; + __I uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[7]; + __I uint32_t NCPRI; /**< Next Channel Priority, offset: 0x7 */ + } NCPRI; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t NCR; /**< Highest Pending Channel Register, offset: 0x4 */ + } NCR; + }; + uint8_t RESERVED_0[5]; + union { /* offset: 0x18 */ + struct { /* offset: 0x18 */ + uint8_t RESERVED_0[5]; + __I uint32_t ENDIANNESS; /**< ENDIAN Status Register, offset: 0x1D */ + } ENDIANNESS; + struct { /* offset: 0x18 */ + uint8_t RESERVED_0[7]; + __I uint32_t EVENTS2; /**< External DMA Requests Mirror #2, offset: 0x1F */ + } EVENTS2; + struct { /* offset: 0x18 */ + uint8_t RESERVED_0[4]; + __I uint32_t MCHN0ADDR; /**< Channel 0 Boot Address, offset: 0x1C */ + } MCHN0ADDR; + struct { /* offset: 0x18 */ + uint8_t RESERVED_0[2]; + __I uint32_t OSTAT; /**< OnCE Status, offset: 0x1A */ + } OSTAT; + __IO uint32_t RTB; /**< OnCE Real-Time Buffer, offset: 0x18 */ + struct { /* offset: 0x18 */ + uint8_t RESERVED_0[6]; + __I uint32_t SDMA_LOCK; /**< Lock Status Register, offset: 0x1E */ + } SDMA_LOCK; + struct { /* offset: 0x18 */ + uint8_t RESERVED_0[1]; + __IO uint32_t TB; /**< OnCE Trace Buffer, offset: 0x19 */ + } TB; + }; +} SDMACORE_Type, *SDMACORE_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SDMACORE - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros + * @{ + */ + + +/* SDMACORE - Register accessors */ +#define SDMACORE_CCPRI_REG(base) ((base)->CCPRI.CCPRI) +#define SDMACORE_CCPTR_REG(base) ((base)->CCPTR.CCPTR) +#define SDMACORE_CCR_REG(base) ((base)->CCR.CCR) +#define SDMACORE_EAA_REG(base) ((base)->EAA.EAA) +#define SDMACORE_EAB_REG(base) ((base)->EAB.EAB) +#define SDMACORE_EAM_REG(base) ((base)->EAM.EAM) +#define SDMACORE_ECOUNT_REG(base) ((base)->ECOUNT.ECOUNT) +#define SDMACORE_ECTL_REG(base) ((base)->ECTL.ECTL) +#define SDMACORE_ED_REG(base) ((base)->ED.ED) +#define SDMACORE_EDM_REG(base) ((base)->EDM.EDM) +#define SDMACORE_EVENTS_REG(base) ((base)->EVENTS.EVENTS) +#define SDMACORE_MC0PTR_REG(base) ((base)->MC0PTR) +#define SDMACORE_NCPRI_REG(base) ((base)->NCPRI.NCPRI) +#define SDMACORE_NCR_REG(base) ((base)->NCR.NCR) +#define SDMACORE_ENDIANNESS_REG(base) ((base)->ENDIANNESS.ENDIANNESS) +#define SDMACORE_EVENTS2_REG(base) ((base)->EVENTS2.EVENTS2) +#define SDMACORE_MCHN0ADDR_REG(base) ((base)->MCHN0ADDR.MCHN0ADDR) +#define SDMACORE_OSTAT_REG(base) ((base)->OSTAT.OSTAT) +#define SDMACORE_RTB_REG(base) ((base)->RTB) +#define SDMACORE_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK.SDMA_LOCK) +#define SDMACORE_TB_REG(base) ((base)->TB.TB) + +/*! + * @} + */ /* end of group SDMACORE_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDMACORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks + * @{ + */ + +/* CCPRI Bit Fields */ +#define SDMACORE_CCPRI_CCPRI_MASK 0x7u +#define SDMACORE_CCPRI_CCPRI_SHIFT 0 +#define SDMACORE_CCPRI_CCPRI(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPRI_CCPRI_SHIFT))&SDMACORE_CCPRI_CCPRI_MASK) +/* CCPTR Bit Fields */ +#define SDMACORE_CCPTR_CCPTR_MASK 0xFFFFu +#define SDMACORE_CCPTR_CCPTR_SHIFT 0 +#define SDMACORE_CCPTR_CCPTR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCPTR_CCPTR_SHIFT))&SDMACORE_CCPTR_CCPTR_MASK) +/* CCR Bit Fields */ +#define SDMACORE_CCR_CCR_MASK 0x1Fu +#define SDMACORE_CCR_CCR_SHIFT 0 +#define SDMACORE_CCR_CCR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_CCR_CCR_SHIFT))&SDMACORE_CCR_CCR_MASK) +/* EAA Bit Fields */ +#define SDMACORE_EAA_EAA_MASK 0xFFFFu +#define SDMACORE_EAA_EAA_SHIFT 0 +#define SDMACORE_EAA_EAA(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAA_EAA_SHIFT))&SDMACORE_EAA_EAA_MASK) +/* EAB Bit Fields */ +#define SDMACORE_EAB_EAB_MASK 0xFFFFu +#define SDMACORE_EAB_EAB_SHIFT 0 +#define SDMACORE_EAB_EAB(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAB_EAB_SHIFT))&SDMACORE_EAB_EAB_MASK) +/* EAM Bit Fields */ +#define SDMACORE_EAM_EAM_MASK 0xFFFFu +#define SDMACORE_EAM_EAM_SHIFT 0 +#define SDMACORE_EAM_EAM(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EAM_EAM_SHIFT))&SDMACORE_EAM_EAM_MASK) +/* ECOUNT Bit Fields */ +#define SDMACORE_ECOUNT_ECOUNT_MASK 0xFFFFu +#define SDMACORE_ECOUNT_ECOUNT_SHIFT 0 +#define SDMACORE_ECOUNT_ECOUNT(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECOUNT_ECOUNT_SHIFT))&SDMACORE_ECOUNT_ECOUNT_MASK) +/* ECTL Bit Fields */ +#define SDMACORE_ECTL_ATS_MASK 0x3u +#define SDMACORE_ECTL_ATS_SHIFT 0 +#define SDMACORE_ECTL_ATS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATS_SHIFT))&SDMACORE_ECTL_ATS_MASK) +#define SDMACORE_ECTL_AATC_MASK 0xCu +#define SDMACORE_ECTL_AATC_SHIFT 2 +#define SDMACORE_ECTL_AATC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_AATC_SHIFT))&SDMACORE_ECTL_AATC_MASK) +#define SDMACORE_ECTL_ABTC_MASK 0x30u +#define SDMACORE_ECTL_ABTC_SHIFT 4 +#define SDMACORE_ECTL_ABTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ABTC_SHIFT))&SDMACORE_ECTL_ABTC_MASK) +#define SDMACORE_ECTL_ATC_MASK 0xC0u +#define SDMACORE_ECTL_ATC_SHIFT 6 +#define SDMACORE_ECTL_ATC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ATC_SHIFT))&SDMACORE_ECTL_ATC_MASK) +#define SDMACORE_ECTL_DTC_MASK 0x300u +#define SDMACORE_ECTL_DTC_SHIFT 8 +#define SDMACORE_ECTL_DTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_DTC_SHIFT))&SDMACORE_ECTL_DTC_MASK) +#define SDMACORE_ECTL_ECTC_MASK 0xC00u +#define SDMACORE_ECTL_ECTC_SHIFT 10 +#define SDMACORE_ECTL_ECTC(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ECTL_ECTC_SHIFT))&SDMACORE_ECTL_ECTC_MASK) +#define SDMACORE_ECTL_CNT_MASK 0x1000u +#define SDMACORE_ECTL_CNT_SHIFT 12 +#define SDMACORE_ECTL_EN_MASK 0x2000u +#define SDMACORE_ECTL_EN_SHIFT 13 +/* ED Bit Fields */ +#define SDMACORE_ED_ED_MASK 0xFFFFFFFFu +#define SDMACORE_ED_ED_SHIFT 0 +#define SDMACORE_ED_ED(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_ED_ED_SHIFT))&SDMACORE_ED_ED_MASK) +/* EDM Bit Fields */ +#define SDMACORE_EDM_EDM_MASK 0xFFFFFFFFu +#define SDMACORE_EDM_EDM_SHIFT 0 +#define SDMACORE_EDM_EDM(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EDM_EDM_SHIFT))&SDMACORE_EDM_EDM_MASK) +/* EVENTS Bit Fields */ +#define SDMACORE_EVENTS_EVENTS_MASK 0xFFFFFFFFu +#define SDMACORE_EVENTS_EVENTS_SHIFT 0 +#define SDMACORE_EVENTS_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS_EVENTS_SHIFT))&SDMACORE_EVENTS_EVENTS_MASK) +/* MC0PTR Bit Fields */ +#define SDMACORE_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMACORE_MC0PTR_MC0PTR_SHIFT 0 +#define SDMACORE_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_MC0PTR_MC0PTR_SHIFT))&SDMACORE_MC0PTR_MC0PTR_MASK) +/* NCPRI Bit Fields */ +#define SDMACORE_NCPRI_NCPRI_MASK 0x7u +#define SDMACORE_NCPRI_NCPRI_SHIFT 0 +#define SDMACORE_NCPRI_NCPRI(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCPRI_NCPRI_SHIFT))&SDMACORE_NCPRI_NCPRI_MASK) +/* NCR Bit Fields */ +#define SDMACORE_NCR_NCR_MASK 0x1Fu +#define SDMACORE_NCR_NCR_SHIFT 0 +#define SDMACORE_NCR_NCR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_NCR_NCR_SHIFT))&SDMACORE_NCR_NCR_MASK) +/* ENDIANNESS Bit Fields */ +#define SDMACORE_ENDIANNESS_APEND_MASK 0x1u +#define SDMACORE_ENDIANNESS_APEND_SHIFT 0 +/* EVENTS2 Bit Fields */ +#define SDMACORE_EVENTS2_EVENTS_MASK 0xFFFFu +#define SDMACORE_EVENTS2_EVENTS_SHIFT 0 +#define SDMACORE_EVENTS2_EVENTS(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_EVENTS2_EVENTS_SHIFT))&SDMACORE_EVENTS2_EVENTS_MASK) +/* MCHN0ADDR Bit Fields */ +#define SDMACORE_MCHN0ADDR_CHN0ADDR_MASK 0x3FFFu +#define SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT 0 +#define SDMACORE_MCHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_MCHN0ADDR_CHN0ADDR_SHIFT))&SDMACORE_MCHN0ADDR_CHN0ADDR_MASK) +#define SDMACORE_MCHN0ADDR_SMSZ_MASK 0x4000u +#define SDMACORE_MCHN0ADDR_SMSZ_SHIFT 14 +/* OSTAT Bit Fields */ +#define SDMACORE_OSTAT_ECDR_MASK 0x7u +#define SDMACORE_OSTAT_ECDR_SHIFT 0 +#define SDMACORE_OSTAT_ECDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_ECDR_SHIFT))&SDMACORE_OSTAT_ECDR_MASK) +#define SDMACORE_OSTAT_MST_MASK 0x80u +#define SDMACORE_OSTAT_MST_SHIFT 7 +#define SDMACORE_OSTAT_SWB_MASK 0x100u +#define SDMACORE_OSTAT_SWB_SHIFT 8 +#define SDMACORE_OSTAT_ODR_MASK 0x200u +#define SDMACORE_OSTAT_ODR_SHIFT 9 +#define SDMACORE_OSTAT_EDR_MASK 0x400u +#define SDMACORE_OSTAT_EDR_SHIFT 10 +#define SDMACORE_OSTAT_RCV_MASK 0x800u +#define SDMACORE_OSTAT_RCV_SHIFT 11 +#define SDMACORE_OSTAT_PST_MASK 0xF000u +#define SDMACORE_OSTAT_PST_SHIFT 12 +#define SDMACORE_OSTAT_PST(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_OSTAT_PST_SHIFT))&SDMACORE_OSTAT_PST_MASK) +/* RTB Bit Fields */ +#define SDMACORE_RTB_RTB_MASK 0xFFFFFFFFu +#define SDMACORE_RTB_RTB_SHIFT 0 +#define SDMACORE_RTB_RTB(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_RTB_RTB_SHIFT))&SDMACORE_RTB_RTB_MASK) +/* SDMA_LOCK Bit Fields */ +#define SDMACORE_SDMA_LOCK_LOCK_MASK 0x1u +#define SDMACORE_SDMA_LOCK_LOCK_SHIFT 0 +/* TB Bit Fields */ +#define SDMACORE_TB_CHFADDR_MASK 0x3FFFu +#define SDMACORE_TB_CHFADDR_SHIFT 0 +#define SDMACORE_TB_CHFADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_CHFADDR_SHIFT))&SDMACORE_TB_CHFADDR_MASK) +#define SDMACORE_TB_TADDR_MASK 0xFFFC000u +#define SDMACORE_TB_TADDR_SHIFT 14 +#define SDMACORE_TB_TADDR(x) (((uint32_t)(((uint32_t)(x))<<SDMACORE_TB_TADDR_SHIFT))&SDMACORE_TB_TADDR_MASK) +#define SDMACORE_TB_TBF_MASK 0x10000000u +#define SDMACORE_TB_TBF_SHIFT 28 + +/*! + * @} + */ /* end of group SDMACORE_Register_Masks */ + + +/* SDMACORE - Peripheral instance base addresses */ +/** Peripheral SDMACORE base address */ +#define SDMACORE_BASE (0x30BD0000u) +/** Peripheral SDMACORE base pointer */ +#define SDMACORE ((SDMACORE_Type *)SDMACORE_BASE) +#define SDMACORE_BASE_PTR (SDMACORE) +/** Array initializer of SDMACORE peripheral base adresses */ +#define SDMACORE_BASE_ADDRS { SDMACORE_BASE } +/** Array initializer of SDMACORE peripheral base pointers */ +#define SDMACORE_BASE_PTRS { SDMACORE } + +/* ---------------------------------------------------------------------------- + -- SDMACORE - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMACORE_Register_Accessor_Macros SDMACORE - Register accessor macros + * @{ + */ + + +/* SDMACORE - Register instance definitions */ +/* SDMACORE */ +#define SDMACORE_MC0PTR SDMACORE_MC0PTR_REG(SDMACORE_BASE_PTR) +#define SDMACORE_CCPTR SDMACORE_CCPTR_REG(SDMACORE_BASE_PTR) +#define SDMACORE_CCR SDMACORE_CCR_REG(SDMACORE_BASE_PTR) +#define SDMACORE_NCR SDMACORE_NCR_REG(SDMACORE_BASE_PTR) +#define SDMACORE_EVENTS SDMACORE_EVENTS_REG(SDMACORE_BASE_PTR) +#define SDMACORE_CCPRI SDMACORE_CCPRI_REG(SDMACORE_BASE_PTR) +#define SDMACORE_NCPRI SDMACORE_NCPRI_REG(SDMACORE_BASE_PTR) +#define SDMACORE_ECOUNT SDMACORE_ECOUNT_REG(SDMACORE_BASE_PTR) +#define SDMACORE_ECTL SDMACORE_ECTL_REG(SDMACORE_BASE_PTR) +#define SDMACORE_EAA SDMACORE_EAA_REG(SDMACORE_BASE_PTR) +#define SDMACORE_EAB SDMACORE_EAB_REG(SDMACORE_BASE_PTR) +#define SDMACORE_EAM SDMACORE_EAM_REG(SDMACORE_BASE_PTR) +#define SDMACORE_ED SDMACORE_ED_REG(SDMACORE_BASE_PTR) +#define SDMACORE_EDM SDMACORE_EDM_REG(SDMACORE_BASE_PTR) +#define SDMACORE_RTB SDMACORE_RTB_REG(SDMACORE_BASE_PTR) +#define SDMACORE_TB SDMACORE_TB_REG(SDMACORE_BASE_PTR) +#define SDMACORE_OSTAT SDMACORE_OSTAT_REG(SDMACORE_BASE_PTR) +#define SDMACORE_MCHN0ADDR SDMACORE_MCHN0ADDR_REG(SDMACORE_BASE_PTR) +#define SDMACORE_ENDIANNESS SDMACORE_ENDIANNESS_REG(SDMACORE_BASE_PTR) +#define SDMACORE_SDMA_LOCK SDMACORE_SDMA_LOCK_REG(SDMACORE_BASE_PTR) +#define SDMACORE_EVENTS2 SDMACORE_EVENTS2_REG(SDMACORE_BASE_PTR) + +/*! + * @} + */ /* end of group SDMACORE_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SDMACORE_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SEMA4 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer + * @{ + */ + +typedef struct { + __IO uint8_t GATE00; /**< Semaphores GATE 0 Register, offset: 0x0 */ + __IO uint8_t GATE01; /**< Semaphores GATE 1 Register, offset: 0x1 */ + __IO uint8_t GATE02; /**< Semaphores GATE 2 Register, offset: 0x2 */ + __IO uint8_t GATE03; /**< Semaphores GATE 3 Register, offset: 0x3 */ + __IO uint8_t GATE04; /**< Semaphores GATE 4 Register, offset: 0x4 */ + __IO uint8_t GATE05; /**< Semaphores GATE 5 Register, offset: 0x5 */ + __IO uint8_t GATE06; /**< Semaphores GATE 6 Register, offset: 0x6 */ + __IO uint8_t GATE07; /**< Semaphores GATE 7 Register, offset: 0x7 */ + __IO uint8_t GATE08; /**< Semaphores GATE 8 Register, offset: 0x8 */ + __IO uint8_t GATE09; /**< Semaphores GATE 9 Register, offset: 0x9 */ + __IO uint8_t GATE10; /**< Semaphores GATE 10 Register, offset: 0xA */ + __IO uint8_t GATE11; /**< Semaphores GATE 11 Register, offset: 0xB */ + __IO uint8_t GATE12; /**< Semaphores GATE 12 Register, offset: 0xC */ + __IO uint8_t GATE13; /**< Semaphores GATE 13 Register, offset: 0xD */ + __IO uint8_t GATE14; /**< Semaphores GATE 14 Register, offset: 0xE */ + __IO uint8_t GATE15; /**< Semaphores GATE 15 Register, offset: 0xF */ + uint8_t RESERVED_0[48]; + struct { /* offset: 0x40, array step: 0x8 */ + __IO uint16_t INE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ + uint8_t RESERVED_0[6]; + } CPnINE[2]; + uint8_t RESERVED_1[48]; + struct { /* offset: 0x80, array step: 0x8 */ + __IO uint16_t NTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */ + uint8_t RESERVED_0[6]; + } CPnNTF[2]; + uint8_t RESERVED_2[112]; + __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */ + uint8_t RESERVED_3[2]; + __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */ +} SEMA4_Type, *SEMA4_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SEMA4 - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros + * @{ + */ + + +/* SEMA4 - Register accessors */ +#define SEMA4_GATE03_REG(base) ((base)->Gate03) +#define SEMA4_GATE02_REG(base) ((base)->Gate02) +#define SEMA4_GATE01_REG(base) ((base)->Gate01) +#define SEMA4_GATE00_REG(base) ((base)->Gate00) +#define SEMA4_GATE07_REG(base) ((base)->Gate07) +#define SEMA4_GATE06_REG(base) ((base)->Gate06) +#define SEMA4_GATE05_REG(base) ((base)->Gate05) +#define SEMA4_GATE04_REG(base) ((base)->Gate04) +#define SEMA4_GATE11_REG(base) ((base)->Gate11) +#define SEMA4_GATE10_REG(base) ((base)->Gate10) +#define SEMA4_GATE09_REG(base) ((base)->Gate09) +#define SEMA4_GATE08_REG(base) ((base)->Gate08) +#define SEMA4_GATE15_REG(base) ((base)->Gate15) +#define SEMA4_GATE14_REG(base) ((base)->Gate14) +#define SEMA4_GATE13_REG(base) ((base)->Gate13) +#define SEMA4_GATE12_REG(base) ((base)->Gate12) +#define SEMA4_CPINE_REG(base,index) ((base)->CPINE[index].CPINE) +#define SEMA4_CPNTF_REG(base,index) ((base)->CPNTF[index].CPNTF) +#define SEMA4_RSTGT_REG(base) ((base)->RSTGT) +#define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) + +/*! + * @} + */ /* end of group SEMA4_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SEMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks + * @{ + */ + +/* Gate03 Bit Fields */ +#define SEMA4_GATE03_GTFSM_MASK 0x3u +#define SEMA4_GATE03_GTFSM_SHIFT 0 +#define SEMA4_GATE03_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE03_GTFSM_SHIFT))&SEMA4_GATE03_GTFSM_MASK) +/* Gate02 Bit Fields */ +#define SEMA4_GATE02_GTFSM_MASK 0x3u +#define SEMA4_GATE02_GTFSM_SHIFT 0 +#define SEMA4_GATE02_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE02_GTFSM_SHIFT))&SEMA4_GATE02_GTFSM_MASK) +/* Gate01 Bit Fields */ +#define SEMA4_GATE01_GTFSM_MASK 0x3u +#define SEMA4_GATE01_GTFSM_SHIFT 0 +#define SEMA4_GATE01_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE01_GTFSM_SHIFT))&SEMA4_GATE01_GTFSM_MASK) +/* Gate00 Bit Fields */ +#define SEMA4_GATE00_GTFSM_MASK 0x3u +#define SEMA4_GATE00_GTFSM_SHIFT 0 +#define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE00_GTFSM_SHIFT))&SEMA4_GATE00_GTFSM_MASK) +/* Gate07 Bit Fields */ +#define SEMA4_GATE07_GTFSM_MASK 0x3u +#define SEMA4_GATE07_GTFSM_SHIFT 0 +#define SEMA4_GATE07_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE07_GTFSM_SHIFT))&SEMA4_GATE07_GTFSM_MASK) +/* Gate06 Bit Fields */ +#define SEMA4_GATE06_GTFSM_MASK 0x3u +#define SEMA4_GATE06_GTFSM_SHIFT 0 +#define SEMA4_GATE06_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE06_GTFSM_SHIFT))&SEMA4_GATE06_GTFSM_MASK) +/* Gate05 Bit Fields */ +#define SEMA4_GATE05_GTFSM_MASK 0x3u +#define SEMA4_GATE05_GTFSM_SHIFT 0 +#define SEMA4_GATE05_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE05_GTFSM_SHIFT))&SEMA4_GATE05_GTFSM_MASK) +/* Gate04 Bit Fields */ +#define SEMA4_GATE04_GTFSM_MASK 0x3u +#define SEMA4_GATE04_GTFSM_SHIFT 0 +#define SEMA4_GATE04_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE04_GTFSM_SHIFT))&SEMA4_GATE04_GTFSM_MASK) +/* Gate11 Bit Fields */ +#define SEMA4_GATE11_GTFSM_MASK 0x3u +#define SEMA4_GATE11_GTFSM_SHIFT 0 +#define SEMA4_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE11_GTFSM_SHIFT))&SEMA4_GATE11_GTFSM_MASK) +/* Gate10 Bit Fields */ +#define SEMA4_GATE10_GTFSM_MASK 0x3u +#define SEMA4_GATE10_GTFSM_SHIFT 0 +#define SEMA4_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE10_GTFSM_SHIFT))&SEMA4_GATE10_GTFSM_MASK) +/* Gate09 Bit Fields */ +#define SEMA4_GATE09_GTFSM_MASK 0x3u +#define SEMA4_GATE09_GTFSM_SHIFT 0 +#define SEMA4_GATE09_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE09_GTFSM_SHIFT))&SEMA4_GATE09_GTFSM_MASK) +/* Gate08 Bit Fields */ +#define SEMA4_GATE08_GTFSM_MASK 0x3u +#define SEMA4_GATE08_GTFSM_SHIFT 0 +#define SEMA4_GATE08_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE08_GTFSM_SHIFT))&SEMA4_GATE08_GTFSM_MASK) +/* Gate15 Bit Fields */ +#define SEMA4_GATE15_GTFSM_MASK 0x3u +#define SEMA4_GATE15_GTFSM_SHIFT 0 +#define SEMA4_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE15_GTFSM_SHIFT))&SEMA4_GATE15_GTFSM_MASK) +/* Gate14 Bit Fields */ +#define SEMA4_GATE14_GTFSM_MASK 0x3u +#define SEMA4_GATE14_GTFSM_SHIFT 0 +#define SEMA4_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE14_GTFSM_SHIFT))&SEMA4_GATE14_GTFSM_MASK) +/* Gate13 Bit Fields */ +#define SEMA4_GATE13_GTFSM_MASK 0x3u +#define SEMA4_GATE13_GTFSM_SHIFT 0 +#define SEMA4_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE13_GTFSM_SHIFT))&SEMA4_GATE13_GTFSM_MASK) +/* Gate12 Bit Fields */ +#define SEMA4_GATE12_GTFSM_MASK 0x3u +#define SEMA4_GATE12_GTFSM_SHIFT 0 +#define SEMA4_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x))<<SEMA4_GATE12_GTFSM_SHIFT))&SEMA4_GATE12_GTFSM_MASK) +/* CPINE Bit Fields */ +#define SEMA4_CPINE_INE7_MASK 0x1u +#define SEMA4_CPINE_INE7_SHIFT 0 +#define SEMA4_CPINE_INE6_MASK 0x2u +#define SEMA4_CPINE_INE6_SHIFT 1 +#define SEMA4_CPINE_INE5_MASK 0x4u +#define SEMA4_CPINE_INE5_SHIFT 2 +#define SEMA4_CPINE_INE4_MASK 0x8u +#define SEMA4_CPINE_INE4_SHIFT 3 +#define SEMA4_CPINE_INE3_MASK 0x10u +#define SEMA4_CPINE_INE3_SHIFT 4 +#define SEMA4_CPINE_INE2_MASK 0x20u +#define SEMA4_CPINE_INE2_SHIFT 5 +#define SEMA4_CPINE_INE1_MASK 0x40u +#define SEMA4_CPINE_INE1_SHIFT 6 +#define SEMA4_CPINE_INE0_MASK 0x80u +#define SEMA4_CPINE_INE0_SHIFT 7 +#define SEMA4_CPINE_INE15_MASK 0x100u +#define SEMA4_CPINE_INE15_SHIFT 8 +#define SEMA4_CPINE_INE14_MASK 0x200u +#define SEMA4_CPINE_INE14_SHIFT 9 +#define SEMA4_CPINE_INE13_MASK 0x400u +#define SEMA4_CPINE_INE13_SHIFT 10 +#define SEMA4_CPINE_INE12_MASK 0x800u +#define SEMA4_CPINE_INE12_SHIFT 11 +#define SEMA4_CPINE_INE11_MASK 0x1000u +#define SEMA4_CPINE_INE11_SHIFT 12 +#define SEMA4_CPINE_INE10_MASK 0x2000u +#define SEMA4_CPINE_INE10_SHIFT 13 +#define SEMA4_CPINE_INE9_MASK 0x4000u +#define SEMA4_CPINE_INE9_SHIFT 14 +#define SEMA4_CPINE_INE8_MASK 0x8000u +#define SEMA4_CPINE_INE8_SHIFT 15 +/* CPNTF Bit Fields */ +#define SEMA4_CPNTF_GN7_MASK 0x1u +#define SEMA4_CPNTF_GN7_SHIFT 0 +#define SEMA4_CPNTF_GN6_MASK 0x2u +#define SEMA4_CPNTF_GN6_SHIFT 1 +#define SEMA4_CPNTF_GN5_MASK 0x4u +#define SEMA4_CPNTF_GN5_SHIFT 2 +#define SEMA4_CPNTF_GN4_MASK 0x8u +#define SEMA4_CPNTF_GN4_SHIFT 3 +#define SEMA4_CPNTF_GN3_MASK 0x10u +#define SEMA4_CPNTF_GN3_SHIFT 4 +#define SEMA4_CPNTF_GN2_MASK 0x20u +#define SEMA4_CPNTF_GN2_SHIFT 5 +#define SEMA4_CPNTF_GN1_MASK 0x40u +#define SEMA4_CPNTF_GN1_SHIFT 6 +#define SEMA4_CPNTF_GN0_MASK 0x80u +#define SEMA4_CPNTF_GN0_SHIFT 7 +#define SEMA4_CPNTF_GN15_MASK 0x100u +#define SEMA4_CPNTF_GN15_SHIFT 8 +#define SEMA4_CPNTF_GN14_MASK 0x200u +#define SEMA4_CPNTF_GN14_SHIFT 9 +#define SEMA4_CPNTF_GN13_MASK 0x400u +#define SEMA4_CPNTF_GN13_SHIFT 10 +#define SEMA4_CPNTF_GN12_MASK 0x800u +#define SEMA4_CPNTF_GN12_SHIFT 11 +#define SEMA4_CPNTF_GN11_MASK 0x1000u +#define SEMA4_CPNTF_GN11_SHIFT 12 +#define SEMA4_CPNTF_GN10_MASK 0x2000u +#define SEMA4_CPNTF_GN10_SHIFT 13 +#define SEMA4_CPNTF_GN9_MASK 0x4000u +#define SEMA4_CPNTF_GN9_SHIFT 14 +#define SEMA4_CPNTF_GN8_MASK 0x8000u +#define SEMA4_CPNTF_GN8_SHIFT 15 +/* RSTGT Bit Fields */ +#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK 0xFFu +#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT 0 +#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT))&SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK) +#define SEMA4_RSTGT_RSTGTN_MASK 0xFF00u +#define SEMA4_RSTGT_RSTGTN_SHIFT 8 +#define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTGT_RSTGTN_SHIFT))&SEMA4_RSTGT_RSTGTN_MASK) +/* RSTNTF Bit Fields */ +#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK 0xFFu +#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT 0 +#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT))&SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK) +#define SEMA4_RSTNTF_RSTNTN_MASK 0xFF00u +#define SEMA4_RSTNTF_RSTNTN_SHIFT 8 +#define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x))<<SEMA4_RSTNTF_RSTNTN_SHIFT))&SEMA4_RSTNTF_RSTNTN_MASK) + +/*! + * @} + */ /* end of group SEMA4_Register_Masks */ + + +/* SEMA4 - Peripheral instance base addresses */ +/** Peripheral SEMA4 base address */ +#define SEMA4_BASE (0x30AC0000u) +/** Peripheral SEMA4 base pointer */ +#define SEMA4 ((SEMA4_Type *)SEMA4_BASE) +#define SEMA4_BASE_PTR (SEMA4) +/** Array initializer of SEMA4 peripheral base adresses */ +#define SEMA4_BASE_ADDRS { SEMA4_BASE } +/** Array initializer of SEMA4 peripheral base pointers */ +#define SEMA4_BASE_PTRS { SEMA4 } + +/* ---------------------------------------------------------------------------- + -- SEMA4 - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Accessor_Macros SEMA4 - Register accessor macros + * @{ + */ + + +/* SEMA4 - Register instance definitions */ +/* SEMA4 */ +#define SEMA4_GATE03 SEMA4_GATE03_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE02 SEMA4_GATE02_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE01 SEMA4_GATE01_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE00 SEMA4_GATE00_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE07 SEMA4_GATE07_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE06 SEMA4_GATE06_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE05 SEMA4_GATE05_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE04 SEMA4_GATE04_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE11 SEMA4_GATE11_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE10 SEMA4_GATE10_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE09 SEMA4_GATE09_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE08 SEMA4_GATE08_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE15 SEMA4_GATE15_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE14 SEMA4_GATE14_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE13 SEMA4_GATE13_REG(SEMA4_BASE_PTR) +#define SEMA4_GATE12 SEMA4_GATE12_REG(SEMA4_BASE_PTR) +#define SEMA4_CP0INE SEMA4_CPINE_REG(SEMA4_BASE_PTR,0) +#define SEMA4_CP1INE SEMA4_CPINE_REG(SEMA4_BASE_PTR,1) +#define SEMA4_CP0NTF SEMA4_CPNTF_REG(SEMA4_BASE_PTR,0) +#define SEMA4_CP1NTF SEMA4_CPNTF_REG(SEMA4_BASE_PTR,1) +#define SEMA4_RSTGT SEMA4_RSTGT_REG(SEMA4_BASE_PTR) +#define SEMA4_RSTNTF SEMA4_RSTNTF_REG(SEMA4_BASE_PTR) + +/* SEMA4 - Register array accessors */ +#define SEMA4_CPINE(index) SEMA4_CPINE_REG(SEMA4_BASE_PTR,index) +#define SEMA4_CPNTF(index) SEMA4_CPNTF_REG(SEMA4_BASE_PTR,index) + +/*! + * @} + */ /* end of group SEMA4_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SEMA4_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SJC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Peripheral_Access_Layer SJC Peripheral Access Layer + * @{ + */ + +/** SJC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< Debug Control Register, offset: 0x4 */ + } DCR; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[7]; + __IO uint32_t GPCCR; /**< General Purpose Clocks Control Register, offset: 0x7 */ + } GPCCR; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint32_t GPSSR; /**< General Purpose Secured Status Register, offset: 0x3 */ + } GPSSR; + __I uint32_t GPUSR1; /**< General Purpose Unsecured Status Register 1, offset: 0x0 */ + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[1]; + __I uint32_t GPUSR2; /**< General Purpose Unsecured Status Register 2, offset: 0x1 */ + } GPUSR2; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[2]; + __I uint32_t GPUSR3; /**< General Purpose Unsecured Status Register 3, offset: 0x2 */ + } GPUSR3; + struct { /* offset: 0x0 */ + uint8_t RESERVED_0[5]; + __I uint32_t SSR; /**< Security Status Register, offset: 0x5 */ + } SSR; + }; +} SJC_Type, *SJC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SJC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros + * @{ + */ + + +/* SJC - Register accessors */ +#define SJC_DCR_REG(base) ((base)->DCR.DCR) +#define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) +#define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) +#define SJC_GPUSR1_REG(base) ((base)->GPUSR1) +#define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) +#define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) +#define SJC_SSR_REG(base) ((base)->SSR.SSR) + +/*! + * @} + */ /* end of group SJC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SJC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Register_Masks SJC Register Masks + * @{ + */ + +/* DCR Bit Fields */ +#define SJC_DCR_DE_TO_ARM_MASK 0x1u +#define SJC_DCR_DE_TO_ARM_SHIFT 0 +#define SJC_DCR_DE_TO_SDMA_MASK 0x2u +#define SJC_DCR_DE_TO_SDMA_SHIFT 1 +#define SJC_DCR_DEBUG_OBS_MASK 0x8u +#define SJC_DCR_DEBUG_OBS_SHIFT 3 +#define SJC_DCR_DIRECT_SDMA_REQ_EN_MASK 0x20u +#define SJC_DCR_DIRECT_SDMA_REQ_EN_SHIFT 5 +#define SJC_DCR_DIRECT_ARM_REQ_EN_MASK 0x40u +#define SJC_DCR_DIRECT_ARM_REQ_EN_SHIFT 6 +/* GPCCR Bit Fields */ +#define SJC_GPCCR_SCLKR_MASK 0x1u +#define SJC_GPCCR_SCLKR_SHIFT 0 +#define SJC_GPCCR_ACLKOFFDIS_MASK 0x2u +#define SJC_GPCCR_ACLKOFFDIS_SHIFT 1 +/* GPSSR Bit Fields */ +#define SJC_GPSSR_GPSSR_MASK 0xFFFFFFFFu +#define SJC_GPSSR_GPSSR_SHIFT 0 +#define SJC_GPSSR_GPSSR(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPSSR_GPSSR_SHIFT))&SJC_GPSSR_GPSSR_MASK) +/* GPUSR1 Bit Fields */ +#define SJC_GPUSR1_A_DBG_MASK 0x1u +#define SJC_GPUSR1_A_DBG_SHIFT 0 +#define SJC_GPUSR1_A_WFI_MASK 0x2u +#define SJC_GPUSR1_A_WFI_SHIFT 1 +#define SJC_GPUSR1_S_STAT_MASK 0x1Cu +#define SJC_GPUSR1_S_STAT_SHIFT 2 +#define SJC_GPUSR1_S_STAT(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR1_S_STAT_SHIFT))&SJC_GPUSR1_S_STAT_MASK) +#define SJC_GPUSR1_PLL_LOCK_MASK 0x100u +#define SJC_GPUSR1_PLL_LOCK_SHIFT 8 +/* GPUSR2 Bit Fields */ +#define SJC_GPUSR2_STBYWFI_MASK 0xFu +#define SJC_GPUSR2_STBYWFI_SHIFT 0 +#define SJC_GPUSR2_STBYWFI(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFI_SHIFT))&SJC_GPUSR2_STBYWFI_MASK) +#define SJC_GPUSR2_S_STAT_MASK 0xF0u +#define SJC_GPUSR2_S_STAT_SHIFT 4 +#define SJC_GPUSR2_S_STAT(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_S_STAT_SHIFT))&SJC_GPUSR2_S_STAT_MASK) +#define SJC_GPUSR2_STBYWFE_MASK 0xF00u +#define SJC_GPUSR2_STBYWFE_SHIFT 8 +#define SJC_GPUSR2_STBYWFE(x) (((uint32_t)(((uint32_t)(x))<<SJC_GPUSR2_STBYWFE_SHIFT))&SJC_GPUSR2_STBYWFE_MASK) +/* GPUSR3 Bit Fields */ +#define SJC_GPUSR3_IPG_WAIT_MASK 0x1u +#define SJC_GPUSR3_IPG_WAIT_SHIFT 0 +#define SJC_GPUSR3_IPG_STOP_MASK 0x2u +#define SJC_GPUSR3_IPG_STOP_SHIFT 1 +#define SJC_GPUSR3_SYS_WAIT_MASK 0x4u +#define SJC_GPUSR3_SYS_WAIT_SHIFT 2 +/* SSR Bit Fields */ +#define SJC_SSR_KTF_MASK 0x1u +#define SJC_SSR_KTF_SHIFT 0 +#define SJC_SSR_KTA_MASK 0x2u +#define SJC_SSR_KTA_SHIFT 1 +#define SJC_SSR_SWF_MASK 0x4u +#define SJC_SSR_SWF_SHIFT 2 +#define SJC_SSR_SWE_MASK 0x8u +#define SJC_SSR_SWE_SHIFT 3 +#define SJC_SSR_EBF_MASK 0x10u +#define SJC_SSR_EBF_SHIFT 4 +#define SJC_SSR_EBG_MASK 0x20u +#define SJC_SSR_EBG_SHIFT 5 +#define SJC_SSR_FT_MASK 0x100u +#define SJC_SSR_FT_SHIFT 8 +#define SJC_SSR_SJM_MASK 0x600u +#define SJC_SSR_SJM_SHIFT 9 +#define SJC_SSR_SJM(x) (((uint32_t)(((uint32_t)(x))<<SJC_SSR_SJM_SHIFT))&SJC_SSR_SJM_MASK) +#define SJC_SSR_RSSTAT_MASK 0x1800u +#define SJC_SSR_RSSTAT_SHIFT 11 +#define SJC_SSR_RSSTAT(x) (((uint32_t)(((uint32_t)(x))<<SJC_SSR_RSSTAT_SHIFT))&SJC_SSR_RSSTAT_MASK) +#define SJC_SSR_BOOTIND_MASK 0x4000u +#define SJC_SSR_BOOTIND_SHIFT 14 + +/*! + * @} + */ /* end of group SJC_Register_Masks */ + + +/* SJC - Peripheral instance base addresses */ +/** Peripheral SJC base address */ +#define SJC_BASE (0u) +/** Peripheral SJC base pointer */ +#define SJC ((SJC_Type *)SJC_BASE) +#define SJC_BASE_PTR (SJC) +/** Array initializer of SJC peripheral base adresses */ +#define SJC_BASE_ADDRS { SJC_BASE } +/** Array initializer of SJC peripheral base pointers */ +#define SJC_BASE_PTRS { SJC } + +/* ---------------------------------------------------------------------------- + -- SJC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Register_Accessor_Macros SJC - Register accessor macros + * @{ + */ + + +/* SJC - Register instance definitions */ +/* SJC */ +#define SJC_GPUSR1 SJC_GPUSR1_REG(SJC_BASE_PTR) +#define SJC_GPUSR2 SJC_GPUSR2_REG(SJC_BASE_PTR) +#define SJC_GPUSR3 SJC_GPUSR3_REG(SJC_BASE_PTR) +#define SJC_GPSSR SJC_GPSSR_REG(SJC_BASE_PTR) +#define SJC_DCR SJC_DCR_REG(SJC_BASE_PTR) +#define SJC_SSR SJC_SSR_REG(SJC_BASE_PTR) +#define SJC_GPCCR SJC_GPCCR_REG(SJC_BASE_PTR) + +/*! + * @} + */ /* end of group SJC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SJC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + uint8_t RESERVED_2[16]; + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + uint8_t RESERVED_3[12]; + __IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + uint8_t RESERVED_4[4]; + __IO uint32_t LPGPR; /**< SNVS_LP General Purpose Register, offset: 0x68 */ + uint8_t RESERVED_5[2956]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type, *SNVS_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SNVS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros + * @{ + */ + + +/* SNVS - Register accessors */ +#define SNVS_HPLR_REG(base) ((base)->HPLR) +#define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) +#define SNVS_HPCR_REG(base) ((base)->HPCR) +#define SNVS_HPSR_REG(base) ((base)->HPSR) +#define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) +#define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) +#define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) +#define SNVS_HPTALR_REG(base) ((base)->HPTALR) +#define SNVS_LPLR_REG(base) ((base)->LPLR) +#define SNVS_LPCR_REG(base) ((base)->LPCR) +#define SNVS_LPSR_REG(base) ((base)->LPSR) +#define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) +#define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) +#define SNVS_LPGPR_REG(base) ((base)->LPGPR) +#define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) +#define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) + +/*! + * @} + */ /* end of group SNVS_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/* HPLR Bit Fields */ +#define SNVS_HPLR_MC_SL_MASK 0x10u +#define SNVS_HPLR_MC_SL_SHIFT 4 +#define SNVS_HPLR_GPR_SL_MASK 0x20u +#define SNVS_HPLR_GPR_SL_SHIFT 5 +/* HPCOMR Bit Fields */ +#define SNVS_HPCOMR_LP_SWR_MASK 0x10u +#define SNVS_HPCOMR_LP_SWR_SHIFT 4 +#define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 +#define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u +#define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 +/* HPCR Bit Fields */ +#define SNVS_HPCR_RTC_EN_MASK 0x1u +#define SNVS_HPCR_RTC_EN_SHIFT 0 +#define SNVS_HPCR_HPTA_EN_MASK 0x2u +#define SNVS_HPCR_HPTA_EN_SHIFT 1 +#define SNVS_HPCR_PI_EN_MASK 0x8u +#define SNVS_HPCR_PI_EN_SHIFT 3 +#define SNVS_HPCR_PI_FREQ_MASK 0xF0u +#define SNVS_HPCR_PI_FREQ_SHIFT 4 +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_PI_FREQ_SHIFT))&SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK 0x100u +#define SNVS_HPCR_HPCALB_EN_SHIFT 8 +#define SNVS_HPCR_HPCALB_VAL_MASK 0x7C00u +#define SNVS_HPCR_HPCALB_VAL_SHIFT 10 +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_HPCALB_VAL_SHIFT))&SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK 0x7000000u +#define SNVS_HPCR_BTN_CONFIG_SHIFT 24 +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPCR_BTN_CONFIG_SHIFT))&SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK 0x8000000u +#define SNVS_HPCR_BTN_MASK_SHIFT 27 +/* HPSR Bit Fields */ +#define SNVS_HPSR_BTN_MASK 0x40u +#define SNVS_HPSR_BTN_SHIFT 6 +#define SNVS_HPSR_BI_MASK 0x80u +#define SNVS_HPSR_BI_SHIFT 7 +/* HPRTCMR Bit Fields */ +#define SNVS_HPRTCMR_RTC_MASK 0xFFFFFFFFu +#define SNVS_HPRTCMR_RTC_SHIFT 0 +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCMR_RTC_SHIFT))&SNVS_HPRTCMR_RTC_MASK) +/* HPRTCLR Bit Fields */ +#define SNVS_HPRTCLR_RTC_MASK 0xFFFFFFFFu +#define SNVS_HPRTCLR_RTC_SHIFT 0 +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPRTCLR_RTC_SHIFT))&SNVS_HPRTCLR_RTC_MASK) +/* HPTAMR Bit Fields */ +#define SNVS_HPTAMR_HPTA_MASK 0x7FFFu +#define SNVS_HPTAMR_HPTA_SHIFT 0 +#define SNVS_HPTAMR_HPTA(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPTAMR_HPTA_SHIFT))&SNVS_HPTAMR_HPTA_MASK) +/* HPTALR Bit Fields */ +#define SNVS_HPTALR_HPTA_MASK 0xFFFFFFFFu +#define SNVS_HPTALR_HPTA_SHIFT 0 +#define SNVS_HPTALR_HPTA(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPTALR_HPTA_SHIFT))&SNVS_HPTALR_HPTA_MASK) +/* LPLR Bit Fields */ +#define SNVS_LPLR_MC_HL_MASK 0x10u +#define SNVS_LPLR_MC_HL_SHIFT 4 +#define SNVS_LPLR_GPR_HL_MASK 0x20u +#define SNVS_LPLR_GPR_HL_SHIFT 5 +/* LPCR Bit Fields */ +#define SNVS_LPCR_MC_ENV_MASK 0x4u +#define SNVS_LPCR_MC_ENV_SHIFT 2 +#define SNVS_LPCR_DP_EN_MASK 0x20u +#define SNVS_LPCR_DP_EN_SHIFT 5 +#define SNVS_LPCR_TOP_MASK 0x40u +#define SNVS_LPCR_TOP_SHIFT 6 +#define SNVS_LPCR_PWR_GLITCH_EN_MASK 0x80u +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT 7 +#define SNVS_LPCR_BTN_PRESS_TIME_MASK 0x30000u +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT 16 +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_BTN_PRESS_TIME_SHIFT))&SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK 0xC0000u +#define SNVS_LPCR_DEBOUNCE_SHIFT 18 +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_DEBOUNCE_SHIFT))&SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK 0x300000u +#define SNVS_LPCR_ON_TIME_SHIFT 20 +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPCR_ON_TIME_SHIFT))&SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK 0x400000u +#define SNVS_LPCR_PK_EN_SHIFT 22 +#define SNVS_LPCR_PK_OVERRIDE_MASK 0x800000u +#define SNVS_LPCR_PK_OVERRIDE_SHIFT 23 +/* LPSR Bit Fields */ +#define SNVS_LPSR_MCR_MASK 0x4u +#define SNVS_LPSR_MCR_SHIFT 2 +#define SNVS_LPSR_EO_MASK 0x20000u +#define SNVS_LPSR_EO_SHIFT 17 +#define SNVS_LPSR_SPO_MASK 0x40000u +#define SNVS_LPSR_SPO_SHIFT 18 +/* LPSMCMR Bit Fields */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK 0xFFFFu +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT 0 +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MON_COUNTER_SHIFT))&SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK 0xFFFF0000u +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT 16 +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCMR_MC_ERA_BITS_SHIFT))&SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/* LPSMCLR Bit Fields */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK 0xFFFFFFFFu +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT 0 +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPSMCLR_MON_COUNTER_SHIFT))&SNVS_LPSMCLR_MON_COUNTER_MASK) +/* LPGPR Bit Fields */ +#define SNVS_LPGPR_GPR_MASK 0xFFFFFFFFu +#define SNVS_LPGPR_GPR_SHIFT 0 +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x))<<SNVS_LPGPR_GPR_SHIFT))&SNVS_LPGPR_GPR_MASK) +/* HPVIDR1 Bit Fields */ +#define SNVS_HPVIDR1_MINOR_REV_MASK 0xFFu +#define SNVS_HPVIDR1_MINOR_REV_SHIFT 0 +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MINOR_REV_SHIFT))&SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK 0xFF00u +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT 8 +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_MAJOR_REV_SHIFT))&SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK 0xFFFF0000u +#define SNVS_HPVIDR1_IP_ID_SHIFT 16 +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR1_IP_ID_SHIFT))&SNVS_HPVIDR1_IP_ID_MASK) +/* HPVIDR2 Bit Fields */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK 0xFFu +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT 0 +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_CONFIG_OPT_SHIFT))&SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK 0xFF00u +#define SNVS_HPVIDR2_ECO_REV_SHIFT 8 +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_ECO_REV_SHIFT))&SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK 0xFF0000u +#define SNVS_HPVIDR2_INTG_OPT_SHIFT 16 +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_INTG_OPT_SHIFT))&SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK 0xFF000000u +#define SNVS_HPVIDR2_IP_ERA_SHIFT 24 +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x))<<SNVS_HPVIDR2_IP_ERA_SHIFT))&SNVS_HPVIDR2_IP_ERA_MASK) + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x3037C000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +#define SNVS_BASE_PTR (SNVS) +/** Array initializer of SNVS peripheral base adresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } + +/* ---------------------------------------------------------------------------- + -- SNVS - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Accessor_Macros SNVS - Register accessor macros + * @{ + */ + + +/* SNVS - Register instance definitions */ +/* SNVS */ +#define SNVS_HPLR SNVS_HPLR_REG(SNVS_BASE_PTR) +#define SNVS_HPCOMR SNVS_HPCOMR_REG(SNVS_BASE_PTR) +#define SNVS_HPCR SNVS_HPCR_REG(SNVS_BASE_PTR) +#define SNVS_HPSR SNVS_HPSR_REG(SNVS_BASE_PTR) +#define SNVS_HPRTCMR SNVS_HPRTCMR_REG(SNVS_BASE_PTR) +#define SNVS_HPRTCLR SNVS_HPRTCLR_REG(SNVS_BASE_PTR) +#define SNVS_HPTAMR SNVS_HPTAMR_REG(SNVS_BASE_PTR) +#define SNVS_HPTALR SNVS_HPTALR_REG(SNVS_BASE_PTR) +#define SNVS_LPLR SNVS_LPLR_REG(SNVS_BASE_PTR) +#define SNVS_LPCR SNVS_LPCR_REG(SNVS_BASE_PTR) +#define SNVS_LPSR SNVS_LPSR_REG(SNVS_BASE_PTR) +#define SNVS_LPSMCMR SNVS_LPSMCMR_REG(SNVS_BASE_PTR) +#define SNVS_LPSMCLR SNVS_LPSMCLR_REG(SNVS_BASE_PTR) +#define SNVS_LPGPR SNVS_LPGPR_REG(SNVS_BASE_PTR) +#define SNVS_HPVIDR1 SNVS_HPVIDR1_REG(SNVS_BASE_PTR) +#define SNVS_HPVIDR2 SNVS_HPVIDR2_REG(SNVS_BASE_PTR) + +/*! + * @} + */ /* end of group SNVS_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SNVS_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SPBA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer + * @{ + */ + +/** SPBA - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ +} SPBA_Type, *SPBA_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SPBA - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros + * @{ + */ + + +/* SPBA - Register accessors */ +#define SPBA_PRR_REG(base,index) ((base)->PRR[index]) + +/*! + * @} + */ /* end of group SPBA_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/* PRR Bit Fields */ +#define SPBA_PRR_RARA_MASK 0x1u +#define SPBA_PRR_RARA_SHIFT 0 +#define SPBA_PRR_RARB_MASK 0x2u +#define SPBA_PRR_RARB_SHIFT 1 +#define SPBA_PRR_RARC_MASK 0x4u +#define SPBA_PRR_RARC_SHIFT 2 +#define SPBA_PRR_ROI_MASK 0x30000u +#define SPBA_PRR_ROI_SHIFT 16 +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_ROI_SHIFT))&SPBA_PRR_ROI_MASK) +#define SPBA_PRR_RMO_MASK 0xC0000000u +#define SPBA_PRR_RMO_SHIFT 30 +#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x))<<SPBA_PRR_RMO_SHIFT))&SPBA_PRR_RMO_MASK) + +/*! + * @} + */ /* end of group SPBA_Register_Masks */ + + +/* SPBA - Peripheral instance base addresses */ +/** Peripheral SPBA base address */ +#define SPBA_BASE (0x308F0000u) +/** Peripheral SPBA base pointer */ +#define SPBA ((SPBA_Type *)SPBA_BASE) +#define SPBA_BASE_PTR (SPBA) +/** Array initializer of SPBA peripheral base adresses */ +#define SPBA_BASE_ADDRS { SPBA_BASE } +/** Array initializer of SPBA peripheral base pointers */ +#define SPBA_BASE_PTRS { SPBA } + +/* ---------------------------------------------------------------------------- + -- SPBA - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Accessor_Macros SPBA - Register accessor macros + * @{ + */ + + +/* SPBA - Register instance definitions */ +/* SPBA */ +#define SPBA_PRR0 SPBA_PRR_REG(SPBA_BASE_PTR,0) +#define SPBA_PRR1 SPBA_PRR_REG(SPBA_BASE_PTR,1) +#define SPBA_PRR2 SPBA_PRR_REG(SPBA_BASE_PTR,2) +#define SPBA_PRR3 SPBA_PRR_REG(SPBA_BASE_PTR,3) +#define SPBA_PRR4 SPBA_PRR_REG(SPBA_BASE_PTR,4) +#define SPBA_PRR5 SPBA_PRR_REG(SPBA_BASE_PTR,5) +#define SPBA_PRR6 SPBA_PRR_REG(SPBA_BASE_PTR,6) +#define SPBA_PRR7 SPBA_PRR_REG(SPBA_BASE_PTR,7) +#define SPBA_PRR8 SPBA_PRR_REG(SPBA_BASE_PTR,8) +#define SPBA_PRR9 SPBA_PRR_REG(SPBA_BASE_PTR,9) +#define SPBA_PRR10 SPBA_PRR_REG(SPBA_BASE_PTR,10) +#define SPBA_PRR11 SPBA_PRR_REG(SPBA_BASE_PTR,11) +#define SPBA_PRR12 SPBA_PRR_REG(SPBA_BASE_PTR,12) +#define SPBA_PRR13 SPBA_PRR_REG(SPBA_BASE_PTR,13) +#define SPBA_PRR14 SPBA_PRR_REG(SPBA_BASE_PTR,14) +#define SPBA_PRR15 SPBA_PRR_REG(SPBA_BASE_PTR,15) +#define SPBA_PRR16 SPBA_PRR_REG(SPBA_BASE_PTR,16) +#define SPBA_PRR17 SPBA_PRR_REG(SPBA_BASE_PTR,17) +#define SPBA_PRR18 SPBA_PRR_REG(SPBA_BASE_PTR,18) +#define SPBA_PRR19 SPBA_PRR_REG(SPBA_BASE_PTR,19) +#define SPBA_PRR20 SPBA_PRR_REG(SPBA_BASE_PTR,20) +#define SPBA_PRR21 SPBA_PRR_REG(SPBA_BASE_PTR,21) +#define SPBA_PRR22 SPBA_PRR_REG(SPBA_BASE_PTR,22) +#define SPBA_PRR23 SPBA_PRR_REG(SPBA_BASE_PTR,23) +#define SPBA_PRR24 SPBA_PRR_REG(SPBA_BASE_PTR,24) +#define SPBA_PRR25 SPBA_PRR_REG(SPBA_BASE_PTR,25) +#define SPBA_PRR26 SPBA_PRR_REG(SPBA_BASE_PTR,26) +#define SPBA_PRR27 SPBA_PRR_REG(SPBA_BASE_PTR,27) +#define SPBA_PRR28 SPBA_PRR_REG(SPBA_BASE_PTR,28) +#define SPBA_PRR29 SPBA_PRR_REG(SPBA_BASE_PTR,29) +#define SPBA_PRR30 SPBA_PRR_REG(SPBA_BASE_PTR,30) +#define SPBA_PRR31 SPBA_PRR_REG(SPBA_BASE_PTR,31) + +/* SPBA - Register array accessors */ +#define SPBA_PRR(index) SPBA_PRR_REG(SPBA_BASE_PTR,index) + +/*! + * @} + */ /* end of group SPBA_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SPBA_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Reset Control Register, offset: 0x0 */ + __IO uint32_t A7RCR0; /**< A7 Reset Control Register, offset: 0x4 */ + __IO uint32_t A7RCR1; /**< A7 Reset Control Register, offset: 0x8 */ + __IO uint32_t M4RCR; /**< M4 Reset Control Register, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERCR; /**< EIM Reset Control Register, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __IO uint32_t HSICPHY_RCR; /**< HSIC PHY Reset Control Register, offset: 0x1C */ + __IO uint32_t USBOPHY1_RCR; /**< USB OTG PHY1 Reset Control Register, offset: 0x20 */ + __IO uint32_t USBOPHY2_RCR; /**< USB OTG PHY2 Reset Control Register, offset: 0x24 */ + __IO uint32_t MIPIPHY_RCR; /**< MIPI PHY Reset Control Register, offset: 0x28 */ + __IO uint32_t PCIEPHY_RCR; /**< PCIE PHY Reset Control Register, offset: 0x2C */ + uint8_t RESERVED_2[40]; + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x58 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x5C */ + uint8_t RESERVED_3[8]; + __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x68 */ + __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */ + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x70 */ + __IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x74 */ + __IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x78 */ + __IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x7C */ + __IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x80 */ + __IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84 */ + __IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x88 */ + __IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x8C */ + __IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x90 */ + __IO uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x94 */ + __IO uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x98 */ + uint8_t RESERVED_4[3940]; + __IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */ +} SRC_Type, *SRC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SRC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros + * @{ + */ + + +/* SRC - Register accessors */ +#define SRC_SCR_REG(base) ((base)->SCR) +#define SRC_A7RCR0_REG(base) ((base)->A7RCR0) +#define SRC_A7RCR1_REG(base) ((base)->A7RCR1) +#define SRC_M4RCR_REG(base) ((base)->M4RCR) +#define SRC_ERCR_REG(base) ((base)->ERCR) +#define SRC_HSICPHY_RCR_REG(base) ((base)->HSICPHY_RCR) +#define SRC_USBOPHY1_RCR_REG(base) ((base)->USBOPHY1_RCR) +#define SRC_USBOPHY2_RCR_REG(base) ((base)->USBOPHY2_RCR) +#define SRC_MIPIPHY_RCR_REG(base) ((base)->MIPIPHY_RCR) +#define SRC_PCIEPHY_RCR_REG(base) ((base)->PCIEPHY_RCR) +#define SRC_SBMR1_REG(base) ((base)->SBMR1) +#define SRC_SRSR_REG(base) ((base)->SRSR) +#define SRC_SISR_REG(base) ((base)->SISR) +#define SRC_SIMR_REG(base) ((base)->SIMR) +#define SRC_SBMR2_REG(base) ((base)->SBMR2) +#define SRC_GPR1_REG(base) ((base)->GPR1) +#define SRC_GPR2_REG(base) ((base)->GPR2) +#define SRC_GPR3_REG(base) ((base)->GPR3) +#define SRC_GPR4_REG(base) ((base)->GPR4) +#define SRC_GPR5_REG(base) ((base)->GPR5) +#define SRC_GPR6_REG(base) ((base)->GPR6) +#define SRC_GPR7_REG(base) ((base)->GPR7) +#define SRC_GPR8_REG(base) ((base)->GPR8) +#define SRC_GPR9_REG(base) ((base)->GPR9) +#define SRC_GPR10_REG(base) ((base)->GPR10) +#define SRC_DDRC_RCR_REG(base) ((base)->DDRC_RCR) + +/*! + * @} + */ /* end of group SRC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/* SCR Bit Fields */ +#define SRC_SCR_MASK_TEMPSENSE_RESET_MASK 0xF0u +#define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT 4 +#define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x))<<SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT))&SRC_SCR_MASK_TEMPSENSE_RESET_MASK) +#define SRC_SCR_DOMAIN0_MASK 0x1000000u +#define SRC_SCR_DOMAIN0_SHIFT 24 +#define SRC_SCR_DOMAIN1_MASK 0x2000000u +#define SRC_SCR_DOMAIN1_SHIFT 25 +#define SRC_SCR_DOMAIN2_MASK 0x4000000u +#define SRC_SCR_DOMAIN2_SHIFT 26 +#define SRC_SCR_DOMAIN3_MASK 0x8000000u +#define SRC_SCR_DOMAIN3_SHIFT 27 +#define SRC_SCR_LOCK_MASK 0x40000000u +#define SRC_SCR_LOCK_SHIFT 30 +#define SRC_SCR_DOM_EN_MASK 0x80000000u +#define SRC_SCR_DOM_EN_SHIFT 31 +/* A7RCR0 Bit Fields */ +#define SRC_A7RCR0_A7_CORE_POR_RESET0_MASK 0x1u +#define SRC_A7RCR0_A7_CORE_POR_RESET0_SHIFT 0 +#define SRC_A7RCR0_A7_CORE_POR_RESET1_MASK 0x2u +#define SRC_A7RCR0_A7_CORE_POR_RESET1_SHIFT 1 +#define SRC_A7RCR0_A7_CORE_RESET0_MASK 0x10u +#define SRC_A7RCR0_A7_CORE_RESET0_SHIFT 4 +#define SRC_A7RCR0_A7_CORE_RESET1_MASK 0x20u +#define SRC_A7RCR0_A7_CORE_RESET1_SHIFT 5 +#define SRC_A7RCR0_A7_DBG_RESET0_MASK 0x100u +#define SRC_A7RCR0_A7_DBG_RESET0_SHIFT 8 +#define SRC_A7RCR0_A7_DBG_RESET1_MASK 0x200u +#define SRC_A7RCR0_A7_DBG_RESET1_SHIFT 9 +#define SRC_A7RCR0_A7_ETM_RESET0_MASK 0x1000u +#define SRC_A7RCR0_A7_ETM_RESET0_SHIFT 12 +#define SRC_A7RCR0_A7_ETM_RESET1_MASK 0x2000u +#define SRC_A7RCR0_A7_ETM_RESET1_SHIFT 13 +#define SRC_A7RCR0_MASK_WDOG1_RST_MASK 0xF0000u +#define SRC_A7RCR0_MASK_WDOG1_RST_SHIFT 16 +#define SRC_A7RCR0_MASK_WDOG1_RST(x) (((uint32_t)(((uint32_t)(x))<<SRC_A7RCR0_MASK_WDOG1_RST_SHIFT))&SRC_A7RCR0_MASK_WDOG1_RST_MASK) +#define SRC_A7RCR0_A7_SOC_DBG_RESET_MASK 0x100000u +#define SRC_A7RCR0_A7_SOC_DBG_RESET_SHIFT 20 +#define SRC_A7RCR0_A7_L2RESET_MASK 0x200000u +#define SRC_A7RCR0_A7_L2RESET_SHIFT 21 +#define SRC_A7RCR0_DOMAIN0_MASK 0x1000000u +#define SRC_A7RCR0_DOMAIN0_SHIFT 24 +#define SRC_A7RCR0_DOMAIN1_MASK 0x2000000u +#define SRC_A7RCR0_DOMAIN1_SHIFT 25 +#define SRC_A7RCR0_DOMAIN2_MASK 0x4000000u +#define SRC_A7RCR0_DOMAIN2_SHIFT 26 +#define SRC_A7RCR0_DOMAIN3_MASK 0x8000000u +#define SRC_A7RCR0_DOMAIN3_SHIFT 27 +#define SRC_A7RCR0_LOCK_MASK 0x40000000u +#define SRC_A7RCR0_LOCK_SHIFT 30 +#define SRC_A7RCR0_DOM_EN_MASK 0x80000000u +#define SRC_A7RCR0_DOM_EN_SHIFT 31 +/* A7RCR1 Bit Fields */ +#define SRC_A7RCR1_A7_CORE1_ENABLE_MASK 0x2u +#define SRC_A7RCR1_A7_CORE1_ENABLE_SHIFT 1 +#define SRC_A7RCR1_DOMAIN0_MASK 0x1000000u +#define SRC_A7RCR1_DOMAIN0_SHIFT 24 +#define SRC_A7RCR1_DOMAIN1_MASK 0x2000000u +#define SRC_A7RCR1_DOMAIN1_SHIFT 25 +#define SRC_A7RCR1_DOMAIN2_MASK 0x4000000u +#define SRC_A7RCR1_DOMAIN2_SHIFT 26 +#define SRC_A7RCR1_DOMAIN3_MASK 0x8000000u +#define SRC_A7RCR1_DOMAIN3_SHIFT 27 +#define SRC_A7RCR1_LOCK_MASK 0x40000000u +#define SRC_A7RCR1_LOCK_SHIFT 30 +#define SRC_A7RCR1_DOM_EN_MASK 0x80000000u +#define SRC_A7RCR1_DOM_EN_SHIFT 31 +/* M4RCR Bit Fields */ +#define SRC_M4RCR_SW_M4C_NON_SCLR_RST_MASK 0x1u +#define SRC_M4RCR_SW_M4C_NON_SCLR_RST_SHIFT 0 +#define SRC_M4RCR_SW_M4C_RST_MASK 0x2u +#define SRC_M4RCR_SW_M4C_RST_SHIFT 1 +#define SRC_M4RCR_SW_M4P_RST_MASK 0x4u +#define SRC_M4RCR_SW_M4P_RST_SHIFT 2 +#define SRC_M4RCR_ENABLE_M4_MASK 0x8u +#define SRC_M4RCR_ENABLE_M4_SHIFT 3 +#define SRC_M4RCR_MASK_WDOG3_RST_MASK 0xF0u +#define SRC_M4RCR_MASK_WDOG3_RST_SHIFT 4 +#define SRC_M4RCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x))<<SRC_M4RCR_MASK_WDOG3_RST_SHIFT))&SRC_M4RCR_MASK_WDOG3_RST_MASK) +#define SRC_M4RCR_WDOG3_RST_OPTION_M4_MASK 0x100u +#define SRC_M4RCR_WDOG3_RST_OPTION_M4_SHIFT 8 +#define SRC_M4RCR_WDOG3_RST_OPTION_MASK 0x200u +#define SRC_M4RCR_WDOG3_RST_OPTION_SHIFT 9 +#define SRC_M4RCR_DOMAIN0_MASK 0x1000000u +#define SRC_M4RCR_DOMAIN0_SHIFT 24 +#define SRC_M4RCR_DOMAIN1_MASK 0x2000000u +#define SRC_M4RCR_DOMAIN1_SHIFT 25 +#define SRC_M4RCR_DOMAIN2_MASK 0x4000000u +#define SRC_M4RCR_DOMAIN2_SHIFT 26 +#define SRC_M4RCR_DOMAIN3_MASK 0x8000000u +#define SRC_M4RCR_DOMAIN3_SHIFT 27 +#define SRC_M4RCR_LOCK_MASK 0x40000000u +#define SRC_M4RCR_LOCK_SHIFT 30 +#define SRC_M4RCR_DOM_EN_MASK 0x80000000u +#define SRC_M4RCR_DOM_EN_SHIFT 31 +/* ERCR Bit Fields */ +#define SRC_ERCR_EIM_RST_MASK 0x1u +#define SRC_ERCR_EIM_RST_SHIFT 0 +#define SRC_ERCR_DOMAIN0_MASK 0x1000000u +#define SRC_ERCR_DOMAIN0_SHIFT 24 +#define SRC_ERCR_DOMAIN1_MASK 0x2000000u +#define SRC_ERCR_DOMAIN1_SHIFT 25 +#define SRC_ERCR_DOMAIN2_MASK 0x4000000u +#define SRC_ERCR_DOMAIN2_SHIFT 26 +#define SRC_ERCR_DOMAIN3_MASK 0x8000000u +#define SRC_ERCR_DOMAIN3_SHIFT 27 +#define SRC_ERCR_LOCK_MASK 0x40000000u +#define SRC_ERCR_LOCK_SHIFT 30 +#define SRC_ERCR_DOM_EN_MASK 0x80000000u +#define SRC_ERCR_DOM_EN_SHIFT 31 +/* HSICPHY_RCR Bit Fields */ +#define SRC_HSICPHY_RCR_HSIC_PHY_POR_MASK 0x1u +#define SRC_HSICPHY_RCR_HSIC_PHY_POR_SHIFT 0 +#define SRC_HSICPHY_RCR_HSICPHY_PORT_RST_MASK 0x2u +#define SRC_HSICPHY_RCR_HSICPHY_PORT_RST_SHIFT 1 +#define SRC_HSICPHY_RCR_DOMAIN0_MASK 0x1000000u +#define SRC_HSICPHY_RCR_DOMAIN0_SHIFT 24 +#define SRC_HSICPHY_RCR_DOMAIN1_MASK 0x2000000u +#define SRC_HSICPHY_RCR_DOMAIN1_SHIFT 25 +#define SRC_HSICPHY_RCR_DOMAIN2_MASK 0x4000000u +#define SRC_HSICPHY_RCR_DOMAIN2_SHIFT 26 +#define SRC_HSICPHY_RCR_DOMAIN3_MASK 0x8000000u +#define SRC_HSICPHY_RCR_DOMAIN3_SHIFT 27 +#define SRC_HSICPHY_RCR_LOCK_MASK 0x40000000u +#define SRC_HSICPHY_RCR_LOCK_SHIFT 30 +#define SRC_HSICPHY_RCR_DOM_EN_MASK 0x80000000u +#define SRC_HSICPHY_RCR_DOM_EN_SHIFT 31 +/* USBOPHY1_RCR Bit Fields */ +#define SRC_USBOPHY1_RCR_USBPHY1_POR_MASK 0x1u +#define SRC_USBOPHY1_RCR_USBPHY1_POR_SHIFT 0 +#define SRC_USBOPHY1_RCR_USBPHY1_PORT_RST_MASK 0x2u +#define SRC_USBOPHY1_RCR_USBPHY1_PORT_RST_SHIFT 1 +#define SRC_USBOPHY1_RCR_DOMAIN0_MASK 0x1000000u +#define SRC_USBOPHY1_RCR_DOMAIN0_SHIFT 24 +#define SRC_USBOPHY1_RCR_DOMAIN1_MASK 0x2000000u +#define SRC_USBOPHY1_RCR_DOMAIN1_SHIFT 25 +#define SRC_USBOPHY1_RCR_DOMAIN2_MASK 0x4000000u +#define SRC_USBOPHY1_RCR_DOMAIN2_SHIFT 26 +#define SRC_USBOPHY1_RCR_DOMAIN3_MASK 0x8000000u +#define SRC_USBOPHY1_RCR_DOMAIN3_SHIFT 27 +#define SRC_USBOPHY1_RCR_LOCK_MASK 0x40000000u +#define SRC_USBOPHY1_RCR_LOCK_SHIFT 30 +#define SRC_USBOPHY1_RCR_DOM_EN_MASK 0x80000000u +#define SRC_USBOPHY1_RCR_DOM_EN_SHIFT 31 +/* USBOPHY2_RCR Bit Fields */ +#define SRC_USBOPHY2_RCR_USBPHY2_POR_MASK 0x1u +#define SRC_USBOPHY2_RCR_USBPHY2_POR_SHIFT 0 +#define SRC_USBOPHY2_RCR_USBPHY2_PORT_RST_MASK 0x2u +#define SRC_USBOPHY2_RCR_USBPHY2_PORT_RST_SHIFT 1 +#define SRC_USBOPHY2_RCR_DOMAIN0_MASK 0x1000000u +#define SRC_USBOPHY2_RCR_DOMAIN0_SHIFT 24 +#define SRC_USBOPHY2_RCR_DOMAIN1_MASK 0x2000000u +#define SRC_USBOPHY2_RCR_DOMAIN1_SHIFT 25 +#define SRC_USBOPHY2_RCR_DOMAIN2_MASK 0x4000000u +#define SRC_USBOPHY2_RCR_DOMAIN2_SHIFT 26 +#define SRC_USBOPHY2_RCR_DOMAIN3_MASK 0x8000000u +#define SRC_USBOPHY2_RCR_DOMAIN3_SHIFT 27 +#define SRC_USBOPHY2_RCR_LOCK_MASK 0x40000000u +#define SRC_USBOPHY2_RCR_LOCK_SHIFT 30 +#define SRC_USBOPHY2_RCR_DOM_EN_MASK 0x80000000u +#define SRC_USBOPHY2_RCR_DOM_EN_SHIFT 31 +/* MIPIPHY_RCR Bit Fields */ +#define SRC_MIPIPHY_RCR_MIPI_PHY_MRST_MASK 0x1u +#define SRC_MIPIPHY_RCR_MIPI_PHY_MRST_SHIFT 0 +#define SRC_MIPIPHY_RCR_MIPI_PHY_SRST_MASK 0x2u +#define SRC_MIPIPHY_RCR_MIPI_PHY_SRST_SHIFT 1 +#define SRC_MIPIPHY_RCR_DOMAIN0_MASK 0x1000000u +#define SRC_MIPIPHY_RCR_DOMAIN0_SHIFT 24 +#define SRC_MIPIPHY_RCR_DOMAIN1_MASK 0x2000000u +#define SRC_MIPIPHY_RCR_DOMAIN1_SHIFT 25 +#define SRC_MIPIPHY_RCR_DOMAIN2_MASK 0x4000000u +#define SRC_MIPIPHY_RCR_DOMAIN2_SHIFT 26 +#define SRC_MIPIPHY_RCR_DOMAIN3_MASK 0x8000000u +#define SRC_MIPIPHY_RCR_DOMAIN3_SHIFT 27 +#define SRC_MIPIPHY_RCR_LOCK_MASK 0x40000000u +#define SRC_MIPIPHY_RCR_LOCK_SHIFT 30 +#define SRC_MIPIPHY_RCR_DOM_EN_MASK 0x80000000u +#define SRC_MIPIPHY_RCR_DOM_EN_SHIFT 31 +/* PCIEPHY_RCR Bit Fields */ +#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_MASK 0x2u +#define SRC_PCIEPHY_RCR_PCIEPHY_G_RST_SHIFT 1 +#define SRC_PCIEPHY_RCR_PCIEPHY_BTN_MASK 0x4u +#define SRC_PCIEPHY_RCR_PCIEPHY_BTN_SHIFT 2 +#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK 0x8u +#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT 3 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK 0x10u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT 4 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK 0x20u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT 5 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK 0x40u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT 6 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK 0x80u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT 7 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK 0x100u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT 8 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK 0x200u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT 9 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK 0x400u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT 10 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK 0x800u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT 11 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK 0x1000u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT 12 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_MAC_MASK 0x2000u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_MAC_SHIFT 13 +#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK 0x4000u +#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT 14 +#define SRC_PCIEPHY_RCR_DOMAIN0_MASK 0x1000000u +#define SRC_PCIEPHY_RCR_DOMAIN0_SHIFT 24 +#define SRC_PCIEPHY_RCR_DOMAIN1_MASK 0x2000000u +#define SRC_PCIEPHY_RCR_DOMAIN1_SHIFT 25 +#define SRC_PCIEPHY_RCR_DOMAIN2_MASK 0x4000000u +#define SRC_PCIEPHY_RCR_DOMAIN2_SHIFT 26 +#define SRC_PCIEPHY_RCR_DOMAIN3_MASK 0x8000000u +#define SRC_PCIEPHY_RCR_DOMAIN3_SHIFT 27 +#define SRC_PCIEPHY_RCR_LOCK_MASK 0x40000000u +#define SRC_PCIEPHY_RCR_LOCK_SHIFT 30 +#define SRC_PCIEPHY_RCR_DOM_EN_MASK 0x80000000u +#define SRC_PCIEPHY_RCR_DOM_EN_SHIFT 31 +/* SBMR1 Bit Fields */ +#define SRC_SBMR1_BOOT_CFG1_MASK 0xFFu +#define SRC_SBMR1_BOOT_CFG1_SHIFT 0 +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG1_SHIFT))&SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK 0xFF00u +#define SRC_SBMR1_BOOT_CFG2_SHIFT 8 +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG2_SHIFT))&SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK 0xFF0000u +#define SRC_SBMR1_BOOT_CFG3_SHIFT 16 +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG3_SHIFT))&SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK 0xFF000000u +#define SRC_SBMR1_BOOT_CFG4_SHIFT 24 +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR1_BOOT_CFG4_SHIFT))&SRC_SBMR1_BOOT_CFG4_MASK) +/* SRSR Bit Fields */ +#define SRC_SRSR_ipp_reset_b_MASK 0x1u +#define SRC_SRSR_ipp_reset_b_SHIFT 0 +#define SRC_SRSR_csu_reset_b_MASK 0x4u +#define SRC_SRSR_csu_reset_b_SHIFT 2 +#define SRC_SRSR_ipp_user_reset_b_MASK 0x8u +#define SRC_SRSR_ipp_user_reset_b_SHIFT 3 +#define SRC_SRSR_wdog1_rst_b_MASK 0x10u +#define SRC_SRSR_wdog1_rst_b_SHIFT 4 +#define SRC_SRSR_jtag_rst_b_MASK 0x20u +#define SRC_SRSR_jtag_rst_b_SHIFT 5 +#define SRC_SRSR_jtag_sw_rst_MASK 0x40u +#define SRC_SRSR_jtag_sw_rst_SHIFT 6 +#define SRC_SRSR_wdog3_rst_b_MASK 0x80u +#define SRC_SRSR_wdog3_rst_b_SHIFT 7 +#define SRC_SRSR_wdog4_rst_b_MASK 0x100u +#define SRC_SRSR_wdog4_rst_b_SHIFT 8 +#define SRC_SRSR_tempsense_rst_b_MASK 0x200u +#define SRC_SRSR_tempsense_rst_b_SHIFT 9 +/* SISR Bit Fields */ +#define SRC_SISR_HSICPHY_PASSED_RESET_MASK 0x2u +#define SRC_SISR_HSICPHY_PASSED_RESET_SHIFT 1 +#define SRC_SISR_OTGPHY1_PASSED_RESET_MASK 0x4u +#define SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT 2 +#define SRC_SISR_OTGPHY2_PASSED_RESET_MASK 0x8u +#define SRC_SISR_OTGPHY2_PASSED_RESET_SHIFT 3 +#define SRC_SISR_MIPIPHY_PASSED_RESET_MASK 0x10u +#define SRC_SISR_MIPIPHY_PASSED_RESET_SHIFT 4 +#define SRC_SISR_M4C_PASSED_RESET_MASK 0x100u +#define SRC_SISR_M4C_PASSED_RESET_SHIFT 8 +#define SRC_SISR_M4P_PASSED_RESET_MASK 0x200u +#define SRC_SISR_M4P_PASSED_RESET_SHIFT 9 +/* SIMR Bit Fields */ +#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_MASK 0x2u +#define SRC_SIMR_MASK_HSICPHY_PASSED_RESET_SHIFT 1 +#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK 0x4u +#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT 2 +#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_MASK 0x8u +#define SRC_SIMR_MASK_OTGPHY2_PASSED_RESET_SHIFT 3 +#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_MASK 0x10u +#define SRC_SIMR_MASK_MIPIPHY_PASSED_RESET_SHIFT 4 +#define SRC_SIMR_MASK_M4C_PASSED_RESET_MASK 0x100u +#define SRC_SIMR_MASK_M4C_PASSED_RESET_SHIFT 8 +#define SRC_SIMR_MASK_M4P_PASSED_RESET_MASK 0x200u +#define SRC_SIMR_MASK_M4P_PASSED_RESET_SHIFT 9 +/* SBMR2 Bit Fields */ +#define SRC_SBMR2_SEC_CONFIG_MASK 0x3u +#define SRC_SBMR2_SEC_CONFIG_SHIFT 0 +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_SEC_CONFIG_SHIFT))&SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK 0x8u +#define SRC_SBMR2_DIR_BT_DIS_SHIFT 3 +#define SRC_SBMR2_BT_FUSE_SEL_MASK 0x10u +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT 4 +#define SRC_SBMR2_BMOD_MASK 0x3000000u +#define SRC_SBMR2_BMOD_SHIFT 24 +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x))<<SRC_SBMR2_BMOD_SHIFT))&SRC_SBMR2_BMOD_MASK) +/* GPR1 Bit Fields */ +#define SRC_GPR1_PERSISTENT_ENTRY0_MASK 0xFFFFFFFFu +#define SRC_GPR1_PERSISTENT_ENTRY0_SHIFT 0 +#define SRC_GPR1_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR1_PERSISTENT_ENTRY0_SHIFT))&SRC_GPR1_PERSISTENT_ENTRY0_MASK) +/* GPR2 Bit Fields */ +#define SRC_GPR2_PERSISTENT_ARG0_MASK 0xFFFFFFFFu +#define SRC_GPR2_PERSISTENT_ARG0_SHIFT 0 +#define SRC_GPR2_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR2_PERSISTENT_ARG0_SHIFT))&SRC_GPR2_PERSISTENT_ARG0_MASK) +/* GPR3 Bit Fields */ +#define SRC_GPR3_PERSISTENT_ENTRY1_MASK 0xFFFFFFFFu +#define SRC_GPR3_PERSISTENT_ENTRY1_SHIFT 0 +#define SRC_GPR3_PERSISTENT_ENTRY1(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR3_PERSISTENT_ENTRY1_SHIFT))&SRC_GPR3_PERSISTENT_ENTRY1_MASK) +/* GPR4 Bit Fields */ +#define SRC_GPR4_PERSISTENT_ARG1_MASK 0xFFFFFFFFu +#define SRC_GPR4_PERSISTENT_ARG1_SHIFT 0 +#define SRC_GPR4_PERSISTENT_ARG1(x) (((uint32_t)(((uint32_t)(x))<<SRC_GPR4_PERSISTENT_ARG1_SHIFT))&SRC_GPR4_PERSISTENT_ARG1_MASK) +/* DDRC_RCR Bit Fields */ +#define SRC_DDRC_RCR_DDRC_PRST_MASK 0x1u +#define SRC_DDRC_RCR_DDRC_PRST_SHIFT 0 +#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK 0x2u +#define SRC_DDRC_RCR_DDRC_CORE_RST_SHIFT 1 +#define SRC_DDRC_RCR_DOMAIN0_MASK 0x1000000u +#define SRC_DDRC_RCR_DOMAIN0_SHIFT 24 +#define SRC_DDRC_RCR_DOMAIN1_MASK 0x2000000u +#define SRC_DDRC_RCR_DOMAIN1_SHIFT 25 +#define SRC_DDRC_RCR_DOMAIN2_MASK 0x4000000u +#define SRC_DDRC_RCR_DOMAIN2_SHIFT 26 +#define SRC_DDRC_RCR_DOMAIN3_MASK 0x8000000u +#define SRC_DDRC_RCR_DOMAIN3_SHIFT 27 +#define SRC_DDRC_RCR_LOCK_MASK 0x40000000u +#define SRC_DDRC_RCR_LOCK_SHIFT 30 +#define SRC_DDRC_RCR_DOM_EN_MASK 0x80000000u +#define SRC_DDRC_RCR_DOM_EN_SHIFT 31 + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x30390000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +#define SRC_BASE_PTR (SRC) +/** Array initializer of SRC peripheral base adresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } + +/* ---------------------------------------------------------------------------- + -- SRC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Accessor_Macros SRC - Register accessor macros + * @{ + */ + + +/* SRC - Register instance definitions */ +/* SRC */ +#define SRC_SCR SRC_SCR_REG(SRC_BASE_PTR) +#define SRC_A7RCR0 SRC_A7RCR0_REG(SRC_BASE_PTR) +#define SRC_A7RCR1 SRC_A7RCR1_REG(SRC_BASE_PTR) +#define SRC_M4RCR SRC_M4RCR_REG(SRC_BASE_PTR) +#define SRC_ERCR SRC_ERCR_REG(SRC_BASE_PTR) +#define SRC_HSICPHY_RCR SRC_HSICPHY_RCR_REG(SRC_BASE_PTR) +#define SRC_USBOPHY1_RCR SRC_USBOPHY1_RCR_REG(SRC_BASE_PTR) +#define SRC_USBOPHY2_RCR SRC_USBOPHY2_RCR_REG(SRC_BASE_PTR) +#define SRC_MIPIPHY_RCR SRC_MIPIPHY_RCR_REG(SRC_BASE_PTR) +#define SRC_PCIEPHY_RCR SRC_PCIEPHY_RCR_REG(SRC_BASE_PTR) +#define SRC_SBMR1 SRC_SBMR1_REG(SRC_BASE_PTR) +#define SRC_SRSR SRC_SRSR_REG(SRC_BASE_PTR) +#define SRC_SISR SRC_SISR_REG(SRC_BASE_PTR) +#define SRC_SIMR SRC_SIMR_REG(SRC_BASE_PTR) +#define SRC_SBMR2 SRC_SBMR2_REG(SRC_BASE_PTR) +#define SRC_GPR1 SRC_GPR1_REG(SRC_BASE_PTR) +#define SRC_GPR2 SRC_GPR2_REG(SRC_BASE_PTR) +#define SRC_GPR3 SRC_GPR3_REG(SRC_BASE_PTR) +#define SRC_GPR4 SRC_GPR4_REG(SRC_BASE_PTR) +#define SRC_GPR5 SRC_GPR5_REG(SRC_BASE_PTR) +#define SRC_GPR6 SRC_GPR6_REG(SRC_BASE_PTR) +#define SRC_GPR7 SRC_GPR7_REG(SRC_BASE_PTR) +#define SRC_GPR8 SRC_GPR8_REG(SRC_BASE_PTR) +#define SRC_GPR9 SRC_GPR9_REG(SRC_BASE_PTR) +#define SRC_GPR10 SRC_GPR10_REG(SRC_BASE_PTR) +#define SRC_DDRC_RCR SRC_DDRC_RCR_REG(SRC_BASE_PTR) + +/*! + * @} + */ /* end of group SRC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group SRC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[768]; + __IO uint32_t HW_ANADIG_TEMPSENSE0; /**< Anadig Tempsensor Control Register 0, offset: 0x300 */ + __IO uint32_t HW_ANADIG_TEMPSENSE0_SET; /**< Anadig Tempsensor Control Register 0, offset: 0x304 */ + __IO uint32_t HW_ANADIG_TEMPSENSE0_CLR; /**< Anadig Tempsensor Control Register 0, offset: 0x308 */ + __IO uint32_t HW_ANADIG_TEMPSENSE0_TOG; /**< Anadig Tempsensor Control Register 0, offset: 0x30C */ + __IO uint32_t HW_ANADIG_TEMPSENSE1; /**< Anadig Tempsensor Control Register 1, offset: 0x310 */ + __IO uint32_t HW_ANADIG_TEMPSENSE1_SET; /**< Anadig Tempsensor Control Register 1, offset: 0x314 */ + __IO uint32_t HW_ANADIG_TEMPSENSE1_CLR; /**< Anadig Tempsensor Control Register 1, offset: 0x318 */ + __IO uint32_t HW_ANADIG_TEMPSENSE1_TOG; /**< Anadig Tempsensor Control Register 1, offset: 0x31C */ + __IO uint32_t HW_ANADIG_TEMPSENSE_TRIM; /**< Anadig Tempsensor Trim Control Register, offset: 0x320 */ + __IO uint32_t HW_ANADIG_TEMPSENSE_TRIM_SET; /**< Anadig Tempsensor Trim Control Register, offset: 0x324 */ + __IO uint32_t HW_ANADIG_TEMPSENSE_TRIM_CLR; /**< Anadig Tempsensor Trim Control Register, offset: 0x328 */ + __IO uint32_t HW_ANADIG_TEMPSENSE_TRIM_TOG; /**< Anadig Tempsensor Trim Control Register, offset: 0x32C */ +} TEMPMON_Type, *TEMPMON_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- TEMPMON - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros + * @{ + */ + + +/* TEMPMON - Register accessors */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_REG(base) ((base)->HW_ANADIG_TEMPSENSE0) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_TOG) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_REG(base) ((base)->HW_ANADIG_TEMPSENSE1) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_TOG) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_TOG) + +/*! + * @} + */ /* end of group TEMPMON_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/* HW_ANADIG_TEMPSENSE0 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK) +/* HW_ANADIG_TEMPSENSE1 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16 +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK) +/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x30360000u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +#define TEMPMON_BASE_PTR (TEMPMON) +/** Array initializer of TEMPMON peripheral base adresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } + +/* ---------------------------------------------------------------------------- + -- TEMPMON - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Accessor_Macros TEMPMON - Register accessor macros + * @{ + */ + + +/* TEMPMON - Register instance definitions */ +/* TEMPMON */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0 TEMPMON_HW_ANADIG_TEMPSENSE0_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET TEMPMON_HW_ANADIG_TEMPSENSE0_SET_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE1 TEMPMON_HW_ANADIG_TEMPSENSE1_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET TEMPMON_HW_ANADIG_TEMPSENSE1_SET_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(TEMPMON_BASE_PTR) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(TEMPMON_BASE_PTR) + +/*! + * @} + */ /* end of group TEMPMON_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group TEMPMON_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ + uint8_t RESERVED_1[60]; + __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ + __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ + __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ + __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ + __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ + __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ + __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ + __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ + __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ + __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ + __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ + __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ + __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ + __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ + __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ +} UART_Type, *UART_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- UART - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros + * @{ + */ + + +/* UART - Register accessors */ +#define UART_URXD_REG(base) ((base)->URXD) +#define UART_UTXD_REG(base) ((base)->UTXD) +#define UART_UCR1_REG(base) ((base)->UCR1) +#define UART_UCR2_REG(base) ((base)->UCR2) +#define UART_UCR3_REG(base) ((base)->UCR3) +#define UART_UCR4_REG(base) ((base)->UCR4) +#define UART_UFCR_REG(base) ((base)->UFCR) +#define UART_USR1_REG(base) ((base)->USR1) +#define UART_USR2_REG(base) ((base)->USR2) +#define UART_UESC_REG(base) ((base)->UESC) +#define UART_UTIM_REG(base) ((base)->UTIM) +#define UART_UBIR_REG(base) ((base)->UBIR) +#define UART_UBMR_REG(base) ((base)->UBMR) +#define UART_UBRC_REG(base) ((base)->UBRC) +#define UART_ONEMS_REG(base) ((base)->ONEMS) +#define UART_UTS_REG(base) ((base)->UTS) +#define UART_UMCR_REG(base) ((base)->UMCR) + +/*! + * @} + */ /* end of group UART_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* URXD Bit Fields */ +#define UART_URXD_RX_DATA_MASK 0xFFu +#define UART_URXD_RX_DATA_SHIFT 0 +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<<UART_URXD_RX_DATA_SHIFT))&UART_URXD_RX_DATA_MASK) +#define UART_URXD_PRERR_MASK 0x400u +#define UART_URXD_PRERR_SHIFT 10 +#define UART_URXD_BRK_MASK 0x800u +#define UART_URXD_BRK_SHIFT 11 +#define UART_URXD_FRMERR_MASK 0x1000u +#define UART_URXD_FRMERR_SHIFT 12 +#define UART_URXD_OVRRUN_MASK 0x2000u +#define UART_URXD_OVRRUN_SHIFT 13 +#define UART_URXD_ERR_MASK 0x4000u +#define UART_URXD_ERR_SHIFT 14 +#define UART_URXD_CHARRDY_MASK 0x8000u +#define UART_URXD_CHARRDY_SHIFT 15 +/* UTXD Bit Fields */ +#define UART_UTXD_TX_DATA_MASK 0xFFu +#define UART_UTXD_TX_DATA_SHIFT 0 +#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x))<<UART_UTXD_TX_DATA_SHIFT))&UART_UTXD_TX_DATA_MASK) +/* UCR1 Bit Fields */ +#define UART_UCR1_UARTEN_MASK 0x1u +#define UART_UCR1_UARTEN_SHIFT 0 +#define UART_UCR1_DOZE_MASK 0x2u +#define UART_UCR1_DOZE_SHIFT 1 +#define UART_UCR1_ATDMAEN_MASK 0x4u +#define UART_UCR1_ATDMAEN_SHIFT 2 +#define UART_UCR1_TXDMAEN_MASK 0x8u +#define UART_UCR1_TXDMAEN_SHIFT 3 +#define UART_UCR1_SNDBRK_MASK 0x10u +#define UART_UCR1_SNDBRK_SHIFT 4 +#define UART_UCR1_RTSDEN_MASK 0x20u +#define UART_UCR1_RTSDEN_SHIFT 5 +#define UART_UCR1_TXMPTYEN_MASK 0x40u +#define UART_UCR1_TXMPTYEN_SHIFT 6 +#define UART_UCR1_IREN_MASK 0x80u +#define UART_UCR1_IREN_SHIFT 7 +#define UART_UCR1_RXDMAEN_MASK 0x100u +#define UART_UCR1_RXDMAEN_SHIFT 8 +#define UART_UCR1_RRDYEN_MASK 0x200u +#define UART_UCR1_RRDYEN_SHIFT 9 +#define UART_UCR1_ICD_MASK 0xC00u +#define UART_UCR1_ICD_SHIFT 10 +#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR1_ICD_SHIFT))&UART_UCR1_ICD_MASK) +#define UART_UCR1_IDEN_MASK 0x1000u +#define UART_UCR1_IDEN_SHIFT 12 +#define UART_UCR1_TRDYEN_MASK 0x2000u +#define UART_UCR1_TRDYEN_SHIFT 13 +#define UART_UCR1_ADBR_MASK 0x4000u +#define UART_UCR1_ADBR_SHIFT 14 +#define UART_UCR1_ADEN_MASK 0x8000u +#define UART_UCR1_ADEN_SHIFT 15 +/* UCR2 Bit Fields */ +#define UART_UCR2_SRST_MASK 0x1u +#define UART_UCR2_SRST_SHIFT 0 +#define UART_UCR2_RXEN_MASK 0x2u +#define UART_UCR2_RXEN_SHIFT 1 +#define UART_UCR2_TXEN_MASK 0x4u +#define UART_UCR2_TXEN_SHIFT 2 +#define UART_UCR2_ATEN_MASK 0x8u +#define UART_UCR2_ATEN_SHIFT 3 +#define UART_UCR2_RTSEN_MASK 0x10u +#define UART_UCR2_RTSEN_SHIFT 4 +#define UART_UCR2_WS_MASK 0x20u +#define UART_UCR2_WS_SHIFT 5 +#define UART_UCR2_STPB_MASK 0x40u +#define UART_UCR2_STPB_SHIFT 6 +#define UART_UCR2_PROE_MASK 0x80u +#define UART_UCR2_PROE_SHIFT 7 +#define UART_UCR2_PREN_MASK 0x100u +#define UART_UCR2_PREN_SHIFT 8 +#define UART_UCR2_RTEC_MASK 0x600u +#define UART_UCR2_RTEC_SHIFT 9 +#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR2_RTEC_SHIFT))&UART_UCR2_RTEC_MASK) +#define UART_UCR2_ESCEN_MASK 0x800u +#define UART_UCR2_ESCEN_SHIFT 11 +#define UART_UCR2_CTS_MASK 0x1000u +#define UART_UCR2_CTS_SHIFT 12 +#define UART_UCR2_CTSC_MASK 0x2000u +#define UART_UCR2_CTSC_SHIFT 13 +#define UART_UCR2_IRTS_MASK 0x4000u +#define UART_UCR2_IRTS_SHIFT 14 +#define UART_UCR2_ESCI_MASK 0x8000u +#define UART_UCR2_ESCI_SHIFT 15 +/* UCR3 Bit Fields */ +#define UART_UCR3_ACIEN_MASK 0x1u +#define UART_UCR3_ACIEN_SHIFT 0 +#define UART_UCR3_INVT_MASK 0x2u +#define UART_UCR3_INVT_SHIFT 1 +#define UART_UCR3_RXDMUXSEL_MASK 0x4u +#define UART_UCR3_RXDMUXSEL_SHIFT 2 +#define UART_UCR3_DTRDEN_MASK 0x8u +#define UART_UCR3_DTRDEN_SHIFT 3 +#define UART_UCR3_AWAKEN_MASK 0x10u +#define UART_UCR3_AWAKEN_SHIFT 4 +#define UART_UCR3_AIRINTEN_MASK 0x20u +#define UART_UCR3_AIRINTEN_SHIFT 5 +#define UART_UCR3_RXDSEN_MASK 0x40u +#define UART_UCR3_RXDSEN_SHIFT 6 +#define UART_UCR3_ADNIMP_MASK 0x80u +#define UART_UCR3_ADNIMP_SHIFT 7 +#define UART_UCR3_RI_MASK 0x100u +#define UART_UCR3_RI_SHIFT 8 +#define UART_UCR3_DCD_MASK 0x200u +#define UART_UCR3_DCD_SHIFT 9 +#define UART_UCR3_DSR_MASK 0x400u +#define UART_UCR3_DSR_SHIFT 10 +#define UART_UCR3_FRAERREN_MASK 0x800u +#define UART_UCR3_FRAERREN_SHIFT 11 +#define UART_UCR3_PARERREN_MASK 0x1000u +#define UART_UCR3_PARERREN_SHIFT 12 +#define UART_UCR3_DTREN_MASK 0x2000u +#define UART_UCR3_DTREN_SHIFT 13 +#define UART_UCR3_DPEC_MASK 0xC000u +#define UART_UCR3_DPEC_SHIFT 14 +#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR3_DPEC_SHIFT))&UART_UCR3_DPEC_MASK) +/* UCR4 Bit Fields */ +#define UART_UCR4_DREN_MASK 0x1u +#define UART_UCR4_DREN_SHIFT 0 +#define UART_UCR4_OREN_MASK 0x2u +#define UART_UCR4_OREN_SHIFT 1 +#define UART_UCR4_BKEN_MASK 0x4u +#define UART_UCR4_BKEN_SHIFT 2 +#define UART_UCR4_TCEN_MASK 0x8u +#define UART_UCR4_TCEN_SHIFT 3 +#define UART_UCR4_LPBYP_MASK 0x10u +#define UART_UCR4_LPBYP_SHIFT 4 +#define UART_UCR4_IRSC_MASK 0x20u +#define UART_UCR4_IRSC_SHIFT 5 +#define UART_UCR4_IDDMAEN_MASK 0x40u +#define UART_UCR4_IDDMAEN_SHIFT 6 +#define UART_UCR4_WKEN_MASK 0x80u +#define UART_UCR4_WKEN_SHIFT 7 +#define UART_UCR4_ENIRI_MASK 0x100u +#define UART_UCR4_ENIRI_SHIFT 8 +#define UART_UCR4_INVR_MASK 0x200u +#define UART_UCR4_INVR_SHIFT 9 +#define UART_UCR4_CTSTL_MASK 0xFC00u +#define UART_UCR4_CTSTL_SHIFT 10 +#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x))<<UART_UCR4_CTSTL_SHIFT))&UART_UCR4_CTSTL_MASK) +/* UFCR Bit Fields */ +#define UART_UFCR_RXTL_MASK 0x3Fu +#define UART_UFCR_RXTL_SHIFT 0 +#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RXTL_SHIFT))&UART_UFCR_RXTL_MASK) +#define UART_UFCR_DCEDTE_MASK 0x40u +#define UART_UFCR_DCEDTE_SHIFT 6 +#define UART_UFCR_RFDIV_MASK 0x380u +#define UART_UFCR_RFDIV_SHIFT 7 +#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x))<<UART_UFCR_RFDIV_SHIFT))&UART_UFCR_RFDIV_MASK) +#define UART_UFCR_TXTL_MASK 0xFC00u +#define UART_UFCR_TXTL_SHIFT 10 +#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x))<<UART_UFCR_TXTL_SHIFT))&UART_UFCR_TXTL_MASK) +/* USR1 Bit Fields */ +#define UART_USR1_SAD_MASK 0x8u +#define UART_USR1_SAD_SHIFT 3 +#define UART_USR1_AWAKE_MASK 0x10u +#define UART_USR1_AWAKE_SHIFT 4 +#define UART_USR1_AIRINT_MASK 0x20u +#define UART_USR1_AIRINT_SHIFT 5 +#define UART_USR1_RXDS_MASK 0x40u +#define UART_USR1_RXDS_SHIFT 6 +#define UART_USR1_DTRD_MASK 0x80u +#define UART_USR1_DTRD_SHIFT 7 +#define UART_USR1_AGTIM_MASK 0x100u +#define UART_USR1_AGTIM_SHIFT 8 +#define UART_USR1_RRDY_MASK 0x200u +#define UART_USR1_RRDY_SHIFT 9 +#define UART_USR1_FRAMERR_MASK 0x400u +#define UART_USR1_FRAMERR_SHIFT 10 +#define UART_USR1_ESCF_MASK 0x800u +#define UART_USR1_ESCF_SHIFT 11 +#define UART_USR1_RTSD_MASK 0x1000u +#define UART_USR1_RTSD_SHIFT 12 +#define UART_USR1_TRDY_MASK 0x2000u +#define UART_USR1_TRDY_SHIFT 13 +#define UART_USR1_RTSS_MASK 0x4000u +#define UART_USR1_RTSS_SHIFT 14 +#define UART_USR1_PARITYERR_MASK 0x8000u +#define UART_USR1_PARITYERR_SHIFT 15 +/* USR2 Bit Fields */ +#define UART_USR2_RDR_MASK 0x1u +#define UART_USR2_RDR_SHIFT 0 +#define UART_USR2_ORE_MASK 0x2u +#define UART_USR2_ORE_SHIFT 1 +#define UART_USR2_BRCD_MASK 0x4u +#define UART_USR2_BRCD_SHIFT 2 +#define UART_USR2_TXDC_MASK 0x8u +#define UART_USR2_TXDC_SHIFT 3 +#define UART_USR2_RTSF_MASK 0x10u +#define UART_USR2_RTSF_SHIFT 4 +#define UART_USR2_DCDIN_MASK 0x20u +#define UART_USR2_DCDIN_SHIFT 5 +#define UART_USR2_DCDDELT_MASK 0x40u +#define UART_USR2_DCDDELT_SHIFT 6 +#define UART_USR2_WAKE_MASK 0x80u +#define UART_USR2_WAKE_SHIFT 7 +#define UART_USR2_IRINT_MASK 0x100u +#define UART_USR2_IRINT_SHIFT 8 +#define UART_USR2_RIIN_MASK 0x200u +#define UART_USR2_RIIN_SHIFT 9 +#define UART_USR2_RIDELT_MASK 0x400u +#define UART_USR2_RIDELT_SHIFT 10 +#define UART_USR2_ACST_MASK 0x800u +#define UART_USR2_ACST_SHIFT 11 +#define UART_USR2_IDLE_MASK 0x1000u +#define UART_USR2_IDLE_SHIFT 12 +#define UART_USR2_DTRF_MASK 0x2000u +#define UART_USR2_DTRF_SHIFT 13 +#define UART_USR2_TXFE_MASK 0x4000u +#define UART_USR2_TXFE_SHIFT 14 +#define UART_USR2_ADET_MASK 0x8000u +#define UART_USR2_ADET_SHIFT 15 +/* UESC Bit Fields */ +#define UART_UESC_ESC_CHAR_MASK 0xFFu +#define UART_UESC_ESC_CHAR_SHIFT 0 +#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x))<<UART_UESC_ESC_CHAR_SHIFT))&UART_UESC_ESC_CHAR_MASK) +/* UTIM Bit Fields */ +#define UART_UTIM_TIM_MASK 0xFFFu +#define UART_UTIM_TIM_SHIFT 0 +#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x))<<UART_UTIM_TIM_SHIFT))&UART_UTIM_TIM_MASK) +/* UBIR Bit Fields */ +#define UART_UBIR_INC_MASK 0xFFFFu +#define UART_UBIR_INC_SHIFT 0 +#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x))<<UART_UBIR_INC_SHIFT))&UART_UBIR_INC_MASK) +/* UBMR Bit Fields */ +#define UART_UBMR_MOD_MASK 0xFFFFu +#define UART_UBMR_MOD_SHIFT 0 +#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x))<<UART_UBMR_MOD_SHIFT))&UART_UBMR_MOD_MASK) +/* UBRC Bit Fields */ +#define UART_UBRC_BCNT_MASK 0xFFFFu +#define UART_UBRC_BCNT_SHIFT 0 +#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x))<<UART_UBRC_BCNT_SHIFT))&UART_UBRC_BCNT_MASK) +/* ONEMS Bit Fields */ +#define UART_ONEMS_ONEMS_MASK 0xFFFFFFu +#define UART_ONEMS_ONEMS_SHIFT 0 +#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x))<<UART_ONEMS_ONEMS_SHIFT))&UART_ONEMS_ONEMS_MASK) +/* UTS Bit Fields */ +#define UART_UTS_SOFTRST_MASK 0x1u +#define UART_UTS_SOFTRST_SHIFT 0 +#define UART_UTS_RXFULL_MASK 0x8u +#define UART_UTS_RXFULL_SHIFT 3 +#define UART_UTS_TXFULL_MASK 0x10u +#define UART_UTS_TXFULL_SHIFT 4 +#define UART_UTS_RXEMPTY_MASK 0x20u +#define UART_UTS_RXEMPTY_SHIFT 5 +#define UART_UTS_TXEMPTY_MASK 0x40u +#define UART_UTS_TXEMPTY_SHIFT 6 +#define UART_UTS_RXDBG_MASK 0x200u +#define UART_UTS_RXDBG_SHIFT 9 +#define UART_UTS_LOOPIR_MASK 0x400u +#define UART_UTS_LOOPIR_SHIFT 10 +#define UART_UTS_DBGEN_MASK 0x800u +#define UART_UTS_DBGEN_SHIFT 11 +#define UART_UTS_LOOP_MASK 0x1000u +#define UART_UTS_LOOP_SHIFT 12 +#define UART_UTS_FRCPERR_MASK 0x2000u +#define UART_UTS_FRCPERR_SHIFT 13 +/* UMCR Bit Fields */ +#define UART_UMCR_MDEN_MASK 0x1u +#define UART_UMCR_MDEN_SHIFT 0 +#define UART_UMCR_SLAM_MASK 0x2u +#define UART_UMCR_SLAM_SHIFT 1 +#define UART_UMCR_TXB8_MASK 0x4u +#define UART_UMCR_TXB8_SHIFT 2 +#define UART_UMCR_SADEN_MASK 0x8u +#define UART_UMCR_SADEN_SHIFT 3 +#define UART_UMCR_SLADDR_MASK 0xFF00u +#define UART_UMCR_SLADDR_SHIFT 8 +#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x))<<UART_UMCR_SLADDR_SHIFT))&UART_UMCR_SLADDR_MASK) + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART1 base address */ +#define UART1_BASE (0x30860000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +#define UART1_BASE_PTR (UART1) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x30890000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +#define UART2_BASE_PTR (UART2) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x30880000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +#define UART3_BASE_PTR (UART3) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x30A60000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +#define UART4_BASE_PTR (UART4) +/** Peripheral UART5 base address */ +#define UART5_BASE (0x30A70000u) +/** Peripheral UART5 base pointer */ +#define UART5 ((UART_Type *)UART5_BASE) +#define UART5_BASE_PTR (UART5) +/** Peripheral UART6 base address */ +#define UART6_BASE (0x30A80000u) +/** Peripheral UART6 base pointer */ +#define UART6 ((UART_Type *)UART6_BASE) +#define UART6_BASE_PTR (UART6) +/** Peripheral UART7 base address */ +#define UART7_BASE (0x30A90000u) +/** Peripheral UART7 base pointer */ +#define UART7 ((UART_Type *)UART7_BASE) +#define UART7_BASE_PTR (UART7) +/** Array initializer of UART peripheral base adresses */ +#define UART_BASE_ADDRS { UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { UART1, UART2, UART3, UART4, UART5, UART6, UART7 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_IRQS { UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn } +/* ---------------------------------------------------------------------------- + -- UART - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros + * @{ + */ + + +/* UART - Register instance definitions */ +/* UART1 */ +#define UART1_URXD UART_URXD_REG(UART1_BASE_PTR) +#define UART1_UTXD UART_UTXD_REG(UART1_BASE_PTR) +#define UART1_UCR1 UART_UCR1_REG(UART1_BASE_PTR) +#define UART1_UCR2 UART_UCR2_REG(UART1_BASE_PTR) +#define UART1_UCR3 UART_UCR3_REG(UART1_BASE_PTR) +#define UART1_UCR4 UART_UCR4_REG(UART1_BASE_PTR) +#define UART1_UFCR UART_UFCR_REG(UART1_BASE_PTR) +#define UART1_USR1 UART_USR1_REG(UART1_BASE_PTR) +#define UART1_USR2 UART_USR2_REG(UART1_BASE_PTR) +#define UART1_UESC UART_UESC_REG(UART1_BASE_PTR) +#define UART1_UTIM UART_UTIM_REG(UART1_BASE_PTR) +#define UART1_UBIR UART_UBIR_REG(UART1_BASE_PTR) +#define UART1_UBMR UART_UBMR_REG(UART1_BASE_PTR) +#define UART1_UBRC UART_UBRC_REG(UART1_BASE_PTR) +#define UART1_ONEMS UART_ONEMS_REG(UART1_BASE_PTR) +#define UART1_UTS UART_UTS_REG(UART1_BASE_PTR) +#define UART1_UMCR UART_UMCR_REG(UART1_BASE_PTR) +/* UART2 */ +#define UART2_URXD UART_URXD_REG(UART2_BASE_PTR) +#define UART2_UTXD UART_UTXD_REG(UART2_BASE_PTR) +#define UART2_UCR1 UART_UCR1_REG(UART2_BASE_PTR) +#define UART2_UCR2 UART_UCR2_REG(UART2_BASE_PTR) +#define UART2_UCR3 UART_UCR3_REG(UART2_BASE_PTR) +#define UART2_UCR4 UART_UCR4_REG(UART2_BASE_PTR) +#define UART2_UFCR UART_UFCR_REG(UART2_BASE_PTR) +#define UART2_USR1 UART_USR1_REG(UART2_BASE_PTR) +#define UART2_USR2 UART_USR2_REG(UART2_BASE_PTR) +#define UART2_UESC UART_UESC_REG(UART2_BASE_PTR) +#define UART2_UTIM UART_UTIM_REG(UART2_BASE_PTR) +#define UART2_UBIR UART_UBIR_REG(UART2_BASE_PTR) +#define UART2_UBMR UART_UBMR_REG(UART2_BASE_PTR) +#define UART2_UBRC UART_UBRC_REG(UART2_BASE_PTR) +#define UART2_ONEMS UART_ONEMS_REG(UART2_BASE_PTR) +#define UART2_UTS UART_UTS_REG(UART2_BASE_PTR) +#define UART2_UMCR UART_UMCR_REG(UART2_BASE_PTR) +/* UART3 */ +#define UART3_URXD UART_URXD_REG(UART3_BASE_PTR) +#define UART3_UTXD UART_UTXD_REG(UART3_BASE_PTR) +#define UART3_UCR1 UART_UCR1_REG(UART3_BASE_PTR) +#define UART3_UCR2 UART_UCR2_REG(UART3_BASE_PTR) +#define UART3_UCR3 UART_UCR3_REG(UART3_BASE_PTR) +#define UART3_UCR4 UART_UCR4_REG(UART3_BASE_PTR) +#define UART3_UFCR UART_UFCR_REG(UART3_BASE_PTR) +#define UART3_USR1 UART_USR1_REG(UART3_BASE_PTR) +#define UART3_USR2 UART_USR2_REG(UART3_BASE_PTR) +#define UART3_UESC UART_UESC_REG(UART3_BASE_PTR) +#define UART3_UTIM UART_UTIM_REG(UART3_BASE_PTR) +#define UART3_UBIR UART_UBIR_REG(UART3_BASE_PTR) +#define UART3_UBMR UART_UBMR_REG(UART3_BASE_PTR) +#define UART3_UBRC UART_UBRC_REG(UART3_BASE_PTR) +#define UART3_ONEMS UART_ONEMS_REG(UART3_BASE_PTR) +#define UART3_UTS UART_UTS_REG(UART3_BASE_PTR) +#define UART3_UMCR UART_UMCR_REG(UART3_BASE_PTR) +/* UART4 */ +#define UART4_URXD UART_URXD_REG(UART4_BASE_PTR) +#define UART4_UTXD UART_UTXD_REG(UART4_BASE_PTR) +#define UART4_UCR1 UART_UCR1_REG(UART4_BASE_PTR) +#define UART4_UCR2 UART_UCR2_REG(UART4_BASE_PTR) +#define UART4_UCR3 UART_UCR3_REG(UART4_BASE_PTR) +#define UART4_UCR4 UART_UCR4_REG(UART4_BASE_PTR) +#define UART4_UFCR UART_UFCR_REG(UART4_BASE_PTR) +#define UART4_USR1 UART_USR1_REG(UART4_BASE_PTR) +#define UART4_USR2 UART_USR2_REG(UART4_BASE_PTR) +#define UART4_UESC UART_UESC_REG(UART4_BASE_PTR) +#define UART4_UTIM UART_UTIM_REG(UART4_BASE_PTR) +#define UART4_UBIR UART_UBIR_REG(UART4_BASE_PTR) +#define UART4_UBMR UART_UBMR_REG(UART4_BASE_PTR) +#define UART4_UBRC UART_UBRC_REG(UART4_BASE_PTR) +#define UART4_ONEMS UART_ONEMS_REG(UART4_BASE_PTR) +#define UART4_UTS UART_UTS_REG(UART4_BASE_PTR) +#define UART4_UMCR UART_UMCR_REG(UART4_BASE_PTR) +/* UART5 */ +#define UART5_URXD UART_URXD_REG(UART5_BASE_PTR) +#define UART5_UTXD UART_UTXD_REG(UART5_BASE_PTR) +#define UART5_UCR1 UART_UCR1_REG(UART5_BASE_PTR) +#define UART5_UCR2 UART_UCR2_REG(UART5_BASE_PTR) +#define UART5_UCR3 UART_UCR3_REG(UART5_BASE_PTR) +#define UART5_UCR4 UART_UCR4_REG(UART5_BASE_PTR) +#define UART5_UFCR UART_UFCR_REG(UART5_BASE_PTR) +#define UART5_USR1 UART_USR1_REG(UART5_BASE_PTR) +#define UART5_USR2 UART_USR2_REG(UART5_BASE_PTR) +#define UART5_UESC UART_UESC_REG(UART5_BASE_PTR) +#define UART5_UTIM UART_UTIM_REG(UART5_BASE_PTR) +#define UART5_UBIR UART_UBIR_REG(UART5_BASE_PTR) +#define UART5_UBMR UART_UBMR_REG(UART5_BASE_PTR) +#define UART5_UBRC UART_UBRC_REG(UART5_BASE_PTR) +#define UART5_ONEMS UART_ONEMS_REG(UART5_BASE_PTR) +#define UART5_UTS UART_UTS_REG(UART5_BASE_PTR) +#define UART5_UMCR UART_UMCR_REG(UART5_BASE_PTR) +/* UART6 */ +#define UART6_URXD UART_URXD_REG(UART6_BASE_PTR) +#define UART6_UTXD UART_UTXD_REG(UART6_BASE_PTR) +#define UART6_UCR1 UART_UCR1_REG(UART6_BASE_PTR) +#define UART6_UCR2 UART_UCR2_REG(UART6_BASE_PTR) +#define UART6_UCR3 UART_UCR3_REG(UART6_BASE_PTR) +#define UART6_UCR4 UART_UCR4_REG(UART6_BASE_PTR) +#define UART6_UFCR UART_UFCR_REG(UART6_BASE_PTR) +#define UART6_USR1 UART_USR1_REG(UART6_BASE_PTR) +#define UART6_USR2 UART_USR2_REG(UART6_BASE_PTR) +#define UART6_UESC UART_UESC_REG(UART6_BASE_PTR) +#define UART6_UTIM UART_UTIM_REG(UART6_BASE_PTR) +#define UART6_UBIR UART_UBIR_REG(UART6_BASE_PTR) +#define UART6_UBMR UART_UBMR_REG(UART6_BASE_PTR) +#define UART6_UBRC UART_UBRC_REG(UART6_BASE_PTR) +#define UART6_ONEMS UART_ONEMS_REG(UART6_BASE_PTR) +#define UART6_UTS UART_UTS_REG(UART6_BASE_PTR) +#define UART6_UMCR UART_UMCR_REG(UART6_BASE_PTR) + +/*! + * @} + */ /* end of group UART_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group UART_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __IO uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL1; /**< Endpoint Control 1, offset: 0x1C4 */ + __IO uint32_t ENDPTCTRL2; /**< Endpoint Control 2, offset: 0x1C8 */ + __IO uint32_t ENDPTCTRL3; /**< Endpoint Control 3, offset: 0x1CC */ + __IO uint32_t ENDPTCTRL4; /**< Endpoint Control 4, offset: 0x1D0 */ + __IO uint32_t ENDPTCTRL5; /**< Endpoint Control 5, offset: 0x1D4 */ + __IO uint32_t ENDPTCTRL6; /**< Endpoint Control 6, offset: 0x1D8 */ + __IO uint32_t ENDPTCTRL7; /**< Endpoint Control 7, offset: 0x1DC */ +} USB_Type, *USB_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- USB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros + * @{ + */ + + +/* USB - Register accessors */ +#define USB_ID_REG(base) ((base)->ID) +#define USB_HWGENERAL_REG(base) ((base)->HWGENERAL) +#define USB_HWHOST_REG(base) ((base)->HWHOST) +#define USB_HWDEVICE_REG(base) ((base)->HWDEVICE) +#define USB_HWTXBUF_REG(base) ((base)->HWTXBUF) +#define USB_HWRXBUF_REG(base) ((base)->HWRXBUF) +#define USB_GPTIMER0LD_REG(base) ((base)->GPTIMER0LD) +#define USB_GPTIMER0CTRL_REG(base) ((base)->GPTIMER0CTRL) +#define USB_GPTIMER1LD_REG(base) ((base)->GPTIMER1LD) +#define USB_GPTIMER1CTRL_REG(base) ((base)->GPTIMER1CTRL) +#define USB_SBUSCFG_REG(base) ((base)->SBUSCFG) +#define USB_CAPLENGTH_REG(base) ((base)->CAPLENGTH) +#define USB_HCIVERSION_REG(base) ((base)->HCIVERSION) +#define USB_HCSPARAMS_REG(base) ((base)->HCSPARAMS) +#define USB_HCCPARAMS_REG(base) ((base)->HCCPARAMS) +#define USB_DCIVERSION_REG(base) ((base)->DCIVERSION) +#define USB_DCCPARAMS_REG(base) ((base)->DCCPARAMS) +#define USB_USBCMD_REG(base) ((base)->USBCMD) +#define USB_USBSTS_REG(base) ((base)->USBSTS) +#define USB_USBINTR_REG(base) ((base)->USBINTR) +#define USB_FRINDEX_REG(base) ((base)->FRINDEX) +#define USB_DEVICEADDR_REG(base) ((base)->DEVICEADDR) +#define USB_PERIODICLISTBASE_REG(base) ((base)->PERIODICLISTBASE) +#define USB_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR) +#define USB_ENDPTLISTADDR_REG(base) ((base)->ENDPTLISTADDR) +#define USB_BURSTSIZE_REG(base) ((base)->BURSTSIZE) +#define USB_TXFILLTUNING_REG(base) ((base)->TXFILLTUNING) +#define USB_ENDPTNAK_REG(base) ((base)->ENDPTNAK) +#define USB_ENDPTNAKEN_REG(base) ((base)->ENDPTNAKEN) +#define USB_CONFIGFLAG_REG(base) ((base)->CONFIGFLAG) +#define USB_PORTSC1_REG(base) ((base)->PORTSC1) +#define USB_OTGSC_REG(base) ((base)->OTGSC) +#define USB_USBMODE_REG(base) ((base)->USBMODE) +#define USB_ENDPTSETUPSTAT_REG(base) ((base)->ENDPTSETUPSTAT) +#define USB_ENDPTPRIME_REG(base) ((base)->ENDPTPRIME) +#define USB_ENDPTFLUSH_REG(base) ((base)->ENDPTFLUSH) +#define USB_ENDPTSTAT_REG(base) ((base)->ENDPTSTAT) +#define USB_ENDPTCOMPLETE_REG(base) ((base)->ENDPTCOMPLETE) +#define USB_ENDPTCTRL0_REG(base) ((base)->ENDPTCTRL0) +#define USB_ENDPTCTRL1_REG(base) ((base)->ENDPTCTRL1) +#define USB_ENDPTCTRL2_REG(base) ((base)->ENDPTCTRL2) +#define USB_ENDPTCTRL3_REG(base) ((base)->ENDPTCTRL3) +#define USB_ENDPTCTRL4_REG(base) ((base)->ENDPTCTRL4) +#define USB_ENDPTCTRL5_REG(base) ((base)->ENDPTCTRL5) +#define USB_ENDPTCTRL6_REG(base) ((base)->ENDPTCTRL6) +#define USB_ENDPTCTRL7_REG(base) ((base)->ENDPTCTRL7) + +/*! + * @} + */ /* end of group USB_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* ID Bit Fields */ +#define USB_ID_ID_MASK 0x3Fu +#define USB_ID_ID_SHIFT 0 +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<USB_ID_ID_SHIFT))&USB_ID_ID_MASK) +#define USB_ID_NID_MASK 0x3F00u +#define USB_ID_NID_SHIFT 8 +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x))<<USB_ID_NID_SHIFT))&USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK 0xFF0000u +#define USB_ID_REVISION_SHIFT 16 +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<USB_ID_REVISION_SHIFT))&USB_ID_REVISION_MASK) +/* HWGENERAL Bit Fields */ +#define USB_HWGENERAL_PHYW_MASK 0x30u +#define USB_HWGENERAL_PHYW_SHIFT 4 +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_PHYW_SHIFT))&USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK 0x1C0u +#define USB_HWGENERAL_PHYM_SHIFT 6 +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_PHYM_SHIFT))&USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK 0x600u +#define USB_HWGENERAL_SM_SHIFT 9 +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x))<<USB_HWGENERAL_SM_SHIFT))&USB_HWGENERAL_SM_MASK) +/* HWHOST Bit Fields */ +#define USB_HWHOST_HC_MASK 0x1u +#define USB_HWHOST_HC_SHIFT 0 +#define USB_HWHOST_NPORT_MASK 0xEu +#define USB_HWHOST_NPORT_SHIFT 1 +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x))<<USB_HWHOST_NPORT_SHIFT))&USB_HWHOST_NPORT_MASK) +/* HWDEVICE Bit Fields */ +#define USB_HWDEVICE_DC_MASK 0x1u +#define USB_HWDEVICE_DC_SHIFT 0 +#define USB_HWDEVICE_DEVEP_MASK 0x3Eu +#define USB_HWDEVICE_DEVEP_SHIFT 1 +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x))<<USB_HWDEVICE_DEVEP_SHIFT))&USB_HWDEVICE_DEVEP_MASK) +/* HWTXBUF Bit Fields */ +#define USB_HWTXBUF_TXBURST_MASK 0xFFu +#define USB_HWTXBUF_TXBURST_SHIFT 0 +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x))<<USB_HWTXBUF_TXBURST_SHIFT))&USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK 0xFF0000u +#define USB_HWTXBUF_TXCHANADD_SHIFT 16 +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x))<<USB_HWTXBUF_TXCHANADD_SHIFT))&USB_HWTXBUF_TXCHANADD_MASK) +/* HWRXBUF Bit Fields */ +#define USB_HWRXBUF_RXBURST_MASK 0xFFu +#define USB_HWRXBUF_RXBURST_SHIFT 0 +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x))<<USB_HWRXBUF_RXBURST_SHIFT))&USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK 0xFF00u +#define USB_HWRXBUF_RXADD_SHIFT 8 +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x))<<USB_HWRXBUF_RXADD_SHIFT))&USB_HWRXBUF_RXADD_MASK) +/* GPTIMER0LD Bit Fields */ +#define USB_GPTIMER0LD_GPTLD_MASK 0xFFFFFFu +#define USB_GPTIMER0LD_GPTLD_SHIFT 0 +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER0LD_GPTLD_SHIFT))&USB_GPTIMER0LD_GPTLD_MASK) +/* GPTIMER0CTRL Bit Fields */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK 0xFFFFFFu +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT 0 +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER0CTRL_GPTCNT_SHIFT))&USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK 0x1000000u +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT 24 +#define USB_GPTIMER0CTRL_GPTRST_MASK 0x40000000u +#define USB_GPTIMER0CTRL_GPTRST_SHIFT 30 +#define USB_GPTIMER0CTRL_GPTRUN_MASK 0x80000000u +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT 31 +/* GPTIMER1LD Bit Fields */ +#define USB_GPTIMER1LD_GPTLD_MASK 0xFFFFFFu +#define USB_GPTIMER1LD_GPTLD_SHIFT 0 +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER1LD_GPTLD_SHIFT))&USB_GPTIMER1LD_GPTLD_MASK) +/* GPTIMER1CTRL Bit Fields */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK 0xFFFFFFu +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT 0 +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x))<<USB_GPTIMER1CTRL_GPTCNT_SHIFT))&USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK 0x1000000u +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT 24 +#define USB_GPTIMER1CTRL_GPTRST_MASK 0x40000000u +#define USB_GPTIMER1CTRL_GPTRST_SHIFT 30 +#define USB_GPTIMER1CTRL_GPTRUN_MASK 0x80000000u +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT 31 +/* SBUSCFG Bit Fields */ +#define USB_SBUSCFG_AHBBRST_MASK 0x7u +#define USB_SBUSCFG_AHBBRST_SHIFT 0 +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x))<<USB_SBUSCFG_AHBBRST_SHIFT))&USB_SBUSCFG_AHBBRST_MASK) +/* CAPLENGTH Bit Fields */ +#define USB_CAPLENGTH_CAPLENGTH_MASK 0xFFu +#define USB_CAPLENGTH_CAPLENGTH_SHIFT 0 +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x))<<USB_CAPLENGTH_CAPLENGTH_SHIFT))&USB_CAPLENGTH_CAPLENGTH_MASK) +/* HCIVERSION Bit Fields */ +#define USB_HCIVERSION_HCIVERSION_MASK 0xFFFFu +#define USB_HCIVERSION_HCIVERSION_SHIFT 0 +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USB_HCIVERSION_HCIVERSION_SHIFT))&USB_HCIVERSION_HCIVERSION_MASK) +/* HCSPARAMS Bit Fields */ +#define USB_HCSPARAMS_N_PORTS_MASK 0xFu +#define USB_HCSPARAMS_N_PORTS_SHIFT 0 +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PORTS_SHIFT))&USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK 0x10u +#define USB_HCSPARAMS_PPC_SHIFT 4 +#define USB_HCSPARAMS_N_PCC_MASK 0xF00u +#define USB_HCSPARAMS_N_PCC_SHIFT 8 +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PCC_SHIFT))&USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK 0xF000u +#define USB_HCSPARAMS_N_CC_SHIFT 12 +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_CC_SHIFT))&USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK 0x10000u +#define USB_HCSPARAMS_PI_SHIFT 16 +#define USB_HCSPARAMS_N_PTT_MASK 0xF00000u +#define USB_HCSPARAMS_N_PTT_SHIFT 20 +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_PTT_SHIFT))&USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK 0xF000000u +#define USB_HCSPARAMS_N_TT_SHIFT 24 +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x))<<USB_HCSPARAMS_N_TT_SHIFT))&USB_HCSPARAMS_N_TT_MASK) +/* HCCPARAMS Bit Fields */ +#define USB_HCCPARAMS_ADC_MASK 0x1u +#define USB_HCCPARAMS_ADC_SHIFT 0 +#define USB_HCCPARAMS_PFL_MASK 0x2u +#define USB_HCCPARAMS_PFL_SHIFT 1 +#define USB_HCCPARAMS_ASP_MASK 0x4u +#define USB_HCCPARAMS_ASP_SHIFT 2 +#define USB_HCCPARAMS_IST_MASK 0xF0u +#define USB_HCCPARAMS_IST_SHIFT 4 +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x))<<USB_HCCPARAMS_IST_SHIFT))&USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK 0xFF00u +#define USB_HCCPARAMS_EECP_SHIFT 8 +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x))<<USB_HCCPARAMS_EECP_SHIFT))&USB_HCCPARAMS_EECP_MASK) +/* DCIVERSION Bit Fields */ +#define USB_DCIVERSION_DCIVERSION_MASK 0xFFFFu +#define USB_DCIVERSION_DCIVERSION_SHIFT 0 +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x))<<USB_DCIVERSION_DCIVERSION_SHIFT))&USB_DCIVERSION_DCIVERSION_MASK) +/* DCCPARAMS Bit Fields */ +#define USB_DCCPARAMS_DEN_MASK 0x1Fu +#define USB_DCCPARAMS_DEN_SHIFT 0 +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x))<<USB_DCCPARAMS_DEN_SHIFT))&USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK 0x80u +#define USB_DCCPARAMS_DC_SHIFT 7 +#define USB_DCCPARAMS_HC_MASK 0x100u +#define USB_DCCPARAMS_HC_SHIFT 8 +/* USBCMD Bit Fields */ +#define USB_USBCMD_RS_MASK 0x1u +#define USB_USBCMD_RS_SHIFT 0 +#define USB_USBCMD_RST_MASK 0x2u +#define USB_USBCMD_RST_SHIFT 1 +#define USB_USBCMD_FS_1_MASK 0xCu +#define USB_USBCMD_FS_1_SHIFT 2 +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_FS_1_SHIFT))&USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK 0x10u +#define USB_USBCMD_PSE_SHIFT 4 +#define USB_USBCMD_ASE_MASK 0x20u +#define USB_USBCMD_ASE_SHIFT 5 +#define USB_USBCMD_IAA_MASK 0x40u +#define USB_USBCMD_IAA_SHIFT 6 +#define USB_USBCMD_ASP_MASK 0x300u +#define USB_USBCMD_ASP_SHIFT 8 +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_ASP_SHIFT))&USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK 0x800u +#define USB_USBCMD_ASPE_SHIFT 11 +#define USB_USBCMD_SUTW_MASK 0x2000u +#define USB_USBCMD_SUTW_SHIFT 13 +#define USB_USBCMD_ATDTW_MASK 0x4000u +#define USB_USBCMD_ATDTW_SHIFT 14 +#define USB_USBCMD_FS_2_MASK 0x8000u +#define USB_USBCMD_FS_2_SHIFT 15 +#define USB_USBCMD_ITC_MASK 0xFF0000u +#define USB_USBCMD_ITC_SHIFT 16 +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x))<<USB_USBCMD_ITC_SHIFT))&USB_USBCMD_ITC_MASK) +/* USBSTS Bit Fields */ +#define USB_USBSTS_UI_MASK 0x1u +#define USB_USBSTS_UI_SHIFT 0 +#define USB_USBSTS_UEI_MASK 0x2u +#define USB_USBSTS_UEI_SHIFT 1 +#define USB_USBSTS_PCI_MASK 0x4u +#define USB_USBSTS_PCI_SHIFT 2 +#define USB_USBSTS_FRI_MASK 0x8u +#define USB_USBSTS_FRI_SHIFT 3 +#define USB_USBSTS_SEI_MASK 0x10u +#define USB_USBSTS_SEI_SHIFT 4 +#define USB_USBSTS_AAI_MASK 0x20u +#define USB_USBSTS_AAI_SHIFT 5 +#define USB_USBSTS_URI_MASK 0x40u +#define USB_USBSTS_URI_SHIFT 6 +#define USB_USBSTS_SRI_MASK 0x80u +#define USB_USBSTS_SRI_SHIFT 7 +#define USB_USBSTS_SLI_MASK 0x100u +#define USB_USBSTS_SLI_SHIFT 8 +#define USB_USBSTS_ULPII_MASK 0x400u +#define USB_USBSTS_ULPII_SHIFT 10 +#define USB_USBSTS_HCH_MASK 0x1000u +#define USB_USBSTS_HCH_SHIFT 12 +#define USB_USBSTS_RCL_MASK 0x2000u +#define USB_USBSTS_RCL_SHIFT 13 +#define USB_USBSTS_PS_MASK 0x4000u +#define USB_USBSTS_PS_SHIFT 14 +#define USB_USBSTS_AS_MASK 0x8000u +#define USB_USBSTS_AS_SHIFT 15 +#define USB_USBSTS_NAKI_MASK 0x10000u +#define USB_USBSTS_NAKI_SHIFT 16 +#define USB_USBSTS_TI0_MASK 0x1000000u +#define USB_USBSTS_TI0_SHIFT 24 +#define USB_USBSTS_TI1_MASK 0x2000000u +#define USB_USBSTS_TI1_SHIFT 25 +/* USBINTR Bit Fields */ +#define USB_USBINTR_UE_MASK 0x1u +#define USB_USBINTR_UE_SHIFT 0 +#define USB_USBINTR_UEE_MASK 0x2u +#define USB_USBINTR_UEE_SHIFT 1 +#define USB_USBINTR_PCE_MASK 0x4u +#define USB_USBINTR_PCE_SHIFT 2 +#define USB_USBINTR_FRE_MASK 0x8u +#define USB_USBINTR_FRE_SHIFT 3 +#define USB_USBINTR_SEE_MASK 0x10u +#define USB_USBINTR_SEE_SHIFT 4 +#define USB_USBINTR_AAE_MASK 0x20u +#define USB_USBINTR_AAE_SHIFT 5 +#define USB_USBINTR_URE_MASK 0x40u +#define USB_USBINTR_URE_SHIFT 6 +#define USB_USBINTR_SRE_MASK 0x80u +#define USB_USBINTR_SRE_SHIFT 7 +#define USB_USBINTR_SLE_MASK 0x100u +#define USB_USBINTR_SLE_SHIFT 8 +#define USB_USBINTR_ULPIE_MASK 0x400u +#define USB_USBINTR_ULPIE_SHIFT 10 +#define USB_USBINTR_NAKE_MASK 0x10000u +#define USB_USBINTR_NAKE_SHIFT 16 +#define USB_USBINTR_UAIE_MASK 0x40000u +#define USB_USBINTR_UAIE_SHIFT 18 +#define USB_USBINTR_UPIE_MASK 0x80000u +#define USB_USBINTR_UPIE_SHIFT 19 +#define USB_USBINTR_TIE0_MASK 0x1000000u +#define USB_USBINTR_TIE0_SHIFT 24 +#define USB_USBINTR_TIE1_MASK 0x2000000u +#define USB_USBINTR_TIE1_SHIFT 25 +/* FRINDEX Bit Fields */ +#define USB_FRINDEX_FRINDEX_MASK 0x3FFFu +#define USB_FRINDEX_FRINDEX_SHIFT 0 +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x))<<USB_FRINDEX_FRINDEX_SHIFT))&USB_FRINDEX_FRINDEX_MASK) +/* DEVICEADDR Bit Fields */ +#define USB_DEVICEADDR_USBADRA_MASK 0x1000000u +#define USB_DEVICEADDR_USBADRA_SHIFT 24 +#define USB_DEVICEADDR_USBADR_MASK 0xFE000000u +#define USB_DEVICEADDR_USBADR_SHIFT 25 +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x))<<USB_DEVICEADDR_USBADR_SHIFT))&USB_DEVICEADDR_USBADR_MASK) +/* PERIODICLISTBASE Bit Fields */ +#define USB_PERIODICLISTBASE_BASEADR_MASK 0xFFFFF000u +#define USB_PERIODICLISTBASE_BASEADR_SHIFT 12 +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x))<<USB_PERIODICLISTBASE_BASEADR_SHIFT))&USB_PERIODICLISTBASE_BASEADR_MASK) +/* ASYNCLISTADDR Bit Fields */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK 0xFFFFFFE0u +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT 5 +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x))<<USB_ASYNCLISTADDR_ASYBASE_SHIFT))&USB_ASYNCLISTADDR_ASYBASE_MASK) +/* ENDPTLISTADDR Bit Fields */ +#define USB_ENDPTLISTADDR_EPBASE_MASK 0xFFFFF800u +#define USB_ENDPTLISTADDR_EPBASE_SHIFT 11 +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTLISTADDR_EPBASE_SHIFT))&USB_ENDPTLISTADDR_EPBASE_MASK) +/* BURSTSIZE Bit Fields */ +#define USB_BURSTSIZE_RXPBURST_MASK 0xFFu +#define USB_BURSTSIZE_RXPBURST_SHIFT 0 +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USB_BURSTSIZE_RXPBURST_SHIFT))&USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK 0x1FF00u +#define USB_BURSTSIZE_TXPBURST_SHIFT 8 +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x))<<USB_BURSTSIZE_TXPBURST_SHIFT))&USB_BURSTSIZE_TXPBURST_MASK) +/* TXFILLTUNING Bit Fields */ +#define USB_TXFILLTUNING_TXSCHOH_MASK 0xFFu +#define USB_TXFILLTUNING_TXSCHOH_SHIFT 0 +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXSCHOH_SHIFT))&USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK 0x1F00u +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT 8 +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXSCHHEALTH_SHIFT))&USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK 0x3F0000u +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT 16 +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x))<<USB_TXFILLTUNING_TXFIFOTHRES_SHIFT))&USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/* ENDPTNAK Bit Fields */ +#define USB_ENDPTNAK_EPRN_MASK 0xFFu +#define USB_ENDPTNAK_EPRN_SHIFT 0 +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAK_EPRN_SHIFT))&USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK 0xFF0000u +#define USB_ENDPTNAK_EPTN_SHIFT 16 +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAK_EPTN_SHIFT))&USB_ENDPTNAK_EPTN_MASK) +/* ENDPTNAKEN Bit Fields */ +#define USB_ENDPTNAKEN_EPRNE_MASK 0xFFu +#define USB_ENDPTNAKEN_EPRNE_SHIFT 0 +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAKEN_EPRNE_SHIFT))&USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK 0xFF0000u +#define USB_ENDPTNAKEN_EPTNE_SHIFT 16 +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTNAKEN_EPTNE_SHIFT))&USB_ENDPTNAKEN_EPTNE_MASK) +/* CONFIGFLAG Bit Fields */ +#define USB_CONFIGFLAG_CF_MASK 0x1u +#define USB_CONFIGFLAG_CF_SHIFT 0 +/* PORTSC1 Bit Fields */ +#define USB_PORTSC1_CCS_MASK 0x1u +#define USB_PORTSC1_CCS_SHIFT 0 +#define USB_PORTSC1_CSC_MASK 0x2u +#define USB_PORTSC1_CSC_SHIFT 1 +#define USB_PORTSC1_PE_MASK 0x4u +#define USB_PORTSC1_PE_SHIFT 2 +#define USB_PORTSC1_PEC_MASK 0x8u +#define USB_PORTSC1_PEC_SHIFT 3 +#define USB_PORTSC1_OCA_MASK 0x10u +#define USB_PORTSC1_OCA_SHIFT 4 +#define USB_PORTSC1_OCC_MASK 0x20u +#define USB_PORTSC1_OCC_SHIFT 5 +#define USB_PORTSC1_FPR_MASK 0x40u +#define USB_PORTSC1_FPR_SHIFT 6 +#define USB_PORTSC1_SUSP_MASK 0x80u +#define USB_PORTSC1_SUSP_SHIFT 7 +#define USB_PORTSC1_PR_MASK 0x100u +#define USB_PORTSC1_PR_SHIFT 8 +#define USB_PORTSC1_HSP_MASK 0x200u +#define USB_PORTSC1_HSP_SHIFT 9 +#define USB_PORTSC1_LS_MASK 0xC00u +#define USB_PORTSC1_LS_SHIFT 10 +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_LS_SHIFT))&USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK 0x1000u +#define USB_PORTSC1_PP_SHIFT 12 +#define USB_PORTSC1_PO_MASK 0x2000u +#define USB_PORTSC1_PO_SHIFT 13 +#define USB_PORTSC1_PIC_MASK 0xC000u +#define USB_PORTSC1_PIC_SHIFT 14 +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PIC_SHIFT))&USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK 0xF0000u +#define USB_PORTSC1_PTC_SHIFT 16 +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PTC_SHIFT))&USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK 0x100000u +#define USB_PORTSC1_WKCN_SHIFT 20 +#define USB_PORTSC1_WKDC_MASK 0x200000u +#define USB_PORTSC1_WKDC_SHIFT 21 +#define USB_PORTSC1_WKOC_MASK 0x400000u +#define USB_PORTSC1_WKOC_SHIFT 22 +#define USB_PORTSC1_PHCD_MASK 0x800000u +#define USB_PORTSC1_PHCD_SHIFT 23 +#define USB_PORTSC1_PFSC_MASK 0x1000000u +#define USB_PORTSC1_PFSC_SHIFT 24 +#define USB_PORTSC1_PTS_2_MASK 0x2000000u +#define USB_PORTSC1_PTS_2_SHIFT 25 +#define USB_PORTSC1_PSPD_MASK 0xC000000u +#define USB_PORTSC1_PSPD_SHIFT 26 +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PSPD_SHIFT))&USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK 0x10000000u +#define USB_PORTSC1_PTW_SHIFT 28 +#define USB_PORTSC1_STS_MASK 0x20000000u +#define USB_PORTSC1_STS_SHIFT 29 +#define USB_PORTSC1_PTS_1_MASK 0xC0000000u +#define USB_PORTSC1_PTS_1_SHIFT 30 +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x))<<USB_PORTSC1_PTS_1_SHIFT))&USB_PORTSC1_PTS_1_MASK) +/* OTGSC Bit Fields */ +#define USB_OTGSC_VD_MASK 0x1u +#define USB_OTGSC_VD_SHIFT 0 +#define USB_OTGSC_VC_MASK 0x2u +#define USB_OTGSC_VC_SHIFT 1 +#define USB_OTGSC_OT_MASK 0x8u +#define USB_OTGSC_OT_SHIFT 3 +#define USB_OTGSC_DP_MASK 0x10u +#define USB_OTGSC_DP_SHIFT 4 +#define USB_OTGSC_IDPU_MASK 0x20u +#define USB_OTGSC_IDPU_SHIFT 5 +#define USB_OTGSC_ID_MASK 0x100u +#define USB_OTGSC_ID_SHIFT 8 +#define USB_OTGSC_AVV_MASK 0x200u +#define USB_OTGSC_AVV_SHIFT 9 +#define USB_OTGSC_ASV_MASK 0x400u +#define USB_OTGSC_ASV_SHIFT 10 +#define USB_OTGSC_BSV_MASK 0x800u +#define USB_OTGSC_BSV_SHIFT 11 +#define USB_OTGSC_BSE_MASK 0x1000u +#define USB_OTGSC_BSE_SHIFT 12 +#define USB_OTGSC_TOGGLE_1MS_MASK 0x2000u +#define USB_OTGSC_TOGGLE_1MS_SHIFT 13 +#define USB_OTGSC_DPS_MASK 0x4000u +#define USB_OTGSC_DPS_SHIFT 14 +#define USB_OTGSC_IDIS_MASK 0x10000u +#define USB_OTGSC_IDIS_SHIFT 16 +#define USB_OTGSC_AVVIS_MASK 0x20000u +#define USB_OTGSC_AVVIS_SHIFT 17 +#define USB_OTGSC_ASVIS_MASK 0x40000u +#define USB_OTGSC_ASVIS_SHIFT 18 +#define USB_OTGSC_BSVIS_MASK 0x80000u +#define USB_OTGSC_BSVIS_SHIFT 19 +#define USB_OTGSC_BSEIS_MASK 0x100000u +#define USB_OTGSC_BSEIS_SHIFT 20 +#define USB_OTGSC_RW2CLEAR_1MS_MASK 0x200000u +#define USB_OTGSC_RW2CLEAR_1MS_SHIFT 21 +#define USB_OTGSC_DPIS_MASK 0x400000u +#define USB_OTGSC_DPIS_SHIFT 22 +#define USB_OTGSC_IDIE_MASK 0x1000000u +#define USB_OTGSC_IDIE_SHIFT 24 +#define USB_OTGSC_AVVIE_MASK 0x2000000u +#define USB_OTGSC_AVVIE_SHIFT 25 +#define USB_OTGSC_ASVIE_MASK 0x4000000u +#define USB_OTGSC_ASVIE_SHIFT 26 +#define USB_OTGSC_BSVIE_MASK 0x8000000u +#define USB_OTGSC_BSVIE_SHIFT 27 +#define USB_OTGSC_BSEIE_MASK 0x10000000u +#define USB_OTGSC_BSEIE_SHIFT 28 +#define USB_OTGSC_INT_EN_1MS_MASK 0x20000000u +#define USB_OTGSC_INT_EN_1MS_SHIFT 29 +#define USB_OTGSC_DPIE_MASK 0x40000000u +#define USB_OTGSC_DPIE_SHIFT 30 +/* USBMODE Bit Fields */ +#define USB_USBMODE_CM_MASK 0x3u +#define USB_USBMODE_CM_SHIFT 0 +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x))<<USB_USBMODE_CM_SHIFT))&USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK 0x4u +#define USB_USBMODE_ES_SHIFT 2 +#define USB_USBMODE_SLOM_MASK 0x8u +#define USB_USBMODE_SLOM_SHIFT 3 +#define USB_USBMODE_SDIS_MASK 0x10u +#define USB_USBMODE_SDIS_SHIFT 4 +/* ENDPTSETUPSTAT Bit Fields */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK 0xFFFFu +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT 0 +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT))&USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/* ENDPTPRIME Bit Fields */ +#define USB_ENDPTPRIME_PERB_MASK 0xFFu +#define USB_ENDPTPRIME_PERB_SHIFT 0 +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTPRIME_PERB_SHIFT))&USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK 0xFF0000u +#define USB_ENDPTPRIME_PETB_SHIFT 16 +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTPRIME_PETB_SHIFT))&USB_ENDPTPRIME_PETB_MASK) +/* ENDPTFLUSH Bit Fields */ +#define USB_ENDPTFLUSH_FERB_MASK 0xFFu +#define USB_ENDPTFLUSH_FERB_SHIFT 0 +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTFLUSH_FERB_SHIFT))&USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK 0xFF0000u +#define USB_ENDPTFLUSH_FETB_SHIFT 16 +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTFLUSH_FETB_SHIFT))&USB_ENDPTFLUSH_FETB_MASK) +/* ENDPTSTAT Bit Fields */ +#define USB_ENDPTSTAT_ERBR_MASK 0xFFu +#define USB_ENDPTSTAT_ERBR_SHIFT 0 +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSTAT_ERBR_SHIFT))&USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK 0xFF0000u +#define USB_ENDPTSTAT_ETBR_SHIFT 16 +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTSTAT_ETBR_SHIFT))&USB_ENDPTSTAT_ETBR_MASK) +/* ENDPTCOMPLETE Bit Fields */ +#define USB_ENDPTCOMPLETE_ERCE_MASK 0xFFu +#define USB_ENDPTCOMPLETE_ERCE_SHIFT 0 +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCOMPLETE_ERCE_SHIFT))&USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK 0xFF0000u +#define USB_ENDPTCOMPLETE_ETCE_SHIFT 16 +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCOMPLETE_ETCE_SHIFT))&USB_ENDPTCOMPLETE_ETCE_MASK) +/* ENDPTCTRL0 Bit Fields */ +#define USB_ENDPTCTRL0_RXS_MASK 0x1u +#define USB_ENDPTCTRL0_RXS_SHIFT 0 +#define USB_ENDPTCTRL0_RXT_MASK 0xCu +#define USB_ENDPTCTRL0_RXT_SHIFT 2 +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL0_RXT_SHIFT))&USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK 0x80u +#define USB_ENDPTCTRL0_RXE_SHIFT 7 +#define USB_ENDPTCTRL0_TXS_MASK 0x10000u +#define USB_ENDPTCTRL0_TXS_SHIFT 16 +#define USB_ENDPTCTRL0_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL0_TXT_SHIFT 18 +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL0_TXT_SHIFT))&USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK 0x800000u +#define USB_ENDPTCTRL0_TXE_SHIFT 23 +/* ENDPTCTRL1 Bit Fields */ +#define USB_ENDPTCTRL1_RXS_MASK 0x1u +#define USB_ENDPTCTRL1_RXS_SHIFT 0 +#define USB_ENDPTCTRL1_RXD_MASK 0x2u +#define USB_ENDPTCTRL1_RXD_SHIFT 1 +#define USB_ENDPTCTRL1_RXT_MASK 0xCu +#define USB_ENDPTCTRL1_RXT_SHIFT 2 +#define USB_ENDPTCTRL1_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL1_RXT_SHIFT))&USB_ENDPTCTRL1_RXT_MASK) +#define USB_ENDPTCTRL1_RXI_MASK 0x20u +#define USB_ENDPTCTRL1_RXI_SHIFT 5 +#define USB_ENDPTCTRL1_RXR_MASK 0x40u +#define USB_ENDPTCTRL1_RXR_SHIFT 6 +#define USB_ENDPTCTRL1_RXE_MASK 0x80u +#define USB_ENDPTCTRL1_RXE_SHIFT 7 +#define USB_ENDPTCTRL1_TXS_MASK 0x10000u +#define USB_ENDPTCTRL1_TXS_SHIFT 16 +#define USB_ENDPTCTRL1_TXD_MASK 0x20000u +#define USB_ENDPTCTRL1_TXD_SHIFT 17 +#define USB_ENDPTCTRL1_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL1_TXT_SHIFT 18 +#define USB_ENDPTCTRL1_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL1_TXT_SHIFT))&USB_ENDPTCTRL1_TXT_MASK) +#define USB_ENDPTCTRL1_TXI_MASK 0x200000u +#define USB_ENDPTCTRL1_TXI_SHIFT 21 +#define USB_ENDPTCTRL1_TXR_MASK 0x400000u +#define USB_ENDPTCTRL1_TXR_SHIFT 22 +#define USB_ENDPTCTRL1_TXE_MASK 0x800000u +#define USB_ENDPTCTRL1_TXE_SHIFT 23 +/* ENDPTCTRL2 Bit Fields */ +#define USB_ENDPTCTRL2_RXS_MASK 0x1u +#define USB_ENDPTCTRL2_RXS_SHIFT 0 +#define USB_ENDPTCTRL2_RXD_MASK 0x2u +#define USB_ENDPTCTRL2_RXD_SHIFT 1 +#define USB_ENDPTCTRL2_RXT_MASK 0xCu +#define USB_ENDPTCTRL2_RXT_SHIFT 2 +#define USB_ENDPTCTRL2_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL2_RXT_SHIFT))&USB_ENDPTCTRL2_RXT_MASK) +#define USB_ENDPTCTRL2_RXI_MASK 0x20u +#define USB_ENDPTCTRL2_RXI_SHIFT 5 +#define USB_ENDPTCTRL2_RXR_MASK 0x40u +#define USB_ENDPTCTRL2_RXR_SHIFT 6 +#define USB_ENDPTCTRL2_RXE_MASK 0x80u +#define USB_ENDPTCTRL2_RXE_SHIFT 7 +#define USB_ENDPTCTRL2_TXS_MASK 0x10000u +#define USB_ENDPTCTRL2_TXS_SHIFT 16 +#define USB_ENDPTCTRL2_TXD_MASK 0x20000u +#define USB_ENDPTCTRL2_TXD_SHIFT 17 +#define USB_ENDPTCTRL2_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL2_TXT_SHIFT 18 +#define USB_ENDPTCTRL2_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL2_TXT_SHIFT))&USB_ENDPTCTRL2_TXT_MASK) +#define USB_ENDPTCTRL2_TXI_MASK 0x200000u +#define USB_ENDPTCTRL2_TXI_SHIFT 21 +#define USB_ENDPTCTRL2_TXR_MASK 0x400000u +#define USB_ENDPTCTRL2_TXR_SHIFT 22 +#define USB_ENDPTCTRL2_TXE_MASK 0x800000u +#define USB_ENDPTCTRL2_TXE_SHIFT 23 +/* ENDPTCTRL3 Bit Fields */ +#define USB_ENDPTCTRL3_RXS_MASK 0x1u +#define USB_ENDPTCTRL3_RXS_SHIFT 0 +#define USB_ENDPTCTRL3_RXD_MASK 0x2u +#define USB_ENDPTCTRL3_RXD_SHIFT 1 +#define USB_ENDPTCTRL3_RXT_MASK 0xCu +#define USB_ENDPTCTRL3_RXT_SHIFT 2 +#define USB_ENDPTCTRL3_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL3_RXT_SHIFT))&USB_ENDPTCTRL3_RXT_MASK) +#define USB_ENDPTCTRL3_RXI_MASK 0x20u +#define USB_ENDPTCTRL3_RXI_SHIFT 5 +#define USB_ENDPTCTRL3_RXR_MASK 0x40u +#define USB_ENDPTCTRL3_RXR_SHIFT 6 +#define USB_ENDPTCTRL3_RXE_MASK 0x80u +#define USB_ENDPTCTRL3_RXE_SHIFT 7 +#define USB_ENDPTCTRL3_TXS_MASK 0x10000u +#define USB_ENDPTCTRL3_TXS_SHIFT 16 +#define USB_ENDPTCTRL3_TXD_MASK 0x20000u +#define USB_ENDPTCTRL3_TXD_SHIFT 17 +#define USB_ENDPTCTRL3_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL3_TXT_SHIFT 18 +#define USB_ENDPTCTRL3_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL3_TXT_SHIFT))&USB_ENDPTCTRL3_TXT_MASK) +#define USB_ENDPTCTRL3_TXI_MASK 0x200000u +#define USB_ENDPTCTRL3_TXI_SHIFT 21 +#define USB_ENDPTCTRL3_TXR_MASK 0x400000u +#define USB_ENDPTCTRL3_TXR_SHIFT 22 +#define USB_ENDPTCTRL3_TXE_MASK 0x800000u +#define USB_ENDPTCTRL3_TXE_SHIFT 23 +/* ENDPTCTRL4 Bit Fields */ +#define USB_ENDPTCTRL4_RXS_MASK 0x1u +#define USB_ENDPTCTRL4_RXS_SHIFT 0 +#define USB_ENDPTCTRL4_RXD_MASK 0x2u +#define USB_ENDPTCTRL4_RXD_SHIFT 1 +#define USB_ENDPTCTRL4_RXT_MASK 0xCu +#define USB_ENDPTCTRL4_RXT_SHIFT 2 +#define USB_ENDPTCTRL4_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL4_RXT_SHIFT))&USB_ENDPTCTRL4_RXT_MASK) +#define USB_ENDPTCTRL4_RXI_MASK 0x20u +#define USB_ENDPTCTRL4_RXI_SHIFT 5 +#define USB_ENDPTCTRL4_RXR_MASK 0x40u +#define USB_ENDPTCTRL4_RXR_SHIFT 6 +#define USB_ENDPTCTRL4_RXE_MASK 0x80u +#define USB_ENDPTCTRL4_RXE_SHIFT 7 +#define USB_ENDPTCTRL4_TXS_MASK 0x10000u +#define USB_ENDPTCTRL4_TXS_SHIFT 16 +#define USB_ENDPTCTRL4_TXD_MASK 0x20000u +#define USB_ENDPTCTRL4_TXD_SHIFT 17 +#define USB_ENDPTCTRL4_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL4_TXT_SHIFT 18 +#define USB_ENDPTCTRL4_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL4_TXT_SHIFT))&USB_ENDPTCTRL4_TXT_MASK) +#define USB_ENDPTCTRL4_TXI_MASK 0x200000u +#define USB_ENDPTCTRL4_TXI_SHIFT 21 +#define USB_ENDPTCTRL4_TXR_MASK 0x400000u +#define USB_ENDPTCTRL4_TXR_SHIFT 22 +#define USB_ENDPTCTRL4_TXE_MASK 0x800000u +#define USB_ENDPTCTRL4_TXE_SHIFT 23 +/* ENDPTCTRL5 Bit Fields */ +#define USB_ENDPTCTRL5_RXS_MASK 0x1u +#define USB_ENDPTCTRL5_RXS_SHIFT 0 +#define USB_ENDPTCTRL5_RXD_MASK 0x2u +#define USB_ENDPTCTRL5_RXD_SHIFT 1 +#define USB_ENDPTCTRL5_RXT_MASK 0xCu +#define USB_ENDPTCTRL5_RXT_SHIFT 2 +#define USB_ENDPTCTRL5_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL5_RXT_SHIFT))&USB_ENDPTCTRL5_RXT_MASK) +#define USB_ENDPTCTRL5_RXI_MASK 0x20u +#define USB_ENDPTCTRL5_RXI_SHIFT 5 +#define USB_ENDPTCTRL5_RXR_MASK 0x40u +#define USB_ENDPTCTRL5_RXR_SHIFT 6 +#define USB_ENDPTCTRL5_RXE_MASK 0x80u +#define USB_ENDPTCTRL5_RXE_SHIFT 7 +#define USB_ENDPTCTRL5_TXS_MASK 0x10000u +#define USB_ENDPTCTRL5_TXS_SHIFT 16 +#define USB_ENDPTCTRL5_TXD_MASK 0x20000u +#define USB_ENDPTCTRL5_TXD_SHIFT 17 +#define USB_ENDPTCTRL5_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL5_TXT_SHIFT 18 +#define USB_ENDPTCTRL5_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL5_TXT_SHIFT))&USB_ENDPTCTRL5_TXT_MASK) +#define USB_ENDPTCTRL5_TXI_MASK 0x200000u +#define USB_ENDPTCTRL5_TXI_SHIFT 21 +#define USB_ENDPTCTRL5_TXR_MASK 0x400000u +#define USB_ENDPTCTRL5_TXR_SHIFT 22 +#define USB_ENDPTCTRL5_TXE_MASK 0x800000u +#define USB_ENDPTCTRL5_TXE_SHIFT 23 +/* ENDPTCTRL6 Bit Fields */ +#define USB_ENDPTCTRL6_RXS_MASK 0x1u +#define USB_ENDPTCTRL6_RXS_SHIFT 0 +#define USB_ENDPTCTRL6_RXD_MASK 0x2u +#define USB_ENDPTCTRL6_RXD_SHIFT 1 +#define USB_ENDPTCTRL6_RXT_MASK 0xCu +#define USB_ENDPTCTRL6_RXT_SHIFT 2 +#define USB_ENDPTCTRL6_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL6_RXT_SHIFT))&USB_ENDPTCTRL6_RXT_MASK) +#define USB_ENDPTCTRL6_RXI_MASK 0x20u +#define USB_ENDPTCTRL6_RXI_SHIFT 5 +#define USB_ENDPTCTRL6_RXR_MASK 0x40u +#define USB_ENDPTCTRL6_RXR_SHIFT 6 +#define USB_ENDPTCTRL6_RXE_MASK 0x80u +#define USB_ENDPTCTRL6_RXE_SHIFT 7 +#define USB_ENDPTCTRL6_TXS_MASK 0x10000u +#define USB_ENDPTCTRL6_TXS_SHIFT 16 +#define USB_ENDPTCTRL6_TXD_MASK 0x20000u +#define USB_ENDPTCTRL6_TXD_SHIFT 17 +#define USB_ENDPTCTRL6_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL6_TXT_SHIFT 18 +#define USB_ENDPTCTRL6_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL6_TXT_SHIFT))&USB_ENDPTCTRL6_TXT_MASK) +#define USB_ENDPTCTRL6_TXI_MASK 0x200000u +#define USB_ENDPTCTRL6_TXI_SHIFT 21 +#define USB_ENDPTCTRL6_TXR_MASK 0x400000u +#define USB_ENDPTCTRL6_TXR_SHIFT 22 +#define USB_ENDPTCTRL6_TXE_MASK 0x800000u +#define USB_ENDPTCTRL6_TXE_SHIFT 23 +/* ENDPTCTRL7 Bit Fields */ +#define USB_ENDPTCTRL7_RXS_MASK 0x1u +#define USB_ENDPTCTRL7_RXS_SHIFT 0 +#define USB_ENDPTCTRL7_RXD_MASK 0x2u +#define USB_ENDPTCTRL7_RXD_SHIFT 1 +#define USB_ENDPTCTRL7_RXT_MASK 0xCu +#define USB_ENDPTCTRL7_RXT_SHIFT 2 +#define USB_ENDPTCTRL7_RXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL7_RXT_SHIFT))&USB_ENDPTCTRL7_RXT_MASK) +#define USB_ENDPTCTRL7_RXI_MASK 0x20u +#define USB_ENDPTCTRL7_RXI_SHIFT 5 +#define USB_ENDPTCTRL7_RXR_MASK 0x40u +#define USB_ENDPTCTRL7_RXR_SHIFT 6 +#define USB_ENDPTCTRL7_RXE_MASK 0x80u +#define USB_ENDPTCTRL7_RXE_SHIFT 7 +#define USB_ENDPTCTRL7_TXS_MASK 0x10000u +#define USB_ENDPTCTRL7_TXS_SHIFT 16 +#define USB_ENDPTCTRL7_TXD_MASK 0x20000u +#define USB_ENDPTCTRL7_TXD_SHIFT 17 +#define USB_ENDPTCTRL7_TXT_MASK 0xC0000u +#define USB_ENDPTCTRL7_TXT_SHIFT 18 +#define USB_ENDPTCTRL7_TXT(x) (((uint32_t)(((uint32_t)(x))<<USB_ENDPTCTRL7_TXT_SHIFT))&USB_ENDPTCTRL7_TXT_MASK) +#define USB_ENDPTCTRL7_TXI_MASK 0x200000u +#define USB_ENDPTCTRL7_TXI_SHIFT 21 +#define USB_ENDPTCTRL7_TXR_MASK 0x400000u +#define USB_ENDPTCTRL7_TXR_SHIFT 22 +#define USB_ENDPTCTRL7_TXE_MASK 0x800000u +#define USB_ENDPTCTRL7_TXE_SHIFT 23 + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x30B10000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +#define USB1_BASE_PTR (USB1) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x30B20000u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +#define USB2_BASE_PTR (USB2) +/** Peripheral USB3 base address */ +#define USB3_BASE (0x30B30000u) +/** Peripheral USB3 base pointer */ +#define USB3 ((USB_Type *)USB3_BASE) +#define USB3_BASE_PTR (USB3) +/** Array initializer of USB peripheral base adresses */ +#define USB_BASE_ADDRS { USB1_BASE, USB2_BASE, USB3_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB1, USB2, USB3 } + +/* ---------------------------------------------------------------------------- + -- USB - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros + * @{ + */ + + +/* USB - Register instance definitions */ +/* USB1 */ +#define USB1_ID USB_ID_REG(USB1_BASE_PTR) +#define USB1_HWGENERAL USB_HWGENERAL_REG(USB1_BASE_PTR) +#define USB1_HWHOST USB_HWHOST_REG(USB1_BASE_PTR) +#define USB1_HWDEVICE USB_HWDEVICE_REG(USB1_BASE_PTR) +#define USB1_HWTXBUF USB_HWTXBUF_REG(USB1_BASE_PTR) +#define USB1_HWRXBUF USB_HWRXBUF_REG(USB1_BASE_PTR) +#define USB1_GPTIMER0LD USB_GPTIMER0LD_REG(USB1_BASE_PTR) +#define USB1_GPTIMER0CTRL USB_GPTIMER0CTRL_REG(USB1_BASE_PTR) +#define USB1_GPTIMER1LD USB_GPTIMER1LD_REG(USB1_BASE_PTR) +#define USB1_GPTIMER1CTRL USB_GPTIMER1CTRL_REG(USB1_BASE_PTR) +#define USB1_SBUSCFG USB_SBUSCFG_REG(USB1_BASE_PTR) +#define USB1_CAPLENGTH USB_CAPLENGTH_REG(USB1_BASE_PTR) +#define USB1_HCIVERSION USB_HCIVERSION_REG(USB1_BASE_PTR) +#define USB1_HCSPARAMS USB_HCSPARAMS_REG(USB1_BASE_PTR) +#define USB1_HCCPARAMS USB_HCCPARAMS_REG(USB1_BASE_PTR) +#define USB1_DCIVERSION USB_DCIVERSION_REG(USB1_BASE_PTR) +#define USB1_DCCPARAMS USB_DCCPARAMS_REG(USB1_BASE_PTR) +#define USB1_USBCMD USB_USBCMD_REG(USB1_BASE_PTR) +#define USB1_USBSTS USB_USBSTS_REG(USB1_BASE_PTR) +#define USB1_USBINTR USB_USBINTR_REG(USB1_BASE_PTR) +#define USB1_FRINDEX USB_FRINDEX_REG(USB1_BASE_PTR) +#define USB1_DEVICEADDR USB_DEVICEADDR_REG(USB1_BASE_PTR) +#define USB1_PERIODICLISTBASE USB_PERIODICLISTBASE_REG(USB1_BASE_PTR) +#define USB1_ASYNCLISTADDR USB_ASYNCLISTADDR_REG(USB1_BASE_PTR) +#define USB1_ENDPTLISTADDR USB_ENDPTLISTADDR_REG(USB1_BASE_PTR) +#define USB1_BURSTSIZE USB_BURSTSIZE_REG(USB1_BASE_PTR) +#define USB1_TXFILLTUNING USB_TXFILLTUNING_REG(USB1_BASE_PTR) +#define USB1_ENDPTNAK USB_ENDPTNAK_REG(USB1_BASE_PTR) +#define USB1_ENDPTNAKEN USB_ENDPTNAKEN_REG(USB1_BASE_PTR) +#define USB1_CONFIGFLAG USB_CONFIGFLAG_REG(USB1_BASE_PTR) +#define USB1_PORTSC1 USB_PORTSC1_REG(USB1_BASE_PTR) +#define USB1_OTGSC USB_OTGSC_REG(USB1_BASE_PTR) +#define USB1_USBMODE USB_USBMODE_REG(USB1_BASE_PTR) +#define USB1_ENDPTSETUPSTAT USB_ENDPTSETUPSTAT_REG(USB1_BASE_PTR) +#define USB1_ENDPTPRIME USB_ENDPTPRIME_REG(USB1_BASE_PTR) +#define USB1_ENDPTFLUSH USB_ENDPTFLUSH_REG(USB1_BASE_PTR) +#define USB1_ENDPTSTAT USB_ENDPTSTAT_REG(USB1_BASE_PTR) +#define USB1_ENDPTCOMPLETE USB_ENDPTCOMPLETE_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL0 USB_ENDPTCTRL0_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL1 USB_ENDPTCTRL1_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL2 USB_ENDPTCTRL2_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL3 USB_ENDPTCTRL3_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL4 USB_ENDPTCTRL4_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL5 USB_ENDPTCTRL5_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL6 USB_ENDPTCTRL6_REG(USB1_BASE_PTR) +#define USB1_ENDPTCTRL7 USB_ENDPTCTRL7_REG(USB1_BASE_PTR) +/* USB2 */ +#define USB2_ID USB_ID_REG(USB2_BASE_PTR) +#define USB2_HWGENERAL USB_HWGENERAL_REG(USB2_BASE_PTR) +#define USB2_HWHOST USB_HWHOST_REG(USB2_BASE_PTR) +#define USB2_HWDEVICE USB_HWDEVICE_REG(USB2_BASE_PTR) +#define USB2_HWTXBUF USB_HWTXBUF_REG(USB2_BASE_PTR) +#define USB2_HWRXBUF USB_HWRXBUF_REG(USB2_BASE_PTR) +#define USB2_GPTIMER0LD USB_GPTIMER0LD_REG(USB2_BASE_PTR) +#define USB2_GPTIMER0CTRL USB_GPTIMER0CTRL_REG(USB2_BASE_PTR) +#define USB2_GPTIMER1LD USB_GPTIMER1LD_REG(USB2_BASE_PTR) +#define USB2_GPTIMER1CTRL USB_GPTIMER1CTRL_REG(USB2_BASE_PTR) +#define USB2_SBUSCFG USB_SBUSCFG_REG(USB2_BASE_PTR) +#define USB2_CAPLENGTH USB_CAPLENGTH_REG(USB2_BASE_PTR) +#define USB2_HCIVERSION USB_HCIVERSION_REG(USB2_BASE_PTR) +#define USB2_HCSPARAMS USB_HCSPARAMS_REG(USB2_BASE_PTR) +#define USB2_HCCPARAMS USB_HCCPARAMS_REG(USB2_BASE_PTR) +#define USB2_DCIVERSION USB_DCIVERSION_REG(USB2_BASE_PTR) +#define USB2_DCCPARAMS USB_DCCPARAMS_REG(USB2_BASE_PTR) +#define USB2_USBCMD USB_USBCMD_REG(USB2_BASE_PTR) +#define USB2_USBSTS USB_USBSTS_REG(USB2_BASE_PTR) +#define USB2_USBINTR USB_USBINTR_REG(USB2_BASE_PTR) +#define USB2_FRINDEX USB_FRINDEX_REG(USB2_BASE_PTR) +#define USB2_DEVICEADDR USB_DEVICEADDR_REG(USB2_BASE_PTR) +#define USB2_PERIODICLISTBASE USB_PERIODICLISTBASE_REG(USB2_BASE_PTR) +#define USB2_ASYNCLISTADDR USB_ASYNCLISTADDR_REG(USB2_BASE_PTR) +#define USB2_ENDPTLISTADDR USB_ENDPTLISTADDR_REG(USB2_BASE_PTR) +#define USB2_BURSTSIZE USB_BURSTSIZE_REG(USB2_BASE_PTR) +#define USB2_TXFILLTUNING USB_TXFILLTUNING_REG(USB2_BASE_PTR) +#define USB2_ENDPTNAK USB_ENDPTNAK_REG(USB2_BASE_PTR) +#define USB2_ENDPTNAKEN USB_ENDPTNAKEN_REG(USB2_BASE_PTR) +#define USB2_CONFIGFLAG USB_CONFIGFLAG_REG(USB2_BASE_PTR) +#define USB2_PORTSC1 USB_PORTSC1_REG(USB2_BASE_PTR) +#define USB2_OTGSC USB_OTGSC_REG(USB2_BASE_PTR) +#define USB2_USBMODE USB_USBMODE_REG(USB2_BASE_PTR) +#define USB2_ENDPTSETUPSTAT USB_ENDPTSETUPSTAT_REG(USB2_BASE_PTR) +#define USB2_ENDPTPRIME USB_ENDPTPRIME_REG(USB2_BASE_PTR) +#define USB2_ENDPTFLUSH USB_ENDPTFLUSH_REG(USB2_BASE_PTR) +#define USB2_ENDPTSTAT USB_ENDPTSTAT_REG(USB2_BASE_PTR) +#define USB2_ENDPTCOMPLETE USB_ENDPTCOMPLETE_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL0 USB_ENDPTCTRL0_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL1 USB_ENDPTCTRL1_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL2 USB_ENDPTCTRL2_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL3 USB_ENDPTCTRL3_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL4 USB_ENDPTCTRL4_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL5 USB_ENDPTCTRL5_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL6 USB_ENDPTCTRL6_REG(USB2_BASE_PTR) +#define USB2_ENDPTCTRL7 USB_ENDPTCTRL7_REG(USB2_BASE_PTR) +/* USB3 */ +#define USB3_ID USB_ID_REG(USB3_BASE_PTR) +#define USB3_HWGENERAL USB_HWGENERAL_REG(USB3_BASE_PTR) +#define USB3_HWHOST USB_HWHOST_REG(USB3_BASE_PTR) +#define USB3_HWDEVICE USB_HWDEVICE_REG(USB3_BASE_PTR) +#define USB3_HWTXBUF USB_HWTXBUF_REG(USB3_BASE_PTR) +#define USB3_HWRXBUF USB_HWRXBUF_REG(USB3_BASE_PTR) +#define USB3_GPTIMER0LD USB_GPTIMER0LD_REG(USB3_BASE_PTR) +#define USB3_GPTIMER0CTRL USB_GPTIMER0CTRL_REG(USB3_BASE_PTR) +#define USB3_GPTIMER1LD USB_GPTIMER1LD_REG(USB3_BASE_PTR) +#define USB3_GPTIMER1CTRL USB_GPTIMER1CTRL_REG(USB3_BASE_PTR) +#define USB3_SBUSCFG USB_SBUSCFG_REG(USB3_BASE_PTR) +#define USB3_CAPLENGTH USB_CAPLENGTH_REG(USB3_BASE_PTR) +#define USB3_HCIVERSION USB_HCIVERSION_REG(USB3_BASE_PTR) +#define USB3_HCSPARAMS USB_HCSPARAMS_REG(USB3_BASE_PTR) +#define USB3_HCCPARAMS USB_HCCPARAMS_REG(USB3_BASE_PTR) +#define USB3_DCIVERSION USB_DCIVERSION_REG(USB3_BASE_PTR) +#define USB3_DCCPARAMS USB_DCCPARAMS_REG(USB3_BASE_PTR) +#define USB3_USBCMD USB_USBCMD_REG(USB3_BASE_PTR) +#define USB3_USBSTS USB_USBSTS_REG(USB3_BASE_PTR) +#define USB3_USBINTR USB_USBINTR_REG(USB3_BASE_PTR) +#define USB3_FRINDEX USB_FRINDEX_REG(USB3_BASE_PTR) +#define USB3_DEVICEADDR USB_DEVICEADDR_REG(USB3_BASE_PTR) +#define USB3_PERIODICLISTBASE USB_PERIODICLISTBASE_REG(USB3_BASE_PTR) +#define USB3_ASYNCLISTADDR USB_ASYNCLISTADDR_REG(USB3_BASE_PTR) +#define USB3_ENDPTLISTADDR USB_ENDPTLISTADDR_REG(USB3_BASE_PTR) +#define USB3_BURSTSIZE USB_BURSTSIZE_REG(USB3_BASE_PTR) +#define USB3_TXFILLTUNING USB_TXFILLTUNING_REG(USB3_BASE_PTR) +#define USB3_ENDPTNAK USB_ENDPTNAK_REG(USB3_BASE_PTR) +#define USB3_ENDPTNAKEN USB_ENDPTNAKEN_REG(USB3_BASE_PTR) +#define USB3_CONFIGFLAG USB_CONFIGFLAG_REG(USB3_BASE_PTR) +#define USB3_PORTSC1 USB_PORTSC1_REG(USB3_BASE_PTR) +#define USB3_OTGSC USB_OTGSC_REG(USB3_BASE_PTR) +#define USB3_USBMODE USB_USBMODE_REG(USB3_BASE_PTR) +#define USB3_ENDPTSETUPSTAT USB_ENDPTSETUPSTAT_REG(USB3_BASE_PTR) +#define USB3_ENDPTPRIME USB_ENDPTPRIME_REG(USB3_BASE_PTR) +#define USB3_ENDPTFLUSH USB_ENDPTFLUSH_REG(USB3_BASE_PTR) +#define USB3_ENDPTSTAT USB_ENDPTSTAT_REG(USB3_BASE_PTR) +#define USB3_ENDPTCOMPLETE USB_ENDPTCOMPLETE_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL0 USB_ENDPTCTRL0_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL1 USB_ENDPTCTRL1_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL2 USB_ENDPTCTRL2_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL3 USB_ENDPTCTRL3_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL4 USB_ENDPTCTRL4_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL5 USB_ENDPTCTRL5_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL6 USB_ENDPTCTRL6_REG(USB3_BASE_PTR) +#define USB3_ENDPTCTRL7 USB_ENDPTCTRL7_REG(USB3_BASE_PTR) + +/*! + * @} + */ /* end of group USB_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group USB_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[512]; + __IO uint32_t USB_x_CTRL1; /**< , offset: 0x200 */ + __IO uint32_t USB_x_CTRL2; /**< , offset: 0x204 */ + uint8_t RESERVED_1[44]; + __IO uint32_t USB_x_PHY_CTL2; /**< , offset: 0x234 */ + uint8_t RESERVED_2[4]; + __IO uint32_t USB_x_PHY_STS; /**< , offset: 0x23C */ + uint8_t RESERVED_3[16]; + __IO uint32_t ADP_CFG1; /**< , offset: 0x250 */ + __IO uint32_t ADP_CFG2; /**< , offset: 0x254 */ + __I uint32_t ADP_STATUS; /**< , offset: 0x258 */ +} USBNC_Type, *USBNC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- USBNC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros + * @{ + */ + + +/* USBNC - Register accessors */ +#define USBNC_USB_x_CTRL1_REG(base) ((base)->USB_x_CTRL1) +#define USBNC_USB_x_CTRL2_REG(base) ((base)->USB_x_CTRL2) +#define USBNC_USB_x_PHY_CTL2_REG(base) ((base)->USB_x_PHY_CTL2) +#define USBNC_USB_x_PHY_STS_REG(base) ((base)->USB_x_PHY_STS) +#define USBNC_ADP_CFG1_REG(base) ((base)->ADP_CFG1) +#define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) +#define USBNC_ADP_STATUS_REG(base) ((base)->ADP_STATUS) + +/*! + * @} + */ /* end of group USBNC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/* USB_x_CTRL1 Bit Fields */ +#define USBNC_USB_x_CTRL1_OVER_CUR_DIS_MASK 0x80u +#define USBNC_USB_x_CTRL1_OVER_CUR_DIS_SHIFT 7 +#define USBNC_USB_x_CTRL1_OVER_CUR_POL_MASK 0x100u +#define USBNC_USB_x_CTRL1_OVER_CUR_POL_SHIFT 8 +#define USBNC_USB_x_CTRL1_PWR_POL_MASK 0x200u +#define USBNC_USB_x_CTRL1_PWR_POL_SHIFT 9 +#define USBNC_USB_x_CTRL1_WIE_MASK 0x400u +#define USBNC_USB_x_CTRL1_WIE_SHIFT 10 +#define USBNC_USB_x_CTRL1_WKUP_SW_EN_MASK 0x4000u +#define USBNC_USB_x_CTRL1_WKUP_SW_EN_SHIFT 14 +#define USBNC_USB_x_CTRL1_WKUP_SW_MASK 0x8000u +#define USBNC_USB_x_CTRL1_WKUP_SW_SHIFT 15 +#define USBNC_USB_x_CTRL1_WKUP_ID_EN_MASK 0x10000u +#define USBNC_USB_x_CTRL1_WKUP_ID_EN_SHIFT 16 +#define USBNC_USB_x_CTRL1_WKUP_VBUS_EN_MASK 0x20000u +#define USBNC_USB_x_CTRL1_WKUP_VBUS_EN_SHIFT 17 +#define USBNC_USB_x_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u +#define USBNC_USB_x_CTRL1_WKUP_DPDM_EN_SHIFT 29 +#define USBNC_USB_x_CTRL1_WIR_MASK 0x80000000u +#define USBNC_USB_x_CTRL1_WIR_SHIFT 31 +/* USB_x_CTRL2 Bit Fields */ +#define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u +#define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 +#define USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<<USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_SHIFT))&USBNC_USB_x_CTRL2_VBUS_SOURCE_SEL_MASK) +#define USBNC_USB_x_CTRL2_AUTURESUME_EN_MASK 0x4u +#define USBNC_USB_x_CTRL2_AUTURESUME_EN_SHIFT 2 +#define USBNC_USB_x_CTRL2_LOWSPEED_EN_MASK 0x8u +#define USBNC_USB_x_CTRL2_LOWSPEED_EN_SHIFT 3 +#define USBNC_USB_x_CTRL2_DIG_ID_SEL_MASK 0x100000u +#define USBNC_USB_x_CTRL2_DIG_ID_SEL_SHIFT 20 +#define USBNC_USB_x_CTRL2_UTMI_CLK_VLD_MASK 0x80000000u +#define USBNC_USB_x_CTRL2_UTMI_CLK_VLD_SHIFT 31 +/* USB_x_PHY_CTL2 Bit Fields */ +#define USBNC_USB_x_PHY_CTL2_CHRGSEL0_MASK 0x1u +#define USBNC_USB_x_PHY_CTL2_CHRGSEL0_SHIFT 0 +#define USBNC_USB_x_PHY_CTL2_VDATDETENB0_MASK 0x2u +#define USBNC_USB_x_PHY_CTL2_VDATDETENB0_SHIFT 1 +#define USBNC_USB_x_PHY_CTL2_VDATSRCENB0_MASK 0x4u +#define USBNC_USB_x_PHY_CTL2_VDATSRCENB0_SHIFT 2 +#define USBNC_USB_x_PHY_CTL2_DCDENB0_MASK 0x8u +#define USBNC_USB_x_PHY_CTL2_DCDENB0_SHIFT 3 +/* USB_x_PHY_STS Bit Fields */ +#define USBNC_USB_x_PHY_STS_LINE_STATE_MASK 0x3u +#define USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT 0 +#define USBNC_USB_x_PHY_STS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<<USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT))&USBNC_USB_x_PHY_STS_LINE_STATE_MASK) +#define USBNC_USB_x_PHY_STS_SESS_VLD_MASK 0x4u +#define USBNC_USB_x_PHY_STS_SESS_VLD_SHIFT 2 +#define USBNC_USB_x_PHY_STS_VBUS_VLD_MASK 0x8u +#define USBNC_USB_x_PHY_STS_VBUS_VLD_SHIFT 3 +#define USBNC_USB_x_PHY_STS_ID_DIG_MASK 0x10u +#define USBNC_USB_x_PHY_STS_ID_DIG_SHIFT 4 +#define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_MASK 0x20000000u +#define USBNC_USB_x_PHY_STS_USB_OTG1_CHD_B_SHIFT 29 +/* ADP_CFG1 Bit Fields */ +#define USBNC_ADP_CFG1_ADP_WAIT_MASK 0x3FFFFu +#define USBNC_ADP_CFG1_ADP_WAIT_SHIFT 0 +#define USBNC_ADP_CFG1_ADP_WAIT(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG1_ADP_WAIT_SHIFT))&USBNC_ADP_CFG1_ADP_WAIT_MASK) +#define USBNC_ADP_CFG1_TIMER_EN_MASK 0x100000u +#define USBNC_ADP_CFG1_TIMER_EN_SHIFT 20 +#define USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK 0x200000u +#define USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT 21 +#define USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK 0x400000u +#define USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT 22 +#define USBNC_ADP_CFG1_ADP_PRB_EN_MASK 0x800000u +#define USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT 23 +/* ADP_CFG2 Bit Fields */ +#define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK 0x7Fu +#define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT 0 +#define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK) +#define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK 0x80u +#define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT 7 +#define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK 0xFF00u +#define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT 8 +#define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT))&USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK) +#define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK 0xFF0000u +#define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT 16 +#define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT))&USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK) +/* ADP_STATUS Bit Fields */ +#define USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK 0xFFu +#define USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT 0 +#define USBNC_ADP_STATUS_ADP_PRB_TIMR(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT))&USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK) +#define USBNC_ADP_STATUS_ADP_CNT_MASK 0x3FFFF00u +#define USBNC_ADP_STATUS_ADP_CNT_SHIFT 8 +#define USBNC_ADP_STATUS_ADP_CNT(x) (((uint32_t)(((uint32_t)(x))<<USBNC_ADP_STATUS_ADP_CNT_SHIFT))&USBNC_ADP_STATUS_ADP_CNT_MASK) +#define USBNC_ADP_STATUS_ADP_SNS_INT_MASK 0x4000000u +#define USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT 26 +#define USBNC_ADP_STATUS_ADP_PRB_INT_MASK 0x8000000u +#define USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT 27 + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x30B10000u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +#define USBNC1_BASE_PTR (USBNC1) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x30B20000u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +#define USBNC2_BASE_PTR (USBNC2) +/** Peripheral USBNC3 base address */ +#define USBNC3_BASE (0x30B30000u) +/** Peripheral USBNC3 base pointer */ +#define USBNC3 ((USBNC_Type *)USBNC3_BASE) +#define USBNC3_BASE_PTR (USBNC3) +/** Array initializer of USBNC peripheral base adresses */ +#define USBNC_BASE_ADDRS { USBNC1_BASE, USBNC2_BASE, USBNC3_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { USBNC1, USBNC2, USBNC3 } + +/* ---------------------------------------------------------------------------- + -- USBNC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Accessor_Macros USBNC - Register accessor macros + * @{ + */ + + +/* USBNC - Register instance definitions */ +/* USBNC1 */ +#define USBNC1_USB_x_CTRL1 USBNC_USB_x_CTRL1_REG(USBNC1_BASE_PTR) +#define USBNC1_USB_x_CTRL2 USBNC_USB_x_CTRL2_REG(USBNC1_BASE_PTR) +#define USBNC1_USB_x_PHY_CTL2 USBNC_USB_x_PHY_CTL2_REG(USBNC1_BASE_PTR) +#define USBNC1_USB_x_PHY_STS USBNC_USB_x_PHY_STS_REG(USBNC1_BASE_PTR) +#define USBNC1_ADP_CFG1 USBNC_ADP_CFG1_REG(USBNC1_BASE_PTR) +#define USBNC1_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC1_BASE_PTR) +#define USBNC1_ADP_STATUS USBNC_ADP_STATUS_REG(USBNC1_BASE_PTR) +/* USBNC2 */ +#define USBNC2_USB_x_CTRL1 USBNC_USB_x_CTRL1_REG(USBNC2_BASE_PTR) +#define USBNC2_USB_x_CTRL2 USBNC_USB_x_CTRL2_REG(USBNC2_BASE_PTR) +#define USBNC2_USB_x_PHY_CTL2 USBNC_USB_x_PHY_CTL2_REG(USBNC2_BASE_PTR) +#define USBNC2_USB_x_PHY_STS USBNC_USB_x_PHY_STS_REG(USBNC2_BASE_PTR) +#define USBNC2_ADP_CFG1 USBNC_ADP_CFG1_REG(USBNC2_BASE_PTR) +#define USBNC2_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC2_BASE_PTR) +#define USBNC2_ADP_STATUS USBNC_ADP_STATUS_REG(USBNC2_BASE_PTR) +/* USBNC3 */ +#define USBNC3_USB_x_CTRL1 USBNC_USB_x_CTRL1_REG(USBNC3_BASE_PTR) +#define USBNC3_USB_x_CTRL2 USBNC_USB_x_CTRL2_REG(USBNC3_BASE_PTR) +#define USBNC3_USB_x_PHY_CTL2 USBNC_USB_x_PHY_CTL2_REG(USBNC3_BASE_PTR) +#define USBNC3_USB_x_PHY_STS USBNC_USB_x_PHY_STS_REG(USBNC3_BASE_PTR) +#define USBNC3_ADP_CFG1 USBNC_ADP_CFG1_REG(USBNC3_BASE_PTR) +#define USBNC3_ADP_CFG2 USBNC_ADP_CFG2_REG(USBNC3_BASE_PTR) +#define USBNC3_ADP_STATUS USBNC_ADP_STATUS_REG(USBNC3_BASE_PTR) + +/*! + * @} + */ /* end of group USBNC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group USBNC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUG; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type, *USBPHY_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- USBPHY - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros + * @{ + */ + + +/* USBPHY - Register accessors */ +#define USBPHY_PWD_REG(base) ((base)->PWD) +#define USBPHY_PWD_SET_REG(base) ((base)->PWD_SET) +#define USBPHY_PWD_CLR_REG(base) ((base)->PWD_CLR) +#define USBPHY_PWD_TOG_REG(base) ((base)->PWD_TOG) +#define USBPHY_TX_REG(base) ((base)->TX) +#define USBPHY_TX_SET_REG(base) ((base)->TX_SET) +#define USBPHY_TX_CLR_REG(base) ((base)->TX_CLR) +#define USBPHY_TX_TOG_REG(base) ((base)->TX_TOG) +#define USBPHY_RX_REG(base) ((base)->RX) +#define USBPHY_RX_SET_REG(base) ((base)->RX_SET) +#define USBPHY_RX_CLR_REG(base) ((base)->RX_CLR) +#define USBPHY_RX_TOG_REG(base) ((base)->RX_TOG) +#define USBPHY_CTRL_REG(base) ((base)->CTRL) +#define USBPHY_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define USBPHY_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define USBPHY_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define USBPHY_STATUS_REG(base) ((base)->STATUS) +#define USBPHY_DEBUG_REG(base) ((base)->DEBUG) +#define USBPHY_DEBUG_SET_REG(base) ((base)->DEBUG_SET) +#define USBPHY_DEBUG_CLR_REG(base) ((base)->DEBUG_CLR) +#define USBPHY_DEBUG_TOG_REG(base) ((base)->DEBUG_TOG) +#define USBPHY_DEBUG0_STATUS_REG(base) ((base)->DEBUG0_STATUS) +#define USBPHY_DEBUG1_REG(base) ((base)->DEBUG1) +#define USBPHY_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define USBPHY_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define USBPHY_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) +#define USBPHY_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group USBPHY_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/* PWD Bit Fields */ +#define USBPHY_PWD_RSVD0_MASK 0x3FFu +#define USBPHY_PWD_RSVD0_SHIFT 0 +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD0_SHIFT))&USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK 0x400u +#define USBPHY_PWD_TXPWDFS_SHIFT 10 +#define USBPHY_PWD_TXPWDIBIAS_MASK 0x800u +#define USBPHY_PWD_TXPWDIBIAS_SHIFT 11 +#define USBPHY_PWD_TXPWDV2I_MASK 0x1000u +#define USBPHY_PWD_TXPWDV2I_SHIFT 12 +#define USBPHY_PWD_RSVD1_MASK 0x1E000u +#define USBPHY_PWD_RSVD1_SHIFT 13 +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD1_SHIFT))&USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK 0x20000u +#define USBPHY_PWD_RXPWDENV_SHIFT 17 +#define USBPHY_PWD_RXPWD1PT1_MASK 0x40000u +#define USBPHY_PWD_RXPWD1PT1_SHIFT 18 +#define USBPHY_PWD_RXPWDDIFF_MASK 0x80000u +#define USBPHY_PWD_RXPWDDIFF_SHIFT 19 +#define USBPHY_PWD_RXPWDRX_MASK 0x100000u +#define USBPHY_PWD_RXPWDRX_SHIFT 20 +#define USBPHY_PWD_RSVD2_MASK 0xFFE00000u +#define USBPHY_PWD_RSVD2_SHIFT 21 +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_RSVD2_SHIFT))&USBPHY_PWD_RSVD2_MASK) +/* PWD_SET Bit Fields */ +#define USBPHY_PWD_SET_RSVD0_MASK 0x3FFu +#define USBPHY_PWD_SET_RSVD0_SHIFT 0 +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD0_SHIFT))&USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK 0x400u +#define USBPHY_PWD_SET_TXPWDFS_SHIFT 10 +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK 0x800u +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT 11 +#define USBPHY_PWD_SET_TXPWDV2I_MASK 0x1000u +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT 12 +#define USBPHY_PWD_SET_RSVD1_MASK 0x1E000u +#define USBPHY_PWD_SET_RSVD1_SHIFT 13 +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD1_SHIFT))&USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK 0x20000u +#define USBPHY_PWD_SET_RXPWDENV_SHIFT 17 +#define USBPHY_PWD_SET_RXPWD1PT1_MASK 0x40000u +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT 18 +#define USBPHY_PWD_SET_RXPWDDIFF_MASK 0x80000u +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT 19 +#define USBPHY_PWD_SET_RXPWDRX_MASK 0x100000u +#define USBPHY_PWD_SET_RXPWDRX_SHIFT 20 +#define USBPHY_PWD_SET_RSVD2_MASK 0xFFE00000u +#define USBPHY_PWD_SET_RSVD2_SHIFT 21 +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_SET_RSVD2_SHIFT))&USBPHY_PWD_SET_RSVD2_MASK) +/* PWD_CLR Bit Fields */ +#define USBPHY_PWD_CLR_RSVD0_MASK 0x3FFu +#define USBPHY_PWD_CLR_RSVD0_SHIFT 0 +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD0_SHIFT))&USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK 0x400u +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT 10 +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK 0x800u +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT 11 +#define USBPHY_PWD_CLR_TXPWDV2I_MASK 0x1000u +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT 12 +#define USBPHY_PWD_CLR_RSVD1_MASK 0x1E000u +#define USBPHY_PWD_CLR_RSVD1_SHIFT 13 +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD1_SHIFT))&USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK 0x20000u +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT 17 +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK 0x40000u +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT 18 +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK 0x80000u +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT 19 +#define USBPHY_PWD_CLR_RXPWDRX_MASK 0x100000u +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT 20 +#define USBPHY_PWD_CLR_RSVD2_MASK 0xFFE00000u +#define USBPHY_PWD_CLR_RSVD2_SHIFT 21 +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_CLR_RSVD2_SHIFT))&USBPHY_PWD_CLR_RSVD2_MASK) +/* PWD_TOG Bit Fields */ +#define USBPHY_PWD_TOG_RSVD0_MASK 0x3FFu +#define USBPHY_PWD_TOG_RSVD0_SHIFT 0 +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD0_SHIFT))&USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK 0x400u +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT 10 +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK 0x800u +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT 11 +#define USBPHY_PWD_TOG_TXPWDV2I_MASK 0x1000u +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT 12 +#define USBPHY_PWD_TOG_RSVD1_MASK 0x1E000u +#define USBPHY_PWD_TOG_RSVD1_SHIFT 13 +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD1_SHIFT))&USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK 0x20000u +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT 17 +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK 0x40000u +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT 18 +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK 0x80000u +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT 19 +#define USBPHY_PWD_TOG_RXPWDRX_MASK 0x100000u +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT 20 +#define USBPHY_PWD_TOG_RSVD2_MASK 0xFFE00000u +#define USBPHY_PWD_TOG_RSVD2_SHIFT 21 +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_PWD_TOG_RSVD2_SHIFT))&USBPHY_PWD_TOG_RSVD2_MASK) +/* TX Bit Fields */ +#define USBPHY_TX_D_CAL_MASK 0xFu +#define USBPHY_TX_D_CAL_SHIFT 0 +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_D_CAL_SHIFT))&USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK 0xF0u +#define USBPHY_TX_RSVD0_SHIFT 4 +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD0_SHIFT))&USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK 0xF00u +#define USBPHY_TX_TXCAL45DN_SHIFT 8 +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DN_SHIFT))&USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK 0xF000u +#define USBPHY_TX_RSVD1_SHIFT 12 +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD1_SHIFT))&USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK 0xF0000u +#define USBPHY_TX_TXCAL45DP_SHIFT 16 +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TXCAL45DP_SHIFT))&USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK 0x3F00000u +#define USBPHY_TX_RSVD2_SHIFT 20 +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD2_SHIFT))&USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK 0x1C000000u +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT 26 +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK 0xE0000000u +#define USBPHY_TX_RSVD5_SHIFT 29 +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_RSVD5_SHIFT))&USBPHY_TX_RSVD5_MASK) +/* TX_SET Bit Fields */ +#define USBPHY_TX_SET_D_CAL_MASK 0xFu +#define USBPHY_TX_SET_D_CAL_SHIFT 0 +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_D_CAL_SHIFT))&USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK 0xF0u +#define USBPHY_TX_SET_RSVD0_SHIFT 4 +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD0_SHIFT))&USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK 0xF00u +#define USBPHY_TX_SET_TXCAL45DN_SHIFT 8 +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DN_SHIFT))&USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK 0xF000u +#define USBPHY_TX_SET_RSVD1_SHIFT 12 +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD1_SHIFT))&USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK 0xF0000u +#define USBPHY_TX_SET_TXCAL45DP_SHIFT 16 +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_TXCAL45DP_SHIFT))&USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK 0x3F00000u +#define USBPHY_TX_SET_RSVD2_SHIFT 20 +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD2_SHIFT))&USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK 0x1C000000u +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT 26 +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK 0xE0000000u +#define USBPHY_TX_SET_RSVD5_SHIFT 29 +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_SET_RSVD5_SHIFT))&USBPHY_TX_SET_RSVD5_MASK) +/* TX_CLR Bit Fields */ +#define USBPHY_TX_CLR_D_CAL_MASK 0xFu +#define USBPHY_TX_CLR_D_CAL_SHIFT 0 +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_D_CAL_SHIFT))&USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK 0xF0u +#define USBPHY_TX_CLR_RSVD0_SHIFT 4 +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD0_SHIFT))&USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK 0xF00u +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT 8 +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DN_SHIFT))&USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK 0xF000u +#define USBPHY_TX_CLR_RSVD1_SHIFT 12 +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD1_SHIFT))&USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK 0xF0000u +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT 16 +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_TXCAL45DP_SHIFT))&USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK 0x3F00000u +#define USBPHY_TX_CLR_RSVD2_SHIFT 20 +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD2_SHIFT))&USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK 0x1C000000u +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT 26 +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK 0xE0000000u +#define USBPHY_TX_CLR_RSVD5_SHIFT 29 +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_CLR_RSVD5_SHIFT))&USBPHY_TX_CLR_RSVD5_MASK) +/* TX_TOG Bit Fields */ +#define USBPHY_TX_TOG_D_CAL_MASK 0xFu +#define USBPHY_TX_TOG_D_CAL_SHIFT 0 +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_D_CAL_SHIFT))&USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK 0xF0u +#define USBPHY_TX_TOG_RSVD0_SHIFT 4 +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD0_SHIFT))&USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK 0xF00u +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT 8 +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DN_SHIFT))&USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK 0xF000u +#define USBPHY_TX_TOG_RSVD1_SHIFT 12 +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD1_SHIFT))&USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK 0xF0000u +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT 16 +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_TXCAL45DP_SHIFT))&USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK 0x3F00000u +#define USBPHY_TX_TOG_RSVD2_SHIFT 20 +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD2_SHIFT))&USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK 0x1C000000u +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT 26 +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT))&USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK 0xE0000000u +#define USBPHY_TX_TOG_RSVD5_SHIFT 29 +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_TX_TOG_RSVD5_SHIFT))&USBPHY_TX_TOG_RSVD5_MASK) +/* RX Bit Fields */ +#define USBPHY_RX_ENVADJ_MASK 0x7u +#define USBPHY_RX_ENVADJ_SHIFT 0 +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_ENVADJ_SHIFT))&USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK 0x8u +#define USBPHY_RX_RSVD0_SHIFT 3 +#define USBPHY_RX_DISCONADJ_MASK 0x70u +#define USBPHY_RX_DISCONADJ_SHIFT 4 +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_DISCONADJ_SHIFT))&USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK 0x3FFF80u +#define USBPHY_RX_RSVD1_SHIFT 7 +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD1_SHIFT))&USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK 0x400000u +#define USBPHY_RX_RXDBYPASS_SHIFT 22 +#define USBPHY_RX_RSVD2_MASK 0xFF800000u +#define USBPHY_RX_RSVD2_SHIFT 23 +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_RSVD2_SHIFT))&USBPHY_RX_RSVD2_MASK) +/* RX_SET Bit Fields */ +#define USBPHY_RX_SET_ENVADJ_MASK 0x7u +#define USBPHY_RX_SET_ENVADJ_SHIFT 0 +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_ENVADJ_SHIFT))&USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK 0x8u +#define USBPHY_RX_SET_RSVD0_SHIFT 3 +#define USBPHY_RX_SET_DISCONADJ_MASK 0x70u +#define USBPHY_RX_SET_DISCONADJ_SHIFT 4 +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_DISCONADJ_SHIFT))&USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK 0x3FFF80u +#define USBPHY_RX_SET_RSVD1_SHIFT 7 +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD1_SHIFT))&USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK 0x400000u +#define USBPHY_RX_SET_RXDBYPASS_SHIFT 22 +#define USBPHY_RX_SET_RSVD2_MASK 0xFF800000u +#define USBPHY_RX_SET_RSVD2_SHIFT 23 +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_SET_RSVD2_SHIFT))&USBPHY_RX_SET_RSVD2_MASK) +/* RX_CLR Bit Fields */ +#define USBPHY_RX_CLR_ENVADJ_MASK 0x7u +#define USBPHY_RX_CLR_ENVADJ_SHIFT 0 +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_ENVADJ_SHIFT))&USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK 0x8u +#define USBPHY_RX_CLR_RSVD0_SHIFT 3 +#define USBPHY_RX_CLR_DISCONADJ_MASK 0x70u +#define USBPHY_RX_CLR_DISCONADJ_SHIFT 4 +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_DISCONADJ_SHIFT))&USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK 0x3FFF80u +#define USBPHY_RX_CLR_RSVD1_SHIFT 7 +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD1_SHIFT))&USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK 0x400000u +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT 22 +#define USBPHY_RX_CLR_RSVD2_MASK 0xFF800000u +#define USBPHY_RX_CLR_RSVD2_SHIFT 23 +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_CLR_RSVD2_SHIFT))&USBPHY_RX_CLR_RSVD2_MASK) +/* RX_TOG Bit Fields */ +#define USBPHY_RX_TOG_ENVADJ_MASK 0x7u +#define USBPHY_RX_TOG_ENVADJ_SHIFT 0 +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_ENVADJ_SHIFT))&USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK 0x8u +#define USBPHY_RX_TOG_RSVD0_SHIFT 3 +#define USBPHY_RX_TOG_DISCONADJ_MASK 0x70u +#define USBPHY_RX_TOG_DISCONADJ_SHIFT 4 +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_DISCONADJ_SHIFT))&USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK 0x3FFF80u +#define USBPHY_RX_TOG_RSVD1_SHIFT 7 +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD1_SHIFT))&USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK 0x400000u +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT 22 +#define USBPHY_RX_TOG_RSVD2_MASK 0xFF800000u +#define USBPHY_RX_TOG_RSVD2_SHIFT 23 +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_RX_TOG_RSVD2_SHIFT))&USBPHY_RX_TOG_RSVD2_MASK) +/* CTRL Bit Fields */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK 0x1u +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT 0 +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK 0x2u +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT 1 +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK 0x4u +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT 2 +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK 0x8u +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT 3 +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK 0x10u +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT 4 +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK 0x20u +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT 5 +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK 0x40u +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT 6 +#define USBPHY_CTRL_ENOTGIDDETECT_MASK 0x80u +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT 7 +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK 0x100u +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT 8 +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK 0x200u +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT 9 +#define USBPHY_CTRL_RESUME_IRQ_MASK 0x400u +#define USBPHY_CTRL_RESUME_IRQ_SHIFT 10 +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK 0x800u +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT 11 +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK 0x1000u +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT 12 +#define USBPHY_CTRL_DATA_ON_LRADC_MASK 0x2000u +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT 13 +#define USBPHY_CTRL_ENUTMILEVEL2_MASK 0x4000u +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT 14 +#define USBPHY_CTRL_ENUTMILEVEL3_MASK 0x8000u +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT 15 +#define USBPHY_CTRL_ENIRQWAKEUP_MASK 0x10000u +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT 16 +#define USBPHY_CTRL_WAKEUP_IRQ_MASK 0x20000u +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT 17 +#define USBPHY_CTRL_RSVD0_MASK 0x40000u +#define USBPHY_CTRL_RSVD0_SHIFT 18 +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK 0x80000u +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT 19 +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK 0x100000u +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT 20 +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK 0x200000u +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT 21 +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK 0x400000u +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT 22 +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK 0x800000u +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT 23 +#define USBPHY_CTRL_FSDLL_RST_EN_MASK 0x1000000u +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT 24 +#define USBPHY_CTRL_RSVD1_MASK 0x6000000u +#define USBPHY_CTRL_RSVD1_SHIFT 25 +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_RSVD1_SHIFT))&USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK 0x8000000u +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT 27 +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK 0x10000000u +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT 28 +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK 0x20000000u +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT 29 +#define USBPHY_CTRL_CLKGATE_MASK 0x40000000u +#define USBPHY_CTRL_CLKGATE_SHIFT 30 +#define USBPHY_CTRL_SFTRST_MASK 0x80000000u +#define USBPHY_CTRL_SFTRST_SHIFT 31 +/* CTRL_SET Bit Fields */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK 0x1u +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT 0 +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK 0x2u +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT 1 +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK 0x4u +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT 2 +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK 0x8u +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT 3 +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK 0x10u +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT 4 +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK 0x20u +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT 5 +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK 0x40u +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT 6 +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK 0x80u +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT 7 +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK 0x100u +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT 8 +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK 0x200u +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT 9 +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK 0x400u +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT 10 +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK 0x800u +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT 11 +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK 0x1000u +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT 12 +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK 0x2000u +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT 13 +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK 0x4000u +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT 14 +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK 0x8000u +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT 15 +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK 0x10000u +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT 16 +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK 0x20000u +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT 17 +#define USBPHY_CTRL_SET_RSVD0_MASK 0x40000u +#define USBPHY_CTRL_SET_RSVD0_SHIFT 18 +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK 0x80000u +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT 19 +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK 0x100000u +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT 20 +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK 0x200000u +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT 21 +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK 0x400000u +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT 22 +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK 0x800000u +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT 23 +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK 0x1000000u +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT 24 +#define USBPHY_CTRL_SET_RSVD1_MASK 0x6000000u +#define USBPHY_CTRL_SET_RSVD1_SHIFT 25 +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_SET_RSVD1_SHIFT))&USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK 0x8000000u +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT 27 +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK 0x10000000u +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT 28 +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK 0x20000000u +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT 29 +#define USBPHY_CTRL_SET_CLKGATE_MASK 0x40000000u +#define USBPHY_CTRL_SET_CLKGATE_SHIFT 30 +#define USBPHY_CTRL_SET_SFTRST_MASK 0x80000000u +#define USBPHY_CTRL_SET_SFTRST_SHIFT 31 +/* CTRL_CLR Bit Fields */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK 0x1u +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT 0 +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK 0x2u +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT 1 +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK 0x4u +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT 2 +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK 0x8u +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT 3 +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK 0x10u +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT 4 +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK 0x20u +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT 5 +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK 0x40u +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT 6 +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK 0x80u +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT 7 +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK 0x100u +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT 8 +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK 0x200u +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT 9 +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK 0x400u +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT 10 +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK 0x800u +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT 11 +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK 0x1000u +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT 12 +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK 0x2000u +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT 13 +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK 0x4000u +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT 14 +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK 0x8000u +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT 15 +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK 0x10000u +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT 16 +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK 0x20000u +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT 17 +#define USBPHY_CTRL_CLR_RSVD0_MASK 0x40000u +#define USBPHY_CTRL_CLR_RSVD0_SHIFT 18 +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK 0x80000u +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT 19 +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK 0x100000u +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT 20 +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK 0x200000u +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT 21 +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK 0x400000u +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT 22 +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK 0x800000u +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT 23 +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK 0x1000000u +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT 24 +#define USBPHY_CTRL_CLR_RSVD1_MASK 0x6000000u +#define USBPHY_CTRL_CLR_RSVD1_SHIFT 25 +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_CLR_RSVD1_SHIFT))&USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK 0x8000000u +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT 27 +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK 0x10000000u +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT 28 +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK 0x20000000u +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT 29 +#define USBPHY_CTRL_CLR_CLKGATE_MASK 0x40000000u +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT 30 +#define USBPHY_CTRL_CLR_SFTRST_MASK 0x80000000u +#define USBPHY_CTRL_CLR_SFTRST_SHIFT 31 +/* CTRL_TOG Bit Fields */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK 0x1u +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT 0 +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK 0x2u +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT 1 +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK 0x4u +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT 2 +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK 0x8u +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT 3 +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK 0x10u +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT 4 +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK 0x20u +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT 5 +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK 0x40u +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT 6 +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK 0x80u +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT 7 +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK 0x100u +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT 8 +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK 0x200u +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT 9 +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK 0x400u +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT 10 +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK 0x800u +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT 11 +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK 0x1000u +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT 12 +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK 0x2000u +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT 13 +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK 0x4000u +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT 14 +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK 0x8000u +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT 15 +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK 0x10000u +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT 16 +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK 0x20000u +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT 17 +#define USBPHY_CTRL_TOG_RSVD0_MASK 0x40000u +#define USBPHY_CTRL_TOG_RSVD0_SHIFT 18 +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK 0x80000u +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT 19 +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK 0x100000u +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT 20 +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK 0x200000u +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT 21 +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK 0x400000u +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT 22 +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK 0x800000u +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT 23 +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK 0x1000000u +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT 24 +#define USBPHY_CTRL_TOG_RSVD1_MASK 0x6000000u +#define USBPHY_CTRL_TOG_RSVD1_SHIFT 25 +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_CTRL_TOG_RSVD1_SHIFT))&USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK 0x8000000u +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT 27 +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK 0x10000000u +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT 28 +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK 0x20000000u +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT 29 +#define USBPHY_CTRL_TOG_CLKGATE_MASK 0x40000000u +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT 30 +#define USBPHY_CTRL_TOG_SFTRST_MASK 0x80000000u +#define USBPHY_CTRL_TOG_SFTRST_SHIFT 31 +/* STATUS Bit Fields */ +#define USBPHY_STATUS_RSVD0_MASK 0x7u +#define USBPHY_STATUS_RSVD0_SHIFT 0 +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD0_SHIFT))&USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK 0x8u +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT 3 +#define USBPHY_STATUS_RSVD1_MASK 0x30u +#define USBPHY_STATUS_RSVD1_SHIFT 4 +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD1_SHIFT))&USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK 0x40u +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT 6 +#define USBPHY_STATUS_RSVD2_MASK 0x80u +#define USBPHY_STATUS_RSVD2_SHIFT 7 +#define USBPHY_STATUS_OTGID_STATUS_MASK 0x100u +#define USBPHY_STATUS_OTGID_STATUS_SHIFT 8 +#define USBPHY_STATUS_RSVD3_MASK 0x200u +#define USBPHY_STATUS_RSVD3_SHIFT 9 +#define USBPHY_STATUS_RESUME_STATUS_MASK 0x400u +#define USBPHY_STATUS_RESUME_STATUS_SHIFT 10 +#define USBPHY_STATUS_RSVD4_MASK 0xFFFFF800u +#define USBPHY_STATUS_RSVD4_SHIFT 11 +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_STATUS_RSVD4_SHIFT))&USBPHY_STATUS_RSVD4_MASK) +/* DEBUG Bit Fields */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK 0x1u +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT 0 +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK 0x2u +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT 1 +#define USBPHY_DEBUG_HSTPULLDOWN_MASK 0xCu +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT 2 +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK 0x30u +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT 4 +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK 0xC0u +#define USBPHY_DEBUG_RSVD0_SHIFT 6 +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD0_SHIFT))&USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK 0xF00u +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT 8 +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK 0x1000u +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT 12 +#define USBPHY_DEBUG_RSVD1_MASK 0xE000u +#define USBPHY_DEBUG_RSVD1_SHIFT 13 +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD1_SHIFT))&USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK 0x1F0000u +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT 16 +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK 0xE00000u +#define USBPHY_DEBUG_RSVD2_SHIFT 21 +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD2_SHIFT))&USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK 0x1000000u +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT 24 +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK 0x1E000000u +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT 25 +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK 0x20000000u +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT 29 +#define USBPHY_DEBUG_CLKGATE_MASK 0x40000000u +#define USBPHY_DEBUG_CLKGATE_SHIFT 30 +#define USBPHY_DEBUG_RSVD3_MASK 0x80000000u +#define USBPHY_DEBUG_RSVD3_SHIFT 31 +/* DEBUG_SET Bit Fields */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK 0x1u +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT 0 +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK 0x2u +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT 1 +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK 0xCu +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT 2 +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK 0x30u +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT 4 +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK 0xC0u +#define USBPHY_DEBUG_SET_RSVD0_SHIFT 6 +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD0_SHIFT))&USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK 0xF00u +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT 8 +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK 0x1000u +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT 12 +#define USBPHY_DEBUG_SET_RSVD1_MASK 0xE000u +#define USBPHY_DEBUG_SET_RSVD1_SHIFT 13 +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD1_SHIFT))&USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK 0x1F0000u +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT 16 +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK 0xE00000u +#define USBPHY_DEBUG_SET_RSVD2_SHIFT 21 +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_RSVD2_SHIFT))&USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK 0x1000000u +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT 24 +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK 0x1E000000u +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT 25 +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK 0x20000000u +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT 29 +#define USBPHY_DEBUG_SET_CLKGATE_MASK 0x40000000u +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT 30 +#define USBPHY_DEBUG_SET_RSVD3_MASK 0x80000000u +#define USBPHY_DEBUG_SET_RSVD3_SHIFT 31 +/* DEBUG_CLR Bit Fields */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK 0x1u +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT 0 +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK 0x2u +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT 1 +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK 0xCu +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT 2 +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK 0x30u +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT 4 +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK 0xC0u +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT 6 +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD0_SHIFT))&USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK 0xF00u +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT 8 +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK 0x1000u +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT 12 +#define USBPHY_DEBUG_CLR_RSVD1_MASK 0xE000u +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT 13 +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD1_SHIFT))&USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK 0x1F0000u +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT 16 +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK 0xE00000u +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT 21 +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_RSVD2_SHIFT))&USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK 0x1000000u +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT 24 +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK 0x1E000000u +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT 25 +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK 0x20000000u +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT 29 +#define USBPHY_DEBUG_CLR_CLKGATE_MASK 0x40000000u +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT 30 +#define USBPHY_DEBUG_CLR_RSVD3_MASK 0x80000000u +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT 31 +/* DEBUG_TOG Bit Fields */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK 0x1u +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT 0 +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK 0x2u +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT 1 +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK 0xCu +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT 2 +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK 0x30u +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT 4 +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT))&USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK 0xC0u +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT 6 +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD0_SHIFT))&USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK 0xF00u +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT 8 +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT))&USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK 0x1000u +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT 12 +#define USBPHY_DEBUG_TOG_RSVD1_MASK 0xE000u +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT 13 +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD1_SHIFT))&USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK 0x1F0000u +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT 16 +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK 0xE00000u +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT 21 +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_RSVD2_SHIFT))&USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK 0x1000000u +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT 24 +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK 0x1E000000u +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT 25 +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT))&USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK 0x20000000u +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT 29 +#define USBPHY_DEBUG_TOG_CLKGATE_MASK 0x40000000u +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT 30 +#define USBPHY_DEBUG_TOG_RSVD3_MASK 0x80000000u +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT 31 +/* DEBUG0_STATUS Bit Fields */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK 0xFFFFu +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT 0 +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK 0x3FF0000u +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT 16 +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK 0xFC000000u +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT 26 +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT))&USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/* DEBUG1 Bit Fields */ +#define USBPHY_DEBUG1_RSVD0_MASK 0x1FFFu +#define USBPHY_DEBUG1_RSVD0_SHIFT 0 +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD0_SHIFT))&USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK 0x6000u +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT 13 +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK 0xFFFF8000u +#define USBPHY_DEBUG1_RSVD1_SHIFT 15 +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_RSVD1_SHIFT))&USBPHY_DEBUG1_RSVD1_MASK) +/* DEBUG1_SET Bit Fields */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK 0x1FFFu +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT 0 +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD0_SHIFT))&USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK 0x6000u +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT 13 +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK 0xFFFF8000u +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT 15 +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_SET_RSVD1_SHIFT))&USBPHY_DEBUG1_SET_RSVD1_MASK) +/* DEBUG1_CLR Bit Fields */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK 0x1FFFu +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT 0 +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD0_SHIFT))&USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK 0x6000u +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT 13 +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK 0xFFFF8000u +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT 15 +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_CLR_RSVD1_SHIFT))&USBPHY_DEBUG1_CLR_RSVD1_MASK) +/* DEBUG1_TOG Bit Fields */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK 0x1FFFu +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT 0 +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD0_SHIFT))&USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK 0x6000u +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT 13 +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT))&USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK 0xFFFF8000u +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT 15 +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG1_TOG_RSVD1_SHIFT))&USBPHY_DEBUG1_TOG_RSVD1_MASK) +/* VERSION Bit Fields */ +#define USBPHY_VERSION_STEP_MASK 0xFFFFu +#define USBPHY_VERSION_STEP_SHIFT 0 +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_STEP_SHIFT))&USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK 0xFF0000u +#define USBPHY_VERSION_MINOR_SHIFT 16 +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MINOR_SHIFT))&USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK 0xFF000000u +#define USBPHY_VERSION_MAJOR_SHIFT 24 +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<USBPHY_VERSION_MAJOR_SHIFT))&USBPHY_VERSION_MAJOR_MASK) + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x30361000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +#define USBPHY1_BASE_PTR (USBPHY1) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x30362000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +#define USBPHY2_BASE_PTR (USBPHY2) +/** Array initializer of USBPHY peripheral base adresses */ +#define USBPHY_BASE_ADDRS { USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { USBPHY1, USBPHY2 } + +/* ---------------------------------------------------------------------------- + -- USBPHY - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Accessor_Macros USBPHY - Register accessor macros + * @{ + */ + + +/* USBPHY - Register instance definitions */ +/* USBPHY1 */ +#define USBPHY1_PWD USBPHY_PWD_REG(USBPHY1_BASE_PTR) +#define USBPHY1_PWD_SET USBPHY_PWD_SET_REG(USBPHY1_BASE_PTR) +#define USBPHY1_PWD_CLR USBPHY_PWD_CLR_REG(USBPHY1_BASE_PTR) +#define USBPHY1_PWD_TOG USBPHY_PWD_TOG_REG(USBPHY1_BASE_PTR) +#define USBPHY1_TX USBPHY_TX_REG(USBPHY1_BASE_PTR) +#define USBPHY1_TX_SET USBPHY_TX_SET_REG(USBPHY1_BASE_PTR) +#define USBPHY1_TX_CLR USBPHY_TX_CLR_REG(USBPHY1_BASE_PTR) +#define USBPHY1_TX_TOG USBPHY_TX_TOG_REG(USBPHY1_BASE_PTR) +#define USBPHY1_RX USBPHY_RX_REG(USBPHY1_BASE_PTR) +#define USBPHY1_RX_SET USBPHY_RX_SET_REG(USBPHY1_BASE_PTR) +#define USBPHY1_RX_CLR USBPHY_RX_CLR_REG(USBPHY1_BASE_PTR) +#define USBPHY1_RX_TOG USBPHY_RX_TOG_REG(USBPHY1_BASE_PTR) +#define USBPHY1_CTRL USBPHY_CTRL_REG(USBPHY1_BASE_PTR) +#define USBPHY1_CTRL_SET USBPHY_CTRL_SET_REG(USBPHY1_BASE_PTR) +#define USBPHY1_CTRL_CLR USBPHY_CTRL_CLR_REG(USBPHY1_BASE_PTR) +#define USBPHY1_CTRL_TOG USBPHY_CTRL_TOG_REG(USBPHY1_BASE_PTR) +#define USBPHY1_STATUS USBPHY_STATUS_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG USBPHY_DEBUG_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG_SET USBPHY_DEBUG_SET_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG_CLR USBPHY_DEBUG_CLR_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG_TOG USBPHY_DEBUG_TOG_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG0_STATUS USBPHY_DEBUG0_STATUS_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG1 USBPHY_DEBUG1_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG1_SET USBPHY_DEBUG1_SET_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG1_CLR USBPHY_DEBUG1_CLR_REG(USBPHY1_BASE_PTR) +#define USBPHY1_DEBUG1_TOG USBPHY_DEBUG1_TOG_REG(USBPHY1_BASE_PTR) +#define USBPHY1_VERSION USBPHY_VERSION_REG(USBPHY1_BASE_PTR) +/* USBPHY2 */ +#define USBPHY2_PWD USBPHY_PWD_REG(USBPHY2_BASE_PTR) +#define USBPHY2_PWD_SET USBPHY_PWD_SET_REG(USBPHY2_BASE_PTR) +#define USBPHY2_PWD_CLR USBPHY_PWD_CLR_REG(USBPHY2_BASE_PTR) +#define USBPHY2_PWD_TOG USBPHY_PWD_TOG_REG(USBPHY2_BASE_PTR) +#define USBPHY2_TX USBPHY_TX_REG(USBPHY2_BASE_PTR) +#define USBPHY2_TX_SET USBPHY_TX_SET_REG(USBPHY2_BASE_PTR) +#define USBPHY2_TX_CLR USBPHY_TX_CLR_REG(USBPHY2_BASE_PTR) +#define USBPHY2_TX_TOG USBPHY_TX_TOG_REG(USBPHY2_BASE_PTR) +#define USBPHY2_RX USBPHY_RX_REG(USBPHY2_BASE_PTR) +#define USBPHY2_RX_SET USBPHY_RX_SET_REG(USBPHY2_BASE_PTR) +#define USBPHY2_RX_CLR USBPHY_RX_CLR_REG(USBPHY2_BASE_PTR) +#define USBPHY2_RX_TOG USBPHY_RX_TOG_REG(USBPHY2_BASE_PTR) +#define USBPHY2_CTRL USBPHY_CTRL_REG(USBPHY2_BASE_PTR) +#define USBPHY2_CTRL_SET USBPHY_CTRL_SET_REG(USBPHY2_BASE_PTR) +#define USBPHY2_CTRL_CLR USBPHY_CTRL_CLR_REG(USBPHY2_BASE_PTR) +#define USBPHY2_CTRL_TOG USBPHY_CTRL_TOG_REG(USBPHY2_BASE_PTR) +#define USBPHY2_STATUS USBPHY_STATUS_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG USBPHY_DEBUG_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG_SET USBPHY_DEBUG_SET_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG_CLR USBPHY_DEBUG_CLR_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG_TOG USBPHY_DEBUG_TOG_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG0_STATUS USBPHY_DEBUG0_STATUS_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG1 USBPHY_DEBUG1_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG1_SET USBPHY_DEBUG1_SET_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG1_CLR USBPHY_DEBUG1_CLR_REG(USBPHY2_BASE_PTR) +#define USBPHY2_DEBUG1_TOG USBPHY_DEBUG1_TOG_REG(USBPHY2_BASE_PTR) +#define USBPHY2_VERSION USBPHY_VERSION_REG(USBPHY2_BASE_PTR) + +/*! + * @} + */ /* end of group USBPHY_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group USBPHY_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[416]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB VBUS Detect Register, offset: 0x1A0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB VBUS Detect Register, offset: 0x1A4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB VBUS Detect Register, offset: 0x1A8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB VBUS Detect Register, offset: 0x1AC */ + __IO uint32_t USB1_CHRG_DETECT; /**< USB Charger Detect Register, offset: 0x1B0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB Charger Detect Register, offset: 0x1B4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB Charger Detect Register, offset: 0x1B8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB Charger Detect Register, offset: 0x1BC */ + __I uint32_t USB1_VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, offset: 0x1C0 */ + uint8_t RESERVED_1[12]; + __I uint32_t USB1_CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, offset: 0x1D0 */ + uint8_t RESERVED_2[28]; + __IO uint32_t USB1_MISC; /**< USB Misc Register, offset: 0x1F0 */ + __IO uint32_t USB1_MISC_SET; /**< USB Misc Register, offset: 0x1F4 */ + __IO uint32_t USB1_MISC_CLR; /**< USB Misc Register, offset: 0x1F8 */ + __IO uint32_t USB1_MISC_TOG; /**< USB Misc Register, offset: 0x1FC */ + __IO uint32_t USB2_VBUS_DETECT; /**< USB VBUS Detect Register, offset: 0x200 */ + __IO uint32_t USB2_VBUS_DETECT_SET; /**< USB VBUS Detect Register, offset: 0x204 */ + __IO uint32_t USB2_VBUS_DETECT_CLR; /**< USB VBUS Detect Register, offset: 0x208 */ + __IO uint32_t USB2_VBUS_DETECT_TOG; /**< USB VBUS Detect Register, offset: 0x20C */ + __IO uint32_t USB2_CHRG_DETECT; /**< USB Charger Detect Register, offset: 0x210 */ + __IO uint32_t USB2_CHRG_DETECT_SET; /**< USB Charger Detect Register, offset: 0x214 */ + __IO uint32_t USB2_CHRG_DETECT_CLR; /**< USB Charger Detect Register, offset: 0x218 */ + __IO uint32_t USB2_CHRG_DETECT_TOG; /**< USB Charger Detect Register, offset: 0x21C */ + __I uint32_t USB2_VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, offset: 0x220 */ + uint8_t RESERVED_3[12]; + __I uint32_t USB2_CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, offset: 0x230 */ + uint8_t RESERVED_4[28]; + __IO uint32_t USB2_MISC; /**< USB Misc Register, offset: 0x250 */ + __IO uint32_t USB2_MISC_SET; /**< USB Misc Register, offset: 0x254 */ + __IO uint32_t USB2_MISC_CLR; /**< USB Misc Register, offset: 0x258 */ + __IO uint32_t USB2_MISC_TOG; /**< USB Misc Register, offset: 0x25C */ + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ +} USB_ANALOG_Type, *USB_ANALOG_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros + * @{ + */ + + +/* USB_ANALOG - Register accessors */ +#define USB_ANALOG_USB1_VBUS_DETECT_REG(base) ((base)->USB1_VBUS_DETECT) +#define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET) +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR) +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG) +#define USB_ANALOG_USB1_CHRG_DETECT_REG(base) ((base)->USB1_CHRG_DETECT) +#define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET) +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR) +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG) +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT) +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT) +#define USB_ANALOG_USB1_MISC_REG(base) ((base)->USB1_MISC) +#define USB_ANALOG_USB1_MISC_SET_REG(base) ((base)->USB1_MISC_SET) +#define USB_ANALOG_USB1_MISC_CLR_REG(base) ((base)->USB1_MISC_CLR) +#define USB_ANALOG_USB1_MISC_TOG_REG(base) ((base)->USB1_MISC_TOG) +#define USB_ANALOG_USB2_VBUS_DETECT_REG(base) ((base)->USB2_VBUS_DETECT) +#define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET) +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR) +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG) +#define USB_ANALOG_USB2_CHRG_DETECT_REG(base) ((base)->USB2_CHRG_DETECT) +#define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET) +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR) +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG) +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT) +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT) +#define USB_ANALOG_USB2_MISC_REG(base) ((base)->USB2_MISC) +#define USB_ANALOG_USB2_MISC_SET_REG(base) ((base)->USB2_MISC_SET) +#define USB_ANALOG_USB2_MISC_CLR_REG(base) ((base)->USB2_MISC_CLR) +#define USB_ANALOG_USB2_MISC_TOG_REG(base) ((base)->USB2_MISC_TOG) +#define USB_ANALOG_DIGPROG_REG(base) ((base)->DIGPROG) + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/* USB1_VBUS_DETECT Bit Fields */ +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB1_VBUS_DETECT_CHARGE_VBUS_SHIFT 27 +/* USB1_VBUS_DETECT_SET Bit Fields */ +#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB1_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27 +/* USB1_VBUS_DETECT_CLR Bit Fields */ +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27 +/* USB1_VBUS_DETECT_TOG Bit Fields */ +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27 +/* USB1_CHRG_DETECT Bit Fields */ +#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB1_CHRG_DETECT_EN_B_MASK 0x100000u +#define USB_ANALOG_USB1_CHRG_DETECT_EN_B_SHIFT 20 +/* USB1_CHRG_DETECT_SET Bit Fields */ +#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_MASK 0x100000u +#define USB_ANALOG_USB1_CHRG_DETECT_SET_EN_B_SHIFT 20 +/* USB1_CHRG_DETECT_CLR Bit Fields */ +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_MASK 0x100000u +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_EN_B_SHIFT 20 +/* USB1_CHRG_DETECT_TOG Bit Fields */ +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_MASK 0x100000u +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_EN_B_SHIFT 20 +/* USB1_VBUS_DETECT_STAT Bit Fields */ +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_MASK 0x1u +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_SESSEND_SHIFT 0 +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_MASK 0x2u +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_BVALID_SHIFT 1 +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_MASK 0x4u +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_AVALID_SHIFT 2 +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3 +/* USB1_CHRG_DETECT_STAT Bit Fields */ +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0 +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1 +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DM_STATE_SHIFT 2 +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_DP_STATE_SHIFT 3 +/* USB1_MISC Bit Fields */ +#define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB1_MISC_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB1_MISC_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB1_MISC_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB1_MISC_EN_CLK_UTMI_SHIFT 30 +/* USB1_MISC_SET Bit Fields */ +#define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB1_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB1_MISC_SET_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB1_MISC_SET_EN_CLK_UTMI_SHIFT 30 +/* USB1_MISC_CLR Bit Fields */ +#define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB1_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB1_MISC_CLR_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB1_MISC_CLR_EN_CLK_UTMI_SHIFT 30 +/* USB1_MISC_TOG Bit Fields */ +#define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB1_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB1_MISC_TOG_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB1_MISC_TOG_EN_CLK_UTMI_SHIFT 30 +/* USB2_VBUS_DETECT Bit Fields */ +#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB2_VBUS_DETECT_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB2_VBUS_DETECT_CHARGE_VBUS_SHIFT 27 +/* USB2_VBUS_DETECT_SET Bit Fields */ +#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB2_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB2_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB2_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT 27 +/* USB2_VBUS_DETECT_CLR Bit Fields */ +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT 27 +/* USB2_VBUS_DETECT_TOG Bit Fields */ +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT))&USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK 0x100000u +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT 20 +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK 0x4000000u +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT 26 +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_MASK 0x8000000u +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT 27 +/* USB2_CHRG_DETECT Bit Fields */ +#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB2_CHRG_DETECT_EN_B_MASK 0x100000u +#define USB_ANALOG_USB2_CHRG_DETECT_EN_B_SHIFT 20 +/* USB2_CHRG_DETECT_SET Bit Fields */ +#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB2_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_MASK 0x100000u +#define USB_ANALOG_USB2_CHRG_DETECT_SET_EN_B_SHIFT 20 +/* USB2_CHRG_DETECT_CLR Bit Fields */ +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_MASK 0x100000u +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_EN_B_SHIFT 20 +/* USB2_CHRG_DETECT_TOG Bit Fields */ +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_MASK 0x40000u +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT 18 +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_MASK 0x80000u +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT 19 +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_MASK 0x100000u +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_EN_B_SHIFT 20 +/* USB2_VBUS_DETECT_STAT Bit Fields */ +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_MASK 0x1u +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_SESSEND_SHIFT 0 +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_MASK 0x2u +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_BVALID_SHIFT 1 +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_MASK 0x4u +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_AVALID_SHIFT 2 +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_MASK 0x8u +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_VBUS_VALID_SHIFT 3 +/* USB2_CHRG_DETECT_STAT Bit Fields */ +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_MASK 0x1u +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT 0 +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_MASK 0x2u +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT 1 +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_MASK 0x4u +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DM_STATE_SHIFT 2 +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_MASK 0x8u +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_DP_STATE_SHIFT 3 +/* USB2_MISC Bit Fields */ +#define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB2_MISC_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB2_MISC_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB2_MISC_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB2_MISC_EN_CLK_UTMI_SHIFT 30 +/* USB2_MISC_SET Bit Fields */ +#define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB2_MISC_SET_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB2_MISC_SET_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB2_MISC_SET_EN_CLK_UTMI_SHIFT 30 +/* USB2_MISC_CLR Bit Fields */ +#define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB2_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB2_MISC_CLR_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB2_MISC_CLR_EN_CLK_UTMI_SHIFT 30 +/* USB2_MISC_TOG Bit Fields */ +#define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_MASK 0x1u +#define USB_ANALOG_USB2_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT 0 +#define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_MASK 0x2u +#define USB_ANALOG_USB2_MISC_TOG_EN_DEGLITCH_SHIFT 1 +#define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_MASK 0x40000000u +#define USB_ANALOG_USB2_MISC_TOG_EN_CLK_UTMI_SHIFT 30 +/* DIGPROG Bit Fields */ +#define USB_ANALOG_DIGPROG_MINOR_MASK 0xFFu +#define USB_ANALOG_DIGPROG_MINOR_SHIFT 0 +#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MINOR_SHIFT))&USB_ANALOG_DIGPROG_MINOR_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK 0xFF00u +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT 8 +#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK 0xFF0000u +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT 16 +#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x))<<USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT))&USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x30360000u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +#define USB_ANALOG_BASE_PTR (USB_ANALOG) +/** Array initializer of USB_ANALOG peripheral base adresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Accessor_Macros USB_ANALOG - Register accessor macros + * @{ + */ + + +/* USB_ANALOG - Register instance definitions */ +/* USB_ANALOG */ +#define USB_ANALOG_USB1_VBUS_DETECT USB_ANALOG_USB1_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_VBUS_DETECT_SET USB_ANALOG_USB1_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_VBUS_DETECT_CLR USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_VBUS_DETECT_TOG USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_CHRG_DETECT USB_ANALOG_USB1_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_CHRG_DETECT_SET USB_ANALOG_USB1_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_CHRG_DETECT_CLR USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_CHRG_DETECT_TOG USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_VBUS_DETECT_STAT USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_CHRG_DETECT_STAT USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_MISC USB_ANALOG_USB1_MISC_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_MISC_SET USB_ANALOG_USB1_MISC_SET_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_MISC_CLR USB_ANALOG_USB1_MISC_CLR_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB1_MISC_TOG USB_ANALOG_USB1_MISC_TOG_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_VBUS_DETECT USB_ANALOG_USB2_VBUS_DETECT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_VBUS_DETECT_SET USB_ANALOG_USB2_VBUS_DETECT_SET_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_VBUS_DETECT_CLR USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_VBUS_DETECT_TOG USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_CHRG_DETECT USB_ANALOG_USB2_CHRG_DETECT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_CHRG_DETECT_SET USB_ANALOG_USB2_CHRG_DETECT_SET_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_CHRG_DETECT_CLR USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_CHRG_DETECT_TOG USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_VBUS_DETECT_STAT USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_CHRG_DETECT_STAT USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_MISC USB_ANALOG_USB2_MISC_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_MISC_SET USB_ANALOG_USB2_MISC_SET_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_MISC_CLR USB_ANALOG_USB2_MISC_CLR_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_USB2_MISC_TOG USB_ANALOG_USB2_MISC_TOG_REG(USB_ANALOG_BASE_PTR) +#define USB_ANALOG_DIGPROG USB_ANALOG_DIGPROG_REG(USB_ANALOG_BASE_PTR) + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type, *WDOG_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- WDOG - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros + * @{ + */ + + +/* WDOG - Register accessors */ +#define WDOG_WCR_REG(base) ((base)->WCR) +#define WDOG_WSR_REG(base) ((base)->WSR) +#define WDOG_WRSR_REG(base) ((base)->WRSR) +#define WDOG_WICR_REG(base) ((base)->WICR) +#define WDOG_WMCR_REG(base) ((base)->WMCR) + +/*! + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* WCR Bit Fields */ +#define WDOG_WCR_WDZST_MASK 0x1u +#define WDOG_WCR_WDZST_SHIFT 0 +#define WDOG_WCR_WDBG_MASK 0x2u +#define WDOG_WCR_WDBG_SHIFT 1 +#define WDOG_WCR_WDE_MASK 0x4u +#define WDOG_WCR_WDE_SHIFT 2 +#define WDOG_WCR_WDT_MASK 0x8u +#define WDOG_WCR_WDT_SHIFT 3 +#define WDOG_WCR_SRS_MASK 0x10u +#define WDOG_WCR_SRS_SHIFT 4 +#define WDOG_WCR_WDA_MASK 0x20u +#define WDOG_WCR_WDA_SHIFT 5 +#define WDOG_WCR_SRE_MASK 0x40u +#define WDOG_WCR_SRE_SHIFT 6 +#define WDOG_WCR_WDW_MASK 0x80u +#define WDOG_WCR_WDW_SHIFT 7 +#define WDOG_WCR_WT_MASK 0xFF00u +#define WDOG_WCR_WT_SHIFT 8 +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WCR_WT_SHIFT))&WDOG_WCR_WT_MASK) +/* WSR Bit Fields */ +#define WDOG_WSR_WSR_MASK 0xFFFFu +#define WDOG_WSR_WSR_SHIFT 0 +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WSR_WSR_SHIFT))&WDOG_WSR_WSR_MASK) +/* WRSR Bit Fields */ +#define WDOG_WRSR_SFTW_MASK 0x1u +#define WDOG_WRSR_SFTW_SHIFT 0 +#define WDOG_WRSR_TOUT_MASK 0x2u +#define WDOG_WRSR_TOUT_SHIFT 1 +#define WDOG_WRSR_POR_MASK 0x10u +#define WDOG_WRSR_POR_SHIFT 4 +/* WICR Bit Fields */ +#define WDOG_WICR_WICT_MASK 0xFFu +#define WDOG_WICR_WICT_SHIFT 0 +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WICR_WICT_SHIFT))&WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK 0x4000u +#define WDOG_WICR_WTIS_SHIFT 14 +#define WDOG_WICR_WIE_MASK 0x8000u +#define WDOG_WICR_WIE_SHIFT 15 +/* WMCR Bit Fields */ +#define WDOG_WMCR_PDE_MASK 0x1u +#define WDOG_WMCR_PDE_SHIFT 0 + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x30280000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +#define WDOG1_BASE_PTR (WDOG1) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x30290000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +#define WDOG2_BASE_PTR (WDOG2) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x302A0000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +#define WDOG3_BASE_PTR (WDOG3) +/** Peripheral WDOG4 base address */ +#define WDOG4_BASE (0x302B0000u) +/** Peripheral WDOG4 base pointer */ +#define WDOG4 ((WDOG_Type *)WDOG4_BASE) +#define WDOG4_BASE_PTR (WDOG4) +/** Array initializer of WDOG peripheral base adresses */ +#define WDOG_BASE_ADDRS { WDOG1_BASE, WDOG2_BASE, WDOG3_BASE, WDOG4_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { WDOG1, WDOG2, WDOG3, WDOG4 } + +/* ---------------------------------------------------------------------------- + -- WDOG - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros + * @{ + */ + + +/* WDOG - Register instance definitions */ +/* WDOG1 */ +#define WDOG1_WCR WDOG_WCR_REG(WDOG1_BASE_PTR) +#define WDOG1_WSR WDOG_WSR_REG(WDOG1_BASE_PTR) +#define WDOG1_WRSR WDOG_WRSR_REG(WDOG1_BASE_PTR) +#define WDOG1_WICR WDOG_WICR_REG(WDOG1_BASE_PTR) +#define WDOG1_WMCR WDOG_WMCR_REG(WDOG1_BASE_PTR) +/* WDOG2 */ +#define WDOG2_WCR WDOG_WCR_REG(WDOG2_BASE_PTR) +#define WDOG2_WSR WDOG_WSR_REG(WDOG2_BASE_PTR) +#define WDOG2_WRSR WDOG_WRSR_REG(WDOG2_BASE_PTR) +#define WDOG2_WICR WDOG_WICR_REG(WDOG2_BASE_PTR) +#define WDOG2_WMCR WDOG_WMCR_REG(WDOG2_BASE_PTR) +/* WDOG3 */ +#define WDOG3_WCR WDOG_WCR_REG(WDOG3_BASE_PTR) +#define WDOG3_WSR WDOG_WSR_REG(WDOG3_BASE_PTR) +#define WDOG3_WRSR WDOG_WRSR_REG(WDOG3_BASE_PTR) +#define WDOG3_WICR WDOG_WICR_REG(WDOG3_BASE_PTR) +#define WDOG3_WMCR WDOG_WMCR_REG(WDOG3_BASE_PTR) +/* WDOG4 */ +#define WDOG4_WCR WDOG_WCR_REG(WDOG4_BASE_PTR) +#define WDOG4_WSR WDOG_WSR_REG(WDOG4_BASE_PTR) +#define WDOG4_WRSR WDOG_WRSR_REG(WDOG4_BASE_PTR) +#define WDOG4_WICR WDOG_WICR_REG(WDOG4_BASE_PTR) +#define WDOG4_WMCR WDOG_WMCR_REG(WDOG4_BASE_PTR) + +/*! + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group WDOG_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer + * @{ + */ + +/** XTALOSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_24M; /**< Anadig 24M Oscillator Control Register, offset: 0x0 */ + __IO uint32_t CTRL_24M_SET; /**< Anadig 24M Oscillator Control Register, offset: 0x4 */ + __IO uint32_t CTRL_24M_CLR; /**< Anadig 24M Oscillator Control Register, offset: 0x8 */ + __IO uint32_t CTRL_24M_TOG; /**< Anadig 24M Oscillator Control Register, offset: 0xC */ + __IO uint32_t RCOSC_CONFIG0; /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x10 */ + __IO uint32_t RCOSC_CONFIG0_SET; /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x14 */ + __IO uint32_t RCOSC_CONFIG0_CLR; /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x18 */ + __IO uint32_t RCOSC_CONFIG0_TOG; /**< Anadig 24MHz RC Osc. config0 Register, offset: 0x1C */ + __IO uint32_t RCOSC_CONFIG1; /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x20 */ + __IO uint32_t RCOSC_CONFIG1_SET; /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x24 */ + __IO uint32_t RCOSC_CONFIG1_CLR; /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x28 */ + __IO uint32_t RCOSC_CONFIG1_TOG; /**< Anadig 24MHz RC Osc. config1 Register, offset: 0x2C */ + __IO uint32_t RCOSC_CONFIG2; /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x30 */ + __IO uint32_t RCOSC_CONFIG2_SET; /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x34 */ + __IO uint32_t RCOSC_CONFIG2_CLR; /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x38 */ + __IO uint32_t RCOSC_CONFIG2_TOG; /**< Anadig 24MHz RC Osc. config2 Register, offset: 0x3C */ + uint8_t RESERVED_0[16]; + __IO uint32_t OSC_32K; /**< 32K Oscillator Control Register, offset: 0x50 */ + __IO uint32_t OSC_32K_SET; /**< 32K Oscillator Control Register, offset: 0x54 */ + __IO uint32_t OSC_32K_CLR; /**< 32K Oscillator Control Register, offset: 0x58 */ + __IO uint32_t OSC_32K_TOG; /**< 32K Oscillator Control Register, offset: 0x5C */ +} XTALOSC_Type, *XTALOSC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- XTALOSC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Register_Accessor_Macros XTALOSC - Register accessor macros + * @{ + */ + + +/* XTALOSC - Register accessors */ +#define XTALOSC_CTRL_24M_REG(base) ((base)->CTRL_24M) +#define XTALOSC_CTRL_24M_SET_REG(base) ((base)->CTRL_24M_SET) +#define XTALOSC_CTRL_24M_CLR_REG(base) ((base)->CTRL_24M_CLR) +#define XTALOSC_CTRL_24M_TOG_REG(base) ((base)->CTRL_24M_TOG) +#define XTALOSC_RCOSC_CONFIG0_REG(base) ((base)->RCOSC_CONFIG0) +#define XTALOSC_RCOSC_CONFIG0_SET_REG(base) ((base)->RCOSC_CONFIG0_SET) +#define XTALOSC_RCOSC_CONFIG0_CLR_REG(base) ((base)->RCOSC_CONFIG0_CLR) +#define XTALOSC_RCOSC_CONFIG0_TOG_REG(base) ((base)->RCOSC_CONFIG0_TOG) +#define XTALOSC_RCOSC_CONFIG1_REG(base) ((base)->RCOSC_CONFIG1) +#define XTALOSC_RCOSC_CONFIG1_SET_REG(base) ((base)->RCOSC_CONFIG1_SET) +#define XTALOSC_RCOSC_CONFIG1_CLR_REG(base) ((base)->RCOSC_CONFIG1_CLR) +#define XTALOSC_RCOSC_CONFIG1_TOG_REG(base) ((base)->RCOSC_CONFIG1_TOG) +#define XTALOSC_RCOSC_CONFIG2_REG(base) ((base)->RCOSC_CONFIG2) +#define XTALOSC_RCOSC_CONFIG2_SET_REG(base) ((base)->RCOSC_CONFIG2_SET) +#define XTALOSC_RCOSC_CONFIG2_CLR_REG(base) ((base)->RCOSC_CONFIG2_CLR) +#define XTALOSC_RCOSC_CONFIG2_TOG_REG(base) ((base)->RCOSC_CONFIG2_TOG) +#define XTALOSC_OSC_32K_REG(base) ((base)->OSC_32K) +#define XTALOSC_OSC_32K_SET_REG(base) ((base)->OSC_32K_SET) +#define XTALOSC_OSC_32K_CLR_REG(base) ((base)->OSC_32K_CLR) +#define XTALOSC_OSC_32K_TOG_REG(base) ((base)->OSC_32K_TOG) + +/*! + * @} + */ /* end of group XTALOSC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks + * @{ + */ + +/* CTRL_24M Bit Fields */ +#define XTALOSC_CTRL_24M_XTAL_24M_PWD_MASK 0x1u +#define XTALOSC_CTRL_24M_XTAL_24M_PWD_SHIFT 0 +#define XTALOSC_CTRL_24M_XTAL_24M_EN_MASK 0x2u +#define XTALOSC_CTRL_24M_XTAL_24M_EN_SHIFT 1 +#define XTALOSC_CTRL_24M_OSC_XTALOK_MASK 0x4u +#define XTALOSC_CTRL_24M_OSC_XTALOK_SHIFT 2 +#define XTALOSC_CTRL_24M_OSC_XTALOK_EN_MASK 0x8u +#define XTALOSC_CTRL_24M_OSC_XTALOK_EN_SHIFT 3 +#define XTALOSC_CTRL_24M_CLKGATE_CTRL_MASK 0x10u +#define XTALOSC_CTRL_24M_CLKGATE_CTRL_SHIFT 4 +#define XTALOSC_CTRL_24M_CLKGATE_DELAY_MASK 0xE0u +#define XTALOSC_CTRL_24M_CLKGATE_DELAY_SHIFT 5 +#define XTALOSC_CTRL_24M_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_CLKGATE_DELAY_MASK) +#define XTALOSC_CTRL_24M_RCOSC_CG_OVERRIDE_MASK 0x100u +#define XTALOSC_CTRL_24M_RCOSC_CG_OVERRIDE_SHIFT 8 +#define XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_MASK 0x600u +#define XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_SHIFT 9 +#define XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC_CTRL_24M_XTALOSC_PWRUP_STAT_MASK 0x800u +#define XTALOSC_CTRL_24M_XTALOSC_PWRUP_STAT_SHIFT 11 +#define XTALOSC_CTRL_24M_OSC_SEL_MASK 0x1000u +#define XTALOSC_CTRL_24M_OSC_SEL_SHIFT 12 +#define XTALOSC_CTRL_24M_RC_OSC_EN_MASK 0x2000u +#define XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT 13 +#define XTALOSC_CTRL_24M_RSVD0_MASK 0x4000u +#define XTALOSC_CTRL_24M_RSVD0_SHIFT 14 +#define XTALOSC_CTRL_24M_XTAL_MISC_MASK 0x7FFF8000u +#define XTALOSC_CTRL_24M_XTAL_MISC_SHIFT 15 +#define XTALOSC_CTRL_24M_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_XTAL_MISC_MASK) +#define XTALOSC_CTRL_24M_RSVD1_MASK 0x80000000u +#define XTALOSC_CTRL_24M_RSVD1_SHIFT 31 +/* CTRL_24M_SET Bit Fields */ +#define XTALOSC_CTRL_24M_SET_XTAL_24M_PWD_MASK 0x1u +#define XTALOSC_CTRL_24M_SET_XTAL_24M_PWD_SHIFT 0 +#define XTALOSC_CTRL_24M_SET_XTAL_24M_EN_MASK 0x2u +#define XTALOSC_CTRL_24M_SET_XTAL_24M_EN_SHIFT 1 +#define XTALOSC_CTRL_24M_SET_OSC_XTALOK_MASK 0x4u +#define XTALOSC_CTRL_24M_SET_OSC_XTALOK_SHIFT 2 +#define XTALOSC_CTRL_24M_SET_OSC_XTALOK_EN_MASK 0x8u +#define XTALOSC_CTRL_24M_SET_OSC_XTALOK_EN_SHIFT 3 +#define XTALOSC_CTRL_24M_SET_CLKGATE_CTRL_MASK 0x10u +#define XTALOSC_CTRL_24M_SET_CLKGATE_CTRL_SHIFT 4 +#define XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_MASK 0xE0u +#define XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_SHIFT 5 +#define XTALOSC_CTRL_24M_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_SET_CLKGATE_DELAY_MASK) +#define XTALOSC_CTRL_24M_SET_RCOSC_CG_OVERRIDE_MASK 0x100u +#define XTALOSC_CTRL_24M_SET_RCOSC_CG_OVERRIDE_SHIFT 8 +#define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_MASK 0x600u +#define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_SHIFT 9 +#define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_STAT_MASK 0x800u +#define XTALOSC_CTRL_24M_SET_XTALOSC_PWRUP_STAT_SHIFT 11 +#define XTALOSC_CTRL_24M_SET_OSC_SEL_MASK 0x1000u +#define XTALOSC_CTRL_24M_SET_OSC_SEL_SHIFT 12 +#define XTALOSC_CTRL_24M_SET_RC_OSC_EN_MASK 0x2000u +#define XTALOSC_CTRL_24M_SET_RC_OSC_EN_SHIFT 13 +#define XTALOSC_CTRL_24M_SET_RSVD0_MASK 0x4000u +#define XTALOSC_CTRL_24M_SET_RSVD0_SHIFT 14 +#define XTALOSC_CTRL_24M_SET_XTAL_MISC_MASK 0x7FFF8000u +#define XTALOSC_CTRL_24M_SET_XTAL_MISC_SHIFT 15 +#define XTALOSC_CTRL_24M_SET_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_SET_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_SET_XTAL_MISC_MASK) +#define XTALOSC_CTRL_24M_SET_RSVD1_MASK 0x80000000u +#define XTALOSC_CTRL_24M_SET_RSVD1_SHIFT 31 +/* CTRL_24M_CLR Bit Fields */ +#define XTALOSC_CTRL_24M_CLR_XTAL_24M_PWD_MASK 0x1u +#define XTALOSC_CTRL_24M_CLR_XTAL_24M_PWD_SHIFT 0 +#define XTALOSC_CTRL_24M_CLR_XTAL_24M_EN_MASK 0x2u +#define XTALOSC_CTRL_24M_CLR_XTAL_24M_EN_SHIFT 1 +#define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_MASK 0x4u +#define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_SHIFT 2 +#define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_EN_MASK 0x8u +#define XTALOSC_CTRL_24M_CLR_OSC_XTALOK_EN_SHIFT 3 +#define XTALOSC_CTRL_24M_CLR_CLKGATE_CTRL_MASK 0x10u +#define XTALOSC_CTRL_24M_CLR_CLKGATE_CTRL_SHIFT 4 +#define XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_MASK 0xE0u +#define XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_SHIFT 5 +#define XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_CLR_CLKGATE_DELAY_MASK) +#define XTALOSC_CTRL_24M_CLR_RCOSC_CG_OVERRIDE_MASK 0x100u +#define XTALOSC_CTRL_24M_CLR_RCOSC_CG_OVERRIDE_SHIFT 8 +#define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_MASK 0x600u +#define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_SHIFT 9 +#define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_STAT_MASK 0x800u +#define XTALOSC_CTRL_24M_CLR_XTALOSC_PWRUP_STAT_SHIFT 11 +#define XTALOSC_CTRL_24M_CLR_OSC_SEL_MASK 0x1000u +#define XTALOSC_CTRL_24M_CLR_OSC_SEL_SHIFT 12 +#define XTALOSC_CTRL_24M_CLR_RC_OSC_EN_MASK 0x2000u +#define XTALOSC_CTRL_24M_CLR_RC_OSC_EN_SHIFT 13 +#define XTALOSC_CTRL_24M_CLR_RSVD0_MASK 0x4000u +#define XTALOSC_CTRL_24M_CLR_RSVD0_SHIFT 14 +#define XTALOSC_CTRL_24M_CLR_XTAL_MISC_MASK 0x7FFF8000u +#define XTALOSC_CTRL_24M_CLR_XTAL_MISC_SHIFT 15 +#define XTALOSC_CTRL_24M_CLR_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_CLR_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_CLR_XTAL_MISC_MASK) +#define XTALOSC_CTRL_24M_CLR_RSVD1_MASK 0x80000000u +#define XTALOSC_CTRL_24M_CLR_RSVD1_SHIFT 31 +/* CTRL_24M_TOG Bit Fields */ +#define XTALOSC_CTRL_24M_TOG_XTAL_24M_PWD_MASK 0x1u +#define XTALOSC_CTRL_24M_TOG_XTAL_24M_PWD_SHIFT 0 +#define XTALOSC_CTRL_24M_TOG_XTAL_24M_EN_MASK 0x2u +#define XTALOSC_CTRL_24M_TOG_XTAL_24M_EN_SHIFT 1 +#define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_MASK 0x4u +#define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_SHIFT 2 +#define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_EN_MASK 0x8u +#define XTALOSC_CTRL_24M_TOG_OSC_XTALOK_EN_SHIFT 3 +#define XTALOSC_CTRL_24M_TOG_CLKGATE_CTRL_MASK 0x10u +#define XTALOSC_CTRL_24M_TOG_CLKGATE_CTRL_SHIFT 4 +#define XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_MASK 0xE0u +#define XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_SHIFT 5 +#define XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_SHIFT))&XTALOSC_CTRL_24M_TOG_CLKGATE_DELAY_MASK) +#define XTALOSC_CTRL_24M_TOG_RCOSC_CG_OVERRIDE_MASK 0x100u +#define XTALOSC_CTRL_24M_TOG_RCOSC_CG_OVERRIDE_SHIFT 8 +#define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_MASK 0x600u +#define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_SHIFT 9 +#define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_SHIFT))&XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_STAT_MASK 0x800u +#define XTALOSC_CTRL_24M_TOG_XTALOSC_PWRUP_STAT_SHIFT 11 +#define XTALOSC_CTRL_24M_TOG_OSC_SEL_MASK 0x1000u +#define XTALOSC_CTRL_24M_TOG_OSC_SEL_SHIFT 12 +#define XTALOSC_CTRL_24M_TOG_RC_OSC_EN_MASK 0x2000u +#define XTALOSC_CTRL_24M_TOG_RC_OSC_EN_SHIFT 13 +#define XTALOSC_CTRL_24M_TOG_RSVD0_MASK 0x4000u +#define XTALOSC_CTRL_24M_TOG_RSVD0_SHIFT 14 +#define XTALOSC_CTRL_24M_TOG_XTAL_MISC_MASK 0x7FFF8000u +#define XTALOSC_CTRL_24M_TOG_XTAL_MISC_SHIFT 15 +#define XTALOSC_CTRL_24M_TOG_XTAL_MISC(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_CTRL_24M_TOG_XTAL_MISC_SHIFT))&XTALOSC_CTRL_24M_TOG_XTAL_MISC_MASK) +#define XTALOSC_CTRL_24M_TOG_RSVD1_MASK 0x80000000u +#define XTALOSC_CTRL_24M_TOG_RSVD1_SHIFT 31 +/* RCOSC_CONFIG0 Bit Fields */ +#define XTALOSC_RCOSC_CONFIG0_TUNE_START_MASK 0x1u +#define XTALOSC_RCOSC_CONFIG0_TUNE_START_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG0_TUNE_ENABLE_MASK 0x2u +#define XTALOSC_RCOSC_CONFIG0_TUNE_ENABLE_SHIFT 1 +#define XTALOSC_RCOSC_CONFIG0_TUNE_BYPASS_MASK 0x4u +#define XTALOSC_RCOSC_CONFIG0_TUNE_BYPASS_SHIFT 2 +#define XTALOSC_RCOSC_CONFIG0_TUNE_INVERT_MASK 0x8u +#define XTALOSC_RCOSC_CONFIG0_TUNE_INVERT_SHIFT 3 +#define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_MASK 0xFF0u +#define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_SHIFT 4 +#define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC_RCOSC_CONFIG0_HYST_PLUS_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG0_HYST_PLUS_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_HYST_MINUS_MASK 0xF0000u +#define XTALOSC_RCOSC_CONFIG0_HYST_MINUS_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_RSVD0_MASK 0xF00000u +#define XTALOSC_RCOSC_CONFIG0_RSVD0_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_MASK 0xFF000000u +#define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/* RCOSC_CONFIG0_SET Bit Fields */ +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_START_MASK 0x1u +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_START_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_ENABLE_MASK 0x2u +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_ENABLE_SHIFT 1 +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_BYPASS_MASK 0x4u +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_BYPASS_SHIFT 2 +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_INVERT_MASK 0x8u +#define XTALOSC_RCOSC_CONFIG0_SET_TUNE_INVERT_SHIFT 3 +#define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_MASK 0xFF0u +#define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_SHIFT 4 +#define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_MASK 0xF0000u +#define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_SET_RSVD0_MASK 0xF00000u +#define XTALOSC_RCOSC_CONFIG0_SET_RSVD0_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK 0xFF000000u +#define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/* RCOSC_CONFIG0_CLR Bit Fields */ +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_START_MASK 0x1u +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_START_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_ENABLE_MASK 0x2u +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_ENABLE_SHIFT 1 +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_BYPASS_MASK 0x4u +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_BYPASS_SHIFT 2 +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_INVERT_MASK 0x8u +#define XTALOSC_RCOSC_CONFIG0_CLR_TUNE_INVERT_SHIFT 3 +#define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_MASK 0xFF0u +#define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT 4 +#define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_MASK 0xF0000u +#define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_MASK 0xF00000u +#define XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK 0xFF000000u +#define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/* RCOSC_CONFIG0_TOG Bit Fields */ +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_START_MASK 0x1u +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_START_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_ENABLE_MASK 0x2u +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_ENABLE_SHIFT 1 +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_BYPASS_MASK 0x4u +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_BYPASS_SHIFT 2 +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_INVERT_MASK 0x8u +#define XTALOSC_RCOSC_CONFIG0_TOG_TUNE_INVERT_SHIFT 3 +#define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_MASK 0xFF0u +#define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT 4 +#define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_MASK 0xF0000u +#define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_MASK 0xF00000u +#define XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK 0xFF000000u +#define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT 24 +#define XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/* RCOSC_CONFIG1 Bit Fields */ +#define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG1_RSVD0_MASK 0xFF000u +#define XTALOSC_RCOSC_CONFIG1_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_MASK 0xFFF00000u +#define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_COUNT_RC_CUR_MASK) +/* RCOSC_CONFIG1_SET Bit Fields */ +#define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG1_SET_RSVD0_MASK 0xFF000u +#define XTALOSC_RCOSC_CONFIG1_SET_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_MASK 0xFFF00000u +#define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/* RCOSC_CONFIG1_CLR Bit Fields */ +#define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_MASK 0xFF000u +#define XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_MASK 0xFFF00000u +#define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/* RCOSC_CONFIG1_TOG Bit Fields */ +#define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_MASK 0xFF000u +#define XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_MASK 0xFFF00000u +#define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT 20 +#define XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT))&XTALOSC_RCOSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/* RCOSC_CONFIG2 Bit Fields */ +#define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG2_RSVD0_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG2_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG2_ENABLE_1M_MASK 0x10000u +#define XTALOSC_RCOSC_CONFIG2_ENABLE_1M_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG2_MUX_1M_MASK 0x20000u +#define XTALOSC_RCOSC_CONFIG2_MUX_1M_SHIFT 17 +#define XTALOSC_RCOSC_CONFIG2_RSVD1_MASK 0x7FFC0000u +#define XTALOSC_RCOSC_CONFIG2_RSVD1_SHIFT 18 +#define XTALOSC_RCOSC_CONFIG2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_RSVD1_MASK) +#define XTALOSC_RCOSC_CONFIG2_CLK_1M_ERR_FL_MASK 0x80000000u +#define XTALOSC_RCOSC_CONFIG2_CLK_1M_ERR_FL_SHIFT 31 +/* RCOSC_CONFIG2_SET Bit Fields */ +#define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG2_SET_RSVD0_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG2_SET_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_SET_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_SET_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG2_SET_ENABLE_1M_MASK 0x10000u +#define XTALOSC_RCOSC_CONFIG2_SET_ENABLE_1M_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG2_SET_MUX_1M_MASK 0x20000u +#define XTALOSC_RCOSC_CONFIG2_SET_MUX_1M_SHIFT 17 +#define XTALOSC_RCOSC_CONFIG2_SET_RSVD1_MASK 0x7FFC0000u +#define XTALOSC_RCOSC_CONFIG2_SET_RSVD1_SHIFT 18 +#define XTALOSC_RCOSC_CONFIG2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_SET_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_SET_RSVD1_MASK) +#define XTALOSC_RCOSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK 0x80000000u +#define XTALOSC_RCOSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT 31 +/* RCOSC_CONFIG2_CLR Bit Fields */ +#define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_CLR_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG2_CLR_ENABLE_1M_MASK 0x10000u +#define XTALOSC_RCOSC_CONFIG2_CLR_ENABLE_1M_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG2_CLR_MUX_1M_MASK 0x20000u +#define XTALOSC_RCOSC_CONFIG2_CLR_MUX_1M_SHIFT 17 +#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_MASK 0x7FFC0000u +#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_SHIFT 18 +#define XTALOSC_RCOSC_CONFIG2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_CLR_RSVD1_MASK) +#define XTALOSC_RCOSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK 0x80000000u +#define XTALOSC_RCOSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT 31 +/* RCOSC_CONFIG2_TOG Bit Fields */ +#define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_MASK 0xFFFu +#define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT 0 +#define XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT))&XTALOSC_RCOSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_MASK 0xF000u +#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_SHIFT 12 +#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_SHIFT))&XTALOSC_RCOSC_CONFIG2_TOG_RSVD0_MASK) +#define XTALOSC_RCOSC_CONFIG2_TOG_ENABLE_1M_MASK 0x10000u +#define XTALOSC_RCOSC_CONFIG2_TOG_ENABLE_1M_SHIFT 16 +#define XTALOSC_RCOSC_CONFIG2_TOG_MUX_1M_MASK 0x20000u +#define XTALOSC_RCOSC_CONFIG2_TOG_MUX_1M_SHIFT 17 +#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_MASK 0x7FFC0000u +#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_SHIFT 18 +#define XTALOSC_RCOSC_CONFIG2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_SHIFT))&XTALOSC_RCOSC_CONFIG2_TOG_RSVD1_MASK) +#define XTALOSC_RCOSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK 0x80000000u +#define XTALOSC_RCOSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT 31 +/* OSC_32K Bit Fields */ +#define XTALOSC_OSC_32K_RTC_XTAL_SOURCE_MASK 0x1u +#define XTALOSC_OSC_32K_RTC_XTAL_SOURCE_SHIFT 0 +#define XTALOSC_OSC_32K_RSVD0_MASK 0xFFFFFFFEu +#define XTALOSC_OSC_32K_RSVD0_SHIFT 1 +#define XTALOSC_OSC_32K_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_RSVD0_SHIFT))&XTALOSC_OSC_32K_RSVD0_MASK) +/* OSC_32K_SET Bit Fields */ +#define XTALOSC_OSC_32K_SET_RTC_XTAL_SOURCE_MASK 0x1u +#define XTALOSC_OSC_32K_SET_RTC_XTAL_SOURCE_SHIFT 0 +#define XTALOSC_OSC_32K_SET_RSVD0_MASK 0xFFFFFFFEu +#define XTALOSC_OSC_32K_SET_RSVD0_SHIFT 1 +#define XTALOSC_OSC_32K_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_SET_RSVD0_SHIFT))&XTALOSC_OSC_32K_SET_RSVD0_MASK) +/* OSC_32K_CLR Bit Fields */ +#define XTALOSC_OSC_32K_CLR_RTC_XTAL_SOURCE_MASK 0x1u +#define XTALOSC_OSC_32K_CLR_RTC_XTAL_SOURCE_SHIFT 0 +#define XTALOSC_OSC_32K_CLR_RSVD0_MASK 0xFFFFFFFEu +#define XTALOSC_OSC_32K_CLR_RSVD0_SHIFT 1 +#define XTALOSC_OSC_32K_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_CLR_RSVD0_SHIFT))&XTALOSC_OSC_32K_CLR_RSVD0_MASK) +/* OSC_32K_TOG Bit Fields */ +#define XTALOSC_OSC_32K_TOG_RTC_XTAL_SOURCE_MASK 0x1u +#define XTALOSC_OSC_32K_TOG_RTC_XTAL_SOURCE_SHIFT 0 +#define XTALOSC_OSC_32K_TOG_RSVD0_MASK 0xFFFFFFFEu +#define XTALOSC_OSC_32K_TOG_RSVD0_SHIFT 1 +#define XTALOSC_OSC_32K_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<XTALOSC_OSC_32K_TOG_RSVD0_SHIFT))&XTALOSC_OSC_32K_TOG_RSVD0_MASK) + +/*! + * @} + */ /* end of group XTALOSC_Register_Masks */ + + +/* XTALOSC - Peripheral instance base addresses */ +/** Peripheral XTALOSC base address */ +#define XTALOSC_BASE (0x30360000u) +/** Peripheral XTALOSC base pointer */ +#define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE) +#define XTALOSC_BASE_PTR (XTALOSC) +/** Array initializer of XTALOSC peripheral base adresses */ +#define XTALOSC_BASE_ADDRS { XTALOSC_BASE } +/** Array initializer of XTALOSC peripheral base pointers */ +#define XTALOSC_BASE_PTRS { XTALOSC } + +/* ---------------------------------------------------------------------------- + -- XTALOSC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Register_Accessor_Macros XTALOSC - Register accessor macros + * @{ + */ + + +/* XTALOSC - Register instance definitions */ +/* XTALOSC */ +#define XTALOSC_CTRL_24M XTALOSC_CTRL_24M_REG(XTALOSC_BASE_PTR) +#define XTALOSC_CTRL_24M_SET XTALOSC_CTRL_24M_SET_REG(XTALOSC_BASE_PTR) +#define XTALOSC_CTRL_24M_CLR XTALOSC_CTRL_24M_CLR_REG(XTALOSC_BASE_PTR) +#define XTALOSC_CTRL_24M_TOG XTALOSC_CTRL_24M_TOG_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG0 XTALOSC_RCOSC_CONFIG0_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG0_SET XTALOSC_RCOSC_CONFIG0_SET_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG0_CLR XTALOSC_RCOSC_CONFIG0_CLR_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG0_TOG XTALOSC_RCOSC_CONFIG0_TOG_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG1 XTALOSC_RCOSC_CONFIG1_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG1_SET XTALOSC_RCOSC_CONFIG1_SET_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG1_CLR XTALOSC_RCOSC_CONFIG1_CLR_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG1_TOG XTALOSC_RCOSC_CONFIG1_TOG_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG2 XTALOSC_RCOSC_CONFIG2_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG2_SET XTALOSC_RCOSC_CONFIG2_SET_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG2_CLR XTALOSC_RCOSC_CONFIG2_CLR_REG(XTALOSC_BASE_PTR) +#define XTALOSC_RCOSC_CONFIG2_TOG XTALOSC_RCOSC_CONFIG2_TOG_REG(XTALOSC_BASE_PTR) +#define XTALOSC_OSC_32K XTALOSC_OSC_32K_REG(XTALOSC_BASE_PTR) +#define XTALOSC_OSC_32K_SET XTALOSC_OSC_32K_SET_REG(XTALOSC_BASE_PTR) +#define XTALOSC_OSC_32K_CLR XTALOSC_OSC_32K_CLR_REG(XTALOSC_BASE_PTR) +#define XTALOSC_OSC_32K_TOG XTALOSC_OSC_32K_TOG_REG(XTALOSC_BASE_PTR) + +/*! + * @} + */ /* end of group XTALOSC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group XTALOSC_Peripheral */ + + +/* ---------------------------------------------------------------------------- + -- uSDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Peripheral_Access_Layer uSDHC Peripheral Access Layer + * @{ + */ + +/** uSDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __I uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[4]; + __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL Control, offset: 0x70 */ + __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL Status, offset: 0x74 */ + uint8_t RESERVED_3[72]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} uSDHC_Type, *uSDHC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- uSDHC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros + * @{ + */ + + +/* uSDHC - Register accessors */ +#define uSDHC_DS_ADDR_REG(base) ((base)->DS_ADDR) +#define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) +#define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) +#define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) +#define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) +#define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) +#define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) +#define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) +#define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) +#define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) +#define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) +#define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) +#define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) +#define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) +#define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) +#define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) +#define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) +#define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) +#define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) +#define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) +#define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) +#define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) +#define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) +#define uSDHC_STROBE_DLL_CTRL_REG(base) ((base)->STROBE_DLL_CTRL) +#define uSDHC_STROBE_DLL_STATUS_REG(base) ((base)->STROBE_DLL_STATUS) +#define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) +#define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) +#define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) +#define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) + +/*! + * @} + */ /* end of group uSDHC_Register_Accessor_Macros */ + + +/* ---------------------------------------------------------------------------- + -- uSDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Register_Masks uSDHC Register Masks + * @{ + */ + +/* DS_ADDR Bit Fields */ +#define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu +#define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 +#define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DS_ADDR_DS_ADDR_SHIFT))&uSDHC_DS_ADDR_DS_ADDR_MASK) +/* BLK_ATT Bit Fields */ +#define uSDHC_BLK_ATT_BLKSIZE_MASK 0x1FFFu +#define uSDHC_BLK_ATT_BLKSIZE_SHIFT 0 +#define uSDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKSIZE_SHIFT))&uSDHC_BLK_ATT_BLKSIZE_MASK) +#define uSDHC_BLK_ATT_BLKCNT_MASK 0xFFFF0000u +#define uSDHC_BLK_ATT_BLKCNT_SHIFT 16 +#define uSDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_BLK_ATT_BLKCNT_SHIFT))&uSDHC_BLK_ATT_BLKCNT_MASK) +/* CMD_ARG Bit Fields */ +#define uSDHC_CMD_ARG_CMDARG_MASK 0xFFFFFFFFu +#define uSDHC_CMD_ARG_CMDARG_SHIFT 0 +#define uSDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_ARG_CMDARG_SHIFT))&uSDHC_CMD_ARG_CMDARG_MASK) +/* CMD_XFR_TYP Bit Fields */ +#define uSDHC_CMD_XFR_TYP_RSPTYP_MASK 0x30000u +#define uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT 16 +#define uSDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_RSPTYP_SHIFT))&uSDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define uSDHC_CMD_XFR_TYP_CCCEN_MASK 0x80000u +#define uSDHC_CMD_XFR_TYP_CCCEN_SHIFT 19 +#define uSDHC_CMD_XFR_TYP_CICEN_MASK 0x100000u +#define uSDHC_CMD_XFR_TYP_CICEN_SHIFT 20 +#define uSDHC_CMD_XFR_TYP_DPSEL_MASK 0x200000u +#define uSDHC_CMD_XFR_TYP_DPSEL_SHIFT 21 +#define uSDHC_CMD_XFR_TYP_CMDTYP_MASK 0xC00000u +#define uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT 22 +#define uSDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDTYP_SHIFT))&uSDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define uSDHC_CMD_XFR_TYP_CMDINX_MASK 0x3F000000u +#define uSDHC_CMD_XFR_TYP_CMDINX_SHIFT 24 +#define uSDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_XFR_TYP_CMDINX_SHIFT))&uSDHC_CMD_XFR_TYP_CMDINX_MASK) +/* CMD_RSP0 Bit Fields */ +#define uSDHC_CMD_RSP0_CMDRSP0_MASK 0xFFFFFFFFu +#define uSDHC_CMD_RSP0_CMDRSP0_SHIFT 0 +#define uSDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP0_CMDRSP0_SHIFT))&uSDHC_CMD_RSP0_CMDRSP0_MASK) +/* CMD_RSP1 Bit Fields */ +#define uSDHC_CMD_RSP1_CMDRSP1_MASK 0xFFFFFFFFu +#define uSDHC_CMD_RSP1_CMDRSP1_SHIFT 0 +#define uSDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP1_CMDRSP1_SHIFT))&uSDHC_CMD_RSP1_CMDRSP1_MASK) +/* CMD_RSP2 Bit Fields */ +#define uSDHC_CMD_RSP2_CMDRSP2_MASK 0xFFFFFFFFu +#define uSDHC_CMD_RSP2_CMDRSP2_SHIFT 0 +#define uSDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP2_CMDRSP2_SHIFT))&uSDHC_CMD_RSP2_CMDRSP2_MASK) +/* CMD_RSP3 Bit Fields */ +#define uSDHC_CMD_RSP3_CMDRSP3_MASK 0xFFFFFFFFu +#define uSDHC_CMD_RSP3_CMDRSP3_SHIFT 0 +#define uSDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CMD_RSP3_CMDRSP3_SHIFT))&uSDHC_CMD_RSP3_CMDRSP3_MASK) +/* DATA_BUFF_ACC_PORT Bit Fields */ +#define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK 0xFFFFFFFFu +#define uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT 0 +#define uSDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT))&uSDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/* PRES_STATE Bit Fields */ +#define uSDHC_PRES_STATE_CIHB_MASK 0x1u +#define uSDHC_PRES_STATE_CIHB_SHIFT 0 +#define uSDHC_PRES_STATE_CDIHB_MASK 0x2u +#define uSDHC_PRES_STATE_CDIHB_SHIFT 1 +#define uSDHC_PRES_STATE_DLA_MASK 0x4u +#define uSDHC_PRES_STATE_DLA_SHIFT 2 +#define uSDHC_PRES_STATE_SDSTB_MASK 0x8u +#define uSDHC_PRES_STATE_SDSTB_SHIFT 3 +#define uSDHC_PRES_STATE_IPGOFF_MASK 0x10u +#define uSDHC_PRES_STATE_IPGOFF_SHIFT 4 +#define uSDHC_PRES_STATE_HCKOFF_MASK 0x20u +#define uSDHC_PRES_STATE_HCKOFF_SHIFT 5 +#define uSDHC_PRES_STATE_PEROFF_MASK 0x40u +#define uSDHC_PRES_STATE_PEROFF_SHIFT 6 +#define uSDHC_PRES_STATE_SDOFF_MASK 0x80u +#define uSDHC_PRES_STATE_SDOFF_SHIFT 7 +#define uSDHC_PRES_STATE_WTA_MASK 0x100u +#define uSDHC_PRES_STATE_WTA_SHIFT 8 +#define uSDHC_PRES_STATE_RTA_MASK 0x200u +#define uSDHC_PRES_STATE_RTA_SHIFT 9 +#define uSDHC_PRES_STATE_BWEN_MASK 0x400u +#define uSDHC_PRES_STATE_BWEN_SHIFT 10 +#define uSDHC_PRES_STATE_BREN_MASK 0x800u +#define uSDHC_PRES_STATE_BREN_SHIFT 11 +#define uSDHC_PRES_STATE_RTR_MASK 0x1000u +#define uSDHC_PRES_STATE_RTR_SHIFT 12 +#define uSDHC_PRES_STATE_TSCD_MASK 0x8000u +#define uSDHC_PRES_STATE_TSCD_SHIFT 15 +#define uSDHC_PRES_STATE_CINST_MASK 0x10000u +#define uSDHC_PRES_STATE_CINST_SHIFT 16 +#define uSDHC_PRES_STATE_CDPL_MASK 0x40000u +#define uSDHC_PRES_STATE_CDPL_SHIFT 18 +#define uSDHC_PRES_STATE_WPSPL_MASK 0x80000u +#define uSDHC_PRES_STATE_WPSPL_SHIFT 19 +#define uSDHC_PRES_STATE_CLSL_MASK 0x800000u +#define uSDHC_PRES_STATE_CLSL_SHIFT 23 +#define uSDHC_PRES_STATE_DLSL_MASK 0xFF000000u +#define uSDHC_PRES_STATE_DLSL_SHIFT 24 +#define uSDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PRES_STATE_DLSL_SHIFT))&uSDHC_PRES_STATE_DLSL_MASK) +/* PROT_CTRL Bit Fields */ +#define uSDHC_PROT_CTRL_LCTL_MASK 0x1u +#define uSDHC_PROT_CTRL_LCTL_SHIFT 0 +#define uSDHC_PROT_CTRL_DTW_MASK 0x6u +#define uSDHC_PROT_CTRL_DTW_SHIFT 1 +#define uSDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DTW_SHIFT))&uSDHC_PROT_CTRL_DTW_MASK) +#define uSDHC_PROT_CTRL_D3CD_MASK 0x8u +#define uSDHC_PROT_CTRL_D3CD_SHIFT 3 +#define uSDHC_PROT_CTRL_EMODE_MASK 0x30u +#define uSDHC_PROT_CTRL_EMODE_SHIFT 4 +#define uSDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_EMODE_SHIFT))&uSDHC_PROT_CTRL_EMODE_MASK) +#define uSDHC_PROT_CTRL_CDTL_MASK 0x40u +#define uSDHC_PROT_CTRL_CDTL_SHIFT 6 +#define uSDHC_PROT_CTRL_CDSS_MASK 0x80u +#define uSDHC_PROT_CTRL_CDSS_SHIFT 7 +#define uSDHC_PROT_CTRL_DMASEL_MASK 0x300u +#define uSDHC_PROT_CTRL_DMASEL_SHIFT 8 +#define uSDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_DMASEL_SHIFT))&uSDHC_PROT_CTRL_DMASEL_MASK) +#define uSDHC_PROT_CTRL_SABGREQ_MASK 0x10000u +#define uSDHC_PROT_CTRL_SABGREQ_SHIFT 16 +#define uSDHC_PROT_CTRL_CREQ_MASK 0x20000u +#define uSDHC_PROT_CTRL_CREQ_SHIFT 17 +#define uSDHC_PROT_CTRL_RWCTL_MASK 0x40000u +#define uSDHC_PROT_CTRL_RWCTL_SHIFT 18 +#define uSDHC_PROT_CTRL_IABG_MASK 0x80000u +#define uSDHC_PROT_CTRL_IABG_SHIFT 19 +#define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK 0x100000u +#define uSDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT 20 +#define uSDHC_PROT_CTRL_WECINT_MASK 0x1000000u +#define uSDHC_PROT_CTRL_WECINT_SHIFT 24 +#define uSDHC_PROT_CTRL_WECINS_MASK 0x2000000u +#define uSDHC_PROT_CTRL_WECINS_SHIFT 25 +#define uSDHC_PROT_CTRL_WECRM_MASK 0x4000000u +#define uSDHC_PROT_CTRL_WECRM_SHIFT 26 +#define uSDHC_PROT_CTRL_BURST_LEN_EN_MASK 0x38000000u +#define uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT 27 +#define uSDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_PROT_CTRL_BURST_LEN_EN_SHIFT))&uSDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK 0x40000000u +#define uSDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT 30 +/* SYS_CTRL Bit Fields */ +#define uSDHC_SYS_CTRL_DVS_MASK 0xF0u +#define uSDHC_SYS_CTRL_DVS_SHIFT 4 +#define uSDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DVS_SHIFT))&uSDHC_SYS_CTRL_DVS_MASK) +#define uSDHC_SYS_CTRL_SDCLKFS_MASK 0xFF00u +#define uSDHC_SYS_CTRL_SDCLKFS_SHIFT 8 +#define uSDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_SDCLKFS_SHIFT))&uSDHC_SYS_CTRL_SDCLKFS_MASK) +#define uSDHC_SYS_CTRL_DTOCV_MASK 0xF0000u +#define uSDHC_SYS_CTRL_DTOCV_SHIFT 16 +#define uSDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_SYS_CTRL_DTOCV_SHIFT))&uSDHC_SYS_CTRL_DTOCV_MASK) +#define uSDHC_SYS_CTRL_IPP_RST_N_MASK 0x800000u +#define uSDHC_SYS_CTRL_IPP_RST_N_SHIFT 23 +#define uSDHC_SYS_CTRL_RSTA_MASK 0x1000000u +#define uSDHC_SYS_CTRL_RSTA_SHIFT 24 +#define uSDHC_SYS_CTRL_RSTC_MASK 0x2000000u +#define uSDHC_SYS_CTRL_RSTC_SHIFT 25 +#define uSDHC_SYS_CTRL_RSTD_MASK 0x4000000u +#define uSDHC_SYS_CTRL_RSTD_SHIFT 26 +#define uSDHC_SYS_CTRL_INITA_MASK 0x8000000u +#define uSDHC_SYS_CTRL_INITA_SHIFT 27 +#define uSDHC_SYS_CTRL_RSTT_MASK 0x10000000u +#define uSDHC_SYS_CTRL_RSTT_SHIFT 28 +/* INT_STATUS Bit Fields */ +#define uSDHC_INT_STATUS_CC_MASK 0x1u +#define uSDHC_INT_STATUS_CC_SHIFT 0 +#define uSDHC_INT_STATUS_TC_MASK 0x2u +#define uSDHC_INT_STATUS_TC_SHIFT 1 +#define uSDHC_INT_STATUS_BGE_MASK 0x4u +#define uSDHC_INT_STATUS_BGE_SHIFT 2 +#define uSDHC_INT_STATUS_DINT_MASK 0x8u +#define uSDHC_INT_STATUS_DINT_SHIFT 3 +#define uSDHC_INT_STATUS_BWR_MASK 0x10u +#define uSDHC_INT_STATUS_BWR_SHIFT 4 +#define uSDHC_INT_STATUS_BRR_MASK 0x20u +#define uSDHC_INT_STATUS_BRR_SHIFT 5 +#define uSDHC_INT_STATUS_CINS_MASK 0x40u +#define uSDHC_INT_STATUS_CINS_SHIFT 6 +#define uSDHC_INT_STATUS_CRM_MASK 0x80u +#define uSDHC_INT_STATUS_CRM_SHIFT 7 +#define uSDHC_INT_STATUS_CINT_MASK 0x100u +#define uSDHC_INT_STATUS_CINT_SHIFT 8 +#define uSDHC_INT_STATUS_RTE_MASK 0x1000u +#define uSDHC_INT_STATUS_RTE_SHIFT 12 +#define uSDHC_INT_STATUS_TP_MASK 0x4000u +#define uSDHC_INT_STATUS_TP_SHIFT 14 +#define uSDHC_INT_STATUS_CTOE_MASK 0x10000u +#define uSDHC_INT_STATUS_CTOE_SHIFT 16 +#define uSDHC_INT_STATUS_CCE_MASK 0x20000u +#define uSDHC_INT_STATUS_CCE_SHIFT 17 +#define uSDHC_INT_STATUS_CEBE_MASK 0x40000u +#define uSDHC_INT_STATUS_CEBE_SHIFT 18 +#define uSDHC_INT_STATUS_CIE_MASK 0x80000u +#define uSDHC_INT_STATUS_CIE_SHIFT 19 +#define uSDHC_INT_STATUS_DTOE_MASK 0x100000u +#define uSDHC_INT_STATUS_DTOE_SHIFT 20 +#define uSDHC_INT_STATUS_DCE_MASK 0x200000u +#define uSDHC_INT_STATUS_DCE_SHIFT 21 +#define uSDHC_INT_STATUS_DEBE_MASK 0x400000u +#define uSDHC_INT_STATUS_DEBE_SHIFT 22 +#define uSDHC_INT_STATUS_AC12E_MASK 0x1000000u +#define uSDHC_INT_STATUS_AC12E_SHIFT 24 +#define uSDHC_INT_STATUS_TNE_MASK 0x4000000u +#define uSDHC_INT_STATUS_TNE_SHIFT 26 +#define uSDHC_INT_STATUS_DMAE_MASK 0x10000000u +#define uSDHC_INT_STATUS_DMAE_SHIFT 28 +/* INT_STATUS_EN Bit Fields */ +#define uSDHC_INT_STATUS_EN_CCSEN_MASK 0x1u +#define uSDHC_INT_STATUS_EN_CCSEN_SHIFT 0 +#define uSDHC_INT_STATUS_EN_TCSEN_MASK 0x2u +#define uSDHC_INT_STATUS_EN_TCSEN_SHIFT 1 +#define uSDHC_INT_STATUS_EN_BGESEN_MASK 0x4u +#define uSDHC_INT_STATUS_EN_BGESEN_SHIFT 2 +#define uSDHC_INT_STATUS_EN_DINTSEN_MASK 0x8u +#define uSDHC_INT_STATUS_EN_DINTSEN_SHIFT 3 +#define uSDHC_INT_STATUS_EN_BWRSEN_MASK 0x10u +#define uSDHC_INT_STATUS_EN_BWRSEN_SHIFT 4 +#define uSDHC_INT_STATUS_EN_BRRSEN_MASK 0x20u +#define uSDHC_INT_STATUS_EN_BRRSEN_SHIFT 5 +#define uSDHC_INT_STATUS_EN_CINSSEN_MASK 0x40u +#define uSDHC_INT_STATUS_EN_CINSSEN_SHIFT 6 +#define uSDHC_INT_STATUS_EN_CRMSEN_MASK 0x80u +#define uSDHC_INT_STATUS_EN_CRMSEN_SHIFT 7 +#define uSDHC_INT_STATUS_EN_CINTSEN_MASK 0x100u +#define uSDHC_INT_STATUS_EN_CINTSEN_SHIFT 8 +#define uSDHC_INT_STATUS_EN_RTESEN_MASK 0x1000u +#define uSDHC_INT_STATUS_EN_RTESEN_SHIFT 12 +#define uSDHC_INT_STATUS_EN_TPSEN_MASK 0x4000u +#define uSDHC_INT_STATUS_EN_TPSEN_SHIFT 14 +#define uSDHC_INT_STATUS_EN_CTOESEN_MASK 0x10000u +#define uSDHC_INT_STATUS_EN_CTOESEN_SHIFT 16 +#define uSDHC_INT_STATUS_EN_CCESEN_MASK 0x20000u +#define uSDHC_INT_STATUS_EN_CCESEN_SHIFT 17 +#define uSDHC_INT_STATUS_EN_CEBESEN_MASK 0x40000u +#define uSDHC_INT_STATUS_EN_CEBESEN_SHIFT 18 +#define uSDHC_INT_STATUS_EN_CIESEN_MASK 0x80000u +#define uSDHC_INT_STATUS_EN_CIESEN_SHIFT 19 +#define uSDHC_INT_STATUS_EN_DTOESEN_MASK 0x100000u +#define uSDHC_INT_STATUS_EN_DTOESEN_SHIFT 20 +#define uSDHC_INT_STATUS_EN_DCESEN_MASK 0x200000u +#define uSDHC_INT_STATUS_EN_DCESEN_SHIFT 21 +#define uSDHC_INT_STATUS_EN_DEBESEN_MASK 0x400000u +#define uSDHC_INT_STATUS_EN_DEBESEN_SHIFT 22 +#define uSDHC_INT_STATUS_EN_AC12ESEN_MASK 0x1000000u +#define uSDHC_INT_STATUS_EN_AC12ESEN_SHIFT 24 +#define uSDHC_INT_STATUS_EN_TNESEN_MASK 0x4000000u +#define uSDHC_INT_STATUS_EN_TNESEN_SHIFT 26 +#define uSDHC_INT_STATUS_EN_DMAESEN_MASK 0x10000000u +#define uSDHC_INT_STATUS_EN_DMAESEN_SHIFT 28 +/* INT_SIGNAL_EN Bit Fields */ +#define uSDHC_INT_SIGNAL_EN_CCIEN_MASK 0x1u +#define uSDHC_INT_SIGNAL_EN_CCIEN_SHIFT 0 +#define uSDHC_INT_SIGNAL_EN_TCIEN_MASK 0x2u +#define uSDHC_INT_SIGNAL_EN_TCIEN_SHIFT 1 +#define uSDHC_INT_SIGNAL_EN_BGEIEN_MASK 0x4u +#define uSDHC_INT_SIGNAL_EN_BGEIEN_SHIFT 2 +#define uSDHC_INT_SIGNAL_EN_DINTIEN_MASK 0x8u +#define uSDHC_INT_SIGNAL_EN_DINTIEN_SHIFT 3 +#define uSDHC_INT_SIGNAL_EN_BWRIEN_MASK 0x10u +#define uSDHC_INT_SIGNAL_EN_BWRIEN_SHIFT 4 +#define uSDHC_INT_SIGNAL_EN_BRRIEN_MASK 0x20u +#define uSDHC_INT_SIGNAL_EN_BRRIEN_SHIFT 5 +#define uSDHC_INT_SIGNAL_EN_CINSIEN_MASK 0x40u +#define uSDHC_INT_SIGNAL_EN_CINSIEN_SHIFT 6 +#define uSDHC_INT_SIGNAL_EN_CRMIEN_MASK 0x80u +#define uSDHC_INT_SIGNAL_EN_CRMIEN_SHIFT 7 +#define uSDHC_INT_SIGNAL_EN_CINTIEN_MASK 0x100u +#define uSDHC_INT_SIGNAL_EN_CINTIEN_SHIFT 8 +#define uSDHC_INT_SIGNAL_EN_RTEIEN_MASK 0x1000u +#define uSDHC_INT_SIGNAL_EN_RTEIEN_SHIFT 12 +#define uSDHC_INT_SIGNAL_EN_TPIEN_MASK 0x4000u +#define uSDHC_INT_SIGNAL_EN_TPIEN_SHIFT 14 +#define uSDHC_INT_SIGNAL_EN_CTOEIEN_MASK 0x10000u +#define uSDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT 16 +#define uSDHC_INT_SIGNAL_EN_CCEIEN_MASK 0x20000u +#define uSDHC_INT_SIGNAL_EN_CCEIEN_SHIFT 17 +#define uSDHC_INT_SIGNAL_EN_CEBEIEN_MASK 0x40000u +#define uSDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT 18 +#define uSDHC_INT_SIGNAL_EN_CIEIEN_MASK 0x80000u +#define uSDHC_INT_SIGNAL_EN_CIEIEN_SHIFT 19 +#define uSDHC_INT_SIGNAL_EN_DTOEIEN_MASK 0x100000u +#define uSDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT 20 +#define uSDHC_INT_SIGNAL_EN_DCEIEN_MASK 0x200000u +#define uSDHC_INT_SIGNAL_EN_DCEIEN_SHIFT 21 +#define uSDHC_INT_SIGNAL_EN_DEBEIEN_MASK 0x400000u +#define uSDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT 22 +#define uSDHC_INT_SIGNAL_EN_AC12EIEN_MASK 0x1000000u +#define uSDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT 24 +#define uSDHC_INT_SIGNAL_EN_TNEIEN_MASK 0x4000000u +#define uSDHC_INT_SIGNAL_EN_TNEIEN_SHIFT 26 +#define uSDHC_INT_SIGNAL_EN_DMAEIEN_MASK 0x10000000u +#define uSDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT 28 +/* AUTOCMD12_ERR_STATUS Bit Fields */ +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK 0x1u +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT 0 +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK 0x2u +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT 1 +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK 0x4u +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT 2 +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK 0x8u +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT 3 +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK 0x10u +#define uSDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT 4 +#define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK 0x80u +#define uSDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT 7 +#define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK 0x400000u +#define uSDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT 22 +#define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK 0x800000u +#define uSDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT 23 +/* HOST_CTRL_CAP Bit Fields */ +#define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK 0x1u +#define uSDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT 0 +#define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK 0x2u +#define uSDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT 1 +#define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK 0x4u +#define uSDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT 2 +#define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK 0xF00u +#define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT 8 +#define uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT))&uSDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK 0x2000u +#define uSDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT 13 +#define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK 0xC000u +#define uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT 14 +#define uSDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT))&uSDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define uSDHC_HOST_CTRL_CAP_MBL_MASK 0x70000u +#define uSDHC_HOST_CTRL_CAP_MBL_SHIFT 16 +#define uSDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_HOST_CTRL_CAP_MBL_SHIFT))&uSDHC_HOST_CTRL_CAP_MBL_MASK) +#define uSDHC_HOST_CTRL_CAP_ADMAS_MASK 0x100000u +#define uSDHC_HOST_CTRL_CAP_ADMAS_SHIFT 20 +#define uSDHC_HOST_CTRL_CAP_HSS_MASK 0x200000u +#define uSDHC_HOST_CTRL_CAP_HSS_SHIFT 21 +#define uSDHC_HOST_CTRL_CAP_DMAS_MASK 0x400000u +#define uSDHC_HOST_CTRL_CAP_DMAS_SHIFT 22 +#define uSDHC_HOST_CTRL_CAP_SRS_MASK 0x800000u +#define uSDHC_HOST_CTRL_CAP_SRS_SHIFT 23 +#define uSDHC_HOST_CTRL_CAP_VS33_MASK 0x1000000u +#define uSDHC_HOST_CTRL_CAP_VS33_SHIFT 24 +#define uSDHC_HOST_CTRL_CAP_VS30_MASK 0x2000000u +#define uSDHC_HOST_CTRL_CAP_VS30_SHIFT 25 +#define uSDHC_HOST_CTRL_CAP_VS18_MASK 0x4000000u +#define uSDHC_HOST_CTRL_CAP_VS18_SHIFT 26 +/* WTMK_LVL Bit Fields */ +#define uSDHC_WTMK_LVL_RD_WML_MASK 0xFFu +#define uSDHC_WTMK_LVL_RD_WML_SHIFT 0 +#define uSDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_WML_SHIFT))&uSDHC_WTMK_LVL_RD_WML_MASK) +#define uSDHC_WTMK_LVL_RD_BRST_LEN_MASK 0x1F00u +#define uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT 8 +#define uSDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_RD_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define uSDHC_WTMK_LVL_WR_WML_MASK 0xFF0000u +#define uSDHC_WTMK_LVL_WR_WML_SHIFT 16 +#define uSDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_WML_SHIFT))&uSDHC_WTMK_LVL_WR_WML_MASK) +#define uSDHC_WTMK_LVL_WR_BRST_LEN_MASK 0x1F000000u +#define uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT 24 +#define uSDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_WTMK_LVL_WR_BRST_LEN_SHIFT))&uSDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/* MIX_CTRL Bit Fields */ +#define uSDHC_MIX_CTRL_DMAEN_MASK 0x1u +#define uSDHC_MIX_CTRL_DMAEN_SHIFT 0 +#define uSDHC_MIX_CTRL_BCEN_MASK 0x2u +#define uSDHC_MIX_CTRL_BCEN_SHIFT 1 +#define uSDHC_MIX_CTRL_AC12EN_MASK 0x4u +#define uSDHC_MIX_CTRL_AC12EN_SHIFT 2 +#define uSDHC_MIX_CTRL_DDR_EN_MASK 0x8u +#define uSDHC_MIX_CTRL_DDR_EN_SHIFT 3 +#define uSDHC_MIX_CTRL_DTDSEL_MASK 0x10u +#define uSDHC_MIX_CTRL_DTDSEL_SHIFT 4 +#define uSDHC_MIX_CTRL_MSBSEL_MASK 0x20u +#define uSDHC_MIX_CTRL_MSBSEL_SHIFT 5 +#define uSDHC_MIX_CTRL_NIBBLE_POS_MASK 0x40u +#define uSDHC_MIX_CTRL_NIBBLE_POS_SHIFT 6 +#define uSDHC_MIX_CTRL_AC23EN_MASK 0x80u +#define uSDHC_MIX_CTRL_AC23EN_SHIFT 7 +#define uSDHC_MIX_CTRL_EXE_TUNE_MASK 0x400000u +#define uSDHC_MIX_CTRL_EXE_TUNE_SHIFT 22 +#define uSDHC_MIX_CTRL_SMP_CLK_SEL_MASK 0x800000u +#define uSDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT 23 +#define uSDHC_MIX_CTRL_AUTO_TUNE_EN_MASK 0x1000000u +#define uSDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT 24 +#define uSDHC_MIX_CTRL_FBCLK_SEL_MASK 0x2000000u +#define uSDHC_MIX_CTRL_FBCLK_SEL_SHIFT 25 +#define uSDHC_MIX_CTRL_HS400_MODE_MASK 0x4000000u +#define uSDHC_MIX_CTRL_HS400_MODE_SHIFT 26 +/* FORCE_EVENT Bit Fields */ +#define uSDHC_FORCE_EVENT_FEVTAC12NE_MASK 0x1u +#define uSDHC_FORCE_EVENT_FEVTAC12NE_SHIFT 0 +#define uSDHC_FORCE_EVENT_FEVTAC12TOE_MASK 0x2u +#define uSDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT 1 +#define uSDHC_FORCE_EVENT_FEVTAC12CE_MASK 0x4u +#define uSDHC_FORCE_EVENT_FEVTAC12CE_SHIFT 2 +#define uSDHC_FORCE_EVENT_FEVTAC12EBE_MASK 0x8u +#define uSDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT 3 +#define uSDHC_FORCE_EVENT_FEVTAC12IE_MASK 0x10u +#define uSDHC_FORCE_EVENT_FEVTAC12IE_SHIFT 4 +#define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK 0x80u +#define uSDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT 7 +#define uSDHC_FORCE_EVENT_FEVTCTOE_MASK 0x10000u +#define uSDHC_FORCE_EVENT_FEVTCTOE_SHIFT 16 +#define uSDHC_FORCE_EVENT_FEVTCCE_MASK 0x20000u +#define uSDHC_FORCE_EVENT_FEVTCCE_SHIFT 17 +#define uSDHC_FORCE_EVENT_FEVTCEBE_MASK 0x40000u +#define uSDHC_FORCE_EVENT_FEVTCEBE_SHIFT 18 +#define uSDHC_FORCE_EVENT_FEVTCIE_MASK 0x80000u +#define uSDHC_FORCE_EVENT_FEVTCIE_SHIFT 19 +#define uSDHC_FORCE_EVENT_FEVTDTOE_MASK 0x100000u +#define uSDHC_FORCE_EVENT_FEVTDTOE_SHIFT 20 +#define uSDHC_FORCE_EVENT_FEVTDCE_MASK 0x200000u +#define uSDHC_FORCE_EVENT_FEVTDCE_SHIFT 21 +#define uSDHC_FORCE_EVENT_FEVTDEBE_MASK 0x400000u +#define uSDHC_FORCE_EVENT_FEVTDEBE_SHIFT 22 +#define uSDHC_FORCE_EVENT_FEVTAC12E_MASK 0x1000000u +#define uSDHC_FORCE_EVENT_FEVTAC12E_SHIFT 24 +#define uSDHC_FORCE_EVENT_FEVTTNE_MASK 0x4000000u +#define uSDHC_FORCE_EVENT_FEVTTNE_SHIFT 26 +#define uSDHC_FORCE_EVENT_FEVTDMAE_MASK 0x10000000u +#define uSDHC_FORCE_EVENT_FEVTDMAE_SHIFT 28 +#define uSDHC_FORCE_EVENT_FEVTCINT_MASK 0x80000000u +#define uSDHC_FORCE_EVENT_FEVTCINT_SHIFT 31 +/* ADMA_ERR_STATUS Bit Fields */ +#define uSDHC_ADMA_ERR_STATUS_ADMAES_MASK 0x3u +#define uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT 0 +#define uSDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_ERR_STATUS_ADMAES_SHIFT))&uSDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define uSDHC_ADMA_ERR_STATUS_ADMALME_MASK 0x4u +#define uSDHC_ADMA_ERR_STATUS_ADMALME_SHIFT 2 +#define uSDHC_ADMA_ERR_STATUS_ADMADCE_MASK 0x8u +#define uSDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT 3 +/* ADMA_SYS_ADDR Bit Fields */ +#define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK 0xFFFFFFFCu +#define uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT 2 +#define uSDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT))&uSDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/* DLL_CTRL Bit Fields */ +#define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK 0x1u +#define uSDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT 0 +#define uSDHC_DLL_CTRL_DLL_CTRL_RESET_MASK 0x2u +#define uSDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT 1 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK 0x78u +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT 3 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK 0x80u +#define uSDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT 7 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT 8 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK 0x70000u +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT 16 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20 +#define uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u +#define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 +#define uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT))&uSDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/* DLL_STATUS Bit Fields */ +#define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK 0x1u +#define uSDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT 0 +#define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK 0x2u +#define uSDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT 1 +#define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK 0x1FCu +#define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT 2 +#define uSDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK 0xFE00u +#define uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT 9 +#define uSDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT))&uSDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/* CLK_TUNE_CTRL_STATUS Bit Fields */ +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK 0xFu +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT 0 +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK 0xF0u +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT 4 +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK 0x7F00u +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT 8 +#define uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK 0x8000u +#define uSDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT 15 +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK 0xF0000u +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT 16 +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK 0xF00000u +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT 20 +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK 0x7F000000u +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT 24 +#define uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT))&uSDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK 0x80000000u +#define uSDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT 31 +/* STROBE_DLL_CTRL Bit Fields */ +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK 0x1u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT 0 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK 0x2u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT 1 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK 0x4u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT 2 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK 0x38u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK 0x40u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT 6 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK 0x80u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT 7 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK 0x100u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT 8 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK 0xFE00u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT 9 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK 0xFF00000u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT 20 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK 0xF0000000u +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT 28 +#define uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT))&uSDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) +/* STROBE_DLL_STATUS Bit Fields */ +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK 0x1u +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT 0 +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK 0x2u +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT 1 +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK 0x1FCu +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT 2 +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT))&uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK 0xFE00u +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT 9 +#define uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT))&uSDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) +/* VEND_SPEC Bit Fields */ +#define uSDHC_VEND_SPEC_EXT_DMA_EN_MASK 0x1u +#define uSDHC_VEND_SPEC_EXT_DMA_EN_SHIFT 0 +#define uSDHC_VEND_SPEC_VSELECT_MASK 0x2u +#define uSDHC_VEND_SPEC_VSELECT_SHIFT 1 +#define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK 0x4u +#define uSDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT 2 +#define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK 0x8u +#define uSDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT 3 +#define uSDHC_VEND_SPEC_DAT3_CD_POL_MASK 0x10u +#define uSDHC_VEND_SPEC_DAT3_CD_POL_SHIFT 4 +#define uSDHC_VEND_SPEC_CD_POL_MASK 0x20u +#define uSDHC_VEND_SPEC_CD_POL_SHIFT 5 +#define uSDHC_VEND_SPEC_WP_POL_MASK 0x40u +#define uSDHC_VEND_SPEC_WP_POL_SHIFT 6 +#define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK 0x80u +#define uSDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT 7 +#define uSDHC_VEND_SPEC_FRC_SDCLK_ON_MASK 0x100u +#define uSDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT 8 +#define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK 0x800u +#define uSDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT 11 +#define uSDHC_VEND_SPEC_HCLK_SOFT_EN_MASK 0x1000u +#define uSDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT 12 +#define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK 0x2000u +#define uSDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT 13 +#define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK 0x4000u +#define uSDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT 14 +#define uSDHC_VEND_SPEC_CRC_CHK_DIS_MASK 0x8000u +#define uSDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT 15 +#define uSDHC_VEND_SPEC_INT_ST_VAL_MASK 0xFF0000u +#define uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT 16 +#define uSDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_VEND_SPEC_INT_ST_VAL_SHIFT))&uSDHC_VEND_SPEC_INT_ST_VAL_MASK) +#define uSDHC_VEND_SPEC_CMD_BYTE_EN_MASK 0x80000000u +#define uSDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT 31 +/* MMC_BOOT Bit Fields */ +#define uSDHC_MMC_BOOT_DTOCV_ACK_MASK 0xFu +#define uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT 0 +#define uSDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_DTOCV_ACK_SHIFT))&uSDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define uSDHC_MMC_BOOT_BOOT_ACK_MASK 0x10u +#define uSDHC_MMC_BOOT_BOOT_ACK_SHIFT 4 +#define uSDHC_MMC_BOOT_BOOT_MODE_MASK 0x20u +#define uSDHC_MMC_BOOT_BOOT_MODE_SHIFT 5 +#define uSDHC_MMC_BOOT_BOOT_EN_MASK 0x40u +#define uSDHC_MMC_BOOT_BOOT_EN_SHIFT 6 +#define uSDHC_MMC_BOOT_AUTO_SABG_EN_MASK 0x80u +#define uSDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT 7 +#define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK 0x100u +#define uSDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT 8 +#define uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK 0xFFFF0000u +#define uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT 16 +#define uSDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT))&uSDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/* VEND_SPEC2 Bit Fields */ +#define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK 0x1u +#define uSDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT 0 +#define uSDHC_VEND_SPEC2_SDR104_OE_DIS_MASK 0x2u +#define uSDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT 1 +#define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK 0x4u +#define uSDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT 2 +#define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK 0x8u +#define uSDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT 3 +#define uSDHC_VEND_SPEC2_TUNING_8bit_EN_MASK 0x10u +#define uSDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT 4 +#define uSDHC_VEND_SPEC2_TUNING_1bit_EN_MASK 0x20u +#define uSDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT 5 +#define uSDHC_VEND_SPEC2_TUNING_CMD_EN_MASK 0x40u +#define uSDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT 6 +#define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK 0x80u +#define uSDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT 7 +#define uSDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK 0x400u +#define uSDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT 10 +#define uSDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK 0x800u +#define uSDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT 11 +/* TUNING_CTRL Bit Fields */ +#define uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK 0xFFu +#define uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT 0 +#define uSDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK 0xFF00u +#define uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT 8 +#define uSDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT))&uSDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define uSDHC_TUNING_CTRL_TUNING_STEP_MASK 0x70000u +#define uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT 16 +#define uSDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_STEP_SHIFT))&uSDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK 0x700000u +#define uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT 20 +#define uSDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x))<<uSDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT))&uSDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define uSDHC_TUNING_CTRL_STD_TUNING_EN_MASK 0x1000000u +#define uSDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT 24 + +/*! + * @} + */ /* end of group uSDHC_Register_Masks */ + + +/* uSDHC - Peripheral instance base addresses */ +/** Peripheral uSDHC1 base address */ +#define uSDHC1_BASE (0x30B40000u) +/** Peripheral uSDHC1 base pointer */ +#define uSDHC1 ((uSDHC_Type *)uSDHC1_BASE) +#define uSDHC1_BASE_PTR (uSDHC1) +/** Peripheral uSDHC2 base address */ +#define uSDHC2_BASE (0x30B50000u) +/** Peripheral uSDHC2 base pointer */ +#define uSDHC2 ((uSDHC_Type *)uSDHC2_BASE) +#define uSDHC2_BASE_PTR (uSDHC2) +/** Peripheral uSDHC3 base address */ +#define uSDHC3_BASE (0x30B60000u) +/** Peripheral uSDHC3 base pointer */ +#define uSDHC3 ((uSDHC_Type *)uSDHC3_BASE) +#define uSDHC3_BASE_PTR (uSDHC3) +/** Array initializer of uSDHC peripheral base adresses */ +#define uSDHC_BASE_ADDRS { uSDHC1_BASE, uSDHC2_BASE, uSDHC3_BASE } +/** Array initializer of uSDHC peripheral base pointers */ +#define uSDHC_BASE_PTRS { uSDHC1, uSDHC2, uSDHC3 } + +/* ---------------------------------------------------------------------------- + -- uSDHC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Register_Accessor_Macros uSDHC - Register accessor macros + * @{ + */ + + +/* uSDHC - Register instance definitions */ +/* uSDHC1 */ +#define uSDHC1_DS_ADDR uSDHC_DS_ADDR_REG(uSDHC1_BASE_PTR) +#define uSDHC1_BLK_ATT uSDHC_BLK_ATT_REG(uSDHC1_BASE_PTR) +#define uSDHC1_CMD_ARG uSDHC_CMD_ARG_REG(uSDHC1_BASE_PTR) +#define uSDHC1_CMD_XFR_TYP uSDHC_CMD_XFR_TYP_REG(uSDHC1_BASE_PTR) +#define uSDHC1_CMD_RSP0 uSDHC_CMD_RSP0_REG(uSDHC1_BASE_PTR) +#define uSDHC1_CMD_RSP1 uSDHC_CMD_RSP1_REG(uSDHC1_BASE_PTR) +#define uSDHC1_CMD_RSP2 uSDHC_CMD_RSP2_REG(uSDHC1_BASE_PTR) +#define uSDHC1_CMD_RSP3 uSDHC_CMD_RSP3_REG(uSDHC1_BASE_PTR) +#define uSDHC1_DATA_BUFF_ACC_PORT uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC1_BASE_PTR) +#define uSDHC1_PRES_STATE uSDHC_PRES_STATE_REG(uSDHC1_BASE_PTR) +#define uSDHC1_PROT_CTRL uSDHC_PROT_CTRL_REG(uSDHC1_BASE_PTR) +#define uSDHC1_SYS_CTRL uSDHC_SYS_CTRL_REG(uSDHC1_BASE_PTR) +#define uSDHC1_INT_STATUS uSDHC_INT_STATUS_REG(uSDHC1_BASE_PTR) +#define uSDHC1_INT_STATUS_EN uSDHC_INT_STATUS_EN_REG(uSDHC1_BASE_PTR) +#define uSDHC1_INT_SIGNAL_EN uSDHC_INT_SIGNAL_EN_REG(uSDHC1_BASE_PTR) +#define uSDHC1_AUTOCMD12_ERR_STATUS uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC1_BASE_PTR) +#define uSDHC1_HOST_CTRL_CAP uSDHC_HOST_CTRL_CAP_REG(uSDHC1_BASE_PTR) +#define uSDHC1_WTMK_LVL uSDHC_WTMK_LVL_REG(uSDHC1_BASE_PTR) +#define uSDHC1_MIX_CTRL uSDHC_MIX_CTRL_REG(uSDHC1_BASE_PTR) +#define uSDHC1_FORCE_EVENT uSDHC_FORCE_EVENT_REG(uSDHC1_BASE_PTR) +#define uSDHC1_ADMA_ERR_STATUS uSDHC_ADMA_ERR_STATUS_REG(uSDHC1_BASE_PTR) +#define uSDHC1_ADMA_SYS_ADDR uSDHC_ADMA_SYS_ADDR_REG(uSDHC1_BASE_PTR) +#define uSDHC1_DLL_CTRL uSDHC_DLL_CTRL_REG(uSDHC1_BASE_PTR) +#define uSDHC1_DLL_STATUS uSDHC_DLL_STATUS_REG(uSDHC1_BASE_PTR) +#define uSDHC1_CLK_TUNE_CTRL_STATUS uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC1_BASE_PTR) +#define uSDHC1_STROBE_DLL_CTRL uSDHC_STROBE_DLL_CTRL_REG(uSDHC1_BASE_PTR) +#define uSDHC1_STROBE_DLL_STATUS uSDHC_STROBE_DLL_STATUS_REG(uSDHC1_BASE_PTR) +#define uSDHC1_VEND_SPEC uSDHC_VEND_SPEC_REG(uSDHC1_BASE_PTR) +#define uSDHC1_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC1_BASE_PTR) +#define uSDHC1_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC1_BASE_PTR) +#define uSDHC1_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC1_BASE_PTR) +/* uSDHC2 */ +#define uSDHC2_DS_ADDR uSDHC_DS_ADDR_REG(uSDHC2_BASE_PTR) +#define uSDHC2_BLK_ATT uSDHC_BLK_ATT_REG(uSDHC2_BASE_PTR) +#define uSDHC2_CMD_ARG uSDHC_CMD_ARG_REG(uSDHC2_BASE_PTR) +#define uSDHC2_CMD_XFR_TYP uSDHC_CMD_XFR_TYP_REG(uSDHC2_BASE_PTR) +#define uSDHC2_CMD_RSP0 uSDHC_CMD_RSP0_REG(uSDHC2_BASE_PTR) +#define uSDHC2_CMD_RSP1 uSDHC_CMD_RSP1_REG(uSDHC2_BASE_PTR) +#define uSDHC2_CMD_RSP2 uSDHC_CMD_RSP2_REG(uSDHC2_BASE_PTR) +#define uSDHC2_CMD_RSP3 uSDHC_CMD_RSP3_REG(uSDHC2_BASE_PTR) +#define uSDHC2_DATA_BUFF_ACC_PORT uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC2_BASE_PTR) +#define uSDHC2_PRES_STATE uSDHC_PRES_STATE_REG(uSDHC2_BASE_PTR) +#define uSDHC2_PROT_CTRL uSDHC_PROT_CTRL_REG(uSDHC2_BASE_PTR) +#define uSDHC2_SYS_CTRL uSDHC_SYS_CTRL_REG(uSDHC2_BASE_PTR) +#define uSDHC2_INT_STATUS uSDHC_INT_STATUS_REG(uSDHC2_BASE_PTR) +#define uSDHC2_INT_STATUS_EN uSDHC_INT_STATUS_EN_REG(uSDHC2_BASE_PTR) +#define uSDHC2_INT_SIGNAL_EN uSDHC_INT_SIGNAL_EN_REG(uSDHC2_BASE_PTR) +#define uSDHC2_AUTOCMD12_ERR_STATUS uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC2_BASE_PTR) +#define uSDHC2_HOST_CTRL_CAP uSDHC_HOST_CTRL_CAP_REG(uSDHC2_BASE_PTR) +#define uSDHC2_WTMK_LVL uSDHC_WTMK_LVL_REG(uSDHC2_BASE_PTR) +#define uSDHC2_MIX_CTRL uSDHC_MIX_CTRL_REG(uSDHC2_BASE_PTR) +#define uSDHC2_FORCE_EVENT uSDHC_FORCE_EVENT_REG(uSDHC2_BASE_PTR) +#define uSDHC2_ADMA_ERR_STATUS uSDHC_ADMA_ERR_STATUS_REG(uSDHC2_BASE_PTR) +#define uSDHC2_ADMA_SYS_ADDR uSDHC_ADMA_SYS_ADDR_REG(uSDHC2_BASE_PTR) +#define uSDHC2_DLL_CTRL uSDHC_DLL_CTRL_REG(uSDHC2_BASE_PTR) +#define uSDHC2_DLL_STATUS uSDHC_DLL_STATUS_REG(uSDHC2_BASE_PTR) +#define uSDHC2_CLK_TUNE_CTRL_STATUS uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC2_BASE_PTR) +#define uSDHC2_STROBE_DLL_CTRL uSDHC_STROBE_DLL_CTRL_REG(uSDHC2_BASE_PTR) +#define uSDHC2_STROBE_DLL_STATUS uSDHC_STROBE_DLL_STATUS_REG(uSDHC2_BASE_PTR) +#define uSDHC2_VEND_SPEC uSDHC_VEND_SPEC_REG(uSDHC2_BASE_PTR) +#define uSDHC2_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC2_BASE_PTR) +#define uSDHC2_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC2_BASE_PTR) +#define uSDHC2_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC2_BASE_PTR) +/* uSDHC3 */ +#define uSDHC3_DS_ADDR uSDHC_DS_ADDR_REG(uSDHC3_BASE_PTR) +#define uSDHC3_BLK_ATT uSDHC_BLK_ATT_REG(uSDHC3_BASE_PTR) +#define uSDHC3_CMD_ARG uSDHC_CMD_ARG_REG(uSDHC3_BASE_PTR) +#define uSDHC3_CMD_XFR_TYP uSDHC_CMD_XFR_TYP_REG(uSDHC3_BASE_PTR) +#define uSDHC3_CMD_RSP0 uSDHC_CMD_RSP0_REG(uSDHC3_BASE_PTR) +#define uSDHC3_CMD_RSP1 uSDHC_CMD_RSP1_REG(uSDHC3_BASE_PTR) +#define uSDHC3_CMD_RSP2 uSDHC_CMD_RSP2_REG(uSDHC3_BASE_PTR) +#define uSDHC3_CMD_RSP3 uSDHC_CMD_RSP3_REG(uSDHC3_BASE_PTR) +#define uSDHC3_DATA_BUFF_ACC_PORT uSDHC_DATA_BUFF_ACC_PORT_REG(uSDHC3_BASE_PTR) +#define uSDHC3_PRES_STATE uSDHC_PRES_STATE_REG(uSDHC3_BASE_PTR) +#define uSDHC3_PROT_CTRL uSDHC_PROT_CTRL_REG(uSDHC3_BASE_PTR) +#define uSDHC3_SYS_CTRL uSDHC_SYS_CTRL_REG(uSDHC3_BASE_PTR) +#define uSDHC3_INT_STATUS uSDHC_INT_STATUS_REG(uSDHC3_BASE_PTR) +#define uSDHC3_INT_STATUS_EN uSDHC_INT_STATUS_EN_REG(uSDHC3_BASE_PTR) +#define uSDHC3_INT_SIGNAL_EN uSDHC_INT_SIGNAL_EN_REG(uSDHC3_BASE_PTR) +#define uSDHC3_AUTOCMD12_ERR_STATUS uSDHC_AUTOCMD12_ERR_STATUS_REG(uSDHC3_BASE_PTR) +#define uSDHC3_HOST_CTRL_CAP uSDHC_HOST_CTRL_CAP_REG(uSDHC3_BASE_PTR) +#define uSDHC3_WTMK_LVL uSDHC_WTMK_LVL_REG(uSDHC3_BASE_PTR) +#define uSDHC3_MIX_CTRL uSDHC_MIX_CTRL_REG(uSDHC3_BASE_PTR) +#define uSDHC3_FORCE_EVENT uSDHC_FORCE_EVENT_REG(uSDHC3_BASE_PTR) +#define uSDHC3_ADMA_ERR_STATUS uSDHC_ADMA_ERR_STATUS_REG(uSDHC3_BASE_PTR) +#define uSDHC3_ADMA_SYS_ADDR uSDHC_ADMA_SYS_ADDR_REG(uSDHC3_BASE_PTR) +#define uSDHC3_DLL_CTRL uSDHC_DLL_CTRL_REG(uSDHC3_BASE_PTR) +#define uSDHC3_DLL_STATUS uSDHC_DLL_STATUS_REG(uSDHC3_BASE_PTR) +#define uSDHC3_CLK_TUNE_CTRL_STATUS uSDHC_CLK_TUNE_CTRL_STATUS_REG(uSDHC3_BASE_PTR) +#define uSDHC3_STROBE_DLL_CTRL uSDHC_STROBE_DLL_CTRL_REG(uSDHC3_BASE_PTR) +#define uSDHC3_STROBE_DLL_STATUS uSDHC_STROBE_DLL_STATUS_REG(uSDHC3_BASE_PTR) +#define uSDHC3_VEND_SPEC uSDHC_VEND_SPEC_REG(uSDHC3_BASE_PTR) +#define uSDHC3_MMC_BOOT uSDHC_MMC_BOOT_REG(uSDHC3_BASE_PTR) +#define uSDHC3_VEND_SPEC2 uSDHC_VEND_SPEC2_REG(uSDHC3_BASE_PTR) +#define uSDHC3_TUNING_CTRL uSDHC_TUNING_CTRL_REG(uSDHC3_BASE_PTR) + +/*! + * @} + */ /* end of group uSDHC_Register_Accessor_Macros */ + + +/*! + * @} + */ /* end of group uSDHC_Peripheral */ + + + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_defines */ + + +/* ---------------------------------------------------------------------------- + -- Backward Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Backward_Compatibility_Symbols Backward Compatibility + * @{ + */ + +/* No backward compatibility issues. */ + +/*! + * @} + */ /* end of group Backward_Compatibility_Symbols */ + + +#else /* #if !defined(MCU_iMX7D) */ + /* There is already included the same memory map. Check if it is compatible (has the same major version) */ + #if (MCU_MEM_MAP_VERSION != 0x0100u) + #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) + #warning There are included two not compatible versions of memory maps. Please check possible differences. + #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ + #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ +#endif /* #if !defined(MCU_iMX7D) */ + +/* iMX7D.h, eof. */ diff --git a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIA.scf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIA.scf new file mode 100755 index 0000000..a94eafb --- /dev/null +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIA.scf @@ -0,0 +1,36 @@ +#! armcc -E --cpu Cortex-M4 + +#define m_text_start 0x60000000 +#define m_text_size 0x7FF0 + +#define m_data_start 0x20000000 +#define m_data_size 0x7FF0 + +#define HEAP_SIZE 0x200 +#define STACK_SIZE 0x400 +#define MY_ALIGN(address, alignment) ((address + (alignment-1)) AND ~(alignment-1)) + + +LR_m_text m_text_start m_text_size +{ + ER_m_text m_text_start m_text_size { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start { ; RW data + .ANY (+RW ) + } + ZI_m_data +0 { ; ZI data + .ANY (+ZI ) + } + + ARM_LIB_HEAP (m_data_start+m_data_size-HEAP_SIZE-STACK_SIZE) EMPTY HEAP_SIZE + { ; Heap region growing up + } + ARM_LIB_STACK (m_data_start+m_data_size) EMPTY -STACK_SIZE + { ; Stack region growing down + } + +} diff --git a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIB.scf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIB.scf new file mode 100755 index 0000000..b7857af --- /dev/null +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_QSPIB.scf @@ -0,0 +1,36 @@ +#! armcc -E --cpu Cortex-M4 + +#define m_text_start 0x68000000 +#define m_text_size 0x7FF0 + +#define m_data_start 0x20000000 +#define m_data_size 0x7FF0 + +#define HEAP_SIZE 0x200 +#define STACK_SIZE 0x400 +#define MY_ALIGN(address, alignment) ((address + (alignment-1)) AND ~(alignment-1)) + + +LR_m_text m_text_start m_text_size +{ + ER_m_text m_text_start m_text_size { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start { ; RW data + .ANY (+RW ) + } + ZI_m_data +0 { ; ZI data + .ANY (+ZI ) + } + + ARM_LIB_HEAP (m_data_start+m_data_size-HEAP_SIZE-STACK_SIZE) EMPTY HEAP_SIZE + { ; Heap region growing up + } + ARM_LIB_STACK (m_data_start+m_data_size) EMPTY -STACK_SIZE + { ; Stack region growing down + } + +} diff --git a/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_tcm.scf b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_tcm.scf new file mode 100755 index 0000000..95a4dda --- /dev/null +++ b/platform/devices/MCIMX7D/linker/arm/MCIMX7D_M4_tcm.scf @@ -0,0 +1,36 @@ +#! armcc -E --cpu Cortex-M4 + +#define m_text_start 0x1FFF8000 +#define m_text_size 0x7FF0 + +#define m_data_start 0x20000000 +#define m_data_size 0x7FF0 + +#define HEAP_SIZE 0x200 +#define STACK_SIZE 0x400 +#define MY_ALIGN(address, alignment) ((address + (alignment-1)) AND ~(alignment-1)) + + +LR_m_text m_text_start m_text_size +{ + ER_m_text m_text_start m_text_size { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start { ; RW data + .ANY (+RW ) + } + ZI_m_data +0 { ; ZI data + .ANY (+ZI ) + } + + ARM_LIB_HEAP (m_data_start+m_data_size-HEAP_SIZE-STACK_SIZE) EMPTY HEAP_SIZE + { ; Heap region growing up + } + ARM_LIB_STACK (m_data_start+m_data_size) EMPTY -STACK_SIZE + { ; Stack region growing down + } + +} diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIA.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIA.ld new file mode 100644 index 0000000..5b5ec1a --- /dev/null +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIA.ld @@ -0,0 +1,167 @@ +/* Entry Point */
+ENTRY(Reset_Handler)
+
+STACK_SIZE = 0x400;
+HEAP_SIZE = 0x200;
+/* Specify the memory areas */
+MEMORY
+{
+ m_text (RX) : ORIGIN = 0x60000000, LENGTH = 0x00007FFF
+
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007FFF
+
+}
+
+SECTIONS
+{
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_text
+
+ __VECTOR_RAM = __VECTOR_TABLE;
+ __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ } > m_data
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+ }
diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIB.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIB.ld new file mode 100644 index 0000000..84dceb5 --- /dev/null +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_QSPIB.ld @@ -0,0 +1,167 @@ +/* Entry Point */
+ENTRY(Reset_Handler)
+
+STACK_SIZE = 0x400;
+HEAP_SIZE = 0x200;
+/* Specify the memory areas */
+MEMORY
+{
+ m_text (RX) : ORIGIN = 0x68000000, LENGTH = 0x00007FFF
+
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007FFF
+
+}
+
+SECTIONS
+{
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_text
+
+ __VECTOR_RAM = __VECTOR_TABLE;
+ __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ } > m_data
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+ }
diff --git a/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_tcm.ld b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_tcm.ld new file mode 100644 index 0000000..5fd3435 --- /dev/null +++ b/platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_tcm.ld @@ -0,0 +1,167 @@ +/* Entry Point */ +ENTRY(Reset_Handler) + +STACK_SIZE = 0x400; +HEAP_SIZE = 0x200; +/* Specify the memory areas */ +MEMORY +{ + m_text (RX) : ORIGIN = 0x1FFF8000, LENGTH = 0x00007FFF + + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00007FFF + +} + +SECTIONS +{ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_text + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + } > m_data + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") + }
\ No newline at end of file diff --git a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIA.icf b/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIA.icf new file mode 100644 index 0000000..f2294ec --- /dev/null +++ b/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIA.icf @@ -0,0 +1,93 @@ +/*
+** ###################################################################
+** Processors: MCIMX7D7DVK10SA
+** MCIMX7D7DVM10SA
+** MCIMX7D3DVK10SA
+** MCIMX7D3EVM10SA
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMX7DRM, Rev.A, February 2015
+** Version: rev. 1.0, 2015-05-19
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright (c) 2015 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x60000000;
+define symbol m_interrupts_end = 0x6000023F;
+
+define symbol m_text_start = 0x60000240;
+define symbol m_text_end = 0x60007FFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x20007FFF;
+
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
diff --git a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIB.icf b/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIB.icf new file mode 100644 index 0000000..cc0930e --- /dev/null +++ b/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_QSPIB.icf @@ -0,0 +1,93 @@ +/*
+** ###################################################################
+** Processors: MCIMX7D7DVK10SA
+** MCIMX7D7DVM10SA
+** MCIMX7D3DVK10SA
+** MCIMX7D3EVM10SA
+**
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: IMX7DRM, Rev.A, February 2015
+** Version: rev. 1.0, 2015-05-19
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright (c) 2015 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** ###################################################################
+*/
+
+define symbol m_interrupts_start = 0x68000000;
+define symbol m_interrupts_end = 0x6800023F;
+
+define symbol m_text_start = 0x68000240;
+define symbol m_text_end = 0x68007FFF;
+
+define symbol m_data_start = 0x20000000;
+define symbol m_data_end = 0x20007FFF;
+
+
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+
+initialize by copy { readwrite, section .textrw };
+do not initialize { section .noinit };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
diff --git a/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_tcm.icf b/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_tcm.icf new file mode 100644 index 0000000..04d9c21 --- /dev/null +++ b/platform/devices/MCIMX7D/linker/iar/MCIMX7D_M4_tcm.icf @@ -0,0 +1,93 @@ +/* +** ################################################################### +** Processors: MCIMX7D7DVK10SA +** MCIMX7D7DVM10SA +** MCIMX7D3DVK10SA +** MCIMX7D3EVM10SA +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMX7DRM, Rev.A, February 2015 +** Version: rev. 1.0, 2015-05-19 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x1FFF8000; +define symbol m_interrupts_end = 0x1FFF823F; + +define symbol m_text_start = 0x1FFF8240; +define symbol m_text_end = 0x1FFFFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x20007FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + diff --git a/platform/devices/MCIMX7D/startup/arm/startup_MCIMX7D_M4.s b/platform/devices/MCIMX7D/startup/arm/startup_MCIMX7D_M4.s new file mode 100644 index 0000000..c367752 --- /dev/null +++ b/platform/devices/MCIMX7D/startup/arm/startup_MCIMX7D_M4.s @@ -0,0 +1,524 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MCIMX7D_M4.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * IMX7D_M4 +; * @version: 0.1 +; * @date: 2015-5-27 +; * @build: b54573 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DefaultISR ;Reserved Interrupt 16 + DCD DefaultISR ;Reserved Interrupt 17 + DCD DefaultISR ;Reserved Interrupt 18 + DCD DefaultISR ;Reserved Interrupt 19 + DCD DefaultISR ;Reserved Interrupt 20 + DCD DefaultISR ;Reserved Interrupt 21 + DCD DefaultISR ;Reserved Interrupt 22 + DCD DefaultISR ;Reserved Interrupt 23 + DCD DefaultISR ;Reserved Interrupt 24 + DCD DefaultISR ;Reserved Interrupt 25 + DCD WDOG3_Handler ;WDOG3 Handler + DCD SEMA4_Handler ;SEMA4_Handler + DCD DefaultISR ;Reserved Interrupt 28 + DCD DefaultISR ;Reserved Interrupt 29 + DCD DefaultISR ;Reserved Interrupt 30 + DCD DefaultISR ;Reserved Interrupt 31 + DCD UART6_Handler ;UART6 Handler + DCD DefaultISR ;Reserved Interrupt 33 + DCD DefaultISR ;Reserved Interrupt 34 + DCD DefaultISR ;Reserved Interrupt 35 + DCD DefaultISR ;Reserved Interrupt 36 + DCD DefaultISR ;Reserved Interrupt 37 + DCD DefaultISR ;Reserved Interrupt 38 + DCD DefaultISR ;Reserved Interrupt 39 + DCD DefaultISR ;Reserved Interrupt 40 + DCD DefaultISR ;Reserved Interrupt 41 + DCD UART1_Handler ;UART1 Handler + DCD UART2_Handler ;UART2 Handler + DCD UART3_Handler ;UART3 Handler + DCD UART4_Handler ;UART4 Handler + DCD UART5_Handler ;UART5 Handler + DCD eCSPI1_Handler ;eCSPI1 Handler + DCD eCSPI2_Handler ;eCSPI2 Handler + DCD eCSPI3_Handler ;eCSPI3 Handler + DCD eCSPI4_Handler ;eCSPI4 Handler + DCD I2C1_Handler ;I2C1 Handler + DCD I2C2_Handler ;I2C2 Handler + DCD I2C3_Handler ;I2C3 Handler + DCD I2C4_Handler ;I2C4 Handler + DCD DefaultISR ;Reserved Interrupt 55 + DCD DefaultISR ;Reserved Interrupt 56 + DCD DefaultISR ;Reserved Interrupt 57 + DCD DefaultISR ;Reserved Interrupt 58 + DCD DefaultISR ;Reserved Interrupt 59 + DCD DefaultISR ;Reserved Interrupt 60 + DCD DefaultISR ;Reserved Interrupt 61 + DCD DefaultISR ;Reserved Interrupt 62 + DCD DefaultISR ;Reserved Interrupt 63 + DCD DefaultISR ;Reserved Interrupt 64 + DCD DefaultISR ;Reserved Interrupt 65 + DCD DefaultISR ;Reserved Interrupt 66 + DCD DefaultISR ;Reserved Interrupt 67 + DCD GPT4_Handler ;GPT4 handler + DCD GPT3_Handler ;GPT3 handler + DCD GPT2_Handler ;GPT2 handler + DCD GPT1_Handler ;GPT1 handler + DCD GPIO1_INT7_Handler ;Active HIGH Interrupt from INT7 from GPIO + DCD GPIO1_INT6_Handler ;Active HIGH Interrupt from INT6 from GPIO + DCD GPIO1_INT5_Handler ;Active HIGH Interrupt from INT5 from GPIO + DCD GPIO1_INT4_Handler ;Active HIGH Interrupt from INT4 from GPIO + DCD GPIO1_INT3_Handler ;Active HIGH Interrupt from INT3 from GPIO + DCD GPIO1_INT2_Handler ;Active HIGH Interrupt from INT2 from GPIO + DCD GPIO1_INT1_Handler ;Active HIGH Interrupt from INT1 from GPIO + DCD GPIO1_INT0_Handler ;Active HIGH Interrupt from INT0 from GPIO + DCD GPIO1_INT15_0_Handler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 + DCD GPIO1_INT31_16_Handler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 + DCD GPIO2_INT15_0_Handler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 + DCD GPIO2_INT31_16_Handler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 + DCD GPIO3_INT15_0_Handler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 + DCD GPIO3_INT31_16_Handler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 + DCD GPIO4_INT15_0_Handler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 + DCD GPIO4_INT31_16_Handler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 + DCD GPIO5_INT15_0_Handler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 + DCD GPIO5_INT31_16_Handler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 + DCD GPIO6_INT15_0_Handler ;Combined interrupt indication for GPIO6 signal 0 throughout 15 + DCD GPIO6_INT31_16_Handler ;Combined interrupt indication for GPIO6 signal 16 throughout 31 + DCD GPIO7_INT15_0_Handler ;Combined interrupt indication for GPIO7 signal 0 throughout 15 + DCD GPIO7_INT31_16_Handler ;Combined interrupt indication for GPIO7 signal 16 throughout 31 + DCD DefaultISR ;Reserved Interrupt 94 + DCD DefaultISR ;Reserved Interrupt 95 + DCD DefaultISR ;Reserved Interrupt 96 + DCD DefaultISR ;Reserved Interrupt 97 + DCD DefaultISR ;Reserved Interrupt 98 + DCD DefaultISR ;Reserved Interrupt 99 + DCD DefaultISR ;Reserved Interrupt 100 + DCD DefaultISR ;Reserved Interrupt 101 + DCD DefaultISR ;Reserved Interrupt 102 + DCD DefaultISR ;Reserved Interrupt 103 + DCD DefaultISR ;Reserved Interrupt 104 + DCD DefaultISR ;Reserved Interrupt 105 + DCD DefaultISR ;Reserved Interrupt 106 + DCD DefaultISR ;Reserved Interrupt 107 + DCD DefaultISR ;Reserved Interrupt 108 + DCD DefaultISR ;Reserved Interrupt 109 + DCD DefaultISR ;Reserved Interrupt 110 + DCD DefaultISR ;Reserved Interrupt 111 + DCD DefaultISR ;Reserved Interrupt 112 + DCD MU_Handler ;MU_Handler + DCD ADC1_Handler ;ADC1 Handler + DCD ADC2_Handler ;ADC2 Handler + DCD DefaultISR ;Reserved Interrupt 116 + DCD DefaultISR ;Reserved Interrupt 117 + DCD DefaultISR ;Reserved Interrupt 118 + DCD DefaultISR ;Reserved Interrupt 119 + DCD DefaultISR ;Reserved Interrupt 120 + DCD DefaultISR ;Reserved Interrupt 121 + DCD DefaultISR ;Reserved Interrupt 122 + DCD DefaultISR ;Reserved Interrupt 123 + DCD DefaultISR ;Reserved Interrupt 124 + DCD DefaultISR ;Reserved Interrupt 125 + DCD FLEXCAN1_Handler ;FLEXCAN1 Handler + DCD FLEXCAN2_Handler ;FLEXCAN2 Handler + DCD DefaultISR ;Reserved Interrupt 128 + DCD DefaultISR ;Reserved Interrupt 129 + DCD DefaultISR ;Reserved Interrupt 130 + DCD DefaultISR ;Reserved Interrupt 131 + DCD DefaultISR ;Reserved Interrupt 132 + DCD DefaultISR ;Reserved Interrupt 133 + DCD DefaultISR ;Reserved Interrupt 134 + DCD DefaultISR ;Reserved Interrupt 135 + DCD DefaultISR ;Reserved Interrupt 136 + DCD DefaultISR ;Reserved Interrupt 137 + DCD DefaultISR ;Reserved Interrupt 138 + DCD DefaultISR ;Reserved Interrupt 139 + DCD DefaultISR ;Reserved Interrupt 140 + DCD DefaultISR ;Reserved Interrupt 141 + DCD UART7_Handler ;UART7 Handler + DCD DefaultISR ;Reserved Interrupt 143 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + + + AREA |.text|, CODE, READONLY +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + CPSID I ; Mask interrupts + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +WDOG3_Handler\ + PROC + EXPORT WDOG3_Handler [WEAK] + B . + ENDP +SEMA4_Handler\ + PROC + EXPORT SEMA4_Handler [WEAK] + B . + ENDP +UART6_Handler\ + PROC + EXPORT UART6_Handler [WEAK] + B . + ENDP +UART1_Handler\ + PROC + EXPORT UART1_Handler [WEAK] + B . + ENDP +UART2_Handler\ + PROC + EXPORT UART2_Handler [WEAK] + B . + ENDP +UART3_Handler\ + PROC + EXPORT UART3_Handler [WEAK] + B . + ENDP +UART4_Handler\ + PROC + EXPORT UART4_Handler [WEAK] + B . + ENDP +UART5_Handler\ + PROC + EXPORT UART5_Handler [WEAK] + B . + ENDP +eCSPI1_Handler\ + PROC + EXPORT eCSPI1_Handler [WEAK] + B . + ENDP +eCSPI2_Handler\ + PROC + EXPORT eCSPI2_Handler [WEAK] + B . + ENDP +eCSPI3_Handler\ + PROC + EXPORT eCSPI3_Handler [WEAK] + B . + ENDP +eCSPI4_Handler\ + PROC + EXPORT eCSPI4_Handler [WEAK] + B . + ENDP +I2C1_Handler\ + PROC + EXPORT I2C1_Handler [WEAK] + B . + ENDP +I2C2_Handler\ + PROC + EXPORT I2C2_Handler [WEAK] + B . + ENDP +I2C3_Handler\ + PROC + EXPORT I2C3_Handler [WEAK] + B . + ENDP +I2C4_Handler\ + PROC + EXPORT I2C4_Handler [WEAK] + B . + ENDP +GPT4_Handler\ + PROC + EXPORT GPT4_Handler [WEAK] + B . + ENDP +GPT3_Handler\ + PROC + EXPORT GPT3_Handler [WEAK] + B . + ENDP +GPT2_Handler\ + PROC + EXPORT GPT2_Handler [WEAK] + B . + ENDP +GPT1_Handler\ + PROC + EXPORT GPT1_Handler [WEAK] + B . + ENDP +GPIO1_INT7_Handler\ + PROC + EXPORT GPIO1_INT7_Handler [WEAK] + B . + ENDP +GPIO1_INT6_Handler\ + PROC + EXPORT GPIO1_INT6_Handler [WEAK] + B . + ENDP +GPIO1_INT5_Handler\ + PROC + EXPORT GPIO1_INT5_Handler [WEAK] + B . + ENDP +GPIO1_INT4_Handler\ + PROC + EXPORT GPIO1_INT4_Handler [WEAK] + B . + ENDP +GPIO1_INT3_Handler\ + PROC + EXPORT GPIO1_INT3_Handler [WEAK] + B . + ENDP +GPIO1_INT2_Handler\ + PROC + EXPORT GPIO1_INT2_Handler [WEAK] + B . + ENDP +GPIO1_INT1_Handler\ + PROC + EXPORT GPIO1_INT1_Handler [WEAK] + B . + ENDP +GPIO1_INT0_Handler\ + PROC + EXPORT GPIO1_INT0_Handler [WEAK] + B . + ENDP +GPIO1_INT15_0_Handler\ + PROC + EXPORT GPIO1_INT15_0_Handler [WEAK] + B . + ENDP +GPIO1_INT31_16_Handler\ + PROC + EXPORT GPIO1_INT31_16_Handler [WEAK] + B . + ENDP +GPIO2_INT15_0_Handler\ + PROC + EXPORT GPIO2_INT15_0_Handler [WEAK] + B . + ENDP +GPIO2_INT31_16_Handler\ + PROC + EXPORT GPIO2_INT31_16_Handler [WEAK] + B . + ENDP +GPIO3_INT15_0_Handler\ + PROC + EXPORT GPIO3_INT15_0_Handler [WEAK] + B . + ENDP +GPIO3_INT31_16_Handler\ + PROC + EXPORT GPIO3_INT31_16_Handler [WEAK] + B . + ENDP +GPIO4_INT15_0_Handler\ + PROC + EXPORT GPIO4_INT15_0_Handler [WEAK] + B . + ENDP +GPIO4_INT31_16_Handler\ + PROC + EXPORT GPIO4_INT31_16_Handler [WEAK] + B . + ENDP +GPIO5_INT15_0_Handler\ + PROC + EXPORT GPIO5_INT15_0_Handler [WEAK] + B . + ENDP +GPIO5_INT31_16_Handler\ + PROC + EXPORT GPIO5_INT31_16_Handler [WEAK] + B . + ENDP +GPIO6_INT15_0_Handler\ + PROC + EXPORT GPIO6_INT15_0_Handler [WEAK] + B . + ENDP +GPIO6_INT31_16_Handler\ + PROC + EXPORT GPIO6_INT31_16_Handler [WEAK] + B . + ENDP +GPIO7_INT15_0_Handler\ + PROC + EXPORT GPIO7_INT15_0_Handler [WEAK] + B . + ENDP +GPIO7_INT31_16_Handler\ + PROC + EXPORT GPIO7_INT31_16_Handler [WEAK] + B . + ENDP +MU_Handler\ + PROC + EXPORT MU_Handler [WEAK] + B . + ENDP +ADC1_Handler\ + PROC + EXPORT ADC1_Handler [WEAK] + B . + ENDP +ADC2_Handler\ + PROC + EXPORT ADC2_Handler [WEAK] + B . + ENDP +FLEXCAN1_Handler\ + PROC + EXPORT FLEXCAN1_Handler [WEAK] + B . + ENDP +FLEXCAN2_Handler\ + PROC + EXPORT FLEXCAN2_Handler [WEAK] + B . + ENDP +UART7_Handler\ + PROC + EXPORT UART7_Handler [WEAK] + B . + ENDP + +Default_Handler\ + PROC + + EXPORT DefaultISR [WEAK] + + +DefaultISR + + B DefaultISR + ENDP + ALIGN + + + END diff --git a/platform/devices/MCIMX7D/startup/gcc/startup_MCIMX7D_M4.S b/platform/devices/MCIMX7D/startup/gcc/startup_MCIMX7D_M4.S new file mode 100644 index 0000000..15965bb --- /dev/null +++ b/platform/devices/MCIMX7D/startup/gcc/startup_MCIMX7D_M4.S @@ -0,0 +1,321 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_MCIMX7D_M4.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* IMX7D_M4 */ +/* @version: 0.1 */ +/* @date: 2015-04-06 */ +/* @build: b54573 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 2015 , Freescale Semiconductor, Inc. */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + + .word __etext + .word __data_start__ + .word __data_end__ + .word __bss_end__ + + + + + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DefaultISR /* 16*/ + .long DefaultISR /* 17*/ + .long DefaultISR /* 18*/ + .long DefaultISR /* 19*/ + .long DefaultISR /* 20*/ + .long DefaultISR /* 21*/ + .long DefaultISR /* 22*/ + .long DefaultISR /* 23*/ + .long DefaultISR /* 24*/ + .long DefaultISR /* 25*/ + .long WDOG3_Handler /* WDOG3 Handler*/ + .long SEMA4_Handler /* SEMA4_Handler*/ + .long DefaultISR /* 28*/ + .long DefaultISR /* 29*/ + .long DefaultISR /* 30*/ + .long DefaultISR /* 31*/ + .long UART6_Handler /* UART6 Handler*/ + .long DefaultISR /* 33*/ + .long DefaultISR /* 34*/ + .long DefaultISR /* 35*/ + .long DefaultISR /* 36*/ + .long DefaultISR /* 37*/ + .long DefaultISR /* 38*/ + .long DefaultISR /* 39*/ + .long DefaultISR /* 40*/ + .long DefaultISR /* 41*/ + .long UART1_Handler /* UART1 Handler*/ + .long UART2_Handler /* UART2 Handler*/ + .long UART3_Handler /* UART3 Handler*/ + .long UART4_Handler /* UART4 Handler*/ + .long UART5_Handler /* UART5 Handler*/ + .long eCSPI1_Handler /* eCSPI1 Handler*/ + .long eCSPI2_Handler /* eCSPI2 Handler*/ + .long eCSPI3_Handler /* eCSPI3 Handler*/ + .long eCSPI4_Handler /* eCSPI4 Handler*/ + .long I2C1_Handler /* I2C1 Handler*/ + .long I2C2_Handler /* I2C2 Handler*/ + .long I2C3_Handler /* I2C3 Handler*/ + .long I2C4_Handler /* I2C4 Handler*/ + .long DefaultISR /* 55*/ + .long DefaultISR /* 56*/ + .long DefaultISR /* 57*/ + .long DefaultISR /* 58*/ + .long DefaultISR /* 59*/ + .long DefaultISR /* 60*/ + .long DefaultISR /* 61*/ + .long DefaultISR /* 62*/ + .long DefaultISR /* 63*/ + .long DefaultISR /* 64*/ + .long DefaultISR /* 65*/ + .long DefaultISR /* 66*/ + .long DefaultISR /* 67*/ + .long GPT4_Handler /* GPT4 handler*/ + .long GPT3_Handler /* GPT3 handler*/ + .long GPT2_Handler /* GPT2 handler*/ + .long GPT1_Handler /* GPT1 handler*/ + .long GPIO1_INT7_Handler /* Active HIGH Interrupt from INT7 from GPIO*/ + .long GPIO1_INT6_Handler /* Active HIGH Interrupt from INT6 from GPIO*/ + .long GPIO1_INT5_Handler /* Active HIGH Interrupt from INT5 from GPIO*/ + .long GPIO1_INT4_Handler /* Active HIGH Interrupt from INT4 from GPIO*/ + .long GPIO1_INT3_Handler /* Active HIGH Interrupt from INT3 from GPIO*/ + .long GPIO1_INT2_Handler /* Active HIGH Interrupt from INT2 from GPIO*/ + .long GPIO1_INT1_Handler /* Active HIGH Interrupt from INT1 from GPIO*/ + .long GPIO1_INT0_Handler /* Active HIGH Interrupt from INT0 from GPIO*/ + .long GPIO1_INT15_0_Handler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ + .long GPIO1_INT31_16_Handler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ + .long GPIO2_INT15_0_Handler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ + .long GPIO2_INT31_16_Handler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ + .long GPIO3_INT15_0_Handler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ + .long GPIO3_INT31_16_Handler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ + .long GPIO4_INT15_0_Handler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ + .long GPIO4_INT31_16_Handler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ + .long GPIO5_INT15_0_Handler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ + .long GPIO5_INT31_16_Handler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ + .long GPIO6_INT15_0_Handler /* Combined interrupt indication for GPIO6 signal 0 throughout 15*/ + .long GPIO6_INT31_16_Handler /* Combined interrupt indication for GPIO6 signal 16 throughout 31*/ + .long GPIO7_INT15_0_Handler /* Combined interrupt indication for GPIO7 signal 0 throughout 15*/ + .long GPIO7_INT31_16_Handler /* Combined interrupt indication for GPIO7 signal 16 throughout 31*/ + .long DefaultISR /* 94*/ + .long DefaultISR /* 95*/ + .long DefaultISR /* 96*/ + .long DefaultISR /* 97*/ + .long DefaultISR /* 98*/ + .long DefaultISR /* 99*/ + .long DefaultISR /* 100*/ + .long DefaultISR /* 101*/ + .long DefaultISR /* 102*/ + .long DefaultISR /* 103*/ + .long DefaultISR /* 104*/ + .long DefaultISR /* 105*/ + .long DefaultISR /* 106*/ + .long DefaultISR /* 107*/ + .long DefaultISR /* 108*/ + .long DefaultISR /* 109*/ + .long DefaultISR /* 110*/ + .long DefaultISR /* 111*/ + .long DefaultISR /* 112*/ + .long MU_Handler /* MU Handler*/ + .long ADC1_Handler /* ADC1 Handler*/ + .long ADC2_Handler /* ADC2 Handler*/ + .long DefaultISR /* 116*/ + .long DefaultISR /* 117*/ + .long DefaultISR /* 118*/ + .long DefaultISR /* 119*/ + .long DefaultISR /* 120*/ + .long DefaultISR /* 121*/ + .long DefaultISR /* 122*/ + .long DefaultISR /* 123*/ + .long DefaultISR /* 124*/ + .long DefaultISR /* 125*/ + .long FLEXCAN1_Handler /* FLEXCAN1 Handler*/ + .long FLEXCAN2_Handler /* FLEXCAN2 Handler*/ + .long DefaultISR /* 128*/ + .long DefaultISR /* 129*/ + .long DefaultISR /* 130*/ + .long DefaultISR /* 131*/ + .long DefaultISR /* 132*/ + .long DefaultISR /* 133*/ + .long DefaultISR /* 134*/ + .long DefaultISR /* 135*/ + .long DefaultISR /* 136*/ + .long DefaultISR /* 137*/ + .long DefaultISR /* 138*/ + .long DefaultISR /* 139*/ + .long DefaultISR /* 140*/ + .long DefaultISR /* 141*/ + .long UART7_Handler /* UART7 Handler*/ + .long DefaultISR /* 143*/ + + .size __isr_vector, . - __isr_vector + + + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + /* data copy */ + ldr r0,=__DATA_ROM + subs r0,r0,#0x1 + ldr r1,=__data_start__ + subs r1,r1,#0x1 + ldr r2,=__data_end__ + subs r3,r2,r1 + b Copy_init_data + Loop_copy_init_data: + adds r1,r1,#0x1 + adds r0,r0,#0x1 + ldrb r4,[r0] + str r4,[r1] + + Copy_init_data: + subs r3,r3,#0x1 + cmp r3,#0x0 + bne Loop_copy_init_data + + cpsie i /* Unmask interrupts */ + bl _start + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler WDOG3_Handler + def_irq_handler SEMA4_Handler + def_irq_handler UART6_Handler + def_irq_handler UART1_Handler + def_irq_handler UART2_Handler + def_irq_handler UART3_Handler + def_irq_handler UART4_Handler + def_irq_handler UART5_Handler + def_irq_handler eCSPI1_Handler + def_irq_handler eCSPI2_Handler + def_irq_handler eCSPI3_Handler + def_irq_handler eCSPI4_Handler + def_irq_handler I2C1_Handler + def_irq_handler I2C2_Handler + def_irq_handler I2C3_Handler + def_irq_handler I2C4_Handler + def_irq_handler GPT4_Handler + def_irq_handler GPT3_Handler + def_irq_handler GPT2_Handler + def_irq_handler GPT1_Handler + def_irq_handler GPIO1_INT7_Handler + def_irq_handler GPIO1_INT6_Handler + def_irq_handler GPIO1_INT5_Handler + def_irq_handler GPIO1_INT4_Handler + def_irq_handler GPIO1_INT3_Handler + def_irq_handler GPIO1_INT2_Handler + def_irq_handler GPIO1_INT1_Handler + def_irq_handler GPIO1_INT0_Handler + def_irq_handler GPIO1_INT15_0_Handler + def_irq_handler GPIO1_INT31_16_Handler + def_irq_handler GPIO2_INT15_0_Handler + def_irq_handler GPIO2_INT31_16_Handler + def_irq_handler GPIO3_INT15_0_Handler + def_irq_handler GPIO3_INT31_16_Handler + def_irq_handler GPIO4_INT15_0_Handler + def_irq_handler GPIO4_INT31_16_Handler + def_irq_handler GPIO5_INT15_0_Handler + def_irq_handler GPIO5_INT31_16_Handler + def_irq_handler GPIO6_INT15_0_Handler + def_irq_handler GPIO6_INT31_16_Handler + def_irq_handler GPIO7_INT15_0_Handler + def_irq_handler GPIO7_INT31_16_Handler + def_irq_handler MU_Handler + def_irq_handler ADC1_Handler + def_irq_handler ADC2_Handler + def_irq_handler FLEXCAN1_Handler + def_irq_handler FLEXCAN2_Handler + def_irq_handler UART7_Handler + .end diff --git a/platform/devices/MCIMX7D/startup/iar/startup_MCIMX7D_M4.s b/platform/devices/MCIMX7D/startup/iar/startup_MCIMX7D_M4.s new file mode 100644 index 0000000..385c49c --- /dev/null +++ b/platform/devices/MCIMX7D/startup/iar/startup_MCIMX7D_M4.s @@ -0,0 +1,520 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MCIMX7D_M4.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; IMX7D_M4 +; @version: 0.1 +; @date: 2015-04-06 +; @build: b49163 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + +;External Interrupts + DCD DefaultISR ;Reserved Interrupt 16 + DCD DefaultISR ;Reserved Interrupt 17 + DCD DefaultISR ;Reserved Interrupt 18 + DCD DefaultISR ;Reserved Interrupt 19 + DCD DefaultISR ;Reserved Interrupt 20 + DCD DefaultISR ;Reserved Interrupt 21 + DCD DefaultISR ;Reserved Interrupt 22 + DCD DefaultISR ;Reserved Interrupt 23 + DCD DefaultISR ;Reserved Interrupt 24 + DCD DefaultISR ;Reserved Interrupt 25 + DCD WDOG3_Handler ;WDOG3 Handler + DCD SEMA4_Handler ;SEMA4 handler + DCD DefaultISR ;Reserved Interrupt 28 + DCD DefaultISR ;Reserved Interrupt 29 + DCD DefaultISR ;Reserved Interrupt 30 + DCD DefaultISR ;Reserved Interrupt 31 + DCD UART6_Handler ;UART6 Handler + DCD DefaultISR ;Reserved Interrupt 33 + DCD DefaultISR ;Reserved Interrupt 34 + DCD DefaultISR ;Reserved Interrupt 35 + DCD DefaultISR ;Reserved Interrupt 36 + DCD DefaultISR ;Reserved Interrupt 37 + DCD DefaultISR ;Reserved Interrupt 38 + DCD DefaultISR ;Reserved Interrupt 39 + DCD DefaultISR ;Reserved Interrupt 40 + DCD DefaultISR ;Reserved Interrupt 41 + DCD UART1_Handler ;UART1 Handler + DCD UART2_Handler ;UART2 Handler + DCD UART3_Handler ;UART3 Handler + DCD UART4_Handler ;UART4 Handler + DCD UART5_Handler ;UART5 Handler + DCD eCSPI1_Handler ;eCSPI1 Handler + DCD eCSPI2_Handler ;eCSPI2 Handler + DCD eCSPI3_Handler ;eCSPI3 Handler + DCD eCSPI4_Handler ;eCSPI4 Handler + DCD I2C1_Handler ;I2C1 Handler + DCD I2C2_Handler ;I2C2 Handler + DCD I2C3_Handler ;I2C3 Handler + DCD I2C4_Handler ;I2C4 Handler + DCD DefaultISR ;Reserved Interrupt 55 + DCD DefaultISR ;Reserved Interrupt 56 + DCD DefaultISR ;Reserved Interrupt 57 + DCD DefaultISR ;Reserved Interrupt 58 + DCD DefaultISR ;Reserved Interrupt 59 + DCD DefaultISR ;Reserved Interrupt 60 + DCD DefaultISR ;Reserved Interrupt 61 + DCD DefaultISR ;Reserved Interrupt 62 + DCD DefaultISR ;Reserved Interrupt 63 + DCD DefaultISR ;Reserved Interrupt 64 + DCD DefaultISR ;Reserved Interrupt 65 + DCD DefaultISR ;Reserved Interrupt 66 + DCD DefaultISR ;Reserved Interrupt 67 + DCD GPT4_Handler ;GPT4 handler + DCD GPT3_Handler ;GPT3 handler + DCD GPT2_Handler ;GPT2 handler + DCD GPT1_Handler ;GPT1 handler + DCD GPIO1_INT7_Handler ;Active HIGH Interrupt from INT7 from GPIO + DCD GPIO1_INT6_Handler ;Active HIGH Interrupt from INT6 from GPIO + DCD GPIO1_INT5_Handler ;Active HIGH Interrupt from INT5 from GPIO + DCD GPIO1_INT4_Handler ;Active HIGH Interrupt from INT4 from GPIO + DCD GPIO1_INT3_Handler ;Active HIGH Interrupt from INT3 from GPIO + DCD GPIO1_INT2_Handler ;Active HIGH Interrupt from INT2 from GPIO + DCD GPIO1_INT1_Handler ;Active HIGH Interrupt from INT1 from GPIO + DCD GPIO1_INT0_Handler ;Active HIGH Interrupt from INT0 from GPIO + DCD GPIO1_INT15_0_Handler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 + DCD GPIO1_INT31_16_Handler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 + DCD GPIO2_INT15_0_Handler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 + DCD GPIO2_INT31_16_Handler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 + DCD GPIO3_INT15_0_Handler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 + DCD GPIO3_INT31_16_Handler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 + DCD GPIO4_INT15_0_Handler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 + DCD GPIO4_INT31_16_Handler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 + DCD GPIO5_INT15_0_Handler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 + DCD GPIO5_INT31_16_Handler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 + DCD GPIO6_INT15_0_Handler ;Combined interrupt indication for GPIO6 signal 0 throughout 15 + DCD GPIO6_INT31_16_Handler ;Combined interrupt indication for GPIO6 signal 16 throughout 31 + DCD GPIO7_INT15_0_Handler ;Combined interrupt indication for GPIO7 signal 0 throughout 15 + DCD GPIO7_INT31_16_Handler ;Combined interrupt indication for GPIO7 signal 16 throughout 31 + DCD DefaultISR ;Reserved Interrupt 94 + DCD DefaultISR ;Reserved Interrupt 95 + DCD DefaultISR ;Reserved Interrupt 96 + DCD DefaultISR ;Reserved Interrupt 97 + DCD DefaultISR ;Reserved Interrupt 98 + DCD DefaultISR ;Reserved Interrupt 99 + DCD DefaultISR ;Reserved Interrupt 100 + DCD DefaultISR ;Reserved Interrupt 101 + DCD DefaultISR ;Reserved Interrupt 102 + DCD DefaultISR ;Reserved Interrupt 103 + DCD DefaultISR ;Reserved Interrupt 104 + DCD DefaultISR ;Reserved Interrupt 105 + DCD DefaultISR ;Reserved Interrupt 106 + DCD DefaultISR ;Reserved Interrupt 107 + DCD DefaultISR ;Reserved Interrupt 108 + DCD DefaultISR ;Reserved Interrupt 109 + DCD DefaultISR ;Reserved Interrupt 110 + DCD DefaultISR ;Reserved Interrupt 111 + DCD DefaultISR ;Reserved Interrupt 112 + DCD MU_Handler ;MU Handler + DCD ADC1_Handler ;ADC1 Handler + DCD ADC2_Handler ;ADC2 Handler + DCD DefaultISR ;Reserved Interrupt 116 + DCD DefaultISR ;Reserved Interrupt 117 + DCD DefaultISR ;Reserved Interrupt 118 + DCD DefaultISR ;Reserved Interrupt 119 + DCD DefaultISR ;Reserved Interrupt 120 + DCD DefaultISR ;Reserved Interrupt 121 + DCD DefaultISR ;Reserved Interrupt 122 + DCD DefaultISR ;Reserved Interrupt 123 + DCD DefaultISR ;Reserved Interrupt 124 + DCD DefaultISR ;Reserved Interrupt 125 + DCD FLEXCAN1_Handler ;FLEXCAN1 Handler + DCD FLEXCAN2_Handler ;FLEXCAN2 Handler + DCD DefaultISR ;Reserved Interrupt 128 + DCD DefaultISR ;Reserved Interrupt 129 + DCD DefaultISR ;Reserved Interrupt 130 + DCD DefaultISR ;Reserved Interrupt 131 + DCD DefaultISR ;Reserved Interrupt 132 + DCD DefaultISR ;Reserved Interrupt 133 + DCD DefaultISR ;Reserved Interrupt 134 + DCD DefaultISR ;Reserved Interrupt 135 + DCD DefaultISR ;Reserved Interrupt 136 + DCD DefaultISR ;Reserved Interrupt 137 + DCD DefaultISR ;Reserved Interrupt 138 + DCD DefaultISR ;Reserved Interrupt 139 + DCD DefaultISR ;Reserved Interrupt 140 + DCD DefaultISR ;Reserved Interrupt 141 + DCD UART7_Handler ;UART7 Handler + DCD DefaultISR ;Reserved Interrupt 143 + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDOG3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG3_Handler + B . + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B . + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B . + + PUBWEAK UART3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART3_Handler + B . + + PUBWEAK UART4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_Handler + B . + + PUBWEAK UART5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_Handler + B . + + PUBWEAK UART6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART6_Handler + B . + + PUBWEAK UART7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_Handler + B . + + PUBWEAK eCSPI1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +eCSPI1_Handler + B . + + PUBWEAK eCSPI2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +eCSPI2_Handler + B . + + PUBWEAK eCSPI3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +eCSPI3_Handler + B . + + PUBWEAK eCSPI4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +eCSPI4_Handler + B . + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B . + + PUBWEAK I2C2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_Handler + B . + + PUBWEAK I2C3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_Handler + B . + + PUBWEAK I2C4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C4_Handler + B . + + PUBWEAK GPT4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPT4_Handler + B . + + PUBWEAK GPT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPT3_Handler + B . + + PUBWEAK GPT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPT2_Handler + B . + + PUBWEAK GPT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPT1_Handler + B . + + PUBWEAK GPIO1_INT7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT7_Handler + B . + + PUBWEAK GPIO1_INT6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT6_Handler + B . + + PUBWEAK GPIO1_INT5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT5_Handler + B . + + PUBWEAK GPIO1_INT4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT4_Handler + B . + + PUBWEAK GPIO1_INT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT3_Handler + B . + + PUBWEAK GPIO1_INT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT2_Handler + B . + + PUBWEAK GPIO1_INT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT1_Handler + B . + + PUBWEAK GPIO1_INT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT0_Handler + B . + + PUBWEAK GPIO1_INT15_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT15_0_Handler + B . + + PUBWEAK GPIO1_INT31_16_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO1_INT31_16_Handler + B . + + PUBWEAK GPIO2_INT15_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO2_INT15_0_Handler + B . + + PUBWEAK GPIO2_INT31_16_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO2_INT31_16_Handler + B . + + PUBWEAK GPIO3_INT15_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO3_INT15_0_Handler + B . + + PUBWEAK GPIO3_INT31_16_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO3_INT31_16_Handler + B . + + PUBWEAK GPIO4_INT15_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO4_INT15_0_Handler + B . + + PUBWEAK GPIO4_INT31_16_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO4_INT31_16_Handler + B . + + PUBWEAK GPIO5_INT15_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO5_INT15_0_Handler + B . + + PUBWEAK GPIO5_INT31_16_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO5_INT31_16_Handler + B . + + PUBWEAK GPIO6_INT15_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO6_INT15_0_Handler + B . + + PUBWEAK GPIO6_INT31_16_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO6_INT31_16_Handler + B . + + PUBWEAK GPIO7_INT15_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO7_INT15_0_Handler + B . + + PUBWEAK GPIO7_INT31_16_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO7_INT31_16_Handler + B . + + PUBWEAK MU_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MU_Handler + B . + + PUBWEAK ADC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_Handler + B . + + PUBWEAK ADC2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC2_Handler + B . + + PUBWEAK SEMA4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SEMA4_Handler + B . + + PUBWEAK FLEXCAN1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +FLEXCAN1_Handler + + PUBWEAK FLEXCAN2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +FLEXCAN2_Handler + + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DefaultISR + B DefaultISR + + END + diff --git a/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.c b/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.c new file mode 100644 index 0000000..550e4ba --- /dev/null +++ b/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include <stdbool.h> +#include "MCIMX7D_M4.h" + + +/* ---------------------------------------------------------------------------- + -- Vector Table offset + ---------------------------------------------------------------------------- */ +#define VECT_TAB_OFFSET 0x0 + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ +uint32_t SystemCoreClock = 240000000; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ +void SystemInit(void) +{ + // The Vector table base address is given by linker script. +#if defined(__CC_ARM) + extern uint32_t Image$$ER_m_text$$Base[]; +#else + extern uint32_t __VECTOR_TABLE[]; +#endif + + +#if ((1 == __FPU_PRESENT) && (1 == __FPU_USED)) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* M4 core root SYS PLL Div2: 240MHz */ + CCM_TARGET_ROOT1 = 0x11000000; + + /* initialize cache */ + // Enable I_Cache + // Enable D_Cache + + /* relocate vector table */ +#if defined(__CC_ARM) + SCB->VTOR = (uint32_t)Image$$ER_m_text$$Base + VECT_TAB_OFFSET; +#else + SCB->VTOR = (uint32_t)__VECTOR_TABLE + VECT_TAB_OFFSET; +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = 240000000; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.h b/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.h new file mode 100644 index 0000000..ed4b1b8 --- /dev/null +++ b/platform/devices/MCIMX7D/startup/system_MCIMX7D_M4.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SYSTEM_MCIMX7D_M4_H +#define __SYSTEM_MCIMX7D_M4_H + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +extern void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MCIMX7D_M4_H */ diff --git a/platform/devices/device_imx.h b/platform/devices/device_imx.h new file mode 100644 index 0000000..fe1b21b --- /dev/null +++ b/platform/devices/device_imx.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +#ifndef __DEVICE_IMX_H__ +#define __DEVICE_IMX_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if defined(CPU_IMX6SX_M4) + + /* CMSIS-style register definitions */ + #include "MCIMX6X/include/MCIMX6SX_M4.h" + +#elif defined(CPU_IMX7D_M4) + + /* CMSIS-style register definitions */ + #include "MCIMX7D/include/MCIMX7D_M4.h" + + #define RDC_SEMAPHORE_MASTER_SELF (6) + #define SEMA4_PROCESSOR_SELF (1) + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __DEVICE_IMX_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ |