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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef __IMX8QXP_VAL_H
#define __IMX8QXP_VAL_H
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#include "imx_env.h"
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_MAX_SIZE (192 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_IDENT
/*
* The memory layout on stack: DATA section save + gd + early malloc
* the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with
* CONFIG_SYS_SPL_MALLOC_START
*/
#define CONFIG_SPL_STACK 0x013fff0
#define CONFIG_SPL_BSS_START_ADDR 0x00130000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x82200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CONFIG_MALLOC_F_ADDR 0x00138000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_CMD_READ
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define CONFIG_PCIE_IMX
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_FEC_XCV_TYPE RGMII
#define PHY_ANEG_TIMEOUT 20000
/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
#define CONFIG_ETHPRIME "eth0"
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
#define AHAB_ENV "sec_boot=no\0"
#endif
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
#ifdef CONFIG_NAND_BOOT
#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
#endif
#define CONFIG_MFG_ENV_SETTINGS \
CONFIG_MFG_ENV_SETTINGS_DEFAULT \
"clk_ignore_unused "\
"\0" \
"initrd_addr=0x83100000\0" \
"initrd_high=0xffffffffffffffff\0" \
"emmc_dev=0\0" \
"sd_dev=1\0" \
/* Initial environment variables */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_MFG_ENV_SETTINGS \
"bootargs=console=ttyLP0,115200 ubi.mtd=nandrootfs " \
"root=ubi0:nandrootfs rootfstype=ubifs " \
MFG_NAND_PARTITION \
"\0"\
"console=ttyLP0,115200 earlycon\0" \
"mtdparts=" MFG_NAND_PARTITION "\0" \
"fdt_addr=0x83000000\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_MFG_ENV_SETTINGS \
M4_BOOT_ENV \
AHAB_ENV \
"script=boot.scr\0" \
"image=Image\0" \
"panel=NULL\0" \
"console=ttyLP0\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"cntr_addr=0x98000000\0" \
"cntr_file=os_cntr_signed.bin\0" \
"boot_fdt=try\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=1\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
"auth_os=auth_cntr ${cntr_addr}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${sec_boot} = yes; then " \
"if run auth_os; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo ERR: failed to authenticate; " \
"fi; " \
"else " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"echo wait for boot; " \
"fi;" \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} earlycon " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"if test ${sec_boot} = yes; then " \
"${get_cmd} ${cntr_addr} ${cntr_file}; " \
"if run auth_os; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo ERR: failed to authenticate; " \
"fi; " \
"else " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"booti; " \
"fi;" \
"fi;\0"
#endif
/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
*/
#ifdef CONFIG_TARGET_IMX8X_17X17_VAL
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#define CONFIG_SYS_FSL_USDHC_NUM 1
#else
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#if defined(CONFIG_TARGET_IMX8QXP_DDR3_VAL) || defined(CONFIG_TARGET_IMX8X_17X17_VAL)
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */
#define PHYS_SDRAM_2_SIZE 0x00000000
#else
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
/* LPDDR4 board total DDR is 3GB */
#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
#endif
/* Serial */
#define CONFIG_BAUDRATE 115200
/* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#ifndef CONFIG_DM_PCA953X
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#endif
#define CONFIG_SERIAL_TAG
#ifdef CONFIG_NAND_MXS
#define CONFIG_CMD_NAND_TRIMFFS
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#endif
/* USB Config */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_USBD_HS
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* USB OTG controller configs */
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#endif
#endif /* __IMX8QXP_VAL_H */
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