summaryrefslogtreecommitdiff
path: root/include/asm-blackfin/mem_init.h
blob: 1a13d908e0f03afb63fc8f4d5382170232259fca (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
/*
 * U-boot - mem_init.h Header file for memory initialization
 *
 * Copyright (c) 2005 blackfin.uclinux.org
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#if ( CONFIG_MEM_MT48LC16M16A2TG_75  ||  CONFIG_MEM_MT48LC64M4A2FB_7E )
	#if ( CONFIG_SCLK_HZ > 119402985 )
		#define SDRAM_tRP	TRP_2
		#define SDRAM_tRP_num	2
		#define SDRAM_tRAS	TRAS_7
		#define SDRAM_tRAS_num	7
		#define SDRAM_tRCD	TRCD_2
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
		#define SDRAM_tRP	TRP_2
		#define SDRAM_tRP_num	2
		#define SDRAM_tRAS	TRAS_6
		#define SDRAM_tRAS_num	6
		#define SDRAM_tRCD	TRCD_2
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ >  89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
		#define SDRAM_tRP	TRP_2
		#define SDRAM_tRP_num	2
		#define SDRAM_tRAS	TRAS_5
		#define SDRAM_tRAS_num	5
		#define SDRAM_tRCD	TRCD_2
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ >  74626866 ) && ( CONFIG_SCLK_HZ <=  89552239 )
		#define SDRAM_tRP	TRP_2
		#define SDRAM_tRP_num	2
		#define SDRAM_tRAS	TRAS_4
		#define SDRAM_tRAS_num	4
		#define SDRAM_tRCD	TRCD_2
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ >  66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
		#define SDRAM_tRP	TRP_2
		#define SDRAM_tRP_num	2
		#define SDRAM_tRAS	TRAS_3
		#define SDRAM_tRAS_num	3
		#define SDRAM_tRCD	TRCD_2
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ >  59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
		#define SDRAM_tRP	TRP_1
		#define SDRAM_tRP_num	1
		#define SDRAM_tRAS	TRAS_4
		#define SDRAM_tRAS_num	3
		#define SDRAM_tRCD	TRCD_1
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ >  44776119 ) && ( CONFIG_SCLK_HZ <=  59701493 )
		#define SDRAM_tRP	TRP_1
		#define SDRAM_tRP_num	1
		#define SDRAM_tRAS	TRAS_3
		#define SDRAM_tRAS_num	3
		#define SDRAM_tRCD	TRCD_1
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ >  29850746 ) && ( CONFIG_SCLK_HZ <=  44776119 )
		#define SDRAM_tRP	TRP_1
		#define SDRAM_tRP_num	1
		#define SDRAM_tRAS	TRAS_2
		#define SDRAM_tRAS_num	2
		#define SDRAM_tRCD	TRCD_1
		#define SDRAM_tWR	TWR_2
	#endif
	#if ( CONFIG_SCLK_HZ <=  29850746 )
		#define SDRAM_tRP	TRP_1
		#define SDRAM_tRP_num	1
		#define SDRAM_tRAS	TRAS_1
		#define SDRAM_tRAS_num	1
		#define SDRAM_tRCD	TRCD_1
		#define SDRAM_tWR	TWR_2
	#endif
#endif

#if (CONFIG_MEM_MT48LC16M16A2TG_75)
	/*SDRAM INFORMATION: */
	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
	#define SDRAM_CL	CL_3
#endif

#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
	/*SDRAM INFORMATION: */
	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
	#define SDRAM_CL	CL_2
#endif

#if ( CONFIG_MEM_SIZE == 128 )
	#define SDRAM_SIZE	EBSZ_128
#endif
#if ( CONFIG_MEM_SIZE == 64 )
	#define SDRAM_SIZE	EBSZ_64
#endif
#if (  CONFIG_MEM_SIZE == 32 )
	#define SDRAM_SIZE	EBSZ_32
#endif
#if ( CONFIG_MEM_SIZE == 16 )
	#define SDRAM_SIZE	EBSZ_16
#endif
#if ( CONFIG_MEM_ADD_WDTH == 11 )
	#define SDRAM_WIDTH	EBCAW_11
#endif
#if ( CONFIG_MEM_ADD_WDTH == 10 )
	#define SDRAM_WIDTH	EBCAW_10
#endif
#if ( CONFIG_MEM_ADD_WDTH == 9 )
	#define SDRAM_WIDTH	EBCAW_9
#endif
#if ( CONFIG_MEM_ADD_WDTH == 8 )
	#define SDRAM_WIDTH	EBCAW_8
#endif

#define mem_SDBCTL	SDRAM_WIDTH | SDRAM_SIZE | EBE

/* Equation from section 17 (p17-46) of BF533 HRM */
#define mem_SDRRC	((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)

/* Enable SCLK Out */
#define mem_SDGCTL	( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )

#define flash_EBIU_AMBCTL_WAT	( ( CONFIG_FLASH_SPEED_BWAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
#define flash_EBIU_AMBCTL_RAT	( ( CONFIG_FLASH_SPEED_BRAT * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
#define flash_EBIU_AMBCTL_HT	( ( CONFIG_FLASH_SPEED_BHT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) )
#define flash_EBIU_AMBCTL_ST	( ( CONFIG_FLASH_SPEED_BST  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
#define flash_EBIU_AMBCTL_TT	( ( CONFIG_FLASH_SPEED_BTT  * 4 )  / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1

#if (flash_EBIU_AMBCTL_TT > 3 )
	#define flash_EBIU_AMBCTL0_TT	B0TT_4
#endif
#if (flash_EBIU_AMBCTL_TT == 3 )
	#define flash_EBIU_AMBCTL0_TT	B0TT_3
#endif
#if (flash_EBIU_AMBCTL_TT == 2 )
	#define flash_EBIU_AMBCTL0_TT	B0TT_2
#endif
#if (flash_EBIU_AMBCTL_TT < 2 )
	#define flash_EBIU_AMBCTL0_TT	B0TT_1
#endif

#if (flash_EBIU_AMBCTL_ST > 3 )
	#define flash_EBIU_AMBCTL0_ST	B0ST_4
#endif
#if (flash_EBIU_AMBCTL_ST == 3 )
	#define flash_EBIU_AMBCTL0_ST	B0ST_3
#endif
#if (flash_EBIU_AMBCTL_ST == 2 )
	#define flash_EBIU_AMBCTL0_ST	B0ST_2
#endif
#if (flash_EBIU_AMBCTL_ST < 2 )
	#define flash_EBIU_AMBCTL0_ST	B0ST_1
#endif

#if (flash_EBIU_AMBCTL_HT > 2 )
	#define flash_EBIU_AMBCTL0_HT	B0HT_3
#endif
#if (flash_EBIU_AMBCTL_HT == 2 )
	#define flash_EBIU_AMBCTL0_HT	B0HT_2
#endif
#if (flash_EBIU_AMBCTL_HT == 1 )
	#define flash_EBIU_AMBCTL0_HT	B0HT_1
#endif
#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT == 0)
	#define flash_EBIU_AMBCTL0_HT	B0HT_0
#endif
#if (flash_EBIU_AMBCTL_HT == 0  && CONFIG_FLASH_SPEED_BHT != 0)
	#define flash_EBIU_AMBCTL0_HT	B0HT_1
#endif

#if (flash_EBIU_AMBCTL_WAT > 14)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_15
#endif
#if (flash_EBIU_AMBCTL_WAT == 14)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_14
#endif
#if (flash_EBIU_AMBCTL_WAT == 13)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_13
#endif
#if (flash_EBIU_AMBCTL_WAT == 12)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_12
#endif
#if (flash_EBIU_AMBCTL_WAT == 11)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_11
#endif
#if (flash_EBIU_AMBCTL_WAT == 10)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_10
#endif
#if (flash_EBIU_AMBCTL_WAT == 9)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_9
#endif
#if (flash_EBIU_AMBCTL_WAT == 8)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_8
#endif
#if (flash_EBIU_AMBCTL_WAT == 7)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_7
#endif
#if (flash_EBIU_AMBCTL_WAT == 6)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_6
#endif
#if (flash_EBIU_AMBCTL_WAT == 5)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_5
#endif
#if (flash_EBIU_AMBCTL_WAT == 4)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_4
#endif
#if (flash_EBIU_AMBCTL_WAT == 3)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_3
#endif
#if (flash_EBIU_AMBCTL_WAT == 2)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_2
#endif
#if (flash_EBIU_AMBCTL_WAT == 1)
	#define flash_EBIU_AMBCTL0_WAT	B0WAT_1
#endif

#if (flash_EBIU_AMBCTL_RAT > 14)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_15
#endif
#if (flash_EBIU_AMBCTL_RAT == 14)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_14
#endif
#if (flash_EBIU_AMBCTL_RAT == 13)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_13
#endif
#if (flash_EBIU_AMBCTL_RAT == 12)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_12
#endif
#if (flash_EBIU_AMBCTL_RAT == 11)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_11
#endif
#if (flash_EBIU_AMBCTL_RAT == 10)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_10
#endif
#if (flash_EBIU_AMBCTL_RAT == 9)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_9
#endif
#if (flash_EBIU_AMBCTL_RAT == 8)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_8
#endif
#if (flash_EBIU_AMBCTL_RAT == 7)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_7
#endif
#if (flash_EBIU_AMBCTL_RAT == 6)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_6
#endif
#if (flash_EBIU_AMBCTL_RAT == 5)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_5
#endif
#if (flash_EBIU_AMBCTL_RAT == 4)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_4
#endif
#if (flash_EBIU_AMBCTL_RAT == 3)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_3
#endif
#if (flash_EBIU_AMBCTL_RAT == 2)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_2
#endif
#if (flash_EBIU_AMBCTL_RAT == 1)
	#define flash_EBIU_AMBCTL0_RAT	B0RAT_1
#endif

#define flash_EBIU_AMBCTL0	flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN