path: root/drivers/net/ticpgmac.c

/*
 * Ethernet driver for OMAP3 OMAP3517EVM chip.
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
 * follows:
 *
 * ----------------------------------------------------------------------------
 * Derived from -
 *               dm644x_emac.c
 *
 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
 *
 * Copyright (C) 2005 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------

 * Modifications:
 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
 * ver  1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
 *
 */
#include <common.h>
#include <command.h>
#include <net.h>
#include <miiphy.h>
#include <asm/arch/ticpgmac.h>


#define STATIC
#define PRINTF(args,...)

#ifdef CONFIG_DRIVER_TI_EMAC

#ifdef CONFIG_CMD_NET

unsigned int	emac_dbg = 1;
#define debug_emac(fmt,args...)	if (emac_dbg) printf(fmt,##args)

#define BD_TO_HW(x) \
        ( ( (x) == 0) ? 0 : ( (x) - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR ))
#define HW_TO_BD(x) \
        ( ( (x) == 0) ? 0 : ( (x) - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR ))

/* Internal static functions */
STATIC int cpgmac_eth_hw_init (void);
STATIC int cpgmac_eth_open (void);
STATIC int cpgmac_eth_close (void);
STATIC int cpgmac_eth_send_packet (volatile void *packet, int length);
STATIC int cpgmac_eth_rcv_packet (void);
STATIC void cpgmac_eth_mdio_enable(void);

STATIC int gen_init_phy(int phy_addr);
STATIC int gen_is_phy_connected(int phy_addr);
STATIC int gen_get_link_status(int phy_addr);
STATIC int gen_auto_negotiate(int phy_addr);

/* Wrappers exported to the U-Boot proper */
int eth_hw_init(void)
{
	return(cpgmac_eth_hw_init());
}

int eth_init(bd_t * bd)
{
	return(cpgmac_eth_open());
}

void eth_halt(void)
{
	cpgmac_eth_close();
}

int eth_send(volatile void *packet, int length)
{
	return(cpgmac_eth_send_packet(packet, length));
}

int eth_rx(void)
{
	return(cpgmac_eth_rcv_packet());
}

void eth_mdio_enable(void)
{
	cpgmac_eth_mdio_enable();
}
/* End of wrappers */

/* cpgmac_eth_mac_addr[0] goes out on the wire first */

STATIC u_int8_t cpgmac_eth_mac_addr[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0x00 };

/*
 * This function must be called before emac_open() if you want to override
 * the default mac address.
 */
void cpgmac_eth_set_mac_addr(const u_int8_t *addr)
{
	int i;

	for (i = 0; i < sizeof (cpgmac_eth_mac_addr); i++) {
		cpgmac_eth_mac_addr[i] = addr[i];
	}
}

/* EMAC Addresses */
STATIC volatile emac_regs	*adap_emac = (emac_regs *)EMAC_BASE_ADDR;
STATIC volatile ewrap_regs	*adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
STATIC volatile mdio_regs	*adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;

/* EMAC descriptors */
STATIC volatile emac_desc	*emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
STATIC volatile emac_desc	*emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
STATIC volatile emac_desc	*emac_rx_active_head = 0;
STATIC volatile emac_desc	*emac_rx_active_tail = 0;
STATIC int			emac_rx_queue_active = 0;

/* Receive packet buffers */
STATIC unsigned char		emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];

/* PHY address for a discovered PHY (0xff - not found) */
STATIC volatile u_int8_t	active_phy_addr = 0xff;

STATIC int	no_phy_init (int phy_addr) { return(1); }
STATIC int	no_phy_is_connected (int phy_addr) { return(1); }
STATIC int	no_phy_get_link_status (int phy_addr)
{
	adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE
		| EMAC_MACCONTROL_FULLDUPLEX_ENABLE);
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
	adap_emac->MACCONTROL |= EMAC_MACCONTROL_RMIISPEED_100;
#endif
	return 1;
}
STATIC int  no_phy_auto_negotiate (int phy_addr) { return(1); }
phy_t				phy  = {
	.init = no_phy_init,
	.is_phy_connected = no_phy_is_connected,
	.get_link_status = no_phy_get_link_status,
	.auto_negotiate = no_phy_auto_negotiate
};

STATIC void cpgmac_eth_mdio_enable(void)
{
	u_int32_t	clkdiv;

	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;

	adap_mdio->CONTROL = (clkdiv & 0xff) |
		MDIO_CONTROL_ENABLE |
		MDIO_CONTROL_FAULT |
		MDIO_CONTROL_FAULT_ENABLE;

	while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;}
}

/*
 * Tries to find an active connected PHY. Returns 1 if address if found.
 * If no active PHY found returns 0. If more than one active PHY (switch)
 * returns 2
 * Sets active_phy_addr variable when returns 1.
 */
STATIC int cpgmac_eth_phy_detect(void)
{
	u_int32_t	phy_act_state;
	int		i;

	active_phy_addr = 0xff;

	if ((phy_act_state = adap_mdio->ALIVE) == 0)
		return(0);				/* No active PHYs */

	debug_emac("cpgmac_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);

	for (i = 0; i < 32; i++) {
		if (phy_act_state & (1 << i)) {
			if (phy_act_state & ~(1 << i))
				return(2);		/* More than one PHY */
			else {
				active_phy_addr = i;
				return(1);
			}
		}
	}

	return(0);	/* Just to make GCC happy */
}


/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
int cpgmac_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
{
	int	tmp;

	while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}

	adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO |
				MDIO_USERACCESS0_WRITE_READ |
				((reg_num & 0x1f) << 21) |
				((phy_addr & 0x1f) << 16);

	/* Wait for command to complete */
	while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;}

	if (tmp & MDIO_USERACCESS0_ACK) {
		*data = tmp & 0xffff;
		return(1);
	}

	*data = -1;
	return(0);
}

/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
int cpgmac_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
{

	while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}

	adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO |
				MDIO_USERACCESS0_WRITE_WRITE |
				((reg_num & 0x1f) << 21) |
				((phy_addr & 0x1f) << 16) |
				(data & 0xffff);

	/* Wait for command to complete */
	while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;}

	return(1);
}

/* PHY functions for a generic PHY */
STATIC int gen_init_phy(int phy_addr)
{
	int	ret = 1;

	if (gen_get_link_status(phy_addr)) {
		/* Try another time */
		ret = gen_get_link_status(phy_addr);
	}

	return(ret);
}

STATIC int gen_is_phy_connected(int phy_addr)
{
	u_int16_t	dummy;

	return(cpgmac_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy));
}

STATIC int gen_get_link_status(int phy_addr)
{
	u_int16_t	tmp,lpa_val,val;

	if (cpgmac_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)
							&& (tmp & 0x04)) {
		//printf("Phy %d MII_Status Reg=0x%x \n",phy_addr,tmp);
		//printf("MACCTRL 0x%x\n",adap_emac->MACCONTROL);

		cpgmac_eth_phy_read(phy_addr,MII_CTRL_REG,&val);
		//printf("Phy CTRL=0x%x \n",val);
		
		cpgmac_eth_phy_read(phy_addr,ANEG_ADVERTISE_REG,&val);
	//	printf("Phy ANEG ADV=0x%x \n",val);
              
		cpgmac_eth_phy_read(phy_addr,ANEG_LPA_REG,&lpa_val);
		//printf("Phy ANEG LPA=0x%x \n",lpa_val);
	      
		/* Speed doesn't matter, there is no setting for it in EMAC. */
		//if (tmp & GEN_PHY_STATUS_FD_MASK) {
		if (lpa_val & (GEN_PHY_ANEG_100DUP | GEN_PHY_ANEG_10DUP ) ) {
			/* set EMAC for Full Duplex  */
		//	printf("Set MACCTRL for full duplex \n");
			adap_emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
				EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
		} else {
			/*set EMAC for Half Duplex  */
			adap_emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
		//	printf("Set MACCTRL for HALF duplex \n");
		}

#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
		//if(tmp & GEN_PHY_STATUS_SPEED100_MASK) {
		if (lpa_val & (GEN_PHY_ANEG_100DUP | GEN_PHY_ANEG_100TX ) ) {
			adap_emac->MACCONTROL |= EMAC_MACCONTROL_RMIISPEED_100;
		//	printf("Set maccontrol for RMII 100 - 0x%x\n",adap_emac->MACCONTROL);

		} else {
			adap_emac->MACCONTROL &= ~EMAC_MACCONTROL_RMIISPEED_100;
			printf("Set maccontrol for RMII 10 -  0x%x\n",adap_emac->MACCONTROL);
		}
#endif

		return(1);
	}

	return(0);
}

STATIC int gen_auto_negotiate(int phy_addr)
{
	u_int16_t	tmp,val;
	unsigned long cntr =0;

	if (!cpgmac_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
		return(0);

        printf("read BMCR 0x%x\n",tmp);
	
	val = tmp | GEN_PHY_CTRL_DUP | GEN_PHY_CTRL_ENA_ANEG | GEN_PHY_CTRL_SPD_SEL ;
	cpgmac_eth_phy_write(phy_addr, PHY_BMCR, val);
	cpgmac_eth_phy_read(phy_addr, PHY_BMCR, &val);
	printf("BMCR set to 0x%X \n",val);

	cpgmac_eth_phy_read(phy_addr,ANEG_ADVERTISE_REG, &val);
	printf("read ANEG 0x%x \n",val);
	val |= ( GEN_PHY_ANEG_100DUP | GEN_PHY_ANEG_100TX | GEN_PHY_ANEG_10DUP | GEN_PHY_ANEG_10TX );
	printf("writing back 0x%x \n",val);
	cpgmac_eth_phy_write(phy_addr, ANEG_ADVERTISE_REG, val);
	cpgmac_eth_phy_read(phy_addr,ANEG_ADVERTISE_REG, &val);
	printf("ANEG ADVT set to 0x%x \n", val);

	
	printf("Restart Auto-negn \n");
	cpgmac_eth_phy_read(phy_addr, PHY_BMCR, &tmp);
	
	/* Restart Auto_negotiation  */
	tmp |= PHY_BMCR_RST_NEG;
	printf("writing bk 0x%x to BMCR for anegn \n",tmp);
	cpgmac_eth_phy_write(phy_addr, PHY_BMCR, tmp);

	/*check AutoNegotiate complete */
	//udelay (10000);
	do{
		udelay(40000);
		cntr++;
		}while(cntr < 150 );

	if (!cpgmac_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
		return(0);
	printf("BMSR after negn 0x%X\n",tmp);

	cpgmac_eth_phy_read(phy_addr,MII_CTRL_REG,&val);
	printf("Phy CTRL=0x%x \n",val);
		
	cpgmac_eth_phy_read(phy_addr,ANEG_ADVERTISE_REG,&val);
	printf("Phy ANEG ADV=0x%x \n",val);
              
	cpgmac_eth_phy_read(phy_addr,ANEG_LPA_REG,&val);
	printf("Phy ANEG LPA=0x%x \n",val);
	      
	cpgmac_eth_phy_read(phy_addr,ANEG_EXP_REG,&val);
	printf("Phy ANEG eXP=0x%x \n",val);
	      
	cpgmac_eth_phy_read(phy_addr,SPL_VEND_REG,&val);
	printf("Phy SPL VEND =0x%x \n",val);
	
	if (!(tmp & PHY_BMSR_AUTN_COMP))
		return(0);

	return(gen_get_link_status(phy_addr));
}
/* End of generic PHY functions */


#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
STATIC int cpgmac_mii_phy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
{
	printf("MII Phy read \n");
	return(cpgmac_eth_phy_read(addr, reg, value) ? 0 : 1);
}

STATIC int cpgmac_mii_phy_write(char *devname, unsigned char addr, unsigned char reg, unsigned short value)
{

	printf("MII Phy write \n");
	return(cpgmac_eth_phy_write(addr, reg, value) ? 0 : 1);
}

int cpgmac_eth_miiphy_initialize(bd_t *bis)
{
	printf("MIIPHY initialize \n");
	miiphy_register(phy.name, cpgmac_mii_phy_read, cpgmac_mii_phy_write);

	return(1);
}
#endif

/*
 * This function initializes the emac hardware. It does NOT initialize
 * EMAC modules power or pin multiplexors, that is done by board_init()
 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
 */
STATIC int cpgmac_eth_hw_init(void)
{
	u_int32_t	phy_id;
	u_int16_t	tmp;
	int		i, ret;

	cpgmac_eth_mdio_enable();

	for (i = 0; i < 256; i++) {
		if (adap_mdio->ALIVE)
			break;
		udelay(1000);
	}

	if (i >= 256) {
		printf("No ETH PHY detected!!!\n");
		return(0);
	}

	/* Find if a PHY is connected and get it's address */
	ret = cpgmac_eth_phy_detect();

	if (ret == 2) {
		printf("More than one PHY detected.\n");
		return(1);
	} else if(ret == 0)
		return(0);

	/* Get PHY ID and initialize phy_ops for a detected PHY */
	if (!cpgmac_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) {
		active_phy_addr = 0xff;
		return(0);
	}

	phy_id = (tmp << 16) & 0xffff0000;

	if (!cpgmac_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) {
		active_phy_addr = 0xff;
		return(0);
	}

	phy_id |= tmp & 0x0000ffff;

	switch (phy_id) {
		default:
			sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr);
			phy.init = gen_init_phy;
			phy.is_phy_connected = gen_is_phy_connected;
			phy.get_link_status = gen_get_link_status;
			phy.auto_negotiate = gen_auto_negotiate;
	}

	printf("Ethernet PHY: %s\n", phy.name);

	/* Override HW configuration value that were latched */
	cpgmac_eth_phy_read(active_phy_addr, SPL_VEND_REG, &tmp);
	printf("read HW config for PHY 0x%x\n",tmp);
//	tmp |= (1 << 14) | ( 7 << 5) ;
	tmp = 0x60e0;
	printf("Program HW config as 0x%x \n",tmp);
	cpgmac_eth_phy_write(active_phy_addr,SPL_VEND_REG,tmp);

	/* Soft reset the PHY */
	cpgmac_eth_phy_write(active_phy_addr, PHY_BMCR, (1 << 15));

	active_phy_addr = 0;

	do
	{
	cpgmac_eth_phy_read(active_phy_addr, PHY_BMCR , &tmp);
	
	}while (tmp & (1 << 15));

	
	

	return(1);
}


/* Eth device open */
STATIC int cpgmac_eth_open(void)
{
	dv_reg_p		addr;
	u_int32_t		clkdiv, cnt;
	volatile emac_desc	*rx_desc;
	int i;

	debug_emac("+ emac_open\n");

	/* Reset EMAC module and disable interrupts in wrapper */
	adap_emac->EMACSOFTRESET = 1;
	while (adap_emac->EMACSOFTRESET != 0) {;}
	adap_ewrap->EMACSOFTRESET = 1;
	while (adap_ewrap->EMACSOFTRESET != 0) {;}

	adap_ewrap->C0RXEN = adap_ewrap->C1RXEN = adap_ewrap->C2RXEN = 0;
	adap_ewrap->C0TXEN = adap_ewrap->C1TXEN = adap_ewrap->C2TXEN = 0;
	adap_ewrap->C0MISCEN = adap_ewrap->C1MISCEN = adap_ewrap->C2MISCEN = 0;

	rx_desc = emac_rx_desc;

	adap_emac->TXCONTROL = 0x01;
	adap_emac->RXCONTROL = 0x01;

	/* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
	/* Using channel 0 only - other channels are disabled */
	for (i = 0; i < 8; i++) {
		adap_emac->MACINDEX = i;
		adap_emac->MACADDRHI =
			(cpgmac_eth_mac_addr[3] << 24) |				/* bits 23-16 */
			(cpgmac_eth_mac_addr[2] << 16) |				/* bits 31-24 */
			(cpgmac_eth_mac_addr[1] << 8)  |				/* bits 39-32 */
			(cpgmac_eth_mac_addr[0]);						/* bits 47-40 */
		adap_emac->MACADDRLO =
			(cpgmac_eth_mac_addr[5] << 8) |					  /* bits 8-0*/
			(cpgmac_eth_mac_addr[4]) | (1 << 19) | (1 << 20); /* bits 8-0 */
	}

	adap_emac->MACHASH1 = 0;
	adap_emac->MACHASH2 = 0;

	/* Set source MAC address - REQUIRED for pause frames */
	adap_emac->MACSRCADDRHI =
		(cpgmac_eth_mac_addr[3] << 24) |	/* bits 23-16 */
		(cpgmac_eth_mac_addr[2] << 16) |	/* bits 31-24 */
		(cpgmac_eth_mac_addr[1] << 8)  |	/* bits 39-32 */
		(cpgmac_eth_mac_addr[0]);			/* bits 47-40 */
	adap_emac->MACSRCADDRLO =
		(cpgmac_eth_mac_addr[5] << 8) |		/* bits 8-0  */
		(cpgmac_eth_mac_addr[4]);			/* bits 15-8 */

	/* Set DMA 8 TX / 8 RX Head pointers to 0 */
	addr = &adap_emac->TX0HDP;
	for(cnt = 0; cnt < 16; cnt++)
		*addr++ = 0;

	addr = &adap_emac->RX0HDP;
	for(cnt = 0; cnt < 16; cnt++)
		*addr++ = 0;

	/* Clear Statistics (do this before setting MacControl register) */
	addr = &adap_emac->RXGOODFRAMES;
	for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
		*addr++ = 0;

	/* No multicast addressing */
	adap_emac->MACHASH1 = 0;
	adap_emac->MACHASH2 = 0;

	/* Create RX queue and set receive process in place */
	emac_rx_active_head = emac_rx_desc;
	for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
		rx_desc->next =BD_TO_HW( (u_int32_t)(rx_desc + 1) );
		rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
		rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
		rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
		rx_desc++;
	}

	/* Set the last descriptor's "next" parameter to 0 to end the RX desc list */
	rx_desc--;
	rx_desc->next = 0;
	emac_rx_active_tail = rx_desc;
	emac_rx_queue_active = 1;

	/* Enable TX/RX */
	adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE;
	adap_emac->RXBUFFEROFFSET = 0;

	/* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */
	adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN;

	/* Enable ch 0 only */
	adap_emac->RXUNICASTSET = 0x01;

	/* Enable MII interface and Full duplex mode */

	/* Init MDIO & get link state */
	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
	adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT);

	if (!phy.auto_negotiate(active_phy_addr))
		return(0);

	/* Start receive process */
	adap_emac->RX0HDP = BD_TO_HW((u_int32_t)emac_rx_desc);

	debug_emac("- emac_open\n");

	return(1);
}

/* EMAC Channel Teardown */
STATIC void cpgmac_eth_ch_teardown(int ch)
{
	dv_reg		dly = 0xff;
	dv_reg		cnt;

	debug_emac("+ emac_ch_teardown\n");

	if (ch == EMAC_CH_TX) {
		/* Init TX channel teardown */
		adap_emac->TXTEARDOWN = 1;
		for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) {
			/* Wait here for Tx teardown completion interrupt to occur
			 * Note: A task delay can be called here to pend rather than
			 * occupying CPU cycles - anyway it has been found that teardown
			 * takes very few cpu cycles and does not affect functionality */
			 dly--;
			 udelay(1);
			 if (dly == 0)
				break;
		}
		adap_emac->TX0CP = cnt;
		adap_emac->TX0HDP = 0;
	} else {
		/* Init RX channel teardown */
		adap_emac->RXTEARDOWN = 1;
		for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) {
			/* Wait here for Rx teardown completion interrupt to occur
			 * Note: A task delay can be called here to pend rather than
			 * occupying CPU cycles - anyway it has been found that teardown
			 * takes very few cpu cycles and does not affect functionality */
			 dly--;
			 udelay(1);
			 if (dly == 0)
				break;
		}
		adap_emac->RX0CP = cnt;
		adap_emac->RX0HDP = 0;
	}

	debug_emac("- emac_ch_teardown\n");
}

/* Eth device close */
STATIC int cpgmac_eth_close(void)
{
	debug_emac("+ emac_close\n");

	cpgmac_eth_ch_teardown(EMAC_CH_TX);	/* TX Channel teardown */
	cpgmac_eth_ch_teardown(EMAC_CH_RX);	/* RX Channel teardown */

	/* Reset EMAC module and disable interrupts in wrapper */
	adap_emac->EMACSOFTRESET = 1;
	adap_ewrap->EMACSOFTRESET = 1;

	adap_ewrap->C0RXEN = adap_ewrap->C1RXEN = adap_ewrap->C2RXEN = 0;
	adap_ewrap->C0TXEN = adap_ewrap->C1TXEN = adap_ewrap->C2TXEN = 0;
	adap_ewrap->C0MISCEN = adap_ewrap->C1MISCEN = adap_ewrap->C2MISCEN = 0;

	debug_emac("- emac_close\n");
	return(1);
}

STATIC int tx_send_loop = 0;

/*
 * This function sends a single packet on the network and returns
 * positive number (number of bytes transmitted) or negative for error
 */
STATIC int cpgmac_eth_send_packet (volatile void *packet, int length)
{
	int ret_status = -1;
	tx_send_loop = 0;

	/* Return error if no link */
	if (!phy.get_link_status (active_phy_addr)) {
		printf ("WARN: emac_send_packet: No link\n");
		return (ret_status);
	}

	/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
	if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
		length = EMAC_MIN_ETHERNET_PKT_SIZE;
	}

	/* Populate the TX descriptor */
	emac_tx_desc->next = 0;
	emac_tx_desc->buffer = (u_int8_t *) packet;
	emac_tx_desc->buff_off_len = (length & 0xffff);
	emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
					  EMAC_CPPI_SOP_BIT |
					  EMAC_CPPI_OWNERSHIP_BIT |
					  EMAC_CPPI_EOP_BIT);
				
	if (!phy.get_link_status (active_phy_addr)) {
	        printf("Link down . Abort Tx - pHY %d\n",active_phy_addr);
		cpgmac_eth_ch_teardown (EMAC_CH_TX);
		return (ret_status);
	}

	/* Send the packet */
	adap_emac->TX0HDP = BD_TO_HW((unsigned int) emac_tx_desc);
	PRINTF("Send: BD=0x%X BF=0x%x len=%d \n", emac_tx_desc, emac_tx_desc->buffer, length);
//	udelay(2500);

	/* Wait for packet to complete or link down */
	while (1) {
		#if 0
		if (!phy.get_link_status (active_phy_addr)) {
		        printf("Link down . Abort Tx - pHY %d\n",active_phy_addr);
			cpgmac_eth_ch_teardown (EMAC_CH_TX);
			return (ret_status);
		}
		#endif
		if (adap_emac->TXINTSTATRAW & 0x01) {
			ret_status = length;
	                //PRINTF("Send Complete: BD=0x%X BF=0x%x len=%d \n", emac_tx_desc, emac_tx_desc->buffer, length);
			break;
		}
		tx_send_loop++;
	}

	return (ret_status);
}

/*
 * This function handles receipt of a packet from the network
 */
STATIC int cpgmac_eth_rcv_packet (void)
{
	volatile emac_desc *rx_curr_desc;
	volatile emac_desc *curr_desc;
	volatile emac_desc *tail_desc;
	int status, ret = -1;

	rx_curr_desc = emac_rx_active_head;
	status = rx_curr_desc->pkt_flag_len;
	if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
		if (status & EMAC_CPPI_RX_ERROR_FRAME) {
			/* Error in packet - discard it and requeue desc */
			printf ("WARN: emac_rcv_pkt: Error in packet\n");
		} else {
			NetReceive (rx_curr_desc->buffer,
					(rx_curr_desc->buff_off_len & 0xffff));
			ret = rx_curr_desc->buff_off_len & 0xffff;
		}

		/* Ack received packet descriptor */
		adap_emac->RX0CP = BD_TO_HW((unsigned int) rx_curr_desc);
		curr_desc = rx_curr_desc;
		emac_rx_active_head =
			(volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
		PRINTF("New Rx Active head 0x%x \n",emac_rx_active_head);
		

		if (status & EMAC_CPPI_EOQ_BIT) {
			if (emac_rx_active_head) {
				adap_emac->RX0HDP =
					BD_TO_HW((unsigned int) emac_rx_active_head);
				PRINTF("Rx EOQ reset HDP for misqueued pkt 0x%x \n",emac_rx_active_head);	
			} else {
				emac_rx_queue_active = 0;
				PRINTF ("INFO:emac_rcv_packet: RX Queue not active\n");
			}
		}

		/* Recycle RX descriptor */
		rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
		rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
		rx_curr_desc->next = 0;

		if (emac_rx_active_head == 0) {
		//	printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
		        PRINTF(" Rx active head NULL, set head/tail to 0x%x",curr_desc);
			emac_rx_active_head = curr_desc;
			emac_rx_active_tail = curr_desc;
			if (emac_rx_queue_active == 0) {
				adap_emac->RX0HDP =
					BD_TO_HW((unsigned int) emac_rx_active_head);
				//printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
				PRINTF("Rx Q inactive , set HDP to 0x%x \n", emac_rx_active_head);
				emac_rx_queue_active = 1;
			}
		} else {
		        PRINTF("Append 0x%x to tail \n", curr_desc);
			tail_desc = emac_rx_active_tail;
			emac_rx_active_tail = curr_desc;
			tail_desc->next = BD_TO_HW((unsigned int) curr_desc);
			status = tail_desc->pkt_flag_len;
			if (status & EMAC_CPPI_EOQ_BIT) {
				status &= ~EMAC_CPPI_EOQ_BIT;
				tail_desc->pkt_flag_len = status;
				adap_emac->RX0HDP = BD_TO_HW((unsigned int) curr_desc);
				PRINTF("Restart the Q in tail append case\n");
			}
		}
		return (ret);
	}
	return (0);
}

#endif /* CONFIG_CMD_NET */

#endif /* CONFIG_DRIVER_TI_EMAC */