1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019, Bin Meng <bmeng.cn@gmail.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <asm/io.h>
struct gemgxl_mgmt_regs {
__u32 tx_clk_sel;
};
struct gemgxl_mgmt_platdata {
struct gemgxl_mgmt_regs *regs;
};
static int gemgxl_mgmt_ofdata_to_platdata(struct udevice *dev)
{
struct gemgxl_mgmt_platdata *plat = dev_get_platdata(dev);
plat->regs = (struct gemgxl_mgmt_regs *)dev_read_addr(dev);
return 0;
}
static ulong gemgxl_mgmt_set_rate(struct clk *clk, ulong rate)
{
struct gemgxl_mgmt_platdata *plat = dev_get_platdata(clk->dev);
/*
* GEMGXL TX clock operation mode:
*
* 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
* and output clock on GMII output signal GTX_CLK
* 1 = MII mode. Use MII input signal TX_CLK in TX logic
*/
writel(rate != 125000000, &plat->regs->tx_clk_sel);
return 0;
}
const struct clk_ops gemgxl_mgmt_ops = {
.set_rate = gemgxl_mgmt_set_rate,
};
static const struct udevice_id gemgxl_mgmt_match[] = {
{ .compatible = "sifive,cadencegemgxlmgmt0", },
{ /* sentinel */ }
};
U_BOOT_DRIVER(sifive_gemgxl_mgmt) = {
.name = "sifive-gemgxl-mgmt",
.id = UCLASS_CLK,
.of_match = gemgxl_mgmt_match,
.ofdata_to_platdata = gemgxl_mgmt_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct gemgxl_mgmt_platdata),
.ops = &gemgxl_mgmt_ops,
};
|
