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/*
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../common/pfuze.h"
#include <asm/arch/crm_regs.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_MXC_SPI
#ifndef CONFIG_DM_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
/* Chip selects CS0:CS3 */
MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
void setup_spinor(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
gpio_request(IMX_GPIO_NR(5, 3), "ecspi1_cs");
gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
}
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == 3 && cs == 0) ? (IMX_GPIO_NR(5, 3)) : -1;
}
#endif
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_MXC_SPI
#ifndef CONFIG_DM_SPI
setup_spinor();
#endif
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
{"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
{NULL, 0},
};
#endif
#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
struct udevice *dev;
int ret, dev_id, rev_id, reg;
ret = pmic_get("pfuze3000@8", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
return ret;
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* disable Low Power Mode during standby mode */
reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
reg |= 0x1;
pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
/* SW1A/1B mode set to APS/APS */
reg = 0x8;
pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
/* SW1A/1B standby voltage set to 0.975V */
reg = 0xb;
pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
/* set SW1B normal voltage to 0.975V */
reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
reg &= ~0x1f;
reg |= PFUZE3000_SW1AB_SETP(9750);
pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
return 0;
}
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
return 0;
}
u32 get_board_rev(void)
{
return get_cpu_rev();
}
int checkboard(void)
{
puts("Board: MX7D 12x12 DDR3 VAL\n");
return 0;
}
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