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|
/*
* Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/mx6.h>
#ifdef CONFIG_FLASH_HEADER
#ifndef CONFIG_FLASH_HEADER_OFFSET
# error "Must define the offset of flash header"
#endif
#define CPU_2_BE_32(l) \
((((l) & 0x000000FF) << 24) | \
(((l) & 0x0000FF00) << 8) | \
(((l) & 0x00FF0000) >> 8) | \
(((l) & 0xFF000000) >> 24))
#define MXC_DCD_ITEM(i, addr, val) \
dcd_node_##i: \
.word CPU_2_BE_32(addr) ; \
.word CPU_2_BE_32(val) ; \
.section ".text.flasheader", "x"
b _start
.org CONFIG_FLASH_HEADER_OFFSET
ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
app_code_jump_v: .word _start
reserv1: .word 0x0
dcd_ptr: .word dcd_hdr
boot_data_ptr: .word boot_data
self_ptr: .word ivt_header
app_code_csf: .word 0x0
reserv2: .word 0x0
boot_data: .word TEXT_BASE
image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
plugin: .word 0x0
#if defined CONFIG_MX6SOLO_DDR3
dcd_hdr: .word 0x408802D2 /* Tag=0xD2, Len=80*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd: .word 0x048402CC /* Tag=0xCC, Len=80*8 + 4, Param=0x04 */
/* DCD */
/* DDR3 initialization based on the MX6Solo Auto Reference Design (ARD) */
/* DDR IO TYPE */
MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
/* CLOCK */
MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
/* ADDRESS */
MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
/* CONTROLE */
MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x000c0030)
MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a4, 0x00003000)
MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4a8, 0x00003000)
MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x4b4, 0x00003030)
MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x4b8, 0x00003030)
MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
/* DATA STROBE */
MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4bc, 0x00000038)
MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c0, 0x00000038)
MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4c4, 0x00000038)
MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4c8, 0x00000038)
MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4cc, 0x00000038)
MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d0, 0x00000038)
MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x4d4, 0x00000038)
MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x4d8, 0x00000038)
/* DATA */
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x764, 0x00000030)
MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x770, 0x00000030)
MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x778, 0x00000030)
MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x77c, 0x00000030)
MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x780, 0x00000030)
MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x470, 0x00000030)
MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x474, 0x00000030)
MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x478, 0x00000030)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x47c, 0x00000030)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x480, 0x00000030)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x484, 0x00000030)
MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x488, 0x00000030)
MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x48c, 0x000C0030)
/* ZQ */
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
/* Write leveling */
MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x0040003c)
MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x0032003e)
MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x83c, 0x42350231)
MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x840, 0x021a0218)
MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x848, 0x4b4b4e49)
MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x850, 0x3f3f3035)
/* Read data bit delay */
MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
MXC_DCD_ITEM(53, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(55, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
/* Complete calibration by forced measurement */
MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d)
MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x00c, 0x696d5323)
MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63)
MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x030, 0x006d0e21)
MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x000, 0x84190000)
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030)
MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d)
MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x004, 0x00011006)
MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
#elif defined CONFIG_LPDDR2
dcd_hdr: .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd: .word 0x04EC03CC /* Tag=0xCC, Len=125*8 + 4, Param=0x04 */
/* DCD */
MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324)
MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333)
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39)
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738)
MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846)
MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35)
MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0)
MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0)
MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00)
MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00)
MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5)
MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036)
MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83)
MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd)
MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c)
MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2)
MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e)
MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac)
MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0)
MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f)
MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000)
MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5)
MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036)
MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83)
MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd)
MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c)
MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2)
MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e)
MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac)
MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0)
MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f)
MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000)
MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030)
MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030)
MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030)
MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030)
MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030)
MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030)
MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030)
MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030)
MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030)
MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030)
MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800)
MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800)
MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0)
MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0)
MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0)
MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
#elif defined CONFIG_MX6DL_DDR3
dcd_hdr: .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd: .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */
# IOMUXC_BASE_ADDR = 0x20e0000
# DDR IO TYPE
MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x774, 0x000c0000)
MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x754, 0x00000000)
# Clock
MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x4ac, 0x00000030)
MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x4b0, 0x00000030)
# Address
MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x464, 0x00000030)
MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x490, 0x00000030)
MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
# Control
MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x494, 0x00000030)
MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x4a0, 0x00000000)
MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x4b4, 0x00000030)
MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x4b8, 0x00000030)
MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x76c, 0x00000030)
# Data Strobe
MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x4bc, 0x00000028)
MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x4c0, 0x00000028)
MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x4c4, 0x00000028)
MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x4c8, 0x00000028)
MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x4cc, 0x00000028)
MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x4d0, 0x00000028)
MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x4d4, 0x00000028)
MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x4d8, 0x00000028)
# DATA
MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x760, 0x00020000)
MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x764, 0x00000028)
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x770, 0x00000028)
MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x778, 0x00000028)
MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x77c, 0x00000028)
MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x780, 0x00000028)
MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x78c, 0x00000028)
MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x470, 0x00000028)
MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x474, 0x00000028)
MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x478, 0x00000028)
MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x47c, 0x00000028)
MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x480, 0x00000028)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x484, 0x00000028)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x488, 0x00000028)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x48c, 0x00000028)
# MMDC_P0_BASE_ADDR = 0x021b0000
# MMDC_P1_BASE_ADDR = 0x021b4000
# Calibrations
# ZQ
MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
# write leveling
MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
# DQS gating, read delay, write delay calibration values
# based on calibration compare of 0x00ffff00
MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42190217)
MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x017B017B)
MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x4176017B)
MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x015F016C)
MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4C4C4D4C)
MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x4A4D4C48)
MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3F40)
MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x3538382E)
# read data bit delay
MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
# Complete calibration by forced measurment
MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
# MMDC init:
# in DDR3, 64-bit mode, only MMDC0 is initiated:
MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x00020025)
MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x00333030)
MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x676B5313)
MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xB66E8B63)
MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x006B1023)
MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
# Initialize 2GB DDR3 - Micron MT41J128M
# final DDR setup
MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032)
MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x05208030)
MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x00025565)
MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)
MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
#else
dcd_hdr: .word 0x40A002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd: .word 0x049C02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */
/* DCD */
/* DDR3 initialization based on the MX6Q Auto Reference Design (ARD) */
/* DDR IO TYPE: */
MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
/* CLOCK: */
MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
/* ADDRESS: */
MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
/* CONTROL: */
MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
/* configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x59c, 0x00000030)
MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5a0, 0x00000030)
MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
/* DATA STROBE: */
MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x5a8, 0x00000028)
MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5b0, 0x00000028)
MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x524, 0x00000028)
MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x51c, 0x00000028)
MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x518, 0x00000028)
MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x50c, 0x00000028)
MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5b8, 0x00000028)
MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5c0, 0x00000028)
/* DATA: */
MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x788, 0x00000028)
MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x794, 0x00000028)
MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x79c, 0x00000028)
MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x7a0, 0x00000028)
MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x7a4, 0x00000028)
MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a8, 0x00000028)
MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x5ac, 0x00000028)
MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x5b4, 0x00000028)
MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x528, 0x00000028)
MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x520, 0x00000028)
MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x514, 0x00000028)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x510, 0x00000028)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x5bc, 0x00000028)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x5c4, 0x00000028)
MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
/* Read DQS Gating calibration */
MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x4302030B)
MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x0275026A)
MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83c, 0x4302031A)
MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x027B0249)
/* Read calibration */
MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x3F343534)
MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x3A373345)
/* Write calibration */
MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x31424732)
MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x48334736)
/* read data bit delay: (3 is the reccommended default value, although out of reset value is 0): */
MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
/* Complete calibration by forced measurement: */
MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
/* MMDC init: */
MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7955)
MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xFF328F64)
MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
/* t during MMDC set up */
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
/* t values */
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x008F1023)
MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
/* Mode register writes */
MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
#endif
#endif
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