1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
#include <errno.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <spl.h>
#include <linux/bitops.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/tcpc.h"
#include "../common/pfuze.h"
#include <usb.h>
#include <dwc3-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
#ifdef CONFIG_FSL_QSPI
int board_qspi_init(void)
{
set_clk_qspi();
return 0;
}
#endif
#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
#ifndef CONFIG_DM_ETH
/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
#endif
return 0;
}
#endif
#ifdef CONFIG_USB_DWC3
#define USB_PHY_CTRL0 0xF0040
#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
#define USB_PHY_CTRL1 0xF0044
#define USB_PHY_CTRL1_RESET BIT(0)
#define USB_PHY_CTRL1_COMMONONN BIT(1)
#define USB_PHY_CTRL1_ATERESET BIT(3)
#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
#define USB_PHY_CTRL2 0xF0048
#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
static struct dwc3_device dwc3_device_data = {
#ifdef CONFIG_SPL_BUILD
.maximum_speed = USB_SPEED_HIGH,
#else
.maximum_speed = USB_SPEED_SUPER,
#endif
.base = USB1_BASE_ADDR,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
.power_down_scale = 2,
};
int usb_gadget_handle_interrupts(int index)
{
dwc3_uboot_handle_interrupt(index);
return 0;
}
static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
{
u32 RegData;
RegData = readl(dwc3->base + USB_PHY_CTRL1);
RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
USB_PHY_CTRL1_COMMONONN);
RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
writel(RegData, dwc3->base + USB_PHY_CTRL1);
RegData = readl(dwc3->base + USB_PHY_CTRL0);
RegData |= USB_PHY_CTRL0_REF_SSP_EN;
writel(RegData, dwc3->base + USB_PHY_CTRL0);
RegData = readl(dwc3->base + USB_PHY_CTRL2);
RegData |= USB_PHY_CTRL2_TXENABLEN0;
writel(RegData, dwc3->base + USB_PHY_CTRL2);
RegData = readl(dwc3->base + USB_PHY_CTRL1);
RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
writel(RegData, dwc3->base + USB_PHY_CTRL1);
}
#endif
#ifdef CONFIG_USB_TCPC
struct tcpc_port port;
struct tcpc_port_config port_config = {
.i2c_bus = 0,
.addr = 0x50,
.port_type = TYPEC_PORT_UFP,
.max_snk_mv = 20000,
.max_snk_ma = 3000,
.max_snk_mw = 15000,
.op_snk_mv = 9000,
};
struct gpio_desc type_sel_desc;
static iomux_v3_cfg_t ss_mux_gpio[] = {
IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
void ss_mux_select(enum typec_cc_polarity pol)
{
if (pol == TYPEC_POLARITY_CC1)
dm_gpio_set_value(&type_sel_desc, 1);
else
dm_gpio_set_value(&type_sel_desc, 0);
}
static int setup_typec(void)
{
int ret;
imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
ret = dm_gpio_lookup_name("GPIO3_15", &type_sel_desc);
if (ret) {
printf("%s lookup GPIO3_15 failed ret = %d\n", __func__, ret);
return -ENODEV;
}
ret = dm_gpio_request(&type_sel_desc, "typec_sel");
if (ret) {
printf("%s request typec_sel failed ret = %d\n", __func__, ret);
return -ENODEV;
}
dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
ret = tcpc_init(&port, port_config, &ss_mux_select);
if (ret) {
printf("%s: tcpc init failed, err=%d\n",
__func__, ret);
}
return ret;
}
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
int board_usb_init(int index, enum usb_init_type init)
{
int ret = 0;
if (index == 0 && init == USB_INIT_DEVICE) {
imx8m_usb_power(index, true);
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_ufp_mode(&port);
#endif
dwc3_nxp_usb_phy_init(&dwc3_device_data);
return dwc3_uboot_init(&dwc3_device_data);
} else if (index == 0 && init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_setup_dfp_mode(&port);
#endif
return ret;
}
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
int ret = 0;
if (index == 0 && init == USB_INIT_DEVICE) {
dwc3_uboot_exit(index);
imx8m_usb_power(index, false);
} else if (index == 0 && init == USB_INIT_HOST) {
#ifdef CONFIG_USB_TCPC
ret = tcpc_disable_src_vbus(&port);
#endif
}
return ret;
}
#endif
int board_init(void)
{
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
init_usb_clk();
#endif
#ifdef CONFIG_USB_TCPC
setup_typec();
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "EVK");
env_set("board_rev", "iMX8MQ");
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
board_late_mmc_env_init();
#endif
return 0;
}
#ifdef CONFIG_ANDROID_SUPPORT
bool is_power_key_pressed(void) {
return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
}
#endif
#ifdef CONFIG_FSL_FASTBOOT
#ifdef CONFIG_ANDROID_RECOVERY
int is_recovery_key_pressing(void)
{
return 0; /* TODO */
}
#endif /* CONFIG_ANDROID_RECOVERY */
#endif /* CONFIG_FSL_FASTBOOT */
|
