board/chromebook-x86/dts/link.dts


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

/dts-v1/;

/include/ "coreboot.dtsi"

/ {
        #address-cells = <1>;
        #size-cells = <1>;
	model = "Google Link";
	compatible = "google,link", "intel,celeron-ivybridge";

	config {
	       silent_console = <0>;
	};

        gpio: gpio {};

	serial {
		reg = <0x3f8 8>;
		clock-frequency = <115200>;
	};

        chosen { };
        memory { device_type = "memory"; reg = <0 0>; };
};