summaryrefslogtreecommitdiff
path: root/arch/x86/cpu/pci.c
blob: f8da08035e62bbcfd5454682bfa5b03fbeca19a9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
/*
 * Copyright (c) 2011 The Chromium OS Authors.
 * (C) Copyright 2008,2009
 * Graeme Russ, <graeme.russ@gmail.com>
 *
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/pci.h>

DECLARE_GLOBAL_DATA_PTR;

static struct pci_controller x86_hose;

int pci_early_init_hose(struct pci_controller **hosep)
{
	struct pci_controller *hose;

	hose = calloc(1, sizeof(struct pci_controller));
	if (!hose)
		return -ENOMEM;

	board_pci_setup_hose(hose);
	pci_setup_type1(hose);
	hose->last_busno = pci_hose_scan(hose);
	gd->hose = hose;
	*hosep = hose;

	return 0;
}

__weak int board_pci_pre_scan(struct pci_controller *hose)
{
	return 0;
}

__weak int board_pci_post_scan(struct pci_controller *hose)
{
	return 0;
}

void pci_init_board(void)
{
	struct pci_controller *hose = &x86_hose;

	/* Stop using the early hose */
	gd->hose = NULL;

	board_pci_setup_hose(hose);
	pci_setup_type1(hose);
	pci_register_hose(hose);

	board_pci_pre_scan(hose);
	hose->last_busno = pci_hose_scan(hose);
	board_pci_post_scan(hose);
}

static struct pci_controller *get_hose(void)
{
	if (gd->hose)
		return gd->hose;

	return pci_bus_to_hose(0);
}

unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
{
	uint8_t value;

	pci_hose_read_config_byte(get_hose(), dev, where, &value);

	return value;
}

unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
{
	uint16_t value;

	pci_hose_read_config_word(get_hose(), dev, where, &value);

	return value;
}

unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
{
	uint32_t value;

	pci_hose_read_config_dword(get_hose(), dev, where, &value);

	return value;
}

void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
{
	pci_hose_write_config_byte(get_hose(), dev, where, value);
}

void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
{
	pci_hose_write_config_word(get_hose(), dev, where, value);
}

void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
{
	pci_hose_write_config_dword(get_hose(), dev, where, value);
}

int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
			ulong *valuep, enum pci_size_t size)
{
	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
	switch (size) {
	case PCI_SIZE_8:
		*valuep = inb(PCI_REG_DATA + (offset & 3));
		break;
	case PCI_SIZE_16:
		*valuep = inw(PCI_REG_DATA + (offset & 2));
		break;
	case PCI_SIZE_32:
		*valuep = inl(PCI_REG_DATA);
		break;
	}

	return 0;
}

int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
			 ulong value, enum pci_size_t size)
{
	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
	switch (size) {
	case PCI_SIZE_8:
		outb(value, PCI_REG_DATA + (offset & 3));
		break;
	case PCI_SIZE_16:
		outw(value, PCI_REG_DATA + (offset & 2));
		break;
	case PCI_SIZE_32:
		outl(value, PCI_REG_DATA);
		break;
	}

	return 0;
}

void pci_assign_irqs(int bus, int device, u8 irq[4])
{
	pci_dev_t bdf;
	int func;
	u16 vendor;
	u8 pin, line;

	for (func = 0; func < 8; func++) {
		bdf = PCI_BDF(bus, device, func);
		vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
		if (vendor == 0xffff || vendor == 0x0000)
			continue;

		pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);

		/* PCI spec says all values except 1..4 are reserved */
		if ((pin < 1) || (pin > 4))
			continue;

		line = irq[pin - 1];
		if (!line)
			continue;

		debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
		      line, bus, device, func, 'A' + pin - 1);

		x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
	}
}