1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
#include <common.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <cache.h>
#include <asm/csr.h>
#ifdef CONFIG_RISCV_NDS_CACHE
/* mcctlcommand */
#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
/* D-cache operation */
#define CCTL_L1D_WBINVAL_ALL 6
#endif
void flush_dcache_all(void)
{
#ifdef CONFIG_RISCV_NDS_CACHE
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
#endif
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
flush_dcache_all();
}
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
flush_dcache_all();
}
void icache_enable(void)
{
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x1\n\t"
"csrw mcache_ctl, t0\n\t"
);
#endif
#endif
}
void icache_disable(void)
{
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x1\n\t"
"csrw mcache_ctl, t0\n\t"
);
#endif
#endif
}
void dcache_enable(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
struct udevice *dev = NULL;
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
uclass_find_first_device(UCLASS_CACHE, &dev);
if (dev)
cache_enable(dev);
#endif
#endif
}
void dcache_disable(void)
{
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
struct udevice *dev = NULL;
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
uclass_find_first_device(UCLASS_CACHE, &dev);
if (dev)
cache_disable(dev);
#endif
#endif
}
int icache_status(void)
{
int ret = 0;
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x01\n\t"
: "=r" (ret)
:
: "memory"
);
#endif
return ret;
}
int dcache_status(void)
{
int ret = 0;
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi %0, t1, 0x02\n\t"
: "=r" (ret)
:
: "memory"
);
#endif
return ret;
}
|
