summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
blob: 9b7181d5b6ff09443c6aafb137fb7ec715326fa0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
/*
 * Copyright 2009-2010 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/fsl_law.h>
#include <pci.h>

struct pci_info {
	u32	cfg;
};

/* The cfg field is a bit mask in which each bit represents the value of
 * cfg_IO_ports[] signal and the bit is set if the interface would be
 * enabled based on the value of cfg_IO_ports[] signal
 *
 * On MPC86xx/PQ3 based systems:
 *   we extract cfg_IO_ports from GUTS register PORDEVSR
 *
 * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
 * without PCIe)
 */

#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCI] = {
		.cfg =   0,
	},
};
#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCI] = {
		.cfg =   0,
	},
};
#elif defined(CONFIG_MPC8536)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCI] = {
		.cfg =   0,
	},
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
	},
	[LAW_TRGT_IF_PCIE_2] = {
		.cfg =   (1 << 5) | (1 << 7),
	},
	[LAW_TRGT_IF_PCIE_3] = {
		.cfg =   (1 << 7),
	},
};
#elif defined(CONFIG_MPC8544)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCI] = {
		.cfg =   0,
	},
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
			 (1 << 6) | (1 << 7),
	},
	[LAW_TRGT_IF_PCIE_2] = {
		.cfg =   (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
	},
	[LAW_TRGT_IF_PCIE_3] = {
		.cfg =   (1 << 6) | (1 << 7),
	},
};
#elif defined(CONFIG_MPC8548)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCI_1] = {
		.cfg =   0,
	},
	[LAW_TRGT_IF_PCI_2] = {
		.cfg =   0,
	},
	/* PCI_2 is always host and we dont use iosel to determine enable/disable */
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
	},
};
#elif defined(CONFIG_MPC8568)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCI] = {
		.cfg =   0,
	},
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
	},
};
#elif defined(CONFIG_MPC8569)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
			 (1 << 8) | (1 << 0xc) | (1 << 0xf),
	},
};
#elif defined(CONFIG_MPC8572)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 2) | (1 << 3) | (1 << 7) |
			 (1 << 0xb) | (1 << 0xc) | (1 << 0xf),
	},
	[LAW_TRGT_IF_PCIE_2] = {
		.cfg =   (1 << 3) | (1 << 7),
	},
	[LAW_TRGT_IF_PCIE_3] = {
		.cfg =   (1 << 7),
	},
};
#elif defined(CONFIG_MPC8610)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCI_1] = {
		.cfg =   0,
	},
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 1) | (1 << 4),
	},
	[LAW_TRGT_IF_PCIE_2] = {
		.cfg =   (1 << 0) | (1 << 4),
	},
};
#elif defined(CONFIG_MPC8641)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
			 (1 << 7) | (1 << 0xe) | (1 << 0xf),
	},
};
#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
      defined(CONFIG_P1012) || defined(CONFIG_P1021)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
	},
	[LAW_TRGT_IF_PCIE_2] = {
		.cfg =   (1 << 0xe),
	},
};
#elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
			 (1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
			 (1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
			 (1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
			 (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
			 (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
	},
	[LAW_TRGT_IF_PCIE_2] = {
		.cfg =   (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
			 (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
			 (1 << 0x18) | (1 << 0x1c),
	},
	[LAW_TRGT_IF_PCIE_3] = {
		.cfg =   (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
			 (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
			 (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
	},
};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
static struct pci_info pci_config_info[] =
{
	[LAW_TRGT_IF_PCIE_1] = {
		.cfg =   (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
			 (1 << 0xd) | (1 << 0xe) | (1 << 0xf),
	},
	[LAW_TRGT_IF_PCIE_2] = {
		.cfg =   (1 << 2) | (1 << 0xe),
	},
	[LAW_TRGT_IF_PCIE_3] = {
		.cfg =   (1 << 2) | (1 << 4),
	},
};
#elif defined(CONFIG_FSL_CORENET)
#else
#error Need to define pci_config_info for processor
#endif

#ifndef CONFIG_FSL_CORENET
int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
{
	return ((1 << io_sel) & pci_config_info[trgt].cfg);
}
#endif