summaryrefslogtreecommitdiff
path: root/arch/arm/mach-mvebu/include/mach/soc.h
blob: cb216bc2cc61d5c2a14139d4538afcaefa43f70a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * Header file for the Marvell's Feroceon CPU core.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H

#define SOC_MV78230_ID		0x7823
#define SOC_MV78260_ID		0x7826
#define SOC_MV78460_ID		0x7846
#define SOC_88F6810_ID		0x6810
#define SOC_88F6820_ID		0x6820
#define SOC_88F6828_ID		0x6828

/* A38x revisions */
#define MV_88F68XX_Z1_ID	0x0
#define MV_88F68XX_A0_ID	0x4

/* TCLK Core Clock definition */
#ifndef CONFIG_SYS_TCLK
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
#endif

/* Armada XP PLL frequency (used for NAND clock generation) */
#define CONFIG_SYS_MVEBU_PLL_CLOCK	2000000000

/* SOC specific definations */
#define INTREG_BASE		0xd0000000
#define INTREG_BASE_ADDR_REG	(INTREG_BASE + 0x20080)
#if defined(CONFIG_SPL_BUILD)
/*
 * The SPL U-Boot version still runs with the default
 * address for the internal registers, configured by
 * the BootROM. Only the main U-Boot version uses the
 * new internal register base address, that also is
 * required for the Linux kernel.
 */
#define SOC_REGS_PHY_BASE	0xd0000000
#else
#define SOC_REGS_PHY_BASE	0xf1000000
#endif
#define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)

#define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
#define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
#define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
#define MVEBU_MPP_BASE		(MVEBU_REGISTER(0x18000))
#define MVEBU_GPIO0_BASE	(MVEBU_REGISTER(0x18100))
#define MVEBU_GPIO1_BASE	(MVEBU_REGISTER(0x18140))
#define MVEBU_GPIO2_BASE	(MVEBU_REGISTER(0x18180))
#define MVEBU_SYSTEM_REG_BASE	(MVEBU_REGISTER(0x18200))
#define MVEBU_CLOCK_BASE	(MVEBU_REGISTER(0x18700))
#define MVEBU_CPU_WIN_BASE	(MVEBU_REGISTER(0x20000))
#define MVEBU_SDRAM_BASE	(MVEBU_REGISTER(0x20180))
#define MVEBU_TIMER_BASE	(MVEBU_REGISTER(0x20300))
#define MVEBU_REG_PCIE_BASE	(MVEBU_REGISTER(0x40000))
#define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
#define MVEBU_USB20_BASE	(MVEBU_REGISTER(0x58000))
#define MVEBU_AXP_SATA_BASE	(MVEBU_REGISTER(0xa0000))
#define MVEBU_SATA0_BASE	(MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE		(MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))

#define SOC_COHERENCY_FABRIC_CTRL_REG	(MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN	(1 << 8)

#define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
#define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))

#define MVEBU_SOC_DEV_MUX_REG	(MVEBU_SYSTEM_REG_BASE + 0x08)
#define NAND_EN			BIT(0)
#define NAND_ARBITER_EN		BIT(27)

#define ARMADA_XP_PUP_ENABLE	(MVEBU_SYSTEM_REG_BASE + 0x44c)
#define GE0_PUP_EN		BIT(0)
#define GE1_PUP_EN		BIT(1)
#define LCD_PUP_EN		BIT(2)
#define NAND_PUP_EN		BIT(4)
#define SPI_PUP_EN		BIT(5)

#define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
#define NAND_ECC_DIVCKL_RATIO_OFFS	8
#define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)

#define SDRAM_MAX_CS		4
#define SDRAM_ADDR_MASK		0xFF000000

/* MVEBU CPU memory windows */
#define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
#define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
#define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE

#define COMPHY_REFCLK_ALIGNMENT	(MVEBU_REGISTER(0x182f8))

/* BootROM error register (also includes some status infos) */
#define CONFIG_BOOTROM_ERR_REG	(MVEBU_REGISTER(0x182d0))
#define BOOTROM_ERR_MODE_OFFS	28
#define BOOTROM_ERR_MODE_MASK	(0xf << BOOTROM_ERR_MODE_OFFS)
#define BOOTROM_ERR_MODE_UART	0x6

#if defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
#define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18600))

#define SAR_CPU_FREQ_OFFS	10
#define SAR_CPU_FREQ_MASK	(0x1f << SAR_CPU_FREQ_OFFS)
#define SAR_BOOT_DEVICE_OFFS	4
#define SAR_BOOT_DEVICE_MASK	(0x1f << SAR_BOOT_DEVICE_OFFS)

#define BOOT_DEV_SEL_OFFS	4
#define BOOT_DEV_SEL_MASK	(0x3f << BOOT_DEV_SEL_OFFS)

#define BOOT_FROM_UART		0x28
#define BOOT_FROM_SPI		0x32
#define BOOT_FROM_MMC		0x30
#define BOOT_FROM_MMC_ALT	0x31
#else
/* SAR values for Armada XP */
#define CONFIG_SAR_REG		(MVEBU_REGISTER(0x18230))
#define CONFIG_SAR2_REG		(MVEBU_REGISTER(0x18234))

#define SAR_CPU_FREQ_OFFS	21
#define SAR_CPU_FREQ_MASK	(0x7 << SAR_CPU_FREQ_OFFS)
#define SAR_FFC_FREQ_OFFS	24
#define SAR_FFC_FREQ_MASK	(0xf << SAR_FFC_FREQ_OFFS)
#define SAR2_CPU_FREQ_OFFS	20
#define SAR2_CPU_FREQ_MASK	(0x1 << SAR2_CPU_FREQ_OFFS)
#define SAR_BOOT_DEVICE_OFFS	5
#define SAR_BOOT_DEVICE_MASK	(0xf << SAR_BOOT_DEVICE_OFFS)

#define BOOT_DEV_SEL_OFFS	5
#define BOOT_DEV_SEL_MASK	(0xf << BOOT_DEV_SEL_OFFS)

#define BOOT_FROM_UART		0x2
#define BOOT_FROM_SPI		0x3
#endif

#endif /* _MVEBU_SOC_H */