summaryrefslogtreecommitdiff
path: root/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
blob: 15f53dd35bee3baeb48f59a11f300e7a648745c1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
/*
 * (C) Copyright 2003
 * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************
 * NAME	    : s3c24x0.h
 * Version  : 31.3.2003
 *
 * common stuff for SAMSUNG S3C24X0 SoC
 ************************************************/

#ifndef __S3C24X0_H__
#define __S3C24X0_H__

/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
	u32	BWSCON;
	u32	BANKCON[8];
	u32	REFRESH;
	u32	BANKSIZE;
	u32	MRSRB6;
	u32	MRSRB7;
};


/* USB HOST (see manual chapter 12) */
struct s3c24x0_usb_host {
	u32	HcRevision;
	u32	HcControl;
	u32	HcCommonStatus;
	u32	HcInterruptStatus;
	u32	HcInterruptEnable;
	u32	HcInterruptDisable;
	u32	HcHCCA;
	u32	HcPeriodCuttendED;
	u32	HcControlHeadED;
	u32	HcControlCurrentED;
	u32	HcBulkHeadED;
	u32	HcBuldCurrentED;
	u32	HcDoneHead;
	u32	HcRmInterval;
	u32	HcFmRemaining;
	u32	HcFmNumber;
	u32	HcPeriodicStart;
	u32	HcLSThreshold;
	u32	HcRhDescriptorA;
	u32	HcRhDescriptorB;
	u32	HcRhStatus;
	u32	HcRhPortStatus1;
	u32	HcRhPortStatus2;
};


/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
	u32	SRCPND;
	u32	INTMOD;
	u32	INTMSK;
	u32	PRIORITY;
	u32	INTPND;
	u32	INTOFFSET;
#ifdef CONFIG_S3C2410
	u32	SUBSRCPND;
	u32	INTSUBMSK;
#endif
};


/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
	u32	DISRC;
#ifdef CONFIG_S3C2410
	u32	DISRCC;
#endif
	u32	DIDST;
#ifdef CONFIG_S3C2410
	u32	DIDSTC;
#endif
	u32	DCON;
	u32	DSTAT;
	u32	DCSRC;
	u32	DCDST;
	u32	DMASKTRIG;
#ifdef CONFIG_S3C2400
	u32	res[1];
#endif
#ifdef CONFIG_S3C2410
	u32	res[7];
#endif
};

struct s3c24x0_dmas {
	struct s3c24x0_dma	dma[4];
};


/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/*                          (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
	u32	LOCKTIME;
	u32	MPLLCON;
	u32	UPLLCON;
	u32	CLKCON;
	u32	CLKSLOW;
	u32	CLKDIVN;
};


/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
	u32	LCDCON1;
	u32	LCDCON2;
	u32	LCDCON3;
	u32	LCDCON4;
	u32	LCDCON5;
	u32	LCDSADDR1;
	u32	LCDSADDR2;
	u32	LCDSADDR3;
	u32	REDLUT;
	u32	GREENLUT;
	u32	BLUELUT;
	u32	res[8];
	u32	DITHMODE;
	u32	TPAL;
#ifdef CONFIG_S3C2410
	u32	LCDINTPND;
	u32	LCDSRCPND;
	u32	LCDINTMSK;
	u32	LPCSEL;
#endif
};


/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
	u32	NFCONF;
	u32	NFCMD;
	u32	NFADDR;
	u32	NFDATA;
	u32	NFSTAT;
	u32	NFECC;
};


/* UART (see manual chapter 11) */
struct s3c24x0_uart {
	u32	ULCON;
	u32	UCON;
	u32	UFCON;
	u32	UMCON;
	u32	UTRSTAT;
	u32	UERSTAT;
	u32	UFSTAT;
	u32	UMSTAT;
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	UTXH;
	u8	res2[3];
	u8	URXH;
#else /* Little Endian */
	u8	UTXH;
	u8	res1[3];
	u8	URXH;
	u8	res2[3];
#endif
	u32	UBRDIV;
};


/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
	u32	TCNTB;
	u32	TCMPB;
	u32	TCNTO;
};

struct s3c24x0_timers {
	u32	TCFG0;
	u32	TCFG1;
	u32	TCON;
	struct s3c24x0_timer	ch[4];
	u32	TCNTB4;
	u32	TCNTO4;
};


/* USB DEVICE (see manual chapter 13) */
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
	u8	res[3];
	u8	EP_FIFO_REG;
#else /*  little endian */
	u8	EP_FIFO_REG;
	u8	res[3];
#endif
};

struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	EP_DMA_CON;
	u8	res2[3];
	u8	EP_DMA_UNIT;
	u8	res3[3];
	u8	EP_DMA_FIFO;
	u8	res4[3];
	u8	EP_DMA_TTC_L;
	u8	res5[3];
	u8	EP_DMA_TTC_M;
	u8	res6[3];
	u8	EP_DMA_TTC_H;
#else /*  little endian */
	u8	EP_DMA_CON;
	u8	res1[3];
	u8	EP_DMA_UNIT;
	u8	res2[3];
	u8	EP_DMA_FIFO;
	u8	res3[3];
	u8	EP_DMA_TTC_L;
	u8	res4[3];
	u8	EP_DMA_TTC_M;
	u8	res5[3];
	u8	EP_DMA_TTC_H;
	u8	res6[3];
#endif
};

struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	FUNC_ADDR_REG;
	u8	res2[3];
	u8	PWR_REG;
	u8	res3[3];
	u8	EP_INT_REG;
	u8	res4[15];
	u8	USB_INT_REG;
	u8	res5[3];
	u8	EP_INT_EN_REG;
	u8	res6[15];
	u8	USB_INT_EN_REG;
	u8	res7[3];
	u8	FRAME_NUM1_REG;
	u8	res8[3];
	u8	FRAME_NUM2_REG;
	u8	res9[3];
	u8	INDEX_REG;
	u8	res10[7];
	u8	MAXP_REG;
	u8	res11[3];
	u8	EP0_CSR_IN_CSR1_REG;
	u8	res12[3];
	u8	IN_CSR2_REG;
	u8	res13[7];
	u8	OUT_CSR1_REG;
	u8	res14[3];
	u8	OUT_CSR2_REG;
	u8	res15[3];
	u8	OUT_FIFO_CNT1_REG;
	u8	res16[3];
	u8	OUT_FIFO_CNT2_REG;
#else /*  little endian */
	u8	FUNC_ADDR_REG;
	u8	res1[3];
	u8	PWR_REG;
	u8	res2[3];
	u8	EP_INT_REG;
	u8	res3[15];
	u8	USB_INT_REG;
	u8	res4[3];
	u8	EP_INT_EN_REG;
	u8	res5[15];
	u8	USB_INT_EN_REG;
	u8	res6[3];
	u8	FRAME_NUM1_REG;
	u8	res7[3];
	u8	FRAME_NUM2_REG;
	u8	res8[3];
	u8	INDEX_REG;
	u8	res9[7];
	u8	MAXP_REG;
	u8	res10[7];
	u8	EP0_CSR_IN_CSR1_REG;
	u8	res11[3];
	u8	IN_CSR2_REG;
	u8	res12[3];
	u8	OUT_CSR1_REG;
	u8	res13[7];
	u8	OUT_CSR2_REG;
	u8	res14[3];
	u8	OUT_FIFO_CNT1_REG;
	u8	res15[3];
	u8	OUT_FIFO_CNT2_REG;
	u8	res16[3];
#endif /*  __BIG_ENDIAN */
	struct s3c24x0_usb_dev_fifos	fifo[5];
	struct s3c24x0_usb_dev_dmas	dma[5];
};


/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
	u32	WTCON;
	u32	WTDAT;
	u32	WTCNT;
};


/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
	u32	IICCON;
	u32	IICSTAT;
	u32	IICADD;
	u32	IICDS;
};


/* IIS (see manual chapter 21) */
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
	u16	res1;
	u16	IISCON;
	u16	res2;
	u16	IISMOD;
	u16	res3;
	u16	IISPSR;
	u16	res4;
	u16	IISFCON;
	u16	res5;
	u16	IISFIFO;
#else /*  little endian */
	u16	IISCON;
	u16	res1;
	u16	IISMOD;
	u16	res2;
	u16	IISPSR;
	u16	res3;
	u16	IISFCON;
	u16	res4;
	u16	IISFIFO;
	u16	res5;
#endif
};


/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
	u32	PACON;
	u32	PADAT;

	u32	PBCON;
	u32	PBDAT;
	u32	PBUP;

	u32	PCCON;
	u32	PCDAT;
	u32	PCUP;

	u32	PDCON;
	u32	PDDAT;
	u32	PDUP;

	u32	PECON;
	u32	PEDAT;
	u32	PEUP;

	u32	PFCON;
	u32	PFDAT;
	u32	PFUP;

	u32	PGCON;
	u32	PGDAT;
	u32	PGUP;

	u32	OPENCR;

	u32	MISCCR;
	u32	EXTINT;
#endif
#ifdef CONFIG_S3C2410
	u32	GPACON;
	u32	GPADAT;
	u32	res1[2];
	u32	GPBCON;
	u32	GPBDAT;
	u32	GPBUP;
	u32	res2;
	u32	GPCCON;
	u32	GPCDAT;
	u32	GPCUP;
	u32	res3;
	u32	GPDCON;
	u32	GPDDAT;
	u32	GPDUP;
	u32	res4;
	u32	GPECON;
	u32	GPEDAT;
	u32	GPEUP;
	u32	res5;
	u32	GPFCON;
	u32	GPFDAT;
	u32	GPFUP;
	u32	res6;
	u32	GPGCON;
	u32	GPGDAT;
	u32	GPGUP;
	u32	res7;
	u32	GPHCON;
	u32	GPHDAT;
	u32	GPHUP;
	u32	res8;

	u32	MISCCR;
	u32	DCLKCON;
	u32	EXTINT0;
	u32	EXTINT1;
	u32	EXTINT2;
	u32	EINTFLT0;
	u32	EINTFLT1;
	u32	EINTFLT2;
	u32	EINTFLT3;
	u32	EINTMASK;
	u32	EINTPEND;
	u32	GSTATUS0;
	u32	GSTATUS1;
	u32	GSTATUS2;
	u32	GSTATUS3;
	u32	GSTATUS4;
#endif
};


/* RTC (see manual chapter 17) */
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
	u8	res1[67];
	u8	RTCCON;
	u8	res2[3];
	u8	TICNT;
	u8	res3[11];
	u8	RTCALM;
	u8	res4[3];
	u8	ALMSEC;
	u8	res5[3];
	u8	ALMMIN;
	u8	res6[3];
	u8	ALMHOUR;
	u8	res7[3];
	u8	ALMDATE;
	u8	res8[3];
	u8	ALMMON;
	u8	res9[3];
	u8	ALMYEAR;
	u8	res10[3];
	u8	RTCRST;
	u8	res11[3];
	u8	BCDSEC;
	u8	res12[3];
	u8	BCDMIN;
	u8	res13[3];
	u8	BCDHOUR;
	u8	res14[3];
	u8	BCDDATE;
	u8	res15[3];
	u8	BCDDAY;
	u8	res16[3];
	u8	BCDMON;
	u8	res17[3];
	u8	BCDYEAR;
#else /*  little endian */
	u8	res0[64];
	u8	RTCCON;
	u8	res1[3];
	u8	TICNT;
	u8	res2[11];
	u8	RTCALM;
	u8	res3[3];
	u8	ALMSEC;
	u8	res4[3];
	u8	ALMMIN;
	u8	res5[3];
	u8	ALMHOUR;
	u8	res6[3];
	u8	ALMDATE;
	u8	res7[3];
	u8	ALMMON;
	u8	res8[3];
	u8	ALMYEAR;
	u8	res9[3];
	u8	RTCRST;
	u8	res10[3];
	u8	BCDSEC;
	u8	res11[3];
	u8	BCDMIN;
	u8	res12[3];
	u8	BCDHOUR;
	u8	res13[3];
	u8	BCDDATE;
	u8	res14[3];
	u8	BCDDAY;
	u8	res15[3];
	u8	BCDMON;
	u8	res16[3];
	u8	BCDYEAR;
	u8	res17[3];
#endif
};


/* ADC (see manual chapter 16) */
struct s3c2400_adc {
	u32	ADCCON;
	u32	ADCDAT;
};


/* ADC (see manual chapter 16) */
struct s3c2410_adc {
	u32	ADCCON;
	u32	ADCTSC;
	u32	ADCDLY;
	u32	ADCDAT0;
	u32	ADCDAT1;
};


/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
	u8	SPCON;
	u8	res1[3];
	u8	SPSTA;
	u8	res2[3];
	u8	SPPIN;
	u8	res3[3];
	u8	SPPRE;
	u8	res4[3];
	u8	SPTDAT;
	u8	res5[3];
	u8	SPRDAT;
	u8	res6[3];
	u8	res7[16];
};

struct s3c24x0_spi {
	struct s3c24x0_spi_channel	ch[S3C24X0_SPI_CHANNELS];
};


/* MMC INTERFACE (see S3C2400 manual chapter 19) */
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	MMCON;
	u8	res2[3];
	u8	MMCRR;
	u8	res3[3];
	u8	MMFCON;
	u8	res4[3];
	u8	MMSTA;
	u16	res5;
	u16	MMFSTA;
	u8	res6[3];
	u8	MMPRE;
	u16	res7;
	u16	MMLEN;
	u8	res8[3];
	u8	MMCR7;
	u32	MMRSP[4];
	u8	res9[3];
	u8	MMCMD0;
	u32	MMCMD1;
	u16	res10;
	u16	MMCR16;
	u8	res11[3];
	u8	MMDAT;
#else
	u8	MMCON;
	u8	res1[3];
	u8	MMCRR;
	u8	res2[3];
	u8	MMFCON;
	u8	res3[3];
	u8	MMSTA;
	u8	res4[3];
	u16	MMFSTA;
	u16	res5;
	u8	MMPRE;
	u8	res6[3];
	u16	MMLEN;
	u16	res7;
	u8	MMCR7;
	u8	res8[3];
	u32	MMRSP[4];
	u8	MMCMD0;
	u8	res9[3];
	u32	MMCMD1;
	u16	MMCR16;
	u16	res10;
	u8	MMDAT;
	u8	res11[3];
#endif
};


/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
	u32	SDICON;
	u32	SDIPRE;
	u32	SDICARG;
	u32	SDICCON;
	u32	SDICSTA;
	u32	SDIRSP0;
	u32	SDIRSP1;
	u32	SDIRSP2;
	u32	SDIRSP3;
	u32	SDIDTIMER;
	u32	SDIBSIZE;
	u32	SDIDCON;
	u32	SDIDCNT;
	u32	SDIDSTA;
	u32	SDIFSTA;
#ifdef __BIG_ENDIAN
	u8	res[3];
	u8	SDIDAT;
#else
	u8	SDIDAT;
	u8	res[3];
#endif
	u32	SDIIMSK;
};

#endif /*__S3C24X0_H__*/