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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 NXP
*/
/dts-v1/;
#include "imx8ulp-evk.dts"
#include "imx8ulp-evk-u-boot.dtsi"
/ {
model = "NXP i.MX8ULP 9X9 EVK";
};
&{/soc@0/bus@2d800000/dsi@2db00000/panel@0} {
reset-gpios = <&gpiof 21 GPIO_ACTIVE_LOW>;
};
&pinctrl_dsi {
fsl,pins = <
MX8ULP_PAD_PTF21__PTF21 0x3
>;
};
&pinctrl_enet {
fsl,pins = <
MX8ULP_PAD_PTF9__ENET0_MDC 0x43
MX8ULP_PAD_PTF8__ENET0_MDIO 0x43
MX8ULP_PAD_PTF5__ENET0_RXER 0x43
MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43
MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
MX8ULP_PAD_PTF0__ENET0_RXD1 0x43
MX8ULP_PAD_PTF4__ENET0_TXEN 0x43
MX8ULP_PAD_PTF3__ENET0_TXD0 0x43
MX8ULP_PAD_PTF2__ENET0_TXD1 0x43
MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43
MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
};
&pinctrl_otgid1 {
fsl,pins = <
MX8ULP_PAD_PTE16__USB0_ID 0x10003
MX8ULP_PAD_PTE18__USB0_OC 0x10003
>;
};
&pinctrl_otgid2 {
fsl,pins = <
MX8ULP_PAD_PTD23__USB1_ID 0x10003
MX8ULP_PAD_PTE20__USB1_OC 0x10003
>;
};
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