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|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
/ {
model = "NXP i.MX8DXL PHANTOM MEK";
compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
chosen {
bootargs = "console=ttyLP0,115200 earlycon";
stdout-path = &lpuart0;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
epdev_on: fixedregulator@100 {
compatible = "regulator-fixed";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_wlreg_on>;
pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "epdev_on";
gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx8qxp-mek {
pinctrl_hog: hoggrp {
fsl,pins = <
SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c
SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
SC_P_ENET0_MDC_CONN_ENET1_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020
SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x00000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021
SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
>;
};
pinctrl_pcieb: pcieagrp{
fsl,pins = <
SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021
>;
};
pinctrl_wlreg_on: wlregongrp{
fsl,pins = <
SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x06000000
>;
};
pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
fsl,pins = <
SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x07800000
>;
};
};
};
&A35_0 {
u-boot,dm-pre-reloc;
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&gpio4 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt35xu512aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <8>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <®_usdhc2_vmmc>;
status = "okay";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii";
phy-handle = <ðphy0>;
fsl,ar8031-phy-fixup;
fsl,magic-packet;
status = "okay";
phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
phy-reset-duration = <10>;
phy-reset-post-delay = <150>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
srp-disable;
hnp-disable;
adp-disable;
power-polarity-active-high;
disable-over-current;
status = "okay";
};
&pcieb{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
epdev_on = <&epdev_on>;
ext_osc = <1>;
status = "okay";
};
|