/*
 * Copyright 2018 NXP
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __DTS_IMX8MN_PINFUNC_H
#define __DTS_IMX8MN_PINFUNC_H

/*
 * The pin function ID is a tuple of
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */
#define MX8MN_IOMUXC_BOOT_MODE2__CCMSRCGPCMIX_BOOT_MODE2                        0x0020 0x025C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_BOOT_MODE2__I2C1_SCL                                       0x0020 0x025C 0x055C 0x1 0x3
#define MX8MN_IOMUXC_BOOT_MODE3__CCMSRCGPCMIX_BOOT_MODE3                        0x0024 0x0260 0x0000 0x0 0x0
#define MX8MN_IOMUXC_BOOT_MODE3__I2C1_SDA                                       0x0024 0x0260 0x056C 0x1 0x3
#define MX8MN_IOMUXC_GPIO1_IO00__GPIO1_IO0                                      0x0028 0x0290 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT             0x0028 0x0290 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO00__ANAMIX_REF_CLK_32K                             0x0028 0x0290 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1                          0x0028 0x0290 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO01__GPIO1_IO1                                      0x002C 0x0294 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO01__PWM1_OUT                                       0x002C 0x0294 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO01__ANAMIX_REF_CLK_24M                             0x002C 0x0294 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2                          0x002C 0x0294 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO02__GPIO1_IO2                                      0x0030 0x0298 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B                                   0x0030 0x0298 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY                                 0x0030 0x0298 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO03__GPIO1_IO3                                      0x0034 0x029C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO03__USDHC1_VSELECT                                 0x0034 0x029C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT0                               0x0034 0x029C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO03__ANAMIX_XTAL_OK                                 0x0034 0x029C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO04__GPIO1_IO4                                      0x0038 0x02A0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                                 0x0038 0x02A0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT1                               0x0038 0x02A0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO04__ANAMIX_XTAL_OK_LV                              0x0038 0x02A0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO05__GPIO1_IO5                                      0x003C 0x02A4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO05__M4_NMI                                         0x003C 0x02A4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY                        0x003C 0x02A4 0x04BC 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT                          0x003C 0x02A4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO06__GPIO1_IO6                                      0x0040 0x02A8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO06__ENET1_MDC                                      0x0040 0x02A8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO06__USDHC1_CD_B                                    0x0040 0x02A8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3                          0x0040 0x02A8 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO07__GPIO1_IO7                                      0x0044 0x02AC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO07__ENET1_MDIO                                     0x0044 0x02AC 0x04C0 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO07__USDHC1_WP                                      0x0044 0x02AC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4                          0x0044 0x02AC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO08__GPIO1_IO8                                      0x0048 0x02B0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO08__ENET1_1588_EVENT0_IN                           0x0048 0x02B0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO08__PWM1_OUT                                       0x0048 0x02B0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO08__USDHC2_RESET_B                                 0x0048 0x02B0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO08__CCMSRCGPCMIX_WAIT                              0x0048 0x02B0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO09__GPIO1_IO9                                      0x004C 0x02B4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO09__ENET1_1588_EVENT0_OUT                          0x004C 0x02B4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO09__PWM2_OUT                                       0x004C 0x02B4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO09__USDHC3_RESET_B                                 0x004C 0x02B4 0x0000 0x4 0x0
#define MX8MN_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT0                               0x004C 0x02B4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO09__CCMSRCGPCMIX_STOP                              0x004C 0x02B4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO10__GPIO1_IO10                                     0x0050 0x02B8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO10__USB1_OTG_ID                                    0x0050 0x02B8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO10__PWM3_OUT                                       0x0050 0x02B8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO11__GPIO1_IO11                                     0x0054 0x02BC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO11__PWM2_OUT                                       0x0054 0x02BC 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO11__USDHC3_VSELECT                                 0x0054 0x02BC 0x0000 0x4 0x0
#define MX8MN_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY                        0x0054 0x02BC 0x04BC 0x5 0x1
#define MX8MN_IOMUXC_GPIO1_IO11__CCMSRCGPCMIX_OUT0                              0x0054 0x02BC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO12__GPIO1_IO12                                     0x0058 0x02C0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO12__USB1_OTG_PWR                                   0x0058 0x02C0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT1                               0x0058 0x02C0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO12__CCMSRCGPCMIX_OUT1                              0x0058 0x02C0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO13__GPIO1_IO13                                     0x005C 0x02C4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO13__USB1_OTG_OC                                    0x005C 0x02C4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO13__PWM2_OUT                                       0x005C 0x02C4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO13__CCMSRCGPCMIX_OUT2                              0x005C 0x02C4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO14__GPIO1_IO14                                     0x0060 0x02C8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO14__USDHC3_CD_B                                    0x0060 0x02C8 0x0598 0x4 0x2
#define MX8MN_IOMUXC_GPIO1_IO14__PWM3_OUT                                       0x0060 0x02C8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO14__CCMSRCGPCMIX_CLKO1                             0x0060 0x02C8 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO15__GPIO1_IO15                                     0x0064 0x02CC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO15__USDHC3_WP                                      0x0064 0x02CC 0x05B8 0x4 0x2
#define MX8MN_IOMUXC_GPIO1_IO15__PWM4_OUT                                       0x0064 0x02CC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO15__CCMSRCGPCMIX_CLKO2                             0x0064 0x02CC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_ENET_MDC__ENET1_MDC                                        0x0068 0x02D0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_MDC__SAI6_TX_DATA0                                    0x0068 0x02D0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_MDC__PDM_BIT_STREAM3                                  0x0068 0x02D0 0x0540 0x3 0x1
#define MX8MN_IOMUXC_ENET_MDC__SPDIF1_OUT                                       0x0068 0x02D0 0x0000 0x4 0x0
#define MX8MN_IOMUXC_ENET_MDC__GPIO1_IO16                                       0x0068 0x02D0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_MDC__USDHC3_STROBE                                    0x0068 0x02D0 0x059C 0x6 0x1
#define MX8MN_IOMUXC_ENET_MDIO__ENET1_MDIO                                      0x006C 0x02D4 0x04C0 0x0 0x1
#define MX8MN_IOMUXC_ENET_MDIO__SAI6_TX_SYNC                                    0x006C 0x02D4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_MDIO__PDM_BIT_STREAM2                                 0x006C 0x02D4 0x053C 0x3 0x1
#define MX8MN_IOMUXC_ENET_MDIO__SPDIF1_IN                                       0x006C 0x02D4 0x05CC 0x4 0x1
#define MX8MN_IOMUXC_ENET_MDIO__GPIO1_IO17                                      0x006C 0x02D4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_MDIO__USDHC3_DATA5                                    0x006C 0x02D4 0x0550 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD3__ENET1_RGMII_TD3                                  0x0070 0x02D8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD3__SAI6_TX_BCLK                                     0x0070 0x02D8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD3__PDM_BIT_STREAM1                                  0x0070 0x02D8 0x0538 0x3 0x1
#define MX8MN_IOMUXC_ENET_TD3__SPDIF1_EXT_CLK                                   0x0070 0x02D8 0x0568 0x4 0x1
#define MX8MN_IOMUXC_ENET_TD3__GPIO1_IO18                                       0x0070 0x02D8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD3__USDHC3_DATA6                                     0x0070 0x02D8 0x0584 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD2__ENET1_RGMII_TD2                                  0x0074 0x02DC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD2__ENET1_TX_CLK                                     0x0074 0x02DC 0x05A4 0x1 0x0
#define MX8MN_IOMUXC_ENET_TD2__CCMSRCGPCMIX_ENET_REF_CLK_ROOT                   0x0074 0x02DC 0x05A4 0x1 0x0
#define MX8MN_IOMUXC_ENET_TD2__SAI6_RX_DATA0                                    0x0074 0x02DC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD2__PDM_BIT_STREAM3                                  0x0074 0x02DC 0x0540 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD2__GPIO1_IO19                                       0x0074 0x02DC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD2__USDHC3_DATA7                                     0x0074 0x02DC 0x054C 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD1__ENET1_RGMII_TD1                                  0x0078 0x02E0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD1__SAI6_RX_SYNC                                     0x0078 0x02E0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD1__PDM_BIT_STREAM2                                  0x0078 0x02E0 0x053C 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD1__GPIO1_IO20                                       0x0078 0x02E0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD1__USDHC3_CD_B                                      0x0078 0x02E0 0x0598 0x6 0x3
#define MX8MN_IOMUXC_ENET_TD0__ENET1_RGMII_TD0                                  0x007C 0x02E4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD0__SAI6_RX_BCLK                                     0x007C 0x02E4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD0__PDM_BIT_STREAM1                                  0x007C 0x02E4 0x0538 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD0__GPIO1_IO21                                       0x007C 0x02E4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD0__USDHC3_WP                                        0x007C 0x02E4 0x05B8 0x6 0x3
#define MX8MN_IOMUXC_ENET_TX_CTL__ENET1_RGMII_TX_CTL                            0x0080 0x02E8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL__SAI6_MCLK                                     0x0080 0x02E8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL__GPIO1_IO22                                    0x0080 0x02E8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL__USDHC3_DATA0                                  0x0080 0x02E8 0x05B4 0x6 0x1
#define MX8MN_IOMUXC_ENET_TXC__ENET1_RGMII_TXC                                  0x0084 0x02EC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TXC__ENET1_TX_ER                                      0x0084 0x02EC 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ENET_TXC__SAI7_TX_DATA0                                    0x0084 0x02EC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TXC__GPIO1_IO23                                       0x0084 0x02EC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TXC__USDHC3_DATA1                                     0x0084 0x02EC 0x05B0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RX_CTL__ENET1_RGMII_RX_CTL                            0x0088 0x02F0 0x0574 0x0 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL__SAI7_TX_SYNC                                  0x0088 0x02F0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL__PDM_BIT_STREAM3                               0x0088 0x02F0 0x0540 0x3 0x3
#define MX8MN_IOMUXC_ENET_RX_CTL__GPIO1_IO24                                    0x0088 0x02F0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL__USDHC3_DATA2                                  0x0088 0x02F0 0x05E4 0x6 0x1
#define MX8MN_IOMUXC_ENET_RXC__ENET1_RGMII_RXC                                  0x008C 0x02F4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RXC__ENET1_RX_ER                                      0x008C 0x02F4 0x05C8 0x1 0x0
#define MX8MN_IOMUXC_ENET_RXC__SAI7_TX_BCLK                                     0x008C 0x02F4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RXC__PDM_BIT_STREAM2                                  0x008C 0x02F4 0x053C 0x3 0x3
#define MX8MN_IOMUXC_ENET_RXC__GPIO1_IO25                                       0x008C 0x02F4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RXC__USDHC3_DATA3                                     0x008C 0x02F4 0x05E0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD0__ENET1_RGMII_RD0                                  0x0090 0x02F8 0x057C 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD0__SAI7_RX_DATA0                                    0x0090 0x02F8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD0__PDM_BIT_STREAM1                                  0x0090 0x02F8 0x0538 0x3 0x3
#define MX8MN_IOMUXC_ENET_RD0__GPIO1_IO26                                       0x0090 0x02F8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD0__USDHC3_DATA4                                     0x0090 0x02F8 0x0558 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD1__ENET1_RGMII_RD1                                  0x0094 0x02FC 0x0554 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD1__SAI7_RX_SYNC                                     0x0094 0x02FC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD1__PDM_BIT_STREAM0                                  0x0094 0x02FC 0x0534 0x3 0x1
#define MX8MN_IOMUXC_ENET_RD1__GPIO1_IO27                                       0x0094 0x02FC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD1__USDHC3_RESET_B                                   0x0094 0x02FC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_ENET_RD2__ENET1_RGMII_RD2                                  0x0098 0x0300 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD2__SAI7_RX_BCLK                                     0x0098 0x0300 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD2__PDM_CLK                                          0x0098 0x0300 0x0000 0x3 0x0
#define MX8MN_IOMUXC_ENET_RD2__GPIO1_IO28                                       0x0098 0x0300 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD2__USDHC3_CLK                                       0x0098 0x0300 0x05A0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD3__ENET1_RGMII_RD3                                  0x009C 0x0304 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD3__SAI7_MCLK                                        0x009C 0x0304 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD3__SPDIF1_IN                                        0x009C 0x0304 0x05CC 0x3 0x5
#define MX8MN_IOMUXC_ENET_RD3__GPIO1_IO29                                       0x009C 0x0304 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD3__USDHC3_CMD                                       0x009C 0x0304 0x05DC 0x6 0x1
#define MX8MN_IOMUXC_SD1_CLK__USDHC1_CLK                                        0x00A0 0x0308 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_CLK__ENET1_MDC                                         0x00A0 0x0308 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_CLK__UART1_DCE_TX                                      0x00A0 0x0308 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_CLK__UART1_DTE_RX                                      0x00A0 0x0308 0x04F4 0x4 0x4
#define MX8MN_IOMUXC_SD1_CLK__GPIO2_IO0                                         0x00A0 0x0308 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_CMD__USDHC1_CMD                                        0x00A4 0x030C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_CMD__ENET1_MDIO                                        0x00A4 0x030C 0x04C0 0x1 0x3
#define MX8MN_IOMUXC_SD1_CMD__UART1_DCE_RX                                      0x00A4 0x030C 0x04F4 0x4 0x5
#define MX8MN_IOMUXC_SD1_CMD__UART1_DTE_TX                                      0x00A4 0x030C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_CMD__GPIO2_IO1                                         0x00A4 0x030C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA0__USDHC1_DATA0                                    0x00A8 0x0310 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1                                 0x00A8 0x0310 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA0__UART1_DCE_RTS_B                                 0x00A8 0x0310 0x04F0 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA0__UART1_DTE_CTS_B                                 0x00A8 0x0310 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA0__GPIO2_IO2                                       0x00A8 0x0310 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA1__USDHC1_DATA1                                    0x00AC 0x0314 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0                                 0x00AC 0x0314 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA1__UART1_DCE_CTS_B                                 0x00AC 0x0314 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA1__UART1_DTE_RTS_B                                 0x00AC 0x0314 0x04F0 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA1__GPIO2_IO3                                       0x00AC 0x0314 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA2__USDHC1_DATA2                                    0x00B0 0x0318 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0                                 0x00B0 0x0318 0x057C 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA2__UART2_DCE_TX                                    0x00B0 0x0318 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA2__UART2_DTE_RX                                    0x00B0 0x0318 0x04FC 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA2__GPIO2_IO4                                       0x00B0 0x0318 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA3__USDHC1_DATA3                                    0x00B4 0x031C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1                                 0x00B4 0x031C 0x0554 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA3__UART2_DCE_RX                                    0x00B4 0x031C 0x04FC 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA3__UART2_DTE_TX                                    0x00B4 0x031C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA3__GPIO2_IO5                                       0x00B4 0x031C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA4__USDHC1_DATA4                                    0x00B8 0x0320 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL                              0x00B8 0x0320 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA4__I2C1_SCL                                        0x00B8 0x0320 0x055C 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA4__UART2_DCE_RTS_B                                 0x00B8 0x0320 0x04F8 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA4__UART2_DTE_CTS_B                                 0x00B8 0x0320 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA4__GPIO2_IO6                                       0x00B8 0x0320 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA5__USDHC1_DATA5                                    0x00BC 0x0324 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA5__ENET1_TX_ER                                     0x00BC 0x0324 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA5__I2C1_SDA                                        0x00BC 0x0324 0x056C 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA5__UART2_DCE_CTS_B                                 0x00BC 0x0324 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA5__UART2_DTE_RTS_B                                 0x00BC 0x0324 0x04F8 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA5__GPIO2_IO7                                       0x00BC 0x0324 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA6__USDHC1_DATA6                                    0x00C0 0x0328 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL                              0x00C0 0x0328 0x0574 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA6__I2C2_SCL                                        0x00C0 0x0328 0x05D0 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA6__UART3_DCE_TX                                    0x00C0 0x0328 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA6__UART3_DTE_RX                                    0x00C0 0x0328 0x0504 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA6__GPIO2_IO8                                       0x00C0 0x0328 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA7__USDHC1_DATA7                                    0x00C4 0x032C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA7__ENET1_RX_ER                                     0x00C4 0x032C 0x05C8 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA7__I2C2_SDA                                        0x00C4 0x032C 0x0560 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA7__UART3_DCE_RX                                    0x00C4 0x032C 0x0504 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA7__UART3_DTE_TX                                    0x00C4 0x032C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA7__GPIO2_IO9                                       0x00C4 0x032C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_RESET_B__USDHC1_RESET_B                                0x00C8 0x0330 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_RESET_B__ENET1_TX_CLK                                  0x00C8 0x0330 0x05A4 0x1 0x1
#define MX8MN_IOMUXC_SD1_RESET_B__CCMSRCGPCMIX_ENET_REF_CLK_ROOT                0x00C8 0x0330 0x05A4 0x1 0x0
#define MX8MN_IOMUXC_SD1_RESET_B__I2C3_SCL                                      0x00C8 0x0330 0x0588 0x3 0x1
#define MX8MN_IOMUXC_SD1_RESET_B__UART3_DCE_RTS_B                               0x00C8 0x0330 0x0500 0x4 0x2
#define MX8MN_IOMUXC_SD1_RESET_B__UART3_DTE_CTS_B                               0x00C8 0x0330 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_RESET_B__GPIO2_IO10                                    0x00C8 0x0330 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_STROBE__USDHC1_STROBE                                  0x00CC 0x0334 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_STROBE__I2C3_SDA                                       0x00CC 0x0334 0x05BC 0x3 0x1
#define MX8MN_IOMUXC_SD1_STROBE__UART3_DCE_CTS_B                                0x00CC 0x0334 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_STROBE__UART3_DTE_RTS_B                                0x00CC 0x0334 0x0500 0x4 0x3
#define MX8MN_IOMUXC_SD1_STROBE__GPIO2_IO11                                     0x00CC 0x0334 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CD_B__USDHC2_CD_B                                      0x00D0 0x0338 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CD_B__GPIO2_IO12                                       0x00D0 0x0338 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK                          0x00D0 0x0338 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_CLK__USDHC2_CLK                                        0x00D4 0x033C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CLK__SAI5_RX_SYNC                                      0x00D4 0x033C 0x04E4 0x1 0x1
#define MX8MN_IOMUXC_SD2_CLK__ECSPI2_SCLK                                       0x00D4 0x033C 0x0580 0x2 0x1
#define MX8MN_IOMUXC_SD2_CLK__UART4_DCE_RX                                      0x00D4 0x033C 0x050C 0x3 0x4
#define MX8MN_IOMUXC_SD2_CLK__UART4_DTE_TX                                      0x00D4 0x033C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_CLK__SAI5_MCLK                                         0x00D4 0x033C 0x0594 0x4 0x1
#define MX8MN_IOMUXC_SD2_CLK__GPIO2_IO13                                        0x00D4 0x033C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                             0x00D4 0x033C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_CMD__USDHC2_CMD                                        0x00D8 0x0340 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CMD__SAI5_RX_BCLK                                      0x00D8 0x0340 0x04D0 0x1 0x1
#define MX8MN_IOMUXC_SD2_CMD__ECSPI2_MOSI                                       0x00D8 0x0340 0x0590 0x2 0x1
#define MX8MN_IOMUXC_SD2_CMD__UART4_DCE_TX                                      0x00D8 0x0340 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_CMD__UART4_DTE_RX                                      0x00D8 0x0340 0x050C 0x3 0x5
#define MX8MN_IOMUXC_SD2_CMD__PDM_CLK                                           0x00D8 0x0340 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD2_CMD__GPIO2_IO14                                        0x00D8 0x0340 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                             0x00D8 0x0340 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA0__USDHC2_DATA0                                    0x00DC 0x0344 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA0__SAI5_RX_DATA0                                   0x00DC 0x0344 0x04D4 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA0__I2C4_SDA                                        0x00DC 0x0344 0x058C 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA0__UART2_DCE_RX                                    0x00DC 0x0344 0x04FC 0x3 0x6
#define MX8MN_IOMUXC_SD2_DATA0__UART2_DTE_TX                                    0x00DC 0x0344 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA0__PDM_BIT_STREAM0                                 0x00DC 0x0344 0x0534 0x4 0x2
#define MX8MN_IOMUXC_SD2_DATA0__GPIO2_IO15                                      0x00DC 0x0344 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                           0x00DC 0x0344 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA1__USDHC2_DATA1                                    0x00E0 0x0348 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA1__SAI5_TX_SYNC                                    0x00E0 0x0348 0x04EC 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA1__I2C4_SCL                                        0x00E0 0x0348 0x05D4 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA1__UART2_DCE_TX                                    0x00E0 0x0348 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA1__UART2_DTE_RX                                    0x00E0 0x0348 0x04FC 0x3 0x7
#define MX8MN_IOMUXC_SD2_DATA1__PDM_BIT_STREAM1                                 0x00E0 0x0348 0x0538 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA1__GPIO2_IO16                                      0x00E0 0x0348 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA1__CCMSRCGPCMIX_WAIT                               0x00E0 0x0348 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA2__USDHC2_DATA2                                    0x00E4 0x034C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA2__SAI5_TX_BCLK                                    0x00E4 0x034C 0x04E8 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA2__ECSPI2_SS0                                      0x00E4 0x034C 0x0570 0x2 0x2
#define MX8MN_IOMUXC_SD2_DATA2__SPDIF1_OUT                                      0x00E4 0x034C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA2__PDM_BIT_STREAM2                                 0x00E4 0x034C 0x053C 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA2__GPIO2_IO17                                      0x00E4 0x034C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA2__CCMSRCGPCMIX_STOP                               0x00E4 0x034C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA3__USDHC2_DATA3                                    0x00E8 0x0350 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA3__SAI5_TX_DATA0                                   0x00E8 0x0350 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD2_DATA3__ECSPI2_MISO                                     0x00E8 0x0350 0x0578 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA3__SPDIF1_IN                                       0x00E8 0x0350 0x05CC 0x3 0x2
#define MX8MN_IOMUXC_SD2_DATA3__PDM_BIT_STREAM3                                 0x00E8 0x0350 0x0540 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA3__GPIO2_IO18                                      0x00E8 0x0350 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET                        0x00E8 0x0350 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_RESET_B__USDHC2_RESET_B                                0x00EC 0x0354 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_RESET_B__GPIO2_IO19                                    0x00EC 0x0354 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET                     0x00EC 0x0354 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_WP__USDHC2_WP                                          0x00F0 0x0358 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_WP__GPIO2_IO20                                         0x00F0 0x0358 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_WP__CORESIGHT_EVENTI                                   0x00F0 0x0358 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_ALE__RAWNAND_ALE                                      0x00F4 0x035C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_ALE__QSPI_A_SCLK                                      0x00F4 0x035C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_ALE__PDM_BIT_STREAM0                                  0x00F4 0x035C 0x0534 0x3 0x3
#define MX8MN_IOMUXC_NAND_ALE__UART3_DCE_RX                                     0x00F4 0x035C 0x0504 0x4 0x6
#define MX8MN_IOMUXC_NAND_ALE__UART3_DTE_TX                                     0x00F4 0x035C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_ALE__GPIO3_IO0                                        0x00F4 0x035C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK                              0x00F4 0x035C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE0_B__RAWNAND_CE0_B                                  0x00F8 0x0360 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE0_B__QSPI_A_SS0_B                                   0x00F8 0x0360 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE0_B__PDM_BIT_STREAM1                                0x00F8 0x0360 0x0538 0x3 0x5
#define MX8MN_IOMUXC_NAND_CE0_B__UART3_DCE_TX                                   0x00F8 0x0360 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_CE0_B__UART3_DTE_RX                                   0x00F8 0x0360 0x0504 0x4 0x7
#define MX8MN_IOMUXC_NAND_CE0_B__GPIO3_IO1                                      0x00F8 0x0360 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL                            0x00F8 0x0360 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE1_B__RAWNAND_CE1_B                                  0x00FC 0x0364 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE1_B__QSPI_A_SS1_B                                   0x00FC 0x0364 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE1_B__USDHC3_STROBE                                  0x00FC 0x0364 0x059C 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE1_B__PDM_BIT_STREAM0                                0x00FC 0x0364 0x0534 0x3 0x4
#define MX8MN_IOMUXC_NAND_CE1_B__I2C4_SCL                                       0x00FC 0x0364 0x05D4 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE1_B__GPIO3_IO2                                      0x00FC 0x0364 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE0                               0x00FC 0x0364 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE2_B__RAWNAND_CE2_B                                  0x0100 0x0368 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE2_B__QSPI_B_SS0_B                                   0x0100 0x0368 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE2_B__USDHC3_DATA5                                   0x0100 0x0368 0x0550 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE2_B__PDM_BIT_STREAM1                                0x0100 0x0368 0x0538 0x3 0x6
#define MX8MN_IOMUXC_NAND_CE2_B__I2C4_SDA                                       0x0100 0x0368 0x058C 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE2_B__GPIO3_IO3                                      0x0100 0x0368 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE1                               0x0100 0x0368 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE3_B__RAWNAND_CE3_B                                  0x0104 0x036C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE3_B__QSPI_B_SS1_B                                   0x0104 0x036C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE3_B__USDHC3_DATA6                                   0x0104 0x036C 0x0584 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE3_B__PDM_BIT_STREAM2                                0x0104 0x036C 0x053C 0x3 0x5
#define MX8MN_IOMUXC_NAND_CE3_B__I2C3_SDA                                       0x0104 0x036C 0x05BC 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE3_B__GPIO3_IO4                                      0x0104 0x036C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE2                               0x0104 0x036C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CLE__RAWNAND_CLE                                      0x0108 0x0370 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CLE__QSPI_B_SCLK                                      0x0108 0x0370 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CLE__USDHC3_DATA7                                     0x0108 0x0370 0x054C 0x2 0x0
#define MX8MN_IOMUXC_NAND_CLE__GPIO3_IO5                                        0x0108 0x0370 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CLE__CORESIGHT_TRACE3                                 0x0108 0x0370 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA00__RAWNAND_DATA00                                0x010C 0x0374 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA00__QSPI_A_DATA0                                  0x010C 0x0374 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA00__PDM_BIT_STREAM2                               0x010C 0x0374 0x053C 0x3 0x6
#define MX8MN_IOMUXC_NAND_DATA00__UART4_DCE_RX                                  0x010C 0x0374 0x050C 0x4 0x6
#define MX8MN_IOMUXC_NAND_DATA00__UART4_DTE_TX                                  0x010C 0x0374 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_DATA00__GPIO3_IO6                                     0x010C 0x0374 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA00__CORESIGHT_TRACE4                              0x010C 0x0374 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA01__RAWNAND_DATA01                                0x0110 0x0378 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA01__QSPI_A_DATA1                                  0x0110 0x0378 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA01__PDM_BIT_STREAM3                               0x0110 0x0378 0x0540 0x3 0x5
#define MX8MN_IOMUXC_NAND_DATA01__UART4_DCE_TX                                  0x0110 0x0378 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_DATA01__UART4_DTE_RX                                  0x0110 0x0378 0x050C 0x4 0x7
#define MX8MN_IOMUXC_NAND_DATA01__GPIO3_IO7                                     0x0110 0x0378 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA01__CORESIGHT_TRACE5                              0x0110 0x0378 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA02__RAWNAND_DATA02                                0x0114 0x037C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA02__QSPI_A_DATA2                                  0x0114 0x037C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA02__USDHC3_CD_B                                   0x0114 0x037C 0x0598 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA02__I2C4_SDA                                      0x0114 0x037C 0x058C 0x4 0x3
#define MX8MN_IOMUXC_NAND_DATA02__GPIO3_IO8                                     0x0114 0x037C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA02__CORESIGHT_TRACE6                              0x0114 0x037C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA03__RAWNAND_DATA03                                0x0118 0x0380 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA03__QSPI_A_DATA3                                  0x0118 0x0380 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA03__USDHC3_WP                                     0x0118 0x0380 0x05B8 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA03__GPIO3_IO9                                     0x0118 0x0380 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA03__CORESIGHT_TRACE7                              0x0118 0x0380 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA04__RAWNAND_DATA04                                0x011C 0x0384 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA04__QSPI_B_DATA0                                  0x011C 0x0384 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA04__USDHC3_DATA0                                  0x011C 0x0384 0x05B4 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA04__GPIO3_IO10                                    0x011C 0x0384 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA04__CORESIGHT_TRACE8                              0x011C 0x0384 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA05__RAWNAND_DATA05                                0x0120 0x0388 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA05__QSPI_B_DATA1                                  0x0120 0x0388 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA05__USDHC3_DATA1                                  0x0120 0x0388 0x05B0 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA05__GPIO3_IO11                                    0x0120 0x0388 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA05__CORESIGHT_TRACE9                              0x0120 0x0388 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA06__RAWNAND_DATA06                                0x0124 0x038C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA06__QSPI_B_DATA2                                  0x0124 0x038C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA06__USDHC3_DATA2                                  0x0124 0x038C 0x05E4 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA06__GPIO3_IO12                                    0x0124 0x038C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10                             0x0124 0x038C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA07__RAWNAND_DATA07                                0x0128 0x0390 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA07__QSPI_B_DATA3                                  0x0128 0x0390 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA07__USDHC3_DATA3                                  0x0128 0x0390 0x05E0 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA07__GPIO3_IO13                                    0x0128 0x0390 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11                             0x0128 0x0390 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DQS__RAWNAND_DQS                                      0x012C 0x0394 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DQS__QSPI_A_DQS                                       0x012C 0x0394 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DQS__PDM_CLK                                          0x012C 0x0394 0x0000 0x3 0x0
#define MX8MN_IOMUXC_NAND_DQS__I2C3_SCL                                         0x012C 0x0394 0x0588 0x4 0x2
#define MX8MN_IOMUXC_NAND_DQS__GPIO3_IO14                                       0x012C 0x0394 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DQS__CORESIGHT_TRACE12                                0x012C 0x0394 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_RE_B__RAWNAND_RE_B                                    0x0130 0x0398 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_RE_B__QSPI_B_DQS                                      0x0130 0x0398 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_RE_B__USDHC3_DATA4                                    0x0130 0x0398 0x0558 0x2 0x0
#define MX8MN_IOMUXC_NAND_RE_B__PDM_BIT_STREAM1                                 0x0130 0x0398 0x0538 0x3 0x7
#define MX8MN_IOMUXC_NAND_RE_B__GPIO3_IO15                                      0x0130 0x0398 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13                               0x0130 0x0398 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_READY_B__RAWNAND_READY_B                              0x0134 0x039C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_READY_B__USDHC3_RESET_B                               0x0134 0x039C 0x0000 0x2 0x0
#define MX8MN_IOMUXC_NAND_READY_B__PDM_BIT_STREAM3                              0x0134 0x039C 0x0540 0x3 0x6
#define MX8MN_IOMUXC_NAND_READY_B__I2C3_SCL                                     0x0134 0x039C 0x0588 0x4 0x3
#define MX8MN_IOMUXC_NAND_READY_B__GPIO3_IO16                                   0x0134 0x039C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14                            0x0134 0x039C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_WE_B__RAWNAND_WE_B                                    0x0138 0x03A0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_WE_B__USDHC3_CLK                                      0x0138 0x03A0 0x05A0 0x2 0x0
#define MX8MN_IOMUXC_NAND_WE_B__I2C3_SDA                                        0x0138 0x03A0 0x05BC 0x4 0x3
#define MX8MN_IOMUXC_NAND_WE_B__GPIO3_IO17                                      0x0138 0x03A0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15                               0x0138 0x03A0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_WP_B__RAWNAND_WP_B                                    0x013C 0x03A4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_WP_B__USDHC3_CMD                                      0x013C 0x03A4 0x05DC 0x2 0x0
#define MX8MN_IOMUXC_NAND_WP_B__I2C4_SDA                                        0x013C 0x03A4 0x058C 0x4 0x4
#define MX8MN_IOMUXC_NAND_WP_B__GPIO3_IO18                                      0x013C 0x03A4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO                                0x013C 0x03A4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SAI5_RXFS__SAI5_RX_SYNC                                    0x0140 0x03A8 0x04E4 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXFS__GPIO3_IO19                                      0x0140 0x03A8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXC__SAI5_RX_BCLK                                     0x0144 0x03AC 0x04D0 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXC__PDM_CLK                                          0x0144 0x03AC 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXC__GPIO3_IO20                                       0x0144 0x03AC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD0__SAI5_RX_DATA0                                   0x0148 0x03B0 0x04D4 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD0__PDM_BIT_STREAM0                                 0x0148 0x03B0 0x0534 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD0__GPIO3_IO21                                      0x0148 0x03B0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD1__SAI5_RX_DATA1                                   0x014C 0x03B4 0x04D8 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD1__SAI5_TX_SYNC                                    0x014C 0x03B4 0x04EC 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD1__PDM_BIT_STREAM1                                 0x014C 0x03B4 0x0538 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD1__GPIO3_IO22                                      0x014C 0x03B4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD2__SAI5_RX_DATA2                                   0x0150 0x03B8 0x04DC 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD2__SAI5_TX_BCLK                                    0x0150 0x03B8 0x04E8 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD2__PDM_BIT_STREAM2                                 0x0150 0x03B8 0x053C 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD2__GPIO3_IO23                                      0x0150 0x03B8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD3__SAI5_RX_DATA3                                   0x0154 0x03BC 0x04E0 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD3__SAI5_TX_DATA0                                   0x0154 0x03BC 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD3__PDM_BIT_STREAM3                                 0x0154 0x03BC 0x0540 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD3__GPIO3_IO24                                      0x0154 0x03BC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_MCLK__SAI5_MCLK                                       0x0158 0x03C0 0x0594 0x0 0x0
#define MX8MN_IOMUXC_SAI5_MCLK__GPIO3_IO25                                      0x0158 0x03C0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXFS__SAI2_RX_SYNC                                    0x01B0 0x0418 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXFS__SAI5_TX_SYNC                                    0x01B0 0x0418 0x04EC 0x1 0x2
#define MX8MN_IOMUXC_SAI2_RXFS__SAI5_TX_DATA1                                   0x01B0 0x0418 0x0000 0x2 0x0
#define MX8MN_IOMUXC_SAI2_RXFS__SAI2_RX_DATA1                                   0x01B0 0x0418 0x05AC 0x3 0x0
#define MX8MN_IOMUXC_SAI2_RXFS__UART1_DCE_TX                                    0x01B0 0x0418 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXFS__UART1_DTE_RX                                    0x01B0 0x0418 0x04F4 0x4 0x2
#define MX8MN_IOMUXC_SAI2_RXFS__GPIO4_IO21                                      0x01B0 0x0418 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXFS__PDM_BIT_STREAM2                                 0x01B0 0x0418 0x053C 0x6 0x7
#define MX8MN_IOMUXC_SAI2_RXC__SAI2_RX_BCLK                                     0x01B4 0x041C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXC__SAI5_TX_BCLK                                     0x01B4 0x041C 0x04E8 0x1 0x2
#define MX8MN_IOMUXC_SAI2_RXC__UART1_DCE_RX                                     0x01B4 0x041C 0x04F4 0x4 0x3
#define MX8MN_IOMUXC_SAI2_RXC__UART1_DTE_TX                                     0x01B4 0x041C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXC__GPIO4_IO22                                       0x01B4 0x041C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXC__PDM_BIT_STREAM1                                  0x01B4 0x041C 0x0538 0x6 0x8
#define MX8MN_IOMUXC_SAI2_RXD0__SAI2_RX_DATA0                                   0x01B8 0x0420 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXD0__SAI5_TX_DATA0                                   0x01B8 0x0420 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_RXD0__SAI2_TX_DATA1                                   0x01B8 0x0420 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI2_RXD0__UART1_DCE_RTS_B                                 0x01B8 0x0420 0x04F0 0x4 0x2
#define MX8MN_IOMUXC_SAI2_RXD0__UART1_DTE_CTS_B                                 0x01B8 0x0420 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXD0__GPIO4_IO23                                      0x01B8 0x0420 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXD0__PDM_BIT_STREAM3                                 0x01B8 0x0420 0x0540 0x6 0x7
#define MX8MN_IOMUXC_SAI2_TXFS__SAI2_TX_SYNC                                    0x01BC 0x0424 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXFS__SAI5_TX_DATA1                                   0x01BC 0x0424 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXFS__SAI2_TX_DATA1                                   0x01BC 0x0424 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI2_TXFS__UART1_DCE_CTS_B                                 0x01BC 0x0424 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_TXFS__UART1_DTE_RTS_B                                 0x01BC 0x0424 0x04F0 0x4 0x3
#define MX8MN_IOMUXC_SAI2_TXFS__GPIO4_IO24                                      0x01BC 0x0424 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXFS__PDM_BIT_STREAM2                                 0x01BC 0x0424 0x053C 0x6 0x8
#define MX8MN_IOMUXC_SAI2_TXC__SAI2_TX_BCLK                                     0x01C0 0x0428 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXC__SAI5_TX_DATA2                                    0x01C0 0x0428 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXC__GPIO4_IO25                                       0x01C0 0x0428 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXC__PDM_BIT_STREAM1                                  0x01C0 0x0428 0x0538 0x6 0x9
#define MX8MN_IOMUXC_SAI2_TXD0__SAI2_TX_DATA0                                   0x01C4 0x042C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXD0__SAI5_TX_DATA3                                   0x01C4 0x042C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXD0__GPIO4_IO26                                      0x01C4 0x042C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE4                         0x01C4 0x042C 0x0540 0x6 0x8
#define MX8MN_IOMUXC_SAI2_MCLK__SAI2_MCLK                                       0x01C8 0x0430 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_MCLK__SAI5_MCLK                                       0x01C8 0x0430 0x0594 0x1 0x2
#define MX8MN_IOMUXC_SAI2_MCLK__GPIO4_IO27                                      0x01C8 0x0430 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_MCLK__SAI3_MCLK                                       0x01C8 0x0430 0x05C0 0x6 0x1
#define MX8MN_IOMUXC_SAI3_RXFS__SAI3_RX_SYNC                                    0x01CC 0x0434 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXFS__GPT1_CAPTURE1                                   0x01CC 0x0434 0x05F0 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXFS__SAI5_RX_SYNC                                    0x01CC 0x0434 0x04E4 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXFS__SAI3_RX_DATA1                                   0x01CC 0x0434 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_RXFS__SPDIF1_IN                                       0x01CC 0x0434 0x05CC 0x4 0x3
#define MX8MN_IOMUXC_SAI3_RXFS__GPIO4_IO28                                      0x01CC 0x0434 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXFS__PDM_BIT_STREAM0                                 0x01CC 0x0434 0x0534 0x6 0x5
#define MX8MN_IOMUXC_SAI3_RXC__SAI3_RX_BCLK                                     0x01D0 0x0438 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXC__GPT1_CLK                                         0x01D0 0x0438 0x05E8 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXC__SAI5_RX_BCLK                                     0x01D0 0x0438 0x04D0 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXC__SAI2_RX_DATA1                                    0x01D0 0x0438 0x05AC 0x3 0x2
#define MX8MN_IOMUXC_SAI3_RXC__UART2_DCE_CTS_B                                  0x01D0 0x0438 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_RXC__UART2_DTE_RTS_B                                  0x01D0 0x0438 0x04F8 0x4 0x2
#define MX8MN_IOMUXC_SAI3_RXC__GPIO4_IO29                                       0x01D0 0x0438 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXC__PDM_CLK                                          0x01D0 0x0438 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SAI3_RXD__SAI3_RX_DATA0                                    0x01D4 0x043C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXD__GPT1_COMPARE1                                    0x01D4 0x043C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXD__SAI5_RX_DATA0                                    0x01D4 0x043C 0x04D4 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXD__SAI3_TX_DATA1                                    0x01D4 0x043C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_RXD__UART2_DCE_RTS_B                                  0x01D4 0x043C 0x04F8 0x4 0x3
#define MX8MN_IOMUXC_SAI3_RXD__UART2_DTE_CTS_B                                  0x01D4 0x043C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_RXD__GPIO4_IO30                                       0x01D4 0x043C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXD__PDM_BIT_STREAM1                                  0x01D4 0x043C 0x0538 0x6 0x10
#define MX8MN_IOMUXC_SAI3_TXFS__SAI3_TX_SYNC                                    0x01D8 0x0440 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXFS__GPT1_CAPTURE2                                   0x01D8 0x0440 0x05EC 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXFS__SAI5_RX_DATA1                                   0x01D8 0x0440 0x04D8 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXFS__SAI3_TX_DATA1                                   0x01D8 0x0440 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_TXFS__UART2_DCE_RX                                    0x01D8 0x0440 0x04FC 0x4 0x2
#define MX8MN_IOMUXC_SAI3_TXFS__UART2_DTE_TX                                    0x01D8 0x0440 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_TXFS__GPIO4_IO31                                      0x01D8 0x0440 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXFS__PDM_BIT_STREAM3                                 0x01D8 0x0440 0x0540 0x6 0x9
#define MX8MN_IOMUXC_SAI3_TXC__SAI3_TX_BCLK                                     0x01DC 0x0444 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXC__GPT1_COMPARE2                                    0x01DC 0x0444 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXC__SAI5_RX_DATA2                                    0x01DC 0x0444 0x04DC 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXC__SAI2_TX_DATA1                                    0x01DC 0x0444 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_TXC__UART2_DCE_TX                                     0x01DC 0x0444 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_TXC__UART2_DTE_RX                                     0x01DC 0x0444 0x04FC 0x4 0x3
#define MX8MN_IOMUXC_SAI3_TXC__GPIO5_IO0                                        0x01DC 0x0444 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXC__PDM_BIT_STREAM2                                  0x01DC 0x0444 0x053C 0x6 0x9
#define MX8MN_IOMUXC_SAI3_TXD__SAI3_TX_DATA0                                    0x01E0 0x0448 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXD__GPT1_COMPARE3                                    0x01E0 0x0448 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXD__SAI5_RX_DATA3                                    0x01E0 0x0448 0x04E0 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXD__SPDIF1_EXT_CLK                                   0x01E0 0x0448 0x0568 0x4 0x2
#define MX8MN_IOMUXC_SAI3_TXD__GPIO5_IO1                                        0x01E0 0x0448 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE5                          0x01E0 0x0448 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SAI3_MCLK__SAI3_MCLK                                       0x01E4 0x044C 0x05C0 0x0 0x0
#define MX8MN_IOMUXC_SAI3_MCLK__PWM4_OUT                                        0x01E4 0x044C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_MCLK__SAI5_MCLK                                       0x01E4 0x044C 0x0594 0x2 0x3
#define MX8MN_IOMUXC_SAI3_MCLK__SPDIF1_OUT                                      0x01E4 0x044C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_MCLK__GPIO5_IO2                                       0x01E4 0x044C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_MCLK__SPDIF1_IN                                       0x01E4 0x044C 0x05CC 0x6 0x4
#define MX8MN_IOMUXC_SPDIF_TX__SPDIF1_OUT                                       0x01E8 0x0450 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_TX__PWM3_OUT                                         0x01E8 0x0450 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_TX__GPIO5_IO3                                        0x01E8 0x0450 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SPDIF_RX__SPDIF1_IN                                        0x01EC 0x0454 0x05CC 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_RX__PWM2_OUT                                         0x01EC 0x0454 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_RX__GPIO5_IO4                                        0x01EC 0x0454 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK__SPDIF1_EXT_CLK                              0x01F0 0x0458 0x0568 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT                                    0x01F0 0x0458 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO5                                   0x01F0 0x0458 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK                                   0x01F4 0x045C 0x05D8 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX                                  0x01F4 0x045C 0x0504 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX                                  0x01F4 0x045C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK__I2C1_SCL                                      0x01F4 0x045C 0x055C 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_SCLK__SAI5_RX_SYNC                                  0x01F4 0x045C 0x04DC 0x3 0x2
#define MX8MN_IOMUXC_ECSPI1_SCLK__GPIO5_IO6                                     0x01F4 0x045C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI                                   0x01F8 0x0460 0x05A8 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX                                  0x01F8 0x0460 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX                                  0x01F8 0x0460 0x0504 0x1 0x1
#define MX8MN_IOMUXC_ECSPI1_MOSI__I2C1_SDA                                      0x01F8 0x0460 0x056C 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_MOSI__SAI5_RX_BCLK                                  0x01F8 0x0460 0x04D0 0x3 0x3
#define MX8MN_IOMUXC_ECSPI1_MOSI__GPIO5_IO7                                     0x01F8 0x0460 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO__ECSPI1_MISO                                   0x01FC 0x0464 0x05C4 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS_B                               0x01FC 0x0464 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS_B                               0x01FC 0x0464 0x0500 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO__I2C2_SCL                                      0x01FC 0x0464 0x05D0 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_MISO__SAI5_RX_DATA0                                 0x01FC 0x0464 0x04D4 0x3 0x3
#define MX8MN_IOMUXC_ECSPI1_MISO__GPIO5_IO8                                     0x01FC 0x0464 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0__ECSPI1_SS0                                     0x0200 0x0468 0x0564 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS_B                                0x0200 0x0468 0x0500 0x1 0x1
#define MX8MN_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS_B                                0x0200 0x0468 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0__I2C2_SDA                                       0x0200 0x0468 0x0560 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_SS0__SAI5_RX_DATA1                                  0x0200 0x0468 0x04D8 0x3 0x2
#define MX8MN_IOMUXC_ECSPI1_SS0__SAI5_TX_SYNC                                   0x0200 0x0468 0x04EC 0x4 0x3
#define MX8MN_IOMUXC_ECSPI1_SS0__GPIO5_IO9                                      0x0200 0x0468 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK                                   0x0204 0x046C 0x0580 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX                                  0x0204 0x046C 0x050C 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX                                  0x0204 0x046C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK__I2C3_SCL                                      0x0204 0x046C 0x0588 0x2 0x4
#define MX8MN_IOMUXC_ECSPI2_SCLK__SAI5_RX_DATA2                                 0x0204 0x046C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK__SAI5_TX_BCLK                                  0x0204 0x046C 0x04E8 0x4 0x3
#define MX8MN_IOMUXC_ECSPI2_SCLK__GPIO5_IO10                                    0x0204 0x046C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI                                   0x0208 0x0470 0x0590 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX                                  0x0208 0x0470 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX                                  0x0208 0x0470 0x050C 0x1 0x1
#define MX8MN_IOMUXC_ECSPI2_MOSI__I2C3_SDA                                      0x0208 0x0470 0x05BC 0x2 0x4
#define MX8MN_IOMUXC_ECSPI2_MOSI__SAI5_RX_DATA3                                 0x0208 0x0470 0x04E0 0x3 0x2
#define MX8MN_IOMUXC_ECSPI2_MOSI__SAI5_TX_DATA0                                 0x0208 0x0470 0x0000 0x4 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI__GPIO5_IO11                                    0x0208 0x0470 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO__ECSPI2_MISO                                   0x020C 0x0474 0x0578 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS_B                               0x020C 0x0474 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS_B                               0x020C 0x0474 0x0508 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO__I2C4_SCL                                      0x020C 0x0474 0x05D4 0x2 0x3
#define MX8MN_IOMUXC_ECSPI2_MISO__SAI5_MCLK                                     0x020C 0x0474 0x0594 0x3 0x4
#define MX8MN_IOMUXC_ECSPI2_MISO__GPIO5_IO12                                    0x020C 0x0474 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0__ECSPI2_SS0                                     0x0210 0x0478 0x0570 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS_B                                0x0210 0x0478 0x0508 0x1 0x1
#define MX8MN_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS_B                                0x0210 0x0478 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0__I2C4_SDA                                       0x0210 0x0478 0x058C 0x2 0x5
#define MX8MN_IOMUXC_ECSPI2_SS0__GPIO5_IO13                                     0x0210 0x0478 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C1_SCL__I2C1_SCL                                         0x0214 0x047C 0x055C 0x0 0x0
#define MX8MN_IOMUXC_I2C1_SCL__ENET1_MDC                                        0x0214 0x047C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C1_SCL__ECSPI1_SCLK                                      0x0214 0x047C 0x05D8 0x3 0x1
#define MX8MN_IOMUXC_I2C1_SCL__GPIO5_IO14                                       0x0214 0x047C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C1_SDA__I2C1_SDA                                         0x0218 0x0480 0x056C 0x0 0x0
#define MX8MN_IOMUXC_I2C1_SDA__ENET1_MDIO                                       0x0218 0x0480 0x04C0 0x1 0x2
#define MX8MN_IOMUXC_I2C1_SDA__ECSPI1_MOSI                                      0x0218 0x0480 0x05A8 0x3 0x1
#define MX8MN_IOMUXC_I2C1_SDA__GPIO5_IO15                                       0x0218 0x0480 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C2_SCL__I2C2_SCL                                         0x021C 0x0484 0x05D0 0x0 0x0
#define MX8MN_IOMUXC_I2C2_SCL__ENET1_1588_EVENT1_IN                             0x021C 0x0484 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C2_SCL__USDHC3_CD_B                                      0x021C 0x0484 0x0598 0x2 0x1
#define MX8MN_IOMUXC_I2C2_SCL__ECSPI1_MISO                                      0x021C 0x0484 0x05C4 0x3 0x1
#define MX8MN_IOMUXC_I2C2_SCL__GPIO5_IO16                                       0x021C 0x0484 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C2_SDA__I2C2_SDA                                         0x0220 0x0488 0x0560 0x0 0x0
#define MX8MN_IOMUXC_I2C2_SDA__ENET1_1588_EVENT1_OUT                            0x0220 0x0488 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C2_SDA__USDHC3_WP                                        0x0220 0x0488 0x05B8 0x2 0x1
#define MX8MN_IOMUXC_I2C2_SDA__ECSPI1_SS0                                       0x0220 0x0488 0x0564 0x3 0x1
#define MX8MN_IOMUXC_I2C2_SDA__GPIO5_IO17                                       0x0220 0x0488 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C3_SCL__I2C3_SCL                                         0x0224 0x048C 0x0588 0x0 0x0
#define MX8MN_IOMUXC_I2C3_SCL__PWM4_OUT                                         0x0224 0x048C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C3_SCL__GPT2_CLK                                         0x0224 0x048C 0x0000 0x2 0x0
#define MX8MN_IOMUXC_I2C3_SCL__ECSPI2_SCLK                                      0x0224 0x048C 0x0580 0x3 0x2
#define MX8MN_IOMUXC_I2C3_SCL__GPIO5_IO18                                       0x0224 0x048C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C3_SDA__I2C3_SDA                                         0x0228 0x0490 0x05BC 0x0 0x0
#define MX8MN_IOMUXC_I2C3_SDA__PWM3_OUT                                         0x0228 0x0490 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C3_SDA__GPT3_CLK                                         0x0228 0x0490 0x0000 0x2 0x0
#define MX8MN_IOMUXC_I2C3_SDA__ECSPI2_MOSI                                      0x0228 0x0490 0x0590 0x3 0x2
#define MX8MN_IOMUXC_I2C3_SDA__GPIO5_IO19                                       0x0228 0x0490 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C4_SCL__I2C4_SCL                                         0x022C 0x0494 0x05D4 0x0 0x0
#define MX8MN_IOMUXC_I2C4_SCL__PWM2_OUT                                         0x022C 0x0494 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C4_SCL__ECSPI2_MISO                                      0x022C 0x0494 0x0578 0x3 0x2
#define MX8MN_IOMUXC_I2C4_SCL__GPIO5_IO20                                       0x022C 0x0494 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C4_SDA__I2C4_SDA                                         0x0230 0x0498 0x058C 0x0 0x0
#define MX8MN_IOMUXC_I2C4_SDA__PWM1_OUT                                         0x0230 0x0498 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C4_SDA__ECSPI2_SS0                                       0x0230 0x0498 0x0570 0x3 0x1
#define MX8MN_IOMUXC_I2C4_SDA__GPIO5_IO21                                       0x0230 0x0498 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART1_RXD__UART1_DCE_RX                                    0x0234 0x049C 0x04F4 0x0 0x0
#define MX8MN_IOMUXC_UART1_RXD__UART1_DTE_TX                                    0x0234 0x049C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART1_RXD__ECSPI3_SCLK                                     0x0234 0x049C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART1_RXD__GPIO5_IO22                                      0x0234 0x049C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART1_TXD__UART1_DCE_TX                                    0x0238 0x04A0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART1_TXD__UART1_DTE_RX                                    0x0238 0x04A0 0x04F4 0x0 0x1
#define MX8MN_IOMUXC_UART1_TXD__ECSPI3_MOSI                                     0x0238 0x04A0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART1_TXD__GPIO5_IO23                                      0x0238 0x04A0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART2_RXD__UART2_DCE_RX                                    0x023C 0x04A4 0x04FC 0x0 0x0
#define MX8MN_IOMUXC_UART2_RXD__UART2_DTE_TX                                    0x023C 0x04A4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART2_RXD__ECSPI3_MISO                                     0x023C 0x04A4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART2_RXD__GPT1_COMPARE3                                   0x023C 0x04A4 0x0000 0x3 0x0
#define MX8MN_IOMUXC_UART2_RXD__GPIO5_IO24                                      0x023C 0x04A4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART2_TXD__UART2_DCE_TX                                    0x0240 0x04A8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART2_TXD__UART2_DTE_RX                                    0x0240 0x04A8 0x04FC 0x0 0x1
#define MX8MN_IOMUXC_UART2_TXD__ECSPI3_SS0                                      0x0240 0x04A8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART2_TXD__GPT1_COMPARE2                                   0x0240 0x04A8 0x0000 0x3 0x0
#define MX8MN_IOMUXC_UART2_TXD__GPIO5_IO25                                      0x0240 0x04A8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART3_RXD__UART3_DCE_RX                                    0x0244 0x04AC 0x0504 0x0 0x2
#define MX8MN_IOMUXC_UART3_RXD__UART3_DTE_TX                                    0x0244 0x04AC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART3_RXD__UART1_DCE_CTS_B                                 0x0244 0x04AC 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART3_RXD__UART1_DTE_RTS_B                                 0x0244 0x04AC 0x04F0 0x1 0x0
#define MX8MN_IOMUXC_UART3_RXD__USDHC3_RESET_B                                  0x0244 0x04AC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_UART3_RXD__GPT1_CAPTURE2                                   0x0244 0x04AC 0x05EC 0x3 0x1
#define MX8MN_IOMUXC_UART3_RXD__GPIO5_IO26                                      0x0244 0x04AC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART3_TXD__UART3_DCE_TX                                    0x0248 0x04B0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART3_TXD__UART3_DTE_RX                                    0x0248 0x04B0 0x0504 0x0 0x3
#define MX8MN_IOMUXC_UART3_TXD__UART1_DCE_RTS_B                                 0x0248 0x04B0 0x04F0 0x1 0x1
#define MX8MN_IOMUXC_UART3_TXD__UART1_DTE_CTS_B                                 0x0248 0x04B0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART3_TXD__USDHC3_VSELECT                                  0x0248 0x04B0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_UART3_TXD__GPT1_CLK                                        0x0248 0x04B0 0x05E8 0x3 0x1
#define MX8MN_IOMUXC_UART3_TXD__GPIO5_IO27                                      0x0248 0x04B0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART4_RXD__UART4_DCE_RX                                    0x024C 0x04B4 0x050C 0x0 0x2
#define MX8MN_IOMUXC_UART4_RXD__UART4_DTE_TX                                    0x024C 0x04B4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART4_RXD__UART2_DCE_CTS_B                                 0x024C 0x04B4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART4_RXD__UART2_DTE_RTS_B                                 0x024C 0x04B4 0x04F8 0x1 0x0
#define MX8MN_IOMUXC_UART4_RXD__GPT1_COMPARE1                                   0x024C 0x04B4 0x0000 0x3 0x0
#define MX8MN_IOMUXC_UART4_RXD__GPIO5_IO28                                      0x024C 0x04B4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART4_TXD__UART4_DCE_TX                                    0x0250 0x04B8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART4_TXD__UART4_DTE_RX                                    0x0250 0x04B8 0x050C 0x0 0x3
#define MX8MN_IOMUXC_UART4_TXD__UART2_DCE_RTS_B                                 0x0250 0x04B8 0x04F8 0x1 0x1
#define MX8MN_IOMUXC_UART4_TXD__UART2_DTE_CTS_B                                 0x0250 0x04B8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART4_TXD__GPT1_CAPTURE1                                   0x0250 0x04B8 0x05F0 0x3 0x1
#define MX8MN_IOMUXC_UART4_TXD__GPIO5_IO29                                      0x0250 0x04B8 0x0000 0x5 0x0

#endif /* __DTS_IMX8MN_PINFUNC_H */