/*
 * Copyright 2018 NXP
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MX7_SNVS_H__
#define __MX7_SNVS_H__

#define SNVS_HPCOMR			SNVS_BASE_ADDR + 0x04
#define SNVS_HPSICR			SNVS_BASE_ADDR + 0x0C
#define SNVS_HPSVCR			SNVS_BASE_ADDR + 0x10
#define SNVS_HPSR			SNVS_BASE_ADDR + 0x14
#define SNVS_HPSVSR			SNVS_BASE_ADDR + 0x18
#define SNVS_LPCR			SNVS_BASE_ADDR + 0x38
#define SNVS_LPMKCR			SNVS_BASE_ADDR + 0x3C
#define SNVS_LPTGFCR		SNVS_BASE_ADDR + 0x44
#define SNVS_LPTDCR			SNVS_BASE_ADDR + 0x48
#define SNVS_LPSR			SNVS_BASE_ADDR + 0x4C
#define SNVS_LPPGDR			SNVS_BASE_ADDR + 0x64
#define SNVS_LPZMKR0		SNVS_BASE_ADDR + 0x6C
#define SNVS_LPZMKR1		SNVS_BASE_ADDR + 0x70
#define SNVS_LPZMKR2		SNVS_BASE_ADDR + 0x74
#define SNVS_LPZMKR3		SNVS_BASE_ADDR + 0x78
#define SNVS_LPZMKR4		SNVS_BASE_ADDR + 0x7C
#define SNVS_LPZMKR5		SNVS_BASE_ADDR + 0x80
#define SNVS_LPZMKR6		SNVS_BASE_ADDR + 0x84
#define SNVS_LPZMKR7		SNVS_BASE_ADDR + 0x88
#define SNVS_LPTDC2R		SNVS_BASE_ADDR + 0xA0
#define SNVS_LPTDSR			SNVS_BASE_ADDR + 0xA4
#define SNVS_LPTGF1CR		SNVS_BASE_ADDR + 0xA8
#define SNVS_LPTGF2CR		SNVS_BASE_ADDR + 0xAC
#define SNVS_LPAT1CR		SNVS_BASE_ADDR + 0xC0
#define SNVS_LPATCTLR		SNVS_BASE_ADDR + 0xE0
#define SNVS_LPATCLKR		SNVS_BASE_ADDR + 0xE4
#define SNVS_LPATRC1R		SNVS_BASE_ADDR + 0xE8
#define SNVS_LPATRC2R		SNVS_BASE_ADDR + 0xEC

#define AT5_POLYSEED		0x12345678

#endif