// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
#include "k3-j721e-binman.dtsi"
#include <dt-bindings/phy/phy-cadence.h>

/ {
	aliases {
		remoteproc0 = &sysctrler;
		remoteproc1 = &a72_0;
	};

	chosen {
		stdout-path = "serial2:115200n8";
		tick-timer = &timer1;
	};

	a72_0: a72@0 {
		compatible = "ti,am654-rproc";
		reg = <0x0 0x00a90000 0x0 0x10>;
		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
				<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
		resets = <&k3_reset 202 0>;
		clocks = <&k3_clks 61 1>;
		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 342 0>;
		assigned-clock-parents= <0>, <0>, <&k3_clks 342 2>;
		assigned-clock-rates = <2000000000>, <200000000>;
		ti,sci = <&dmsc>;
		ti,sci-proc-id = <32>;
		ti,sci-host-id = <10>;
		bootph-pre-ram;
	};

	clk_200mhz: dummy_clock_200mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;
		bootph-pre-ram;
	};

	clk_19_2mhz: dummy_clock_19_2mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <19200000>;
		bootph-pre-ram;
	};
};

&cbass_mcu_wakeup {
	mcu_secproxy: secproxy@28380000 {
		bootph-pre-ram;
		compatible = "ti,am654-secure-proxy";
		reg = <0x0 0x2a380000 0x0 0x80000>,
		      <0x0 0x2a400000 0x0 0x80000>,
		      <0x0 0x2a480000 0x0 0x80000>;
		reg-names = "rt", "scfg", "target_data";
		#mbox-cells = <1>;
	};

	sysctrler: sysctrler {
		bootph-pre-ram;
		compatible = "ti,am654-system-controller";
		mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
		mbox-names = "tx", "rx";
	};

	wkup_vtm0: wkup_vtm@42040000 {
		compatible = "ti,am654-vtm", "ti,j721e-avs", "ti,j721e-vtm";
		reg = <0x0 0x42040000 0x0 0x330>,
		      <0x00 0x42050000 0x00 0x350>,
		      <0x00 0x43000300 0x00 0x10>;
		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
		#thermal-sensor-cells = <1>;
	};

	dm_tifs: dm-tifs {
		compatible = "ti,j721e-dm-sci";
		ti,host-id = <3>;
		ti,secure-host;
		mbox-names = "rx", "tx";
		mboxes= <&mcu_secproxy 21>,
			<&mcu_secproxy 23>;
		bootph-pre-ram;
	};
};

&dmsc {
	mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
	mbox-names = "tx", "rx", "notify";
	ti,host-id = <4>;
	ti,secure-host;
};

&wkup_pmx0 {
	wkup_uart0_pins_default: wkup_uart0_pins_default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
			J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
		>;
	};

	mcu_uart0_pins_default: mcu_uart0_pins_default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
			J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
		>;
	};

	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
		>;
	};

	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
		>;
	};

	wkup_gpio_pins_default: wkup-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
		>;
	};

	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
		>;
	};

	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
		>;
	};
};

&main_pmx0 {
	main_uart0_pins_default: main_uart0_pins_default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
			J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
		>;
	};

	main_usbss0_pins_default: main_usbss0_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_mmc1_pins_default: main_mmc1_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
		>;
	};

	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
		>;
	};
};

&wkup_uart0 {
	bootph-pre-ram;
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
	status = "okay";
};

&wkup_gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_gpio_pins_default>;
};

&mcu_uart0 {
	/delete-property/ power-domains;
	/delete-property/ clocks;
	/delete-property/ clock-names;
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_uart0_pins_default>;
	status = "okay";
	clock-frequency = <48000000>;
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	status = "okay";
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_sdhci0 {
	/delete-property/ power-domains;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	clock-names = "clk_xin";
	clocks = <&clk_200mhz>;
	ti,driver-strength-ohm = <50>;
	non-removable;
	bus-width = <8>;
};

&main_sdhci1 {
	/delete-property/ power-domains;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	clock-names = "clk_xin";
	clocks = <&clk_200mhz>;
	ti,driver-strength-ohm = <50>;
};

&wkup_i2c0 {
	bootph-pre-ram;
	tps659413a: tps659413a@48 {
		reg = <0x48>;
		compatible = "ti,tps659413";
		bootph-pre-ram;
		pinctrl-names = "default";
		pinctrl-0 = <&wkup_i2c0_pins_default>;
		clock-frequency = <400000>;

		regulators: regulators {
			bootph-pre-ram;
			buck12_reg: buck12 {
				/*VDD_CPU*/
				regulator-name = "buck12";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <900000>;
				regulator-always-on;
				regulator-boot-on;
				bootph-pre-ram;
			};
		};
	};
};

&wkup_vtm0 {
	vdd-supply-2 = <&buck12_reg>;
	bootph-pre-ram;
};

&usbss0 {
	/delete-property/ power-domains;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	clocks = <&clk_19_2mhz>;
	clock-names = "ref";
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
};

&main_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&hbmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
	reg = <0x0 0x47040000 0x0 0x100>,
		<0x0 0x50000000 0x0 0x8000000>;
	ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
		 <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */

	flash@0,0 {
		compatible = "cypress,hyperflash", "cfi-flash";
		reg = <0x0 0x0 0x4000000>;
	};
};

&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;

	reg = <0x0 0x47040000 0x0 0x100>,
	      <0x0 0x50000000 0x0 0x8000000>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <50000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <0>;
		cdns,phy-mode;
	};
};

&ospi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
	bootph-pre-ram;

	reg = <0x0 0x47050000 0x0 0x100>,
	      <0x0 0x58000000 0x0 0x8000000>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;
		bootph-pre-ram;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "qspi.tiboot3";
				reg = <0x0 0x80000>;
			};

			partition@80000 {
				label = "qspi.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "qspi.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "qspi.env";
				reg = <0x680000 0x20000>;
			};

			partition@6a0000 {
				label = "qspi.env.backup";
				reg = <0x6a0000 0x20000>;
			};

			partition@6c0000 {
				label = "qspi.sysfw";
				reg = <0x6c0000 0x100000>;
			};

			partition@800000 {
				label = "qspi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fe0000 {
				label = "qspi.phypattern";
				reg = <0x3fe0000 0x20000>;
			};
		};
	};
};

&mcu_ringacc {
	ti,sci = <&dm_tifs>;
};

&mcu_udmap {
	ti,sci = <&dm_tifs>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&serdes0 {
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;

	serdes0_pcie_link: link@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};

	serdes0_qsgmii_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_QSGMII>;
		resets = <&serdes_wiz0 2>;
	};
};

/* EEPROM might be read before SYSFW is available */
&wkup_i2c0 {
	/delete-property/ power-domains;
};