// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am64x-binman.dtsi" / { chosen { stdout-path = "serial2:115200n8"; tick-timer = &timer1; }; aliases { mmc1 = &sdhci1; }; memory@80000000 { bootph-pre-ram; }; }; &cbass_main{ bootph-pre-ram; timer1: timer@2400000 { compatible = "ti,omap5430-timer"; reg = <0x0 0x2400000 0x0 0x80>; ti,timer-alwon; clock-frequency = <200000000>; bootph-pre-ram; }; }; &main_conf { bootph-pre-ram; chipid@14 { bootph-pre-ram; }; }; &main_pmx0 { bootph-pre-ram; main_i2c0_pins_default: main-i2c0-pins-default { bootph-pre-ram; pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ >; }; }; &main_i2c0 { status = "okay"; bootph-pre-ram; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; tps65219: pmic@30 { compatible = "ti,tps65219"; reg = <0x30>; regulators { buck1_reg: buck1 { regulator-name = "VDD_CORE"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <750000>; regulator-boot-on; regulator-always-on; }; buck2_reg: buck2 { regulator-name = "VCC1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; buck3_reg: buck3 { regulator-name = "VDD_LPDDR4"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: ldo1 { regulator-name = "VDDSHV_SD_IO_PMIC"; regulator-min-microvolt = <33000000>; regulator-max-microvolt = <33000000>; }; ldo2_reg: ldo2 { regulator-name = "VDDAR_CORE"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; }; ldo3_reg: ldo3 { regulator-name = "VDDA_1V8"; regulator-min-microvolt = <18000000>; regulator-max-microvolt = <18000000>; regulator-boot-on; regulator-always-on; }; ldo4_reg: ldo4 { regulator-name = "VDD_PHY_2V5"; regulator-min-microvolt = <25000000>; regulator-max-microvolt = <25000000>; regulator-boot-on; regulator-always-on; }; }; }; }; &main_uart0 { bootph-pre-ram; }; &dmss { bootph-pre-ram; }; &secure_proxy_main { bootph-pre-ram; }; &dmsc { bootph-pre-ram; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; bootph-pre-ram; }; }; &k3_pds { bootph-pre-ram; }; &k3_clks { bootph-pre-ram; }; &k3_reset { bootph-pre-ram; }; &sdhci0 { status = "disabled"; bootph-pre-ram; }; &sdhci1 { bootph-pre-ram; }; &main_mmc1_pins_default { bootph-pre-ram; }; &cpsw3g { reg = <0x0 0x8000000 0x0 0x200000>, <0x0 0x43000200 0x0 0x8>; reg-names = "cpsw_nuss", "mac_efuse"; /delete-property/ ranges; pinctrl-0 = <&mdio1_pins_default /* HACK: as MDIO driver is not DM enabled */ &rgmii1_pins_default &rgmii2_pins_default>; bootph-pre-ram; cpsw-phy-sel@04044 { compatible = "ti,am64-phy-gmii-sel"; reg = <0x0 0x43004044 0x0 0x8>; bootph-pre-ram; }; ethernet-ports { bootph-pre-ram; }; }; &cpsw_port2 { bootph-pre-ram; }; &main_bcdma { bootph-pre-ram; reg = <0x00 0x485c0100 0x00 0x100>, <0x00 0x4c000000 0x00 0x20000>, <0x00 0x4a820000 0x00 0x20000>, <0x00 0x4aa40000 0x00 0x20000>, <0x00 0x4bc00000 0x00 0x100000>, <0x00 0x48600000 0x00 0x8000>, <0x00 0x484a4000 0x00 0x2000>, <0x00 0x484c2000 0x00 0x2000>; reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", "cfg", "tchan", "rchan"; }; &main_pktdma { bootph-pre-ram; reg = <0x00 0x485c0000 0x00 0x100>, <0x00 0x4a800000 0x00 0x20000>, <0x00 0x4aa00000 0x00 0x40000>, <0x00 0x4b800000 0x00 0x400000>, <0x00 0x485e0000 0x00 0x20000>, <0x00 0x484a0000 0x00 0x4000>, <0x00 0x484c0000 0x00 0x2000>, <0x00 0x48430000 0x00 0x4000>; reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg", "tchan", "rchan", "rflow"; }; &rgmii1_pins_default { bootph-pre-ram; }; &rgmii2_pins_default { bootph-pre-ram; }; &mdio1_pins_default { bootph-pre-ram; }; &cpsw3g_phy1 { bootph-pre-ram; }; &main_usb0_pins_default { bootph-pre-ram; }; &serdes_ln_ctrl { u-boot,mux-autoprobe; }; &usbss0 { bootph-pre-ram; }; &usb0 { dr_mode = "host"; bootph-pre-ram; }; &serdes_wiz0 { bootph-pre-ram; }; &serdes0_usb_link { bootph-pre-ram; }; &serdes0 { bootph-pre-ram; }; &serdes_refclk { bootph-pre-ram; }; &ospi0_pins_default { bootph-pre-ram; }; &fss { bootph-pre-ram; }; &ospi0 { bootph-pre-ram; flash@0 { bootph-pre-ram; partitions { bootph-pre-ram; #address-cells = <1>; #size-cells = <1>; partition@3fc0000 { bootph-pre-ram; reg = <0x3fc0000 0x40000>; }; }; }; };