// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2023 Toradex */ #include "k3-am625-verdin-wifi-dev-binman.dtsi" / { aliases { eeprom0 = &eeprom_module; eeprom1 = &eeprom_carrier_board; eeprom2 = &eeprom_display_adapter; }; chosen { tick-timer = &main_timer0; }; memory@80000000 { bootph-pre-ram; }; }; &cbass_main { bootph-pre-ram; timer@2400000 { clock-frequency = <25000000>; bootph-pre-ram; }; }; &cbass_mcu { bootph-pre-ram; }; &cbass_wakeup { bootph-pre-ram; }; &chipid { bootph-pre-ram; }; &cpsw3g { /* U-Boot does not support pinctrls in the cpsw3g_midio node so we just add them all here */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth_clock &pinctrl_mdio &pinctrl_rgmii1 &pinctrl_rgmii2>; reg = <0x0 0x8000000 0x0 0x200000>, <0x0 0x43000200 0x0 0x8>; reg-names = "cpsw_nuss", "mac_efuse"; /delete-property/ ranges; bootph-pre-ram; cpsw-phy-sel@04044 { compatible = "ti,am64-phy-gmii-sel"; reg = <0x0 0x00104044 0x0 0x8>; bootph-pre-ram; }; }; &cpsw3g_phy0 { /* U-Boot currently does not support reset-gpios so we just hog it */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth_int>; bootph-pre-ram; }; &cpsw3g_phy1 { bootph-pre-ram; }; &cpsw_port1 { bootph-pre-ram; }; &cpsw_port2 { bootph-pre-ram; }; /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ &cpsw3g_mdio { /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; /delete-property/ assigned-clock-rates; }; &dmsc { bootph-pre-ram; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; bootph-pre-ram; }; }; &dmss { bootph-pre-ram; }; &fss { bootph-pre-ram; }; &k3_clks { bootph-pre-ram; }; &k3_pds { bootph-pre-ram; }; &k3_reset { bootph-pre-ram; }; &main_bcdma { bootph-pre-ram; reg = <0x00 0x485c0100 0x00 0x100>, <0x00 0x4c000000 0x00 0x20000>, <0x00 0x4a820000 0x00 0x20000>, <0x00 0x4aa40000 0x00 0x20000>, <0x00 0x4bc00000 0x00 0x100000>, <0x00 0x48600000 0x00 0x8000>, <0x00 0x484a4000 0x00 0x2000>, <0x00 0x484c2000 0x00 0x2000>; reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt" , "cfg", "tchan", "rchan"; }; &main_gpio0 { bootph-pre-ram; /* FIXME: no PHY reset support */ reset-ethphy { gpio-hog; gpios = <17 GPIO_ACTIVE_HIGH>; line-name = "reset_ethphy"; output-high; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth_reset>; }; }; /* On-module I2C - PMIC_I2C */ &main_i2c0 { eeprom_module: eeprom@50 { compatible = "i2c-eeprom"; pagesize = <16>; reg = <0x50>; }; }; /* Verdin I2C_1 */ &main_i2c1 { /* EEPROM on display adapter (MIPI DSI Display Adapter) */ eeprom_display_adapter: eeprom@50 { compatible = "i2c-eeprom"; reg = <0x50>; pagesize = <16>; }; /* EEPROM on carrier board */ eeprom_carrier_board: eeprom@57 { compatible = "i2c-eeprom"; reg = <0x57>; pagesize = <16>; }; }; &main_pktdma { bootph-pre-ram; reg = <0x00 0x485c0000 0x00 0x100>, <0x00 0x4a800000 0x00 0x20000>, <0x00 0x4aa00000 0x00 0x20000>, <0x00 0x4b800000 0x00 0x200000>, <0x00 0x485e0000 0x00 0x10000>, <0x00 0x484a0000 0x00 0x2000>, <0x00 0x484c0000 0x00 0x2000>, <0x00 0x48430000 0x00 0x1000>; reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg", "tchan", "rchan", "rflow"; }; &main_pmx0 { bootph-pre-ram; }; /* Verdin UART_3, used as the Linux console */ &main_uart0 { bootph-pre-ram; }; /* Verdin UART_1 */ &main_uart1 { bootph-pre-ram; }; &mcu_pmx0 { bootph-pre-ram; }; &pinctrl_ctrl_sleep_moci { bootph-pre-ram; }; &pinctrl_i2c0 { bootph-pre-ram; }; &pinctrl_i2c1 { bootph-pre-ram; }; &pinctrl_sdhci0 { bootph-pre-ram; }; &pinctrl_uart0 { bootph-pre-ram; }; &pinctrl_uart1 { bootph-pre-ram; }; &pinctrl_wkup_uart0 { bootph-pre-ram; }; &sdhci0 { bootph-pre-ram; }; &sdhci2 { status = "disabled"; }; &secure_proxy_main { bootph-pre-ram; }; &usbss0 { bootph-pre-ram; }; &usb0 { dr_mode = "peripheral"; /* Since role switching is not supported in U-Boot */ /delete-property/ extcon; bootph-pre-ram; }; &verdin_ctrl_sleep_moci { bootph-pre-ram; }; &wkup_conf { bootph-pre-ram; }; /* Verdin UART_2 */ &wkup_uart0 { bootph-pre-ram; };