// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

#include "imx8mp-sec-def.h"
#include "imx8mp-u-boot.dtsi"

/ {
	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	wdt-reboot {
		compatible = "wdt-reboot";
		u-boot,dm-spl;
		wdt = <&wdog1>;
	};

	mcu_rdc {
		compatible = "imx8m,mcu_rdc";
			    /* rdc config when MCU starts
			     * master
			     *   SDMA3p --> domain 1
			     *   SDMA3b --> domain 1
			     *   SDMA3_SPBA2 --> domain 1
			     * peripheral:
			     *   SAI3   --> Only domain 1 can access
			     *   UART4  --> Only domain 1 can access
			     *   GPT1   --> Only domain 1 can access
			     *   SDMA3  --> Only domain 1 can access
			     *   I2C3   --> Only domain 1 can access
			     * memory:
			     *   TCM    --> Only domain 1 can access (0x7E0000~0x81FFFF)
			     *   DDR    --> Only domain 1 can access (0x80000000~0x81000000)
			     * end.
			     */
		start-config = <
			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
			    RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0
			    RDC_PDAP RDC_PDAP_I2C3  PDAP_D1_ACCESS 0x0 0x0
			    RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS
			    RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS
			    0x0      0x0            0x0  0x0 0x0
			  >;
			    /* rdc config when MCU stops
			     * memory:
			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
			     *   DDR    --> domain 0/1 can access (0x80000000~0x81000000)
			     * end.
			     */
		stop-config = <
			    RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS
			    RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS
			    0x0      0x0            0x0  0x0 0x0
			  >;
	};
};

&clk {
	u-boot,dm-pre-reloc;
	u-boot,dm-spl;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	/delete-property/ assigned-clock-rates;

};

&crypto {
	u-boot,dm-spl;
};

&eqos {
	compatible = "fsl,imx-eqos";
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-parents;
	/delete-property/ assigned-clock-rates;
};

&gpio1 {
	u-boot,dm-spl;
};

&gpio2 {
	u-boot,dm-spl;
};

&gpio3 {
	u-boot,dm-spl;
};

&gpio4 {
	u-boot,dm-spl;

	ctrl_sleep_moci {
		u-boot,dm-spl;
	};
};

&gpio5 {
	u-boot,dm-spl;
};

&i2c1 {
	u-boot,dm-spl;
};

&i2c2 {
	u-boot,dm-spl;
};

&i2c3 {
	u-boot,dm-spl;
};

&pinctrl_ctrl_sleep_moci {
	u-boot,dm-spl;
};

&pinctrl_i2c1 {
	u-boot,dm-spl;
};

&pinctrl_reg_usdhc2_vmmc {
	u-boot,dm-spl;
	u-boot,off-on-delay-us = <20000>;
};

&pinctrl_uart3 {
	u-boot,dm-spl;
};

&pinctrl_usdhc2_gpio {
	u-boot,dm-spl;
};

&pinctrl_usdhc2 {
	u-boot,dm-spl;
};

&pinctrl_usdhc3 {
	u-boot,dm-spl;
};

&pinctrl_wdog {
	u-boot,dm-spl;
};

&pmic {
	u-boot,dm-spl;
};

&reg_usdhc2_vmmc {
	u-boot,dm-spl;
};

&sec_jr0 {
	u-boot,dm-spl;
};

&sec_jr1 {
	u-boot,dm-spl;
};

&sec_jr2 {
	u-boot,dm-spl;
};

&uart3 {
	u-boot,dm-spl;
};

&usb3_0 {
	/delete-property/ power-domains;
};

&usb3_1 {
	/delete-property/ power-domains;
};

&usb_dwc3_0 {
	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
	assigned-clock-rates = <400000000>;
};

&usb_dwc3_1 {
	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
	assigned-clock-rates = <400000000>;
};

&usdhc2 {
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
	assigned-clock-rates = <400000000>;
	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	sd-uhs-ddr50;
	sd-uhs-sdr104;
	u-boot,dm-spl;
};

&usdhc3 {
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
	assigned-clock-rates = <400000000>;
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	u-boot,dm-spl;
};

&wdog1 {
	u-boot,dm-spl;
};