From 5c374c9ee16fee2bf68533cc4010b3c0df21f783 Mon Sep 17 00:00:00 2001 From: Julien May Date: Mon, 23 Jun 2008 13:57:52 +0200 Subject: Add support for the hammerhead (AVR32) board The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap700x/clk.h | 1 + include/configs/hammerhead.h | 172 ++++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+) create mode 100644 include/configs/hammerhead.h (limited to 'include') diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index a9d8431a66..e9a4fe4d64 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -82,6 +82,7 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id) #endif extern void clk_init(void); +extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h new file mode 100644 index 0000000000..ab13d2e32c --- /dev/null +++ b/include/configs/hammerhead.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2008 Miromico AG + * + * Configuration settings for the Miromico Hammerhead AVR32 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_HAMMERHEAD 1 + +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 125 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 25000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 5 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 + +#define CONFIG_HOSTNAME hammerhead + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=mtd1 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet address + * should be generated and assigned to the environment variables + * "ethaddr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) + +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Hammerhead> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) + +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 0eb5717a85b6cba3f67c11fa89bdde38dcd081b5 Mon Sep 17 00:00:00 2001 From: Hans-Christian Egtvedt Date: Wed, 6 Aug 2008 14:42:13 +0200 Subject: avr32: add support for EarthLCD Favr-32 board This patch adds support for the Favr-32 board made by EarthLCD. This kit, which is also called ezLCD-101 when running with EarthLCD firmware, has a 10.4" touch screen LCD panel, 16 MB 32-bit SDRAM, 8 MB parallel flash, Ethernet, audio out, USB device, SD-card slot, USART and various other connectors for cennecting stuff to SPI, I2C, GPIO, etc. Signed-off-by: Hans-Christian Egtvedt Signed-off-by: Haavard Skinnemoen --- include/configs/favr-32-ezkit.h | 201 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 include/configs/favr-32-ezkit.h (limited to 'include') diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h new file mode 100644 index 0000000000..6f77c256bd --- /dev/null +++ b/include/configs/favr-32-ezkit.h @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * Configuration settings for the Favr-32 EarthLCD LCD kit. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_FAVR32_EZKIT 1 + +#define CONFIG_FAVR32_EZKIT_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ +#define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ +#define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ +#define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k" + +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm $(fileaddr)" + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on Favr-32 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 13b50fe3bc065c48911fa373231421280855a9d6 Mon Sep 17 00:00:00 2001 From: Mark Jackson Date: Wed, 30 Jul 2008 13:07:27 +0100 Subject: avr32: Add MIMC200 board The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra 8MByte FLASH and 128KByte FRAM. Signed-off-by: Mark Jackson Signed-off-by: Haavard Skinnemoen --- include/configs/mimc200.h | 177 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 include/configs/mimc200.h (limited to 'include') diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h new file mode 100644 index 0000000000..3486be0ba5 --- /dev/null +++ b/include/configs/mimc200.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * Configuration settings for the AVR32 Network Gateway + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_MIMC200 1 + +#define CONFIG_MIMC200_EXT_FLASH 1 + +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 10000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 15 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 +#define CONFIG_MIMC200_DBGLINK 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock1 fbmem=600k rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm" + +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_SILENT_CONSOLE_INPUT 1 /* disable console inputs */ +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +/* + * Only interrupt autoboot if is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT 1 + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE + +#define CFG_FRAM_BASE 0x08000000 +#define CFG_FRAM_SIZE 0x20000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (1024*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) + +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 25da0b84195fdda89a943b2d25757db5afeef5b8 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 20 Aug 2008 09:27:37 +0200 Subject: favr-32-ezkit: Fix printf format warnings Signed-off-by: Haavard Skinnemoen --- include/configs/favr-32-ezkit.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 6f77c256bd..a27c02ad25 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -108,7 +108,7 @@ #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 #define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " -- cgit v1.2.3 From 33eac2b3d946fc998a09245dfe54d017079b9056 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 20 Aug 2008 09:28:36 +0200 Subject: hammerhead: Add missing printf parameter to CONFIG_AUTOBOOT_PROMPT Signed-off-by: Haavard Skinnemoen --- include/configs/hammerhead.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index ab13d2e32c..8e83daa376 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -83,7 +83,7 @@ #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 #define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" + "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " -- cgit v1.2.3