From 9c7dea602edd9027848d312e9b3b69f06c15f163 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 25 May 2015 22:35:04 +0800 Subject: x86: Refactor PIRQ routing support PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/dt-bindings/interrupt-router/intel-irq.h | 31 ++++++++++++++++++++++++ include/fdtdec.h | 1 + 2 files changed, 32 insertions(+) create mode 100644 include/dt-bindings/interrupt-router/intel-irq.h (limited to 'include') diff --git a/include/dt-bindings/interrupt-router/intel-irq.h b/include/dt-bindings/interrupt-router/intel-irq.h new file mode 100644 index 00000000000..5092f33dfa0 --- /dev/null +++ b/include/dt-bindings/interrupt-router/intel-irq.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2015, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_INTEL_IRQ_H_ +#define _DT_BINDINGS_INTEL_IRQ_H_ + +/* PCI interrupt pin */ +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +/* PIRQs */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* PCI bdf encoding */ +#ifndef PCI_BDF +#define PCI_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8) +#endif + +#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 6bf5f614e8b..64c7fa1955e 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -178,6 +178,7 @@ enum fdt_compat_id { COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ + COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_COUNT, }; -- cgit v1.2.3