From 92c20fbd3a7788c1a154f50a3f44f28a7763f99a Mon Sep 17 00:00:00 2001 From: John Rigby Date: Thu, 30 Oct 2008 16:39:35 -0600 Subject: ADS5121 DIU Make inclusion of FSL logo optional Make inclusion of FSL logo optional and turn it off by default. Signed-off-by: John Rigby --- include/configs/ads5121.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index bb3525f1751..bb38be6bf3d 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -47,6 +47,7 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ +#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */ /* video */ #undef CONFIG_VIDEO -- cgit v1.2.3 From abfbd0ae4967df18102345db4f4b529a13da107b Mon Sep 17 00:00:00 2001 From: Martha Marx Date: Mon, 26 Jan 2009 10:45:07 -0700 Subject: ADS5121 Add IC Ident Module (IIM) support IIM (IC Identification Module) is the fusebox for the mpc5121. Use #define CONFIG_IIM to turn on the clock for this module use #define CONFIG_CMD_FUSE to add fusebox commands. Fusebox commands include the ability to read the status, read the register cache, override the register cache, program the fuses and sense them. Signed-off-by: Martha Marx Signed-off-by: John Rigby --- include/asm-ppc/immap_512x.h | 20 +++++++++++++++++++- include/configs/ads5121.h | 6 ++++++ include/mpc512x.h | 24 ++++++++++++++++++++++++ 3 files changed, 49 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index cd9094519be..4cef6a83ef0 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -415,7 +415,25 @@ typedef struct ioctrl512x { * IIM */ typedef struct iim512x { - u8 fixme[0x1000]; + u32 stat; /* IIM status register */ + u32 statm; /* IIM status IRQ mask */ + u32 err; /* IIM errors register */ + u32 emask; /* IIM error IRQ mask */ + u32 fctl; /* IIM fuse control register */ + u32 ua; /* IIM upper address register */ + u32 la; /* IIM lower address register */ + u32 sdat; /* IIM explicit sense data */ + u8 res0[0x08]; + u32 prg_p; /* IIM program protection register */ + u8 res1[0x10]; + u32 divide; /* IIM divide factor register */ + u8 res2[0x7c0]; + u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ + u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ + u8 res3[0x380]; + u32 fbac1; /* IIM fuse bank 1 protection */ + u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ + u8 res4[0x380]; } iim512x_t; /* diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index bb38be6bf3d..0aca4a52aa5 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -294,6 +294,11 @@ #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #endif +/* + * IIM - IC Identification Module + */ +#undef CONFIG_IIM + /* * EEPROM configuration */ @@ -349,6 +354,7 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE +#undef CONFIG_CMD_FUSE #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/mpc512x.h b/include/mpc512x.h index 05a206358b0..714287c864a 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -574,6 +574,30 @@ void iopin_initialize(iopin_t *,int); /* Register Offset Base */ #define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800) +/* IIM control */ +#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5)) +#define IIM_SET_LA(f, bit) (((f & 0x0000001f) << 3) | bit) +#define IIM_STAT_BUSY 0x00000080 +#define IIM_STAT_PRGD 0x00000002 +#define IIM_STAT_SNSD 0x00000001 +#define IIM_ERR_WPE 0x00000040 +#define IIM_ERR_OPE 0x00000020 +#define IIM_ERR_RPE 0x00000010 +#define IIM_ERR_WLRE 0x00000008 +#define IIM_ERR_SNSE 0x00000004 +#define IIM_ERR_PARITYE 0x00000002 +#define IIM_PRG_P_SET 0x000000aa +#define IIM_PRG_P_UNSET 0 +#define IIM_FCTL_PROG_PULSE 0x00000020 +#define IIM_FCTL_PROG 0x00000001 +#define IIM_FCTL_ESNS_N 0x00000008 +#define IIM_FBAC_FBWP 0x00000080 +#define IIM_FBAC_FBOP 0x00000040 +#define IIM_FBAC_FBRP 0x00000020 +#define IIM_FBAC_FBESP 0x00000008 +#define IIM_PROTECTION 0x000000e8 +#define IIM_FMAX 31 + /* Number of I2C buses */ #define I2C_BUS_CNT 3 -- cgit v1.2.3 From 70a4da45e16b72e8e5b0baaecdaee9be8619647d Mon Sep 17 00:00:00 2001 From: Ralph Kondziella Date: Mon, 26 Jan 2009 12:34:36 -0700 Subject: ADS5121 Add PATA support Original patch from Ralph Kondziella plus clean up by Wolfgang Denk plus changes by John Rigby use ips clock not lpc port forward to current u-boot release Signed-off-by: Ralph Kondziella Signed-off-by: Wolfgang Denk Signed-off-by: John Rigby --- include/asm-ppc/immap_512x.h | 29 +++++++++++++++++++++++- include/configs/ads5121.h | 52 ++++++++++++++++++++++++++++++++++++++++++++ include/mpc512x.h | 1 + 3 files changed, 81 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 4cef6a83ef0..808786985e5 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -469,7 +469,34 @@ typedef struct lpc512x { * PATA */ typedef struct pata512x { - u8 fixme[0x100]; + /* LOCAL Registers */ + u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ + u32 pata_time2; /* Time register 2: PIO timing parameter */ + u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ + u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ + u32 pata_time5; /* Time register 5: UDMA timing parameter */ + u32 pata_time6; /* Time register 6: UDMA timing parameter */ + u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ + u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ + u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ + u32 pata_ata_control; /* ATA Interface control register */ + u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ + u32 pata_irq_enable; /* Interrupt enable register */ + u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ + u32 pata_fifo_alarm; /* fifo alarm threshold */ + u32 res1[0x1A]; + /* DRIVE Registers */ + u32 pata_drive_data; /* drive data register*/ + u32 pata_drive_features;/* drive features register */ + u32 pata_drive_sectcnt; /* drive sector count register */ + u32 pata_drive_sectnum; /* drive sector number register */ + u32 pata_drive_cyllow; /* drive cylinder low register */ + u32 pata_drive_cylhigh; /* drive cylinder high register */ + u32 pata_drive_dev_head;/* drive device head register */ + u32 pata_drive_command; /* write = drive command, read = drive status reg */ + u32 res2[0x06]; + u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ + u32 res3[0x09]; } pata512x_t; /* diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 0aca4a52aa5..8fda3f29fab 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -355,11 +355,19 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE #undef CONFIG_CMD_FUSE +#define CONFIG_CMD_IDE +#define CONFIG_CMD_EXT2 #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif +#if defined(CONFIG_CMD_IDE) +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif /* defined(CONFIG_CMD_IDE) */ + /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set @@ -496,4 +504,48 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@80000000/serial@11300" +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for IDE not supported */ + +#define CONFIG_IDE_RESET /* reset for IDE supported */ +#define CONFIG_IDE_PREINIT + +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA + +/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#define ATA_BASE_ADDR MPC512X_PATA + +/* + * Control register bit definitions + */ +#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 +#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 +#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 +#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 +#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 +#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 +#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 +#define FSL_ATA_CTRL_IORDY_EN 0x01000000 + #endif /* __CONFIG_H */ diff --git a/include/mpc512x.h b/include/mpc512x.h index 714287c864a..0f022939da6 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -573,6 +573,7 @@ void iopin_initialize(iopin_t *,int); /* Register Offset Base */ #define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800) +#define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200) /* IIM control */ #define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5)) -- cgit v1.2.3