From 075cbae1639189a9d9c76e74e954721f354f397a Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Tue, 16 Jan 2018 20:44:25 +0300 Subject: ARC: HSDK: CGU: Update AXI, TUN, ARC clock options Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin --- include/dt-bindings/clock/snps,hsdk-cgu.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h index 813ab715310..2cfe34eb35f 100644 --- a/include/dt-bindings/clock/snps,hsdk-cgu.h +++ b/include/dt-bindings/clock/snps,hsdk-cgu.h @@ -33,8 +33,10 @@ #define CLK_SYS_UART_REF 18 #define CLK_SYS_EBI_REF 19 #define CLK_TUN_PLL 20 -#define CLK_TUN 21 -#define CLK_HDMI_PLL 22 -#define CLK_HDMI 23 +#define CLK_TUN_TUN 21 +#define CLK_TUN_ROM 22 +#define CLK_TUN_PWM 23 +#define CLK_HDMI_PLL 24 +#define CLK_HDMI 25 #endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */ -- cgit v1.2.3