From c40b6df87fc0193a7184ada9f53aaf57cdec0cdf Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Mon, 25 Feb 2019 08:14:49 +0000 Subject: clk: Add SiFive FU540 PRCI clock driver Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf --- include/dt-bindings/clk/sifive-fu540-prci.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clk/sifive-fu540-prci.h b/include/dt-bindings/clk/sifive-fu540-prci.h new file mode 100644 index 0000000000..531523ea62 --- /dev/null +++ b/include/dt-bindings/clk/sifive-fu540-prci.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Copyright (C) 2018 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H +#define __LINUX_CLK_SIFIVE_FU540_PRCI_H + +/* Clock indexes for use by Device Tree data */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif -- cgit v1.2.3