From 90832f970e6b6a9940325016d7f46d75869ccb39 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 10 Jun 2018 19:48:59 -0700 Subject: MLK-18591-9 android: iot: Add board support for imx6ul pico-som Add board support for imx6ul pico-som, porting from v2017.03 Signed-off-by: Ye Li --- include/configs/picosom-imx6ul.h | 251 ++++++++++++++++++++++++ include/configs/picosom-imx6ul_android_things.h | 62 ++++++ 2 files changed, 313 insertions(+) create mode 100644 include/configs/picosom-imx6ul.h create mode 100644 include/configs/picosom-imx6ul_android_things.h (limited to 'include/configs') diff --git a/include/configs/picosom-imx6ul.h b/include/configs/picosom-imx6ul.h new file mode 100644 index 0000000000..727b0dd351 --- /dev/null +++ b/include/configs/picosom-imx6ul.h @@ -0,0 +1,251 @@ +/* + * Copyright (C) 2015 Technexion Ltd. + * Copyright 2018 NXP + * + * Configuration settings for the Technexion PicoSOM i.mx6UL board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __PICOSOM_IMX6UL_CONFIG_H +#define __PICOSOM_IMX6UL_CONFIG_H + + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE MX6UL_UART6_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */ +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#endif + +/* I2C configs */ +#define CONFIG_CMD_I2C +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + + +#define PHYS_SDRAM_SIZE SZ_512M + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 + + +/* #define CONFIG_VIDEO */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc5\0" \ + "bootargs=console=ttymxc5,115200 ubi.mtd=3 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=TFT43AB\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc5\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_SIZE SZ_8K + +#ifdef CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_QSPI_BASE QSPI0_BASE_ADDR +#define CONFIG_QSPI_MEMMAP_BASE QSPI0_AMBA_BASE + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (13 * SZ_64K) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (384 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (60 << 20) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define PRODUCT_NAME "imx6ul_pico" +#define VARIANT_NAME "imx6ul_pico" + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) +#include "picosom-imx6ul_android_things.h" +#endif + +#endif diff --git a/include/configs/picosom-imx6ul_android_things.h b/include/configs/picosom-imx6ul_android_things.h new file mode 100644 index 0000000000..a0c580a6a1 --- /dev/null +++ b/include/configs/picosom-imx6ul_android_things.h @@ -0,0 +1,62 @@ + +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PICOSOM_IMX6UL_ANDROID_THINGS_H +#define __PICOSOM_IMX6UL_ANDROID_THINGS_H + +#ifdef CONFIG_AVB_ATX +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 32 +#endif + +#define AVB_RPMB +#ifdef AVB_RPMB +#define KEYSLOT_BLKS 0xFFF +#define KEYSLOT_HWPARTITION_ID 2 +#endif + +#include "mx_android_common.h" +#define TRUSTY_OS_ENTRY 0x9e000000 +#define TRUSTY_OS_RAM_SIZE 0x2000000 +#define TRUSTY_OS_MMC_BLKS 0xFFF +#define TEE_HWPARTITION_ID 2 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NON_SECURE_FASTBOOT +#endif +/* For NAND we don't support lock/unlock */ +#ifndef CONFIG_NAND_BOOT +#define CONFIG_FASTBOOT_LOCK +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT +#define FSL_FASTBOOT_FB_DEV "mmc" +#endif + +#define CONFIG_ANDROID_AB_SUPPORT +#define CONFIG_FSL_CAAM_KB +#define CONFIG_CMD_FSL_CAAM_KB +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_AVB_SUPPORT +#define CONFIG_SYSTEM_RAMDISK_SUPPORT +#ifdef CONFIG_AVB_SUPPORT + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#define CONFIG_SUPPORT_EMMC_RPMB +/* fuse bank size in word */ +#define CONFIG_AVB_FUSE_BANK_SIZEW 8 +#define CONFIG_AVB_FUSE_BANK_START 10 +#define CONFIG_AVB_FUSE_BANK_END 15 +#endif + + +#endif +/* __PICOSOM_IMX6UL_ANDROID_THINGS_H */ -- cgit v1.2.3