From bf56080769f13025daaeb80d967eea19e7f78d60 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 10 Sep 2010 23:04:05 +0200 Subject: 4xx: add missing CONFIG_SYS_SRAM_SIZE definition A number of boards define CONFIG_SYS_SRAM_BASE but fail to define CONFIG_SYS_SRAM_SIZE which is needed when cleaning up the code that prints this information with the bdinfo command. Add the missing deinitions. Signed-off-by: Wolfgang Denk Cc: Stefan Roese Acked-by: Stefan Roese --- include/configs/bubinga.h | 1 + include/configs/canyonlands.h | 1 + include/configs/intip.h | 1 + include/configs/luan.h | 1 + include/configs/t3corp.h | 1 + 5 files changed, 5 insertions(+) (limited to 'include/configs') diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 627060a759..159a265d25 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -179,6 +179,7 @@ * (Set up by the startup code) */ #define CONFIG_SYS_SRAM_BASE 0xFFF00000 +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_FLASH_BASE 0xFFF80000 /*----------------------------------------------------------------------- diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 6fe7639e86..e2c58a51ab 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -111,6 +111,7 @@ #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ diff --git a/include/configs/intip.h b/include/configs/intip.h index 19f12fa770..0c0bb373bd 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -93,6 +93,7 @@ #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ diff --git a/include/configs/luan.h b/include/configs/luan.h index b158b741ba..ccd9397df4 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -53,6 +53,7 @@ #define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ #define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ #define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ +#define CONFIG_SYS_SRAM_SIZE (1 << 20) #define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index b38886b53f..41ee15b229 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -86,6 +86,7 @@ #define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ -- cgit v1.2.3 From 36116650440406f99cc2c309f8f7c8388da46241 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 11 Aug 2010 09:38:31 +0200 Subject: Cleanup use of CONFIG_SYS_SRAM_BASE and CONFIG_SYS_SRAM_SIZE Traditionally many boards used local definitions for SRAM base address and size (like SRAM_BASE, SRAM_LEN and/or SRAM_SIZE), while the (now) "official" names are CONFIG_SYS_SRAM_BASE and CONFIG_SYS_SRAM_SIZE. The corresponding code in arch/powerpc/lib/board.c was board specific, and has never actually been maintained well. Replace this by feature- specific code and adapt the boards that actually use this. NOTE: there is still a ton of boards using the old #defines, which therefor contain incorrect values in bi_sramstart and bi_sramsize. All respective board maintainers are requested to clean up their respective configurations. Thanks. Signed-off-by: Wolfgang Denk Cc: Josef Wagner Cc: Stefan Roese Cc: Heiko Schocher Cc: Wolfgang Denk --- include/configs/CPC45.h | 5 +++-- include/configs/IP860.h | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index 91d262a22c..668cfa2ebb 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -347,13 +347,12 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define SRAM_BASE 0x80000000 /* SRAM base address */ -#define SRAM_END 0x801FFFFF /*----------------------------------------------------------------------*/ /* CPC45 Memory Map */ /*----------------------------------------------------------------------*/ #define SRAM_BASE 0x80000000 /* SRAM base address */ +#define SRAM_END 0x801FFFFF #define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ #define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ #define BCSR_BASE 0x80600000 /* board control / status registers */ @@ -361,6 +360,8 @@ #define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ #define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ +#define CONFIG_SYS_SRAM_BASE SRAM_BASE +#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1) /*---------------------------------------------------------------------*/ /* CPC45 Control/Status Registers */ diff --git a/include/configs/IP860.h b/include/configs/IP860.h index be63ea5736..ed6b7fde9c 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -375,6 +375,8 @@ extern unsigned long ip860_get_clk_freq (void); #define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK))) #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */ +#define CONFIG_SYS_SRAM_BASE SRAM_BASE +#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE /* * BR4/OR4 - Board Control & Status (8 bit) -- cgit v1.2.3 From d2e22731c86b54f863c2a3afa54306a77cb60fca Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 1 Jul 2010 09:44:39 +0200 Subject: IceCube.h: update configuration Increase malloc size, enable command line editing and history, enable hush shell. Signed-off-by: Wolfgang Denk --- include/configs/IceCube.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 5d3a744fff..396110016b 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -280,7 +280,7 @@ #endif #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* @@ -317,6 +317,10 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ -- cgit v1.2.3 From 6d014adfa2ac4b1151d2b80a6943f59c3e254239 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 20 Jun 2010 16:03:45 +0200 Subject: Remove support for CONFIG_HAS_UID and "forceenv" command This (undocumented) concept was only in use for the MVSMR and davinci_schmoogie Sergey Kubushyn boards. Drop it for now. If really needed, it should be reimplemented later in the context of the new environment command set. Signed-off-by: Wolfgang Denk Cc: Andre Schwarz Cc: Sergey Kubushyn Acked-by: Sergey Kubushyn --- include/configs/MVSMR.h | 1 - include/configs/davinci_schmoogie.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h index 6492068c2f..000c4c6dcd 100644 --- a/include/configs/MVSMR.h +++ b/include/configs/MVSMR.h @@ -185,7 +185,6 @@ */ #define CONFIG_ENV_IS_IN_FLASH #undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_HAS_UID #define CONFIG_OVERWRITE_ETHADDR_ONCE #define CONFIG_ENV_OFFSET 0x8000 diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 875dda4442..04cdc210e6 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -99,7 +99,6 @@ /*=====================*/ #define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ #define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ -#define CONFIG_HAS_UID #define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ #define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */ /*==============================*/ -- cgit v1.2.3 From d1831c5ee61a2d3f8c2248eb9822d5a9c8c9c017 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 13 Sep 2010 12:12:33 +0200 Subject: mpc52xx: Cleanup use of CONFIG_SYS_SRAM_BASE and CONFIG_SYS_SRAM_SIZE cleanup for the uc101 and the mucmc52 board. Signed-off-by: Heiko Schocher --- include/configs/mucmc52.h | 2 ++ include/configs/uc101.h | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h index 07ed046199..f87dc9c650 100644 --- a/include/configs/mucmc52.h +++ b/include/configs/mucmc52.h @@ -80,6 +80,8 @@ #define CONFIG_SYS_CS1_SIZE 0x00100000 #define CONFIG_SYS_CS1_CFG 0x00019B00 +#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE + /* FRAM 32Kbyte @0x80700000 */ #define CONFIG_SYS_CS2_START 0x80700000 #define CONFIG_SYS_CS2_SIZE 0x00008000 diff --git a/include/configs/uc101.h b/include/configs/uc101.h index fc0b103fbb..19722615a6 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -65,9 +65,7 @@ #define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */ /* SRAM */ -#define SRAM_BASE CONFIG_SYS_SRAM_BASE -#define SRAM_LEN 0x1fffff -#define SRAM_END (SRAM_BASE + SRAM_LEN) +#define CONFIG_SYS_SRAM_SIZE 0x200000 /* * GPIO configuration -- cgit v1.2.3 From c3330e9d6a11b6ead4a2346001338ce884b5832b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 17 Sep 2010 13:10:30 +0200 Subject: ARM (ARM926ejs): add data cache support, tested on magnesium and tx25 board Enable "cache" command on tx25 and magnesium board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- magnesium 32,6s 22,5s 30s = x 1,09 tx25 (29MB only) 9,69s 5,05s 8,16s = x 1,19 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- magnesium 4,25s 2,08s 1,72s = x 2,47 tx25 4,82s 2,04s 1,84s = x 2,62 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Alessandro Rubini Signed-off-by: Heiko Schocher Cc: Alessandro Rubini --- include/configs/imx27lite-common.h | 1 + include/configs/tx25.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include/configs') diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 1da860261a..33550ba661 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -188,6 +188,7 @@ */ #include #define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_FAT diff --git a/include/configs/tx25.h b/include/configs/tx25.h index c8188ca525..013aa3541c 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -131,6 +131,7 @@ /* U-Boot commands */ #include #define CONFIG_CMD_NAND +#define CONFIG_CMD_CACHE /* * Ethernet -- cgit v1.2.3 From 95c6f6d34d4ff23f4d005488d84682eec5fa9ec8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 17 Sep 2010 13:10:31 +0200 Subject: ARM V7 (OMAP): add data cache support, test on Beagle board Add data cache support for ARM V7 systems. Used cache flush functions from linux:arch/arm/mm/cache-v7.S developed from Catalin Marinas. Enable "cache" command on Beagle board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- Beagle (Cortex A8) 116s 106s 30.3s = x 3.8 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- Beagle (Cortex A8) 1.84s 1.64s 0.12s = x 15.3 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher Reviewed-by: Ben Gardiner --- include/configs/omap3_beagle.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 71553f9a08..3f6e803eb9 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -120,6 +120,7 @@ /* commands to include */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -- cgit v1.2.3 From 7e4a9e6dc819b2b3499659ca90e1e9c6d4ca3077 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 17 Sep 2010 13:10:32 +0200 Subject: ARM (ARM11): add data cache support, test on Qong board Add data cache support for arm1136 systems. Enable "cache" command on Qong board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- QONG (ARM11) 177s 95s 43s = x 4.1 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- QONG (ARM11) 1.54s 0.95s 0.18s = x 8.6 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher --- include/configs/qong.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/qong.h b/include/configs/qong.h index 100fa3f8ac..4735b5eb88 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -104,6 +104,7 @@ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_NET -- cgit v1.2.3 From e48b7c0aad687f0b42ba9985c3e2dc67c2cac71d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 17 Sep 2010 13:10:40 +0200 Subject: ARM: implement relocation for ARM11 Change the implementation for ARM11 to relocate the code to an arbitrary address in RAM. Tested on the qong board. Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher --- include/configs/qong.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/configs') diff --git a/include/configs/qong.h b/include/configs/qong.h index 4735b5eb88..7a68b7b97e 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -282,4 +282,14 @@ extern int qong_nand_rdy(void *chip); "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ "128k(env2),2432k(kernel),13m(ramdisk),-(user)" +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + +#define CONFIG_BOARD_EARLY_INIT_F 1 + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 561142af20f1fd7b425d9425730014e656defb91 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 17 Sep 2010 13:10:41 +0200 Subject: ARM: implement relocation for ARM V7 (OMAP) Change the implementation for ARM V7 to relocate the code to an arbitrary address in RAM. Adapt the Beagle board (Cortex A8) to test the changes. Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher --- include/configs/omap3_beagle.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/configs') diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 3f6e803eb9..2463be416e 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -340,4 +340,9 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ -- cgit v1.2.3 From ab86f72c354f9b2572340f72b74ca0a258c451bd Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 17 Sep 2010 13:10:42 +0200 Subject: ARM: implement relocation for ARM926 Change the implementation for arm926 to relocate the code to an arbitrary address in RAM. Adapt the TX25 (i.MX25), magnesium board to test the changes. On the tx25 board TEXT_BASE is set to the final relocation address to prevent one more copying of u-boot code when relocating. More info see: doc/README.arm-relocation da850 board: Tested-by: Ben Gardiner Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher Cc: Ben Gardiner --- include/configs/da850evm.h | 6 +++++- include/configs/imx27lite-common.h | 5 +++++ include/configs/km_arm.h | 4 ++++ include/configs/tx25.h | 13 +++++++++---- 4 files changed, 23 insertions(+), 5 deletions(-) (limited to 'include/configs') diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 357715d660..016a21e9d0 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ /* * Memory Info @@ -137,4 +136,9 @@ #undef CONFIG_CMD_ENV #endif +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 33550ba661..812e5f2e71 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -235,4 +235,9 @@ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) #endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 1617e697de..8673e6ff64 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -180,4 +180,8 @@ int get_scl (void); #undef CONFIG_JFFS2_CMDLINE #endif +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_INIT_SP_ADDR (0x00000000 + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 013aa3541c..c798570aec 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -40,9 +40,9 @@ /* Start copying real U-boot from the second page */ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 -/* Load U-Boot to this address */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x81f00000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST + +#define CONFIG_SYS_NAND_U_BOOT_DST (0x81fc0000) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_SPARE_SIZE 64 @@ -52,7 +52,6 @@ #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #else #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT #endif #define CONFIG_DISPLAY_CPUINFO @@ -177,4 +176,10 @@ "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \ "upd=run load update\0" \ +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 97003756249bd790910417eb66f0039bbf06a02c Mon Sep 17 00:00:00 2001 From: Ben Gardiner Date: Mon, 23 Aug 2010 09:08:15 -0400 Subject: da8xx: fixup ARM relocation support Split the existing dram_init for da8xx when ARM reloc is enabled, like the changes to arch/arm/cpu/arm926ejs/orion5x/dram.c in 0f234d263b17ccf1b8fd776eb8c15b7cdb27a887 by Heiko Schocher . Without these changes gd->ram_size is '0' which leads to incorrect relocation when CONFIG_SYS_ARM_WITHOUT_RELOC is defined and the board does not boot. We use get_ram_size to dynamically calculate the available RAM because it runs on different board version with different ram, as suggested by Heiko in private communication. Tested on a da850evm with 128M of DDR2 installed; with both CONFIG_SYS_ARM_WITHOUT_RELOC defined and undefined. Signed-off-by: Ben Gardiner Reviewed-by: Sudhakar Rajashekhara CC: Sudhakar Rajashekhara CC: Heiko Schocher --- include/configs/da850evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/configs') diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 016a21e9d0..d02b1968b9 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -47,6 +47,7 @@ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) -- cgit v1.2.3 From 90964353ffbddc554317ccfd9821b012f95449ab Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 19 Sep 2010 12:40:02 +0200 Subject: aev board: Fix compile problems Recent changes caused thatthe aev board now is included in the boards built by MAKEALL, which revealed that compilation for this board has been broken for a long time: mpc5xxx_fec.c:899:2: error: #error fec->xcv_type not initialized. mpc5xxx_fec.c:899:2: error: #error fec->xcv_type not initialized. Fix it. Signed-off-by: Wolfgang Denk --- include/configs/aev.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/aev.h b/include/configs/aev.h index 98958a6237..54e6c57c8e 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -286,10 +286,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* -- cgit v1.2.3 From 77efe35fec0d93804e3a3a5bf4d1bb25f52bfde5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 19 Sep 2010 21:28:25 +0200 Subject: Remove HMI10 board support Recent changes caused that the HMI10 board now is included in the boards built by MAKEALL, which revealed that compilation for this board has been broken for a long time: ps2ser.c: In function 'ps2ser_init': ps2ser.c:155: error: 'UART_LCR' undeclared (first use in this function) ps2ser.c:155: error: (Each undeclared identifier is reported only once ps2ser.c:155: error: for each function it appears in.) ps2ser.c:156: error: 'UART_DLL' undeclared (first use in this function) ps2ser.c:157: error: 'UART_DLM' undeclared (first use in this function) ps2ser.c:159: error: 'UART_IER' undeclared (first use in this function) ps2ser.c:160: error: 'UART_MCR' undeclared (first use in this function) ps2ser.c:161: error: 'UART_FCR' undeclared (first use in this function) ps2ser.c:162: error: 'UART_FCR_ENABLE_FIFO' undeclared (first use in this function) ps2ser.c:166: error: 'UART_LSR' undeclared (first use in this function) ps2ser.c: In function 'ps2ser_putc': ps2ser.c:198: error: 'UART_LSR' undeclared (first use in this function) ps2ser.c:200: error: 'UART_TX' undeclared (first use in this function) ps2ser.c: In function 'ps2ser_getc_hw': ps2ser.c:224: error: 'UART_LSR' undeclared (first use in this function) ps2ser.c:225: error: 'UART_RX' undeclared (first use in this function) ps2ser.c: In function 'ps2ser_interrupt': ps2ser.c:293: error: 'UART_IIR' undeclared (first use in this function) The board is orphaned, and AFAICT has reached EOL. Drop support for it. Signed-off-by: Wolfgang Denk --- include/configs/HMI10.h | 504 ------------------------------------------------ 1 file changed, 504 deletions(-) delete mode 100644 include/configs/HMI10.h (limited to 'include/configs') diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h deleted file mode 100644 index 2747d8cce8..0000000000 --- a/include/configs/HMI10.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_HMI10 -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_LCD -#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 2 /* .. on COM3 */ -#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/HMI10/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOARD_EARLY_INIT_R 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_SPLASH_SCREEN - #define CONFIG_CMD_BMP -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0100000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4100000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8100000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC100000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 5 -#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ -#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#endif - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From 9ddc3af8a13ab4d24b562531984dec99221b23c1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 19 Sep 2010 21:32:37 +0200 Subject: Remove smmaco4 board support Recent changes caused that the smmaco4 board now is included in the boards built by MAKEALL, which revealed that compilation for this board has been broken for a long time: mpc5xxx_fec.c:899:2: error: #error fec->xcv_type not initialized. The board is orphaned. Drop support for it. Signed-off-by: Wolfgang Denk --- include/configs/smmaco4.h | 379 ---------------------------------------------- 1 file changed, 379 deletions(-) delete mode 100644 include/configs/smmaco4.h (limited to 'include/configs') diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h deleted file mode 100644 index 060026bb64..0000000000 --- a/include/configs/smmaco4.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/smmaco4/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/smmaco4/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From ca5def3f30860a97cc76453eb846fffbde997035 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 31 Aug 2010 10:00:10 +0200 Subject: cfi_flash: Simplify dynamic flash bank number detection This patch simplifies the use of CONFIG_SYS_MAX_FLASH_BANKS_DETECT. By moving these optional variables and defines into the common code, board specific code is minimized. Currently only the following board use this feature: APC405, IDS8247, TQM834x And IDS8247 doesn't seem to really need this feature, since its not updating the bank number variable at all. So this patch removes the definition of CONFIG_SYS_MAX_FLASH_BANKS_DETECT from this board port. This new framework will be used by the upcoming lwmon5 update as well. Signed-off-by: Stefan Roese Acked-by: Heiko Schocher Cc: Matthias Fuchs --- include/configs/APC405.h | 6 ------ include/configs/IDS8247.h | 3 +-- include/configs/TQM834x.h | 4 ---- 3 files changed, 1 insertion(+), 12 deletions(-) (limited to 'include/configs') diff --git a/include/configs/APC405.h b/include/configs/APC405.h index a7724adb42..bb0238f4f0 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -264,16 +264,10 @@ /* * FLASH organization */ -#ifndef __ASSEMBLY__ -extern int flash_banks; -#endif - #define CONFIG_SYS_FLASH_BASE 0xFE000000 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS flash_banks /* max num of flash banks */ - /* updated in board_early_init_r */ #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 #define CONFIG_SYS_FLASH_QUIET_TEST 1 #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 71bb7b48c8..4e73941fcf 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -227,7 +227,7 @@ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ /* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk * The main FLASH is whichever is connected to *CS0. @@ -242,7 +242,6 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c1e0e6429a..9193b5107f 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -101,10 +101,6 @@ * defined as tqm834x_num_flash_banks. */ #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 -#ifndef __ASSEMBLY__ -extern int tqm834x_num_flash_banks; -#endif -#define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -- cgit v1.2.3 From b9d74b48107d139333322288f9c1c4989f5d7659 Mon Sep 17 00:00:00 2001 From: Matthias Weisser Date: Tue, 21 Sep 2010 15:37:44 +0200 Subject: arm: Make jadecpu board use relocation This patch modifies jadecpu board so that it is usable with the relocation patches by Heiko Schocher Signed-off-by: Matthias Weisser --- include/configs/jadecpu.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/configs') diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h index 29c534c4a9..a5d8764b51 100644 --- a/include/configs/jadecpu.h +++ b/include/configs/jadecpu.h @@ -146,6 +146,9 @@ #define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR 0x01008000 + /* * FLASH and environment organization */ -- cgit v1.2.3 From e69e520f9d235bb7d96296081fdfc09b9fee8c46 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 31 Aug 2010 19:56:43 -0500 Subject: fsl: refactor MPC8610 and MPC5121 DIU code to use existing bitmap and logo features The Freescale MPC8610 and MPC5121 DIU code had re-implement two features that already existed in U-Boot: bitmap drawing and top-of-screen logo (CONFIG_VIDEO_LOGO). So delete the 8610-specific code and use the built-in features instead. Signed-off-by: Timur Tabi --- include/configs/MPC8610HPCD.h | 5 ++++- include/configs/mpc5121ads.h | 6 ++++-- 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 4d9606e498..58d3d995fa 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -24,9 +24,12 @@ /* video */ #undef CONFIG_VIDEO -#if defined(CONFIG_VIDEO) +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO #endif #ifdef RUN_DIAG diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 5281042efd..272502a2ff 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -47,14 +47,16 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ -#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */ /* video */ #undef CONFIG_VIDEO -#if defined(CONFIG_VIDEO) +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO #endif /* CONFIG_PCI is defined at config time */ -- cgit v1.2.3 From 5e7abce99163a00b8d267cc8045f06b498728288 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 11 Sep 2010 09:31:43 +0200 Subject: ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese --- include/configs/PPChameleonEVB.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'include/configs') diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 44f03dc390..09f3544ae0 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -577,17 +577,6 @@ #define DIMM_READ_ADDR 0xAB #define DIMM_WRITE_ADDR 0xAA -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - /* Defines for CPC0_PLLMR1 Register fields */ #define PLL_ACTIVE 0x80000000 #define CPC0_PLLMR1_SSCS 0x80000000 -- cgit v1.2.3 From afabb498b749b48ca3ee7e833fe1501e2d6993cb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 12 Sep 2010 06:21:37 +0200 Subject: ppc4xx: Big header cleanup part 2, mostly PPC405 related This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese --- include/configs/ASH405.h | 10 +++++----- include/configs/CATcenter.h | 12 ++++++------ include/configs/CMS700.h | 12 ++++++------ include/configs/DP405.h | 12 ++++++------ include/configs/G2000.h | 10 +++++----- include/configs/HH405.h | 10 +++++----- include/configs/HUB405.h | 10 +++++----- include/configs/PLU405.h | 10 +++++----- include/configs/PPChameleonEVB.h | 12 ++++++------ include/configs/VOH405.h | 10 +++++----- include/configs/VOM405.h | 12 ++++++------ include/configs/WUH405.h | 10 +++++----- include/configs/bubinga.h | 10 +++++----- include/configs/quad100hd.h | 10 +++++----- include/configs/zeus.h | 10 +++++----- 15 files changed, 80 insertions(+), 80 deletions(-) (limited to 'include/configs') diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 4cb805223c..98bd6f32e5 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -335,12 +335,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 229a5138e5..da85442b1e 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -535,13 +535,13 @@ * GPIO0[30] - EMAC0 input * GPIO0[31] - EMAC1 reject packet as output */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1L 0x15555444 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ +#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 /* diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 2b6786b9dc..ede99700f1 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -301,12 +301,12 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 4423f2ab62..0ee456bbd0 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -243,12 +243,12 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000540 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ /* diff --git a/include/configs/G2000.h b/include/configs/G2000.h index d2883eb8d7..4d29f21553 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -367,12 +367,12 @@ * * following GPIO setting changed for G20000, 080304 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40005555 -#define CONFIG_SYS_GPIO0_OSRL 0x40000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40005555 +#define CONFIG_SYS_GPIO0_OSRH 0x40000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 /* diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 01e0bc65ec..d940a886d2 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -461,12 +461,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555440 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0017 #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 8c6d5edff7..72e907b66d 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -334,12 +334,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index f917eb5c25..a3087829de 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -379,12 +379,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x00000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 09f3544ae0..e9cae85f5c 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -542,13 +542,13 @@ * GPIO0[30] - EMAC0 input * GPIO0[31] - EMAC1 reject packet as output */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1L 0x15555444 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ +#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 /* diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 9c91fccb11..21bb5b6d4b 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -388,12 +388,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555440 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x00000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0x777E0017 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 871e4c339e..747d6a08d6 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -273,12 +273,12 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ /* diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index be9ac6261c..7756d3aad0 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -332,12 +332,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 159a265d25..05c4766b57 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -284,12 +284,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x55555555 -#define CONFIG_SYS_GPIO0_OSRL 0x40000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x55555555 +#define CONFIG_SYS_GPIO0_OSRH 0x40000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xFFFF8014 /*----------------------------------------------------------------------- diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 5538b18ef8..b7781873b6 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -270,12 +270,12 @@ * Taken in part from PPCBoot board/icecube/icecube.h */ /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ -#define CONFIG_SYS_GPIO0_OSRH 0x55555550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x55555550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xFFFF8097 #define CONFIG_SYS_GPIO0_ODR 0x00000000 diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 3b2aede4fd..1ae990ff40 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -279,12 +279,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x15555550 /* Chip selects */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */ -#define CONFIG_SYS_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */ -#define CONFIG_SYS_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */ +#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */ +#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ #define CONFIG_SYS_GPIO0_ODR 0x00000000 -- cgit v1.2.3 From 550650ddd0fde00f245bc3da72d7272844198394 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Sep 2010 16:05:31 +0200 Subject: ppc4xx: Use common NS16550 driver for PPC4xx UART This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese --- include/configs/APC405.h | 6 ++++++ include/configs/AR405.h | 6 ++++++ include/configs/ASH405.h | 7 ++++++- include/configs/CANBT.h | 6 ++++++ include/configs/CATcenter.h | 6 +++++- include/configs/CMS700.h | 7 ++++++- include/configs/CPCI2DP.h | 7 ++++++- include/configs/CPCI405.h | 6 ++++++ include/configs/CPCI4052.h | 6 ++++++ include/configs/CPCI405AB.h | 6 ++++++ include/configs/CPCI405DT.h | 6 ++++++ include/configs/CPCIISER4.h | 6 ++++++ include/configs/CRAYL1.h | 6 ++++++ include/configs/DP405.h | 7 ++++++- include/configs/DU405.h | 6 ++++++ include/configs/DU440.h | 9 +++++---- include/configs/ERIC.h | 6 ++++++ include/configs/G2000.h | 7 ++++++- include/configs/HH405.h | 7 ++++++- include/configs/HUB405.h | 7 ++++++- include/configs/JSE.h | 8 ++++++-- include/configs/KAREF.h | 6 +++++- include/configs/METROBOX.h | 6 +++++- include/configs/MIP405.h | 6 ++++++ include/configs/OCRTC.h | 6 ++++++ include/configs/ORSG.h | 6 ++++++ include/configs/PCI405.h | 6 ++++++ include/configs/PIP405.h | 6 ++++++ include/configs/PLU405.h | 7 ++++++- include/configs/PMC405.h | 6 ++++++ include/configs/PMC405DE.h | 7 ++++++- include/configs/PMC440.h | 11 ++++++----- include/configs/PPChameleonEVB.h | 6 ++++++ include/configs/VOH405.h | 7 ++++++- include/configs/VOM405.h | 7 ++++++- include/configs/W7OLMC.h | 6 ++++++ include/configs/W7OLMG.h | 6 ++++++ include/configs/WUH405.h | 7 ++++++- include/configs/XPEDITE1000.h | 7 ++++++- include/configs/acadia.h | 1 + include/configs/alpr.h | 8 ++++++-- include/configs/amcc-common.h | 6 +++++- include/configs/bamboo.h | 6 ++---- include/configs/bubinga.h | 1 + include/configs/canyonlands.h | 4 +--- include/configs/csb272.h | 6 ++++++ include/configs/csb472.h | 6 ++++++ include/configs/dlvision.h | 1 + include/configs/ebony.h | 2 +- include/configs/gdppc440etx.h | 7 +++++-- include/configs/hcu5.h | 4 ---- include/configs/icon.h | 3 +-- include/configs/intip.h | 4 +--- include/configs/katmai.h | 3 +-- include/configs/kilauea.h | 4 +--- include/configs/korat.h | 10 +++++----- include/configs/luan.h | 4 +--- include/configs/lwmon5.h | 10 +++++----- include/configs/makalu.h | 4 +--- include/configs/neo.h | 6 ++++++ include/configs/netstal-common.h | 5 +++++ include/configs/ocotea.h | 2 +- include/configs/p3p440.h | 7 ++++++- include/configs/pcs440ep.h | 8 +++++--- include/configs/quad100hd.h | 5 +++++ include/configs/redwood.h | 6 +++++- include/configs/sbc405.h | 6 ++++++ include/configs/sc3.h | 5 +++++ include/configs/sequoia.h | 6 +----- include/configs/t3corp.h | 4 +--- include/configs/taihu.h | 2 +- include/configs/taishan.h | 3 +-- include/configs/walnut.h | 1 + include/configs/yosemite.h | 4 +--- include/configs/yucca.h | 3 +-- include/configs/zeus.h | 12 ++++++++---- 76 files changed, 340 insertions(+), 96 deletions(-) (limited to 'include/configs') diff --git a/include/configs/APC405.h b/include/configs/APC405.h index bb0238f4f0..cb3f80bfa0 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -176,6 +176,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 45c64c2d2c..568ce15c7b 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -127,6 +127,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 98bd6f32e5..789f7501fd 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -124,9 +124,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 115a6f9886..ad075b80b8 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -100,6 +100,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index da85442b1e..550c462b88 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -86,7 +86,11 @@ # error "* External frequency (SysClk) not defined! *" #endif -#define CONFIG_UART1_CONSOLE 1 /* Use second UART */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index ede99700f1..9c57acb00c 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -122,9 +122,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 922121173a..c6882fdda3 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -111,9 +111,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 3e7020df89..da57b04bba 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -125,6 +125,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d3000f6578..d682d3726f 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -134,6 +134,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index d3763441ef..1c521f2a3f 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -133,6 +133,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 07acab0c2b..c7b79311cc 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -135,6 +135,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index 5b50bcf331..f114290130 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -110,6 +110,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 9ab30ecbaf..f6cd760811 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -47,6 +47,12 @@ #define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ #define CONFIG_NET_MULTI +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) #define CONFIG_PRAM 16 diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 0ee456bbd0..5311dfb006 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -97,9 +97,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 8f1fc78bce..0907c3ab06 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -109,6 +109,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 830466f7a8..9c3499406f 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -64,9 +64,6 @@ #define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH #define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */ -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -86,10 +83,14 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index e07f9a1dc5..da3b4ae22a 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -139,6 +139,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180 /* The following table includes the supported baudrates */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 4d29f21553..e2e6cb29ce 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -151,9 +151,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index d940a886d2..0db9298611 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -176,9 +176,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 72e907b66d..5dea96ef5b 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -118,9 +118,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 98f5661a09..c692b5458d 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -95,9 +95,13 @@ #define CONFIG_ENV_OFFSET 0x00 #define CONFIG_ENV_SIZE 512 - /* The JSE connects UART1 to the console tap connector. */ -#define CONFIG_UART1_CONSOLE 1 +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + /* Set console baudrate to 9600 */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 49a7378f27..f936ae57de 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -59,7 +59,6 @@ #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -91,6 +90,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SERIAL_MULTI 1 #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index e7429dd199..7f2542c1f3 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -153,6 +152,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SERIAL_MULTI 1 #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 7e6484ee94..e833e6d193 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -176,6 +176,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 916667 diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 55471af34a..ad2e4da389 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -105,6 +105,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 142471362f..3d35362ffd 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -105,6 +105,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 0d443ea2d4..244d6fe502 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -110,6 +110,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 3e57c0b92f..2901cfd6d6 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -167,6 +167,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index a3087829de..928ed8e15b 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -135,9 +135,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 00a12fb833..c420efe812 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -130,6 +130,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ #define CONFIG_SYS_BASE_BAUD 806400 diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 2c048dd0dd..5b1048efb4 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -107,9 +107,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 3c19f52d9c..fd2e9a9f96 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -72,9 +72,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 #define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */ -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -95,10 +92,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -#undef CONFIG_UART1_CONSOLE /* console on front panel */ +#define CONFIG_SERIAL_MULTI 1 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index e9cae85f5c..f9b20143a0 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -191,6 +191,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 21bb5b6d4b..b9ea6104e9 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -133,9 +133,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 747d6a08d6..a88b41a969 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -120,9 +120,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index f06bfe5521..0fbe80ce8c 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -125,6 +125,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 384000 diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index be8c9f82ef..f12fa55d2a 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -133,6 +133,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 384000 diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 7756d3aad0..34a5fff138 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -122,9 +122,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h index cf39aeaaf7..f76ede3ce6 100644 --- a/include/configs/XPEDITE1000.h +++ b/include/configs/XPEDITE1000.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) @@ -112,6 +111,12 @@ extern void out32(unsigned int, unsigned long); /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/acadia.h b/include/configs/acadia.h index bd3388f626..b6f909c110 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -89,6 +89,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/alpr.h b/include/configs/alpr.h index ee0c14d960..75106b4278 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 @@ -75,9 +74,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 23a859fcb4..9c53d3785c 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -31,8 +31,12 @@ /* * UART */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 8c4127da08..18276c5886 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -62,8 +62,7 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ /*Don't change either of these*/ #define CONFIG_SYS_USB_DEVICE 0x50000000 @@ -85,9 +84,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * NVRAM/RTC diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 05c4766b57..336e69ea93 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -123,6 +123,7 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index e2c58a51ab..51087f7371 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -114,8 +114,6 @@ #define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ - #define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */ /*----------------------------------------------------------------------- @@ -130,7 +128,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 9ded330664..71082109ee 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -160,6 +160,12 @@ * UART configuration * */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ #undef CONFIG_SYS_BASE_BAUD #define CONFIG_BAUDRATE 38400 /* Default baud rate */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 71eb083e33..7b9f29ac32 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -159,6 +159,12 @@ * UART configuration * */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 38400 /* Default baud rate */ diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index 4533799971..5916db6e99 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -97,6 +97,7 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 10f425dd1e..09357d9086 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -61,7 +61,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -81,6 +80,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index d193919dc5..d6db7bf494 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -59,7 +59,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ /*Don't change either of these*/ @@ -80,8 +79,12 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_UART1_CONSOLE /* * Environment diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 26d2d0c9d3..6694f53378 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -70,9 +70,6 @@ #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -94,7 +91,6 @@ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_BAUDRATE 115200 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/icon.h b/include/configs/icon.h index 7a4e60cbc0..779af25fae 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -52,7 +52,6 @@ * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ @@ -106,7 +105,7 @@ /* * Serial Port */ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* diff --git a/include/configs/intip.h b/include/configs/intip.h index 0c0bb373bd..82c828284a 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -96,8 +96,6 @@ #define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ - #define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ /* @@ -113,7 +111,7 @@ /* * Serial Port */ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /* * Environment diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 2a7ab8de0e..884dd74a17 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -61,7 +61,6 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ @@ -105,7 +104,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /*----------------------------------------------------------------------- diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 48dc9463a8..937d7c5e24 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -57,7 +57,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 #define CONFIG_SYS_NAND_ADDR 0xF8000000 #define CONFIG_SYS_FPGA_BASE 0xF0000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ /*----------------------------------------------------------------------- * Initial RAM & Stack Pointer Configuration Options @@ -115,8 +114,7 @@ * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/korat.h b/include/configs/korat.h index f95df684ea..0107a7b943 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -71,9 +71,6 @@ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000) -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -93,11 +90,14 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/luan.h b/include/configs/luan.h index ccd9397df4..6b1a41f8e0 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -58,8 +58,6 @@ #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */ - #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ @@ -88,8 +86,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ -#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 6461124e56..9df6fc77f7 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -62,9 +62,6 @@ #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -106,11 +103,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -/* define this if you want console on UART1 */ -#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 52339f9c63..83a2d4a65a 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -55,7 +55,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xFC000000 #define CONFIG_SYS_FPGA_BASE 0xF0000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ /*----------------------------------------------------------------------- * Initial RAM & Stack Pointer Configuration Options @@ -112,9 +111,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no ext. clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/neo.h b/include/configs/neo.h index f275c7b2a3..fde814b1e5 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -98,6 +98,12 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index cb7efe7abc..8f42b6c62c 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -34,7 +34,12 @@ /* * UART */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 2e809b0f33..b388a406fd 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -58,7 +58,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -81,6 +80,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index d6b92070a9..6edf91ecc6 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -80,6 +79,12 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 1f744b875d..85152d12a3 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -60,7 +60,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ /*Don't change either of these*/ @@ -80,11 +79,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index b7781873b6..0764cc85e3 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -105,6 +105,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/redwood.h b/include/configs/redwood.h index 4b744a7949..913db9480a 100644 --- a/include/configs/redwood.h +++ b/include/configs/redwood.h @@ -47,7 +47,6 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -77,6 +76,11 @@ #define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */ #define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ + /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 429b11c196..187002c107 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -147,6 +147,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 19084cec43..094d38b270 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -76,6 +76,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SERIAL_MULTI #undef CONFIG_SERIAL_SOFTWARE_FIFO /* diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 568d9fc0cd..900d1dbdcb 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -84,9 +84,6 @@ #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -105,9 +102,8 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE /* * Environment diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 41ee15b229..39ca7930ba 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -89,8 +89,6 @@ #define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ - /* * Initial RAM & stack pointer (placed in OCM) */ @@ -104,7 +102,7 @@ /* * Serial Port */ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /* * Environment diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 836081d0d5..a9954e4573 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -127,11 +127,11 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE 1 /*----------------------------------------------------------------------- * I2C stuff diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 6423fd7f48..ce4a612256 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -50,7 +50,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -77,7 +76,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ /*----------------------------------------------------------------------- diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 630c0d3a3c..191c28fc3a 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -84,6 +84,7 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index b66ab58d86..ed0560ad97 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -62,7 +62,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ /*Don't change either of these*/ @@ -84,9 +83,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 0b4dfb8e73..dfba50859a 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -60,7 +60,6 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ @@ -106,7 +105,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 1ae990ff40..6fbf38a329 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -122,14 +122,18 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /*----------------------------------------------------------------------- * Miscellaneous configurable options -- cgit v1.2.3 From 24956642ef7de5d8340683d721113f993ffaa0a8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 15 Sep 2010 09:33:25 +0200 Subject: Remove unused CONFIG_SERIAL_SOFTWARE_FIFO feature This patch removes the completely unused CONFIG_SERIAL_SOFTWARE_FIFO feature from U-Boot. It has only been implemented for PPC4xx and was not used at all. So let's remove it and make the code smaller and cleaner. Signed-off-by: Stefan Roese Acked-by: Detlev Zundel --- include/configs/AP1000.h | 6 ------ include/configs/ATUM8548.h | 1 - include/configs/JSE.h | 6 ------ include/configs/KAREF.h | 1 - include/configs/METROBOX.h | 1 - include/configs/ML2.h | 10 ---------- include/configs/MPC8308RDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8323ERDB.h | 1 - include/configs/MPC832XEMDS.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC8360EMDS.h | 1 - include/configs/MPC8360ERDK.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC837XERDB.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8540ADS.h | 1 - include/configs/MPC8540EVAL.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/MVBLM7.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/P2020DS.h | 1 - include/configs/PM854.h | 1 - include/configs/SBC8540.h | 1 - include/configs/TQM834x.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/aria.h | 1 - include/configs/bubinga.h | 1 - include/configs/dlvision.h | 1 - include/configs/eNET.h | 1 - include/configs/ebony.h | 1 - include/configs/hcu5.h | 1 - include/configs/kmeter1.h | 1 - include/configs/mcu25.h | 7 ------- include/configs/mecp5123.h | 1 - include/configs/mpc5121ads.h | 1 - include/configs/neo.h | 1 - include/configs/ocotea.h | 1 - include/configs/sbc8349.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8560.h | 1 - include/configs/sbc8641d.h | 1 - include/configs/sc3.h | 8 -------- include/configs/socrates.h | 1 - include/configs/stxssa.h | 1 - include/configs/taihu.h | 1 - include/configs/vme8349.h | 1 - include/configs/walnut.h | 1 - include/configs/yucca.h | 1 - 58 files changed, 90 deletions(-) (limited to 'include/configs') diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index ae0a8731fa..e7070756d5 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -52,12 +52,6 @@ #define CONFIG_BOOTCOMMAND "" /* autoboot command */ -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - #define CONFIG_BOOTARGS "console=ttyS0,57600" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c133033bcc..58f0c1f997 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -200,7 +200,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/JSE.h b/include/configs/JSE.h index c692b5458d..b0b117575c 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -105,12 +105,6 @@ /* Set console baudrate to 9600 */ #define CONFIG_BAUDRATE 9600 -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - /* * Configuration related to auto-boot. * diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index f936ae57de..a44d8fabbc 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -95,7 +95,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SERIAL_MULTI 1 #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 7f2542c1f3..d805a245df 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -157,7 +157,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SERIAL_MULTI 1 #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/ML2.h b/include/configs/ML2.h index 5fcc1733bc..2fc0119e5f 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -52,16 +52,6 @@ #define CONFIG_PREBOOT "fsload 0x00100000 /boot/image" -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#if 0 -#define CONFIG_SERIAL_SOFTWARE_FIFO 4000 -#else -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#endif - #if 0 #define CONFIG_BOOTARGS "root=/dev/nfs " \ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 6cd5da7950..c6f12bd729 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -279,7 +279,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index f1b110b9d6..70072555e5 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -298,7 +298,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 9a296a1e4a..590005d927 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -262,7 +262,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 68ff191667..99577563ba 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -273,7 +273,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 73dbea4b74..eaa8a9deff 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -283,7 +283,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 9be571fecf..4c6c2737f4 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -329,7 +329,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index c58e0031ae..c8db10b2b9 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -307,7 +307,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 9fa577df9b..2685deed78 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -237,7 +237,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 9092755c6d..bdf8a2a0bf 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -299,7 +299,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 79dadc4a54..675021cf51 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -316,7 +316,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 2a3c058619..0a9f47b97c 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -400,7 +400,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 577c276107..c133895873 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -237,7 +237,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 7daf934d02..75227a6ade 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -173,7 +173,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 8797b3099d..c3167e9ddf 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -263,7 +263,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d1ac32f4ad..1804582499 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -214,7 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 33f49f5f08..e1e4acf616 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -282,7 +282,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 0f71f11c65..b0dd17528b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -261,7 +261,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 2dc2932524..a98ecde8d2 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -244,7 +244,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 8177db371a..8ffd4583b5 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -276,7 +276,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #define CONFIG_SERIAL_MULTI 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 081661e6b3..34ebbdbc34 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -333,7 +333,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 58d3d995fa..645d947a5d 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -221,7 +221,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 974cb6ba7d..3b80d14e98 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -275,7 +275,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index c28eb64fb1..5b12b88c8c 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -150,7 +150,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 7e901e17cc..fa45b5be17 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -281,7 +281,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 79ce2c0a8b..74cff0c6a7 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -337,7 +337,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 7426bcadfd..cf8a8cf49c 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -174,7 +174,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 5d424dd75f..d6b3cb8ca5 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -205,7 +205,6 @@ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 9193b5107f..be0fe7228c 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -162,7 +162,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index abbaf383c7..ccb339de06 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -256,7 +256,6 @@ #else /* !CONFIG_TQM8560 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/aria.h b/include/configs/aria.h index c5f9cc1046..01e347e690 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -321,7 +321,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /* * Serial console configuration diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 336e69ea93..3e64492cd0 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -124,7 +124,6 @@ * set Linux BASE_BAUD to 403200. */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index 5916db6e99..21d2d284a6 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -98,7 +98,6 @@ * set Linux BASE_BAUD to 403200. */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 361fe61b04..da2a97d26d 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -59,7 +59,6 @@ * Serial Configuration */ #define CONFIG_SERIAL_MULTI -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 09357d9086..8c3284a94d 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -81,7 +81,6 @@ * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ /*----------------------------------------------------------------------- diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 6694f53378..10b1e0feee 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -90,7 +90,6 @@ *----------------------------------------------------------------------*/ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_BAUDRATE 115200 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index f7d36b1ff2..1dcdeab9bb 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -257,7 +257,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index 5f31198836..604298675e 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -86,16 +86,9 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - /* Set console baudrate to 9600 */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 92c4f5fdb3..539c8c18fb 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -218,7 +218,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /* * Serial console configuration diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 272502a2ff..e999e0609d 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -286,7 +286,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /* * Serial console configuration diff --git a/include/configs/neo.h b/include/configs/neo.h index fde814b1e5..f8f53e8f37 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -104,7 +104,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index b388a406fd..4f59cc6bdc 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -81,7 +81,6 @@ * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ /*----------------------------------------------------------------------- diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index deaddde3bf..e85e8f7ef4 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -270,7 +270,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 564f661bcb..8d047dec8d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -338,7 +338,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 53d06ed698..635227800e 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -203,7 +203,6 @@ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 618513ab66..a7831c0545 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -257,7 +257,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 094d38b270..278b60ebbc 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -82,14 +82,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SERIAL_MULTI -#undef CONFIG_SERIAL_SOFTWARE_FIFO -/* - * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input - * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature - */ -#if CONFIG_SERIAL_SOFTWARE_FIFO - #define CONFIG_POWER_DOWN -#endif /* * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz diff --git a/include/configs/socrates.h b/include/configs/socrates.h index af1e19ee0a..88be34914e 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -218,7 +218,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 57bb8d1a38..911c906492 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -176,7 +176,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/taihu.h b/include/configs/taihu.h index a9954e4573..7e660eea02 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -128,7 +128,6 @@ * set Linux BASE_BAUD to 403200. */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index f493e75d6f..ec533b8f35 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -184,7 +184,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 191c28fc3a..3be489da5f 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -85,7 +85,6 @@ * set Linux BASE_BAUD to 403200. */ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/yucca.h b/include/configs/yucca.h index dfba50859a..a540355188 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -107,7 +107,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ -- cgit v1.2.3 From 5b9144638e7d4c86e0470e21869b341278e183c3 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Tue, 21 Sep 2010 09:38:04 +0200 Subject: ppx4xx: remove unused functionality for DU405 boards Remove some unused functionality to make U-Boot build again. Especially PCI is not used on the board. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/DU405.h | 31 +++++-------------------------- 1 file changed, 5 insertions(+), 26 deletions(-) (limited to 'include/configs') diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 0907c3ab06..6ba9f13bf1 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -73,6 +73,11 @@ #include #undef CONFIG_CMD_NFS +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS #define CONFIG_CMD_IDE #define CONFIG_CMD_ELF #define CONFIG_CMD_MII @@ -131,32 +136,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- -- cgit v1.2.3 From e8d3ca8b339a2697d14550790c3a0e3748b2358c Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 30 Aug 2010 18:04:52 -0500 Subject: mpc831xerdb: enable mtdparts for NAND The default partition table matches the .dts files for these boards in Linux. This allows these partitions to be used by name with U-Boot's "nand" command. Signed-off-by: Scott Wood Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 9 ++++++++- include/configs/MPC8315ERDB.h | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 524afa5c6e..adf05ee439 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semiconductor, Inc. 2006. + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. * * See file CREDITS for list of people who contributed to this * project. @@ -232,6 +232,13 @@ #define CONFIG_SYS_NAND_BASE 0xE2800000 #endif +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITION +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=e2800000.flash" +#define MTDPARTS_DEFAULT \ + "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 70072555e5..a5d4375ae1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. * * Dave Liu * @@ -243,6 +243,13 @@ #define CONFIG_SYS_NAND_BASE 0xE0600000 #endif +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITION +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=e0600000.flash" +#define MTDPARTS_DEFAULT \ + "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 -- cgit v1.2.3 From 9f530d59e63f6a4584e0caee54f92255c7ed59ab Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Fri, 10 Sep 2010 15:42:32 -0700 Subject: e300: increase CONFIG_SYS_BOOTMAPSZ to allow booting large kernels Newer Linux kernels can overrun the initial memory window used for booting with their BSS area. When this happens, they overwrite the FDT and silently fail to boot. On e300 CPUs, the Linux kernel uses an initial BAT covering the first 256MB of RAM. See arch/powerpc/kernel/head_32.S for details. Increase the value of CONFIG_SYS_BOOTMAPSZ to accommodate the maximum value allowed by Linux. This will allow very large kernels to boot. Signed-off-by: Ira W. Snyder Signed-off-by: Kim Phillips --- include/configs/MPC8308RDB.h | 4 ++-- include/configs/MPC8313ERDB.h | 4 ++-- include/configs/MPC8315ERDB.h | 4 ++-- include/configs/MPC8323ERDB.h | 4 ++-- include/configs/MPC832XEMDS.h | 4 ++-- include/configs/MPC8349EMDS.h | 4 ++-- include/configs/MPC8349ITX.h | 4 ++-- include/configs/MPC8360EMDS.h | 4 ++-- include/configs/MPC8360ERDK.h | 4 ++-- include/configs/MPC837XEMDS.h | 4 ++-- include/configs/MPC837XERDB.h | 4 ++-- include/configs/MVBLM7.h | 4 ++-- include/configs/SIMPC8313.h | 4 ++-- include/configs/TQM834x.h | 4 ++-- include/configs/aria.h | 4 ++-- include/configs/kmeter1.h | 4 ++-- include/configs/mecp5123.h | 4 ++-- include/configs/mpc5121ads.h | 4 ++-- include/configs/pdm360ng.h | 4 ++-- include/configs/sbc8349.h | 4 ++-- include/configs/ve8313.h | 4 ++-- include/configs/vme8349.h | 4 ++-- 22 files changed, 44 insertions(+), 44 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index c6f12bd729..d919871ee3 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -438,10 +438,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index adf05ee439..3fdd1b0d2f 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -460,10 +460,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index a5d4375ae1..abc29c04fe 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -535,10 +535,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 590005d927..0719fcea32 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -429,10 +429,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 99577563ba..bed62bd6eb 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -446,10 +446,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index eaa8a9deff..55e9de01ae 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -495,10 +495,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 4c6c2737f4..117f745f26 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -538,10 +538,10 @@ boards, we say we have two, but don't display a message if we find only one. */ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index c8db10b2b9..d7381aad32 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -486,10 +486,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 2685deed78..fc53ecc67a 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -403,10 +403,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index bdf8a2a0bf..8546ebc31f 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -536,10 +536,10 @@ extern int board_pci_host_broken(void); /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 675021cf51..20c23045fb 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -544,10 +544,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 5b12b88c8c..25d8077314 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -299,10 +299,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_HRCW_LOW 0x0 #define CONFIG_SYS_HRCW_HIGH 0x0 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 70b7489ab1..9c8c318573 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -373,10 +373,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index be0fe7228c..d0c6a4dc5d 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -354,10 +354,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ diff --git a/include/configs/aria.h b/include/configs/aria.h index 01e347e690..c5a3febd0f 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -506,10 +506,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 1dcdeab9bb..4794256160 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -357,10 +357,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 539c8c18fb..a26de0bcb4 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -343,10 +343,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Linux initial memory map */ /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index e999e0609d..3740316d6b 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -478,10 +478,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 718abdf42b..f073fcd7d8 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -412,11 +412,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e85e8f7ef4..b8f4b6eee8 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -464,10 +464,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 56d24f9014..45976db217 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -366,10 +366,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ /* 0x64050000 */ #define CONFIG_SYS_HRCW_LOW (\ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ec533b8f35..f2fb59203f 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -401,10 +401,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -- cgit v1.2.3 From 65ea758939a7bcbc87fe1c1bd816a98176bc2a9b Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Fri, 17 Sep 2010 23:41:49 +0200 Subject: MPC8308RDB: various clean ups This patch cleans up the Freescale MPC8308RDB Development board support. Things fixed: - Removed unused PCIE2 definitions from configuration - SICR{L,H} defines used for System I/O Configuration Registers values instead of hardcoding - CONFIG_SYS_SCCR_PCIEXP1CM used to enable PCIE clock instead of writing to SCCR from the board code - sleep mode stuff removed as MPC8308 has no support for deep sleep and PMCCR1 register. board_early_init_f() removed. - MPC8308 has no ERRATA for DDR controller so workaround removed - 'assignment in if statement' issues solved - use LBLAWAR_* defines instead of hardcoding Signed-off-by: Ilya Yanok Signed-off-by: Kim Phillips --- include/configs/MPC8308RDB.h | 46 +++++++++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 20 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index d919871ee3..13142719da 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -85,10 +85,27 @@ /* * System IO Config */ -#define CONFIG_SYS_SICRH 0x01b7d103 -#define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */ - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_SD |\ + SICRH_ESDHC_B_SD |\ + SICRH_ESDHC_C_SD |\ + SICRH_GPIO_A_TSEC2 |\ + SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_CRS |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V2P5 |\ + SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ /* * IMMR new address @@ -218,7 +235,7 @@ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) #define CONFIG_SYS_BR0_PRELIM (\ CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ @@ -260,7 +277,7 @@ /* 0xFFFF8396 */ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #ifdef CONFIG_VSC7385_ENET #define CONFIG_TSEC2 @@ -270,7 +287,7 @@ /* Access window base at VSC7385 base */ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access window size 128K */ -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 #define CONFIG_VSC7385_IMAGE_SIZE 8192 @@ -335,19 +352,8 @@ #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 -/* - * Fake PCIE2 definitions: there is no PCIE2 on this board but the code - * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this - */ -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 #define CONFIG_PCI #define CONFIG_PCIE -- cgit v1.2.3 From bc8f8c2614c8e104a66198633d8d765b720ed907 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Fri, 17 Sep 2010 23:41:50 +0200 Subject: mpc8308_p1m: support for MPC8308 P1M board This patch provides support for MPC8308 P1M board with the following set of features: Dual UART is supported NOR flash is supported Both TSEC Ethernet controllers are supported PCI Express initialization is supported Both I2C controllers are supported Signed-off-by: Ilya Yanok Signed-off-by: Kim Phillips --- include/configs/mpc8308_p1m.h | 555 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 555 insertions(+) create mode 100644 include/configs/mpc8308_p1m.h (limited to 'include/configs') diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h new file mode 100644 index 0000000000..0f8270b3a5 --- /dev/null +++ b/include/configs/mpc8308_p1m.h @@ -0,0 +1,555 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ + +/* + * On-board devices + * + * TSECs + */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz + * We choose the A type silicon as default, so the core is 400Mhz. + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_3X1) +/* + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits + * in 8308's HRCWH according to the manual, but original Freescale's + * code has them and I've expirienced some problems using the board + * with BDI3000 attached when I've tried to set these bits to zero + * (UART doesn't work after the 'reset run' command). + */ +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_MII |\ + HRCWH_TSEC2M_IN_MII |\ + HRCWH_BIG_ENDIAN) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_GPIO |\ + SICRH_ESDHC_B_GPIO |\ + SICRH_ESDHC_C_GTM |\ + SICRH_GPIO_A_TSEC2 |\ + SICRH_GPIO_B_TSEC2_TX_CLK |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_CRS |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V3P3 |\ + SICRH_TSOBI2_V3P3) /* 0xf577d100 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ + +#define CONFIG_SYS_GPIO1_PRELIM +/* GPIO Default input/output settings */ +#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 +/* + * Default GPIO values: + * LED#1 enabled; WLAN enabled; Both COM LED on (orange) + */ +#define CONFIG_SYS_GPIO1_DAT 0x08008C00 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of two chips HY5PS12621BFP-C4 from HYNIX + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (6 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x27256222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x121048c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03600100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE) + /* 0x43080000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=3, AL=1 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ + +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) + +#define CONFIG_SYS_BR0_PRELIM (\ + CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ + (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ + BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_4 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) +/* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) + +/* + * SJA1000 CAN controller on Local Bus + */ +#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_SJA1000_BASE \ + | (1 << BR_PS_SHIFT) /* 8 bit port size */ \ + | BR_V ) /* valid */ +#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_GPCM_SCY_5 \ + | OR_GPCM_EHTR) + /* 0xFFFF8052 */ + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +/* + * CPLD on Local Bus + */ +#define CONFIG_SYS_CPLD_BASE 0xFBFF8000 +#define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \ + | (1 << BR_PS_SHIFT) /* 8 bit port size */ \ + | BR_V ) /* valid */ +#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_GPCM_SCY_4 \ + | OR_GPCM_EHTR) + /* 0xFFFF8042 */ + +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 + +#define CONFIG_PCI +#define CONFIG_PCIE + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_NET_MULTI +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS 0 +#define TSEC2_FLAGS 0 + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=${consoledev},${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "kernel_addr=FC0A0000\0" \ + "fdt_addr=FC2A0000\0" \ + "ramdisk_addr=FC2C0000\0" \ + "u-boot=mpc8308_p1m/u-boot.bin\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr_r=C00000\0" \ + "hostname=mpc8308_p1m\0" \ + "bootfile=mpc8308_p1m/uImage\0" \ + "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ + "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "bootcmd=run flash_self\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 9eda770b460161e6d6112c67cec0f46ec8d44921 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 22 Sep 2010 15:36:27 -0500 Subject: mpc83xx: extend CONFIG_SYS_BOOTMAPSZ increase to mpc8308_p1m continuation of commit 39da1ba923d55f316f9f1bb3a960e4ed91dc17ac: "e300: increase CONFIG_SYS_BOOTMAPSZ to allow booting large kernels" Signed-off-by: Kim Phillips --- include/configs/mpc8308_p1m.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 0f8270b3a5..b5a19e4a86 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -437,7 +437,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup -- cgit v1.2.3