From 1ba62f10172ead798a8176435cfffff2f79f21c5 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 29 Feb 2012 12:36:51 +0000 Subject: powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- include/configs/P1010RDB.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f2d33668d8..08fc4e8427 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -181,7 +181,7 @@ /* DDR Setup */ #define CONFIG_FSL_DDR3 -#define CONFIG_DDR_RAW_TIMING +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 3098c5acfe..a8db06f05d 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -227,7 +227,7 @@ /* DDR Setup */ #define CONFIG_FSL_DDR3 -#define CONFIG_DDR_RAW_TIMING +#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 -- cgit v1.2.3