From 4621fc3fe7cd65b78b3cbd31f65c9f7f72b22bd3 Mon Sep 17 00:00:00 2001
From: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Tue, 15 Jan 2008 13:39:44 -0600
Subject: ColdFire: Add MCF547x_8x related header files

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off by: John Rigby <jrigby@freescale.com>
---
 include/asm-m68k/immap.h | 93 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

(limited to 'include/asm-m68k/immap.h')

diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 9dd970772a3..916bf966135 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -273,4 +273,97 @@
 #endif
 #endif				/* CONFIG_M54455 */
 
+#ifdef CONFIG_M547x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CFG_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+
+#define FEC0_RX_TASK		0
+#define FEC0_TX_TASK		1
+#define FEC0_RX_PRIORITY	6
+#define FEC0_TX_PRIORITY	7
+#define FEC0_RX_INIT		16
+#define FEC0_TX_INIT		17
+#define FEC1_RX_TASK		2
+#define FEC1_TX_TASK		3
+#define FEC1_RX_PRIORITY	6
+#define FEC1_TX_PRIORITY	7
+#define FEC1_RX_INIT		30
+#define FEC1_TX_INIT		31
+#endif
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x100))
+
+#ifdef CONFIG_SLTTMR
+#define CFG_UDELAY_BASE		(MMAP_SLT1)
+#define CFG_TMR_BASE		(MMAP_SLT0)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO		(INT0_HI_SLT0)
+#define CFG_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0x1E)
+#define CFG_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#endif
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0		(0x40000000)
+#define CFG_PCI_BAR1		(CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0		(CFG_MBAR)
+#define CFG_PCI_TBATR1		(CFG_SDRAM_BASE)
+#endif
+#endif				/* CONFIG_M547x */
+
+#ifdef CONFIG_M548x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CFG_FEC0_IOBASE		(MMAP_FEC0)
+#define CFG_FEC1_IOBASE		(MMAP_FEC1)
+
+#define FEC0_RX_TASK		0
+#define FEC0_TX_TASK		1
+#define FEC0_RX_PRIORITY	6
+#define FEC0_TX_PRIORITY	7
+#define FEC0_RX_INIT		16
+#define FEC0_TX_INIT		17
+#define FEC1_RX_TASK		2
+#define FEC1_TX_TASK		3
+#define FEC1_RX_PRIORITY	6
+#define FEC1_TX_PRIORITY	7
+#define FEC1_RX_INIT		30
+#define FEC1_TX_INIT		31
+#endif
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x100))
+
+/* Timer */
+#ifdef CONFIG_SLTTMR
+#define CFG_UDELAY_BASE		(MMAP_SLT1)
+#define CFG_TMR_BASE		(MMAP_SLT0)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
+#define CFG_TMRINTR_NO		(INT0_HI_SLT0)
+#define CFG_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0x1E)
+#define CFG_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#endif
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+
+#ifdef CONFIG_PCI
+#define CFG_PCI_BAR0		(CFG_MBAR)
+#define CFG_PCI_BAR1		(CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0		(CFG_MBAR)
+#define CFG_PCI_TBATR1		(CFG_SDRAM_BASE)
+#endif
+#endif				/* CONFIG_M548x */
+
 #endif				/* __IMMAP_H */
-- 
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