From cf6eca7ccd9025e9f34f179682516f1e5d7e0e78 Mon Sep 17 00:00:00 2001 From: Lawrence Yu Date: Fri, 4 Mar 2016 09:08:56 -0800 Subject: sunxi: Configure only LVDS pins instead of all LCD pins when LVDS interface selected The behavior before this patch would attempt to configure the mux setting for pins 0 to 27 on PORTD to all be setting 3 for LVDS. The LVDS interface actually only uses pins 18 to 27 and not pins 0 to 27 as in the parallel LCD interface. This patch restricts the configuration to only the relevant pins 18 to 27 on PORTD. This was tested on a sun8i A33 tablet with an LVDS screen. MMC1 has the capability to use pins 2 to 7 on PORTD and the mux on those pins was being inadvertently set to setting 3 for MMC functionality which this patch corrects. Signed-off-by: Lawrence Yu [hdegoede@redhat.com: Only apply this change to A23 / A33] Signed-off-by: Hans de Goede --- drivers/video/sunxi_display.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 9fee66a2a45..56f6c8e3497 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -767,7 +767,11 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode, (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; int bp, clk_delay, clk_div, clk_double, pin, total, val; +#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS + for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) { +#else for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) { +#endif #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0); #endif -- cgit v1.2.3 From b813ef0252b0532318195491f8b53011b22d6f16 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 18 Mar 2016 08:43:04 +0100 Subject: sunxi: Add a bunch of missing compatible strings to sunxi_gpio.c The kernel has different compatible strings for the pio block because the pin-muxing is different on all the different SoCs, but sunxi_gpio.c only support the basic gpio functionality, which is identical everywhere. Add the missing compatible strings for various SoC models. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/gpio/sunxi_gpio.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 9d8f11ef302..a7cec18d57f 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -277,9 +277,17 @@ static int gpio_sunxi_bind(struct udevice *parent) start = 'L' - 'A'; no_banks = 2; /* L & M */ } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset, - "allwinner,sun8i-a23-r-pinctrl") == 0) { + "allwinner,sun8i-a23-r-pinctrl") == 0 || + fdt_node_check_compatible(gd->fdt_blob, parent->of_offset, + "allwinner,sun8i-a83t-r-pinctrl") == 0 || + fdt_node_check_compatible(gd->fdt_blob, parent->of_offset, + "allwinner,sun8i-h3-r-pinctrl") == 0) { start = 'L' - 'A'; no_banks = 1; /* L only */ + } else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset, + "allwinner,sun9i-a80-r-pinctrl") == 0) { + start = 'L' - 'A'; + no_banks = 3; /* L, M & N */ } else { start = 0; no_banks = SUNXI_GPIO_BANKS; @@ -316,9 +324,14 @@ static const struct udevice_id sunxi_gpio_ids[] = { { .compatible = "allwinner,sun7i-a20-pinctrl" }, { .compatible = "allwinner,sun8i-a23-pinctrl" }, { .compatible = "allwinner,sun8i-a33-pinctrl" }, + { .compatible = "allwinner,sun8i-a83t-pinctrl", }, + { .compatible = "allwinner,sun8i-h3-pinctrl" }, { .compatible = "allwinner,sun9i-a80-pinctrl" }, { .compatible = "allwinner,sun6i-a31-r-pinctrl" }, { .compatible = "allwinner,sun8i-a23-r-pinctrl" }, + { .compatible = "allwinner,sun8i-a83t-r-pinctrl" }, + { .compatible = "allwinner,sun8i-h3-r-pinctrl", }, + { .compatible = "allwinner,sun9i-a80-r-pinctrl", }, { } }; -- cgit v1.2.3 From 948603d4d637a0e04a3214253b911cfc4ed11220 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 21 Mar 2016 14:44:35 +0100 Subject: sunxi: Fix 2nd usb controller on sun4i/sun7i no longer working The 2nd usb controller on sun4i/sun7i has its base address 0x8000 bytes from the 1st one, rather then 0x1000. Also the ahb clk gates are interleaved with the ohci clk-gates introducing a hole between the clks for usb1 and usb2. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/usb/host/ehci-sunxi.c | 13 +++++++++++-- drivers/usb/host/ohci-sunxi.c | 15 ++++++++++++--- 2 files changed, 23 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index cf3dcc43274..677a5d3b07f 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -17,6 +17,14 @@ #include #include "ehci.h" +#ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 +#define AHB_CLK_DIST 2 +#else +#define BASE_DIST 0x1000 +#define AHB_CLK_DIST 1 +#endif + struct ehci_sunxi_priv { struct ehci_ctrl ehci; int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ @@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice *dev) #ifdef CONFIG_MACH_SUN8I_H3 priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0; #endif - priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1; - priv->ahb_gate_mask <<= priv->phy_index - 1; + priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST; + priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; + priv->phy_index++; /* Non otg phys start at 1 */ setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); #ifdef CONFIG_SUNXI_GEN_SUN6I diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 1b1f6516978..d4fb95abe1e 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -17,6 +17,14 @@ #include #include "ohci.h" +#ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 +#define AHB_CLK_DIST 2 +#else +#define BASE_DIST 0x1000 +#define AHB_CLK_DIST 1 +#endif + struct ohci_sunxi_priv { ohci_t ohci; int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ @@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice *dev) priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0; #endif priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1; - priv->ahb_gate_mask <<= priv->phy_index - 1; - priv->usb_gate_mask <<= priv->phy_index - 1; + priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; + priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; + priv->usb_gate_mask <<= priv->phy_index; + priv->phy_index++; /* Non otg phys start at 1 */ setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask); -- cgit v1.2.3