From 30b5d9aa9aee9853b6b51d93ddf16d762d20c538 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Apr 2018 18:14:24 +0900 Subject: mmc: tmio: move clk_enable() to each driver's probe function I need to differentiate the clock handling for uniphier-sd. Move it to each driver's probe function from the tmio common code so that renesas-sdhi will not be affected. Signed-off-by: Masahiro Yamada --- drivers/mmc/renesas-sdhi.c | 23 +++++++++++++++++++++++ drivers/mmc/tmio-common.c | 22 ---------------------- drivers/mmc/uniphier-sd.c | 25 +++++++++++++++++++++++++ 3 files changed, 48 insertions(+), 22 deletions(-) (limited to 'drivers') diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 56a43ca7d3f..8e49b2f73cc 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -330,8 +330,10 @@ static const struct udevice_id renesas_sdhi_match[] = { static int renesas_sdhi_probe(struct udevice *dev) { + struct tmio_sd_priv *priv = dev_get_priv(dev); u32 quirks = dev_get_driver_data(dev); struct fdt_resource reg_res; + struct clk clk; DECLARE_GLOBAL_DATA_PTR; int ret; @@ -348,6 +350,27 @@ static int renesas_sdhi_probe(struct udevice *dev) quirks |= TMIO_SD_CAP_16BIT; } + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get host clock\n"); + return ret; + } + + /* set to max rate */ + priv->mclk = clk_set_rate(&clk, ULONG_MAX); + if (IS_ERR_VALUE(priv->mclk)) { + dev_err(dev, "failed to set rate for host clock\n"); + clk_free(&clk); + return priv->mclk; + } + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) { + dev_err(dev, "failed to enable host clock\n"); + return ret; + } + ret = tmio_sd_probe(dev, quirks); #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) if (!ret) diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 5f1c9c0bd4d..4ea66121427 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -713,7 +713,6 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) struct tmio_sd_priv *priv = dev_get_priv(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); fdt_addr_t base; - struct clk clk; int ret; base = devfdt_get_addr(dev); @@ -728,27 +727,6 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev); #endif - ret = clk_get_by_index(dev, 0, &clk); - if (ret < 0) { - dev_err(dev, "failed to get host clock\n"); - return ret; - } - - /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { - dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; - } - - ret = clk_enable(&clk); - clk_free(&clk); - if (ret) { - dev_err(dev, "failed to enable host clock\n"); - return ret; - } - ret = mmc_of_parse(dev, &plat->cfg); if (ret < 0) { dev_err(dev, "failed to parse host caps\n"); diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 47379b0328e..bc6e41dbf6d 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -32,6 +32,31 @@ static const struct udevice_id uniphier_sd_match[] = { static int uniphier_sd_probe(struct udevice *dev) { + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get host clock\n"); + return ret; + } + + /* set to max rate */ + priv->mclk = clk_set_rate(&clk, ULONG_MAX); + if (IS_ERR_VALUE(priv->mclk)) { + dev_err(dev, "failed to set rate for host clock\n"); + clk_free(&clk); + return priv->mclk; + } + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) { + dev_err(dev, "failed to enable host clock\n"); + return ret; + } + return tmio_sd_probe(dev, 0); } -- cgit v1.2.3 From fc2d0302b666cd127fca3a8a800f33841de11c41 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Apr 2018 18:14:25 +0900 Subject: mmc: uniphier-sd: skip clock set-up for SPL The size of SPL is hitting the limit (64KB) for uniphier_v7_defconfig. When booting from SD/eMMC, obviously its clock has been properly set up by the boot ROM. Acutually, no need to re-initialize the clock in SPL. Using a clock driver would generalize the SoC specific code, but solving the memory footprint problem would win. Signed-off-by: Masahiro Yamada --- drivers/mmc/uniphier-sd.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index bc6e41dbf6d..61f8da4e413 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -33,6 +33,7 @@ static const struct udevice_id uniphier_sd_match[] = { static int uniphier_sd_probe(struct udevice *dev) { struct tmio_sd_priv *priv = dev_get_priv(dev); +#ifndef CONFIG_SPL_BUILD struct clk clk; int ret; @@ -56,6 +57,9 @@ static int uniphier_sd_probe(struct udevice *dev) dev_err(dev, "failed to enable host clock\n"); return ret; } +#else + priv->mclk = 100000000; +#endif return tmio_sd_probe(dev, 0); } -- cgit v1.2.3 From 045e4fcb44cd040f0ebbdee3cb54d553a7168fd3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Apr 2018 18:14:27 +0900 Subject: clk: uniphier: disable SPL_CLK The last clock consumer in SPL, SD/eMMC driver, gave up using the clock driver. The clock driver is only used in U-Boot proper. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig index 3666d8414ce..a26ca8c1cda 100644 --- a/drivers/clk/uniphier/Kconfig +++ b/drivers/clk/uniphier/Kconfig @@ -2,7 +2,6 @@ config CLK_UNIPHIER def_bool y depends on ARCH_UNIPHIER select CLK - select SPL_CLK if SPL help Support for clock controllers on UniPhier SoCs. Say Y if you want to control clocks provided by System Control -- cgit v1.2.3