From 09bfd962bdc97359b916bfbf18a17e2a85396d65 Mon Sep 17 00:00:00 2001 From: Tony O'Brien Date: Fri, 2 Dec 2016 09:22:34 +1300 Subject: mpc85xx: pcie: Implement workaround for Erratum A007815 The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin Signed-off-by: Tony O'Brien [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun --- drivers/pci/fsl_pci_init.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/pci') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dcd597..af20cf0f3e7 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + /* The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + clrbits_be32(&pci->dbi_ro_wr_en, 0x01); +#endif + /* Use generic setup_device to initialize standard pci regs, * but do not allocate any windows since any BAR found (such * as PCSRBAR) is not in this cpu's memory space. -- cgit v1.2.3