From 393ee7f3429965148dcc0e3ec77cba456e9762f8 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:46 -0500 Subject: net: calxedaxgmac: enable rx cut-thru There is no reason to wait for the entire frame to start DMA on receive, so enable rx cut-thru for better performance. Signed-off-by: Rob Herring --- drivers/net/calxedaxgmac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/net') diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index e3553d68d86..803687a7eff 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -400,7 +400,7 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis) /* set flow control parameters and store and forward mode */ value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) | (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) | - XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF; + XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF; writel(value, ®s->core_opmode); /* enable pause frames */ -- cgit v1.2.3 From 2bf36ac638ab2db9f0295aa47064976eeebf80c1 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:37 +0530 Subject: drivers: net: cpsw: remove hard coding bd ram for cpsw BD ram address may vary in various SOC, so removing the hardcoding and passing the same information through platform data Signed-off-by: Mugunthan V N --- drivers/net/cpsw.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 379b679d2e4..dc0a2be23bc 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -51,8 +51,6 @@ #define CPDMA_RXCP_VER1 0x160 #define CPDMA_RXCP_VER2 0x260 -#define CPDMA_RAM_ADDR 0x4a102000 - /* Descriptor mode bits */ #define CPDMA_DESC_SOP BIT(31) #define CPDMA_DESC_EOP BIT(30) @@ -984,12 +982,12 @@ int cpsw_register(struct cpsw_platform_data *data) return -ENOMEM; } - priv->descs = (void *)CPDMA_RAM_ADDR; priv->host_port = data->host_port_num; priv->regs = regs; priv->host_port_regs = regs + data->host_port_reg_ofs; priv->dma_regs = regs + data->cpdma_reg_ofs; priv->ale_regs = regs + data->ale_reg_ofs; + priv->descs = (void *)regs + data->bd_ram_ofs; int idx = 0; -- cgit v1.2.3 From 454ac635257f78a369015bde7795ddf979d64e12 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:38 +0530 Subject: drivers: net: cpsw: Enable statistics for all port Enable hardware statistics for all ports, enabling only to host port is useless Signed-off-by: Mugunthan V N --- drivers/net/cpsw.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/net') diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index dc0a2be23bc..f1e9f720a77 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -772,6 +772,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis) /* enable statistics collection only on the host port */ __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); + __raw_writel(0x7, &priv->regs->stat_port_en); cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); -- cgit v1.2.3 From f6d1f6e4a58edae4776937647381a43fea5e83a5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 23 Jul 2013 15:32:36 +0200 Subject: net, phy, cpsw: fix gigabit register access accessing a lan9303 switch with the cpsw driver results in wrong speed detection, as the switch sets the BMSR_ERCAP in BMSR register, and follow read of the MII_STAT1000 register fails, as the switch does not support it. Current code did not check, if a phy_read() fails ... fix this. Signed-off-by: Heiko Schocher Cc: Joe Hershberger Acked-by: Mugunthan V N Signed-off-by: Tom Rini --- drivers/net/cpsw.c | 2 +- drivers/net/phy/phy.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/net') diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index f1e9f720a77..9bab71a212d 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -487,7 +487,7 @@ static inline void wait_for_idle(void) static int cpsw_mdio_read(struct mii_dev *bus, int phy_id, int dev_addr, int phy_reg) { - unsigned short data; + int data; u32 reg; if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 6fe793de5da..62925bb2863 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -277,7 +277,7 @@ int genphy_parse_link(struct phy_device *phydev) /* We're using autonegotiation */ if (mii_reg & BMSR_ANEGCAPABLE) { u32 lpa = 0; - u32 gblpa = 0; + int gblpa = 0; u32 estatus = 0; /* Check for gigabit capability */ @@ -286,6 +286,10 @@ int genphy_parse_link(struct phy_device *phydev) * both PHYs in the link */ gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); + if (gblpa < 0) { + debug("Could not read MII_STAT1000. Ignoring gigabit capability\n"); + gblpa = 0; + } gblpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000) << 2; } -- cgit v1.2.3