From 9ca8388059de8f10e035fbdcaa418ec3caeb0599 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 25 May 2017 14:25:55 +0530 Subject: nand: zynq: Add support for 16-bit buswidth This patch adds support for 16-bit buswidth by determining the bus width based on mio configuration. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/mtd/nand/zynq_nand.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c index efd3c9b7987..4d0ea9e6b9d 100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@ -16,6 +16,7 @@ #include #include #include +#include /* The NAND flash driver defines */ #define ZYNQ_NAND_CMD_PHASE 1 @@ -83,6 +84,15 @@ #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ +#define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13 +#define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8 + +enum zynq_nand_bus_width { + NAND_BW_UNKNOWN = -1, + NAND_BW_8BIT, + NAND_BW_16BIT, +}; + #ifndef NAND_CMD_LOCK_TIGHT #define NAND_CMD_LOCK_TIGHT 0x2c #endif @@ -1005,6 +1015,23 @@ static int zynq_nand_device_ready(struct mtd_info *mtd) return 0; } +static int zynq_nand_check_is_16bit_bw_flash(void) +{ + int is_16bit_bw = NAND_BW_UNKNOWN; + int mio_num_8bit = 0, mio_num_16bit = 0; + + mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8"); + if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT) + is_16bit_bw = NAND_BW_8BIT; + + mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16"); + if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT && + mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT) + is_16bit_bw = NAND_BW_16BIT; + + return is_16bit_bw; +} + static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) { struct zynq_nand_info *xnand; @@ -1016,6 +1043,7 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) unsigned long ecc_cfg; int ondie_ecc_enabled = 0; int err = -1; + int is_16bit_bw; xnand = calloc(1, sizeof(struct zynq_nand_info)); if (!xnand) { @@ -1045,6 +1073,16 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) nand_chip->read_buf = zynq_nand_read_buf; nand_chip->write_buf = zynq_nand_write_buf; + is_16bit_bw = zynq_nand_check_is_16bit_bw_flash(); + if (is_16bit_bw == NAND_BW_UNKNOWN) { + printf("%s: Unable detect NAND based on MIO settings\n", + __func__); + goto fail; + } + + if (is_16bit_bw == NAND_BW_16BIT) + nand_chip->options = NAND_BUSWIDTH_16; + nand_chip->bbt_options = NAND_BBT_USE_FLASH; /* Initialize the NAND flash interface on NAND controller */ -- cgit v1.2.3 From 9fdde6c4bbb6840dd175f0c29dfcc791fc0c1d2a Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 25 May 2017 12:15:24 +0530 Subject: nand: zynq: Send address cycles as per onfi parameter page Send address cycles as per value read from onfi parameter page for Read and write commands instead of using a hard coded value. This may vary for different parts and hence use it from onfi parameter page value. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/mtd/nand/zynq_nand.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'drivers/mtd/nand') diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c index 4d0ea9e6b9d..e932a58bf60 100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@ -84,6 +84,9 @@ #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ +#define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F +#define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0 + #define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13 #define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8 @@ -778,6 +781,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, { struct nand_chip *chip = mtd->priv; const struct zynq_nand_command_format *curr_cmd = NULL; + u8 addr_cycles = 0; struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv; void *cmd_addr; unsigned long cmd_data = 0; @@ -828,8 +832,18 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, else end_cmd = curr_cmd->end_cmd; + if (command == NAND_CMD_READ0 || + command == NAND_CMD_SEQIN) { + addr_cycles = chip->onfi_params.addr_cycles & + ZYNQ_NAND_ROW_ADDR_CYCL_MASK; + addr_cycles += ((chip->onfi_params.addr_cycles & + ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4); + } else { + addr_cycles = curr_cmd->addr_cycles; + } + cmd_phase_addr = (unsigned long)xnand->nand_base | - (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT) | + (addr_cycles << ADDR_CYCLES_SHIFT) | (end_cmd_valid << END_CMD_VALID_SHIFT) | (COMMAND_PHASE) | (end_cmd << END_CMD_SHIFT) | -- cgit v1.2.3