From bb3e5aa2896d69a6fe86861004d7d4e33824efbe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 29 Jan 2019 15:54:09 +0000 Subject: sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki --- drivers/clk/sunxi/clk_a10s.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clk/sunxi/clk_a10s.c') diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index aa904ce067..87b74e52dc 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_OTG] = GATE(0x060, BIT(0)), [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), [CLK_AHB_OHCI] = GATE(0x060, BIT(2)), + [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), -- cgit v1.2.3