From 8097cba809d8c40d8fe72f792c7dc0644c845a32 Mon Sep 17 00:00:00 2001 From: Vikas Manocha Date: Thu, 2 Jul 2015 18:29:46 -0700 Subject: spi: cadence_qspi: add device tree binding doc This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the stv0991 device tree. Signed-off-by: Vikas Manocha Reviewed-by: Jagannadh Teki --- doc/device-tree-bindings/spi/spi-cadence.txt | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-cadence.txt (limited to 'doc') diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt new file mode 100644 index 0000000000..c1e2233d7c --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-cadence.txt @@ -0,0 +1,28 @@ +Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size. +- status : enable in requried dts. + +connected flash properties +-------------------------- + +- spi-max-frequency : Max supported spi frequency. +- page-size : Flash page size. +- block-size : Flash memory block size. +- tshsl-ns : Added delay in master reference clocks (ref_clk) for + the length that the master mode chip select outputs + are de-asserted between transactions. +- tsd2d-ns : Delay in master reference clocks (ref_clk) between one + chip select being de-activated and the activation of + another. +- tchsh-ns : Delay in master reference clocks between last bit of + current transaction and de-asserting the device chip + select (n_ss_out). +- tslch-ns : Delay in master reference clocks between setting + n_ss_out low and first bit transfer -- cgit v1.2.3