From 6c7a29a5b49c7541969a1feef4a1affb59194e55 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 25 Mar 2011 14:11:48 -0500 Subject: p4080ds: add README.p4080ds which documents the "serdes" hwconfig option Add documentation for the "serdes" hwconfig option, which is used to specify the status of SerDes banks two and three for the SERDES8 erratum work-around. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- doc/README.p4080ds | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 doc/README.p4080ds (limited to 'doc') diff --git a/doc/README.p4080ds b/doc/README.p4080ds new file mode 100644 index 0000000000..3ed59a8cff --- /dev/null +++ b/doc/README.p4080ds @@ -0,0 +1,32 @@ +Overview +-------- +The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC. + +SerDes hwconfig configuration +----------------------------- +The P4080 RCW includes three sets of bits the specify which SerDes lanes +should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two), +and SRDS_LPD_B3 (for bank three). Each of these contains four bits, one for +each lane in the bank. SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and +SRDS_LPD_B3 be set to 0b1111. This forces banks two and three to be powered +down at reset. + +To re-enable these banks in U-Boot, two hwconfig are available: +"fsl_srds_lpd_b2" and "fsl_srds_lpd_b3". The value passed via fsl_srds_lpd_b2 +is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into +SRDS_LPD_B3. Each bit represents one of each bank, and a value of '1' +indicates that the lane should be powered down. + +For example, to indicate that both SerDes banks 2 and 3 are powered down, add +the following to hwconfig: + + serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf + +The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant +bit corresponds to lane A. To indicate that just lane A of bank 3 is to be +powered down, use: + + serdes:fsl_srds_lpd_b3=8 + +These options should be specified only if U-Boot does not automatically power +on the correct lanes. -- cgit v1.2.3 From b93f81a418d0768d22a8c7cc8e8c5441e5439249 Mon Sep 17 00:00:00 2001 From: Jiang Yutang Date: Fri, 4 Mar 2011 10:25:54 +0800 Subject: powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang Signed-off-by: Kumar Gala --- doc/README.p1022ds | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 doc/README.p1022ds (limited to 'doc') diff --git a/doc/README.p1022ds b/doc/README.p1022ds new file mode 100644 index 0000000000..473ecf6217 --- /dev/null +++ b/doc/README.p1022ds @@ -0,0 +1,24 @@ +Overview +-------- +P1022ds is a Low End Dual core platform supporting the P1022 processor +of QorIQ series. P1022 is an e500 based dual core SOC. + + +Pin Multiplex(hwconfig setting) +------------------------------- +Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex +via hwconfig, i.e: +'setenv hwconfig usb2' to enable USB2 and disable eTsec2 +'setenv hwconfig tdm' to enable TDM and disable Audio +'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz) + and disable TDM +'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio +'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources + is 11MHz), disable eTsec2 and TDM + +Warning: TDM and AUDIO can not enable simultaneous ! +and AUDIO codec clock sources only setting as 11MHz or 12MHz ! +'setenv hwconfig 'audclk:12;tdm' --- error ! +'setenv hwconfig 'audclk:11;tdm' --- error ! +'setenv hwconfig 'audclk:10' --- error ! + -- cgit v1.2.3