From 28d77d968bfe0316deb5bf15c17f57d5ff2c8821 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 30 Jan 2008 14:48:28 +0100 Subject: ppc4xx: Fix problem with init-ram bigger than 4k on 440 platforms Signed-off-by: Stefan Roese --- cpu/ppc4xx/start.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'cpu') diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 77c2aa4117..06380248ca 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -110,6 +110,10 @@ # endif #endif /* CFG_INIT_DCACHE_CS */ +#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10))) +#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! +#endif + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ -- cgit v1.2.3 From ff02f139804f3cb61414f7bbcbfdaa0279e3efae Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 1 Feb 2008 09:38:29 +0100 Subject: ppc4xx: Fix ndfc HW ECC byte order The current ndfc HW ECC implementation swaps the first two ECC bytes. But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering, so this swapping in the HW ECC driver is bogus. This patch fixes this problem and now really uses the SMC ECC byte order. Thanks to Sean MacLennan for pointing this out. Signed-off-by: Stefan Roese --- cpu/ppc4xx/ndfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index ec1b38cffa..9e2229daf9 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -121,8 +121,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, /* The NDFC uses Smart Media (SMC) bytes order */ - ecc_code[0] = p[2]; - ecc_code[1] = p[1]; + ecc_code[0] = p[1]; + ecc_code[1] = p[2]; ecc_code[2] = p[3]; return 0; -- cgit v1.2.3 From 29e3500cbc43c89eff6e720ca83e375deeecd9b3 Mon Sep 17 00:00:00 2001 From: Larry Johnson Date: Tue, 22 Jan 2008 08:51:59 -0500 Subject: ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code Signed-off-by: Larry Johnson --- cpu/ppc4xx/denali_spd_ddr2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 825bc2139c..60f89c97fc 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -3,7 +3,7 @@ * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core * DDR2 controller, specifically the 440EPx/GRx. * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org. * * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... @@ -77,10 +77,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#if defined(CFG_ENABLE_SDRAM_CACHE) +#if defined(CONFIG_4xx_DCACHE) #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -- cgit v1.2.3