From a2c95a72247990dee9a03b26b4dc9fc0182c97ed Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 28 Jul 2006 18:34:58 +0200 Subject: PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance AMCC suggested to set the PMU bit to 0 for best performace on the PPC440 DDR controller. Please see doc/README.440-DDR-performance for details. Patch by Stefan Roese, 28 Jul 2006 --- cpu/ppc4xx/sdram.c | 2 +- cpu/ppc4xx/spd_sdram.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index e31d59d80e..faeea5c91e 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -379,7 +379,7 @@ long int initdram(int board_type) /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */ udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c index c0a6933b84..c24456bea8 100644 --- a/cpu/ppc4xx/spd_sdram.c +++ b/cpu/ppc4xx/spd_sdram.c @@ -1007,9 +1007,9 @@ void program_cfg0(unsigned long* dimm_populated, } /* - * program Page Management Unit + * program Page Management Unit (0 == enabled) */ - cfg0 |= SDRAM_CFG0_PMUD; + cfg0 &= ~SDRAM_CFG0_PMUD; /* * program Memory Controller Options 0 -- cgit v1.2.3