From 2ccceacc04b009d923afb7c26189ba2f8a2a5d46 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 7 Dec 2006 10:34:14 -0600 Subject: Add support for 8641 Rev 2 silicon. Without this patch, I am unable to get to the prompt on rev 2 silicon. Only set ddrioovcr for rev1. Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- cpu/mpc86xx/spd_sdram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index b18e8225def..ac9ff81ce60 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -284,9 +284,9 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, } /* - * Adjust DDR II IO voltage biasing. It just makes it work. + * Adjust DDR II IO voltage biasing. Rev1 only */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { + if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { gur->ddrioovcr = (0 | 0x80000000 /* Enable */ | 0x10000000 /* VSEL to 1.8V */ -- cgit v1.2.3 From 9964a4dd0d4ef5a037febaebf1aa494b1a72991c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 7 Dec 2006 10:35:55 -0600 Subject: Set Rev 2.x 86xx PIC in mixed mode. Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang Signed-off-by: Jon Loeliger --- cpu/mpc86xx/interrupts.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 1df6cdc5b93..49820bbd811 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -80,6 +80,26 @@ int interrupt_init(void) { int ret; + /* + * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to + * implement PEX10 errata. As INT is active high, it + * will cause core to take 0x500 interrupt. + * + * Due to the PIC's default pass through mode, as soon + * as interrupts are enabled (MSR[EE] = 1), an interrupt + * will be taken and u-boot will hang. This is due to a + * hardware change (per an errata fix) on new revisions + * of the board with Rev 2.x parts. + * + * Setting the PIC to mixed mode prevents the hang. + */ + if ((get_svr() & 0xf0) == 0x20) { + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; + } + /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); -- cgit v1.2.3