From 12b43d515c62682fcf7b578f31920a2be49142fe Mon Sep 17 00:00:00 2001 From: wdenk Date: Tue, 5 Apr 2005 21:57:18 +0000 Subject: Add support for MPC8220 based "sorcery" board. --- cpu/mpc8220/Makefile | 5 +- cpu/mpc8220/cpu_init.c | 10 ++-- cpu/mpc8220/dramSetup.c | 20 +++++--- cpu/mpc8220/serial.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++++ cpu/mpc8220/speed.c | 58 ++++++++++----------- cpu/mpc8220/start.S | 1 + cpu/mpc8220/uart.c | 5 +- 7 files changed, 186 insertions(+), 44 deletions(-) create mode 100644 cpu/mpc8220/serial.c (limited to 'cpu') diff --git a/cpu/mpc8220/Makefile b/cpu/mpc8220/Makefile index e64964b340..8b9979daf5 100644 --- a/cpu/mpc8220/Makefile +++ b/cpu/mpc8220/Makefile @@ -27,8 +27,9 @@ LIB = lib$(CPU).a START = start.o ASOBJS = io.o fec_dma_tasks.o -OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o dramSetup.o interrupts.o \ - loadtask.o uart.o speed.o +OBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \ + interrupts.o loadtask.o serial.o speed.o \ + traps.o uart.o all: .depend $(START) $(ASOBJS) $(LIB) diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c index 09b23ee14a..a1e2f659cf 100644 --- a/cpu/mpc8220/cpu_init.c +++ b/cpu/mpc8220/cpu_init.c @@ -55,7 +55,11 @@ void cpu_init_f (void) */ #if defined (CFG_CS0_BASE) flexbus->csar0 = CFG_CS0_BASE; + +/* Sorcery-C can hang-up after CTRL reg initialization */ +#if defined (CFG_CS0_CTRL) flexbus->cscr0 = CFG_CS0_CTRL; +#endif flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1; __asm__ volatile ("sync"); #endif @@ -97,15 +101,15 @@ void cpu_init_f (void) /* This section of the code cannot place in cpu_init_r(), it will cause the system to hang */ /* enable timebase */ - xlbarb->config = 0x00002000; - xlbarb->addrTenTimeOut = 0x1000; xlbarb->dataTenTimeOut = 0x1000; xlbarb->busActTimeOut = 0x2000; + xlbarb->config = 0x00002000; + /* Master Priority Enable */ - xlbarb->mastPriEn = 0x1f; xlbarb->mastPriority = 0; + xlbarb->mastPriEn = 0x1f; } /* diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c index 033b71966c..90a7183106 100644 --- a/cpu/mpc8220/dramSetup.c +++ b/cpu/mpc8220/dramSetup.c @@ -32,9 +32,9 @@ characteristics to initialize the dram on MPC8220 #include "i2cCore.h" #include "dramSetup.h" -#define SPD_SIZE 0x40 -#define DRAM_SPD 0xA2 /* on Board SPD eeprom */ -#define TOTAL_BANK 2 +#define SPD_SIZE CFG_SDRAM_SPD_SIZE +#define DRAM_SPD (CFG_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */ +#define TOTAL_BANK CFG_SDRAM_TOTAL_BANKS int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse) { @@ -144,7 +144,7 @@ int readSpdData (u8 * spdData) break; } - pi2cReg->adr = 0x90; /* I2C device address */ + pi2cReg->adr = CFG_I2C_SLAVE<<1; pi2cReg->cr = I2C_CTL_EN; /* Set Enable */ @@ -569,7 +569,7 @@ u32 dramSetup (void) cfg_value |= CFG1_SWT2RWP ((type == TYPE_DDR) ? 7 : 2); /* Set the Read CAS latency. We're going to use a CL of - * 2 for DDR and SDR. + * 2.5 for DDR and 2 SDR. */ cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2); @@ -685,10 +685,14 @@ u32 dramSetup (void) } - /* Set up mode value for CAS latency == 2 */ + /* Set up mode value for CAS latency */ +#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */ + mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | + MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD); +#else mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) | MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2) | MODE_CMD); - +#endif asm volatile ("sync"); /* Write Extended Mode - enable DLL */ @@ -698,7 +702,7 @@ u32 dramSetup (void) memctl->mode = (temp >> 16); /* mode */ asm volatile ("sync"); - /* Write Mode - reset DLL, set CAS latency == 2 */ + /* Write Mode - reset DLL, set CAS latency */ temp = mode_value | MODE_OPMODE (MODE_OPMODE_RESETDLL); memctl->mode = (temp >> 16); /* mode */ asm volatile ("sync"); diff --git a/cpu/mpc8220/serial.c b/cpu/mpc8220/serial.c new file mode 100644 index 0000000000..08285b87b9 --- /dev/null +++ b/cpu/mpc8220/serial.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include +#include + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if defined (CONFIG_EXTUART_CONSOLE) + volatile uchar *cpld = (volatile uchar *) CFG_CPLD_BASE; +#endif + + /* Check CPLD Switch 2 whether is external or internal */ +#if defined (CONFIG_EXTUART_CONSOLE) + if ((*cpld & 0x02) == 0x02) { + gd->bExtUart = 1; + return ext_serial_init (); + } else +#endif + { +#if defined(CONFIG_PSC_CONSOLE) + gd->bExtUart = 0; + return psc_serial_init (); +#endif + } + + return (0); +} + +void serial_putc (const char c) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + ext_serial_putc (c); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + psc_serial_putc (c); +#endif + } +} + +void serial_puts (const char *s) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + ext_serial_puts (s); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + psc_serial_puts (s); +#endif + } +} + +int serial_getc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + return ext_serial_getc (); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + return psc_serial_getc (); +#endif + } +} + +int serial_tstc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + return ext_serial_tstc (); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + return psc_serial_tstc (); +#endif + } +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + ext_serial_setbrg (); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + psc_serial_setbrg (); +#endif + } +} diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c index bd79911800..0c3df7c99a 100644 --- a/cpu/mpc8220/speed.c +++ b/cpu/mpc8220/speed.c @@ -42,30 +42,30 @@ int get_clocks (void) DECLARE_GLOBAL_DATA_PTR; pllcfg_t bus2core[] = { - {0x10, 2, 8}, /* 1 */ - {0x08, 2, 4}, - {0x60, 3, 8}, /* 1.5 */ + {0x02, 2, 8}, /* 1 */ + {0x01, 2, 4}, + {0x0C, 3, 8}, /* 1.5 */ {0x00, 3, 4}, - {0xc0, 3, 2}, - {0x28, 4, 4}, /* 2 */ - {0x20, 4, 2}, - {0x88, 5, 4}, /* 2.5 */ - {0x30, 5, 2}, - {0x80, 6, 4}, /* 3 */ - {0x40, 6, 2}, - {0x70, 7, 2}, /* 3.5 */ - {0x50, 8, 2}, /* 4 */ - {0x38, 9, 2}, /* 4.5 */ - {0x58, 10, 2}, /* 5 */ - {0x48, 11, 2}, /* 5.5 */ - {0x68, 12, 2}, /* 6 */ - {0x90, 13, 2}, /* 6.5 */ - {0xa0, 14, 2}, /* 7 */ - {0xb0, 15, 2}, /* 7.5 */ - {0xe0, 16, 2} /* 8 */ + {0x18, 3, 2}, + {0x05, 4, 4}, /* 2 */ + {0x04, 4, 2}, + {0x11, 5, 4}, /* 2.5 */ + {0x06, 5, 2}, + {0x10, 6, 4}, /* 3 */ + {0x08, 6, 2}, + {0x0E, 7, 2}, /* 3.5 */ + {0x0A, 8, 2}, /* 4 */ + {0x07, 9, 2}, /* 4.5 */ + {0x0B, 10, 2}, /* 5 */ + {0x09, 11, 2}, /* 5.5 */ + {0x0D, 12, 2}, /* 6 */ + {0x12, 13, 2}, /* 6.5 */ + {0x14, 14, 2}, /* 7 */ + {0x16, 15, 2}, /* 7.5 */ + {0x1C, 16, 2} /* 8 */ }; u32 hid1; - int i, size; + int i, size, pci2bus; #if !defined(CFG_MPC8220_CLKIN) #error clock measuring not implemented yet - define CFG_MPC8220_CLKIN @@ -73,9 +73,12 @@ int get_clocks (void) gd->inp_clk = CFG_MPC8220_CLKIN; - /* Bus clock is fixed at 120Mhz for now */ - /* will do dynamic in the future */ - gd->bus_clk = CFG_MPC8220_CLKIN * 4; + /* Read XLB to PCI(INP) clock multiplier */ + pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & + PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT; + + /* XLB bus clock */ + gd->bus_clk = CFG_MPC8220_CLKIN * pci2bus; /* PCI clock is same as input clock */ gd->pci_clk = CFG_MPC8220_CLKIN; @@ -88,14 +91,13 @@ int get_clocks (void) asm volatile ("mfspr %0, 1009":"=r" (hid1):); size = sizeof (bus2core) / sizeof (pllcfg_t); - hid1 >>= 24; + + hid1 >>= 27; for (i = 0; i < size; i++) if (hid1 == bus2core[i].hid1) { gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1; - /* Input Multiplier is determined by MPLL, - hardcoded for now at 16 */ - gd->vco_clk = gd->pci_clk * 16; + gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2; break; } diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index 6072374a61..c5d2388cad 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -111,6 +111,7 @@ boot_warm: /* MBAR is mirrored into the MBAR SPR */ mtspr MBAR,r3 + mtspr SPRN_SPRG7W,r3 lis r4, CFG_DEFAULT_MBAR@h stw r3, 0(r4) #endif /* CFG_DEFAULT_MBAR */ diff --git a/cpu/mpc8220/uart.c b/cpu/mpc8220/uart.c index fcf947dc4a..4ff8ccbf3f 100644 --- a/cpu/mpc8220/uart.c +++ b/cpu/mpc8220/uart.c @@ -47,8 +47,7 @@ int psc_serial_init (void) /* write to CSR: RX/TX baud rate from timers */ psc->sr_csr = 0xdd000000; - psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR1_RX_RTS; - psc->mr1_2 = PSC_MR2_STOP_BITS_1 | PSC_MR2_TX_CTS; + psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; /* Setting up BaudRate */ counter = ((gd->bus_clk / gd->baudrate)) >> 5; @@ -77,7 +76,7 @@ void psc_serial_putc (const char c) serial_putc ('\r'); /* Wait for last character to go. */ - while (!(psc->sr_csr & PSC_SR_TXEMT)); + while (!(psc->sr_csr & PSC_SR_TXRDY)); psc->xmitbuf[0] = c; } -- cgit v1.2.3