From fb05f6da35ea1c15c553abe6f23f656bf18dc5db Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 7 May 2007 23:58:31 +0200 Subject: new: USE_MSR_INTR support --- cpu/microblaze/cache.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) mode change 100644 => 100755 cpu/microblaze/cache.c (limited to 'cpu/microblaze/cache.c') diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c old mode 100644 new mode 100755 index 683044caea..4f36a84ec4 --- a/cpu/microblaze/cache.c +++ b/cpu/microblaze/cache.c @@ -23,6 +23,7 @@ */ #include +#include #if (CONFIG_COMMANDS & CFG_CMD_CACHE) @@ -47,18 +48,18 @@ int icache_status (void) } void icache_enable (void) { - __asm__ __volatile__ ("msrset r0, 0x80"); + MSRSET(0x20); } void icache_disable(void) { - __asm__ __volatile__ ("msrclr r0, 0x80"); + MSRCLR(0x20); } void dcache_enable (void) { - __asm__ __volatile__ ("msrset r0, 0x20"); + MSRSET(0x80); } void dcache_disable(void) { - __asm__ __volatile__ ("msrclr r0, 0x20"); + MSRCLR(0x80); } #endif -- cgit v1.2.3