From 8df54067b614e6debb4a4c4a89dd108c70b42e71 Mon Sep 17 00:00:00 2001
From: Terry Lv <r65388@freescale.com>
Date: Thu, 18 Mar 2010 18:43:28 +0800
Subject: ENGR00121731: Add mmu, l1cache, l2cache support for mx53

Add mmu, l1cache, l2cache support for mx53.

Signed-off-by: Terry Lv <r65388@freescale.com>
---
 cpu/arm_cortexa8/mx51/generic.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'cpu/arm_cortexa8/mx51')

diff --git a/cpu/arm_cortexa8/mx51/generic.c b/cpu/arm_cortexa8/mx51/generic.c
index 0762c03b24..eb1a0230bf 100644
--- a/cpu/arm_cortexa8/mx51/generic.c
+++ b/cpu/arm_cortexa8/mx51/generic.c
@@ -26,7 +26,9 @@
 #include <common.h>
 #include <asm/arch/mx51.h>
 #include <asm/errno.h>
+#ifdef CONFIG_ARCH_CPU_INIT
 #include <asm/cache-cp15.h>
+#endif
 #include "crm_regs.h"
 
 enum pll_clocks {
-- 
cgit v1.2.3