From f12e4549b6fb01cd2654348af95a3c7a6ac161e7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 13 Sep 2008 02:23:05 +0200 Subject: Coding style cleanup, update CHANGELOG Signed-off-by: Wolfgang Denk --- board/a3000/a3000.c | 1 - board/amirix/ap1000/ap1000.c | 1 - board/ap325rxa/u-boot.lds | 1 - board/mucmc52/mucmc52.c | 68 +++++++++++++++++----------------- board/purple/purple.c | 1 - board/samsung/smdk6400/lowlevel_init.S | 32 ++++++++-------- board/sh7785lcr/config.mk | 1 - board/sh7785lcr/lowlevel_init.S | 1 - board/sh7785lcr/rtl8169.h | 1 - board/sh7785lcr/rtl8169_mac.c | 1 - board/sh7785lcr/selfcheck.c | 1 - board/sh7785lcr/u-boot.lds | 1 - board/sl8245/sl8245.c | 1 - board/stxssa/stxssa.c | 1 - 14 files changed, 50 insertions(+), 62 deletions(-) (limited to 'board') diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c index 040ba89765..1ba21edf72 100644 --- a/board/a3000/a3000.c +++ b/board/a3000/a3000.c @@ -115,4 +115,3 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } - diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index 8f30ed966b..e9f80ff5ce 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -703,4 +703,3 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } - diff --git a/board/ap325rxa/u-boot.lds b/board/ap325rxa/u-boot.lds index 015f58b45e..e9f8dc0def 100644 --- a/board/ap325rxa/u-boot.lds +++ b/board/ap325rxa/u-boot.lds @@ -103,4 +103,3 @@ SECTIONS PROVIDE (_end = .); } - diff --git a/board/mucmc52/mucmc52.c b/board/mucmc52/mucmc52.c index ae3ca24221..74417c44f9 100644 --- a/board/mucmc52/mucmc52.c +++ b/board/mucmc52/mucmc52.c @@ -192,22 +192,22 @@ phys_size_t initdram (int board_type) #endif /* CFG_RAMBOOT */ /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04); - __asm__ volatile ("sync"); - } + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04); + __asm__ volatile ("sync"); + } return dramsize + dramsize2; } @@ -339,14 +339,14 @@ int misc_init_r (void) free (str); #endif /* CONFIG_PREBOOT */ - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' '); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' '); return 0; } @@ -365,16 +365,16 @@ int board_early_init_r (void) int last_stage_init (void) { - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2'); - - return 0; + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M'); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U'); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C'); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.'); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M'); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C'); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5'); + out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2'); + + return 0; } #if defined(CONFIG_HW_WATCHDOG) diff --git a/board/purple/purple.c b/board/purple/purple.c index c129d7a109..900e66f72f 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -282,4 +282,3 @@ int board_eth_init(bd_t *bis) return plb2800_eth_initialize(bis); } #endif - diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 034c810f7b..e0119a771c 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -2,7 +2,7 @@ * Memory Setup stuff - taken from blob memsetup.S * * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * * Modified for the Samsung SMDK2410 by * (C) Copyright 2002 @@ -73,8 +73,8 @@ lowlevel_init: ldr r1, [r0] str r1, [r0] - ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 - ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 + ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 + ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 /* Disable all interrupts (VIC0 and VIC1) */ mvn r3, #0x0 @@ -107,11 +107,11 @@ lowlevel_init: bl mem_ctrl_asm_init /* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset + ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) + ldr r1, [r0] + bic r1, r1, #0xfffffff7 + cmp r1, #0x8 + beq wakeup_reset 1: mov lr, r12 @@ -124,10 +124,10 @@ wakeup_reset: ldr r1, [r0] str r1, [r0] - /* LED test */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x3000 - str r1, [r0, #GPNDAT_OFFSET] + /* LED test */ + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x3000 + str r1, [r0, #GPNDAT_OFFSET] /* Load return address and jump to kernel */ ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) @@ -201,7 +201,7 @@ wait_for_async: str r1, [r0, #MPLL_LOCK_OFFSET] /* Set Clock Divider */ - ldr r1, [r0, #CLK_DIV0_OFFSET] + ldr r1, [r0, #CLK_DIV0_OFFSET] bic r1, r1, #0x30000 bic r1, r1, #0xff00 bic r1, r1, #0xff @@ -252,7 +252,7 @@ uart_asm_init: /* set GPIO to enable UART */ ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x220022 - str r1, [r0, #GPACON_OFFSET] + str r1, [r0, #GPACON_OFFSET] mov pc, lr #endif @@ -265,11 +265,11 @@ nand_asm_init: ldr r1, [r0, #NFCONF_OFFSET] orr r1, r1, #0x70 orr r1, r1, #0x7700 - str r1, [r0, #NFCONF_OFFSET] + str r1, [r0, #NFCONF_OFFSET] ldr r1, [r0, #NFCONT_OFFSET] orr r1, r1, #0x07 - str r1, [r0, #NFCONT_OFFSET] + str r1, [r0, #NFCONT_OFFSET] mov pc, lr #endif diff --git a/board/sh7785lcr/config.mk b/board/sh7785lcr/config.mk index 93761eec87..20807dfc52 100644 --- a/board/sh7785lcr/config.mk +++ b/board/sh7785lcr/config.mk @@ -23,4 +23,3 @@ # NOTE: Must match value used in u-boot.lds (in this directory). # TEXT_BASE = 0x0ff80000 - diff --git a/board/sh7785lcr/lowlevel_init.S b/board/sh7785lcr/lowlevel_init.S index 8126296e5b..50e1789cc5 100644 --- a/board/sh7785lcr/lowlevel_init.S +++ b/board/sh7785lcr/lowlevel_init.S @@ -315,4 +315,3 @@ CS_I2C_WCR_D: .long 0x00000003 CCR_A: .long 0xff00001c CCR_D: .long 0x0000090b - diff --git a/board/sh7785lcr/rtl8169.h b/board/sh7785lcr/rtl8169.h index d1c0d64b1d..ca9c0bd94c 100644 --- a/board/sh7785lcr/rtl8169.h +++ b/board/sh7785lcr/rtl8169.h @@ -55,4 +55,3 @@ const unsigned short EEPROM_W_Data_8169_B[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; - diff --git a/board/sh7785lcr/rtl8169_mac.c b/board/sh7785lcr/rtl8169_mac.c index 2bc873bd16..bf0ba145d2 100644 --- a/board/sh7785lcr/rtl8169_mac.c +++ b/board/sh7785lcr/rtl8169_mac.c @@ -346,4 +346,3 @@ U_BOOT_CMD( "\n" " - print MAC address for RTL8110\n" ); - diff --git a/board/sh7785lcr/selfcheck.c b/board/sh7785lcr/selfcheck.c index 9c228e5f6d..d924595b76 100644 --- a/board/sh7785lcr/selfcheck.c +++ b/board/sh7785lcr/selfcheck.c @@ -170,4 +170,3 @@ U_BOOT_CMD( "hwtest sata - check SiI3512 ID\n" "hwtest pci - output PCI slot device ID\n" ); - diff --git a/board/sh7785lcr/u-boot.lds b/board/sh7785lcr/u-boot.lds index 8dcc6c7b1b..231769f3b3 100644 --- a/board/sh7785lcr/u-boot.lds +++ b/board/sh7785lcr/u-boot.lds @@ -94,4 +94,3 @@ SECTIONS PROVIDE (_end = .); } - diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c index e66272ecb9..25adc2832d 100644 --- a/board/sl8245/sl8245.c +++ b/board/sl8245/sl8245.c @@ -77,4 +77,3 @@ int board_eth_init(bd_t *bis) #endif return rc; } - diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 71e9b088ac..4d4dc06e34 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -407,4 +407,3 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); /* Initialize TSECs first */ return pci_eth_init(bis); } - -- cgit v1.2.3