From 285c74811ec34c79b177e5d79936ffe0980a99a4 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Thu, 1 Sep 2016 12:56:43 -0400 Subject: board: ls1043ardb: move sec_init to board_init sec_init() which was earlier called in misc_init_r() is now done in board_init() before PPA init as SEC block will be used during PPA image validation. Signed-off-by: Aneesh Bansal Signed-off-by: Sumit Garg Reviewed-by: York Sun --- board/freescale/ls1043ardb/ls1043ardb.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) (limited to 'board') diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index d3e37b4996..70fef79cd0 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -94,6 +94,23 @@ int board_init(void) enable_layerscape_ns_access(); #endif +#ifdef CONFIG_SECURE_BOOT + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -137,21 +154,6 @@ int config_board_mux(void) int misc_init_r(void) { config_board_mux(); -#ifdef CONFIG_SECURE_BOOT - /* In case of Secure Boot, the IBR configures the SMMU - * to allow only Secure transactions. - * SMMU must be reset in bypass mode. - * Set the ClientPD bit and Clear the USFCFG Bit - */ - u32 val; - val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_SCR0, val); - val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_NSCR0, val); -#endif -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif return 0; } #endif -- cgit v1.2.3 From 341238fd135dc61cd387546c77901a3eac478a36 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 2 Aug 2016 19:03:23 +0800 Subject: arm: fsl-layerscape: move forward the non-secure access permission setup Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/ls1012afrdm/ls1012afrdm.c | 5 ----- board/freescale/ls1012aqds/ls1012aqds.c | 5 ----- board/freescale/ls1012ardb/ls1012ardb.c | 5 ----- board/freescale/ls1021aqds/ls1021aqds.c | 4 ---- board/freescale/ls1021atwr/ls1021atwr.c | 4 ---- board/freescale/ls1043aqds/ls1043aqds.c | 4 ---- board/freescale/ls1043ardb/ls1043ardb.c | 5 ----- 7 files changed, 32 deletions(-) (limited to 'board') diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index a94a458f53..5a2b1f48fe 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -175,10 +174,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - return 0; } diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 71eea82a03..852d683dd8 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -207,10 +206,6 @@ int board_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index f69768d24e..a3748defb6 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -207,10 +206,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - return 0; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index dbea0bff26..291b0f4c72 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -446,10 +446,6 @@ int board_init(void) ls102xa_smmu_stream_id_init(); -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 77482a947b..85c036b36c 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -489,10 +489,6 @@ int board_init(void) ls102xa_smmu_stream_id_init(); -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 941dfbc447..16425575b2 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -316,9 +315,6 @@ int board_init(void) config_serdes_mux(); #endif -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif return 0; } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 70fef79cd0..33997899ff 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -90,10 +89,6 @@ int board_init(void) init_final_memctl_regs(); #endif -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - #ifdef CONFIG_SECURE_BOOT /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. -- cgit v1.2.3 From c37fdbdbb0dd65cb4aa147c9cf9352901014be3b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 2 Aug 2016 19:03:24 +0800 Subject: fsl: csu: add an API to set individual device access permission Add this API to make the individual device is able to be set to the specified permission. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/common/ns_access.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) (limited to 'board') diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index d8d16c520f..c3d7a5e907 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -9,25 +9,31 @@ #include #include -static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; u32 *reg; - uint32_t val; - int i; + uint32_t tmp; - for (i = 0; i < num; i++) { - reg = base + ns_dev[i].ind / 2; - val = in_be32(reg); - if (ns_dev[i].ind % 2 == 0) { - val &= 0x0000ffff; - val |= ns_dev[i].val << 16; - } else { - val &= 0xffff0000; - val |= ns_dev[i].val; - } - out_be32(reg, val); + reg = base + ns_dev->ind / 2; + tmp = in_be32(reg); + if (ns_dev->ind % 2 == 0) { + tmp &= 0x0000ffff; + tmp |= val << 16; + } else { + tmp &= 0xffff0000; + tmp |= val; } + + out_be32(reg, tmp); +} + +static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + int i; + + for (i = 0; i < num; i++) + set_devices_ns_access(ns_dev + i, ns_dev[i].val); } void enable_layerscape_ns_access(void) -- cgit v1.2.3 From 664b6520582fcea7e150f57258c7a63627837318 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 2 Aug 2016 19:03:26 +0800 Subject: fsl: csu: add an API to set R/W permission to PCIe Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/common/ns_access.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'board') diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index c3d7a5e907..81c921122e 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -8,6 +8,7 @@ #include #include #include +#include void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { @@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void) { enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); } + +void set_pcie_ns_access(int pcie, u16 val) +{ + switch (pcie) { +#ifdef CONFIG_PCIE1 + case PCIE1: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); + return; +#endif +#ifdef CONFIG_PCIE2 + case PCIE2: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); + return; +#endif +#ifdef CONFIG_PCIE3 + case PCIE3: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); + return; +#endif + default: + debug("The PCIE%d doesn't exist!\n", pcie); + return; + } +} -- cgit v1.2.3 From b392a6d4b05b7409283cd75b4ac6bd12018d187a Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 2 Aug 2016 19:03:27 +0800 Subject: fsl-layerscape: Add workaround for PCIe erratum A010315 As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/ls1012aqds/ls1012aqds.c | 4 ++++ board/freescale/ls1012ardb/ls1012ardb.c | 4 ++++ board/freescale/ls1021aqds/ls1021aqds.c | 4 ++++ board/freescale/ls1021atwr/ls1021atwr.c | 4 ++++ board/freescale/ls1043aqds/ls1043aqds.c | 4 ++++ board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ 6 files changed, 24 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 852d683dd8..874c122725 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -206,6 +206,10 @@ int board_init(void) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index a3748defb6..6598ab37ee 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -202,6 +202,10 @@ int board_init(void) */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 291b0f4c72..4eb38a73c9 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -430,6 +430,10 @@ int board_init(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 85c036b36c..4638bed478 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -480,6 +480,10 @@ void ls1twr_program_regulator(void) int board_init(void) { +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 16425575b2..8835a49bb5 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -308,6 +308,10 @@ int misc_init_r(void) int board_init(void) { +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init(); diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 33997899ff..e213128c1b 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -85,6 +85,10 @@ int board_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + #ifdef CONFIG_FSL_IFC init_final_memctl_regs(); #endif -- cgit v1.2.3 From b63a9506296b10b9730c3ff4a0e9611f6f98e7db Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 3 Aug 2016 12:33:00 -0700 Subject: armv8: ls2080a: Remove debug server support Debug server feature has been dropped from roadmap. Signed-off-by: York Sun --- board/freescale/ls2080a/ls2080a.c | 5 ----- board/freescale/ls2080aqds/ls2080aqds.c | 4 ---- board/freescale/ls2080ardb/ls2080ardb.c | 4 ---- 3 files changed, 13 deletions(-) (limited to 'board') diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 00337d7091..d0a88d4ef9 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -60,10 +59,6 @@ int dram_init(void) #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { -#ifdef CONFIG_FSL_DEBUG_SERVER - debug_server_init(); -#endif - return 0; } #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 7d95debcaa..ca4a2e5cb7 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -265,9 +264,6 @@ int dram_init(void) #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { -#ifdef CONFIG_FSL_DEBUG_SERVER - debug_server_init(); -#endif #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index a65cd4ab80..7d8a7115dc 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -229,9 +228,6 @@ int dram_init(void) #if defined(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { -#ifdef CONFIG_FSL_DEBUG_SERVER - debug_server_init(); -#endif #ifdef CONFIG_FSL_CAAM sec_init(); #endif -- cgit v1.2.3 From 214ffae02d03cd548549c6390eb9c19b9e6b085f Mon Sep 17 00:00:00 2001 From: Hongbo Zhang Date: Fri, 19 Aug 2016 17:20:33 +0800 Subject: nxp: ls102xa: add LS1 PSCI system suspend The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang Reviewed-by: York Sun --- board/freescale/common/arm_sleep.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 71ed15e6a6..16fd445306 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -66,6 +66,36 @@ static void dp_ddr_restore(void) *dst++ = *src++; } +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +void ls1_psci_resume_fixup(void) +{ + u32 tmp; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef QIXIS_BASE + void *qixis_base = (void *)QIXIS_BASE; + + /* Pull on PCIe RST# */ + out_8(qixis_base + QIXIS_RST_FORCE_3, 0); + + /* disable deep sleep signals in FPGA */ + tmp = in_8(qixis_base + QIXIS_PWR_CTL2); + tmp &= ~QIXIS_PWR_CTL2_PCTL; + out_8(qixis_base + QIXIS_PWR_CTL2, tmp); +#endif + + /* Disable wakeup interrupt during deep sleep */ + out_be32(&scfg->pmcintecr, 0); + /* Clear PMC interrupt status */ + out_be32(&scfg->pmcintsr, 0xffffffff); + + /* Disable Warm Device Reset */ + tmp = in_be32(&scfg->dpslpcr); + tmp &= ~SCFG_DPSLPCR_WDRR_EN; + out_be32(&scfg->dpslpcr, tmp); +} +#endif + static void dp_resume_prepare(void) { dp_ddr_restore(); @@ -74,6 +104,9 @@ static void dp_resume_prepare(void) #ifdef CONFIG_U_QE u_qe_resume(); #endif +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) + ls1_psci_resume_fixup(); +#endif } int fsl_dp_resume(void) @@ -88,7 +121,7 @@ int fsl_dp_resume(void) dp_resume_prepare(); /* Get the entry address and jump to kernel */ - start_addr = in_le32(&scfg->sparecr[1]); + start_addr = in_le32(&scfg->sparecr[3]); debug("Entry address is 0x%08x\n", start_addr); kernel_resume = (void (*)(void))start_addr; secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); -- cgit v1.2.3 From 93a6d3284ca635496c6de097e49cadc8f62e6256 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 1 Sep 2016 14:50:36 +0800 Subject: armv7:ls1021a: Enable workaround for DDR erratum A-009942 Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/ls1021atwr/ls1021atwr.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 4638bed478..d96fd774d3 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -142,7 +142,7 @@ int checkboard(void) void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; - u32 temp_sdram_cfg; + u32 temp_sdram_cfg, tmp; out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); @@ -189,6 +189,11 @@ void ddrmc_init(void) out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + udelay(1); #ifdef CONFIG_DEEP_SLEEP -- cgit v1.2.3 From b9e745bbe2562fda710d668dc9cef46e0b23049f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 26 Aug 2016 18:30:39 +0800 Subject: driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/ls1012afrdm/ls1012afrdm.c | 116 ------------------------------ board/freescale/ls1012aqds/ls1012aqds.c | 116 ------------------------------ board/freescale/ls1012ardb/ls1012ardb.c | 116 ------------------------------ 3 files changed, 348 deletions(-) (limited to 'board') diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 5a2b1f48fe..d644e9423b 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -17,20 +17,6 @@ DECLARE_GLOBAL_DATA_PTR; -static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) -{ - int timeout = 1000; - - out_be32(ptr, value); - - while (in_be32(ptr) & bits) { - udelay(100); - timeout--; - } - if (timeout <= 0) - puts("Error: wait for clear timeout.\n"); -} - int checkboard(void) { puts("Board: LS1012AFRDM "); @@ -38,108 +24,6 @@ int checkboard(void) return 0; } -void mmdc_init(void) -{ - struct mmdc_p_regs *mmdc = - (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; - - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - /* configure timing parms */ - out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); - out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); - out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); - out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); - - /* other parms */ - out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); - out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); - out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); - out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); - - /* out of reset delays */ - out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); - - /* physical parms */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); - out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); - - /* Enable MMDC */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); - - /* dram init sequence: update MRs */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | - CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); - - /* dram init sequence: ZQCL */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); - set_wait_for_bits_clear(&mmdc->mpzqhwctrl, - CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, - FORCE_ZQ_AUTO_CALIBRATION); - - /* Calibrations now: wr lvl */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | - CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); - set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); - - mdelay(1); - - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - mdelay(1); - - /* Calibrations now: Read DQS gating calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); - set_wait_for_bits_clear(&mmdc->mpdgctrl0, - AUTO_RD_DQS_GATING_CALIBRATION_EN, - AUTO_RD_DQS_GATING_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* Calibrations now: Read calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - set_wait_for_bits_clear(&mmdc->mprddlhwctl, - AUTO_RD_CALIBRATION_EN, - AUTO_RD_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* PD, SR */ - out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); - out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); - - /* refresh scheme */ - set_wait_for_bits_clear(&mmdc->mdref, - CONFIG_SYS_MMDC_CORE_REFRESH_CTL, - START_REFRESH); - - /* disable CON_REQ */ - out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); -} - int dram_init(void) { mmdc_init(); diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 874c122725..188b6bc979 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -27,20 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) -{ - int timeout = 1000; - - out_be32(ptr, value); - - while (in_be32(ptr) & bits) { - udelay(100); - timeout--; - } - if (timeout <= 0) - puts("Error: wait for clear timeout.\n"); -} - int checkboard(void) { char buf[64]; @@ -66,108 +52,6 @@ int checkboard(void) return 0; } -void mmdc_init(void) -{ - struct mmdc_p_regs *mmdc = - (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; - - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - /* configure timing parms */ - out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); - out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); - out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); - out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); - - /* other parms */ - out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); - out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); - out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); - out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); - - /* out of reset delays */ - out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); - - /* physical parms */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); - out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); - - /* Enable MMDC */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); - - /* dram init sequence: update MRs */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | - CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); - - /* dram init sequence: ZQCL */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); - set_wait_for_bits_clear(&mmdc->mpzqhwctrl, - CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, - FORCE_ZQ_AUTO_CALIBRATION); - - /* Calibrations now: wr lvl */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | - CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); - set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); - - mdelay(1); - - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - mdelay(1); - - /* Calibrations now: Read DQS gating calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); - set_wait_for_bits_clear(&mmdc->mpdgctrl0, - AUTO_RD_DQS_GATING_CALIBRATION_EN, - AUTO_RD_DQS_GATING_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* Calibrations now: Read calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - set_wait_for_bits_clear(&mmdc->mprddlhwctl, - AUTO_RD_CALIBRATION_EN, - AUTO_RD_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* PD, SR */ - out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); - out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); - - /* refresh scheme */ - set_wait_for_bits_clear(&mmdc->mdref, - CONFIG_SYS_MMDC_CORE_REFRESH_CTL, - START_REFRESH); - - /* disable CON_REQ */ - out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); -} - int dram_init(void) { mmdc_init(); diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 6598ab37ee..50f91876ca 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -21,20 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; -static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) -{ - int timeout = 1000; - - out_be32(ptr, value); - - while (in_be32(ptr) & bits) { - udelay(100); - timeout--; - } - if (timeout <= 0) - puts("Error: wait for clear timeout.\n"); -} - int checkboard(void) { u8 in1; @@ -70,108 +56,6 @@ int checkboard(void) return 0; } -void mmdc_init(void) -{ - struct mmdc_p_regs *mmdc = - (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; - - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - /* configure timing parms */ - out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); - out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); - out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); - out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); - - /* other parms */ - out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); - out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); - out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); - out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); - - /* out of reset delays */ - out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); - - /* physical parms */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); - out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); - - /* Enable MMDC */ - out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); - - /* dram init sequence: update MRs */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | - CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); - - /* dram init sequence: ZQCL */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); - set_wait_for_bits_clear(&mmdc->mpzqhwctrl, - CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, - FORCE_ZQ_AUTO_CALIBRATION); - - /* Calibrations now: wr lvl */ - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | - CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); - set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); - - mdelay(1); - - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); - out_be32(&mmdc->mdscr, CONFIGURATION_REQ); - - mdelay(1); - - /* Calibrations now: Read DQS gating calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); - set_wait_for_bits_clear(&mmdc->mpdgctrl0, - AUTO_RD_DQS_GATING_CALIBRATION_EN, - AUTO_RD_DQS_GATING_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* Calibrations now: Read calibration */ - out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | - CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); - out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | - CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); - out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); - set_wait_for_bits_clear(&mmdc->mprddlhwctl, - AUTO_RD_CALIBRATION_EN, - AUTO_RD_CALIBRATION_EN); - - out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | - CMD_BANK_ADDR_3)); - - /* PD, SR */ - out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); - out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); - - /* refresh scheme */ - set_wait_for_bits_clear(&mmdc->mdref, - CONFIG_SYS_MMDC_CORE_REFRESH_CTL, - START_REFRESH); - - /* disable CON_REQ */ - out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); -} - int dram_init(void) { mmdc_init(); -- cgit v1.2.3 From dd02936f81de477680f27af244fd2085ce460152 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 7 Sep 2016 18:47:28 +0800 Subject: armv8: ls1046ardb: Add LS1046ARDB board support LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu Signed-off-by: Shaohui Xie Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- board/freescale/ls1046ardb/Kconfig | 16 +++ board/freescale/ls1046ardb/MAINTAINERS | 9 ++ board/freescale/ls1046ardb/Makefile | 10 ++ board/freescale/ls1046ardb/README | 76 ++++++++++ board/freescale/ls1046ardb/cpld.c | 158 +++++++++++++++++++++ board/freescale/ls1046ardb/cpld.h | 49 +++++++ board/freescale/ls1046ardb/ddr.c | 140 ++++++++++++++++++ board/freescale/ls1046ardb/ddr.h | 44 ++++++ board/freescale/ls1046ardb/eth.c | 77 ++++++++++ board/freescale/ls1046ardb/ls1046ardb.c | 136 ++++++++++++++++++ board/freescale/ls1046ardb/ls1046ardb_pbi.cfg | 22 +++ board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg | 7 + board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg | 7 + 13 files changed, 751 insertions(+) create mode 100644 board/freescale/ls1046ardb/Kconfig create mode 100644 board/freescale/ls1046ardb/MAINTAINERS create mode 100644 board/freescale/ls1046ardb/Makefile create mode 100644 board/freescale/ls1046ardb/README create mode 100644 board/freescale/ls1046ardb/cpld.c create mode 100644 board/freescale/ls1046ardb/cpld.h create mode 100644 board/freescale/ls1046ardb/ddr.c create mode 100644 board/freescale/ls1046ardb/ddr.h create mode 100644 board/freescale/ls1046ardb/eth.c create mode 100644 board/freescale/ls1046ardb/ls1046ardb.c create mode 100644 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg create mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg (limited to 'board') diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig new file mode 100644 index 0000000000..a62255c78d --- /dev/null +++ b/board/freescale/ls1046ardb/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS1046ARDB + +config SYS_BOARD + default "ls1046ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046ardb" + +endif diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS new file mode 100644 index 0000000000..ff42bef090 --- /dev/null +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -0,0 +1,9 @@ +LS1046A BOARD +M: Mingkai Hu +S: Maintained +F: board/freescale/ls1046ardb/ +F: board/freescale/ls1046ardb/ls1046ardb.c +F: include/configs/ls1046ardb.h +F: configs/ls1046ardb_qspi_defconfig +F: configs/ls1046ardb_sdcard_defconfig +F: configs/ls1046ardb_emmc_defconfig diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile new file mode 100644 index 0000000000..348eb76ea7 --- /dev/null +++ b/board/freescale/ls1046ardb/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2016 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpld.o +obj-y += ddr.o +obj-y += ls1046ardb.o +obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README new file mode 100644 index 0000000000..1ef7d479a3 --- /dev/null +++ b/board/freescale/ls1046ardb/README @@ -0,0 +1,76 @@ +Overview +-------- +The LS1046A Reference Design Board (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The LS1046ARDB provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + LS1046ARDB board Overview + ----------------------- + - SERDES1 Connections, 4 lanes supporting: + - Lane0: XFI with x1 RJ45 connector + - Lane1: XFI Cage + - Lane2: SGMII.5 + - Lane3: SGMII.6 + - SERDES2 Connections, 4 lanes supporting: + - Lane0: PCIe1 with miniPCIe slot + - Lane1: PCIe2 with PCIe x2 slot + - Lane2: PCIe3 with PCIe x4 slot + - Lane3: SATA + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One 512 MB NAND flash with ECC support + - CPLD connection + - USB 3.0 + - one Type A port, one Micro-AB port + - SDHC: connects directly to a full SD/MMC slot + - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +QSPI flash map: +Start Address End Address Description Size +0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB +0x00_4010_0000 - 0x00_401F_FFFF U-Boot 1MB +0x00_4020_0000 - 0x00_402F_FFFF U-Boot Env 1MB +0x00_4030_0000 - 0x00_403F_FFFF FMan ucode 1MB +0x00_4040_0000 - 0x00_404F_FFFF UEFI 1MB +0x00_4050_0000 - 0x00_406F_FFFF PPA 2MB +0x00_4070_0000 - 0x00_408F_FFFF Secure boot header + + bootscript 2MB +0x00_4090_0000 - 0x00_40FF_FFFF Reserved 7MB +0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB + +Booting Options +--------------- +a) QSPI boot +b) SD boot +c) eMMC boot diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c new file mode 100644 index 0000000000..81a646e28c --- /dev/null +++ b/board/freescale/ls1046ardb/cpld.c @@ -0,0 +1,158 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Freescale LS1046ARDB board-specific CPLD controlling supports. + */ + +#include +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_QSPI; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + u8 reg7 = CPLD_READ(vbank); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; + CPLD_WRITE(vbank, reg7); + + CPLD_WRITE(system_rst, 1); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_QSPI; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(vbank, 0); + + CPLD_WRITE(system_rst, 1); +} + +void cpld_set_sd(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_SD; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); + printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); + printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); + printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); + printf("vbank = %x\n", CPLD_READ(vbank)); + printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); + printf("uart_sel = %x\n", CPLD_READ(uart_sel)); + printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); + printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel)); + printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel)); + printf("status_led = %x\n", CPLD_READ(status_led)); + printf("sd_emmc = %x\n", CPLD_READ(sd_emmc)); + printf("vdd_en = %x\n", CPLD_READ(vdd_en)); + printf("vdd_sel = %x\n", CPLD_READ(vdd_sel)); + putc('\n'); +} +#endif + +void cpld_rev_bit(unsigned char *value) +{ + u8 rev_val, val; + int i; + + val = *value; + rev_val = val & 1; + for (i = 1; i <= 7; i++) { + val >>= 1; + rev_val <<= 1; + rev_val |= val & 1; + } + + *value = rev_val; +} + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else if (strcmp(argv[2], "sd") == 0) + cpld_set_sd(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" + "cpld reset sd: reset to boot from SD card\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif +); diff --git a/board/freescale/ls1046ardb/cpld.h b/board/freescale/ls1046ardb/cpld.h new file mode 100644 index 0000000000..458da7e892 --- /dev/null +++ b/board/freescale/ls1046ardb/cpld.h @@ -0,0 +1,49 @@ +/* + * Copyright 2016 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CPLD_H__ +#define __CPLD_H__ + +/* + * CPLD register set of LS1046ARDB board-specific. + * CPLD Revision: V2.1 + */ +struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ + u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */ + u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */ + u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */ + u8 sysclk_sel; /* 0x8 - System clock POR Register */ + u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ + u8 sd1refclk_sel; /* 0xA - */ + u8 rgmii_1588_sel; /* 0xB - */ + u8 reg_1588_clk_sel; /* 0xC - */ + u8 status_led; /* 0xD - */ + u8 global_rst; /* 0xE - */ + u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */ + u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */ + u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */ +}; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); +void cpld_rev_bit(unsigned char *value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_SW_MUX_BANK_SEL 0x40 +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_QSPI 0x044 +#define CPLD_CFG_RCW_SRC_SD 0x040 +#endif diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c new file mode 100644 index 0000000000..a9b7dbdf90 --- /dev/null +++ b/board/freescale/ls1046ardb/ddr.c @@ -0,0 +1,140 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "ddr.h" +#ifdef CONFIG_FSL_DEEP_SLEEP +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64-bit data bus */ + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + + erratum_a008850_post(); + + return dram_size; +} + +void dram_init_banksize(void) +{ + /* + * gd->arch.secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h new file mode 100644 index 0000000000..9e440f67b4 --- /dev/null +++ b/board/freescale/ls1046ardb/ddr.h @@ -0,0 +1,44 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +void erratum_a008850_post(void); + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c new file mode 100644 index 0000000000..ac8bbec9a3 --- /dev/null +++ b/board/freescale/ls1046ardb/eth.c @@ -0,0 +1,77 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + /* Set the two on-board SGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); + + /* Set the on-board AQ PHY address */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + + switch (srds_s1) { + case 0x1133: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + fm_info_set_mdio(i, dev); + + /* XFI on lane A, MAC 9 */ + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(FM1_10GEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c new file mode 100644 index 0000000000..585c807818 --- /dev/null +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -0,0 +1,136 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; + u8 sd1refclk_sel; + + puts("Board: LS1046ARDB, boot from "); + + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x44) + printf("QSPI vBank %d\n", CPLD_READ(vbank)); + else if (cfg_rcw_src == 0x40) + puts("SD\n"); + else + puts("Invalid setting of SW5\n"); + + printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); + + puts("SERDES Reference Clocks:\n"); + sd1refclk_sel = CPLD_READ(sd1refclk_sel); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = initdram(0); + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); + + return 0; +} + +void config_board_mux(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + + /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ + out_be32(&scfg->rcwpmuxcr0, 0x3300); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + return 0; +} diff --git a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg new file mode 100644 index 0000000000..5478217524 --- /dev/null +++ b/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg @@ -0,0 +1,22 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg new file mode 100644 index 0000000000..6a5076e099 --- /dev/null +++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150010 0e000000 00000000 00000000 +11335559 40000012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003000 00000096 00000001 diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg new file mode 100644 index 0000000000..d5265b846f --- /dev/null +++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150010 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003101 00000096 00000001 -- cgit v1.2.3 From 126fe70d7746d7e60a6331391cab6713368b78dc Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Wed, 7 Sep 2016 17:56:14 +0800 Subject: armv8: ls1046aqds: Add LS1046AQDS board support LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- board/freescale/common/vid.c | 8 +- board/freescale/ls1046aqds/Kconfig | 15 + board/freescale/ls1046aqds/MAINTAINERS | 10 + board/freescale/ls1046aqds/Makefile | 9 + board/freescale/ls1046aqds/README | 70 ++++ board/freescale/ls1046aqds/ddr.c | 140 +++++++ board/freescale/ls1046aqds/ddr.h | 44 +++ board/freescale/ls1046aqds/eth.c | 415 +++++++++++++++++++++ board/freescale/ls1046aqds/ls1046aqds.c | 298 +++++++++++++++ board/freescale/ls1046aqds/ls1046aqds_pbi.cfg | 17 + board/freescale/ls1046aqds/ls1046aqds_qixis.h | 39 ++ board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg | 7 + .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg | 8 + .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg | 8 + 14 files changed, 1084 insertions(+), 4 deletions(-) create mode 100644 board/freescale/ls1046aqds/Kconfig create mode 100644 board/freescale/ls1046aqds/MAINTAINERS create mode 100644 board/freescale/ls1046aqds/Makefile create mode 100644 board/freescale/ls1046aqds/README create mode 100644 board/freescale/ls1046aqds/ddr.c create mode 100644 board/freescale/ls1046aqds/ddr.h create mode 100644 board/freescale/ls1046aqds/eth.c create mode 100644 board/freescale/ls1046aqds/ls1046aqds.c create mode 100644 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg create mode 100644 board/freescale/ls1046aqds/ls1046aqds_qixis.h create mode 100644 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg create mode 100644 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg create mode 100644 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg (limited to 'board') diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 2f29795137..1a503042f0 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -8,7 +8,7 @@ #include #include #include -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 #include #elif defined(CONFIG_FSL_LSCH3) #include @@ -247,7 +247,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd) * SoC before converting into an IR VID value */ vdd += board_vdd_drop_compensation(); -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 vid = DIV_ROUND_UP(vdd - 265, 5); #else vid = DIV_ROUND_UP(vdd - 245, 5); @@ -287,7 +287,7 @@ static int set_voltage(int i2caddress, int vdd) int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); -#if defined(CONFIG_LS1043A) || defined(CONFIG_FSL_LSCH3) +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = @@ -386,7 +386,7 @@ int adjust_vdd(ulong vdd_override) * | T | | | | | * ------------------------------------------------------ */ -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig new file mode 100644 index 0000000000..723f4ba90a --- /dev/null +++ b/board/freescale/ls1046aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1046AQDS + +config SYS_BOARD + default "ls1046aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046aqds" + +endif diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS new file mode 100644 index 0000000000..b4549ae138 --- /dev/null +++ b/board/freescale/ls1046aqds/MAINTAINERS @@ -0,0 +1,10 @@ +LS1046AQDS BOARD +M: Mingkai Hu +S: Maintained +F: board/freescale/ls1046aqds/ +F: include/configs/ls1046aqds.h +F: configs/ls1046aqds_defconfig +F: configs/ls1046aqds_nand_defconfig +F: configs/ls1046aqds_sdcard_ifc_defconfig +F: configs/ls1046aqds_sdcard_qspi_defconfig +F: configs/ls1046aqds_qspi_defconfig diff --git a/board/freescale/ls1046aqds/Makefile b/board/freescale/ls1046aqds/Makefile new file mode 100644 index 0000000000..df6e5461db --- /dev/null +++ b/board/freescale/ls1046aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ddr.o +obj-y += eth.o +obj-y += ls1046aqds.o diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README new file mode 100644 index 0000000000..b8fa32652b --- /dev/null +++ b/board/freescale/ls1046aqds/README @@ -0,0 +1,70 @@ +Overview +-------- +The LS1046A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The LS1046AQDS provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + LS1046AQDS board Overview + ----------------------- + - SERDES Connections, 8 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 + - XFI + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One in-socket 128 MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - PromJet Port + - FPGA connection + - USB 3.0 + - Three high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - The other two USB 3.0 ports configured as OTG with micro-AB connector + - SDHC port connects directly to an adapter card slot, featuring: + - Optional clock feedback paths, and optional high-speed voltage translation assistance + - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC + - eMMC memory devices + - DSPI: Onboard support for three SPI flash memory devices + - 4 I2C controllers + - One SATA onboard connectors + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +Booting Options +--------------- +a) Promjet Boot +b) NOR boot +c) NAND boot +d) SD boot +e) QSPI boot diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c new file mode 100644 index 0000000000..d8139653ad --- /dev/null +++ b/board/freescale/ls1046aqds/ddr.c @@ -0,0 +1,140 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#ifdef CONFIG_FSL_DEEP_SLEEP +#include +#endif +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64b data bus */ + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + return fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + erratum_a008850_post(); + + return dram_size; +} + +void dram_init_banksize(void) +{ + /* + * gd->arch.secure_ram tracks the location of secure memory. + * It was set as if the memory starts from 0. + * The address needs to add the offset of its bank. + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; +#endif + } +} diff --git a/board/freescale/ls1046aqds/ddr.h b/board/freescale/ls1046aqds/ddr.h new file mode 100644 index 0000000000..b5940321e0 --- /dev/null +++ b/board/freescale/ls1046aqds/ddr.h @@ -0,0 +1,44 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +void erratum_a008850_post(void); + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c new file mode 100644 index 0000000000..046db11261 --- /dev/null +++ b/board/freescale/ls1046aqds/eth.c @@ -0,0 +1,415 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/fman.h" +#include "ls1046aqds_qixis.h" + +#define EMI_NONE 0xFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT4 4 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "LS1046AQDS_MDIO_RGMII1", + "LS1046AQDS_MDIO_RGMII2", + "LS1046AQDS_MDIO_SLOT1", + "LS1046AQDS_MDIO_SLOT2", + "LS1046AQDS_MDIO_SLOT4", + "NULL", +}; + +/* Map SerDes 1 & 2 lanes to default slot. */ +static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; + +static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI1_SLOT4) + return NULL; + + name = ls1046aqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct ls1046aqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void ls1046aqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1046aqds_mdio *priv = bus->priv; + + ls1046aqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1046aqds_mdio *priv = bus->priv; + + ls1046aqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, + regnum, value); +} + +static int ls1046aqds_mdio_reset(struct mii_dev *bus) +{ + struct ls1046aqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1046aqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1046aqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1046aqds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1046aqds_mdio_read; + bus->write = ls1046aqds_mdio_write; + bus->reset = ls1046aqds_mdio_reset; + sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + switch (port) { + case FM1_DTSEC9: + fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1"); + break; + case FM1_DTSEC10: + fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1"); + break; + default: + break; + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { + /* 2.5G SGMII interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(1000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 2.5G SGMII on QDS */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "sgmii-2500"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); + break; + case FM1_DTSEC10: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "qsgmii"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && + (port == FM1_10GEC1 || port == FM1_10GEC2)) { + /* XFI interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + + for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + switch (mdio_mux[i]) { + case EMI1_SLOT1: + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT4: + fdt_status_okay_by_alias(fdt, "emi1_slot4"); + break; + default: + break; + } + break; + default: + break; + } + } +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1, srds_s2; + u8 brdcfg12; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + srds_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x3333: + /* SGMII on slot 1, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + case 0x1333: + case 0x2333: + /* SGMII on slot 1, MAC 10 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + case 0x1133: + case 0x2233: + /* SGMII on slot 1, MAC 5/6 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x1040: + case 0x2040: + /* QSGMII on lane B, MAC 6/5/10/1 */ + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC10, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x3363: + /* SGMII on slot 1, MAC 9/10 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + case 0x1163: + case 0x2263: + case 0x2223: + /* SGMII on slot 1, MAC 6 */ + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", + srds_s1); + break; + } + + if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) + /* SGMII on slot 4, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + if (i == FM1_DTSEC5) { + /* route lane 2 to slot1 so to have + * one sgmii riser card supports + * MAC5 and MAC6. + */ + brdcfg12 = QIXIS_READ(brdcfg[12]); + QIXIS_WRITE(brdcfg[12], + brdcfg12 | 0x80); + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else { + /* clear the bit 7 to route lane B on slot2. */ + brdcfg12 = QIXIS_READ(brdcfg[12]); + QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); + + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + lane_to_slot[lane] = 2; + } + + if (i == FM1_DTSEC2) + lane = 5; + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c new file mode 100644 index 0000000000..8c18538503 --- /dev/null +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -0,0 +1,298 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/vid.h" +#include "../common/qixis.h" +#include "ls1046aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_GPIO, +}; + +int checkboard(void) +{ + char buf[64]; +#ifndef CONFIG_SD_BOOT + u8 sw; +#endif + + puts("Board: LS1046AQDS, boot from "); + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0xF) + printf("QSPI\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + return 0; +} + +bool if_board_diff_clk(void) +{ + u8 diff_conf = QIXIS_READ(brdcfg[11]); + + return diff_conf & 0x40; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + if (if_board_diff_clk()) + return get_board_sys_clk(); + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + + return 66666666; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + gd->ram_size = initdram(0); + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +int board_early_init_f(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; +#endif + +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif + fsl_lsch2_early_init_f(); + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_DEEP_SLEEP +/* determine if it is a warm boot */ +bool is_warm_boot(void) +{ +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} +#endif + +int config_board_mux(int ctrl_type) +{ + u8 reg14; + + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_GPIO: + reg14 = (reg14 & (~0x6)) | 0x2; + break; + default: + puts("Unsupported mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + if (hwconfig("gpio")) + config_board_mux(MUX_TYPE_GPIO); + + return 0; +} +#endif + +int board_init(void) +{ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifdef CONFIG_SYS_FSL_SERDES + config_serdes_mux(); +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + u8 reg; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + /* Disable IFC if QSPI is enabled */ + if (reg == 0xF) + do_fixup_by_compat(blob, "fsl,ifc", + "status", "disabled", 8 + 1, 1); + + return 0; +} +#endif + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg b/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg new file mode 100644 index 0000000000..5a6b7b84a4 --- /dev/null +++ b/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg @@ -0,0 +1,17 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#flush PBI data +096100c0 000fffff diff --git a/board/freescale/ls1046aqds/ls1046aqds_qixis.h b/board/freescale/ls1046aqds/ls1046aqds_qixis.h new file mode 100644 index 0000000000..58ab132531 --- /dev/null +++ b/board/freescale/ls1046aqds/ls1046aqds_qixis.h @@ -0,0 +1,39 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1046AQDS_QIXIS_H__ +#define __LS1046AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1046AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg new file mode 100644 index 0000000000..b5fc08ce2a --- /dev/null +++ b/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0c150010 0e000000 00000000 00000000 +11335559 40005012 e0116000 c1000000 +00000000 00000000 00000000 00038800 +00000000 01001101 00000096 00000001 diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg new file mode 100644 index 0000000000..59d24d6790 --- /dev/null +++ b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable IFC; disable QSPI +0c150010 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00038800 +00000000 01001101 00000096 00000001 diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg new file mode 100644 index 0000000000..9401a6f0f4 --- /dev/null +++ b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable QSPI; disable IFC +0c150010 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00038800 +20124000 01001101 00000096 00000001 -- cgit v1.2.3 From 1fdcc8dfc7612acc765cd483051dcfaac399f4f1 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 26 Sep 2016 08:09:25 -0700 Subject: driver: ddr: fsl_mmdc: Pass board parameters through data structure Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun CC: Shengzhou Liu Reviewed-by: Tom Rini --- board/freescale/ls1012afrdm/ls1012afrdm.c | 18 +++++++++++++++++- board/freescale/ls1012aqds/ls1012aqds.c | 18 +++++++++++++++++- board/freescale/ls1012ardb/ls1012ardb.c | 18 +++++++++++++++++- 3 files changed, 51 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index d644e9423b..b03bdb82c6 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -26,7 +26,23 @@ int checkboard(void) int dram_init(void) { - mmdc_init(); + static const struct fsl_mmdc_info mparam = { + 0x04180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); gd->ram_size = CONFIG_SYS_SDRAM_SIZE; diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 188b6bc979..94440b3c80 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -54,7 +54,23 @@ int checkboard(void) int dram_init(void) { - mmdc_init(); + static const struct fsl_mmdc_info mparam = { + 0x05180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); gd->ram_size = CONFIG_SYS_SDRAM_SIZE; diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 50f91876ca..778434d684 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -58,7 +58,23 @@ int checkboard(void) int dram_init(void) { - mmdc_init(); + static const struct fsl_mmdc_info mparam = { + 0x05180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -- cgit v1.2.3