From c14f3c31112653f5c5a34b748e9defbd3bc5a8ef Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 22 Apr 2019 21:43:33 +0530 Subject: board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build AM654 SoC is IO coherent wrt A53 cores, therefore enable SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra --- board/ti/am65x/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index d4b36dbb42f..98172c28f5d 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM bool "TI K3 based AM654 EVM running on A53" select ARM64 select SOC_K3_AM6 + select SYS_DISABLE_DCACHE_OPS config TARGET_AM654_R5_EVM bool "TI K3 based AM654 EVM running on R5" -- cgit v1.2.3