From a678bfef83e7ca7c4ff3a599b23d6af176803ea1 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Thu, 25 Oct 2018 16:13:26 +0800 Subject: MLK-20044 imx8mm_evk: update DDRC RFSHCTL3 for DDR4 timing Update the RFSHCTL3 config for DDR4. Signed-off-by: Bai Ping --- board/freescale/imx8mm_evk/ddr4_timing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/imx8mm_evk/ddr4_timing.c b/board/freescale/imx8mm_evk/ddr4_timing.c index 8b622a9040a..acbb1b02bb4 100644 --- a/board/freescale/imx8mm_evk/ddr4_timing.c +++ b/board/freescale/imx8mm_evk/ddr4_timing.c @@ -16,7 +16,7 @@ struct dram_cfg_param ddr4_ddrc_cfg[] = { { DDRC_PWRTMG(0), 0x00221306 }, { DDRC_RFSHCTL0(0), 0x00c0a070 }, { DDRC_RFSHCTL1(0), 0x00010008 }, - { DDRC_RFSHCTL3(0), 0x00000010 }, + { DDRC_RFSHCTL3(0), 0x00000000 }, { DDRC_RFSHTMG(0), 0x004980f4 }, { DDRC_CRCPARCTL0(0), 0x00000000 }, { DDRC_CRCPARCTL1(0), 0x00001010 }, -- cgit v1.2.3