From a1d9321fecc7f01e3e37d11adbda402e95458045 Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren@nvidia.com>
Date: Wed, 14 Dec 2011 14:56:21 -0700
Subject: fdt: Tegra3: Add Cardhu device-tree file

BUG=chromium-os:23496
TEST=none

Modeled on tegra3-waluigi.dts

Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I3a31084fa747991484dda4a40e89deda97a1ff1f
Reviewed-on: https://gerrit.chromium.org/gerrit/12939
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 board/nvidia/cardhu/tegra3-cardhu.dts | 115 ++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)
 create mode 100644 board/nvidia/cardhu/tegra3-cardhu.dts

(limited to 'board')

diff --git a/board/nvidia/cardhu/tegra3-cardhu.dts b/board/nvidia/cardhu/tegra3-cardhu.dts
new file mode 100644
index 00000000000..921c87e3327
--- /dev/null
+++ b/board/nvidia/cardhu/tegra3-cardhu.dts
@@ -0,0 +1,115 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "tegra30.dtsi"
+
+/ {
+	model = "Google Cardhu";
+	compatible = "google,cardhu", "nvidia,tegra30";
+
+	config {
+		silent_console = <0>;
+		odmdata = <0x300d8011>;
+		hwid = "ARM CARDHU TEST 6666";
+		machine-arch-id = <3436>;
+	};
+
+	aliases {
+		console = "/serial@70006000";
+                usb0 = "/usb@0x7d008000";
+                usb1 = "/usb@0x7d000000";
+
+		sdmmc0 = "/sdhci@78000600";
+		sdmmc1 = "/sdhci@78000000";
+
+		i2c0 = "/i2c@0x7000d000";
+		i2c1 = "/i2c@0x7000c000";
+		i2c2 = "/i2c@0x7000c400";
+		i2c3 = "/i2c@0x7000c500";
+		i2c4 = "/i2c@0x7000c700";
+	};
+
+	chosen {
+		bootargs = "";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0xc0000000>;
+	};
+
+	serial@70006000 {
+		status = "ok";
+		/*
+		 * TBD - use CONFIG_SYS_PLLP_BASE_IS_408MHZ somehow here.
+		 * Currently I put this back to 216MHz in fdt_decode.c
+		 */
+		clock-frequency = <408000000>;
+	};
+
+	/* External SD card - SDMMC1 */
+	sdhci@78000000 {
+		status = "ok";
+		width = <4>;	/* width of SDIO port */
+		removable = <1>;
+		/* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+		cd-gpio = <&gpio 69 0>; /* card detect, GMI_IORDY => I.05 */
+		wp-gpio = <&gpio 155 0>; /* write protect, VI_D11 => T.03 */
+		power-gpio = <&gpio 31 3>; /* power enable, VI_HSYNC => D.07 */
+	};
+
+	/* Internal eMMC - SDMMC4 */
+	emmc: sdhci@78000600 {
+		status = "ok";
+		width = <4>;	/* width of SDIO port */
+		removable = <0>;
+	};
+
+	lcd {
+		compatible = "nvidia,tegra2-lcd";
+		width = <1366>;
+		height = <768>;
+		bits_per_pixel = <16>;
+		pwfm = <&pwfm0>;
+		display = <&display1>;
+		frame-buffer = <0x1C022000>;
+
+		pixel_clock = <68000000>;
+
+		/* Timing: ref_to_sync, sync_width. back_porch, front_porch */
+		horiz_timing = <0 30 52 64>;
+		vert_timing = <12 5 20 25>;
+
+		/* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+		backlight-vdd = <&gpio 56 3>;		/* PH0, LCD1_BL_PWM */
+		backlight-enable = <&gpio 58 3>;	/* PH2, LCD1_BL_EN */
+		lvds-shutdown = <&gpio 90 3>;		/* PL2, LVDS1_SHTDN */
+		panel-vdd = <&gpio 92 3>;		/* PL4, EN_VDD_PNL1 */
+
+		/*
+		 * Panel required timings
+		 * Timing 1: delay between panel_vdd-rise and data-rise
+		 * Timing 2: delay between data-rise and backlight_vdd-rise
+		 * Timing 3: delay between backlight_vdd and pwm-rise
+		 */
+
+		panel-timings = <0 0 0 0>;
+	};
+
+	usb@0x7d000000 {
+		status = "ok";
+		host-mode = <1>;
+		vbus-pullup-gpio = <&gpio 233 3>;	/* PDD1, EN_3V3_PU */
+	};
+
+	usbphy: usbphy@0 {
+		compatible = "smsc,usb3315";
+		status = "ok";
+	};
+
+	usb@0x7d008000 {
+		status = "ok";
+		utmi = <&usbphy>;
+		host-mode = <0>;
+	};
+};
-- 
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